pcie_ed

2025.04.16.14:28:29 Datasheet
Overview

All Components
   BAM_INTERPRETER intel_pcie_bam_interpreter 1.1
   emif_s10_ddr4a altera_emif_s10 19.2.8
   emif_s10_ddr4b altera_emif_s10 19.2.8
   mem intel_onchip_memory 1.4.9
   mm_bridge_bar4 altera_avalon_mm_bridge 20.1.0
   mm_bridge_bar4_mem altera_avalon_mm_bridge 20.1.0
   mm_bridge_bar4_periphery altera_avalon_mm_bridge 20.1.0
   mm_bridge_ddr4a altera_avalon_mm_bridge 20.1.0
   mm_bridge_ddr4b altera_avalon_mm_bridge 20.1.0
   mm_bridge_onchip_mem altera_avalon_mm_bridge 20.1.0
   mm_bridge_pcie_rd altera_avalon_mm_bridge 20.1.0
   mm_bridge_pcie_wr altera_avalon_mm_bridge 20.1.0
   mm_ccb_ddr4a mm_ccb 19.2.1
   mm_ccb_ddr4b mm_ccb 19.2.1
   pcie_mcdma intel_pcie_mcdma 24.2.0
   pio_button altera_avalon_pio 19.2.3
   pio_led altera_avalon_pio 19.2.3
Memory Map
BAM_INTERPRETER mm_bridge_bar4 mm_bridge_bar4_mem mm_bridge_bar4_periphery mm_bridge_ddr4a mm_bridge_ddr4b mm_bridge_onchip_mem mm_bridge_pcie_rd mm_bridge_pcie_wr mm_ccb_ddr4a mm_ccb_ddr4b pcie_mcdma
 AVMM_BAM_Master  m0  m0  m0  m0  m0  m0  m0  m0  m0  m0  d2hdm_master  h2ddm_master  bam_master
  BAM_INTERPRETER
AVMM_BAM_Slave  0x0000_0000 - 0x3fff_ffff
  emif_s10_ddr4a
ctrl_amm_0  0x0000_0000 - 0xffff_ffff 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0000 - 0xffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff
  emif_s10_ddr4b
ctrl_amm_0  0x0000_0000 - 0xffff_ffff 0x0000_0001_0000_0000 - 0x0000_0001_ffff_ffff 0x0000_0001_0000_0000 - 0x0000_0001_ffff_ffff 0x0000_0000 - 0xffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff
  mem
s1  0x0000_0000_0010_0000 - 0x0000_0000_0017_ffff
s2  0x0410_0000 - 0x0417_ffff 0x0010_0000 - 0x0017_ffff 0x0010_0000 - 0x0017_ffff 0x0000_0000 - 0x0007_ffff 0x0000_0000_0010_0000 - 0x0000_0000_0017_ffff
  mm_bridge_bar4
s0  0x0400_0000 - 0x04ff_ffff
  mm_bridge_bar4_mem
s0  0x0400_0000 - 0x041f_ffff 0x0000_0000 - 0x001f_ffff
  mm_bridge_bar4_periphery
s0  0x0480_0000 - 0x0480_007f 0x0080_0000 - 0x0080_007f
  mm_bridge_ddr4a
s0  0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0000 - 0xffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff
  mm_bridge_ddr4b
s0  0x0000_0001_0000_0000 - 0x0000_0001_ffff_ffff 0x0000_0001_0000_0000 - 0x0000_0001_ffff_ffff 0x0000_0000 - 0xffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff
  mm_bridge_onchip_mem
s0  0x0410_0000 - 0x0417_ffff 0x0010_0000 - 0x0017_ffff 0x0010_0000 - 0x0017_ffff 0x0000_0000_0010_0000 - 0x0000_0000_0017_ffff
  mm_bridge_pcie_rd
s0  0x0000_0010_0000_0000 - 0x0000_0011_ffff_ffff
  mm_bridge_pcie_wr
s0  0x0000_0010_0000_0000 - 0x0000_0011_ffff_ffff
  mm_ccb_ddr4a
s0  0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff
  mm_ccb_ddr4b
s0  0x0000_0001_0000_0000 - 0x0000_0001_ffff_ffff 0x0000_0001_0000_0000 - 0x0000_0001_ffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff
  pcie_mcdma
usr_hip_reconfig 
  pio_button
s1  0x0480_0040 - 0x0480_004f 0x0080_0040 - 0x0080_004f 0x0040 - 0x004f
  pio_led
s1  0x0480_0000 - 0x0480_000f 0x0080_0000 - 0x0080_000f 0x0000 - 0x000f

BAM_INTERPRETER

intel_pcie_bam_interpreter v1.1
pcie_mcdma bam_master   BAM_INTERPRETER
  AVMM_BAM_Slave
coreclkout_hip  
  clock
app_nreset_status  
  reset
AVMM_BAM_Master   mm_bridge_bar4
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_s10_ddr4a

altera_emif_s10 v19.2.8
mm_bridge_ddr4a m0   emif_s10_ddr4a
  ctrl_amm_0
emif_usr_clk   mm_bridge_ddr4a
  clk
emif_usr_reset_n  
  reset
emif_usr_clk   mm_ccb_ddr4a
  m0_clk
emif_usr_reset_n  
  m0_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_s10_ddr4b

altera_emif_s10 v19.2.8
mm_bridge_ddr4b m0   emif_s10_ddr4b
  ctrl_amm_0
emif_usr_clk   mm_bridge_ddr4b
  clk
emif_usr_reset_n  
  reset
emif_usr_clk   mm_ccb_ddr4b
  m0_clk
emif_usr_reset_n  
  m0_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mem

intel_onchip_memory v1.4.9
pcie_mcdma d2hdm_master   mem
  s1
coreclkout_hip  
  clk1
app_nreset_status  
  reset1
mm_bridge_onchip_mem m0  
  s2


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 1
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE UNUSED
INIT_MEM_CONTENT 0
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

mm_bridge_bar4

altera_avalon_mm_bridge v20.1.0
BAM_INTERPRETER AVMM_BAM_Master   mm_bridge_bar4
  s0
pcie_mcdma coreclkout_hip  
  clk
app_nreset_status  
  reset
m0   mm_bridge_bar4_mem
  s0
m0   mm_bridge_bar4_periphery
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_bar4_mem

altera_avalon_mm_bridge v20.1.0
mm_bridge_bar4 m0   mm_bridge_bar4_mem
  s0
pcie_mcdma coreclkout_hip  
  clk
app_nreset_status  
  reset
m0   mm_bridge_onchip_mem
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_bar4_periphery

altera_avalon_mm_bridge v20.1.0
mm_bridge_bar4 m0   mm_bridge_bar4_periphery
  s0
pcie_mcdma coreclkout_hip  
  clk
app_nreset_status  
  reset
m0   pio_led
  s1
m0   pio_button
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_ddr4a

altera_avalon_mm_bridge v20.1.0
mm_ccb_ddr4a m0   mm_bridge_ddr4a
  s0
emif_s10_ddr4a emif_usr_clk  
  clk
emif_usr_reset_n  
  reset
m0   emif_s10_ddr4a
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_ddr4b

altera_avalon_mm_bridge v20.1.0
mm_ccb_ddr4b m0   mm_bridge_ddr4b
  s0
emif_s10_ddr4b emif_usr_clk  
  clk
emif_usr_reset_n  
  reset
m0   emif_s10_ddr4b
  ctrl_amm_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_onchip_mem

altera_avalon_mm_bridge v20.1.0
pcie_mcdma h2ddm_master   mm_bridge_onchip_mem
  s0
coreclkout_hip  
  clk
app_nreset_status  
  reset
mm_bridge_bar4_mem m0  
  s0
m0   mem
  s2


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_pcie_rd

altera_avalon_mm_bridge v20.1.0
pcie_mcdma d2hdm_master   mm_bridge_pcie_rd
  s0
coreclkout_hip  
  clk
app_nreset_status  
  reset
m0   mm_ccb_ddr4a
  s0
m0   mm_ccb_ddr4b
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_pcie_wr

altera_avalon_mm_bridge v20.1.0
pcie_mcdma h2ddm_master   mm_bridge_pcie_wr
  s0
coreclkout_hip  
  clk
app_nreset_status  
  reset
m0   mm_ccb_ddr4a
  s0
m0   mm_ccb_ddr4b
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_ccb_ddr4a

mm_ccb v19.2.1
mm_bridge_pcie_wr m0   mm_ccb_ddr4a
  s0
mm_bridge_pcie_rd m0  
  s0
pcie_mcdma coreclkout_hip  
  s0_clk
app_nreset_status  
  s0_reset
emif_s10_ddr4a emif_usr_clk  
  m0_clk
emif_usr_reset_n  
  m0_reset
m0   mm_bridge_ddr4a
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_ccb_ddr4b

mm_ccb v19.2.1
mm_bridge_pcie_rd m0   mm_ccb_ddr4b
  s0
mm_bridge_pcie_wr m0  
  s0
pcie_mcdma coreclkout_hip  
  s0_clk
app_nreset_status  
  s0_reset
emif_s10_ddr4b emif_usr_clk  
  m0_clk
emif_usr_reset_n  
  m0_reset
m0   mm_bridge_ddr4b
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_mcdma

intel_pcie_mcdma v24.2.0
resetIP ninit_done   pcie_mcdma
  ninit_done
bam_master   BAM_INTERPRETER
  AVMM_BAM_Slave
coreclkout_hip  
  clock
app_nreset_status  
  reset
d2hdm_master   mm_bridge_pcie_rd
  s0
coreclkout_hip  
  clk
app_nreset_status  
  reset
d2hdm_master   mem
  s1
coreclkout_hip  
  clk1
app_nreset_status  
  reset1
h2ddm_master   mm_bridge_onchip_mem
  s0
coreclkout_hip  
  clk
app_nreset_status  
  reset
h2ddm_master   mm_bridge_pcie_wr
  s0
coreclkout_hip  
  clk
app_nreset_status  
  reset
coreclkout_hip   mm_bridge_bar4
  clk
app_nreset_status  
  reset
coreclkout_hip   mm_bridge_bar4_mem
  clk
app_nreset_status  
  reset
coreclkout_hip   mm_bridge_bar4_periphery
  clk
app_nreset_status  
  reset
coreclkout_hip   pio_led
  clk
app_nreset_status  
  reset
coreclkout_hip   pio_button
  clk
app_nreset_status  
  reset
coreclkout_hip   mm_ccb_ddr4a
  s0_clk
app_nreset_status  
  s0_reset
coreclkout_hip   mm_ccb_ddr4b
  s0_clk
app_nreset_status  
  s0_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

pio_button

altera_avalon_pio v19.2.3
mm_bridge_bar4_periphery m0   pio_button
  s1
pcie_mcdma coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 125000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v19.2.3
mm_bridge_bar4_periphery m0   pio_led
  s1
pcie_mcdma coreclkout_hip  
  clk
app_nreset_status  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 125000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

resetIP

altera_s10_user_rst_clkgate v19.4.7


Parameters

generateLegacySim false
  

Software Assignments

(none)
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