| wrala_hwtcl |
Gen3x16, Interface - 512 bit, 250 MHz |
| select_design_example_hwtcl |
AVMM DMA |
| virtual_rp_ep_mode_hwtcl |
Native Endpoint |
| enable_multi_func_hwtcl |
0 |
| user_total_pf_count_hwtcl |
1 |
| enable_sriov_hwtcl |
0 |
| virtual_pf0_sriov_enable_hwtcl |
0 |
| virtual_pf1_sriov_enable_hwtcl |
0 |
| virtual_pf2_sriov_enable_hwtcl |
0 |
| virtual_pf3_sriov_enable_hwtcl |
0 |
| pf0_bar2_type_user_hwtcl |
Disabled |
| pf0_bar3_type_user_hwtcl |
Disabled |
| pf0_bar4_type_user_hwtcl |
64-bit prefetchable memory |
| pf0_bar4_address_width_user_hwtcl |
24 |
| pf0_bar5_type_user_hwtcl |
Disabled |
| pf0_expansion_base_address_register_hwtcl |
0 |
| enable_advanced_interrupt_hwtcl |
0 |
| pf0_num_dma_chan_pf_hwtcl |
4 |
| pf1_num_dma_chan_pf_hwtcl |
0 |
| pf2_num_dma_chan_pf_hwtcl |
0 |
| pf3_num_dma_chan_pf_hwtcl |
0 |
| pf0_num_dma_chan_per_vf_hwtcl |
0 |
| pf1_num_dma_chan_per_vf_hwtcl |
0 |
| pf2_num_dma_chan_per_vf_hwtcl |
0 |
| pf3_num_dma_chan_per_vf_hwtcl |
0 |
| enable_hip_pipe_interface |
1 |
| virtual_maxpayload_size_hwtcl |
512 |
| pf0_pcie_cap_port_num_hwtcl |
1 |
| pf1_pcie_cap_port_num_hwtcl |
0 |
| pf2_pcie_cap_port_num_hwtcl |
0 |
| pf3_pcie_cap_port_num_hwtcl |
0 |
| pf0_pcie_cap_slot_clk_config_hwtcl |
1 |
| virtual_pf0_msix_enable_hwtcl |
1 |
| pf0_pci_msix_table_size_hwtcl |
15 |
| pf0_pci_msix_table_offset_hwtcl |
131072 |
| pf0_pci_msix_bir_hwtcl |
0 |
| pf0_pci_msix_pba_offset_hwtcl |
196608 |
| pf0_pci_msix_pba_hwtcl |
0 |
| virtual_pf1_msix_enable_hwtcl |
0 |
| pf1_pci_msix_table_size_hwtcl |
0 |
| pf1_pci_msix_table_offset_hwtcl |
0 |
| pf1_pci_msix_bir_hwtcl |
0 |
| pf1_pci_msix_pba_offset_hwtcl |
0 |
| pf1_pci_msix_pba_hwtcl |
0 |
| virtual_pf2_msix_enable_hwtcl |
0 |
| pf2_pci_msix_table_size_hwtcl |
0 |
| pf2_pci_msix_table_offset_hwtcl |
0 |
| pf2_pci_msix_bir_hwtcl |
0 |
| pf2_pci_msix_pba_offset_hwtcl |
0 |
| pf2_pci_msix_pba_hwtcl |
0 |
| virtual_pf3_msix_enable_hwtcl |
0 |
| pf3_pci_msix_table_size_hwtcl |
0 |
| pf3_pci_msix_table_offset_hwtcl |
0 |
| pf3_pci_msix_bir_hwtcl |
0 |
| pf3_pci_msix_pba_offset_hwtcl |
0 |
| pf3_pci_msix_pba_hwtcl |
0 |
| pf0_pcie_slot_imp_hwtcl |
0 |
| pf0_pcie_cap_slot_power_limit_value_hwtcl |
0 |
| pf0_pcie_cap_slot_power_limit_scale_hwtcl |
0 |
| pf0_pcie_cap_phy_slot_num_hwtcl |
0 |
| pf0_pcie_cap_ep_l0s_accpt_latency_hwtcl |
0 |
| pf0_pcie_cap_ep_l1_accpt_latency_hwtcl |
0 |
| cvp_user_id_hwtcl |
0 |
| xcvr_reconfig_hwtcl |
0 |
| xcvr_adme_hwtcl |
0 |
| pcie_link_inspector_hwtcl |
0 |
| pf0_pcie_cap_sel_deemphasis_hwtcl |
6dB |
| anlg_voltage |
1_0V |
| pf0_pci_type0_vendor_id_hwtcl |
4466 |
| pf0_pci_type0_device_id_hwtcl |
2500 |
| pf0_revision_id_hwtcl |
1 |
| pf0_class_code_hwtcl |
16711680 |
| pf0_subsys_vendor_id_hwtcl |
0 |
| pf0_subsys_dev_id_hwtcl |
0 |
| pf1_pci_type0_vendor_id_hwtcl |
4466 |
| pf1_pci_type0_device_id_hwtcl |
0 |
| pf1_revision_id_hwtcl |
1 |
| pf1_class_code_hwtcl |
16711680 |
| pf1_subsys_vendor_id_hwtcl |
0 |
| pf1_subsys_dev_id_hwtcl |
0 |
| pf2_pci_type0_vendor_id_hwtcl |
4466 |
| pf2_pci_type0_device_id_hwtcl |
0 |
| pf2_revision_id_hwtcl |
1 |
| pf2_class_code_hwtcl |
16711680 |
| pf2_subsys_vendor_id_hwtcl |
0 |
| pf2_subsys_dev_id_hwtcl |
0 |
| pf3_pci_type0_vendor_id_hwtcl |
4466 |
| pf3_pci_type0_device_id_hwtcl |
0 |
| pf3_revision_id_hwtcl |
1 |
| pf3_class_code_hwtcl |
16711680 |
| pf3_subsys_vendor_id_hwtcl |
0 |
| pf3_subsys_dev_id_hwtcl |
0 |
| mode_hwtcl |
BAM_MCDMA |
| uport_type_hwtcl |
AVMM |
| num_avmm_uport_hwtcl |
1 |
| chosen_devkit_hwtcl |
NONE |
| enable_32bit_address_hwtcl |
0 |
| enable_user_msix_hwtcl |
0 |
| enable_user_flr_hwtcl |
0 |
| d2h_num_active_channel_hwtcl |
8 |
| d2h_max_num_desc_fetch_hwtcl |
16 |
| en_metadata_8_hwtcl |
0 |
| enable_cs_hwtcl |
0 |
| enable_byte_aligned_txfr_hwtcl |
0 |
| enable_user_hip_reconfig_hwtcl |
0 |
| enable_example_design_sim_hwtcl |
0 |
| enable_example_design_synth_hwtcl |
1 |
| select_design_example_rtl_lang_hwtcl |
Verilog |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |