golden top Board Configuration

golden top Board Configuration

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Copyright © 2003-2025 Terasic Inc. All Rights Reserved.

Pin Assignments:

CLOCK
Name Location Direction IO Standard
CLK_100_B3A AV8 input 1.8 V
CLK_100_B3L B2 input 1.8 V
CLK_25_B3L B5 input 1.8 V

Buttons
Name Location Direction IO Standard
BUTTON[0] V31 input 3.0-V LVTTL
BUTTON[1] V30 input 3.0-V LVTTL

Swtiches
Name Location Direction IO Standard
SW[0] AT21 input 1.2 V
SW[1] AM22 input 1.2 V

LED
Name Location Direction IO Standard
LED[0] AP21 output 1.2 V
LED[1] AT20 output 1.2 V

Reset
Name Location Direction IO Standard
FPGA_RST B7 input 1.8 V
HPS_RST E7 input 1.8 V

DDR4A
Name Location Direction IO Standard
DDR4A_REFCLK_p D27 input LVDS
DDR4A_A[0] M28 output SSTL-12
DDR4A_A[1] N28 output SSTL-12
DDR4A_A[2] R26 output SSTL-12
DDR4A_A[3] P26 output SSTL-12
DDR4A_A[4] P28 output SSTL-12
DDR4A_A[5] R27 output SSTL-12
DDR4A_A[6] K26 output SSTL-12
DDR4A_A[7] K27 output SSTL-12
DDR4A_A[8] N26 output SSTL-12
DDR4A_A[9] N27 output SSTL-12
DDR4A_A[10] L27 output SSTL-12
DDR4A_A[11] M27 output SSTL-12
DDR4A_A[12] J29 output SSTL-12
DDR4A_A[13] J28 output SSTL-12
DDR4A_A[14] K28 output SSTL-12
DDR4A_A[15] H31 output SSTL-12
DDR4A_A[16] H30 output SSTL-12
DDR4A_BA[0] H27 output SSTL-12
DDR4A_BA[1] G27 output SSTL-12
DDR4A_BG[0] F27 output SSTL-12
DDR4A_CK K31 output DIFFERENTIAL 1.2-V SSTL
DDR4A_CK_n L30 output DIFFERENTIAL 1.2-V SSTL
DDR4A_CKE M30 output SSTL-12
DDR4A_DQS[0] C23 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[1] N25 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[2] T23 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[3] J23 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[4] D8 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[5] E14 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[6] R17 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS[7] N17 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[0] C22 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[1] P25 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[2] R24 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[3] H23 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[4] C8 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[5] F14 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[6] P18 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQS_n[7] M17 inout DIFFERENTIAL 1.2-V POD
DDR4A_DQ[0] F24 inout 1.2-V POD
DDR4A_DQ[1] B22 inout 1.2-V POD
DDR4A_DQ[2] E24 inout 1.2-V POD
DDR4A_DQ[3] D23 inout 1.2-V POD
DDR4A_DQ[4] D24 inout 1.2-V POD
DDR4A_DQ[5] A22 inout 1.2-V POD
DDR4A_DQ[6] E23 inout 1.2-V POD
DDR4A_DQ[7] A21 inout 1.2-V POD
DDR4A_DQ[8] J25 inout 1.2-V POD
DDR4A_DQ[9] G25 inout 1.2-V POD
DDR4A_DQ[10] L25 inout 1.2-V POD
DDR4A_DQ[11] J24 inout 1.2-V POD
DDR4A_DQ[12] L24 inout 1.2-V POD
DDR4A_DQ[13] H26 inout 1.2-V POD
DDR4A_DQ[14] M25 inout 1.2-V POD
DDR4A_DQ[15] K24 inout 1.2-V POD
DDR4A_DQ[16] K22 inout 1.2-V POD
DDR4A_DQ[17] L22 inout 1.2-V POD
DDR4A_DQ[18] K23 inout 1.2-V POD
DDR4A_DQ[19] M22 inout 1.2-V POD
DDR4A_DQ[20] M23 inout 1.2-V POD
DDR4A_DQ[21] N22 inout 1.2-V POD
DDR4A_DQ[22] P23 inout 1.2-V POD
DDR4A_DQ[23] N23 inout 1.2-V POD
DDR4A_DQ[24] F21 inout 1.2-V POD
DDR4A_DQ[25] F22 inout 1.2-V POD
DDR4A_DQ[26] E21 inout 1.2-V POD
DDR4A_DQ[27] D21 inout 1.2-V POD
DDR4A_DQ[28] H21 inout 1.2-V POD
DDR4A_DQ[29] G22 inout 1.2-V POD
DDR4A_DQ[30] E22 inout 1.2-V POD
DDR4A_DQ[31] J21 inout 1.2-V POD
DDR4A_DQ[32] D11 inout 1.2-V POD
DDR4A_DQ[33] E11 inout 1.2-V POD
DDR4A_DQ[34] D10 inout 1.2-V POD
DDR4A_DQ[35] F12 inout 1.2-V POD
DDR4A_DQ[36] F11 inout 1.2-V POD
DDR4A_DQ[37] G12 inout 1.2-V POD
DDR4A_DQ[38] C10 inout 1.2-V POD
DDR4A_DQ[39] C11 inout 1.2-V POD
DDR4A_DQ[40] G14 inout 1.2-V POD
DDR4A_DQ[41] D15 inout 1.2-V POD
DDR4A_DQ[42] E13 inout 1.2-V POD
DDR4A_DQ[43] D14 inout 1.2-V POD
DDR4A_DQ[44] G13 inout 1.2-V POD
DDR4A_DQ[45] G15 inout 1.2-V POD
DDR4A_DQ[46] J15 inout 1.2-V POD
DDR4A_DQ[47] H15 inout 1.2-V POD
DDR4A_DQ[48] J16 inout 1.2-V POD
DDR4A_DQ[49] N16 inout 1.2-V POD
DDR4A_DQ[50] K16 inout 1.2-V POD
DDR4A_DQ[51] N15 inout 1.2-V POD
DDR4A_DQ[52] L16 inout 1.2-V POD
DDR4A_DQ[53] P16 inout 1.2-V POD
DDR4A_DQ[54] M15 inout 1.2-V POD
DDR4A_DQ[55] P15 inout 1.2-V POD
DDR4A_DQ[56] M18 inout 1.2-V POD
DDR4A_DQ[57] E16 inout 1.2-V POD
DDR4A_DQ[58] F17 inout 1.2-V POD
DDR4A_DQ[59] G17 inout 1.2-V POD
DDR4A_DQ[60] N18 inout 1.2-V POD
DDR4A_DQ[61] H17 inout 1.2-V POD
DDR4A_DQ[62] L17 inout 1.2-V POD
DDR4A_DQ[63] K17 inout 1.2-V POD
DDR4A_DBI_n[0] G23 inout 1.2-V POD
DDR4A_DBI_n[1] G24 inout 1.2-V POD
DDR4A_DBI_n[2] P24 inout 1.2-V POD
DDR4A_DBI_n[3] H22 inout 1.2-V POD
DDR4A_DBI_n[4] E12 inout 1.2-V POD
DDR4A_DBI_n[5] F15 inout 1.2-V POD
DDR4A_DBI_n[6] L15 inout 1.2-V POD
DDR4A_DBI_n[7] H16 inout 1.2-V POD
DDR4A_CS_n M29 output SSTL-12
DDR4A_RESET_n P31 output 1.2 V
DDR4A_ODT K30 output SSTL-12
DDR4A_PAR P29 output SSTL-12
DDR4A_ALERT_n B23 input 1.2 V
DDR4A_ACT_n L29 output SSTL-12
DDR4A_RZQ J30 input 1.2 V

DDR4B
Name Location Direction IO Standard
DDR4B_REFCLK_p AY19 input LVDS
DDR4B_A[0] AM25 output SSTL-12
DDR4B_A[1] AN25 output SSTL-12
DDR4B_A[2] AP24 output SSTL-12
DDR4B_A[3] AP25 output SSTL-12
DDR4B_A[4] AL24 output SSTL-12
DDR4B_A[5] AM24 output SSTL-12
DDR4B_A[6] AL26 output SSTL-12
DDR4B_A[7] AL25 output SSTL-12
DDR4B_A[8] AP23 output SSTL-12
DDR4B_A[9] AN23 output SSTL-12
DDR4B_A[10] AR23 output SSTL-12
DDR4B_A[11] AR24 output SSTL-12
DDR4B_A[12] AY21 output SSTL-12
DDR4B_A[13] BB19 output SSTL-12
DDR4B_A[14] BA19 output SSTL-12
DDR4B_A[15] AW21 output SSTL-12
DDR4B_A[16] AV21 output SSTL-12
DDR4B_BA[0] BA20 output SSTL-12
DDR4B_BA[1] AW20 output SSTL-12
DDR4B_BG[0] AV20 output SSTL-12
DDR4B_CK AU22 output DIFFERENTIAL 1.2-V SSTL
DDR4B_CK_n AV22 output DIFFERENTIAL 1.2-V SSTL
DDR4B_CKE AV23 output SSTL-12
DDR4B_DQS[0] AT27 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[1] BB25 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[2] AP29 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[3] AK28 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[4] BB18 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[5] AM18 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[6] AK22 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS[7] AH18 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[0] AU27 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[1] BA25 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[2] AR30 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[3] AK27 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[4] BB17 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[5] AN18 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[6] AK21 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQS_n[7] AJ18 inout DIFFERENTIAL 1.2-V POD
DDR4B_DQ[0] AV25 inout 1.2-V POD
DDR4B_DQ[1] AW24 inout 1.2-V POD
DDR4B_DQ[2] AW25 inout 1.2-V POD
DDR4B_DQ[3] AY24 inout 1.2-V POD
DDR4B_DQ[4] AT26 inout 1.2-V POD
DDR4B_DQ[5] AT24 inout 1.2-V POD
DDR4B_DQ[6] AR27 inout 1.2-V POD
DDR4B_DQ[7] AU25 inout 1.2-V POD
DDR4B_DQ[8] BA26 inout 1.2-V POD
DDR4B_DQ[9] AY26 inout 1.2-V POD
DDR4B_DQ[10] AY27 inout 1.2-V POD
DDR4B_DQ[11] BA24 inout 1.2-V POD
DDR4B_DQ[12] BB27 inout 1.2-V POD
DDR4B_DQ[13] AW26 inout 1.2-V POD
DDR4B_DQ[14] AV27 inout 1.2-V POD
DDR4B_DQ[15] BA27 inout 1.2-V POD
DDR4B_DQ[16] AP28 inout 1.2-V POD
DDR4B_DQ[17] AT29 inout 1.2-V POD
DDR4B_DQ[18] AP30 inout 1.2-V POD
DDR4B_DQ[19] AM30 inout 1.2-V POD
DDR4B_DQ[20] AR28 inout 1.2-V POD
DDR4B_DQ[21] AT30 inout 1.2-V POD
DDR4B_DQ[22] AN30 inout 1.2-V POD
DDR4B_DQ[23] AL30 inout 1.2-V POD
DDR4B_DQ[24] AM28 inout 1.2-V POD
DDR4B_DQ[25] AP26 inout 1.2-V POD
DDR4B_DQ[26] AK29 inout 1.2-V POD
DDR4B_DQ[27] AN27 inout 1.2-V POD
DDR4B_DQ[28] AL29 inout 1.2-V POD
DDR4B_DQ[29] AM27 inout 1.2-V POD
DDR4B_DQ[30] AK30 inout 1.2-V POD
DDR4B_DQ[31] AN28 inout 1.2-V POD
DDR4B_DQ[32] AV18 inout 1.2-V POD
DDR4B_DQ[33] BA17 inout 1.2-V POD
DDR4B_DQ[34] AW16 inout 1.2-V POD
DDR4B_DQ[35] AY16 inout 1.2-V POD
DDR4B_DQ[36] AV16 inout 1.2-V POD
DDR4B_DQ[37] AW18 inout 1.2-V POD
DDR4B_DQ[38] AU18 inout 1.2-V POD
DDR4B_DQ[39] AV17 inout 1.2-V POD
DDR4B_DQ[40] AR17 inout 1.2-V POD
DDR4B_DQ[41] AT19 inout 1.2-V POD
DDR4B_DQ[42] AR19 inout 1.2-V POD
DDR4B_DQ[43] AT17 inout 1.2-V POD
DDR4B_DQ[44] AP19 inout 1.2-V POD
DDR4B_DQ[45] AR18 inout 1.2-V POD
DDR4B_DQ[46] AR16 inout 1.2-V POD
DDR4B_DQ[47] AT16 inout 1.2-V POD
DDR4B_DQ[48] AK23 inout 1.2-V POD
DDR4B_DQ[49] AJ23 inout 1.2-V POD
DDR4B_DQ[50] AL22 inout 1.2-V POD
DDR4B_DQ[51] AL20 inout 1.2-V POD
DDR4B_DQ[52] AJ24 inout 1.2-V POD
DDR4B_DQ[53] AL21 inout 1.2-V POD
DDR4B_DQ[54] AJ25 inout 1.2-V POD
DDR4B_DQ[55] AK24 inout 1.2-V POD
DDR4B_DQ[56] AK19 inout 1.2-V POD
DDR4B_DQ[57] AK17 inout 1.2-V POD
DDR4B_DQ[58] AL19 inout 1.2-V POD
DDR4B_DQ[59] AK18 inout 1.2-V POD
DDR4B_DQ[60] AM20 inout 1.2-V POD
DDR4B_DQ[61] AJ19 inout 1.2-V POD
DDR4B_DQ[62] AM19 inout 1.2-V POD
DDR4B_DQ[63] AM17 inout 1.2-V POD
DDR4B_DBI_n[0] AU24 inout 1.2-V POD
DDR4B_DBI_n[1] AV26 inout 1.2-V POD
DDR4B_DBI_n[2] AT31 inout 1.2-V POD
DDR4B_DBI_n[3] AL27 inout 1.2-V POD
DDR4B_DBI_n[4] AY18 inout 1.2-V POD
DDR4B_DBI_n[5] AP18 inout 1.2-V POD
DDR4B_DBI_n[6] AH24 inout 1.2-V POD
DDR4B_DBI_n[7] AN17 inout 1.2-V POD
DDR4B_CS_n AT22 output SSTL-12
DDR4B_RESET_n AY22 output 1.2 V
DDR4B_ODT BB23 output SSTL-12
DDR4B_PAR AW23 output SSTL-12
DDR4B_ALERT_n AT25 input 1.2 V
DDR4B_ACT_n AR22 output SSTL-12
DDR4B_RZQ BA21 input 1.2 V

USBFX3
Name Location Direction IO Standard
USBFX3_RESET_n AW11 output 1.8 V
USBFX3_PCLK AV6 output 1.8 V
USBFX3_CTL0_SLCS_n AR3 output 1.8 V
USBFX3_UART_TX AW1 output 1.8 V
USBFX3_UART_RX AU2 input 1.8 V
USBFX3_CTL10 AV11 output 1.8 V
USBFX3_CTL11_A1 AV12 output 1.8 V
USBFX3_CTL12_A0 AV5 output 1.8 V
USBFX3_CTL15_INT_n AP4 input 1.8 V
USBFX3_CTL1_SLWR_n AW9 output 1.8 V
USBFX3_CTL2_SLOE_n AV7 output 1.8 V
USBFX3_CTL3_SLRD_n AV10 output 1.8 V
USBFX3_CTL4_FLAGA AR4 input 1.8 V
USBFX3_CTL5_FLAGB AV2 input 1.8 V
USBFX3_CTL6_FLAGC AU3 input 1.8 V
USBFX3_CTL7_PKTEND_n AV3 output 1.8 V
USBFX3_CTL8_FLAGD AW10 input 1.8 V
USBFX3_CTL9 AU10 output 1.8 V
USBFX3_DQ[0] BA5 inout 1.8 V
USBFX3_DQ[1] BB5 inout 1.8 V
USBFX3_DQ[2] BA4 inout 1.8 V
USBFX3_DQ[3] BB4 inout 1.8 V
USBFX3_DQ[4] AW5 inout 1.8 V
USBFX3_DQ[5] AU5 inout 1.8 V
USBFX3_DQ[6] AY4 inout 1.8 V
USBFX3_DQ[7] AW4 inout 1.8 V
USBFX3_DQ[8] AW3 inout 1.8 V
USBFX3_DQ[9] AY3 inout 1.8 V
USBFX3_DQ[10] AY6 inout 1.8 V
USBFX3_DQ[11] AY7 inout 1.8 V
USBFX3_DQ[12] AU4 inout 1.8 V
USBFX3_DQ[13] BA2 inout 1.8 V
USBFX3_DQ[14] AY2 inout 1.8 V
USBFX3_DQ[15] AV1 inout 1.8 V
USBFX3_DQ[16] AW8 inout 1.8 V
USBFX3_DQ[17] AT7 inout 1.8 V
USBFX3_DQ[18] AU7 inout 1.8 V
USBFX3_DQ[19] AW6 inout 1.8 V
USBFX3_DQ[20] AT9 inout 1.8 V
USBFX3_DQ[21] AU9 inout 1.8 V
USBFX3_DQ[22] AU8 inout 1.8 V
USBFX3_DQ[23] AT10 inout 1.8 V
USBFX3_DQ[24] AT11 inout 1.8 V
USBFX3_DQ[25] AT12 inout 1.8 V
USBFX3_DQ[26] AR11 inout 1.8 V
USBFX3_DQ[27] AR12 inout 1.8 V
USBFX3_DQ[28] AR13 inout 1.8 V
USBFX3_DQ[29] AP13 inout 1.8 V
USBFX3_DQ[30] AU12 inout 1.8 V
USBFX3_DQ[31] AU13 inout 1.8 V
USBFX3_OTG_ID AP3 inout 1.8 V
USBFX3_USB_MODE A5 output 1.8 V

ENETB
Name Location Direction IO Standard
ENETB_RX_CLK B3 input 1.8 V
ENETB_RX_DATA[0] E3 input 1.8 V
ENETB_RX_DATA[1] E2 input 1.8 V
ENETB_RX_DATA[2] G7 input 1.8 V
ENETB_RX_DATA[3] F7 input 1.8 V
ENETB_RX_DATA[4] D3 input 1.8 V
ENETB_RX_DATA[5] D4 input 1.8 V
ENETB_RX_DATA[6] E1 input 1.8 V
ENETB_RX_DATA[7] D1 input 1.8 V
ENETB_RX_COL A4 input 1.8 V
ENETB_RX_CRS C3 input 1.8 V
ENETB_RX_DV C2 input 1.8 V
ENETB_RX_ER D5 input 1.8 V
ENETB_GTX_CLK B4 output 1.8 V
ENETB_TX_DATA[0] F5 output 1.8 V
ENETB_TX_DATA[1] F6 output 1.8 V
ENETB_TX_DATA[2] J8 output 1.8 V
ENETB_TX_DATA[3] J9 output 1.8 V
ENETB_TX_DATA[4] F4 output 1.8 V
ENETB_TX_DATA[5] E4 output 1.8 V
ENETB_TX_DATA[6] H7 output 1.8 V
ENETB_TX_DATA[7] H8 output 1.8 V
ENETB_TX_EN H12 output 1.8 V
ENETB_TX_ER H11 output 1.8 V
ENETB_INT_n E9 input 1.8 V
ENETB_MDC E8 output 1.8 V
ENETB_MDIO A6 inout 1.8 V
ENETB_RESET_n A7 output 1.8 V

I2C for EEPROM (Si5341)
Name Location Direction IO Standard
FPGA_I2C_SCL AU19 inout 1.2 V
FPGA_I2C_SDA AU20 inout 1.2 V

Power Monitor
Name Location Direction IO Standard
PM_I2C_SCL AM10 inout 1.8 V
PM_I2C_SDA W11 inout 1.8 V
PM_ALERT_n Y13 input 1.8 V

PCIe Edge
Name Location Direction IO Standard
PCIE_SMBCLK AP8 inout 1.8 V
PCIE_SMBDAT AP10 inout 1.8 V
PCIE_REFCLK_p AT34 input HCSL
PCIE_TX_p[0] BB34 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[1] BA36 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[2] BB38 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[3] AY38 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[4] BA40 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[5] AV38 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[6] AW40 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[7] AV42 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[8] AU40 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[9] AT42 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[10] AR40 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[11] AP42 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[12] AN40 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[13] AM42 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[14] AL40 output HSSI DIFFERENTIAL I/O
PCIE_TX_p[15] AK42 output HSSI DIFFERENTIAL I/O
PCIE_RX_p[0] AV30 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[1] AY30 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[2] BB30 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[3] AW32 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[4] BA32 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[5] AY34 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[6] AU36 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[7] AW36 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[8] AR36 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[9] AN36 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[10] AT38 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[11] AP38 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[12] AL36 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[13] AM38 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[14] AK38 input CURRENT MODE LOGIC (CML)
PCIE_RX_p[15] AJ36 input CURRENT MODE LOGIC (CML)
PCIE_PERST_n AC26 input 3.0-V LVTTL

QSFPA
Name Location Direction IO Standard
QSFPA_REFCLK_p T34 input LVDS
QSFPA_TX_p[0] N40 output HSSI DIFFERENTIAL I/O
QSFPA_TX_p[1] M42 output HSSI DIFFERENTIAL I/O
QSFPA_TX_p[2] L40 output HSSI DIFFERENTIAL I/O
QSFPA_TX_p[3] K42 output HSSI DIFFERENTIAL I/O
QSFPA_RX_p[0] M38 input HSSI DIFFERENTIAL I/O
QSFPA_RX_p[1] K38 input HSSI DIFFERENTIAL I/O
QSFPA_RX_p[2] L36 input HSSI DIFFERENTIAL I/O
QSFPA_RX_p[3] H38 input HSSI DIFFERENTIAL I/O
QSFPA_INTERRUPT_n V8 input 1.8 V
QSFPA_LP_MODE W8 output 1.8 V
QSFPA_MOD_PRS_n V12 input 1.8 V
QSFPA_MOD_SEL_n W1 output 1.8 V
QSFPA_RST_n V1 output 1.8 V
QSFPA_SCL W6 inout 1.8 V
QSFPA_SDA Y6 inout 1.8 V

QSFPB
Name Location Direction IO Standard
QSFPB_REFCLK_p P34 input LVDS
QSFPB_TX_p[0] J40 output HSSI DIFFERENTIAL I/O
QSFPB_TX_p[1] H42 output HSSI DIFFERENTIAL I/O
QSFPB_TX_p[2] G40 output HSSI DIFFERENTIAL I/O
QSFPB_TX_p[3] F42 output HSSI DIFFERENTIAL I/O
QSFPB_RX_p[0] J36 input HSSI DIFFERENTIAL I/O
QSFPB_RX_p[1] G36 input HSSI DIFFERENTIAL I/O
QSFPB_RX_p[2] C36 input HSSI DIFFERENTIAL I/O
QSFPB_RX_p[3] E36 input HSSI DIFFERENTIAL I/O
QSFPB_INTERRUPT_n U7 input 1.8 V
QSFPB_LP_MODE U8 output 1.8 V
QSFPB_MOD_PRS_n Y7 input 1.8 V
QSFPB_MOD_SEL_n V10 output 1.8 V
QSFPB_RST_n V11 output 1.8 V
QSFPB_SCL U10 inout 1.8 V
QSFPB_SDA U9 inout 1.8 V

Transceiver reference clock
Name Location Direction IO Standard
XCVR_REFCLK1D_p AM34 input LVDS
XCVR_REFCLK1E_p AH34 input LVDS
XCVR_REFCLK1K_p AB34 input LVDS
XCVR_REFCLK1L_p V34 input LVDS
XCVR_REFCLK1M_p M34 input LVDS

MCIO
Name Location Direction IO Standard
MCIO_SMBCLK AJ5 inout 1.8 V
MCIO_SMBDAT AK2 inout 1.8 V
MCIO_CONN_CLK_p Y34 input HCSL
MCIO_TX_p[0] AA40 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[1] Y42 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[2] W40 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[3] V42 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[4] U40 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[5] T42 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[6] R40 output HSSI DIFFERENTIAL I/O
MCIO_TX_p[7] P42 output HSSI DIFFERENTIAL I/O
MCIO_RX_p[0] W36 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[1] Y38 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[2] U36 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[3] V38 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[4] T38 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[5] R36 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[6] P38 input CURRENT MODE LOGIC (CML)
MCIO_RX_p[7] N36 input CURRENT MODE LOGIC (CML)
MCIO_PERST_n AA28 input 3.0-V LVTTL
MCIO_SMB_ALERT_n AJ6 input 1.8 V

EXP
Name Location Direction IO Standard
EXP_EN AA1 input 1.8 V

HPS
Name Location Direction IO Standard
HPS_EMMC_CLK C20 output 1.8 V
HPS_EMMC_CMD L21 inout 1.8 V
HPS_EMMC_DATA[0] J18 inout 1.8 V
HPS_EMMC_DATA[1] K21 inout 1.8 V
HPS_EMMC_DATA[2] H18 inout 1.8 V
HPS_EMMC_DATA[3] P19 inout 1.8 V
HPS_ENETA_MDC B20 output 1.8 V
HPS_ENETA_MDIO R19 inout 1.8 V
HPS_ENETA_RX_CLK B10 input 1.8 V
HPS_ENETA_RX_CTL A17 input 1.8 V
HPS_ENETA_RX_DATA[0] B9 input 1.8 V
HPS_ENETA_RX_DATA[1] A20 input 1.8 V
HPS_ENETA_RX_DATA[2] B19 input 1.8 V
HPS_ENETA_RX_DATA[3] B8 input 1.8 V
HPS_ENETA_TX_CLK A19 output 1.8 V
HPS_ENETA_TX_CTL C17 output 1.8 V
HPS_ENETA_TX_DATA[0] A9 output 1.8 V
HPS_ENETA_TX_DATA[1] B18 output 1.8 V
HPS_ENETA_TX_DATA[2] B12 output 1.8 V
HPS_ENETA_TX_DATA[3] C15 output 1.8 V
HPS_GPIO[0] D18 inout 1.8 V
HPS_GPIO[1] D20 inout 1.8 V
HPS_I2C_SCL N20 inout 1.8 V
HPS_I2C_SDA G18 inout 1.8 V
HPS_OSC_CLK E17 input 1.8 V
HPS_UART_CTS M19 input 1.8 V
HPS_UART_RTS F19 output 1.8 V
HPS_UART_RX F20 input 1.8 V
HPS_UART_TX D19 output 1.8 V
HPS_USB_CLK A15 input 1.8 V
HPS_USB_DATA[0] A11 inout 1.8 V
HPS_USB_DATA[1] B13 inout 1.8 V
HPS_USB_DATA[2] B14 inout 1.8 V
HPS_USB_DATA[3] B17 inout 1.8 V
HPS_USB_DATA[4] A10 inout 1.8 V
HPS_USB_DATA[5] A16 inout 1.8 V
HPS_USB_DATA[6] A12 inout 1.8 V
HPS_USB_DATA[7] C16 inout 1.8 V
HPS_USB_DIR C18 input 1.8 V
HPS_USB_NXT A14 input 1.8 V
HPS_USB_STP B15 output 1.8 V

INFO
Name Location Direction IO Standard
INFO_SPI_SCLK AA29 output 3.0-V LVTTL
INFO_SPI_MISO W29 input 3.0-V LVTTL
INFO_SPI_MOSI W28 output 3.0-V LVTTL
INFO_SPI_CS_n Y28 output 3.0-V LVTTL