system |

2025.06.05.15:11:20 | Datasheet

Overview

Processor
intel_niosv_g Bantam Lake 4.0.0
All Components
intel_niosv_g intel_niosv_g 4.0.0
intel_onchip_memory intel_onchip_memory 1.4.10
jtag_uart altera_avalon_jtag_uart 19.3.0
mm_ccb mm_ccb 19.3.0
pio_ddr4_cal_done altera_avalon_pio 19.2.4
pio_key altera_avalon_pio 19.2.4
sysid_qsys altera_avalon_sysid_qsys 19.1.8
timer altera_avalon_timer 19.3.5
Memory Map

| intel_niosv_g | mm_ccb
instruction_manager | data_manager | m0
emif_io96b_ddr4comp |  |  |
s0_axi4 |  | 0x4000_0000 - 0x7fff_ffff |
s0_axi4lite |  |  |
intel_niosv_g |  |  |
timer_sw_agent |  | 0x0001_0000 - 0x0001_003f |
dm_agent | 0x0000_0000 - 0x0000_ffff | 0x0000_0000 - 0x0000_ffff |
intel_onchip_memory |  |  |
s1 | 0x0080_0000 - 0x0087_ffff | 0x0080_0000 - 0x0087_ffff |
jtag_uart |  |  |
avalon_jtag_slave |  | 0x0001_00c8 - 0x0001_00cf | 0x0048 - 0x004f
mm_ccb |  |  |
s0 |  | 0x0001_0080 - 0x0001_00ff |
pio_ddr4_cal_done |  |  |
s1 |  | 0x0001_00b0 - 0x0001_00bf | 0x0030 - 0x003f
pio_key |  |  |
s1 |  | 0x0001_00a0 - 0x0001_00af | 0x0020 - 0x002f
sysid_qsys |  |  |
control_slave |  | 0x0001_00c0 - 0x0001_00c7 | 0x0040 - 0x0047
timer |  |  |
s1 |  | 0x0001_0080 - 0x0001_009f | 0x0000 - 0x001f

## clock_in

altera_clock_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## emif_io96b_ddr4comp

emif_io96b_ddr4comp v3.0.0

intel_niosv_g | data_manager | emif_io96b_ddr4comp
s0_axi4
iopll_sys | outclk0
s0_axi4_clock_in
outclk0
s0_axi4lite_clock
reset_in | out_reset
core_init_n
out_reset
s0_axi4lite_reset_n

## Parameters
generateLegacySim | false

## Software Assignments (none)

## intel_niosv_g

intel_niosv_g v4.0.0

iopll_sys | outclk0 | intel_niosv_g
clk
reset_in | out_reset
reset
|  | data_manager | mm_ccb
|  | s0
|  | data_manager | emif_io96b_ddr4comp
|  | s0_axi4
|  | data_manager | intel_onchip_memory
|  | s1
|  | instruction_manager
|  | s1
|  | platform_irq_rx | timer
|  | irq
|  | platform_irq_rx | jtag_uart
|  | irq

## Parameters
generateLegacySim | false

## Software Assignments
CLIC_EN | false
CPU_FREQ | 100000000u
DATA_ADDR_WIDTH | 32
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 4096
HAS_CSR_SUPPORT | 1
HAS_DEBUG_STUB |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
INST_ADDR_WIDTH | 32
INT_MODE | 0
MTIME_OFFSET | 0x00010000
NIOSV_CORE_VARIANT | 3
NUM_GPR | 32
NUM_SRF_BANKS | 1
RESET_ADDR | 0x00800000
TICKS_PER_SEC | no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE | 2

## intel_onchip_memory

intel_onchip_memory v1.4.10

intel_niosv_g | data_manager | intel_onchip_memory
s1
instruction_manager
s1
iopll_sys | outclk0
clk1
reset_in | out_reset
reset1

## Parameters
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | system_intel_onchip_memory_0_intel_onchip_memory
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 524288
WRITABLE | 1

## iopll_sys

altera_iopll v20.0.0

clock_in | out_clk | iopll_sys
refclk
reset_in | out_reset
reset
|  | outclk0 | intel_niosv_g
|  | clk
|  | outclk0 | intel_onchip_memory
|  | clk1
|  | outclk0 | emif_io96b_ddr4comp
|  | s0_axi4_clock_in
|  | outclk0
|  | s0_axi4lite_clock
|  | outclk0 | mm_ccb
|  | s0_clk

## Parameters
generateLegacySim | false

## Software Assignments (none)

## jtag_uart

altera_avalon_jtag_uart v19.3.0

mm_ccb | m0 | jtag_uart
avalon_jtag_slave
clock_in | out_clk
clk
intel_niosv_g | platform_irq_rx
irq
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
READ_DEPTH | 64
READ_THRESHOLD | 8
WRITE_DEPTH | 64
WRITE_THRESHOLD | 8

## mm_ccb

mm_ccb v19.3.0

intel_niosv_g | data_manager | mm_ccb
s0
clock_in | out_clk
m0_clk
iopll_sys | outclk0
s0_clk
reset_in | out_reset
m0_reset
out_reset
s0_reset
|  | m0 | jtag_uart
|  | avalon_jtag_slave
|  | m0 | sysid_qsys
|  | control_slave
|  | m0 | timer
|  | s1
|  | m0 | pio_ddr4_cal_done
|  | s1
|  | m0 | pio_key
|  | s1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## pio_ddr4_cal_done

altera_avalon_pio v19.2.4

mm_ccb | m0 | pio_ddr4_cal_done
s1
clock_in | out_clk
clk
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 1
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## pio_key

altera_avalon_pio v19.2.4

mm_ccb | m0 | pio_key
s1
clock_in | out_clk
clk
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 50000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 0

## reset_in

altera_reset_bridge v19.2.0

clock_in | out_clk | reset_in
clk
|  | out_reset | emif_io96b_ddr4comp
|  | core_init_n
|  | out_reset
|  | s0_axi4lite_reset_n
|  | out_reset | mm_ccb
|  | m0_reset
|  | out_reset
|  | s0_reset
|  | out_reset | iopll_sys
|  | reset
|  | out_reset | intel_niosv_g
|  | reset
|  | out_reset | jtag_uart
|  | reset
|  | out_reset | sysid_qsys
|  | reset
|  | out_reset | timer
|  | reset
|  | out_reset | pio_ddr4_cal_done
|  | reset
|  | out_reset | pio_key
|  | reset
|  | out_reset | intel_onchip_memory
|  | reset1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## sysid_qsys

altera_avalon_sysid_qsys v19.1.8

mm_ccb | m0 | sysid_qsys
control_slave
clock_in | out_clk
clk
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
ID | 0
TIMESTAMP | 0

## timer

altera_avalon_timer v19.3.5

mm_ccb | m0 | timer
s1
clock_in | out_clk
clk
intel_niosv_g | platform_irq_rx
irq
reset_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
ALWAYS_RUN | 0
COUNTER_SIZE | 32
FIXED_PERIOD | 0
FREQ | 50000000
LOAD_VALUE | 49999
MULT | 0.001
PERIOD | 1
PERIOD_UNITS | ms
RESET_OUTPUT | 0
SNAPSHOT | 1
TICKS_PER_SEC | 1000
TIMEOUT_PULSE_OUTPUT | 0
TIMER_DEVICE_TYPE | 1

generation took 0.01 seconds | rendering took 0.05 seconds