# File saved with Nlview 7.5.7 2022-07-21 7101 VDI=41 GEI=38 GUI=QT:6.5.3
#  -curmodule
# non-default properties - (restore without -noprops)
property -colorscheme classic
property attrcolor #525252
property autobundle 129
property backgroundcolor #ffffff
property boxcolor0 #000000
property boxcolor1 #515a3d
property boxcolor2 #005b85
property boxcolor7 #653171
property boxhierpins 3
property boxinstcolor #005b85
property boxpincolor #525252
property boxpinfontsize 8
property buscolor #000000
property buswidthlimit 0
property createnetattrdsp 1024
property createvconn 65
property decorate 1
property elidetext 1
property fillcolor1 #b1d272
property fillcolor2 #00c7fd
property fillcolor3 #b4f0ff
property fillcolor5 #c0c0c0
property fillcolor6 #5b69ff
property fillcolor7 #cc94da
property fillcolor8 #86b3ca
property fillcolor9 #98a1ff
property fillcolor10 #548fad
property fillcolor11 #aeaeae
property instattrmax -1
property netcolor #000000
property nohiernegpins 0
property overlaycolor #000000
property pbuscolor #525252
property pbusnamecolor #005b85
property pinattrmax -1
property portcolor #525252
property portnamecolor #005b85
property ripattrmax -1
property rippercolor #000000
property rubberbandcolor #00aaff
property selectionappearance 6
property selectioncolor #aa1027
property sheetheight 34
property sheetwidth 44
property showmarks 9
property showpagenumbers 1
property showripindex 1
property showvconn 1
#
module new golden_top {}
load symbol heart_beat {} HIERBOX pin clk input.left pin led output.right boxcolor 2 fillcolor 2 fillregion 3 linewidth 2
load port CLOCK2_50 input -attr @name CLOCK2_50 -pg 1 -lvl 0 -x 0 -y 80
load port CLOCK3_50 input -attr @name CLOCK3_50 -pg 1 -lvl 0 -x 0 -y 100
load port CLOCK_50 input -attr @name CLOCK_50 -pg 1 -lvl 0 -x 0 -y 60
load port CPU_RESET_N input -attr @name CPU_RESET_N -pg 1 -lvl 0 -x 0 -y 120
load port DRAM_CLK output -attr @name DRAM_CLK -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 350
load port DRAM_CKE output -attr @name DRAM_CKE -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 320
load port DRAM_LDQM output -attr @name DRAM_LDQM -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 430
load port DRAM_UDQM output -attr @name DRAM_UDQM -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 490
load port DRAM_CS_N output -attr @name DRAM_CS_N -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 380
load port DRAM_WE_N output -attr @name DRAM_WE_N -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 520
load port DRAM_CAS_N output -attr @name DRAM_CAS_N -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 290
load port DRAM_RAS_N output -attr @name DRAM_RAS_N -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 460
load port TD_CLK27 input -attr @name TD_CLK27 -pg 1 -lvl 0 -x 0 -y 200
load port TD_HS input -attr @name TD_HS -pg 1 -lvl 0 -x 0 -y 240
load port TD_VS input -attr @name TD_VS -pg 1 -lvl 0 -x 0 -y 260
load port TD_RESET_N output -attr @name TD_RESET_N -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 860
load port AUD_BCLK inout -attr @name AUD_BCLK -pg 1 -lvl 2 -x 230 -y 120
load port AUD_XCK output -attr @name AUD_XCK -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 200
load port AUD_ADCLRCK inout -attr @name AUD_ADCLRCK -pg 1 -lvl 2 -x 230 -y 100
load port AUD_ADCDAT input -attr @name AUD_ADCDAT -pg 1 -lvl 0 -x 0 -y 40
load port AUD_DACLRCK inout -attr @name AUD_DACLRCK -pg 1 -lvl 2 -x 230 -y 170
load port AUD_DACDAT output -attr @name AUD_DACDAT -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 150
load port ADC_SCLK output -attr @name ADC_SCLK -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 80
load port ADC_DOUT input -attr @name ADC_DOUT -pg 1 -lvl 0 -x 0 -y 20
load port ADC_DIN output -attr @name ADC_DIN -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 50
load port ADC_CONVST output -attr @name ADC_CONVST -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 20
load port FPGA_I2C_SCLK output -attr @name FPGA_I2C_SCLK -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 550
load port FPGA_I2C_SDAT inout -attr @name FPGA_I2C_SDAT -pg 1 -lvl 2 -x 230 -y 570
load port IRDA_TXD output -attr @name IRDA_TXD -attr @vconn 1'h0 -pg 1 -lvl 2 -x 230 -y 800
load port IRDA_RXD input -attr @name IRDA_RXD -pg 1 -lvl 0 -x 0 -y 140
load portBus GPIO inout [35:0] -attr @name GPIO[35:0] -portAttr GPIO[35] @name GPIO[35] -portAttr GPIO[34] @name GPIO[34] -portAttr GPIO[33] @name GPIO[33] -portAttr GPIO[32] @name GPIO[32] -portAttr GPIO[31] @name GPIO[31] -portAttr GPIO[30] @name GPIO[30] -portAttr GPIO[29] @name GPIO[29] -portAttr GPIO[28] @name GPIO[28] -portAttr GPIO[27] @name GPIO[27] -portAttr GPIO[26] @name GPIO[26] -portAttr GPIO[25] @name GPIO[25] -portAttr GPIO[24] @name GPIO[24] -portAttr GPIO[23] @name GPIO[23] -portAttr GPIO[22] @name GPIO[22] -portAttr GPIO[21] @name GPIO[21] -portAttr GPIO[20] @name GPIO[20] -portAttr GPIO[19] @name GPIO[19] -portAttr GPIO[18] @name GPIO[18] -portAttr GPIO[17] @name GPIO[17] -portAttr GPIO[16] @name GPIO[16] -portAttr GPIO[15] @name GPIO[15] -portAttr GPIO[14] @name GPIO[14] -portAttr GPIO[13] @name GPIO[13] -portAttr GPIO[12] @name GPIO[12] -portAttr GPIO[11] @name GPIO[11] -portAttr GPIO[10] @name GPIO[10] -portAttr GPIO[9] @name GPIO[9] -portAttr GPIO[8] @name GPIO[8] -portAttr GPIO[7] @name GPIO[7] -portAttr GPIO[6] @name GPIO[6] -portAttr GPIO[5] @name GPIO[5] -portAttr GPIO[4] @name GPIO[4] -portAttr GPIO[3] @name GPIO[3] -portAttr GPIO[2] @name GPIO[2] -portAttr GPIO[1] @name GPIO[1] -portAttr GPIO[0] @name GPIO[0] -pg 1 -lvl 2 -x 230 -y 590
load portBus TD_DATA input [7:0] -attr @name TD_DATA[7:0] -portAttr TD_DATA[7] @name TD_DATA[7] -portAttr TD_DATA[6] @name TD_DATA[6] -portAttr TD_DATA[5] @name TD_DATA[5] -portAttr TD_DATA[4] @name TD_DATA[4] -portAttr TD_DATA[3] @name TD_DATA[3] -portAttr TD_DATA[2] @name TD_DATA[2] -portAttr TD_DATA[1] @name TD_DATA[1] -portAttr TD_DATA[0] @name TD_DATA[0] -pg 1 -lvl 0 -x 0 -y 220
load portBus DRAM_DQ inout [15:0] -attr @name DRAM_DQ[15:0] -portAttr DRAM_DQ[15] @name DRAM_DQ[15] -portAttr DRAM_DQ[14] @name DRAM_DQ[14] -portAttr DRAM_DQ[13] @name DRAM_DQ[13] -portAttr DRAM_DQ[12] @name DRAM_DQ[12] -portAttr DRAM_DQ[11] @name DRAM_DQ[11] -portAttr DRAM_DQ[10] @name DRAM_DQ[10] -portAttr DRAM_DQ[9] @name DRAM_DQ[9] -portAttr DRAM_DQ[8] @name DRAM_DQ[8] -portAttr DRAM_DQ[7] @name DRAM_DQ[7] -portAttr DRAM_DQ[6] @name DRAM_DQ[6] -portAttr DRAM_DQ[5] @name DRAM_DQ[5] -portAttr DRAM_DQ[4] @name DRAM_DQ[4] -portAttr DRAM_DQ[3] @name DRAM_DQ[3] -portAttr DRAM_DQ[2] @name DRAM_DQ[2] -portAttr DRAM_DQ[1] @name DRAM_DQ[1] -portAttr DRAM_DQ[0] @name DRAM_DQ[0] -pg 1 -lvl 2 -x 230 -y 400
load portBus DRAM_BA output [1:0] -attr @name DRAM_BA[1:0] -attr @vconn 2'h0 -portAttr DRAM_BA[1] @name DRAM_BA[1] -portAttr DRAM_BA[0] @name DRAM_BA[0] -pg 1 -lvl 2 -x 230 -y 260
load portBus DRAM_ADDR output [12:0] -attr @name DRAM_ADDR[12:0] -attr @vconn 13'h0 -portAttr DRAM_ADDR[12] @name DRAM_ADDR[12] -portAttr DRAM_ADDR[11] @name DRAM_ADDR[11] -portAttr DRAM_ADDR[10] @name DRAM_ADDR[10] -portAttr DRAM_ADDR[9] @name DRAM_ADDR[9] -portAttr DRAM_ADDR[8] @name DRAM_ADDR[8] -portAttr DRAM_ADDR[7] @name DRAM_ADDR[7] -portAttr DRAM_ADDR[6] @name DRAM_ADDR[6] -portAttr DRAM_ADDR[5] @name DRAM_ADDR[5] -portAttr DRAM_ADDR[4] @name DRAM_ADDR[4] -portAttr DRAM_ADDR[3] @name DRAM_ADDR[3] -portAttr DRAM_ADDR[2] @name DRAM_ADDR[2] -portAttr DRAM_ADDR[1] @name DRAM_ADDR[1] -portAttr DRAM_ADDR[0] @name DRAM_ADDR[0] -pg 1 -lvl 2 -x 230 -y 230
load portBus HEX5 output [6:0] -attr @name HEX5[6:0] -attr @vconn 7'h0 -portAttr HEX5[6] @name HEX5[6] -portAttr HEX5[5] @name HEX5[5] -portAttr HEX5[4] @name HEX5[4] -portAttr HEX5[3] @name HEX5[3] -portAttr HEX5[2] @name HEX5[2] -portAttr HEX5[1] @name HEX5[1] -portAttr HEX5[0] @name HEX5[0] -pg 1 -lvl 2 -x 230 -y 770
load portBus HEX4 output [6:0] -attr @name HEX4[6:0] -attr @vconn 7'h0 -portAttr HEX4[6] @name HEX4[6] -portAttr HEX4[5] @name HEX4[5] -portAttr HEX4[4] @name HEX4[4] -portAttr HEX4[3] @name HEX4[3] -portAttr HEX4[2] @name HEX4[2] -portAttr HEX4[1] @name HEX4[1] -portAttr HEX4[0] @name HEX4[0] -pg 1 -lvl 2 -x 230 -y 740
load portBus HEX3 output [6:0] -attr @name HEX3[6:0] -attr @vconn 7'h0 -portAttr HEX3[6] @name HEX3[6] -portAttr HEX3[5] @name HEX3[5] -portAttr HEX3[4] @name HEX3[4] -portAttr HEX3[3] @name HEX3[3] -portAttr HEX3[2] @name HEX3[2] -portAttr HEX3[1] @name HEX3[1] -portAttr HEX3[0] @name HEX3[0] -pg 1 -lvl 2 -x 230 -y 710
load portBus HEX2 output [6:0] -attr @name HEX2[6:0] -attr @vconn 7'h0 -portAttr HEX2[6] @name HEX2[6] -portAttr HEX2[5] @name HEX2[5] -portAttr HEX2[4] @name HEX2[4] -portAttr HEX2[3] @name HEX2[3] -portAttr HEX2[2] @name HEX2[2] -portAttr HEX2[1] @name HEX2[1] -portAttr HEX2[0] @name HEX2[0] -pg 1 -lvl 2 -x 230 -y 680
load portBus HEX1 output [6:0] -attr @name HEX1[6:0] -attr @vconn 7'h0 -portAttr HEX1[6] @name HEX1[6] -portAttr HEX1[5] @name HEX1[5] -portAttr HEX1[4] @name HEX1[4] -portAttr HEX1[3] @name HEX1[3] -portAttr HEX1[2] @name HEX1[2] -portAttr HEX1[1] @name HEX1[1] -portAttr HEX1[0] @name HEX1[0] -pg 1 -lvl 2 -x 230 -y 650
load portBus HEX0 output [6:0] -attr @name HEX0[6:0] -attr @vconn 7'h0 -portAttr HEX0[6] @name HEX0[6] -portAttr HEX0[5] @name HEX0[5] -portAttr HEX0[4] @name HEX0[4] -portAttr HEX0[3] @name HEX0[3] -portAttr HEX0[2] @name HEX0[2] -portAttr HEX0[1] @name HEX0[1] -portAttr HEX0[0] @name HEX0[0] -pg 1 -lvl 2 -x 230 -y 620
load portBus LEDR output [9:0] -attr @name LEDR[9:0] -attr @vconn 10'h0 -portAttr LEDR[9] @name LEDR[9] -portAttr LEDR[8] @name LEDR[8] -portAttr LEDR[7] @name LEDR[7] -portAttr LEDR[6] @name LEDR[6] -portAttr LEDR[5] @name LEDR[5] -portAttr LEDR[4] @name LEDR[4] -portAttr LEDR[3] @name LEDR[3] -portAttr LEDR[2] @name LEDR[2] -portAttr LEDR[1] @name LEDR[1] -portAttr LEDR[0] @name LEDR[0] -pg 1 -lvl 2 -x 230 -y 830
load portBus SW input [9:0] -attr @name SW[9:0] -portAttr SW[9] @name SW[9] -portAttr SW[8] @name SW[8] -portAttr SW[7] @name SW[7] -portAttr SW[6] @name SW[6] -portAttr SW[5] @name SW[5] -portAttr SW[4] @name SW[4] -portAttr SW[3] @name SW[3] -portAttr SW[2] @name SW[2] -portAttr SW[1] @name SW[1] -portAttr SW[0] @name SW[0] -pg 1 -lvl 0 -x 0 -y 180
load portBus KEY input [3:0] -attr @name KEY[3:0] -portAttr KEY[3] @name KEY[3] -portAttr KEY[2] @name KEY[2] -portAttr KEY[1] @name KEY[1] -portAttr KEY[0] @name KEY[0] -pg 1 -lvl 0 -x 0 -y 160
load inst heart_beat_clk50 heart_beat {} -autohide -attr @name heart_beat_clk50 -attr @cell heart_beat -pinAttr clk @name clk -pinAttr clk @vconn 1'h0 -pinAttr led @name led -hierPinAttr clk @name clk -hierPinAttr led @name led -pg 1 -lvl 1 -x 80 -y 50
load net gnd -ground -attr @name gnd -port ADC_CONVST -port ADC_DIN -port ADC_SCLK -port AUD_DACDAT -port AUD_XCK -port DRAM_ADDR[12] -port DRAM_ADDR[11] -port DRAM_ADDR[10] -port DRAM_ADDR[9] -port DRAM_ADDR[8] -port DRAM_ADDR[7] -port DRAM_ADDR[6] -port DRAM_ADDR[5] -port DRAM_ADDR[4] -port DRAM_ADDR[3] -port DRAM_ADDR[2] -port DRAM_ADDR[1] -port DRAM_ADDR[0] -port DRAM_BA[1] -port DRAM_BA[0] -port DRAM_CAS_N -port DRAM_CKE -port DRAM_CLK -port DRAM_CS_N -port DRAM_LDQM -port DRAM_RAS_N -port DRAM_UDQM -port DRAM_WE_N -port FPGA_I2C_SCLK -port HEX0[6] -port HEX0[5] -port HEX0[4] -port HEX0[3] -port HEX0[2] -port HEX0[1] -port HEX0[0] -port HEX1[6] -port HEX1[5] -port HEX1[4] -port HEX1[3] -port HEX1[2] -port HEX1[1] -port HEX1[0] -port HEX2[6] -port HEX2[5] -port HEX2[4] -port HEX2[3] -port HEX2[2] -port HEX2[1] -port HEX2[0] -port HEX3[6] -port HEX3[5] -port HEX3[4] -port HEX3[3] -port HEX3[2] -port HEX3[1] -port HEX3[0] -port HEX4[6] -port HEX4[5] -port HEX4[4] -port HEX4[3] -port HEX4[2] -port HEX4[1] -port HEX4[0] -port HEX5[6] -port HEX5[5] -port HEX5[4] -port HEX5[3] -port HEX5[2] -port HEX5[1] -port HEX5[0] -port IRDA_TXD -port LEDR[9] -port LEDR[8] -port LEDR[7] -port LEDR[6] -port LEDR[5] -port LEDR[4] -port LEDR[3] -port LEDR[2] -port LEDR[1] -port LEDR[0] -port TD_RESET_N -pin heart_beat_clk50 clk
load net GPIO[0] -attr @name GPIO[0] -attr @rip 0 -port GPIO[0]
load net GPIO[1] -attr @name GPIO[1] -attr @rip 1 -port GPIO[1]
load net GPIO[2] -attr @name GPIO[2] -attr @rip 2 -port GPIO[2]
load net GPIO[3] -attr @name GPIO[3] -attr @rip 3 -port GPIO[3]
load net GPIO[4] -attr @name GPIO[4] -attr @rip 4 -port GPIO[4]
load net GPIO[5] -attr @name GPIO[5] -attr @rip 5 -port GPIO[5]
load net GPIO[6] -attr @name GPIO[6] -attr @rip 6 -port GPIO[6]
load net GPIO[7] -attr @name GPIO[7] -attr @rip 7 -port GPIO[7]
load net GPIO[8] -attr @name GPIO[8] -attr @rip 8 -port GPIO[8]
load net GPIO[9] -attr @name GPIO[9] -attr @rip 9 -port GPIO[9]
load net GPIO[10] -attr @name GPIO[10] -attr @rip 10 -port GPIO[10]
load net GPIO[11] -attr @name GPIO[11] -attr @rip 11 -port GPIO[11]
load net GPIO[12] -attr @name GPIO[12] -attr @rip 12 -port GPIO[12]
load net GPIO[13] -attr @name GPIO[13] -attr @rip 13 -port GPIO[13]
load net GPIO[14] -attr @name GPIO[14] -attr @rip 14 -port GPIO[14]
load net GPIO[15] -attr @name GPIO[15] -attr @rip 15 -port GPIO[15]
load net GPIO[16] -attr @name GPIO[16] -attr @rip 16 -port GPIO[16]
load net GPIO[17] -attr @name GPIO[17] -attr @rip 17 -port GPIO[17]
load net GPIO[18] -attr @name GPIO[18] -attr @rip 18 -port GPIO[18]
load net GPIO[19] -attr @name GPIO[19] -attr @rip 19 -port GPIO[19]
load net GPIO[20] -attr @name GPIO[20] -attr @rip 20 -port GPIO[20]
load net GPIO[21] -attr @name GPIO[21] -attr @rip 21 -port GPIO[21]
load net GPIO[22] -attr @name GPIO[22] -attr @rip 22 -port GPIO[22]
load net GPIO[23] -attr @name GPIO[23] -attr @rip 23 -port GPIO[23]
load net GPIO[24] -attr @name GPIO[24] -attr @rip 24 -port GPIO[24]
load net GPIO[25] -attr @name GPIO[25] -attr @rip 25 -port GPIO[25]
load net GPIO[26] -attr @name GPIO[26] -attr @rip 26 -port GPIO[26]
load net GPIO[27] -attr @name GPIO[27] -attr @rip 27 -port GPIO[27]
load net GPIO[28] -attr @name GPIO[28] -attr @rip 28 -port GPIO[28]
load net GPIO[29] -attr @name GPIO[29] -attr @rip 29 -port GPIO[29]
load net GPIO[30] -attr @name GPIO[30] -attr @rip 30 -port GPIO[30]
load net GPIO[31] -attr @name GPIO[31] -attr @rip 31 -port GPIO[31]
load net GPIO[32] -attr @name GPIO[32] -attr @rip 32 -port GPIO[32]
load net GPIO[33] -attr @name GPIO[33] -attr @rip 33 -port GPIO[33]
load net GPIO[34] -attr @name GPIO[34] -attr @rip 34 -port GPIO[34]
load net GPIO[35] -attr @name GPIO[35] -attr @rip 35 -port GPIO[35]
load net FPGA_I2C_SDAT -attr @name FPGA_I2C_SDAT -port FPGA_I2C_SDAT
netloc FPGA_I2C_SDAT 1 1 1 N 570
load net AUD_DACLRCK -attr @name AUD_DACLRCK -port AUD_DACLRCK
netloc AUD_DACLRCK 1 1 1 N 170
load net AUD_ADCLRCK -attr @name AUD_ADCLRCK -port AUD_ADCLRCK
netloc AUD_ADCLRCK 1 1 1 N 100
load net AUD_BCLK -attr @name AUD_BCLK -port AUD_BCLK
netloc AUD_BCLK 1 1 1 N 120
load net DRAM_DQ[0] -attr @name DRAM_DQ[0] -attr @rip 0 -port DRAM_DQ[0]
load net DRAM_DQ[1] -attr @name DRAM_DQ[1] -attr @rip 1 -port DRAM_DQ[1]
load net DRAM_DQ[2] -attr @name DRAM_DQ[2] -attr @rip 2 -port DRAM_DQ[2]
load net DRAM_DQ[3] -attr @name DRAM_DQ[3] -attr @rip 3 -port DRAM_DQ[3]
load net DRAM_DQ[4] -attr @name DRAM_DQ[4] -attr @rip 4 -port DRAM_DQ[4]
load net DRAM_DQ[5] -attr @name DRAM_DQ[5] -attr @rip 5 -port DRAM_DQ[5]
load net DRAM_DQ[6] -attr @name DRAM_DQ[6] -attr @rip 6 -port DRAM_DQ[6]
load net DRAM_DQ[7] -attr @name DRAM_DQ[7] -attr @rip 7 -port DRAM_DQ[7]
load net DRAM_DQ[8] -attr @name DRAM_DQ[8] -attr @rip 8 -port DRAM_DQ[8]
load net DRAM_DQ[9] -attr @name DRAM_DQ[9] -attr @rip 9 -port DRAM_DQ[9]
load net DRAM_DQ[10] -attr @name DRAM_DQ[10] -attr @rip 10 -port DRAM_DQ[10]
load net DRAM_DQ[11] -attr @name DRAM_DQ[11] -attr @rip 11 -port DRAM_DQ[11]
load net DRAM_DQ[12] -attr @name DRAM_DQ[12] -attr @rip 12 -port DRAM_DQ[12]
load net DRAM_DQ[13] -attr @name DRAM_DQ[13] -attr @rip 13 -port DRAM_DQ[13]
load net DRAM_DQ[14] -attr @name DRAM_DQ[14] -attr @rip 14 -port DRAM_DQ[14]
load net DRAM_DQ[15] -attr @name DRAM_DQ[15] -attr @rip 15 -port DRAM_DQ[15]
load net CLOCK2_50 -attr @name CLOCK2_50 -port CLOCK2_50
netloc CLOCK2_50 1 0 1 N 80
load netBundle GPIO [35:0] -attr @name GPIO
netbloc GPIO 1 1 1 N 590
load netBundle DRAM_DQ [15:0] -attr @name DRAM_DQ
netbloc DRAM_DQ 1 1 1 N 400
levelinfo -pg 1 0 80 230
pagesize -pg 1 -db -bbox -sgen -120 0 380 880
show
zoom 1.50794
scrollpos -640 -8
#
# initialize ictrl to current module golden_top {}
ictrl init {} |
ictrl property autohide 1
ictrl property addSubpinInfo 1
ictrl property addSubportInfo 1
ictrl property addFillcolor12 0
