Sdram_RD_FIFO |

2025.05.27.14:13:20 | Datasheet

Overview

Memory Map

## fifo_0

fifo v19.4.0

## Parameters
GUI_Clock | 4
GUI_delaypipe | 4
GUI_synStage | 3
GUI_LegacyRREQ | 1
GUI_RAM_BLOCK_TYPE | Auto
GUI_Optimize | 0
GUI_Width | 16
GUI_Depth | 512
GUI_output_width | 8
GUI_AlmostFullThr | 1
GUI_AlmostEmptyThr | 1
GUI_MAX_DEPTH | Auto
GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT | true
GUI_DISABLE_REG_POWER_UP_VALUE | false
GUI_diff_widths | false
GUI_Full | true
GUI_Empty | true
GUI_UsedW | true
GUI_AlmostFull | false
GUI_AlmostEmpty | false
GUI_sc_aclr | false
GUI_sc_sclr | false
GUI_rsFull | false
GUI_rsEmpty | true
GUI_rsUsedW | true
GUI_wsFull | true
GUI_wsEmpty | false
GUI_wsUsedW | true
GUI_msb_usedw | false
GUI_dc_aclr | true
GUI_write_aclr_synch | false
GUI_read_aclr_synch | false
GUI_OVERFLOW_CHECKING | false
GUI_UNDERFLOW_CHECKING | false
GUI_LE_BasedFIFO | false
GUI_MAX_DEPTH_BY_9 | false
GUI_ENABLE_ECC | false
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

generation took 0.00 seconds | rendering took 0.02 seconds