nios_system_emif_io96b_ddr4comp_0 |

2025.06.05.00:28:15 | Datasheet

Overview

Memory Map

| emif_io96b_ddr4comp_0_cal_0 | emif_io96b_ddr4comp_0_cal_0_cal_0 | emif_io96b_ddr4comp_0_cal_0_cal_0_jamb | emif_io96b_ddr4comp_0_cal_0_cal_0_jamb_jamb
m0_axi4lite | m0_axi4lite | master | master
emif_io96b_ddr4comp_0 |  |  |  |
s0_axi4 |  |  |  |
s0_axi4lite |  |  |  |
emif_io96b_ddr4comp_0_cal_0 |  |  |  |
s0_axi4lite |  |  |  |
s0_noc_axi4lite |  |  |  |
s0_noc_axi4litenoc |  |  |  |
emif_io96b_ddr4comp_0_cal_0_cal_0 |  |  |  |
s0_axi4lite |  |  |  |
s0_noc_axi4lite |  |  |  |
s0_noc_axi4litenoc |  |  |  |

## emif_io96b_ddr4comp_0

emif_io96b_ddr4comp v3.0.0

## Parameters
MEM_CHANNEL_DATA_DQ_WIDTH | 32
MEM_CHANNEL_ECC_DQ_WIDTH | 0
MEM_DIE_DQ_WIDTH | 16
MEM_DIE_DENSITY_GBITS | 4
MEM_CHANNEL_CS_WIDTH | 1
MEM_SPEEDBIN | 2666T
MEM_CLAMSHELL_EN | false
MEM_AC_PARITY_EN | false
MEM_OPERATING_FREQ_MHZ_AUTOSET_EN | true
MEM_OPERATING_FREQ_MHZ | 1200
CTRL_DM_EN | true
CTRL_WR_DBI_EN | false
CTRL_RD_DBI_EN | false
TURNAROUND_R2W_SAMECS_CYC | 0
TURNAROUND_R2R_SAMECS_CYC | 0
TURNAROUND_W2W_SAMECS_CYC | 0
TURNAROUND_W2R_SAMECS_CYC | 0
PHY_REFCLK_FREQ_MHZ_AUTOSET_EN | false
PHY_REFCLK_ADVANCED_SELECT_EN | true
PHY_REFCLK_FREQ_MHZ | 150.0
PHY_AC_PLACEMENT | BOT
PHY_ALERT_N_PLACEMENT | AC2
PHY_FORCE_MIN_4_AC_LANES_EN | false
PHY_MAINBAND_ACCESS_MODE | ASYNC
PHY_SIDEBAND_ACCESS_MODE | FABRIC
PHY_SWIZZLE_MAP | PIN_SWIZZLE_CH0_DQS0=0,2,4,6,3,1,5,7;PIN_SWIZZLE_CH0_DQS1=8,10,14,12,9,11,13,15;PIN_SWIZZLE_CH0_DQS2=21,20,18,16,17,19,22,23;PIN_SWIZZLE_CH0_DQS3=30,28,24,26,27,31,29,25;
DEBUG_TOOLS_EN | false
INSTANCE_ID | 0
ADV_CAL_ENABLE_MARGIN | false
MEM_WR_PREAMBLE_MODE | 1.0
MEM_RD_PREAMBLE_MODE | 1.0
MEM_CL_CYC | 18.0
MEM_CWL_CYC | 12.0
MEM_TREFI_NS | 7800.0
MEM_TRAS_NS | 32.0
MEM_TRCD_NS | 13.5
MEM_TRP_NS | 13.5
MEM_TRC_NS | 45.5
MEM_TCCD_L_NS | 6.0
MEM_TCCD_S_NS | 4.0
MEM_TRRD_L_NS | 8.0
MEM_TRRD_S_NS | 7.0
MEM_TFAW_NS | 30.0
MEM_TWTR_L_NS | 9.0
MEM_TWTR_S_NS | 3.0
MEM_TWR_NS | 15.0
MEM_TMRD_NS | 6.66667
MEM_TCKSRE_NS | 13.0
MEM_TCKSRX_NS | 13.0
MEM_TCKE_NS | 7.0
MEM_TCKESR_CYC | 8.0
MEM_TMPRR_NS | 0.83333
MEM_TRFC_NS | 260.0
MEM_TDQSCK_NS | 0.0
MEM_TDQSS_CYC | 0.0
MEM_TDSH_NS | 0.15
MEM_TDSS_NS | 0.15
MEM_TIH_NS | 80000.0
MEM_TIS_NS | 55000.0
MEM_TQSH_NS | 0.33333
MEM_TWLH_NS | 0.10833
MEM_TWLS_NS | 0.10833
MEM_TRFC_DLR_NS | 0.0
MEM_TRRD_DLR_NS | 0.0
MEM_TFAW_DLR_NS | 0.0
MEM_TCCD_DLR_NS | 0.0
MEM_TXP_NS | 6.0
MEM_TXS_NS | 270.0
MEM_TXS_DLL_NS | 853.33333
MEM_TCPDED_NS | 3.33333
MEM_TMOD_NS | 20.0
MEM_TZQCS_NS | 106.66667
MEM_TZQINIT_CYC | 1024.0
MEM_TZQOPER_CYC | 512.0
JEDEC_OVERRIDE_TABLE_PARAM_NAME | MEM_CL_CYC,MEM_TRCD_NS,MEM_TRP_NS,MEM_TCCD_L_NS,MEM_TCCD_S_NS,MEM_TRRD_L_NS,MEM_TRRD_S_NS,MEM_TCKSRE_NS,MEM_TCKSRX_NS,MEM_TCKE_NS,MEM_TCKESR_CYC,MEM_TRC_NS,MEM_TWTR_L_NS,MEM_TWTR_S_NS
EX_DESIGN_HDL_FORMAT | VERILOG
EX_DESIGN_GEN_SYNTH | true
EX_DESIGN_GEN_SIM | true
EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN | true
EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ | 310.0
EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ | 100.0
EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ | 100
EX_DESIGN_TG_CSR_ACCESS_MODE | JTAG
EX_DESIGN_TG_PROGRAM | MEDIUM
EX_DESIGN_PMON_CH0_EN | false
PHY_TERM_X_R_S_AC_OUTPUT_OHM | SERIES_34_OHM_CAL
PHY_TERM_X_R_S_CK_OUTPUT_OHM | SERIES_34_OHM_CAL
PHY_TERM_X_R_S_DQ_OUTPUT_OHM | SERIES_34_OHM_CAL
PHY_TERM_X_DQ_SLEW_RATE | FASTEST
PHY_TERM_X_R_T_DQ_INPUT_OHM | RT_50_OHM_CAL
PHY_TERM_X_DQ_VREF | 68.3
PHY_TERM_X_R_T_REFCLK_INPUT_OHM | RT_DIFF
MEM_ODT_DQ_X_TGT_WR | 4
MEM_ODT_DQ_X_NON_TGT_WR | off
MEM_ODT_DQ_X_NON_TGT_RD | off
MEM_ODT_DQ_X_RON | 7
MEM_VREF_DQ_X_RANGE | 2
MEM_VREF_DQ_X_VALUE | 67.75
ANALOG_PARAM_DERIVATION_PARAM_NAME |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## emif_io96b_ddr4comp_0_cal_0

emif_io96b_ddr4comp_emif_io96b_cal v3.0.0

## Parameters
INSTANCE_ID | 0
NUM_CALBUS_PERIPHS | 1
NUM_CALBUS_PLLS | 0
PORT_S_AXIL_MODE | FABRIC
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## emif_io96b_ddr4comp_0_cal_0_cal_0

emif_io96b_cal v2.1.0

## Parameters
INSTANCE_ID | 0
NUM_CALBUS_PERIPHS | 1
NUM_CALBUS_PLLS | 0
PORT_S_AXIL_MODE | FABRIC
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

## emif_io96b_ddr4comp_0_cal_0_cal_0_jamb

emif_io96b_cal_alt_mem_if_jtag_master v2.1.0

## Parameters
USE_PLI | 0
PLI_PORT | 50000
FAST_VER | 0
FIFO_DEPTHS | 2
generateLegacySim | false

## Software Assignments (none)

## emif_io96b_ddr4comp_0_cal_0_cal_0_jamb_jamb

alt_mem_if_jtag_master v19.1

## Parameters
USE_PLI | 0
PLI_PORT | 50000
FAST_VER | 0
FIFO_DEPTHS | 2
generateLegacySim | false

## Software Assignments (none)

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