nios_system |

2025.05.29.11:39:02 | Datasheet

Overview

Processor
niosv_g Bantam Lake 4.0.0
All Components
jtag_uart altera_avalon_jtag_uart 19.3.0
mm_bridge_peripheral altera_avalon_mm_bridge 20.1.0
niosv_g intel_niosv_g 4.0.0
onchip_memory intel_onchip_memory 1.4.10
pio_sw altera_avalon_pio 19.2.4
spi_master altera_avalon_spi 19.2.6
sysid_qsys altera_avalon_sysid_qsys 19.1.8
Memory Map

| mm_bridge_peripheral | niosv_g
m0 | instruction_manager | data_manager
jtag_uart |  |  |
avalon_jtag_slave | 0x0000_1000 - 0x0000_1007 |  | 0x0008_1000 - 0x0008_1007
mm_bridge_peripheral |  |  |
s0 |  |  | 0x0008_0000 - 0x000f_ffff
niosv_g |  |  |
timer_sw_agent |  |  | 0x0001_0000 - 0x0001_003f
dm_agent |  | 0x0000_0000 - 0x0000_ffff | 0x0000_0000 - 0x0000_ffff
onchip_memory |  |  |
s1 |  | 0x0004_0000 - 0x0007_ffff | 0x0004_0000 - 0x0007_ffff
pio_sw |  |  |
s1 | 0x0000_1020 - 0x0000_102f |  | 0x0008_1020 - 0x0008_102f
spi_master |  |  |
spi_control_port | 0x0000_0000 - 0x0000_001f |  | 0x0008_0000 - 0x0008_001f
sysid_qsys |  |  |
control_slave | 0x0000_1008 - 0x0000_100f |  | 0x0008_1008 - 0x0008_100f

## clock_in

altera_clock_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## iopll

altera_iopll v20.0.0

clock_in | out_clk | iopll
refclk
reset_bridge | out_reset
reset
|  | outclk0 | pio_sw
|  | clk
|  | outclk0 | jtag_uart
|  | clk
|  | outclk0 | sysid_qsys
|  | clk
|  | outclk0 | niosv_g
|  | clk
|  | outclk0 | mm_bridge_peripheral
|  | clk
|  | outclk0 | spi_master
|  | clk
|  | outclk0 | onchip_memory
|  | clk1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## jtag_uart

altera_avalon_jtag_uart v19.3.0

mm_bridge_peripheral | m0 | jtag_uart
avalon_jtag_slave
iopll | outclk0
clk
niosv_g | platform_irq_rx
irq
reset_bridge | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
READ_DEPTH | 64
READ_THRESHOLD | 8
WRITE_DEPTH | 64
WRITE_THRESHOLD | 8

## mm_bridge_peripheral

altera_avalon_mm_bridge v20.1.0

niosv_g | data_manager | mm_bridge_peripheral
s0
iopll | outclk0
clk
reset_bridge | out_reset
reset
|  | m0 | jtag_uart
|  | avalon_jtag_slave
|  | m0 | sysid_qsys
|  | control_slave
|  | m0 | pio_sw
|  | s1
|  | m0 | spi_master
|  | spi_control_port

## Parameters
generateLegacySim | false

## Software Assignments (none)

## niosv_g

intel_niosv_g v4.0.0

iopll | outclk0 | niosv_g
clk
reset_bridge | out_reset
reset
|  | data_manager | mm_bridge_peripheral
|  | s0
|  | data_manager | onchip_memory
|  | s1
|  | instruction_manager
|  | s1
|  | platform_irq_rx | pio_sw
|  | irq
|  | platform_irq_rx | jtag_uart
|  | irq
|  | platform_irq_rx | spi_master
|  | irq

## Parameters
generateLegacySim | false

## Software Assignments
CLIC_EN | false
CPU_FREQ | 100000000u
DATA_ADDR_WIDTH | 32
DCACHE_LINE_SIZE | 32
DCACHE_LINE_SIZE_LOG2 | 5
DCACHE_SIZE | 4096
HAS_CSR_SUPPORT | 1
HAS_DEBUG_STUB |
ICACHE_LINE_SIZE | 32
ICACHE_LINE_SIZE_LOG2 | 5
ICACHE_SIZE | 4096
INST_ADDR_WIDTH | 32
INT_MODE | 0
MTIME_OFFSET | 0x00010000
NIOSV_CORE_VARIANT | 3
NUM_GPR | 32
NUM_SRF_BANKS | 1
RESET_ADDR | 0x00040000
TICKS_PER_SEC | no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE | 2

## onchip_memory

intel_onchip_memory v1.4.10

niosv_g | data_manager | onchip_memory
s1
instruction_manager
s1
iopll | outclk0
clk1
reset_bridge | out_reset
reset1

## Parameters
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | onchip_memory_onchip_memory
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 0
SIZE_MULTIPLE | 1
SIZE_VALUE | 262144
WRITABLE | 1

## pio_sw

altera_avalon_pio v19.2.4

mm_bridge_peripheral | m0 | pio_sw
s1
iopll | outclk0
clk
niosv_g | platform_irq_rx
irq
reset_bridge | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 10
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | ANY
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## reset_bridge

altera_reset_bridge v19.2.0

clock_in | out_clk | reset_bridge
clk
reset_release | ninit_done
in_reset
reset_in | out_reset
in_reset
|  | out_reset | iopll
|  | reset
|  | out_reset | niosv_g
|  | reset
|  | out_reset | sysid_qsys
|  | reset
|  | out_reset | jtag_uart
|  | reset
|  | out_reset | pio_sw
|  | reset
|  | out_reset | mm_bridge_peripheral
|  | reset
|  | out_reset | spi_master
|  | reset
|  | out_reset | onchip_memory
|  | reset1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## reset_in

altera_reset_bridge v19.2.0

clock_in | out_clk | reset_in
clk
|  | out_reset | reset_bridge
|  | in_reset

## Parameters
generateLegacySim | false

## Software Assignments (none)

## reset_release

intel_user_rst_clkgate v1.0.1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## spi_master

altera_avalon_spi v19.2.6

mm_bridge_peripheral | m0 | spi_master
spi_control_port
iopll | outclk0
clk
niosv_g | platform_irq_rx
irq
reset_bridge | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
CLOCKMULT | 1
CLOCKPHASE | 0
CLOCKPOLARITY | 0
CLOCKUNITS | "Hz"
DATABITS | 8
DATAWIDTH | 16
DELAYMULT | "1.0E-9"
DELAYUNITS | "ns"
EXTRADELAY | 0
INSERT_SYNC | 0
ISMASTER | 1
LSBFIRST | 0
NUMSLAVES | 1
PREFIX | "spi_"
SYNC_REG_DEPTH | 2
TARGETCLOCK | 250000u
TARGETSSDELAY | "0.0"

## sysid_qsys

altera_avalon_sysid_qsys v19.1.8

mm_bridge_peripheral | m0 | sysid_qsys
control_slave
iopll | outclk0
clk
reset_bridge | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
ID | 0
TIMESTAMP | 0

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