emif_io96b_hps_emif_io96b_hps_300_dreo77y_refclk_bridge |

2025.08.14.15:42:49 | Datasheet

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## refclk_bridge

qsys_interface_bridge v1.0

## Parameters
INTERFACES | refclk_in clock sink,refclk_out clock source,refclk_in_gpio conduit end,refclk_out_gpio conduit start
PORTS | refclk_in refclk_in clk input 1,refclk_out refclk_out clk output 1,refclk_in_gpio refclk_in_gpio export output 1,refclk_out_gpio refclk_out_gpio export input 1
CONNECTIONS | refclk_in refclk_in_gpio,refclk_out_gpio refclk_out
CUSTOM_ELABORATION_COMMANDS |
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments (none)

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