| MEM_CHANNEL_DATA_DQ_WIDTH |
32 |
| MEM_CHANNEL_ECC_DQ_WIDTH |
0 |
| MEM_DIE_DQ_WIDTH |
16 |
| MEM_DIE_DENSITY_GBITS |
4 |
| MEM_CHANNEL_CS_WIDTH |
1 |
| MEM_SPEEDBIN |
2666T |
| MEM_CLAMSHELL_EN |
false |
| MEM_AC_PARITY_EN |
false |
| MEM_OPERATING_FREQ_MHZ_AUTOSET_EN |
true |
| MEM_OPERATING_FREQ_MHZ |
1066.667 |
| CTRL_DM_EN |
false |
| CTRL_WR_DBI_EN |
false |
| CTRL_RD_DBI_EN |
true |
| TURNAROUND_R2W_SAMECS_CYC |
0 |
| TURNAROUND_R2R_SAMECS_CYC |
0 |
| TURNAROUND_W2W_SAMECS_CYC |
0 |
| TURNAROUND_W2R_SAMECS_CYC |
0 |
| PHY_REFCLK_FREQ_MHZ_AUTOSET_EN |
false |
| PHY_REFCLK_ADVANCED_SELECT_EN |
true |
| PHY_REFCLK_FREQ_MHZ |
150.0 |
| PHY_AC_PLACEMENT |
BOT |
| PHY_ALERT_N_PLACEMENT |
AC2 |
| PHY_FORCE_MIN_4_AC_LANES_EN |
false |
| PHY_MAINBAND_ACCESS_MODE |
HARD_PATH |
| PHY_SIDEBAND_ACCESS_MODE |
HARD_PATH |
| PHY_SWIZZLE_MAP |
PIN_SWIZZLE_CH0_DQS0=0 2 4 6 3 1 5 7;PIN_SWIZZLE_CH0_DQS1=8 10 14 12 9 11 13 15;PIN_SWIZZLE_CH0_DQS2=21 20 18 16 17 19 22 23;PIN_SWIZZLE_CH0_DQS3=30 28 24 26 27 31 29 25; |
| DEBUG_TOOLS_EN |
false |
| INSTANCE_ID |
0 |
| ADV_CAL_ENABLE_MARGIN |
false |
| MEM_WR_PREAMBLE_MODE |
1.0 |
| MEM_RD_PREAMBLE_MODE |
1.0 |
| MEM_CL_CYC |
18.0 |
| MEM_CWL_CYC |
11.0 |
| MEM_TREFI_NS |
7800.0 |
| MEM_TRAS_NS |
32.0 |
| MEM_TRCD_NS |
13.5 |
| MEM_TRP_NS |
13.5 |
| MEM_TRC_NS |
45.5 |
| MEM_TCCD_L_NS |
6.0 |
| MEM_TCCD_S_NS |
4.0 |
| MEM_TRRD_L_NS |
7.0 |
| MEM_TRRD_S_NS |
6.0 |
| MEM_TFAW_NS |
30.0 |
| MEM_TWTR_L_NS |
8.0 |
| MEM_TWTR_S_NS |
3.0 |
| MEM_TWR_NS |
15.0 |
| MEM_TMRD_NS |
7.5 |
| MEM_TCKSRE_NS |
13.0 |
| MEM_TCKSRX_NS |
13.0 |
| MEM_TCKE_NS |
7.0 |
| MEM_TCKESR_CYC |
8.0 |
| MEM_TMPRR_NS |
0.9375 |
| MEM_TRFC_NS |
260.0 |
| MEM_TDQSCK_NS |
0.0 |
| MEM_TDQSS_CYC |
0.0 |
| MEM_TDSH_NS |
0.16875 |
| MEM_TDSS_NS |
0.16875 |
| MEM_TIH_NS |
80000.0 |
| MEM_TIS_NS |
55000.0 |
| MEM_TQSH_NS |
0.375 |
| MEM_TWLH_NS |
0.12188 |
| MEM_TWLS_NS |
0.12188 |
| MEM_TRFC_DLR_NS |
0.0 |
| MEM_TRRD_DLR_NS |
0.0 |
| MEM_TFAW_DLR_NS |
0.0 |
| MEM_TCCD_DLR_NS |
0.0 |
| MEM_TXP_NS |
6.0 |
| MEM_TXS_NS |
270.0 |
| MEM_TXS_DLL_NS |
959.9997 |
| MEM_TCPDED_NS |
3.75 |
| MEM_TMOD_NS |
22.49999 |
| MEM_TZQCS_NS |
119.99996 |
| MEM_TZQINIT_CYC |
1024.0 |
| MEM_TZQOPER_CYC |
512.0 |
| JEDEC_OVERRIDE_TABLE_PARAM_NAME |
MEM_TCCD_L_NS,MEM_TCCD_S_NS,MEM_TRRD_L_NS,MEM_TRRD_S_NS,MEM_TRCD_NS,MEM_TRP_NS,MEM_TWTR_L_NS,MEM_TWTR_S_NS,MEM_TCKSRE_NS,MEM_TCKSRX_NS,MEM_TCKE_NS,MEM_TRC_NS,MEM_TCKESR_CYC |
| EX_DESIGN_HDL_FORMAT |
VERILOG |
| EX_DESIGN_GEN_SYNTH |
true |
| EX_DESIGN_GEN_SIM |
true |
| EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN |
true |
| EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ |
200.0 |
| EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ |
100.0 |
| EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ |
100 |
| EX_DESIGN_TG_CSR_ACCESS_MODE |
JTAG |
| EX_DESIGN_TG_PROGRAM |
MEDIUM |
| EX_DESIGN_PMON_CH0_EN |
false |
| PHY_TERM_X_R_S_AC_OUTPUT_OHM |
SERIES_34_OHM_CAL |
| PHY_TERM_X_R_S_CK_OUTPUT_OHM |
SERIES_34_OHM_CAL |
| PHY_TERM_X_R_S_DQ_OUTPUT_OHM |
SERIES_34_OHM_CAL |
| PHY_TERM_X_DQ_SLEW_RATE |
FASTEST |
| PHY_TERM_X_R_T_DQ_INPUT_OHM |
RT_50_OHM_CAL |
| PHY_TERM_X_DQ_VREF |
68.3 |
| PHY_TERM_X_R_T_REFCLK_INPUT_OHM |
RT_DIFF |
| MEM_ODT_DQ_X_TGT_WR |
4 |
| MEM_ODT_DQ_X_NON_TGT_WR |
off |
| MEM_ODT_DQ_X_NON_TGT_RD |
off |
| MEM_ODT_DQ_X_RON |
7 |
| MEM_VREF_DQ_X_RANGE |
2 |
| MEM_VREF_DQ_X_VALUE |
67.75 |
| ANALOG_PARAM_DERIVATION_PARAM_NAME |
|
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |