nios_system

2024.08.01.14:16:54 Datasheet
Overview
Processor
   niosv_g Bantam Lake 2.2.0
All Components
   audio AUDIO_IF 1.0
   audio_i2c i2c_opencores 12.0
   jtag_uart altera_avalon_jtag_uart 19.2.4
   mm_bridge_peripheral altera_avalon_mm_bridge 20.1.0
   niosv_g intel_niosv_g 2.2.0
   onchip_memory intel_onchip_memory 1.4.8
   pio_key altera_avalon_pio 19.2.3
   pio_led altera_avalon_pio 19.2.3
   pio_sw altera_avalon_pio 19.2.3
   seg7 SEG7_IF 1.0
   sysid_qsys altera_avalon_sysid_qsys 19.1.6
Memory Map
mm_bridge_peripheral niosv_g
 m0  instruction_manager  data_manager
  audio
avalon_slave  0x0000_0020 - 0x0000_003f 0x0008_0020 - 0x0008_003f
  audio_i2c
avalon_slave_0  0x0000_0000 - 0x0000_001f 0x0008_0000 - 0x0008_001f
  emif_ph2
s0_axi4  0x8000_0000 - 0xbfff_ffff
s0_axil  0x1000_0000 - 0x17ff_ffff
  jtag_uart
avalon_jtag_slave  0x0000_0098 - 0x0000_009f 0x0008_0098 - 0x0008_009f
  mm_bridge_peripheral
s0  0x0008_0000 - 0x000b_ffff
  niosv_g
timer_sw_agent  0x0001_0000 - 0x0001_003f
dm_agent  0x0000_0000 - 0x0000_ffff 0x0000_0000 - 0x0000_ffff
  onchip_memory
s1  0x0010_0000 - 0x0017_ffff 0x0010_0000 - 0x0017_ffff
  pio_key
s1  0x0000_0060 - 0x0000_006f 0x0008_0060 - 0x0008_006f
  pio_led
s1  0x0000_0070 - 0x0000_007f 0x0008_0070 - 0x0008_007f
  pio_sw
s1  0x0000_0080 - 0x0000_008f 0x0008_0080 - 0x0008_008f
  seg7
avalon_slave  0x0000_0040 - 0x0000_005f 0x0008_0040 - 0x0008_005f
  sysid_qsys
control_slave  0x0000_0090 - 0x0000_0097 0x0008_0090 - 0x0008_0097

audio

AUDIO_IF v1.0
mm_bridge_peripheral m0   audio
  avalon_slave
pll_audio outclk0  
  clock_sink
reset_bridge out_reset  
  clock_sink_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

audio_i2c

i2c_opencores v12.0
mm_bridge_peripheral m0   audio_i2c
  avalon_slave_0
iopll outclk0  
  clock
niosv_g platform_irq_rx  
  interrupt_sender
reset_bridge out_reset  
  clock_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_ph2

emif_ph2 v6.2.0
niosv_g data_manager   emif_ph2
  s0_axi4
data_manager  
  s0_axil
iopll outclk0  
  s0_axil_clk
outclk0  
  usr_async_clk_0
reset_release ninit_done  
  core_init_n_0
reset_bridge out_reset  
  s0_axil_rst_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll

altera_iopll v19.3.1
clock_in out_clk   iopll
  refclk
reset_bridge out_reset  
  reset
outclk0   pio_sw
  clk
outclk0   jtag_uart
  clk
outclk0   sysid_qsys
  clk
outclk0   niosv_g
  clk
outclk0   mm_bridge_peripheral
  clk
outclk0   pio_led
  clk
outclk0   pio_key
  clk
outclk0   onchip_memory
  clk1
outclk0   audio_i2c
  clock
outclk0   seg7
  clock_sink
outclk0   emif_ph2
  s0_axil_clk
outclk0  
  usr_async_clk_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.2.4
mm_bridge_peripheral m0   jtag_uart
  avalon_jtag_slave
iopll outclk0  
  clk
niosv_g platform_irq_rx  
  irq
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

mm_bridge_peripheral

altera_avalon_mm_bridge v20.1.0
niosv_g data_manager   mm_bridge_peripheral
  s0
iopll outclk0  
  clk
reset_bridge out_reset  
  reset
m0   jtag_uart
  avalon_jtag_slave
m0   seg7
  avalon_slave
m0   audio
  avalon_slave
m0   audio_i2c
  avalon_slave_0
m0   sysid_qsys
  control_slave
m0   pio_sw
  s1
m0   pio_led
  s1
m0   pio_key
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_g

intel_niosv_g v2.2.0
iopll outclk0   niosv_g
  clk
reset_bridge out_reset  
  reset
data_manager   mm_bridge_peripheral
  s0
data_manager   emif_ph2
  s0_axi4
data_manager  
  s0_axil
data_manager   onchip_memory
  s1
instruction_manager  
  s1
platform_irq_rx   audio_i2c
  interrupt_sender
platform_irq_rx   pio_sw
  irq
platform_irq_rx   jtag_uart
  irq
platform_irq_rx   pio_key
  irq


Parameters

generateLegacySim false
  

Software Assignments

CPU_FREQ 100000000u
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 4096
HAS_CSR_SUPPORT 1
HAS_DEBUG_STUB
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INST_ADDR_WIDTH 32
MTIME_OFFSET 0x00010000
NIOSV_CORE_VARIANT 3
NUM_GPR 32
RESET_ADDR 0x00100000
TICKS_PER_SEC no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE 2

onchip_memory

intel_onchip_memory v1.4.8
niosv_g data_manager   onchip_memory
  s1
instruction_manager  
  s1
iopll outclk0  
  clk1
reset_bridge out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE onchip_memory_onchip_memory
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

pio_key

altera_avalon_pio v19.2.3
mm_bridge_peripheral m0   pio_key
  s1
iopll outclk0  
  clk
niosv_g platform_irq_rx  
  irq
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 4
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

pio_led

altera_avalon_pio v19.2.3
mm_bridge_peripheral m0   pio_led
  s1
iopll outclk0  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 10
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_sw

altera_avalon_pio v19.2.3
mm_bridge_peripheral m0   pio_sw
  s1
iopll outclk0  
  clk
niosv_g platform_irq_rx  
  irq
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 10
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

pll_audio

altera_iopll v19.3.1
clock_in out_clk   pll_audio
  refclk
reset_bridge out_reset  
  reset
outclk0   audio
  clock_sink


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_bridge

altera_reset_bridge v19.2.0
clock_in out_clk   reset_bridge
  clk
reset_release ninit_done  
  in_reset
reset_in out_reset  
  in_reset
out_reset   audio_i2c
  clock_reset
out_reset   seg7
  clock_sink_reset
out_reset   audio
  clock_sink_reset
out_reset   iopll
  reset
out_reset   niosv_g
  reset
out_reset   sysid_qsys
  reset
out_reset   jtag_uart
  reset
out_reset   pio_sw
  reset
out_reset   mm_bridge_peripheral
  reset
out_reset   pll_audio
  reset
out_reset   pio_led
  reset
out_reset   pio_key
  reset
out_reset   onchip_memory
  reset1
out_reset   emif_ph2
  s0_axil_rst_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   reset_bridge
  in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_release

intel_user_rst_clkgate v1.0.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

seg7

SEG7_IF v1.0
mm_bridge_peripheral m0   seg7
  avalon_slave
iopll outclk0  
  clock_sink
reset_bridge out_reset  
  clock_sink_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid_qsys

altera_avalon_sysid_qsys v19.1.6
mm_bridge_peripheral m0   sysid_qsys
  control_slave
iopll outclk0  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0
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