number_of_multipliers |
3 |
width_a |
8 |
width_b |
17 |
width_result |
27 |
gui_4th_asynchronous_clear |
false |
gui_associated_clock_enable |
false |
gui_output_register |
true |
gui_output_register_clock |
CLOCK0 |
gui_output_register_aclr |
NONE |
gui_output_register_sclr |
NONE |
gui_multiplier1_direction |
ADD |
gui_multiplier3_direction |
ADD |
gui_use_subnadd |
false |
gui_representation_a |
UNSIGNED |
gui_representation_b |
SIGNED |
gui_input_register_a |
true |
gui_input_register_a_clock |
CLOCK0 |
gui_input_register_a_aclr |
NONE |
gui_input_register_a_sclr |
NONE |
gui_input_register_b |
true |
gui_input_register_b_clock |
CLOCK0 |
gui_input_register_b_aclr |
NONE |
gui_input_register_b_sclr |
NONE |
gui_multiplier_a_input |
Multiplier input |
gui_multiplier_b_input |
Multiplier input |
gui_multiplier_register |
false |
preadder_mode |
SIMPLE |
gui_preadder_direction |
ADD |
width_c |
16 |
gui_datac_input_register |
false |
width_coef |
18 |
gui_coef_register |
false |
coef0_0 |
0 |
coef0_1 |
0 |
coef0_2 |
0 |
coef0_3 |
0 |
coef0_4 |
0 |
coef0_5 |
0 |
coef0_6 |
0 |
coef0_7 |
0 |
coef1_0 |
0 |
coef1_1 |
0 |
coef1_2 |
0 |
coef1_3 |
0 |
coef1_4 |
0 |
coef1_5 |
0 |
coef1_6 |
0 |
coef1_7 |
0 |
coef2_0 |
0 |
coef2_1 |
0 |
coef2_2 |
0 |
coef2_3 |
0 |
coef2_4 |
0 |
coef2_5 |
0 |
coef2_6 |
0 |
coef2_7 |
0 |
coef3_0 |
0 |
coef3_1 |
0 |
coef3_2 |
0 |
coef3_3 |
0 |
coef3_4 |
0 |
coef3_5 |
0 |
coef3_6 |
0 |
coef3_7 |
0 |
accumulator |
NO |
accum_direction |
ADD |
gui_ena_preload_const |
false |
gui_accumulate_port_select |
0 |
loadconst_value |
64 |
gui_accum_sload_register |
false |
gui_double_accum |
false |
chainout_adder |
NO |
chainout_adder_direction |
ADD |
port_negate |
PORT_UNUSED |
negate_register |
UNREGISTERED |
negate_aclr |
NONE |
negate_sclr |
NONE |
gui_systolic_delay |
false |
gui_pipelining |
1 |
latency |
1 |
gui_input_latency_clock |
CLOCK0 |
gui_input_latency_aclr |
ACLR0 |
gui_input_latency_sclr |
NONE |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |