{ "Info" "IDMS_INIT_MSG_DB" "" "Initialized Quartus Message Database" {  } {  } 0 21958 "Initialized Quartus Message Database" 0 0 "Design Software" 0 -1 0 ""}
{ "Info" "0" "" "Analyzing source files" {  } {  } 0 0 "Analyzing source files" 0 0 "0" 0 0 1761622518501 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552549 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552550 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552550 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552550 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552550 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552564 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552564 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552564 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552565 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552565 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552565 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552567 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552567 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552567 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_reset_controller_1924/synth/altera_reset_controller.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552569 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552569 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552578 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552578 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552579 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552579 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552579 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552579 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552580 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552580 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552580 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552580 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552581 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552582 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552582 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552583 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_reset_controller_1924/synth/altera_reset_controller.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552584 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552584 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552650 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552650 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552660 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552663 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552663 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552665 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_reset_controller_1924/synth/altera_reset_controller.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552668 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552668 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552672 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552673 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552673 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552673 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552673 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552674 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552674 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552674 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552675 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552675 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552675 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552677 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552677 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552678 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_reset_controller_1924/synth/altera_reset_controller.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552679 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1761622552680 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/cal_io96b_interface.svh emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv(17) " "Verilog HDL info at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv(17): analyzing included file hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/cal_io96b_interface.svh" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv" 17 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1761622554509 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv(17) " "Verilog HDL info at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv(17): back to file 'hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi.sv" 17 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1761622554510 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_interface.svh emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv(17) " "Verilog HDL info at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv(17): analyzing included file hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_interface.svh" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv" 17 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1761622554700 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv(17) " "Verilog HDL info at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv(17): back to file 'hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i.sv" 17 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1761622554701 ""}
{ "Info" "0" "" "Elaborating from top-level entity \"golden_top\"" {  } {  } 0 0 "Elaborating from top-level entity \"golden_top\"" 0 0 "0" 0 0 1761622555161 ""}
{ "Info" "IVRFX2_USER_LIBRARY_SEARCH_ORDER" "altera_iopll_2000; pll; altera_avalon_pio_1924; dipsw_pio; rst_in; periph_rst_in; jtag_rst_in; altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_sc_fifo_1932; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; altera_reset_controller_1924; altera_jtag_avalon_master_191; hps_f2sdram; altera_avalon_sysid_qsys_1918; sysid; altera_avalon_mm_bridge_2010; pb_cpu_0; led_pio; intel_user_rst_clkgate_101; user_rst_clkgate_0; button_pio; clk_100; intel_sundancemesa_hps_100; intel_sundancemesa_mpfe_100; intel_agilex_5_soc_900; agilex_hps; altera_address_span_extender_1920; ext_hps_f2sdram_master; hps_m; intel_onchip_memory_1410; ocm; f2sdram_adapter_10; f2sdram_adapter; fpga_m; periph_clk; jtag_clk; altera_merlin_master_translator_193; altera_merlin_axi_translator_1981; altera_merlin_master_agent_1940; altera_merlin_axi_slave_ni_19122; altera_avalon_st_pipeline_stage_1930; altera_merlin_router_1921; altera_merlin_traffic_limiter_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1922; altera_merlin_width_adapter_1961; altera_mm_interconnect_1920; altera_merlin_axi_master_ni_19112; altera_merlin_slave_translator_191; altera_merlin_slave_agent_1930; altera_merlin_burst_adapter_1940; altera_irq_mapper_2001; qsys_top; jtag_subsys; hps_subsys; peripheral_subsys; emif_io96b_hps_emif_io96b_hps_400_d2657ri; alt_mem_if_jtag_master_191; emif_io96b_cal_220; emif_io96b_lpddr4_400; emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4; qsys_interface_bridge_10; emif_io96b_hps_emif_io96b_hps_400_d2657ri_refclk_bridge; altera_gpio_core10_ph2_2210; altera_gpio_2300; emif_io96b_hps_emif_io96b_hps_400_d2657ri_refclk_gpio; emif_io96b_hps; altera_ace5lite_cache_coherency_translator_211; qsys_top_ace5lite_cache_coherency_translator_0 " "Library search order is as follows: \"altera_iopll_2000; pll; altera_avalon_pio_1924; dipsw_pio; rst_in; periph_rst_in; jtag_rst_in; altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_sc_fifo_1932; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; altera_reset_controller_1924; altera_jtag_avalon_master_191; hps_f2sdram; altera_avalon_sysid_qsys_1918; sysid; altera_avalon_mm_bridge_2010; pb_cpu_0; led_pio; intel_user_rst_clkgate_101; user_rst_clkgate_0; button_pio; clk_100; intel_sundancemesa_hps_100; intel_sundancemesa_mpfe_100; intel_agilex_5_soc_900; agilex_hps; altera_address_span_extender_1920; ext_hps_f2sdram_master; hps_m; intel_onchip_memory_1410; ocm; f2sdram_adapter_10; f2sdram_adapter; fpga_m; periph_clk; jtag_clk; altera_merlin_master_translator_193; altera_merlin_axi_translator_1981; altera_merlin_master_agent_1940; altera_merlin_axi_slave_ni_19122; altera_avalon_st_pipeline_stage_1930; altera_merlin_router_1921; altera_merlin_traffic_limiter_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1922; altera_merlin_width_adapter_1961; altera_mm_interconnect_1920; altera_merlin_axi_master_ni_19112; altera_merlin_slave_translator_191; altera_merlin_slave_agent_1930; altera_merlin_burst_adapter_1940; altera_irq_mapper_2001; qsys_top; jtag_subsys; hps_subsys; peripheral_subsys; emif_io96b_hps_emif_io96b_hps_400_d2657ri; alt_mem_if_jtag_master_191; emif_io96b_cal_220; emif_io96b_lpddr4_400; emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4; qsys_interface_bridge_10; emif_io96b_hps_emif_io96b_hps_400_d2657ri_refclk_bridge; altera_gpio_core10_ph2_2210; altera_gpio_2300; emif_io96b_hps_emif_io96b_hps_400_d2657ri_refclk_gpio; emif_io96b_hps; altera_ace5lite_cache_coherency_translator_211; qsys_top_ace5lite_cache_coherency_translator_0\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." {  } {  } 0 18235 "Library search order is as follows: \"%1!s!\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." 0 0 "Design Software" 0 -1 1761622555202 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_agilex_config_reset_release_endpoint rtl altera_agilex_config_reset_release_endpoint.vhd(122) " "VHDL info at altera_agilex_config_reset_release_endpoint.vhd(122): executing entity \"altera_agilex_config_reset_release_endpoint\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622558006 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622558006 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index=\"YES\",sld_node_info_internal=203451904)(1,1)(1,3) rtl sld_jtag_endpoint_adapter.vhd(96) " "VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity \"sld_jtag_endpoint_adapter(sld_ir_width=3,sld_auto_instance_index=\"YES\",sld_node_info_internal=203451904)(1,1)(1,3)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 96 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622558009 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1) rtl altera_sld_agent_endpoint.vhd(122) " "VHDL info at altera_sld_agent_endpoint.vhd(122): executing entity \"altera_sld_agent_endpoint(mfr_code=110,type_code=132,version=1,ir_width=3)(1,1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622558010 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=5,receive_width=26,settings=\"\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host \{ \} type_name 0 instance_name 0 psig 9b67919e\}\")(1,155) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=5,receive_width=26,settings=\"\{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance -1 ir_width 3 bridge_agent 0 prefer_host \{ \} type_name 0 instance_name 0 psig 9b67919e\}\")(1,155)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622558010 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v(126) " "Verilog HDL info at fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v(126): extracting RAM for identifier 'mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_sc_fifo_1932/synth/fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_sc_fifo_1932/synth/fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v" 126 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622558023 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v(127) " "Verilog HDL info at fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_sc_fifo_1932/synth/fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/altera_avalon_sc_fifo_1932/synth/fpga_m_altera_avalon_sc_fifo_1932_onpcouq.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622558023 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 fpga_m_channel_adapter_1922_rd56ufy.sv(91) " "Verilog HDL assignment warning at fpga_m_channel_adapter_1922_rd56ufy.sv(91): truncated value with size 8 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/channel_adapter_1922/synth/fpga_m_channel_adapter_1922_rd56ufy.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/fpga_m/channel_adapter_1922/synth/fpga_m_channel_adapter_1922_rd56ufy.sv" 91 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622558035 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v(126) " "Verilog HDL info at hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v(126): extracting RAM for identifier 'mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_sc_fifo_1932/synth/hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_sc_fifo_1932/synth/hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v" 126 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622558038 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v(127) " "Verilog HDL info at hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_sc_fifo_1932/synth/hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/altera_avalon_sc_fifo_1932/synth/hps_f2sdram_altera_avalon_sc_fifo_1932_onpcouq.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622558038 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 hps_f2sdram_channel_adapter_1922_rd56ufy.sv(91) " "Verilog HDL assignment warning at hps_f2sdram_channel_adapter_1922_rd56ufy.sv(91): truncated value with size 8 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/channel_adapter_1922/synth/hps_f2sdram_channel_adapter_1922_rd56ufy.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_f2sdram/channel_adapter_1922/synth/hps_f2sdram_channel_adapter_1922_rd56ufy.sv" 91 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622558041 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem hps_m_altera_avalon_sc_fifo_1932_onpcouq.v(126) " "Verilog HDL info at hps_m_altera_avalon_sc_fifo_1932_onpcouq.v(126): extracting RAM for identifier 'mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_sc_fifo_1932/synth/hps_m_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_sc_fifo_1932/synth/hps_m_altera_avalon_sc_fifo_1932_onpcouq.v" 126 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622558043 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem hps_m_altera_avalon_sc_fifo_1932_onpcouq.v(127) " "Verilog HDL info at hps_m_altera_avalon_sc_fifo_1932_onpcouq.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_sc_fifo_1932/synth/hps_m_altera_avalon_sc_fifo_1932_onpcouq.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/altera_avalon_sc_fifo_1932/synth/hps_m_altera_avalon_sc_fifo_1932_onpcouq.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622558043 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 hps_m_channel_adapter_1922_rd56ufy.sv(91) " "Verilog HDL assignment warning at hps_m_channel_adapter_1922_rd56ufy.sv(91): truncated value with size 8 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/channel_adapter_1922/synth/hps_m_channel_adapter_1922_rd56ufy.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/jtag_subsys/ip/jtag_subsys/hps_m/channel_adapter_1922/synth/hps_m_channel_adapter_1922_rd56ufy.sv" 91 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622558047 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "core_avl_readdata\[7\] io0_emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i_atom_inst_pll.sv(71) " "Net \"core_avl_readdata\[7\]\" does not have a driver at io0_emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i_atom_inst_pll.sv(71)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/io96b_0/io0_emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i_atom_inst_pll.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_lpddr4_400/synth/io96b_0/io0_emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_lpddr4_400_wydhl7i_atom_inst_pll.sv" 71 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622559265 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "comp_to_seq__avl_readdata\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(194) " "Net \"comp_to_seq__avl_readdata\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(194)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 194 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560613 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane0\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(202) " "Net \"periph0_to_seq__avl_readdata_lane0\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(202)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 202 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560613 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane1\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(203) " "Net \"periph0_to_seq__avl_readdata_lane1\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(203)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 203 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560613 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane2\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(204) " "Net \"periph0_to_seq__avl_readdata_lane2\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(204)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 204 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560613 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane3\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(205) " "Net \"periph0_to_seq__avl_readdata_lane3\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(205)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 205 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560620 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane4\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(206) " "Net \"periph0_to_seq__avl_readdata_lane4\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(206)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 206 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560620 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane5\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(207) " "Net \"periph0_to_seq__avl_readdata_lane5\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(207)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 207 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560620 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane6\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(208) " "Net \"periph0_to_seq__avl_readdata_lane6\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(208)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 208 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560620 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane7\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(209) " "Net \"periph0_to_seq__avl_readdata_lane7\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(209)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 209 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560620 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pll0_to_seq__avl_readdata\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(216) " "Net \"pll0_to_seq__avl_readdata\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(216)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 216 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560620 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pll1_to_seq__avl_readdata\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(217) " "Net \"pll1_to_seq__avl_readdata\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(217)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 217 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pll2_to_seq__avl_readdata\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(218) " "Net \"pll2_to_seq__avl_readdata\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(218)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 218 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_ckgen\[31\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(225) " "Net \"periph0_to_seq__avl_readdata_ckgen\[31\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(225)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 225 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__phy_clk emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(226) " "Net \"periph0_to_seq__phy_clk\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(226)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 226 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__phy_clksync emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(227) " "Net \"periph0_to_seq__phy_clksync\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(227)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 227 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph1_to_seq__phy_clk emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(228) " "Net \"periph1_to_seq__phy_clk\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(228)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 228 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph1_to_seq__phy_clksync emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(229) " "Net \"periph1_to_seq__phy_clksync\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(229)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 229 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa0_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(230) " "Net \"periph0_pa0_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(230)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 230 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa1_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(231) " "Net \"periph0_pa1_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(231)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 231 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa2_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(232) " "Net \"periph0_pa2_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(232)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 232 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa3_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(233) " "Net \"periph0_pa3_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(233)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 233 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa4_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(234) " "Net \"periph0_pa4_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(234)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 234 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa5_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(235) " "Net \"periph0_pa5_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(235)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 235 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560621 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa6_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(236) " "Net \"periph0_pa6_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(236)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 236 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560622 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa7_to_seq__rddata\[95\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(237) " "Net \"periph0_pa7_to_seq__rddata\[95\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(237)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 237 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560622 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "cpa_to_fa__lock\[1\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(289) " "Net \"cpa_to_fa__lock\[1\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(289)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 289 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560622 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph_calbus_0_b\[1097\] emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(566) " "Net \"periph_calbus_0_b\[1097\]\" does not have a driver at emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv(566)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_400_d2657ri/synth/ip/emif_io96b_hps_emif_io96b_hps_400_d2657ri/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4/emif_io96b_cal_220/synth/emif_io96b_hps_emif_io96b_hps_400_d2657ri_emif_0_lpddr4_emif_io96b_cal_220_bda2ybi_cal_arch_fp_top.sv" 566 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622560622 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 button_pio_altera_avalon_pio_1924_qjofkqi.v(94) " "Verilog HDL assignment warning at button_pio_altera_avalon_pio_1924_qjofkqi.v(94): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" 94 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560769 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 button_pio_altera_avalon_pio_1924_qjofkqi.v(106) " "Verilog HDL assignment warning at button_pio_altera_avalon_pio_1924_qjofkqi.v(106): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" 106 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560769 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 button_pio_altera_avalon_pio_1924_qjofkqi.v(118) " "Verilog HDL assignment warning at button_pio_altera_avalon_pio_1924_qjofkqi.v(118): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" 118 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560769 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 button_pio_altera_avalon_pio_1924_qjofkqi.v(130) " "Verilog HDL assignment warning at button_pio_altera_avalon_pio_1924_qjofkqi.v(130): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/button_pio/altera_avalon_pio_1924/synth/button_pio_altera_avalon_pio_1924_qjofkqi.v" 130 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560770 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(94) " "Verilog HDL assignment warning at dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(94): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" 94 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560771 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(106) " "Verilog HDL assignment warning at dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(106): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" 106 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560771 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(118) " "Verilog HDL assignment warning at dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(118): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" 118 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560778 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(130) " "Verilog HDL assignment warning at dipsw_pio_altera_avalon_pio_1924_qjofkqi.v(130): truncated value with size 2 to match size of target (1)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/ip/peripheral_subsys/dipsw_pio/altera_avalon_pio_1924/synth/dipsw_pio_altera_avalon_pio_1924_qjofkqi.v" 130 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1761622560778 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_avalon_sc_fifo_1932/synth/peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_avalon_sc_fifo_1932/synth/peripheral_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622560808 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(107) " "Verilog HDL warning at peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(107): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" 107 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622560828 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(114) " "Verilog HDL warning at peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(114): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" 114 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622560828 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(121) " "Verilog HDL warning at peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(121): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" 121 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622560828 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(128) " "Verilog HDL warning at peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv(128): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_demultiplexer_1921/synth/peripheral_subsys_altera_merlin_demultiplexer_1921_uppfuvi.sv" 128 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622560828 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq.sv(365) " "Verilog HDL Case Statement warning at peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq.sv(365): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_multiplexer_1922/synth/peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/peripheral_subsys/peripheral_subsys/altera_merlin_multiplexer_1922/synth/peripheral_subsys_altera_merlin_multiplexer_1922_cbyifnq.sv" 365 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1761622560836 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv(93) " "Verilog HDL warning at qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv(93): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv" 93 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622560925 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv(100) " "Verilog HDL warning at qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv(100): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_xjbh4ri.sv" 100 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622560925 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "qsys_top_altera_merlin_multiplexer_1922_jvnl3ja.sv(331) " "Verilog HDL Case Statement warning at qsys_top_altera_merlin_multiplexer_1922_jvnl3ja.sv(331): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_jvnl3ja.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_jvnl3ja.sv" 331 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1761622560931 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "datachk_array qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(421) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(421): extracting RAM for identifier 'datachk_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" 421 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622560936 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "data_array qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(437) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(437): extracting RAM for identifier 'data_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" 437 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622560937 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "user_data_array qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(438) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(438): extracting RAM for identifier 'user_data_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" 438 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622560937 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "byteen_array qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(439) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv(439): extracting RAM for identifier 'byteen_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_y2c2syq.sv" 439 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622560937 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "qsys_top_altera_merlin_multiplexer_1922_2nczl5y.sv(307) " "Verilog HDL Case Statement warning at qsys_top_altera_merlin_multiplexer_1922_2nczl5y.sv(307): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_2nczl5y.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_2nczl5y.sv" 307 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1761622561102 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "qsys_top_altera_merlin_multiplexer_1922_55m6siq.sv(331) " "Verilog HDL Case Statement warning at qsys_top_altera_merlin_multiplexer_1922_55m6siq.sv(331): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_55m6siq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_55m6siq.sv" 331 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1761622561110 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "datachk_array qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(421) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(421): extracting RAM for identifier 'datachk_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" 421 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561118 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "data_array qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(437) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(437): extracting RAM for identifier 'data_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" 437 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561119 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "user_data_array qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(438) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(438): extracting RAM for identifier 'user_data_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" 438 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561119 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "byteen_array qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(439) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_yznogci.sv(439): extracting RAM for identifier 'byteen_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_yznogci.sv" 439 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561119 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561221 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv(93) " "Verilog HDL warning at qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv(93): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv" 93 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622561299 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv(100) " "Verilog HDL warning at qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv(100): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_5vdj4hy.sv" 100 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622561301 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "qsys_top_altera_merlin_multiplexer_1922_cfvmo7a.sv(331) " "Verilog HDL Case Statement warning at qsys_top_altera_merlin_multiplexer_1922_cfvmo7a.sv(331): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_cfvmo7a.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_cfvmo7a.sv" 331 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1761622561307 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "datachk_array qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(421) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(421): extracting RAM for identifier 'datachk_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" 421 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561313 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "data_array qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(437) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(437): extracting RAM for identifier 'data_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" 437 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561313 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "user_data_array qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(438) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(438): extracting RAM for identifier 'user_data_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" 438 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561314 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "byteen_array qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(439) " "Verilog HDL info at qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv(439): extracting RAM for identifier 'byteen_array'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_width_adapter_1961/synth/qsys_top_altera_merlin_width_adapter_1961_beuh43a.sv" 439 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561314 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561383 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1761622561391 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "qsys_top_altera_merlin_multiplexer_1922_666s25q.sv(307) " "Verilog HDL Case Statement warning at qsys_top_altera_merlin_multiplexer_1922_666s25q.sv(307): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv" 307 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1761622561417 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv(93) " "Verilog HDL warning at qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv(93): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv" 93 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622561420 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv(100) " "Verilog HDL warning at qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv(100): right shift count is greater than or equal to the width of the value" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv" 100 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1761622561420 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "7 3 led_pio_external_connection_in_port golden_top.v(213) " "Verilog HDL warning at golden_top.v(213): actual bit length 7 differs from formal bit length 3 for port \"led_pio_external_connection_in_port\"" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 213 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1761622561440 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "7 3 led_pio_external_connection_out_port golden_top.v(214) " "Verilog HDL warning at golden_top.v(214): actual bit length 7 differs from formal bit length 3 for port \"led_pio_external_connection_out_port\"" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 214 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1761622561440 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "2 4 button_pio_external_connection_export golden_top.v(216) " "Verilog HDL warning at golden_top.v(216): actual bit length 2 differs from formal bit length 4 for port \"button_pio_external_connection_export\"" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 216 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1761622561440 ""}
{ "Info" "IVRFX2_VRFX_FSM_HAS_UNCLEAN_RESET" "mgr_c_st " "Can't recognize finite state machine \"mgr_c_st\" because it has a complex reset state" {  } {  } 0 13246 "Can't recognize finite state machine \"%1!s!\" because it has a complex reset state" 0 0 "Design Software" 0 -1 1761622568317 ""}
{ "Info" "IVRFX2_VRFX_FSM_HAS_UNCLEAN_RESET" "sub_c_st " "Can't recognize finite state machine \"sub_c_st\" because it has a complex reset state" {  } {  } 0 13246 "Can't recognize finite state machine \"%1!s!\" because it has a complex reset state" 0 0 "Design Software" 0 -1 1761622568318 ""}
{ "Info" "0" "" "Found 462 design entities" {  } {  } 0 0 "Found 462 design entities" 0 0 "0" 0 0 1761622574472 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_CLK golden_top gnd top-level " "Output port \"DRAM_CLK\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 56 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_CLK"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_CKE golden_top gnd top-level " "Output port \"DRAM_CKE\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 57 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_CKE"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_ADDR\[0..12\] golden_top gnd top-level " "Output port \"DRAM_ADDR\[0..12\]\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 58 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_ADDR[12]"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_BA\[0..1\] golden_top gnd top-level " "Output port \"DRAM_BA\[0..1\]\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 59 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_BA[1]"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_LDQM golden_top gnd top-level " "Output port \"DRAM_LDQM\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 61 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_LDQM"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_UDQM golden_top gnd top-level " "Output port \"DRAM_UDQM\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 62 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_UDQM"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_CS_n\[0..1\] golden_top gnd top-level " "Output port \"DRAM_CS_n\[0..1\]\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 63 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_CS_n[1]"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_WE_n golden_top gnd top-level " "Output port \"DRAM_WE_n\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 64 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577157 "DRAM_WE_n"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_CAS_n golden_top gnd top-level " "Output port \"DRAM_CAS_n\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 65 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577171 "DRAM_CAS_n"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "DRAM_RAS_n golden_top gnd top-level " "Output port \"DRAM_RAS_n\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 66 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577171 "DRAM_RAS_n"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "HDMI_TX_CLK golden_top gnd top-level " "Output port \"HDMI_TX_CLK\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 104 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577171 "HDMI_TX_CLK"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "HDMI_TX_HS golden_top gnd top-level " "Output port \"HDMI_TX_HS\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 105 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577171 "HDMI_TX_HS"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "HDMI_TX_VS golden_top gnd top-level " "Output port \"HDMI_TX_VS\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 106 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577171 "HDMI_TX_VS"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "HDMI_TX_D\[0..23\] golden_top gnd top-level " "Output port \"HDMI_TX_D\[0..23\]\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 107 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577171 "HDMI_TX_D[23]"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "HDMI_TX_DE golden_top gnd top-level " "Output port \"HDMI_TX_DE\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 108 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577172 "HDMI_TX_DE"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "FPGA_UART_TX golden_top gnd top-level " "Output port \"FPGA_UART_TX\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 127 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577172 "FPGA_UART_TX"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "ADC_SCK golden_top gnd top-level " "Output port \"ADC_SCK\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 131 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577172 "ADC_SCK"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "ADC_SDI golden_top gnd top-level " "Output port \"ADC_SDI\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 133 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577172 "ADC_SDI"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "ADC_CS_n golden_top gnd top-level " "Output port \"ADC_CS_n\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/golden_top.v" 134 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1761622577172 "ADC_CS_n"}
{ "Info" "0" "" "There are 679 partitions after elaboration." {  } {  } 0 0 "There are 679 partitions after elaboration." 0 0 "0" 0 0 1761622577683 ""}
{ "Info" "" "Running rule checking for Agilex5 protocol IPs... " "Running rule checking for Agilex5 protocol IPs..." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1761622580894 ""}
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab_0 " "Starting IP generation for the debug fabric: alt_sld_fab_0." {  } {  } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Design Software" 0 -1 1761622581758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581814 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Quartus is a registered trademark of Intel Corporation in the " "Quartus is a registered trademark of Intel Corporation in the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "US and other countries.  Portions of the Quartus Prime software " "US and other countries.  Portions of the Quartus Prime software" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Code, and other portions of the code included in this download " "Code, and other portions of the code included in this download" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Or on this DVD, are licensed to Intel Corporation and are the " "Or on this DVD, are licensed to Intel Corporation and are the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Copyrighted property of third parties. For license details, " "Copyrighted property of third parties. For license details," {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Refer to the End User License Agreement at " "Refer to the End User License Agreement at" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Http://fpgasoftware.intel.com/eula. " "Http://fpgasoftware.intel.com/eula." {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622581815 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777 " "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600852 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600868 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 splitter.clock_1 clock " "Add_connection sldfabric.clock_0 splitter.clock_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 splitter.node_1 conduit " "Add_connection sldfabric.node_0 splitter.node_1 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_2 clock " "Add_connection sldfabric.clock_1 splitter.clock_2 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_2 conduit " "Add_connection sldfabric.node_1 splitter.node_2 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622600869 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777 " "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601763 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601778 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601778 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601778 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601778 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 splitter.clock_1 clock " "Add_connection sldfabric.clock_0 splitter.clock_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 splitter.node_1 conduit " "Add_connection sldfabric.node_0 splitter.node_1 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_2 clock " "Add_connection sldfabric.clock_1 splitter.clock_2 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_2 conduit " "Add_connection sldfabric.node_1 splitter.node_2 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601779 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601874 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Deploying alt_sld_fab_0 to D:\\DE25-Nano\\revB\\Sunshine\\GHRD\\dni\\sandboxes\\DESKTOP-N9Q81IJ_15528_0\\sld\\ipgen\\alt_sld_fab_0.ip " "Deploying alt_sld_fab_0 to D:\\DE25-Nano\\revB\\Sunshine\\GHRD\\dni\\sandboxes\\DESKTOP-N9Q81IJ_15528_0\\sld\\ipgen\\alt_sld_fab_0.ip" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622601875 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Quartus is a registered trademark of Intel Corporation in the " "Quartus is a registered trademark of Intel Corporation in the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "US and other countries.  Portions of the Quartus Prime software " "US and other countries.  Portions of the Quartus Prime software" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Code, and other portions of the code included in this download " "Code, and other portions of the code included in this download" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Or on this DVD, are licensed to Intel Corporation and are the " "Or on this DVD, are licensed to Intel Corporation and are the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Copyrighted property of third parties. For license details, " "Copyrighted property of third parties. For license details," {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Refer to the End User License Agreement at " "Refer to the End User License Agreement at" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Http://fpgasoftware.intel.com/eula. " "Http://fpgasoftware.intel.com/eula." {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622603364 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625081 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777 " "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625083 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625090 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625090 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625090 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625091 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625091 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625091 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625091 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625091 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625091 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 splitter.clock_1 clock " "Add_connection sldfabric.clock_0 splitter.clock_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 splitter.node_1 conduit " "Add_connection sldfabric.node_0 splitter.node_1 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_2 clock " "Add_connection sldfabric.clock_1 splitter.clock_2 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_2 conduit " "Add_connection sldfabric.node_1 splitter.node_2 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625092 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625957 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625958 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777 " "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625958 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625973 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625973 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625973 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625973 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 splitter.clock_1 clock " "Add_connection sldfabric.clock_0 splitter.clock_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 splitter.node_1 conduit " "Add_connection sldfabric.node_0 splitter.node_1 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_2 clock " "Add_connection sldfabric.clock_1 splitter.clock_2 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625974 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_2 conduit " "Add_connection sldfabric.node_1 splitter.node_2 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625975 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625975 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625976 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625976 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625976 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625976 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622625976 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Saving generation log to D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt " "Saving generation log to D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626133 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Generated by version: 25.1.1 build 125 " "Generated by version: 25.1.1 build 125" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626156 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Starting: Create HDL design files for synthesis " "Starting: Create HDL design files for synthesis" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626156 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Qsys-generate D:\\DE25-Nano\\revB\\Sunshine\\GHRD\\dni\\sandboxes\\DESKTOP-N9Q81IJ_15528_0\\sld\\ipgen\\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\\DE25-Nano\\revB\\Sunshine\\GHRD\\dni\\sandboxes\\DESKTOP-N9Q81IJ_15528_0\\sld\\ipgen\\alt_sld_fab_0 --family=\"Agilex 5\" --part=A5EB013BB23BE4SCS " "Qsys-generate D:\\DE25-Nano\\revB\\Sunshine\\GHRD\\dni\\sandboxes\\DESKTOP-N9Q81IJ_15528_0\\sld\\ipgen\\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\\DE25-Nano\\revB\\Sunshine\\GHRD\\dni\\sandboxes\\DESKTOP-N9Q81IJ_15528_0\\sld\\ipgen\\alt_sld_fab_0 --family=\"Agilex 5\" --part=A5EB013BB23BE4SCS" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626156 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777 " "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626964 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 splitter.clock_1 clock " "Add_connection sldfabric.clock_0 splitter.clock_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 splitter.node_1 conduit " "Add_connection sldfabric.node_0 splitter.node_1 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626980 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_2 clock " "Add_connection sldfabric.clock_1 splitter.clock_2 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_2 conduit " "Add_connection sldfabric.node_1 splitter.node_2 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622626981 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627096 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627097 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777 " "Set_instance_parameter_value ident DESIGN_HASH 7bd008b4d4bf4bc62777" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627097 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627114 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627116 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627116 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627116 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627119 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627119 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627119 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 1 " "Set_instance_parameter_value agilexconfigreset COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627119 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_1\} \} moduleassign \{debug.virtualInterface.link_1 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_2\} \} moduleassign \{debug.virtualInterface.link_2 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 3 23\} \{irq irq out 1 1\} \{ir_out ir_out out 3 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 3\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627120 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 splitter.clock_1 clock " "Add_connection sldfabric.clock_0 splitter.clock_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 splitter.node_1 conduit " "Add_connection sldfabric.node_0 splitter.node_1 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_2 clock " "Add_connection sldfabric.clock_1 splitter.clock_2 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_2 conduit " "Add_connection sldfabric.node_1 splitter.node_2 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 2 ir_width 3 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627121 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627234 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Transforming system: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Transforming system: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627321 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Naming system components in system: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Naming system components in system: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627441 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Processing generation queue\" " "Alt_sld_fab_0: \"Processing generation queue\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627441 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627441 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627473 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_1920_savqngi\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_1920_savqngi\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627488 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_splitter_1920_2duqtxq\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_splitter_1920_2duqtxq\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627630 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: altera_jtag_wys_atom\" " "Alt_sld_fab_0: \"Generating: altera_jtag_wys_atom\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627646 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627676 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_ck46dgq\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_ck46dgq\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627723 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_ku24h5y\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_ku24h5y\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627723 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Conf_reset_src: \"Generating: conf_reset_src\" " "Conf_reset_src: \"Generating: conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627723 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Grounded_conf_reset_src: \"Generating: grounded_conf_reset_src\" " "Grounded_conf_reset_src: \"Generating: grounded_conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627723 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_cpztvzi\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_cpztvzi\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627723 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: conf_reset_src\" " "Alt_sld_fab_0: \"Generating: conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627742 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: grounded_conf_reset_src\" " "Alt_sld_fab_0: \"Generating: grounded_conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627754 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_for_debug\" " "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_for_debug\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627765 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_to_debug_logic\" " "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_to_debug_logic\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627801 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: Done \"alt_sld_fab_0\" with 13 modules, 14 files " "Alt_sld_fab_0: Done \"alt_sld_fab_0\" with 13 modules, 14 files" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627802 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Finished: Create HDL design files for synthesis " "Finished: Create HDL design files for synthesis" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627867 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Generation of D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 1777 ms " "Generation of D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 1777 ms" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1761622627867 ""}
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab_0 " "Finished IP generation for the debug fabric: alt_sld_fab_0." {  } {  } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Design Software" 0 -1 1761622628596 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000010000001101110000000100000110000100000011011100000000100001100001000000110111000000000\",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(1,0)(1,96) rtl alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd(13) " "VHDL info at alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd(13): executing entity \"alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000010000001101110000000100000110000100000011011100000000100001100001000000110111000000000\",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(1,0)(1,96)\" with architecture \"rtl\"" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd" 13 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622630931 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_hub(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000010000001101110000000100000110000100000011011100000000100001100001000000110111000000000\",force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(95,0) rtl sld_jtag_hub.vhd(89) " "VHDL info at sld_jtag_hub.vhd(89): executing entity \"sld_jtag_hub(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000010000001101110000000100000110000100000011011100000000100001100001000000110111000000000\",force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(95,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 89 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622630933 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_shadow_jsm(ip_major_version=1,ip_minor_version=5) rtl sld_hub.vhd(1554) " "VHDL info at sld_hub.vhd(1554): executing entity \"sld_shadow_jsm(ip_major_version=1,ip_minor_version=5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_hub.vhd" 1554 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622630934 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_rom_sr(n_bits=128) INFO_REG sld_rom_sr.vhd(5) " "VHDL info at sld_rom_sr.vhd(5): executing entity \"sld_rom_sr(n_bits=128)\" with architecture \"INFO_REG\"" {  } { { "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera_pro/25.1.1/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1761622630935 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ir_in_2d\[3\]\[4\] alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd(283) " "Net \"ir_in_2d\[3\]\[4\]\" does not have a driver at alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd(283)" {  } { { "D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd" "" { Text "D:/DE25-Nano/revB/Sunshine/GHRD/dni/sandboxes/DESKTOP-N9Q81IJ_15528_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_mkoj4fi.vhd" 283 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1761622630943 ""}
{ "Info" "0" "" "DA report generation in native DNI mode" {  } {  } 0 0 "DA report generation in native DNI mode" 0 0 "0" 0 0 1761622664402 ""}
{ "Info" "IDRC_START_RUN_DA_DRC" "partitioned " "Running Design Assistant Rules for snapshot 'partitioned'" {  } {  } 0 21615 "Running Design Assistant Rules for snapshot '%1!s!'" 0 0 "Design Software" 0 -1 1761622664409 ""}
{ "Info" "" "" "No waiver waived any violations" {  } {  } 0 0 "No waiver waived any violations" 0 0 "Design Software" 0 -1 1761622665054 ""}
{ "Info" "IDRC_PASSED_RULES_RESULT" "28 29 partitioned  1 " "Design Assistant Results: 28 of 29 enabled rules passed, and 1 rules was disabled, in snapshot 'partitioned'" {  } {  } 0 22360 "Design Assistant Results: %1!d! of %2!d! enabled rules passed, and %5!d! rules was disabled, in snapshot '%3!s!'%4!s!" 0 0 "Design Software" 0 -1 1761622665054 ""}
{ "Info" "IDRC_NO_CRITICAL_WARN_SEVERITY_RESULT" "0 19 Critical partitioned  " "Design Assistant Results: 0 of 19 Critical severity rules issued violations in snapshot 'partitioned'" {  } {  } 0 21660 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1761622665054 ""}
{ "Info" "IDRC_NO_WARN_SEVERITY_RESULT" "0 1 High partitioned  " "Design Assistant Results: 0 of 1 High severity rules issued violations in snapshot 'partitioned'" {  } {  } 0 21661 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1761622665054 ""}
{ "Info" "IDRC_MEDIUM_SEVERITY_RESULT" "0 1 Medium partitioned  " "Design Assistant Results: 0 of 1 Medium severity rules issued violations in snapshot 'partitioned'" {  } {  } 0 21621 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1761622665055 ""}
{ 