vvp_system

2025.08.27.09:39:26 Datasheet
Overview

All Components
   intel_vvp_demosaic intel_vvp_demosaic 24.4.1
   intel_vvp_pip_conv_4to1 intel_vvp_pip_conv 24.5.1
   intel_vvp_switch intel_vvp_switch 24.4.1
   intel_vvp_tpg_1 intel_vvp_tpg 24.5.1
   intel_vvp_vfb intel_vvp_vfb 24.5.1
   mm_bridge_control altera_avalon_mm_bridge 20.1.0
Memory Map
intel_vvp_vfb mm_bridge_control
 av_mm_mem_write_host  av_mm_mem_read_host  m0
  emif_io96b_lpddr4a
s0_axi4  0x0000_0000 - 0x3fff_ffff 0x0000_0000 - 0x3fff_ffff
s0_axi4lite 
  intel_vvp_demosaic
av_mm_control_agent  0x0000 - 0x01ff
  intel_vvp_pip_conv_4to1
av_mm_control_agent  0x0400 - 0x05ff
  intel_vvp_switch
av_mm_control_agent  0x0800 - 0x09ff
  intel_vvp_tpg_1
av_mm_control_agent  0x0200 - 0x03ff
  intel_vvp_vfb
av_mm_control_agent  0x0600 - 0x07ff
  mm_bridge_control
s0 

clock_in_control

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_in_csi2

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_in_hdmi

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_in_mem

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_in_vid

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_io96b_lpddr4a

emif_io96b_lpddr4 v4.0.0
intel_vvp_vfb av_mm_mem_read_host   emif_io96b_lpddr4a
  s0_axi4
av_mm_mem_write_host  
  s0_axi4
clock_in_mem out_clk  
  s0_axi4_clock_in
out_clk  
  s0_axi4lite_clock
reset_in out_reset  
  core_init_n
out_reset  
  s0_axi4lite_reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_cvo

intel_vvp_cvo v24.4.1
intel_vvp_vfb axi4s_vid_out   intel_vvp_cvo
  axi4s_vid_in
clock_in_hdmi out_clk  
  fr_clock
clock_in_vid out_clk  
  vid_clock
reset_in out_reset  
  fr_reset
out_reset  
  vid_reset
reset_in_vvp out_reset  
  fr_reset
out_reset  
  vid_reset
axi4s_fr_vid_out   intel_vvp_fr2cv
  axi4s_fr_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_demosaic

intel_vvp_demosaic v24.4.1
mm_bridge_control m0   intel_vvp_demosaic
  av_mm_control_agent
clock_in_control out_clk  
  agent_clock
clock_in_csi2 out_clk  
  main_clock
reset_in out_reset  
  agent_reset
out_reset  
  main_reset
reset_in_vvp out_reset  
  main_reset
axi4s_vid_out   intel_vvp_switch
  axi4s_vid_in_1


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_fr2cv

intel_vvp_fr2cv v24.3.1
intel_vvp_cvo axi4s_fr_vid_out   intel_vvp_fr2cv
  axi4s_fr_vid_in
clock_in_hdmi out_clk  
  vid_clock
reset_in_vvp out_reset  
  vid_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_pip_conv_4to1

intel_vvp_pip_conv v24.5.1
mm_bridge_control m0   intel_vvp_pip_conv_4to1
  av_mm_control_agent
intel_vvp_pixel_adapter axi4s_vid_out  
  axi4s_vid_in
clock_in_control out_clk  
  agent_clock
clock_in_csi2 out_clk  
  in_clock
clock_in_vid out_clk  
  out_clock
reset_in out_reset  
  agent_reset
out_reset  
  in_reset
out_reset  
  out_reset
reset_in_vvp out_reset  
  in_reset
out_reset  
  out_reset
axi4s_vid_out   intel_vvp_vfb
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_pixel_adapter

intel_vvp_pixel_adapter v24.6.1
intel_vvp_switch axi4s_vid_out_0   intel_vvp_pixel_adapter
  axi4s_vid_in
clock_in_csi2 out_clk  
  main_clock
reset_in out_reset  
  main_reset
reset_in_vvp out_reset  
  main_reset
axi4s_vid_out   intel_vvp_pip_conv_4to1
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_switch

intel_vvp_switch v24.4.1
mm_bridge_control m0   intel_vvp_switch
  av_mm_control_agent
intel_vvp_tpg axi4s_vid_out  
  axi4s_vid_in_0
intel_vvp_demosaic axi4s_vid_out  
  axi4s_vid_in_1
intel_vvp_tpg_1 axi4s_vid_out  
  axi4s_vid_in_2
clock_in_control out_clk  
  agent_clock
clock_in_csi2 out_clk  
  main_clock
reset_in out_reset  
  agent_reset
out_reset  
  main_reset
axi4s_vid_out_0   intel_vvp_pixel_adapter
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_tpg

intel_vvp_tpg v24.5.1
clock_in_csi2 out_clk   intel_vvp_tpg
  main_clock
reset_in out_reset  
  main_reset
axi4s_vid_out   intel_vvp_switch
  axi4s_vid_in_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_tpg_1

intel_vvp_tpg v24.5.1
mm_bridge_control m0   intel_vvp_tpg_1
  av_mm_control_agent
clock_in_control out_clk  
  agent_clock
clock_in_csi2 out_clk  
  main_clock
reset_in out_reset  
  agent_reset
out_reset  
  main_reset
axi4s_vid_out   intel_vvp_switch
  axi4s_vid_in_2


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_vfb

intel_vvp_vfb v24.5.1
mm_bridge_control m0   intel_vvp_vfb
  av_mm_control_agent
intel_vvp_pip_conv_4to1 axi4s_vid_out  
  axi4s_vid_in
clock_in_control out_clk  
  control_clock
clock_in_vid out_clk  
  main_clock
clock_in_mem out_clk  
  mem_clock
reset_in out_reset  
  control_reset
out_reset  
  main_reset
out_reset  
  mem_reset
reset_in_vvp out_reset  
  main_reset
out_reset  
  mem_reset
av_mm_mem_read_host   emif_io96b_lpddr4a
  s0_axi4
av_mm_mem_write_host  
  s0_axi4
axi4s_vid_out   intel_vvp_cvo
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_control

altera_avalon_mm_bridge v20.1.0
clock_in_control out_clk   mm_bridge_control
  clk
reset_in out_reset  
  reset
m0   intel_vvp_switch
  av_mm_control_agent
m0   intel_vvp_vfb
  av_mm_control_agent
m0   intel_vvp_pip_conv_4to1
  av_mm_control_agent
m0   intel_vvp_tpg_1
  av_mm_control_agent
m0   intel_vvp_demosaic
  av_mm_control_agent


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in_vid out_clk   reset_in
  clk
out_reset   intel_vvp_switch
  agent_reset
out_reset  
  main_reset
out_reset   intel_vvp_pip_conv_4to1
  agent_reset
out_reset  
  in_reset
out_reset  
  out_reset
out_reset   intel_vvp_tpg_1
  agent_reset
out_reset  
  main_reset
out_reset   intel_vvp_demosaic
  agent_reset
out_reset  
  main_reset
out_reset   intel_vvp_vfb
  control_reset
out_reset  
  main_reset
out_reset  
  mem_reset
out_reset   emif_io96b_lpddr4a
  core_init_n
out_reset  
  s0_axi4lite_reset_n
out_reset   intel_vvp_cvo
  fr_reset
out_reset  
  vid_reset
out_reset   intel_vvp_tpg
  main_reset
out_reset   intel_vvp_pixel_adapter
  main_reset
out_reset   mm_bridge_control
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in_vvp

altera_reset_bridge v19.2.0
clock_in_vid out_clk   reset_in_vvp
  clk
out_reset   intel_vvp_cvo
  fr_reset
out_reset  
  vid_reset
out_reset   intel_vvp_pip_conv_4to1
  in_reset
out_reset  
  out_reset
out_reset   intel_vvp_vfb
  main_reset
out_reset  
  mem_reset
out_reset   intel_vvp_pixel_adapter
  main_reset
out_reset   intel_vvp_demosaic
  main_reset
out_reset   intel_vvp_fr2cv
  vid_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
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