system

2025.08.27.09:39:24 Datasheet
Overview
Processor
   intel_niosv_g Bantam Lake 4.0.0
All Components
   i2c altera_avalon_i2c 19.2.6
   intel_niosv_g intel_niosv_g 4.0.0
   intel_onchip_memory intel_onchip_memory 1.4.10
   jtag_uart altera_avalon_jtag_uart 19.3.1
   pio_cam_gpio altera_avalon_pio 19.2.4
   pio_hdmi_config_done altera_avalon_pio 19.2.4
   pio_key altera_avalon_pio 19.2.4
   pio_led altera_avalon_pio 19.2.4
   pio_mem_ready altera_avalon_pio 19.2.4
   pio_switch altera_avalon_pio 19.2.4
   pio_vvp_reset_n altera_avalon_pio 19.2.4
   sysid_qsys altera_avalon_sysid_qsys 19.1.8
   timer altera_avalon_timer 19.3.5
   vvp_system vvp_system 1.0
   vvp_system_intel_vvp_demosaic intel_vvp_demosaic 24.4.1
   vvp_system_intel_vvp_pip_conv_4to1 intel_vvp_pip_conv 24.5.1
   vvp_system_intel_vvp_switch intel_vvp_switch 24.4.1
   vvp_system_intel_vvp_tpg_1 intel_vvp_tpg 24.5.1
   vvp_system_intel_vvp_vfb intel_vvp_vfb 24.5.1
   vvp_system_mm_bridge_control altera_avalon_mm_bridge 20.1.0
Memory Map
intel_niosv_g vvp_system_intel_vvp_vfb vvp_system_mm_bridge_control
 instruction_manager  data_manager  av_mm_mem_write_host  av_mm_mem_read_host  m0
  i2c
csr  0x0009_1040 - 0x0009_107f
  intel_niosv_g
timer_sw_agent  0x0009_1000 - 0x0009_103f
dm_agent  0x0008_0000 - 0x0008_ffff 0x0008_0000 - 0x0008_ffff
  intel_onchip_memory
s1  0x0000_0000 - 0x0007_ffff 0x0000_0000 - 0x0007_ffff
  jtag_uart
avalon_jtag_slave  0x0009_1118 - 0x0009_111f
  pio_cam_gpio
s1  0x0009_10a0 - 0x0009_10af
  pio_hdmi_config_done
s1  0x0009_10d0 - 0x0009_10df
  pio_key
s1  0x0009_10e0 - 0x0009_10ef
  pio_led
s1  0x0009_1100 - 0x0009_110f
  pio_mem_ready
s1  0x0009_10c0 - 0x0009_10cf
  pio_switch
s1  0x0009_10f0 - 0x0009_10ff
  pio_vvp_reset_n
s1  0x0009_10b0 - 0x0009_10bf
  sysid_qsys
control_slave  0x0009_1110 - 0x0009_1117
  timer
s1  0x0009_1080 - 0x0009_109f
  vvp_system
mm_bridge_control_s0 
  vvp_system_emif_io96b_lpddr4a
s0_axi4  0x0000_0000 - 0x3fff_ffff 0x0000_0000 - 0x3fff_ffff
s0_axi4lite 
  vvp_system_intel_vvp_demosaic
av_mm_control_agent  0x0009_0000 - 0x0009_01ff 0x0000 - 0x01ff
  vvp_system_intel_vvp_pip_conv_4to1
av_mm_control_agent  0x0009_0400 - 0x0009_05ff 0x0400 - 0x05ff
  vvp_system_intel_vvp_switch
av_mm_control_agent  0x0009_0800 - 0x0009_09ff 0x0800 - 0x09ff
  vvp_system_intel_vvp_tpg_1
av_mm_control_agent  0x0009_0200 - 0x0009_03ff 0x0200 - 0x03ff
  vvp_system_intel_vvp_vfb
av_mm_control_agent  0x0009_0600 - 0x0009_07ff 0x0600 - 0x07ff
  vvp_system_mm_bridge_control
s0  0x0009_0000 - 0x0009_0fff

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

i2c

altera_avalon_i2c v19.2.6
intel_niosv_g data_manager   i2c
  csr
platform_irq_rx  
  interrupt_sender
iopll_sys outclk0  
  clock
reset_in out_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

FIFO_DEPTH 4
FREQ 100000000
USE_AV_ST 0

intel_niosv_g

intel_niosv_g v4.0.0
iopll_sys outclk0   intel_niosv_g
  clk
reset_in out_reset  
  ndm_reset_in
out_reset  
  reset
data_manager   jtag_uart
  avalon_jtag_slave
platform_irq_rx  
  irq
data_manager   sysid_qsys
  control_slave
data_manager   i2c
  csr
platform_irq_rx  
  interrupt_sender
data_manager   vvp_system_mm_bridge_control
  s0
data_manager   intel_onchip_memory
  s1
instruction_manager  
  s1
data_manager   timer
  s1
platform_irq_rx  
  irq
data_manager   pio_led
  s1
data_manager   pio_switch
  s1
data_manager   pio_key
  s1
platform_irq_rx  
  irq
data_manager   pio_hdmi_config_done
  s1
data_manager   pio_mem_ready
  s1
data_manager   pio_vvp_reset_n
  s1
data_manager   pio_cam_gpio
  s1


Parameters

generateLegacySim false
  

Software Assignments

CLIC_EN false
CPU_FREQ 100000000u
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 4096
HAS_CSR_SUPPORT 1
HAS_DEBUG_STUB
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INST_ADDR_WIDTH 32
INT_MODE 0
MTIME_OFFSET 0x00091000
NIOSV_CORE_VARIANT 3
NUM_GPR 32
NUM_SRF_BANKS 1
RESET_ADDR 0x00000000
TICKS_PER_SEC no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE 2

intel_onchip_memory

intel_onchip_memory v1.4.10
intel_niosv_g data_manager   intel_onchip_memory
  s1
instruction_manager  
  s1
iopll_sys outclk0  
  clk1
reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ram
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 1
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

iopll_hdmi

altera_iopll v20.0.0
clock_in out_clk   iopll_hdmi
  refclk
reset_in out_reset  
  reset
outclk0   vvp_system_clock_in_hdmi
  in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll_sys

altera_iopll v20.0.0
clock_in out_clk   iopll_sys
  refclk
reset_in out_reset  
  reset
outclk0   intel_niosv_g
  clk
outclk0   jtag_uart
  clk
outclk0   sysid_qsys
  clk
outclk0   timer
  clk
outclk0   pio_led
  clk
outclk0   pio_switch
  clk
outclk0   pio_key
  clk
outclk0   pio_hdmi_config_done
  clk
outclk0   pio_mem_ready
  clk
outclk0   pio_vvp_reset_n
  clk
outclk0   pio_cam_gpio
  clk
outclk0   intel_onchip_memory
  clk1
outclk0   i2c
  clock
outclk0   vvp_system_clock_in_control
  in_clk
outclk3   vvp_system_clock_in_vid
  in_clk
outclk4   vvp_system_clock_in_mem
  in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.3.1
intel_niosv_g data_manager   jtag_uart
  avalon_jtag_slave
platform_irq_rx  
  irq
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

pio_cam_gpio

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_cam_gpio
  s1
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

pio_hdmi_config_done

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_hdmi_config_done
  s1
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_key

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_key
  s1
platform_irq_rx  
  irq
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 1
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE FALLING
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

pio_led

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_led
  s1
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

pio_mem_ready

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_mem_ready
  s1
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_switch

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_switch
  s1
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_vvp_reset_n

altera_avalon_pio v19.2.4
intel_niosv_g data_manager   pio_vvp_reset_n
  s1
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 100000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 1

reset_in

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in_vvp

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in_vvp
  clk
out_reset   vvp_system_reset_in_vvp
  in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid_qsys

altera_avalon_sysid_qsys v19.1.8
intel_niosv_g data_manager   sysid_qsys
  control_slave
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

timer

altera_avalon_timer v19.3.5
intel_niosv_g data_manager   timer
  s1
platform_irq_rx  
  irq
iopll_sys outclk0  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 100000000
LOAD_VALUE 99999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1

vvp_system

vvp_system v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_clock_in_control

altera_clock_bridge v19.2.0
iopll_sys outclk0   vvp_system_clock_in_control
  in_clk
out_clk   vvp_system_intel_vvp_switch
  agent_clock
out_clk   vvp_system_intel_vvp_pip_conv_4to1
  agent_clock
out_clk   vvp_system_intel_vvp_tpg_1
  agent_clock
out_clk   vvp_system_intel_vvp_demosaic
  agent_clock
out_clk   vvp_system_mm_bridge_control
  clk
out_clk   vvp_system_intel_vvp_vfb
  control_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_clock_in_csi2

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_clock_in_hdmi

altera_clock_bridge v19.2.0
iopll_hdmi outclk0   vvp_system_clock_in_hdmi
  in_clk
out_clk   vvp_system_intel_vvp_cvo
  fr_clock
out_clk   vvp_system_intel_vvp_fr2cv
  vid_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_clock_in_mem

altera_clock_bridge v19.2.0
iopll_sys outclk4   vvp_system_clock_in_mem
  in_clk
out_clk   vvp_system_intel_vvp_vfb
  mem_clock
out_clk   vvp_system_emif_io96b_lpddr4a
  s0_axi4_clock_in
out_clk  
  s0_axi4lite_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_clock_in_vid

altera_clock_bridge v19.2.0
iopll_sys outclk3   vvp_system_clock_in_vid
  in_clk
out_clk   vvp_system_reset_in
  clk
out_clk   vvp_system_reset_in_vvp
  clk
out_clk   vvp_system_intel_vvp_vfb
  main_clock
out_clk   vvp_system_intel_vvp_pip_conv_4to1
  out_clock
out_clk   vvp_system_intel_vvp_cvo
  vid_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_emif_io96b_lpddr4a

emif_io96b_lpddr4 v4.0.0
vvp_system_intel_vvp_vfb av_mm_mem_read_host   vvp_system_emif_io96b_lpddr4a
  s0_axi4
av_mm_mem_write_host  
  s0_axi4
vvp_system_clock_in_mem out_clk  
  s0_axi4_clock_in
out_clk  
  s0_axi4lite_clock
vvp_system_reset_in out_reset  
  core_init_n
out_reset  
  s0_axi4lite_reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_cvo

intel_vvp_cvo v24.4.1
vvp_system_intel_vvp_vfb axi4s_vid_out   vvp_system_intel_vvp_cvo
  axi4s_vid_in
vvp_system_clock_in_hdmi out_clk  
  fr_clock
vvp_system_clock_in_vid out_clk  
  vid_clock
vvp_system_reset_in out_reset  
  fr_reset
out_reset  
  vid_reset
vvp_system_reset_in_vvp out_reset  
  fr_reset
out_reset  
  vid_reset
axi4s_fr_vid_out   vvp_system_intel_vvp_fr2cv
  axi4s_fr_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_demosaic

intel_vvp_demosaic v24.4.1
vvp_system_mm_bridge_control m0   vvp_system_intel_vvp_demosaic
  av_mm_control_agent
vvp_system_clock_in_control out_clk  
  agent_clock
vvp_system_clock_in_csi2 out_clk  
  main_clock
vvp_system_reset_in out_reset  
  agent_reset
out_reset  
  main_reset
vvp_system_reset_in_vvp out_reset  
  main_reset
axi4s_vid_out   vvp_system_intel_vvp_switch
  axi4s_vid_in_1


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_fr2cv

intel_vvp_fr2cv v24.3.1
vvp_system_intel_vvp_cvo axi4s_fr_vid_out   vvp_system_intel_vvp_fr2cv
  axi4s_fr_vid_in
vvp_system_clock_in_hdmi out_clk  
  vid_clock
vvp_system_reset_in_vvp out_reset  
  vid_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_pip_conv_4to1

intel_vvp_pip_conv v24.5.1
vvp_system_mm_bridge_control m0   vvp_system_intel_vvp_pip_conv_4to1
  av_mm_control_agent
vvp_system_intel_vvp_pixel_adapter axi4s_vid_out  
  axi4s_vid_in
vvp_system_clock_in_control out_clk  
  agent_clock
vvp_system_clock_in_csi2 out_clk  
  in_clock
vvp_system_clock_in_vid out_clk  
  out_clock
vvp_system_reset_in out_reset  
  agent_reset
out_reset  
  in_reset
out_reset  
  out_reset
vvp_system_reset_in_vvp out_reset  
  in_reset
out_reset  
  out_reset
axi4s_vid_out   vvp_system_intel_vvp_vfb
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_pixel_adapter

intel_vvp_pixel_adapter v24.6.1
vvp_system_intel_vvp_switch axi4s_vid_out_0   vvp_system_intel_vvp_pixel_adapter
  axi4s_vid_in
vvp_system_clock_in_csi2 out_clk  
  main_clock
vvp_system_reset_in out_reset  
  main_reset
vvp_system_reset_in_vvp out_reset  
  main_reset
axi4s_vid_out   vvp_system_intel_vvp_pip_conv_4to1
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_switch

intel_vvp_switch v24.4.1
vvp_system_mm_bridge_control m0   vvp_system_intel_vvp_switch
  av_mm_control_agent
vvp_system_intel_vvp_tpg axi4s_vid_out  
  axi4s_vid_in_0
vvp_system_intel_vvp_demosaic axi4s_vid_out  
  axi4s_vid_in_1
vvp_system_intel_vvp_tpg_1 axi4s_vid_out  
  axi4s_vid_in_2
vvp_system_clock_in_control out_clk  
  agent_clock
vvp_system_clock_in_csi2 out_clk  
  main_clock
vvp_system_reset_in out_reset  
  agent_reset
out_reset  
  main_reset
axi4s_vid_out_0   vvp_system_intel_vvp_pixel_adapter
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_tpg

intel_vvp_tpg v24.5.1
vvp_system_clock_in_csi2 out_clk   vvp_system_intel_vvp_tpg
  main_clock
vvp_system_reset_in out_reset  
  main_reset
axi4s_vid_out   vvp_system_intel_vvp_switch
  axi4s_vid_in_0


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_tpg_1

intel_vvp_tpg v24.5.1
vvp_system_mm_bridge_control m0   vvp_system_intel_vvp_tpg_1
  av_mm_control_agent
vvp_system_clock_in_control out_clk  
  agent_clock
vvp_system_clock_in_csi2 out_clk  
  main_clock
vvp_system_reset_in out_reset  
  agent_reset
out_reset  
  main_reset
axi4s_vid_out   vvp_system_intel_vvp_switch
  axi4s_vid_in_2


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_intel_vvp_vfb

intel_vvp_vfb v24.5.1
vvp_system_mm_bridge_control m0   vvp_system_intel_vvp_vfb
  av_mm_control_agent
vvp_system_intel_vvp_pip_conv_4to1 axi4s_vid_out  
  axi4s_vid_in
vvp_system_clock_in_control out_clk  
  control_clock
vvp_system_clock_in_vid out_clk  
  main_clock
vvp_system_clock_in_mem out_clk  
  mem_clock
vvp_system_reset_in out_reset  
  control_reset
out_reset  
  main_reset
out_reset  
  mem_reset
vvp_system_reset_in_vvp out_reset  
  main_reset
out_reset  
  mem_reset
av_mm_mem_read_host   vvp_system_emif_io96b_lpddr4a
  s0_axi4
av_mm_mem_write_host  
  s0_axi4
axi4s_vid_out   vvp_system_intel_vvp_cvo
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_mm_bridge_control

altera_avalon_mm_bridge v20.1.0
vvp_system_clock_in_control out_clk   vvp_system_mm_bridge_control
  clk
vvp_system_reset_in out_reset  
  reset
intel_niosv_g data_manager  
  s0
m0   vvp_system_intel_vvp_switch
  av_mm_control_agent
m0   vvp_system_intel_vvp_vfb
  av_mm_control_agent
m0   vvp_system_intel_vvp_pip_conv_4to1
  av_mm_control_agent
m0   vvp_system_intel_vvp_tpg_1
  av_mm_control_agent
m0   vvp_system_intel_vvp_demosaic
  av_mm_control_agent


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_reset_in

altera_reset_bridge v19.2.0
vvp_system_clock_in_vid out_clk   vvp_system_reset_in
  clk
reset_in out_reset  
  in_reset
out_reset   vvp_system_intel_vvp_switch
  agent_reset
out_reset  
  main_reset
out_reset   vvp_system_intel_vvp_pip_conv_4to1
  agent_reset
out_reset  
  in_reset
out_reset  
  out_reset
out_reset   vvp_system_intel_vvp_tpg_1
  agent_reset
out_reset  
  main_reset
out_reset   vvp_system_intel_vvp_demosaic
  agent_reset
out_reset  
  main_reset
out_reset   vvp_system_intel_vvp_vfb
  control_reset
out_reset  
  main_reset
out_reset  
  mem_reset
out_reset   vvp_system_emif_io96b_lpddr4a
  core_init_n
out_reset  
  s0_axi4lite_reset_n
out_reset   vvp_system_intel_vvp_cvo
  fr_reset
out_reset  
  vid_reset
out_reset   vvp_system_intel_vvp_tpg
  main_reset
out_reset   vvp_system_intel_vvp_pixel_adapter
  main_reset
out_reset   vvp_system_mm_bridge_control
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

vvp_system_reset_in_vvp

altera_reset_bridge v19.2.0
vvp_system_clock_in_vid out_clk   vvp_system_reset_in_vvp
  clk
reset_in_vvp out_reset  
  in_reset
out_reset   vvp_system_intel_vvp_cvo
  fr_reset
out_reset  
  vid_reset
out_reset   vvp_system_intel_vvp_pip_conv_4to1
  in_reset
out_reset  
  out_reset
out_reset   vvp_system_intel_vvp_vfb
  main_reset
out_reset  
  mem_reset
out_reset   vvp_system_intel_vvp_pixel_adapter
  main_reset
out_reset   vvp_system_intel_vvp_demosaic
  main_reset
out_reset   vvp_system_intel_vvp_fr2cv
  vid_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
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