EMIF_Qsys

2025.08.28.18:03:40 Datasheet
Overview
Memory Map
  emif_lpddr4a
s0_axi4 
s0_axi4lite 
  emif_lpddr4b
s0_axi4 
s0_axi4lite 

clock_310m

altera_clock_bridge v19.2.0
iopll outclk0   clock_310m
  in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4a

emif_io96b_lpddr4 v4.0.0
iopll outclk0   emif_lpddr4a
  s0_axi4_clock_in
reset_in out_reset  
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4b

emif_io96b_lpddr4 v4.0.0
iopll outclk0   emif_lpddr4b
  s0_axi4_clock_in
reset_in out_reset  
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll

altera_iopll v20.0.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
iopll outclk0   reset_in
  clk
out_reset   emif_lpddr4a
  core_init_n
out_reset   emif_lpddr4b
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)
generation took 0.01 seconds rendering took 0.03 seconds