csi2_dphy_sys_tx_axi4s_clk_bridge
2025.03.17.17:10:13
Datasheet
Overview
Memory Map
tx_axi4s_clk_bridge
altera_clock_bridge v19.2.0
Parameters
DERIVED_CLOCK_RATE
0
EXPLICIT_CLOCK_RATE
300000000
NUM_CLOCK_OUTPUTS
1
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0.00 seconds
rendering took 0.00 seconds