csi2_dphy_sys_mipi_dphy

2025.08.27.13:01:42 Datasheet
Overview

Memory Map
  mipi_dphy
axi_lite 

mipi_dphy

mipi_dphy v6.0.0


Parameters

GUI_NUM_PLL 1
GUI_RZQ_SHARING false
GUI_RZQ_ID 1
GUI_SKEW_CAL_LEN 32768
GUI_ALT_CAL_LEN 65536
SHOW_8PPI false
GUI_CORE_CLK_DIV_0 8
GUI_REF_CLK_FREQ_MHZ_0 50.0
GUI_REF_CLK_IO_0 2
GUI_VCO_FREQ_MHZ_0 800.0
GUI_DPHY_IP_ROLE_0 0
GUI_SKEW_CAL_EN_0 false
GUI_SOURCE_PLL_0 0
GUI_BIT_RATE_MBPS_RNG_0 987.0
GUI_PPI_WIDTH_USR_0 16
GUI_NUM_LANES_0 2
GUI_BYTE_LOC_0 4
GUI_CONTINUOUS_CLK_0 false
DER_FR_CLK_FREQ_MHZ_0 100.0
GUI_RX_TIMING_RW_0 1
GUI_RX_AUTO_TYPE_0 2
GUI_RX_CLK_LOSS_DETECT_0_AUTO_BOOL true
GUI_RX_CLK_LOSS_DETECT_0_AUTO 5
GUI_RX_CLK_SETTLE_0_AUTO_BOOL true
GUI_RX_CLK_SETTLE_0_AUTO 10
GUI_RX_HS_SETTLE_0_AUTO_BOOL true
GUI_RX_HS_SETTLE_0_AUTO 5
GUI_RX_INIT_0_AUTO_BOOL true
GUI_RX_INIT_0_AUTO 15
GUI_RX_DLANE_DESKEW_DELAY_0_0 0
GUI_RX_DLANE_DESKEW_DELAY_1_0 0
GUI_RX_CAP_EQ_MODE_0 0
GUI_DPHY_IP_ROLE_1 2
GUI_DPHY_IP_ROLE_2 2
GUI_DPHY_IP_ROLE_3 2
GUI_DPHY_IP_ROLE_4 2
GUI_DPHY_IP_ROLE_5 2
GUI_DPHY_IP_ROLE_6 2
GUI_DPHY_IP_ROLE_7 2
EX_DESIGN_HDL_FORMAT HDL_FORMAT_VERILOG
EX_DESIGN_GEN_SYNTH false
EX_DESIGN_GEN_SIM true
EX_DESIGN_TEST_COUNT 10
EX_DESIGN_SIM_LOOPBACK true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
generation took 0.00 seconds rendering took 0.02 seconds