csi2_dphy_sys

2025.08.27.13:01:31 Datasheet
Overview

All Components
   csi2_rx intel_mipi_csi2 2.0.1
Memory Map
  csi2_rx
avalon_mm_control_interface 
  mipi_dphy
axi_lite 

csi2_rx

intel_mipi_csi2 v2.0.1
mipi_dphy LINK0_CK_ppi_rx_hs_clk   csi2_rx
  ck_ppi_hs_clk
LINK0_D0_ppi_rx_hs_clk  
  d0_ppi_hs_clk
LINK0_D1_ppi_rx_hs_clk  
  d1_ppi_hs_clk
LINK0_CK_ppi_ctrl  
  ck_ppi_ctrl
LINK0_D0_ppi_ctrl  
  d0_ppi_ctrl
LINK0_D1_ppi_ctrl  
  d1_ppi_ctrl
LINK0_CK_ppi_rx_hs_srst  
  ck_ppi_rx_hs_srst
LINK0_D0_ppi_rx_hs_srst  
  d0_ppi_rx_hs_srst
LINK0_D1_ppi_rx_hs_srst  
  d1_ppi_rx_hs_srst
rx_axi4s_clk_bridge out_clk  
  axi4s_clk
reset_release_0 ninit_done  
  axi4s_rst
ck_ppi_hs   mipi_dphy
  LINK0_CK_ppi_rx_hs
ck_ppi_lp  
  LINK0_CK_ppi_rx_lp
d0_ppi_hs  
  LINK0_D0_ppi_rx_hs
d0_ppi_lp  
  LINK0_D0_ppi_rx_lp
d1_ppi_hs  
  LINK0_D1_ppi_rx_hs
d1_ppi_lp  
  LINK0_D1_ppi_rx_lp
i_ck_ppi_rx_err  
  LINK0_CK_ppi_rx_err
i_d0_ppi_rx_err  
  LINK0_D0_ppi_rx_err
i_d1_ppi_rx_err  
  LINK0_D1_ppi_rx_err


Parameters

generateLegacySim false
  

Software Assignments

(none)

mipi_dphy

mipi_dphy v6.0.0
csi2_rx ck_ppi_hs   mipi_dphy
  LINK0_CK_ppi_rx_hs
ck_ppi_lp  
  LINK0_CK_ppi_rx_lp
d0_ppi_hs  
  LINK0_D0_ppi_rx_hs
d0_ppi_lp  
  LINK0_D0_ppi_rx_lp
d1_ppi_hs  
  LINK0_D1_ppi_rx_hs
d1_ppi_lp  
  LINK0_D1_ppi_rx_lp
i_ck_ppi_rx_err  
  LINK0_CK_ppi_rx_err
i_d0_ppi_rx_err  
  LINK0_D0_ppi_rx_err
i_d1_ppi_rx_err  
  LINK0_D1_ppi_rx_err
reset_release_0 ninit_done  
  arst
ninit_done  
  reg_srst
LINK0_CK_ppi_rx_hs_clk   csi2_rx
  ck_ppi_hs_clk
LINK0_D0_ppi_rx_hs_clk  
  d0_ppi_hs_clk
LINK0_D1_ppi_rx_hs_clk  
  d1_ppi_hs_clk
LINK0_CK_ppi_ctrl  
  ck_ppi_ctrl
LINK0_D0_ppi_ctrl  
  d0_ppi_ctrl
LINK0_D1_ppi_ctrl  
  d1_ppi_ctrl
LINK0_CK_ppi_rx_hs_srst  
  ck_ppi_rx_hs_srst
LINK0_D0_ppi_rx_hs_srst  
  d0_ppi_rx_hs_srst
LINK0_D1_ppi_rx_hs_srst  
  d1_ppi_rx_hs_srst


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_release_0

intel_user_rst_clkgate v1.0.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

rx_axi4s_clk_bridge

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)
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