| MEM_NUM_CHANNELS |
1 |
| MEM_CHANNEL_DATA_DQ_WIDTH |
32 |
| MEM_DIE_DENSITY_GBITS |
4 |
| MEM_CHANNEL_CS_WIDTH |
1 |
| MEM_OPERATING_FREQ_MHZ_AUTOSET_EN |
false |
| MEM_OPERATING_FREQ_MHZ |
1066.667 |
| CTRL_ECC_INLINE_EN |
false |
| CTRL_DM_EN |
true |
| CTRL_WR_DBI_EN |
false |
| CTRL_RD_DBI_EN |
true |
| CTRL_PERFORMANCE_PROFILE |
SEQ |
| TURNAROUND_R2W_SAMECS_CYC |
0 |
| TURNAROUND_R2R_SAMECS_CYC |
0 |
| TURNAROUND_W2W_SAMECS_CYC |
0 |
| TURNAROUND_W2R_SAMECS_CYC |
0 |
| PHY_REFCLK_FREQ_MHZ_AUTOSET_EN |
false |
| PHY_REFCLK_ADVANCED_SELECT_EN |
true |
| PHY_REFCLK_FREQ_MHZ |
166.6667 |
| PHY_AC_PLACEMENT |
BOT |
| PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN |
true |
| PHY_MAINBAND_ACCESS_MODE |
ASYNC |
| PHY_SIDEBAND_ACCESS_MODE |
FABRIC |
| PHY_SWIZZLE_MAP |
PIN_SWIZZLE_CH0_DQS0=5,4,0,7,1,6,2,3;PIN_SWIZZLE_CH0_DQS1=15,8,14,9,12,13,11,10;PIN_SWIZZLE_CH0_DQS2=18,22,19,20,21,23,16,17;PIN_SWIZZLE_CH0_DQS3=27,29,28,26,24,25,31,30; |
| DEBUG_TOOLS_EN |
false |
| INSTANCE_ID |
0 |
| ADV_CAL_ENABLE_MARGIN |
false |
| MEM_CL_CYC |
22 |
| MEM_CWL_CYC |
18 |
| MEM_RD_POSTAMBLE_CYC |
1 |
| MEM_WR_POSTAMBLE_CYC |
1 |
| MEM_TSR_NS |
15.0 |
| MEM_TRFCAB_NS |
180.0 |
| MEM_TRFCPB_NS |
90.0 |
| MEM_TXSR_NS |
187.5 |
| MEM_TXP_NS |
7.5 |
| MEM_TCCD_NS |
8.0 |
| MEM_TRTP_NS |
7.5 |
| MEM_TRCD_NS |
18.0 |
| MEM_TRPPB_NS |
18.0 |
| MEM_TRPAB_NS |
21.0 |
| MEM_TRAS_NS |
42.0 |
| MEM_TWR_NS |
18.0 |
| MEM_TWTR_NS |
10.0 |
| MEM_TRRD_NS |
10.0 |
| MEM_TPPD_CYC |
4.0 |
| MEM_TFAW_NS |
40.0 |
| MEM_TRC_NS |
63.0 |
| MEM_TREFW_NS |
3.2E7 |
| MEM_MINNUMREFSREQ |
8192.0 |
| MEM_TREFI_NS |
3904.0 |
| MEM_TCKE_NS |
7.5 |
| MEM_TCMDCKE_NS |
2.81 |
| MEM_TCKELCK_NS |
5.0 |
| MEM_TCSCKE_NS |
1.75 |
| MEM_TCKCKEH_NS |
2.81 |
| MEM_TCSCKEH_NS |
1.75 |
| MEM_TMRWCKEL_NS |
14.0 |
| MEM_TZQCKE_NS |
2.81 |
| MEM_TMRR_NS |
7.5 |
| MEM_TMRW_NS |
10.0 |
| MEM_TMRD_NS |
14.0 |
| MEM_TESCKE_NS |
2.81 |
| MEM_TZQCAL_NS |
1000.0 |
| MEM_TZQLAT_NS |
30.0 |
| MEM_TDQSCK_MAX_NS |
3.5 |
| MEM_TDQSCK_MIN_NS |
1.5 |
| MEM_TCKCKEL_NS |
5.0 |
| MEM_TCKELCMD_NS |
5.0 |
| MEM_TCKEHCMD_NS |
7.5 |
| JEDEC_OVERRIDE_TABLE_PARAM_NAME |
MEM_TRFCAB_NS,MEM_TRFCPB_NS,MEM_TCCD_NS,MEM_RD_POSTAMBLE_CYC,MEM_WR_POSTAMBLE_CYC,MEM_TCMDCKE_NS,MEM_TCKCKEH_NS,MEM_TZQCKE_NS,MEM_TESCKE_NS |
| EX_DESIGN_HDL_FORMAT |
VERILOG |
| EX_DESIGN_GEN_SYNTH |
true |
| EX_DESIGN_GEN_SIM |
true |
| EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN |
true |
| EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ |
310.0 |
| EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ |
100.0 |
| EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ |
100 |
| EX_DESIGN_TG_CSR_ACCESS_MODE |
JTAG |
| EX_DESIGN_TG_PROGRAM |
MEDIUM |
| EX_DESIGN_PMON_CH0_EN |
false |
| PHY_TERM_X_R_S_AC_OUTPUT_OHM |
SERIES_40_OHM_CAL |
| PHY_TERM_X_R_S_CK_OUTPUT_OHM |
SERIES_40_OHM_CAL |
| PHY_TERM_X_R_S_DQ_OUTPUT_OHM |
SERIES_40_OHM_CAL |
| PHY_TERM_X_DQ_SLEW_RATE |
FASTEST |
| PHY_TERM_X_R_T_DQ_INPUT_OHM |
RT_50_OHM_CAL |
| PHY_TERM_X_DQ_VREF |
17.5 |
| PHY_TERM_X_R_T_REFCLK_INPUT_OHM |
RT_DIFF |
| MEM_ODT_DQ_X_TGT_WR |
5 |
| MEM_ODT_DQ_X_IDLE |
off |
| MEM_ODT_DQ_X_RON |
6 |
| MEM_VREF_DQ_X_RANGE |
1 |
| MEM_VREF_DQ_X_VALUE |
18.0 |
| MEM_ODT_CA_X_CA_COMM |
3 |
| MEM_ODT_CA_X_CA_ENABLE |
true |
| MEM_ODT_CA_X_CS_ENABLE |
true |
| MEM_ODT_CA_X_CK_ENABLE |
true |
| MEM_VREF_CA_X_CA_RANGE |
2 |
| MEM_VREF_CA_X_CA_VALUE |
27.2 |
| ANALOG_PARAM_DERIVATION_PARAM_NAME |
|
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |