Qsys

2025.08.29.16:31:31 Datasheet
Overview
Processor
   intel_niosv_m Abbotts Lake 26.0.0
All Components
   address_span_extender altera_address_span_extender 19.2.0
   intel_niosv_m intel_niosv_m 26.0.0
   jtag_uart altera_avalon_jtag_uart 19.3.1
   mm_ccb mm_ccb 19.3.0
   mm_ccb_lpddr4 mm_ccb 19.3.0
   pio_key altera_avalon_pio 19.2.4
   pio_led altera_avalon_pio 19.2.4
   sysid_qsys altera_avalon_sysid_qsys 19.1.8
   timer altera_avalon_timer 19.3.5
Memory Map
address_span_extender intel_niosv_m mm_ccb mm_ccb_lpddr4
 expanded_master  instruction_manager  data_manager  m0  m0
  address_span_extender
windowed_slave  0x4000_0000 - 0x7fff_ffff
cntl  0x0009_0440 - 0x0009_0447
  emif_lpddr4a
s0_axi4  0x0000_0000 - 0x3fff_ffff 0x0000_0000 - 0x3fff_ffff
s0_axi4lite 
  emif_lpddr4b
s0_axi4  0x4000_0000 - 0x7fff_ffff 0x4000_0000 - 0x7fff_ffff
s0_axi4lite 
  intel_niosv_m
timer_sw_agent  0x0009_0400 - 0x0009_043f
dm_agent  0x0008_0000 - 0x0008_ffff 0x0008_0000 - 0x0008_ffff
  intel_onchip_memory
axi_s1  0x0000_0000 - 0x0007_ffff 0x0000_0000 - 0x0007_ffff
  jtag_uart
avalon_jtag_slave  0x0009_0048 - 0x0009_004f 0x0048 - 0x004f
  mm_ccb
s0  0x0009_0000 - 0x0009_03ff
  mm_ccb_lpddr4
s0  0x0000_0000 - 0x7fff_ffff
  pio_key
s1  0x0009_0030 - 0x0009_003f 0x0030 - 0x003f
  pio_led
s1  0x0009_0020 - 0x0009_002f 0x0020 - 0x002f
  sysid_qsys
control_slave  0x0009_0040 - 0x0009_0047 0x0040 - 0x0047
  timer
s1  0x0009_0000 - 0x0009_001f 0x0000 - 0x001f

address_span_extender

altera_address_span_extender v19.2.0
intel_niosv_m data_manager   address_span_extender
  cntl
data_manager  
  windowed_slave
iopll outclk0  
  clock
reset_in out_reset  
  reset
expanded_master   mm_ccb_lpddr4
  s0


Parameters

generateLegacySim false
  

Software Assignments

BURSTCOUNT_WIDTH 1
BYTEENABLE_WIDTH 4
CNTL_ADDRESS_WIDTH 1
DATA_WIDTH 32
MASTER_ADDRESS_WIDTH 31
MAX_BURST_BYTES 4
MAX_BURST_WORDS 1
SLAVE_ADDRESS_SHIFT 2
SLAVE_ADDRESS_WIDTH 28
SUB_WINDOW_COUNT 1

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4a

emif_io96b_lpddr4 v4.0.0
mm_ccb_lpddr4 m0   emif_lpddr4a
  s0_axi4
iopll outclk0  
  s0_axi4_clock_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4b

emif_io96b_lpddr4 v4.0.0
mm_ccb_lpddr4 m0   emif_lpddr4b
  s0_axi4
iopll outclk0  
  s0_axi4_clock_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_niosv_m

intel_niosv_m v26.0.0
iopll outclk0   intel_niosv_m
  clk
reset_in out_reset  
  reset
data_manager   intel_onchip_memory
  axi_s1
instruction_manager  
  axi_s1
data_manager   address_span_extender
  cntl
data_manager  
  windowed_slave
data_manager   mm_ccb
  s0
platform_irq_rx   jtag_uart
  irq
platform_irq_rx   timer
  irq


Parameters

generateLegacySim false
  

Software Assignments

CPU_FREQ 310000000u
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
HAS_CSR_SUPPORT 1
HAS_DEBUG_STUB
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
INST_ADDR_WIDTH 32
INT_MODE 0
MTIME_OFFSET 0x00090400
NIOSV_CORE_VARIANT 1
NUM_GPR 32
RESET_ADDR 0x00000000
TICKS_PER_SEC no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE 2

intel_onchip_memory

intel_onchip_memory v1.4.10
intel_niosv_m data_manager   intel_onchip_memory
  axi_s1
instruction_manager  
  axi_s1
iopll outclk0  
  clk1
reset_in out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE Qsys_intel_onchip_memory_0_intel_onchip_memory_0
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

iopll

altera_iopll v20.0.0
clock_in out_clk   iopll
  refclk
reset_in out_reset  
  reset
outclk0   intel_niosv_m
  clk
outclk0   intel_onchip_memory
  clk1
outclk0   address_span_extender
  clock
outclk0   emif_lpddr4b
  s0_axi4_clock_in
outclk0   emif_lpddr4a
  s0_axi4_clock_in
outclk0   mm_ccb
  s0_clk
outclk2  
  m0_clk
outclk2   jtag_uart
  clk
outclk2   sysid_qsys
  clk
outclk2   timer
  clk
outclk2   pio_key
  clk
outclk2   pio_led
  clk
outclk2   mm_ccb_lpddr4
  m0_clk
outclk2  
  s0_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.3.1
mm_ccb m0   jtag_uart
  avalon_jtag_slave
iopll outclk2  
  clk
intel_niosv_m platform_irq_rx  
  irq
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

mm_ccb

mm_ccb v19.3.0
intel_niosv_m data_manager   mm_ccb
  s0
iopll outclk0  
  s0_clk
outclk2  
  m0_clk
reset_in out_reset  
  m0_reset
out_reset  
  s0_reset
m0   jtag_uart
  avalon_jtag_slave
m0   sysid_qsys
  control_slave
m0   timer
  s1
m0   pio_key
  s1
m0   pio_led
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_ccb_lpddr4

mm_ccb v19.3.0
address_span_extender expanded_master   mm_ccb_lpddr4
  s0
iopll outclk2  
  m0_clk
outclk2  
  s0_clk
reset_in out_reset  
  m0_reset
out_reset  
  s0_reset
m0   emif_lpddr4a
  s0_axi4
m0   emif_lpddr4b
  s0_axi4


Parameters

generateLegacySim false
  

Software Assignments

(none)

pio_key

altera_avalon_pio v19.2.4
mm_ccb m0   pio_key
  s1
iopll outclk2  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v19.2.4
mm_ccb m0   pio_led
  s1
iopll outclk2  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 8
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   mm_ccb
  m0_reset
out_reset  
  s0_reset
out_reset   mm_ccb_lpddr4
  m0_reset
out_reset  
  s0_reset
out_reset   iopll
  reset
out_reset   jtag_uart
  reset
out_reset   pio_led
  reset
out_reset   timer
  reset
out_reset   pio_key
  reset
out_reset   sysid_qsys
  reset
out_reset   address_span_extender
  reset
out_reset   intel_niosv_m
  reset
out_reset   intel_onchip_memory
  reset1


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid_qsys

altera_avalon_sysid_qsys v19.1.8
mm_ccb m0   sysid_qsys
  control_slave
iopll outclk2  
  clk
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

timer

altera_avalon_timer v19.3.5
mm_ccb m0   timer
  s1
iopll outclk2  
  clk
intel_niosv_m platform_irq_rx  
  irq
reset_in out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
COUNTER_SIZE 32
FIXED_PERIOD 0
FREQ 50000000
LOAD_VALUE 49999
MULT 0.001
PERIOD 1
PERIOD_UNITS ms
RESET_OUTPUT 0
SNAPSHOT 1
TICKS_PER_SEC 1000
TIMEOUT_PULSE_OUTPUT 0
TIMER_DEVICE_TYPE 1
generation took 0.02 seconds rendering took 0.06 seconds