// nios_system.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system (
		input  wire       clk_clk,                       //                    clk.clk
		input  wire [9:0] sw_external_connection_export, // sw_external_connection.export
		input  wire       reset_reset_n,                 //                  reset.reset_n
		input  wire       spi_master_external_MISO,      //    spi_master_external.MISO
		output wire       spi_master_external_MOSI,      //                       .MOSI
		output wire       spi_master_external_SCLK,      //                       .SCLK
		output wire       spi_master_external_SS_n       //                       .SS_n
	);

	wire         clock_in_out_clk_clk;                                      // clock_in:out_clk -> [iopll:refclk, reset_bridge:clk, reset_in:clk, rst_controller_002:clk]
	wire         iopll_outclk0_clk;                                         // iopll:outclk_0 -> [irq_mapper:clk, jtag_uart:clk, mm_bridge_peripheral:clk, mm_interconnect_0:iopll_outclk0_clk, mm_interconnect_1:iopll_outclk0_clk, niosv_g:clk, onchip_memory:clk, pio_sw:clk, rst_controller:clk, rst_controller_001:clk, spi_master:clk, sysid_qsys:clock]
	wire         reset_bridge_out_reset_reset;                              // reset_bridge:out_reset_n -> [iopll:rst, rst_controller:reset_in0, rst_controller_001:reset_in0]
	wire   [7:0] niosv_g_data_manager_arlen;                                // niosv_g:data_manager_arlen -> mm_interconnect_0:niosv_g_data_manager_arlen
	wire   [3:0] niosv_g_data_manager_wstrb;                                // niosv_g:data_manager_wstrb -> mm_interconnect_0:niosv_g_data_manager_wstrb
	wire         niosv_g_data_manager_wready;                               // mm_interconnect_0:niosv_g_data_manager_wready -> niosv_g:data_manager_wready
	wire         niosv_g_data_manager_rready;                               // niosv_g:data_manager_rready -> mm_interconnect_0:niosv_g_data_manager_rready
	wire   [7:0] niosv_g_data_manager_awlen;                                // niosv_g:data_manager_awlen -> mm_interconnect_0:niosv_g_data_manager_awlen
	wire         niosv_g_data_manager_wvalid;                               // niosv_g:data_manager_wvalid -> mm_interconnect_0:niosv_g_data_manager_wvalid
	wire  [31:0] niosv_g_data_manager_araddr;                               // niosv_g:data_manager_araddr -> mm_interconnect_0:niosv_g_data_manager_araddr
	wire   [2:0] niosv_g_data_manager_arprot;                               // niosv_g:data_manager_arprot -> mm_interconnect_0:niosv_g_data_manager_arprot
	wire   [2:0] niosv_g_data_manager_awprot;                               // niosv_g:data_manager_awprot -> mm_interconnect_0:niosv_g_data_manager_awprot
	wire  [31:0] niosv_g_data_manager_wdata;                                // niosv_g:data_manager_wdata -> mm_interconnect_0:niosv_g_data_manager_wdata
	wire         niosv_g_data_manager_arvalid;                              // niosv_g:data_manager_arvalid -> mm_interconnect_0:niosv_g_data_manager_arvalid
	wire  [31:0] niosv_g_data_manager_awaddr;                               // niosv_g:data_manager_awaddr -> mm_interconnect_0:niosv_g_data_manager_awaddr
	wire   [1:0] niosv_g_data_manager_bresp;                                // mm_interconnect_0:niosv_g_data_manager_bresp -> niosv_g:data_manager_bresp
	wire         niosv_g_data_manager_arready;                              // mm_interconnect_0:niosv_g_data_manager_arready -> niosv_g:data_manager_arready
	wire  [31:0] niosv_g_data_manager_rdata;                                // mm_interconnect_0:niosv_g_data_manager_rdata -> niosv_g:data_manager_rdata
	wire         niosv_g_data_manager_awready;                              // mm_interconnect_0:niosv_g_data_manager_awready -> niosv_g:data_manager_awready
	wire   [2:0] niosv_g_data_manager_arsize;                               // niosv_g:data_manager_arsize -> mm_interconnect_0:niosv_g_data_manager_arsize
	wire         niosv_g_data_manager_bready;                               // niosv_g:data_manager_bready -> mm_interconnect_0:niosv_g_data_manager_bready
	wire         niosv_g_data_manager_rlast;                                // mm_interconnect_0:niosv_g_data_manager_rlast -> niosv_g:data_manager_rlast
	wire         niosv_g_data_manager_wlast;                                // niosv_g:data_manager_wlast -> mm_interconnect_0:niosv_g_data_manager_wlast
	wire   [1:0] niosv_g_data_manager_rresp;                                // mm_interconnect_0:niosv_g_data_manager_rresp -> niosv_g:data_manager_rresp
	wire         niosv_g_data_manager_bvalid;                               // mm_interconnect_0:niosv_g_data_manager_bvalid -> niosv_g:data_manager_bvalid
	wire   [2:0] niosv_g_data_manager_awsize;                               // niosv_g:data_manager_awsize -> mm_interconnect_0:niosv_g_data_manager_awsize
	wire         niosv_g_data_manager_awvalid;                              // niosv_g:data_manager_awvalid -> mm_interconnect_0:niosv_g_data_manager_awvalid
	wire         niosv_g_data_manager_rvalid;                               // mm_interconnect_0:niosv_g_data_manager_rvalid -> niosv_g:data_manager_rvalid
	wire   [1:0] niosv_g_instruction_manager_awburst;                       // niosv_g:instruction_manager_awburst -> mm_interconnect_0:niosv_g_instruction_manager_awburst
	wire   [7:0] niosv_g_instruction_manager_arlen;                         // niosv_g:instruction_manager_arlen -> mm_interconnect_0:niosv_g_instruction_manager_arlen
	wire   [3:0] niosv_g_instruction_manager_wstrb;                         // niosv_g:instruction_manager_wstrb -> mm_interconnect_0:niosv_g_instruction_manager_wstrb
	wire         niosv_g_instruction_manager_wready;                        // mm_interconnect_0:niosv_g_instruction_manager_wready -> niosv_g:instruction_manager_wready
	wire         niosv_g_instruction_manager_rready;                        // niosv_g:instruction_manager_rready -> mm_interconnect_0:niosv_g_instruction_manager_rready
	wire   [7:0] niosv_g_instruction_manager_awlen;                         // niosv_g:instruction_manager_awlen -> mm_interconnect_0:niosv_g_instruction_manager_awlen
	wire         niosv_g_instruction_manager_wvalid;                        // niosv_g:instruction_manager_wvalid -> mm_interconnect_0:niosv_g_instruction_manager_wvalid
	wire  [31:0] niosv_g_instruction_manager_araddr;                        // niosv_g:instruction_manager_araddr -> mm_interconnect_0:niosv_g_instruction_manager_araddr
	wire   [2:0] niosv_g_instruction_manager_arprot;                        // niosv_g:instruction_manager_arprot -> mm_interconnect_0:niosv_g_instruction_manager_arprot
	wire   [2:0] niosv_g_instruction_manager_awprot;                        // niosv_g:instruction_manager_awprot -> mm_interconnect_0:niosv_g_instruction_manager_awprot
	wire  [31:0] niosv_g_instruction_manager_wdata;                         // niosv_g:instruction_manager_wdata -> mm_interconnect_0:niosv_g_instruction_manager_wdata
	wire         niosv_g_instruction_manager_arvalid;                       // niosv_g:instruction_manager_arvalid -> mm_interconnect_0:niosv_g_instruction_manager_arvalid
	wire  [31:0] niosv_g_instruction_manager_awaddr;                        // niosv_g:instruction_manager_awaddr -> mm_interconnect_0:niosv_g_instruction_manager_awaddr
	wire   [1:0] niosv_g_instruction_manager_bresp;                         // mm_interconnect_0:niosv_g_instruction_manager_bresp -> niosv_g:instruction_manager_bresp
	wire         niosv_g_instruction_manager_arready;                       // mm_interconnect_0:niosv_g_instruction_manager_arready -> niosv_g:instruction_manager_arready
	wire  [31:0] niosv_g_instruction_manager_rdata;                         // mm_interconnect_0:niosv_g_instruction_manager_rdata -> niosv_g:instruction_manager_rdata
	wire         niosv_g_instruction_manager_awready;                       // mm_interconnect_0:niosv_g_instruction_manager_awready -> niosv_g:instruction_manager_awready
	wire   [1:0] niosv_g_instruction_manager_arburst;                       // niosv_g:instruction_manager_arburst -> mm_interconnect_0:niosv_g_instruction_manager_arburst
	wire   [2:0] niosv_g_instruction_manager_arsize;                        // niosv_g:instruction_manager_arsize -> mm_interconnect_0:niosv_g_instruction_manager_arsize
	wire         niosv_g_instruction_manager_bready;                        // niosv_g:instruction_manager_bready -> mm_interconnect_0:niosv_g_instruction_manager_bready
	wire         niosv_g_instruction_manager_rlast;                         // mm_interconnect_0:niosv_g_instruction_manager_rlast -> niosv_g:instruction_manager_rlast
	wire         niosv_g_instruction_manager_wlast;                         // niosv_g:instruction_manager_wlast -> mm_interconnect_0:niosv_g_instruction_manager_wlast
	wire   [1:0] niosv_g_instruction_manager_rresp;                         // mm_interconnect_0:niosv_g_instruction_manager_rresp -> niosv_g:instruction_manager_rresp
	wire         niosv_g_instruction_manager_bvalid;                        // mm_interconnect_0:niosv_g_instruction_manager_bvalid -> niosv_g:instruction_manager_bvalid
	wire   [2:0] niosv_g_instruction_manager_awsize;                        // niosv_g:instruction_manager_awsize -> mm_interconnect_0:niosv_g_instruction_manager_awsize
	wire         niosv_g_instruction_manager_awvalid;                       // niosv_g:instruction_manager_awvalid -> mm_interconnect_0:niosv_g_instruction_manager_awvalid
	wire         niosv_g_instruction_manager_rvalid;                        // mm_interconnect_0:niosv_g_instruction_manager_rvalid -> niosv_g:instruction_manager_rvalid
	wire  [31:0] mm_interconnect_0_niosv_g_dm_agent_readdata;               // niosv_g:dm_agent_readdata -> mm_interconnect_0:niosv_g_dm_agent_readdata
	wire         mm_interconnect_0_niosv_g_dm_agent_waitrequest;            // niosv_g:dm_agent_waitrequest -> mm_interconnect_0:niosv_g_dm_agent_waitrequest
	wire  [15:0] mm_interconnect_0_niosv_g_dm_agent_address;                // mm_interconnect_0:niosv_g_dm_agent_address -> niosv_g:dm_agent_address
	wire         mm_interconnect_0_niosv_g_dm_agent_read;                   // mm_interconnect_0:niosv_g_dm_agent_read -> niosv_g:dm_agent_read
	wire         mm_interconnect_0_niosv_g_dm_agent_readdatavalid;          // niosv_g:dm_agent_readdatavalid -> mm_interconnect_0:niosv_g_dm_agent_readdatavalid
	wire         mm_interconnect_0_niosv_g_dm_agent_write;                  // mm_interconnect_0:niosv_g_dm_agent_write -> niosv_g:dm_agent_write
	wire  [31:0] mm_interconnect_0_niosv_g_dm_agent_writedata;              // mm_interconnect_0:niosv_g_dm_agent_writedata -> niosv_g:dm_agent_writedata
	wire  [31:0] mm_interconnect_0_mm_bridge_peripheral_s0_readdata;        // mm_bridge_peripheral:s0_readdata -> mm_interconnect_0:mm_bridge_peripheral_s0_readdata
	wire         mm_interconnect_0_mm_bridge_peripheral_s0_waitrequest;     // mm_bridge_peripheral:s0_waitrequest -> mm_interconnect_0:mm_bridge_peripheral_s0_waitrequest
	wire         mm_interconnect_0_mm_bridge_peripheral_s0_debugaccess;     // mm_interconnect_0:mm_bridge_peripheral_s0_debugaccess -> mm_bridge_peripheral:s0_debugaccess
	wire  [18:0] mm_interconnect_0_mm_bridge_peripheral_s0_address;         // mm_interconnect_0:mm_bridge_peripheral_s0_address -> mm_bridge_peripheral:s0_address
	wire         mm_interconnect_0_mm_bridge_peripheral_s0_read;            // mm_interconnect_0:mm_bridge_peripheral_s0_read -> mm_bridge_peripheral:s0_read
	wire   [3:0] mm_interconnect_0_mm_bridge_peripheral_s0_byteenable;      // mm_interconnect_0:mm_bridge_peripheral_s0_byteenable -> mm_bridge_peripheral:s0_byteenable
	wire         mm_interconnect_0_mm_bridge_peripheral_s0_readdatavalid;   // mm_bridge_peripheral:s0_readdatavalid -> mm_interconnect_0:mm_bridge_peripheral_s0_readdatavalid
	wire         mm_interconnect_0_mm_bridge_peripheral_s0_write;           // mm_interconnect_0:mm_bridge_peripheral_s0_write -> mm_bridge_peripheral:s0_write
	wire  [31:0] mm_interconnect_0_mm_bridge_peripheral_s0_writedata;       // mm_interconnect_0:mm_bridge_peripheral_s0_writedata -> mm_bridge_peripheral:s0_writedata
	wire   [0:0] mm_interconnect_0_mm_bridge_peripheral_s0_burstcount;      // mm_interconnect_0:mm_bridge_peripheral_s0_burstcount -> mm_bridge_peripheral:s0_burstcount
	wire  [31:0] mm_interconnect_0_onchip_memory_s1_readdata;               // onchip_memory:readdata -> mm_interconnect_0:onchip_memory_s1_readdata
	wire  [15:0] mm_interconnect_0_onchip_memory_s1_address;                // mm_interconnect_0:onchip_memory_s1_address -> onchip_memory:address
	wire         mm_interconnect_0_onchip_memory_s1_read;                   // mm_interconnect_0:onchip_memory_s1_read -> onchip_memory:read
	wire   [3:0] mm_interconnect_0_onchip_memory_s1_byteenable;             // mm_interconnect_0:onchip_memory_s1_byteenable -> onchip_memory:byteenable
	wire         mm_interconnect_0_onchip_memory_s1_write;                  // mm_interconnect_0:onchip_memory_s1_write -> onchip_memory:write
	wire  [31:0] mm_interconnect_0_onchip_memory_s1_writedata;              // mm_interconnect_0:onchip_memory_s1_writedata -> onchip_memory:writedata
	wire  [31:0] mm_interconnect_0_niosv_g_timer_sw_agent_readdata;         // niosv_g:timer_sw_agent_readdata -> mm_interconnect_0:niosv_g_timer_sw_agent_readdata
	wire         mm_interconnect_0_niosv_g_timer_sw_agent_waitrequest;      // niosv_g:timer_sw_agent_waitrequest -> mm_interconnect_0:niosv_g_timer_sw_agent_waitrequest
	wire   [5:0] mm_interconnect_0_niosv_g_timer_sw_agent_address;          // mm_interconnect_0:niosv_g_timer_sw_agent_address -> niosv_g:timer_sw_agent_address
	wire         mm_interconnect_0_niosv_g_timer_sw_agent_read;             // mm_interconnect_0:niosv_g_timer_sw_agent_read -> niosv_g:timer_sw_agent_read
	wire   [3:0] mm_interconnect_0_niosv_g_timer_sw_agent_byteenable;       // mm_interconnect_0:niosv_g_timer_sw_agent_byteenable -> niosv_g:timer_sw_agent_byteenable
	wire         mm_interconnect_0_niosv_g_timer_sw_agent_readdatavalid;    // niosv_g:timer_sw_agent_readdatavalid -> mm_interconnect_0:niosv_g_timer_sw_agent_readdatavalid
	wire         mm_interconnect_0_niosv_g_timer_sw_agent_write;            // mm_interconnect_0:niosv_g_timer_sw_agent_write -> niosv_g:timer_sw_agent_write
	wire  [31:0] mm_interconnect_0_niosv_g_timer_sw_agent_writedata;        // mm_interconnect_0:niosv_g_timer_sw_agent_writedata -> niosv_g:timer_sw_agent_writedata
	wire         mm_bridge_peripheral_m0_waitrequest;                       // mm_interconnect_1:mm_bridge_peripheral_m0_waitrequest -> mm_bridge_peripheral:m0_waitrequest
	wire  [31:0] mm_bridge_peripheral_m0_readdata;                          // mm_interconnect_1:mm_bridge_peripheral_m0_readdata -> mm_bridge_peripheral:m0_readdata
	wire         mm_bridge_peripheral_m0_debugaccess;                       // mm_bridge_peripheral:m0_debugaccess -> mm_interconnect_1:mm_bridge_peripheral_m0_debugaccess
	wire  [18:0] mm_bridge_peripheral_m0_address;                           // mm_bridge_peripheral:m0_address -> mm_interconnect_1:mm_bridge_peripheral_m0_address
	wire         mm_bridge_peripheral_m0_read;                              // mm_bridge_peripheral:m0_read -> mm_interconnect_1:mm_bridge_peripheral_m0_read
	wire   [3:0] mm_bridge_peripheral_m0_byteenable;                        // mm_bridge_peripheral:m0_byteenable -> mm_interconnect_1:mm_bridge_peripheral_m0_byteenable
	wire         mm_bridge_peripheral_m0_readdatavalid;                     // mm_interconnect_1:mm_bridge_peripheral_m0_readdatavalid -> mm_bridge_peripheral:m0_readdatavalid
	wire  [31:0] mm_bridge_peripheral_m0_writedata;                         // mm_bridge_peripheral:m0_writedata -> mm_interconnect_1:mm_bridge_peripheral_m0_writedata
	wire         mm_bridge_peripheral_m0_write;                             // mm_bridge_peripheral:m0_write -> mm_interconnect_1:mm_bridge_peripheral_m0_write
	wire   [0:0] mm_bridge_peripheral_m0_burstcount;                        // mm_bridge_peripheral:m0_burstcount -> mm_interconnect_1:mm_bridge_peripheral_m0_burstcount
	wire         mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect;  // mm_interconnect_1:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
	wire  [31:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata;    // jtag_uart:av_readdata -> mm_interconnect_1:jtag_uart_avalon_jtag_slave_readdata
	wire         mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_1:jtag_uart_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_address;     // mm_interconnect_1:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
	wire         mm_interconnect_1_jtag_uart_avalon_jtag_slave_read;        // mm_interconnect_1:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
	wire         mm_interconnect_1_jtag_uart_avalon_jtag_slave_write;       // mm_interconnect_1:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
	wire  [31:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata;   // mm_interconnect_1:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
	wire  [31:0] mm_interconnect_1_sysid_qsys_control_slave_readdata;       // sysid_qsys:readdata -> mm_interconnect_1:sysid_qsys_control_slave_readdata
	wire   [0:0] mm_interconnect_1_sysid_qsys_control_slave_address;        // mm_interconnect_1:sysid_qsys_control_slave_address -> sysid_qsys:address
	wire         mm_interconnect_1_pio_sw_s1_chipselect;                    // mm_interconnect_1:pio_sw_s1_chipselect -> pio_sw:chipselect
	wire  [31:0] mm_interconnect_1_pio_sw_s1_readdata;                      // pio_sw:readdata -> mm_interconnect_1:pio_sw_s1_readdata
	wire   [1:0] mm_interconnect_1_pio_sw_s1_address;                       // mm_interconnect_1:pio_sw_s1_address -> pio_sw:address
	wire         mm_interconnect_1_pio_sw_s1_write;                         // mm_interconnect_1:pio_sw_s1_write -> pio_sw:write_n
	wire  [31:0] mm_interconnect_1_pio_sw_s1_writedata;                     // mm_interconnect_1:pio_sw_s1_writedata -> pio_sw:writedata
	wire         mm_interconnect_1_spi_master_spi_control_port_chipselect;  // mm_interconnect_1:spi_master_spi_control_port_chipselect -> spi_master:spi_select
	wire  [15:0] mm_interconnect_1_spi_master_spi_control_port_readdata;    // spi_master:data_to_cpu -> mm_interconnect_1:spi_master_spi_control_port_readdata
	wire   [2:0] mm_interconnect_1_spi_master_spi_control_port_address;     // mm_interconnect_1:spi_master_spi_control_port_address -> spi_master:mem_addr
	wire         mm_interconnect_1_spi_master_spi_control_port_read;        // mm_interconnect_1:spi_master_spi_control_port_read -> spi_master:read_n
	wire         mm_interconnect_1_spi_master_spi_control_port_write;       // mm_interconnect_1:spi_master_spi_control_port_write -> spi_master:write_n
	wire  [15:0] mm_interconnect_1_spi_master_spi_control_port_writedata;   // mm_interconnect_1:spi_master_spi_control_port_writedata -> spi_master:data_from_cpu
	wire         irq_mapper_receiver0_irq;                                  // pio_sw:irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                  // jtag_uart:av_irq -> irq_mapper:receiver1_irq
	wire         irq_mapper_receiver2_irq;                                  // spi_master:irq -> irq_mapper:receiver2_irq
	wire  [15:0] niosv_g_platform_irq_rx_irq;                               // irq_mapper:sender_irq -> niosv_g:platform_irq_rx_irq
	wire         rst_controller_reset_out_reset;                            // rst_controller:reset_out -> [irq_mapper:reset, jtag_uart:rst_n, niosv_g:reset_reset, onchip_memory:reset, pio_sw:reset_n, rst_translator:in_reset, spi_master:reset_n, sysid_qsys:reset_n]
	wire         rst_controller_reset_out_reset_req;                        // rst_controller:reset_req -> [onchip_memory:reset_req, rst_translator:reset_req_in]
	wire         rst_controller_001_reset_out_reset;                        // rst_controller_001:reset_out -> [mm_bridge_peripheral:reset, mm_interconnect_0:mm_bridge_peripheral_reset_reset_bridge_in_reset_reset, mm_interconnect_0:niosv_g_reset_reset_bridge_in_reset_reset, mm_interconnect_1:jtag_uart_reset_reset_bridge_in_reset_reset, mm_interconnect_1:mm_bridge_peripheral_reset_reset_bridge_in_reset_reset]
	wire         rst_controller_002_reset_out_reset;                        // rst_controller_002:reset_out -> reset_bridge:in_reset_n
	wire         reset_release_ninit_done_reset;                            // reset_release:ninit_done -> rst_controller_002:reset_in0
	wire         reset_in_out_reset_reset;                                  // reset_in:out_reset_n -> rst_controller_002:reset_in1

	clock_in clock_in (
		.in_clk  (clk_clk),              //   input,  width = 1,  in_clk.clk
		.out_clk (clock_in_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	iopll iopll (
		.refclk   (clock_in_out_clk_clk),          //   input,  width = 1,  refclk.clk
		.rst      (~reset_bridge_out_reset_reset), //   input,  width = 1,   reset.reset
		.outclk_0 (iopll_outclk0_clk),             //  output,  width = 1, outclk0.clk
		.outclk_1 ()                               //  output,  width = 1, outclk1.clk
	);

	jtag_uart jtag_uart (
		.clk            (iopll_outclk0_clk),                                         //   input,   width = 1,               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                           //   input,   width = 1,             reset.reset_n
		.av_chipselect  (mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect),  //   input,   width = 1, avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_1_jtag_uart_avalon_jtag_slave_address),     //   input,   width = 1,                  .address
		.av_read_n      (~mm_interconnect_1_jtag_uart_avalon_jtag_slave_read),       //   input,   width = 1,                  .read_n
		.av_readdata    (mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata),    //  output,  width = 32,                  .readdata
		.av_write_n     (~mm_interconnect_1_jtag_uart_avalon_jtag_slave_write),      //   input,   width = 1,                  .write_n
		.av_writedata   (mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata),   //   input,  width = 32,                  .writedata
		.av_waitrequest (mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest), //  output,   width = 1,                  .waitrequest
		.av_irq         (irq_mapper_receiver1_irq)                                   //  output,   width = 1,               irq.irq
	);

	mm_bridge_peripheral mm_bridge_peripheral (
		.clk              (iopll_outclk0_clk),                                       //   input,   width = 1,   clk.clk
		.reset            (rst_controller_001_reset_out_reset),                      //   input,   width = 1, reset.reset
		.s0_waitrequest   (mm_interconnect_0_mm_bridge_peripheral_s0_waitrequest),   //  output,   width = 1,    s0.waitrequest
		.s0_readdata      (mm_interconnect_0_mm_bridge_peripheral_s0_readdata),      //  output,  width = 32,      .readdata
		.s0_readdatavalid (mm_interconnect_0_mm_bridge_peripheral_s0_readdatavalid), //  output,   width = 1,      .readdatavalid
		.s0_burstcount    (mm_interconnect_0_mm_bridge_peripheral_s0_burstcount),    //   input,   width = 1,      .burstcount
		.s0_writedata     (mm_interconnect_0_mm_bridge_peripheral_s0_writedata),     //   input,  width = 32,      .writedata
		.s0_address       (mm_interconnect_0_mm_bridge_peripheral_s0_address),       //   input,  width = 19,      .address
		.s0_write         (mm_interconnect_0_mm_bridge_peripheral_s0_write),         //   input,   width = 1,      .write
		.s0_read          (mm_interconnect_0_mm_bridge_peripheral_s0_read),          //   input,   width = 1,      .read
		.s0_byteenable    (mm_interconnect_0_mm_bridge_peripheral_s0_byteenable),    //   input,   width = 4,      .byteenable
		.s0_debugaccess   (mm_interconnect_0_mm_bridge_peripheral_s0_debugaccess),   //   input,   width = 1,      .debugaccess
		.m0_waitrequest   (mm_bridge_peripheral_m0_waitrequest),                     //   input,   width = 1,    m0.waitrequest
		.m0_readdata      (mm_bridge_peripheral_m0_readdata),                        //   input,  width = 32,      .readdata
		.m0_readdatavalid (mm_bridge_peripheral_m0_readdatavalid),                   //   input,   width = 1,      .readdatavalid
		.m0_burstcount    (mm_bridge_peripheral_m0_burstcount),                      //  output,   width = 1,      .burstcount
		.m0_writedata     (mm_bridge_peripheral_m0_writedata),                       //  output,  width = 32,      .writedata
		.m0_address       (mm_bridge_peripheral_m0_address),                         //  output,  width = 19,      .address
		.m0_write         (mm_bridge_peripheral_m0_write),                           //  output,   width = 1,      .write
		.m0_read          (mm_bridge_peripheral_m0_read),                            //  output,   width = 1,      .read
		.m0_byteenable    (mm_bridge_peripheral_m0_byteenable),                      //  output,   width = 4,      .byteenable
		.m0_debugaccess   (mm_bridge_peripheral_m0_debugaccess)                      //  output,   width = 1,      .debugaccess
	);

	niosv_g niosv_g (
		.clk                          (iopll_outclk0_clk),                                      //   input,   width = 1,                 clk.clk
		.reset_reset                  (rst_controller_reset_out_reset),                         //   input,   width = 1,               reset.reset
		.platform_irq_rx_irq          (niosv_g_platform_irq_rx_irq),                            //   input,  width = 16,     platform_irq_rx.irq
		.instruction_manager_awaddr   (niosv_g_instruction_manager_awaddr),                     //  output,  width = 32, instruction_manager.awaddr
		.instruction_manager_awlen    (niosv_g_instruction_manager_awlen),                      //  output,   width = 8,                    .awlen
		.instruction_manager_awsize   (niosv_g_instruction_manager_awsize),                     //  output,   width = 3,                    .awsize
		.instruction_manager_awburst  (niosv_g_instruction_manager_awburst),                    //  output,   width = 2,                    .awburst
		.instruction_manager_awprot   (niosv_g_instruction_manager_awprot),                     //  output,   width = 3,                    .awprot
		.instruction_manager_awvalid  (niosv_g_instruction_manager_awvalid),                    //  output,   width = 1,                    .awvalid
		.instruction_manager_awready  (niosv_g_instruction_manager_awready),                    //   input,   width = 1,                    .awready
		.instruction_manager_wdata    (niosv_g_instruction_manager_wdata),                      //  output,  width = 32,                    .wdata
		.instruction_manager_wstrb    (niosv_g_instruction_manager_wstrb),                      //  output,   width = 4,                    .wstrb
		.instruction_manager_wlast    (niosv_g_instruction_manager_wlast),                      //  output,   width = 1,                    .wlast
		.instruction_manager_wvalid   (niosv_g_instruction_manager_wvalid),                     //  output,   width = 1,                    .wvalid
		.instruction_manager_wready   (niosv_g_instruction_manager_wready),                     //   input,   width = 1,                    .wready
		.instruction_manager_bresp    (niosv_g_instruction_manager_bresp),                      //   input,   width = 2,                    .bresp
		.instruction_manager_bvalid   (niosv_g_instruction_manager_bvalid),                     //   input,   width = 1,                    .bvalid
		.instruction_manager_bready   (niosv_g_instruction_manager_bready),                     //  output,   width = 1,                    .bready
		.instruction_manager_araddr   (niosv_g_instruction_manager_araddr),                     //  output,  width = 32,                    .araddr
		.instruction_manager_arlen    (niosv_g_instruction_manager_arlen),                      //  output,   width = 8,                    .arlen
		.instruction_manager_arsize   (niosv_g_instruction_manager_arsize),                     //  output,   width = 3,                    .arsize
		.instruction_manager_arburst  (niosv_g_instruction_manager_arburst),                    //  output,   width = 2,                    .arburst
		.instruction_manager_arprot   (niosv_g_instruction_manager_arprot),                     //  output,   width = 3,                    .arprot
		.instruction_manager_arvalid  (niosv_g_instruction_manager_arvalid),                    //  output,   width = 1,                    .arvalid
		.instruction_manager_arready  (niosv_g_instruction_manager_arready),                    //   input,   width = 1,                    .arready
		.instruction_manager_rdata    (niosv_g_instruction_manager_rdata),                      //   input,  width = 32,                    .rdata
		.instruction_manager_rresp    (niosv_g_instruction_manager_rresp),                      //   input,   width = 2,                    .rresp
		.instruction_manager_rlast    (niosv_g_instruction_manager_rlast),                      //   input,   width = 1,                    .rlast
		.instruction_manager_rvalid   (niosv_g_instruction_manager_rvalid),                     //   input,   width = 1,                    .rvalid
		.instruction_manager_rready   (niosv_g_instruction_manager_rready),                     //  output,   width = 1,                    .rready
		.data_manager_awaddr          (niosv_g_data_manager_awaddr),                            //  output,  width = 32,        data_manager.awaddr
		.data_manager_awlen           (niosv_g_data_manager_awlen),                             //  output,   width = 8,                    .awlen
		.data_manager_awsize          (niosv_g_data_manager_awsize),                            //  output,   width = 3,                    .awsize
		.data_manager_awprot          (niosv_g_data_manager_awprot),                            //  output,   width = 3,                    .awprot
		.data_manager_awvalid         (niosv_g_data_manager_awvalid),                           //  output,   width = 1,                    .awvalid
		.data_manager_awready         (niosv_g_data_manager_awready),                           //   input,   width = 1,                    .awready
		.data_manager_wdata           (niosv_g_data_manager_wdata),                             //  output,  width = 32,                    .wdata
		.data_manager_wstrb           (niosv_g_data_manager_wstrb),                             //  output,   width = 4,                    .wstrb
		.data_manager_wlast           (niosv_g_data_manager_wlast),                             //  output,   width = 1,                    .wlast
		.data_manager_wvalid          (niosv_g_data_manager_wvalid),                            //  output,   width = 1,                    .wvalid
		.data_manager_wready          (niosv_g_data_manager_wready),                            //   input,   width = 1,                    .wready
		.data_manager_bresp           (niosv_g_data_manager_bresp),                             //   input,   width = 2,                    .bresp
		.data_manager_bvalid          (niosv_g_data_manager_bvalid),                            //   input,   width = 1,                    .bvalid
		.data_manager_bready          (niosv_g_data_manager_bready),                            //  output,   width = 1,                    .bready
		.data_manager_araddr          (niosv_g_data_manager_araddr),                            //  output,  width = 32,                    .araddr
		.data_manager_arlen           (niosv_g_data_manager_arlen),                             //  output,   width = 8,                    .arlen
		.data_manager_arsize          (niosv_g_data_manager_arsize),                            //  output,   width = 3,                    .arsize
		.data_manager_arprot          (niosv_g_data_manager_arprot),                            //  output,   width = 3,                    .arprot
		.data_manager_arvalid         (niosv_g_data_manager_arvalid),                           //  output,   width = 1,                    .arvalid
		.data_manager_arready         (niosv_g_data_manager_arready),                           //   input,   width = 1,                    .arready
		.data_manager_rdata           (niosv_g_data_manager_rdata),                             //   input,  width = 32,                    .rdata
		.data_manager_rresp           (niosv_g_data_manager_rresp),                             //   input,   width = 2,                    .rresp
		.data_manager_rlast           (niosv_g_data_manager_rlast),                             //   input,   width = 1,                    .rlast
		.data_manager_rvalid          (niosv_g_data_manager_rvalid),                            //   input,   width = 1,                    .rvalid
		.data_manager_rready          (niosv_g_data_manager_rready),                            //  output,   width = 1,                    .rready
		.timer_sw_agent_address       (mm_interconnect_0_niosv_g_timer_sw_agent_address),       //   input,   width = 6,      timer_sw_agent.address
		.timer_sw_agent_byteenable    (mm_interconnect_0_niosv_g_timer_sw_agent_byteenable),    //   input,   width = 4,                    .byteenable
		.timer_sw_agent_read          (mm_interconnect_0_niosv_g_timer_sw_agent_read),          //   input,   width = 1,                    .read
		.timer_sw_agent_readdata      (mm_interconnect_0_niosv_g_timer_sw_agent_readdata),      //  output,  width = 32,                    .readdata
		.timer_sw_agent_write         (mm_interconnect_0_niosv_g_timer_sw_agent_write),         //   input,   width = 1,                    .write
		.timer_sw_agent_writedata     (mm_interconnect_0_niosv_g_timer_sw_agent_writedata),     //   input,  width = 32,                    .writedata
		.timer_sw_agent_waitrequest   (mm_interconnect_0_niosv_g_timer_sw_agent_waitrequest),   //  output,   width = 1,                    .waitrequest
		.timer_sw_agent_readdatavalid (mm_interconnect_0_niosv_g_timer_sw_agent_readdatavalid), //  output,   width = 1,                    .readdatavalid
		.dm_agent_address             (mm_interconnect_0_niosv_g_dm_agent_address),             //   input,  width = 16,            dm_agent.address
		.dm_agent_read                (mm_interconnect_0_niosv_g_dm_agent_read),                //   input,   width = 1,                    .read
		.dm_agent_readdata            (mm_interconnect_0_niosv_g_dm_agent_readdata),            //  output,  width = 32,                    .readdata
		.dm_agent_write               (mm_interconnect_0_niosv_g_dm_agent_write),               //   input,   width = 1,                    .write
		.dm_agent_writedata           (mm_interconnect_0_niosv_g_dm_agent_writedata),           //   input,  width = 32,                    .writedata
		.dm_agent_waitrequest         (mm_interconnect_0_niosv_g_dm_agent_waitrequest),         //  output,   width = 1,                    .waitrequest
		.dm_agent_readdatavalid       (mm_interconnect_0_niosv_g_dm_agent_readdatavalid)        //  output,   width = 1,                    .readdatavalid
	);

	onchip_memory onchip_memory (
		.clk        (iopll_outclk0_clk),                             //   input,   width = 1,   clk1.clk
		.address    (mm_interconnect_0_onchip_memory_s1_address),    //   input,  width = 16,     s1.address
		.read       (mm_interconnect_0_onchip_memory_s1_read),       //   input,   width = 1,       .read
		.readdata   (mm_interconnect_0_onchip_memory_s1_readdata),   //  output,  width = 32,       .readdata
		.byteenable (mm_interconnect_0_onchip_memory_s1_byteenable), //   input,   width = 4,       .byteenable
		.write      (mm_interconnect_0_onchip_memory_s1_write),      //   input,   width = 1,       .write
		.writedata  (mm_interconnect_0_onchip_memory_s1_writedata),  //   input,  width = 32,       .writedata
		.reset      (rst_controller_reset_out_reset),                //   input,   width = 1, reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)             //   input,   width = 1,       .reset_req
	);

	pio_sw pio_sw (
		.clk        (iopll_outclk0_clk),                      //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),        //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_1_pio_sw_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_1_pio_sw_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_1_pio_sw_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_1_pio_sw_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_1_pio_sw_s1_readdata),   //  output,  width = 32,                    .readdata
		.in_port    (sw_external_connection_export),          //   input,  width = 10, external_connection.export
		.irq        (irq_mapper_receiver0_irq)                //  output,   width = 1,                 irq.irq
	);

	reset_bridge reset_bridge (
		.clk         (clock_in_out_clk_clk),                //   input,  width = 1,       clk.clk
		.in_reset_n  (~rst_controller_002_reset_out_reset), //   input,  width = 1,  in_reset.reset_n
		.out_reset_n (reset_bridge_out_reset_reset)         //  output,  width = 1, out_reset.reset_n
	);

	reset_in reset_in (
		.clk         (clock_in_out_clk_clk),     //   input,  width = 1,       clk.clk
		.in_reset_n  (reset_reset_n),            //   input,  width = 1,  in_reset.reset_n
		.out_reset_n (reset_in_out_reset_reset)  //  output,  width = 1, out_reset.reset_n
	);

	reset_release reset_release (
		.ninit_done (reset_release_ninit_done_reset)  //  output,  width = 1, ninit_done.reset
	);

	nios_system_spi_0 spi_master (
		.clk           (iopll_outclk0_clk),                                        //   input,   width = 1,              clk.clk
		.reset_n       (~rst_controller_reset_out_reset),                          //   input,   width = 1,            reset.reset_n
		.data_from_cpu (mm_interconnect_1_spi_master_spi_control_port_writedata),  //   input,  width = 16, spi_control_port.writedata
		.data_to_cpu   (mm_interconnect_1_spi_master_spi_control_port_readdata),   //  output,  width = 16,                 .readdata
		.mem_addr      (mm_interconnect_1_spi_master_spi_control_port_address),    //   input,   width = 3,                 .address
		.read_n        (~mm_interconnect_1_spi_master_spi_control_port_read),      //   input,   width = 1,                 .read_n
		.spi_select    (mm_interconnect_1_spi_master_spi_control_port_chipselect), //   input,   width = 1,                 .chipselect
		.write_n       (~mm_interconnect_1_spi_master_spi_control_port_write),     //   input,   width = 1,                 .write_n
		.irq           (irq_mapper_receiver2_irq),                                 //  output,   width = 1,              irq.irq
		.MISO          (spi_master_external_MISO),                                 //   input,   width = 1,         external.MISO
		.MOSI          (spi_master_external_MOSI),                                 //  output,   width = 1,                 .MOSI
		.SCLK          (spi_master_external_SCLK),                                 //  output,   width = 1,                 .SCLK
		.SS_n          (spi_master_external_SS_n)                                  //  output,   width = 1,                 .SS_n
	);

	sysid_qsys sysid_qsys (
		.clock    (iopll_outclk0_clk),                                   //   input,   width = 1,           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //   input,   width = 1,         reset.reset_n
		.readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata), //  output,  width = 32, control_slave.readdata
		.address  (mm_interconnect_1_sysid_qsys_control_slave_address)   //   input,   width = 1,              .address
	);

	nios_system_altera_mm_interconnect_1920_gvlg2ai mm_interconnect_0 (
		.niosv_g_data_manager_awaddr                            (niosv_g_data_manager_awaddr),                             //   input,  width = 32,                             niosv_g_data_manager.awaddr
		.niosv_g_data_manager_awlen                             (niosv_g_data_manager_awlen),                              //   input,   width = 8,                                                 .awlen
		.niosv_g_data_manager_awsize                            (niosv_g_data_manager_awsize),                             //   input,   width = 3,                                                 .awsize
		.niosv_g_data_manager_awprot                            (niosv_g_data_manager_awprot),                             //   input,   width = 3,                                                 .awprot
		.niosv_g_data_manager_awvalid                           (niosv_g_data_manager_awvalid),                            //   input,   width = 1,                                                 .awvalid
		.niosv_g_data_manager_awready                           (niosv_g_data_manager_awready),                            //  output,   width = 1,                                                 .awready
		.niosv_g_data_manager_wdata                             (niosv_g_data_manager_wdata),                              //   input,  width = 32,                                                 .wdata
		.niosv_g_data_manager_wstrb                             (niosv_g_data_manager_wstrb),                              //   input,   width = 4,                                                 .wstrb
		.niosv_g_data_manager_wlast                             (niosv_g_data_manager_wlast),                              //   input,   width = 1,                                                 .wlast
		.niosv_g_data_manager_wvalid                            (niosv_g_data_manager_wvalid),                             //   input,   width = 1,                                                 .wvalid
		.niosv_g_data_manager_wready                            (niosv_g_data_manager_wready),                             //  output,   width = 1,                                                 .wready
		.niosv_g_data_manager_bresp                             (niosv_g_data_manager_bresp),                              //  output,   width = 2,                                                 .bresp
		.niosv_g_data_manager_bvalid                            (niosv_g_data_manager_bvalid),                             //  output,   width = 1,                                                 .bvalid
		.niosv_g_data_manager_bready                            (niosv_g_data_manager_bready),                             //   input,   width = 1,                                                 .bready
		.niosv_g_data_manager_araddr                            (niosv_g_data_manager_araddr),                             //   input,  width = 32,                                                 .araddr
		.niosv_g_data_manager_arlen                             (niosv_g_data_manager_arlen),                              //   input,   width = 8,                                                 .arlen
		.niosv_g_data_manager_arsize                            (niosv_g_data_manager_arsize),                             //   input,   width = 3,                                                 .arsize
		.niosv_g_data_manager_arprot                            (niosv_g_data_manager_arprot),                             //   input,   width = 3,                                                 .arprot
		.niosv_g_data_manager_arvalid                           (niosv_g_data_manager_arvalid),                            //   input,   width = 1,                                                 .arvalid
		.niosv_g_data_manager_arready                           (niosv_g_data_manager_arready),                            //  output,   width = 1,                                                 .arready
		.niosv_g_data_manager_rdata                             (niosv_g_data_manager_rdata),                              //  output,  width = 32,                                                 .rdata
		.niosv_g_data_manager_rresp                             (niosv_g_data_manager_rresp),                              //  output,   width = 2,                                                 .rresp
		.niosv_g_data_manager_rlast                             (niosv_g_data_manager_rlast),                              //  output,   width = 1,                                                 .rlast
		.niosv_g_data_manager_rvalid                            (niosv_g_data_manager_rvalid),                             //  output,   width = 1,                                                 .rvalid
		.niosv_g_data_manager_rready                            (niosv_g_data_manager_rready),                             //   input,   width = 1,                                                 .rready
		.niosv_g_instruction_manager_awaddr                     (niosv_g_instruction_manager_awaddr),                      //   input,  width = 32,                      niosv_g_instruction_manager.awaddr
		.niosv_g_instruction_manager_awlen                      (niosv_g_instruction_manager_awlen),                       //   input,   width = 8,                                                 .awlen
		.niosv_g_instruction_manager_awsize                     (niosv_g_instruction_manager_awsize),                      //   input,   width = 3,                                                 .awsize
		.niosv_g_instruction_manager_awburst                    (niosv_g_instruction_manager_awburst),                     //   input,   width = 2,                                                 .awburst
		.niosv_g_instruction_manager_awprot                     (niosv_g_instruction_manager_awprot),                      //   input,   width = 3,                                                 .awprot
		.niosv_g_instruction_manager_awvalid                    (niosv_g_instruction_manager_awvalid),                     //   input,   width = 1,                                                 .awvalid
		.niosv_g_instruction_manager_awready                    (niosv_g_instruction_manager_awready),                     //  output,   width = 1,                                                 .awready
		.niosv_g_instruction_manager_wdata                      (niosv_g_instruction_manager_wdata),                       //   input,  width = 32,                                                 .wdata
		.niosv_g_instruction_manager_wstrb                      (niosv_g_instruction_manager_wstrb),                       //   input,   width = 4,                                                 .wstrb
		.niosv_g_instruction_manager_wlast                      (niosv_g_instruction_manager_wlast),                       //   input,   width = 1,                                                 .wlast
		.niosv_g_instruction_manager_wvalid                     (niosv_g_instruction_manager_wvalid),                      //   input,   width = 1,                                                 .wvalid
		.niosv_g_instruction_manager_wready                     (niosv_g_instruction_manager_wready),                      //  output,   width = 1,                                                 .wready
		.niosv_g_instruction_manager_bresp                      (niosv_g_instruction_manager_bresp),                       //  output,   width = 2,                                                 .bresp
		.niosv_g_instruction_manager_bvalid                     (niosv_g_instruction_manager_bvalid),                      //  output,   width = 1,                                                 .bvalid
		.niosv_g_instruction_manager_bready                     (niosv_g_instruction_manager_bready),                      //   input,   width = 1,                                                 .bready
		.niosv_g_instruction_manager_araddr                     (niosv_g_instruction_manager_araddr),                      //   input,  width = 32,                                                 .araddr
		.niosv_g_instruction_manager_arlen                      (niosv_g_instruction_manager_arlen),                       //   input,   width = 8,                                                 .arlen
		.niosv_g_instruction_manager_arsize                     (niosv_g_instruction_manager_arsize),                      //   input,   width = 3,                                                 .arsize
		.niosv_g_instruction_manager_arburst                    (niosv_g_instruction_manager_arburst),                     //   input,   width = 2,                                                 .arburst
		.niosv_g_instruction_manager_arprot                     (niosv_g_instruction_manager_arprot),                      //   input,   width = 3,                                                 .arprot
		.niosv_g_instruction_manager_arvalid                    (niosv_g_instruction_manager_arvalid),                     //   input,   width = 1,                                                 .arvalid
		.niosv_g_instruction_manager_arready                    (niosv_g_instruction_manager_arready),                     //  output,   width = 1,                                                 .arready
		.niosv_g_instruction_manager_rdata                      (niosv_g_instruction_manager_rdata),                       //  output,  width = 32,                                                 .rdata
		.niosv_g_instruction_manager_rresp                      (niosv_g_instruction_manager_rresp),                       //  output,   width = 2,                                                 .rresp
		.niosv_g_instruction_manager_rlast                      (niosv_g_instruction_manager_rlast),                       //  output,   width = 1,                                                 .rlast
		.niosv_g_instruction_manager_rvalid                     (niosv_g_instruction_manager_rvalid),                      //  output,   width = 1,                                                 .rvalid
		.niosv_g_instruction_manager_rready                     (niosv_g_instruction_manager_rready),                      //   input,   width = 1,                                                 .rready
		.niosv_g_dm_agent_address                               (mm_interconnect_0_niosv_g_dm_agent_address),              //  output,  width = 16,                                 niosv_g_dm_agent.address
		.niosv_g_dm_agent_write                                 (mm_interconnect_0_niosv_g_dm_agent_write),                //  output,   width = 1,                                                 .write
		.niosv_g_dm_agent_read                                  (mm_interconnect_0_niosv_g_dm_agent_read),                 //  output,   width = 1,                                                 .read
		.niosv_g_dm_agent_readdata                              (mm_interconnect_0_niosv_g_dm_agent_readdata),             //   input,  width = 32,                                                 .readdata
		.niosv_g_dm_agent_writedata                             (mm_interconnect_0_niosv_g_dm_agent_writedata),            //  output,  width = 32,                                                 .writedata
		.niosv_g_dm_agent_readdatavalid                         (mm_interconnect_0_niosv_g_dm_agent_readdatavalid),        //   input,   width = 1,                                                 .readdatavalid
		.niosv_g_dm_agent_waitrequest                           (mm_interconnect_0_niosv_g_dm_agent_waitrequest),          //   input,   width = 1,                                                 .waitrequest
		.mm_bridge_peripheral_s0_address                        (mm_interconnect_0_mm_bridge_peripheral_s0_address),       //  output,  width = 19,                          mm_bridge_peripheral_s0.address
		.mm_bridge_peripheral_s0_write                          (mm_interconnect_0_mm_bridge_peripheral_s0_write),         //  output,   width = 1,                                                 .write
		.mm_bridge_peripheral_s0_read                           (mm_interconnect_0_mm_bridge_peripheral_s0_read),          //  output,   width = 1,                                                 .read
		.mm_bridge_peripheral_s0_readdata                       (mm_interconnect_0_mm_bridge_peripheral_s0_readdata),      //   input,  width = 32,                                                 .readdata
		.mm_bridge_peripheral_s0_writedata                      (mm_interconnect_0_mm_bridge_peripheral_s0_writedata),     //  output,  width = 32,                                                 .writedata
		.mm_bridge_peripheral_s0_burstcount                     (mm_interconnect_0_mm_bridge_peripheral_s0_burstcount),    //  output,   width = 1,                                                 .burstcount
		.mm_bridge_peripheral_s0_byteenable                     (mm_interconnect_0_mm_bridge_peripheral_s0_byteenable),    //  output,   width = 4,                                                 .byteenable
		.mm_bridge_peripheral_s0_readdatavalid                  (mm_interconnect_0_mm_bridge_peripheral_s0_readdatavalid), //   input,   width = 1,                                                 .readdatavalid
		.mm_bridge_peripheral_s0_waitrequest                    (mm_interconnect_0_mm_bridge_peripheral_s0_waitrequest),   //   input,   width = 1,                                                 .waitrequest
		.mm_bridge_peripheral_s0_debugaccess                    (mm_interconnect_0_mm_bridge_peripheral_s0_debugaccess),   //  output,   width = 1,                                                 .debugaccess
		.onchip_memory_s1_address                               (mm_interconnect_0_onchip_memory_s1_address),              //  output,  width = 16,                                 onchip_memory_s1.address
		.onchip_memory_s1_write                                 (mm_interconnect_0_onchip_memory_s1_write),                //  output,   width = 1,                                                 .write
		.onchip_memory_s1_read                                  (mm_interconnect_0_onchip_memory_s1_read),                 //  output,   width = 1,                                                 .read
		.onchip_memory_s1_readdata                              (mm_interconnect_0_onchip_memory_s1_readdata),             //   input,  width = 32,                                                 .readdata
		.onchip_memory_s1_writedata                             (mm_interconnect_0_onchip_memory_s1_writedata),            //  output,  width = 32,                                                 .writedata
		.onchip_memory_s1_byteenable                            (mm_interconnect_0_onchip_memory_s1_byteenable),           //  output,   width = 4,                                                 .byteenable
		.niosv_g_timer_sw_agent_address                         (mm_interconnect_0_niosv_g_timer_sw_agent_address),        //  output,   width = 6,                           niosv_g_timer_sw_agent.address
		.niosv_g_timer_sw_agent_write                           (mm_interconnect_0_niosv_g_timer_sw_agent_write),          //  output,   width = 1,                                                 .write
		.niosv_g_timer_sw_agent_read                            (mm_interconnect_0_niosv_g_timer_sw_agent_read),           //  output,   width = 1,                                                 .read
		.niosv_g_timer_sw_agent_readdata                        (mm_interconnect_0_niosv_g_timer_sw_agent_readdata),       //   input,  width = 32,                                                 .readdata
		.niosv_g_timer_sw_agent_writedata                       (mm_interconnect_0_niosv_g_timer_sw_agent_writedata),      //  output,  width = 32,                                                 .writedata
		.niosv_g_timer_sw_agent_byteenable                      (mm_interconnect_0_niosv_g_timer_sw_agent_byteenable),     //  output,   width = 4,                                                 .byteenable
		.niosv_g_timer_sw_agent_readdatavalid                   (mm_interconnect_0_niosv_g_timer_sw_agent_readdatavalid),  //   input,   width = 1,                                                 .readdatavalid
		.niosv_g_timer_sw_agent_waitrequest                     (mm_interconnect_0_niosv_g_timer_sw_agent_waitrequest),    //   input,   width = 1,                                                 .waitrequest
		.niosv_g_reset_reset_bridge_in_reset_reset              (rst_controller_001_reset_out_reset),                      //   input,   width = 1,              niosv_g_reset_reset_bridge_in_reset.reset
		.mm_bridge_peripheral_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),                      //   input,   width = 1, mm_bridge_peripheral_reset_reset_bridge_in_reset.reset
		.iopll_outclk0_clk                                      (iopll_outclk0_clk)                                        //   input,   width = 1,                                    iopll_outclk0.clk
	);

	nios_system_altera_mm_interconnect_1920_g7zuaki mm_interconnect_1 (
		.mm_bridge_peripheral_m0_address                        (mm_bridge_peripheral_m0_address),                           //   input,  width = 19,                          mm_bridge_peripheral_m0.address
		.mm_bridge_peripheral_m0_waitrequest                    (mm_bridge_peripheral_m0_waitrequest),                       //  output,   width = 1,                                                 .waitrequest
		.mm_bridge_peripheral_m0_burstcount                     (mm_bridge_peripheral_m0_burstcount),                        //   input,   width = 1,                                                 .burstcount
		.mm_bridge_peripheral_m0_byteenable                     (mm_bridge_peripheral_m0_byteenable),                        //   input,   width = 4,                                                 .byteenable
		.mm_bridge_peripheral_m0_read                           (mm_bridge_peripheral_m0_read),                              //   input,   width = 1,                                                 .read
		.mm_bridge_peripheral_m0_readdata                       (mm_bridge_peripheral_m0_readdata),                          //  output,  width = 32,                                                 .readdata
		.mm_bridge_peripheral_m0_readdatavalid                  (mm_bridge_peripheral_m0_readdatavalid),                     //  output,   width = 1,                                                 .readdatavalid
		.mm_bridge_peripheral_m0_write                          (mm_bridge_peripheral_m0_write),                             //   input,   width = 1,                                                 .write
		.mm_bridge_peripheral_m0_writedata                      (mm_bridge_peripheral_m0_writedata),                         //   input,  width = 32,                                                 .writedata
		.mm_bridge_peripheral_m0_debugaccess                    (mm_bridge_peripheral_m0_debugaccess),                       //   input,   width = 1,                                                 .debugaccess
		.jtag_uart_avalon_jtag_slave_address                    (mm_interconnect_1_jtag_uart_avalon_jtag_slave_address),     //  output,   width = 1,                      jtag_uart_avalon_jtag_slave.address
		.jtag_uart_avalon_jtag_slave_write                      (mm_interconnect_1_jtag_uart_avalon_jtag_slave_write),       //  output,   width = 1,                                                 .write
		.jtag_uart_avalon_jtag_slave_read                       (mm_interconnect_1_jtag_uart_avalon_jtag_slave_read),        //  output,   width = 1,                                                 .read
		.jtag_uart_avalon_jtag_slave_readdata                   (mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata),    //   input,  width = 32,                                                 .readdata
		.jtag_uart_avalon_jtag_slave_writedata                  (mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata),   //  output,  width = 32,                                                 .writedata
		.jtag_uart_avalon_jtag_slave_waitrequest                (mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest), //   input,   width = 1,                                                 .waitrequest
		.jtag_uart_avalon_jtag_slave_chipselect                 (mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect),  //  output,   width = 1,                                                 .chipselect
		.sysid_qsys_control_slave_address                       (mm_interconnect_1_sysid_qsys_control_slave_address),        //  output,   width = 1,                         sysid_qsys_control_slave.address
		.sysid_qsys_control_slave_readdata                      (mm_interconnect_1_sysid_qsys_control_slave_readdata),       //   input,  width = 32,                                                 .readdata
		.pio_sw_s1_address                                      (mm_interconnect_1_pio_sw_s1_address),                       //  output,   width = 2,                                        pio_sw_s1.address
		.pio_sw_s1_write                                        (mm_interconnect_1_pio_sw_s1_write),                         //  output,   width = 1,                                                 .write
		.pio_sw_s1_readdata                                     (mm_interconnect_1_pio_sw_s1_readdata),                      //   input,  width = 32,                                                 .readdata
		.pio_sw_s1_writedata                                    (mm_interconnect_1_pio_sw_s1_writedata),                     //  output,  width = 32,                                                 .writedata
		.pio_sw_s1_chipselect                                   (mm_interconnect_1_pio_sw_s1_chipselect),                    //  output,   width = 1,                                                 .chipselect
		.spi_master_spi_control_port_address                    (mm_interconnect_1_spi_master_spi_control_port_address),     //  output,   width = 3,                      spi_master_spi_control_port.address
		.spi_master_spi_control_port_write                      (mm_interconnect_1_spi_master_spi_control_port_write),       //  output,   width = 1,                                                 .write
		.spi_master_spi_control_port_read                       (mm_interconnect_1_spi_master_spi_control_port_read),        //  output,   width = 1,                                                 .read
		.spi_master_spi_control_port_readdata                   (mm_interconnect_1_spi_master_spi_control_port_readdata),    //   input,  width = 16,                                                 .readdata
		.spi_master_spi_control_port_writedata                  (mm_interconnect_1_spi_master_spi_control_port_writedata),   //  output,  width = 16,                                                 .writedata
		.spi_master_spi_control_port_chipselect                 (mm_interconnect_1_spi_master_spi_control_port_chipselect),  //  output,   width = 1,                                                 .chipselect
		.mm_bridge_peripheral_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),                        //   input,   width = 1, mm_bridge_peripheral_reset_reset_bridge_in_reset.reset
		.jtag_uart_reset_reset_bridge_in_reset_reset            (rst_controller_001_reset_out_reset),                        //   input,   width = 1,            jtag_uart_reset_reset_bridge_in_reset.reset
		.iopll_outclk0_clk                                      (iopll_outclk0_clk)                                          //   input,   width = 1,                                    iopll_outclk0.clk
	);

	nios_system_altera_irq_mapper_2001_k3auftq irq_mapper (
		.clk           (iopll_outclk0_clk),              //   input,   width = 1,       clk.clk
		.reset         (rst_controller_reset_out_reset), //   input,   width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),       //   input,   width = 1, receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),       //   input,   width = 1, receiver1.irq
		.receiver2_irq (irq_mapper_receiver2_irq),       //   input,   width = 1, receiver2.irq
		.sender_irq    (niosv_g_platform_irq_rx_irq)     //  output,  width = 16,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_bridge_out_reset_reset),      //   input,  width = 1, reset_in0.reset
		.clk            (iopll_outclk0_clk),                  //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset),     //  output,  width = 1, reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req), //  output,  width = 1,          .reset_req
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (~reset_bridge_out_reset_reset),      //   input,  width = 1, reset_in0.reset
		.clk            (iopll_outclk0_clk),                  //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_002 (
		.reset_in0      (reset_release_ninit_done_reset),     //   input,  width = 1, reset_in0.reset
		.reset_in1      (~reset_in_out_reset_reset),          //   input,  width = 1, reset_in1.reset
		.clk            (clock_in_out_clk_clk),               //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_002_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
