# TCL File Generated by Component Editor 24.1
# Mon Jun 24 09:58:22 CST 2024
# DO NOT MODIFY


#
# core_sdram_axi4 "SDRAM AXI4 (opencores.org)" v1.1
#  2024.06.24.09:58:22
# SDRAM AXI4 Controller from opencores.org
#

#
# request TCL package from ACDS 24.1
#
package require -exact qsys 24.1


#
# module core_sdram_axi4
#
set_module_property DESCRIPTION "SDRAM AXI4 Controller from opencores.org"
set_module_property NAME core_sdram_axi4
set_module_property VERSION 1.3
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property BSP_CPU false
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "SDRAM AXI4 (opencores.org)"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property LOAD_ELABORATION_LIMIT 0
set_module_property PRE_COMP_MODULE_ENABLED false


#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL sdram_axi
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file sdram_axi.v VERILOG PATH sdram_axi.v TOP_LEVEL_FILE
add_fileset_file sdram_axi_core.v VERILOG PATH sdram_axi_core.v
add_fileset_file sdram_axi_pmem.v VERILOG PATH sdram_axi_pmem.v

add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL sdram_axi
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file sdram_axi.v VERILOG PATH sdram_axi.v
add_fileset_file sdram_axi_core.v VERILOG PATH sdram_axi_core.v
add_fileset_file sdram_axi_pmem.v VERILOG PATH sdram_axi_pmem.v


#
# parameters
#
add_parameter SDRAM_MHZ INTEGER 50
set_parameter_property SDRAM_MHZ DEFAULT_VALUE 50
set_parameter_property SDRAM_MHZ DISPLAY_NAME SDRAM_MHZ
set_parameter_property SDRAM_MHZ UNITS None
set_parameter_property SDRAM_MHZ ALLOWED_RANGES -2147483648:2147483647
set_parameter_property SDRAM_MHZ AFFECTS_GENERATION false
set_parameter_property SDRAM_MHZ HDL_PARAMETER true
set_parameter_property SDRAM_MHZ EXPORT true
add_parameter SDRAM_ADDR_W INTEGER 24
set_parameter_property SDRAM_ADDR_W DEFAULT_VALUE 24
set_parameter_property SDRAM_ADDR_W DISPLAY_NAME SDRAM_ADDR_W
set_parameter_property SDRAM_ADDR_W UNITS None
set_parameter_property SDRAM_ADDR_W ALLOWED_RANGES -2147483648:2147483647
set_parameter_property SDRAM_ADDR_W AFFECTS_GENERATION false
set_parameter_property SDRAM_ADDR_W HDL_PARAMETER true
set_parameter_property SDRAM_ADDR_W EXPORT true
add_parameter SDRAM_COL_W INTEGER 9
set_parameter_property SDRAM_COL_W DEFAULT_VALUE 9
set_parameter_property SDRAM_COL_W DISPLAY_NAME SDRAM_COL_W
set_parameter_property SDRAM_COL_W UNITS None
set_parameter_property SDRAM_COL_W ALLOWED_RANGES -2147483648:2147483647
set_parameter_property SDRAM_COL_W AFFECTS_GENERATION false
set_parameter_property SDRAM_COL_W HDL_PARAMETER true
set_parameter_property SDRAM_COL_W EXPORT true
add_parameter SDRAM_READ_LATENCY INTEGER 2
set_parameter_property SDRAM_READ_LATENCY DEFAULT_VALUE 2
set_parameter_property SDRAM_READ_LATENCY DISPLAY_NAME SDRAM_READ_LATENCY
set_parameter_property SDRAM_READ_LATENCY UNITS None
set_parameter_property SDRAM_READ_LATENCY ALLOWED_RANGES -2147483648:2147483647
set_parameter_property SDRAM_READ_LATENCY AFFECTS_GENERATION false
set_parameter_property SDRAM_READ_LATENCY HDL_PARAMETER true
set_parameter_property SDRAM_READ_LATENCY EXPORT true


#
# display items
#


#
# connection point sdram
#
add_interface sdram conduit end
set_interface_property sdram associatedClock ""
set_interface_property sdram associatedReset ""
set_interface_property sdram ENABLED true
set_interface_property sdram EXPORT_OF ""
set_interface_property sdram PORT_NAME_MAP ""
set_interface_property sdram CMSIS_SVD_VARIABLES ""
set_interface_property sdram SVD_ADDRESS_GROUP ""
set_interface_property sdram IPXACT_REGISTER_MAP_VARIABLES ""
set_interface_property sdram SV_INTERFACE_TYPE ""
set_interface_property sdram SV_INTERFACE_MODPORT_TYPE ""

add_interface_port sdram sdram_cke_o cke Output 1
add_interface_port sdram sdram_cs_o cs_n Output 1
add_interface_port sdram sdram_ras_o ras_n Output 1
add_interface_port sdram sdram_cas_o cas_n Output 1
add_interface_port sdram sdram_we_o we_n Output 1
add_interface_port sdram sdram_dqm_o dqm Output 4
add_interface_port sdram sdram_addr_o addr Output 13
add_interface_port sdram sdram_ba_o ba Output 2
add_interface_port sdram sdram_data_output_o data_out Output 32
add_interface_port sdram sdram_data_out_en_o data_oe Output 1
add_interface_port sdram sdram_data_input_i data_in Input 32


#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
set_interface_property clock_sink IPXACT_REGISTER_MAP_VARIABLES ""
set_interface_property clock_sink SV_INTERFACE_TYPE ""
set_interface_property clock_sink SV_INTERFACE_MODPORT_TYPE ""

add_interface_port clock_sink clk_i clk Input 1


#
# connection point clock_sample_sink
#
add_interface clock_sample_sink clock end
set_interface_property clock_sample_sink ENABLED true
set_interface_property clock_sample_sink EXPORT_OF ""
set_interface_property clock_sample_sink PORT_NAME_MAP ""
set_interface_property clock_sample_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sample_sink SVD_ADDRESS_GROUP ""
set_interface_property clock_sample_sink IPXACT_REGISTER_MAP_VARIABLES ""
set_interface_property clock_sample_sink SV_INTERFACE_TYPE ""
set_interface_property clock_sample_sink SV_INTERFACE_MODPORT_TYPE ""

add_interface_port clock_sample_sink clk_sample_i clk Input 1


#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
set_interface_property reset_sink IPXACT_REGISTER_MAP_VARIABLES ""
set_interface_property reset_sink SV_INTERFACE_TYPE ""
set_interface_property reset_sink SV_INTERFACE_MODPORT_TYPE ""

add_interface_port reset_sink rst_i reset Input 1


#
# connection point axi4_slave
#
add_interface axi4_slave axi4 end
set_interface_property axi4_slave associatedClock clock_sink
set_interface_property axi4_slave associatedReset reset_sink
set_interface_property axi4_slave wakeupSignals false
set_interface_property axi4_slave uniqueIdSupport false
set_interface_property axi4_slave poison false
set_interface_property axi4_slave traceSignals false
set_interface_property axi4_slave readAcceptanceCapability 1
set_interface_property axi4_slave writeAcceptanceCapability 1
set_interface_property axi4_slave combinedAcceptanceCapability 1
set_interface_property axi4_slave readDataReorderingDepth 1
set_interface_property axi4_slave bridgesToMaster ""
set_interface_property axi4_slave dfhFeatureGuid 0
set_interface_property axi4_slave dfhGroupId 0
set_interface_property axi4_slave dfhParameterId ""
set_interface_property axi4_slave dfhParameterName ""
set_interface_property axi4_slave dfhParameterVersion ""
set_interface_property axi4_slave dfhParameterData ""
set_interface_property axi4_slave dfhParameterDataLength ""
set_interface_property axi4_slave dfhFeatureMajorVersion 0
set_interface_property axi4_slave dfhFeatureMinorVersion 0
set_interface_property axi4_slave dfhFeatureId 35
set_interface_property axi4_slave dfhFeatureType 3
set_interface_property axi4_slave ENABLED true
set_interface_property axi4_slave EXPORT_OF ""
set_interface_property axi4_slave PORT_NAME_MAP ""
set_interface_property axi4_slave CMSIS_SVD_VARIABLES ""
set_interface_property axi4_slave SVD_ADDRESS_GROUP ""
set_interface_property axi4_slave IPXACT_REGISTER_MAP_VARIABLES ""
set_interface_property axi4_slave SV_INTERFACE_TYPE ""
set_interface_property axi4_slave SV_INTERFACE_MODPORT_TYPE ""

add_interface_port axi4_slave inport_awvalid_i awvalid Input 1
add_interface_port axi4_slave inport_awaddr_i awaddr Input "(SDRAM_ADDR_W) - (0) + 2"
add_interface_port axi4_slave inport_awid_i awid Input 4
add_interface_port axi4_slave inport_awlen_i awlen Input 8
add_interface_port axi4_slave inport_awburst_i awburst Input 2
add_interface_port axi4_slave inport_wvalid_i wvalid Input 1
add_interface_port axi4_slave inport_wdata_i wdata Input 64
add_interface_port axi4_slave inport_wstrb_i wstrb Input 8
add_interface_port axi4_slave inport_wlast_i wlast Input 1
add_interface_port axi4_slave inport_bready_i bready Input 1
add_interface_port axi4_slave inport_arvalid_i arvalid Input 1
add_interface_port axi4_slave inport_araddr_i araddr Input "(SDRAM_ADDR_W) - (0) + 2"
add_interface_port axi4_slave inport_arid_i arid Input 4
add_interface_port axi4_slave inport_arlen_i arlen Input 8
add_interface_port axi4_slave inport_arburst_i arburst Input 2
add_interface_port axi4_slave inport_rready_i rready Input 1
add_interface_port axi4_slave inport_awready_o awready Output 1
add_interface_port axi4_slave inport_wready_o wready Output 1
add_interface_port axi4_slave inport_bvalid_o bvalid Output 1
add_interface_port axi4_slave inport_bresp_o bresp Output 2
add_interface_port axi4_slave inport_bid_o bid Output 4
add_interface_port axi4_slave inport_arready_o arready Output 1
add_interface_port axi4_slave inport_rvalid_o rvalid Output 1
add_interface_port axi4_slave inport_rdata_o rdata Output 64
add_interface_port axi4_slave inport_rresp_o rresp Output 2
add_interface_port axi4_slave inport_rid_o rid Output 4
add_interface_port axi4_slave inport_rlast_o rlast Output 1
add_interface_port axi4_slave inport_awsize_i awsize Input 3
add_interface_port axi4_slave inport_arsize_i arsize Input 3

