// nios_system_altera_mm_interconnect_1920_g7zuaki.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_altera_mm_interconnect_1920_g7zuaki (
		input  wire [18:0] mm_bridge_peripheral_m0_address,                        //                          mm_bridge_peripheral_m0.address
		output wire        mm_bridge_peripheral_m0_waitrequest,                    //                                                 .waitrequest
		input  wire [0:0]  mm_bridge_peripheral_m0_burstcount,                     //                                                 .burstcount
		input  wire [3:0]  mm_bridge_peripheral_m0_byteenable,                     //                                                 .byteenable
		input  wire        mm_bridge_peripheral_m0_read,                           //                                                 .read
		output wire [31:0] mm_bridge_peripheral_m0_readdata,                       //                                                 .readdata
		output wire        mm_bridge_peripheral_m0_readdatavalid,                  //                                                 .readdatavalid
		input  wire        mm_bridge_peripheral_m0_write,                          //                                                 .write
		input  wire [31:0] mm_bridge_peripheral_m0_writedata,                      //                                                 .writedata
		input  wire        mm_bridge_peripheral_m0_debugaccess,                    //                                                 .debugaccess
		output wire [0:0]  jtag_uart_avalon_jtag_slave_address,                    //                      jtag_uart_avalon_jtag_slave.address
		output wire        jtag_uart_avalon_jtag_slave_write,                      //                                                 .write
		output wire        jtag_uart_avalon_jtag_slave_read,                       //                                                 .read
		input  wire [31:0] jtag_uart_avalon_jtag_slave_readdata,                   //                                                 .readdata
		output wire [31:0] jtag_uart_avalon_jtag_slave_writedata,                  //                                                 .writedata
		input  wire        jtag_uart_avalon_jtag_slave_waitrequest,                //                                                 .waitrequest
		output wire        jtag_uart_avalon_jtag_slave_chipselect,                 //                                                 .chipselect
		output wire [0:0]  sysid_qsys_control_slave_address,                       //                         sysid_qsys_control_slave.address
		input  wire [31:0] sysid_qsys_control_slave_readdata,                      //                                                 .readdata
		output wire [1:0]  pio_sw_s1_address,                                      //                                        pio_sw_s1.address
		output wire        pio_sw_s1_write,                                        //                                                 .write
		input  wire [31:0] pio_sw_s1_readdata,                                     //                                                 .readdata
		output wire [31:0] pio_sw_s1_writedata,                                    //                                                 .writedata
		output wire        pio_sw_s1_chipselect,                                   //                                                 .chipselect
		output wire [2:0]  spi_master_spi_control_port_address,                    //                      spi_master_spi_control_port.address
		output wire        spi_master_spi_control_port_write,                      //                                                 .write
		output wire        spi_master_spi_control_port_read,                       //                                                 .read
		input  wire [15:0] spi_master_spi_control_port_readdata,                   //                                                 .readdata
		output wire [15:0] spi_master_spi_control_port_writedata,                  //                                                 .writedata
		output wire        spi_master_spi_control_port_chipselect,                 //                                                 .chipselect
		input  wire        mm_bridge_peripheral_reset_reset_bridge_in_reset_reset, // mm_bridge_peripheral_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        jtag_uart_reset_reset_bridge_in_reset_reset,            //            jtag_uart_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        iopll_outclk0_clk                                       //                                    iopll_outclk0.clk,          Clock Input
	);

	wire          mm_bridge_peripheral_m0_translator_avalon_universal_master_0_waitrequest;   // mm_bridge_peripheral_m0_agent:av_waitrequest -> mm_bridge_peripheral_m0_translator:uav_waitrequest
	wire   [31:0] mm_bridge_peripheral_m0_translator_avalon_universal_master_0_readdata;      // mm_bridge_peripheral_m0_agent:av_readdata -> mm_bridge_peripheral_m0_translator:uav_readdata
	wire          mm_bridge_peripheral_m0_translator_avalon_universal_master_0_debugaccess;   // mm_bridge_peripheral_m0_translator:uav_debugaccess -> mm_bridge_peripheral_m0_agent:av_debugaccess
	wire   [18:0] mm_bridge_peripheral_m0_translator_avalon_universal_master_0_address;       // mm_bridge_peripheral_m0_translator:uav_address -> mm_bridge_peripheral_m0_agent:av_address
	wire          mm_bridge_peripheral_m0_translator_avalon_universal_master_0_read;          // mm_bridge_peripheral_m0_translator:uav_read -> mm_bridge_peripheral_m0_agent:av_read
	wire    [3:0] mm_bridge_peripheral_m0_translator_avalon_universal_master_0_byteenable;    // mm_bridge_peripheral_m0_translator:uav_byteenable -> mm_bridge_peripheral_m0_agent:av_byteenable
	wire          mm_bridge_peripheral_m0_translator_avalon_universal_master_0_readdatavalid; // mm_bridge_peripheral_m0_agent:av_readdatavalid -> mm_bridge_peripheral_m0_translator:uav_readdatavalid
	wire          mm_bridge_peripheral_m0_translator_avalon_universal_master_0_lock;          // mm_bridge_peripheral_m0_translator:uav_lock -> mm_bridge_peripheral_m0_agent:av_lock
	wire          mm_bridge_peripheral_m0_translator_avalon_universal_master_0_write;         // mm_bridge_peripheral_m0_translator:uav_write -> mm_bridge_peripheral_m0_agent:av_write
	wire   [31:0] mm_bridge_peripheral_m0_translator_avalon_universal_master_0_writedata;     // mm_bridge_peripheral_m0_translator:uav_writedata -> mm_bridge_peripheral_m0_agent:av_writedata
	wire    [2:0] mm_bridge_peripheral_m0_translator_avalon_universal_master_0_burstcount;    // mm_bridge_peripheral_m0_translator:uav_burstcount -> mm_bridge_peripheral_m0_agent:av_burstcount
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata;                              // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_waitrequest;                           // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
	wire          jtag_uart_avalon_jtag_slave_agent_m0_debugaccess;                           // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
	wire   [18:0] jtag_uart_avalon_jtag_slave_agent_m0_address;                               // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
	wire    [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable;                            // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
	wire          jtag_uart_avalon_jtag_slave_agent_m0_read;                                  // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
	wire          jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid;                         // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
	wire          jtag_uart_avalon_jtag_slave_agent_m0_lock;                                  // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata;                             // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_write;                                 // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
	wire    [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount;                            // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_valid;                          // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
	wire  [118:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data;                           // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_ready;                          // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket;                  // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket;                    // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid;                       // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
	wire  [118:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data;                        // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready;                       // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;               // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;                 // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid;                     // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data;                      // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready;                     // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
	wire          cmd_mux_src_valid;                                                          // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
	wire  [117:0] cmd_mux_src_data;                                                           // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
	wire          cmd_mux_src_ready;                                                          // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
	wire    [3:0] cmd_mux_src_channel;                                                        // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                                  // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                    // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
	wire   [31:0] sysid_qsys_control_slave_agent_m0_readdata;                                 // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
	wire          sysid_qsys_control_slave_agent_m0_waitrequest;                              // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
	wire          sysid_qsys_control_slave_agent_m0_debugaccess;                              // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
	wire   [18:0] sysid_qsys_control_slave_agent_m0_address;                                  // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
	wire    [3:0] sysid_qsys_control_slave_agent_m0_byteenable;                               // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
	wire          sysid_qsys_control_slave_agent_m0_read;                                     // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
	wire          sysid_qsys_control_slave_agent_m0_readdatavalid;                            // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
	wire          sysid_qsys_control_slave_agent_m0_lock;                                     // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
	wire   [31:0] sysid_qsys_control_slave_agent_m0_writedata;                                // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
	wire          sysid_qsys_control_slave_agent_m0_write;                                    // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
	wire    [2:0] sysid_qsys_control_slave_agent_m0_burstcount;                               // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
	wire          sysid_qsys_control_slave_agent_rf_source_valid;                             // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
	wire  [118:0] sysid_qsys_control_slave_agent_rf_source_data;                              // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
	wire          sysid_qsys_control_slave_agent_rf_source_ready;                             // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
	wire          sysid_qsys_control_slave_agent_rf_source_startofpacket;                     // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
	wire          sysid_qsys_control_slave_agent_rf_source_endofpacket;                       // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_valid;                          // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
	wire  [118:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data;                           // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_ready;                          // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket;                  // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket;                    // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
	wire          sysid_qsys_control_slave_agent_rdata_fifo_src_valid;                        // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data;                         // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
	wire          sysid_qsys_control_slave_agent_rdata_fifo_src_ready;                        // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
	wire          cmd_mux_001_src_valid;                                                      // cmd_mux_001:src_valid -> sysid_qsys_control_slave_agent:cp_valid
	wire  [117:0] cmd_mux_001_src_data;                                                       // cmd_mux_001:src_data -> sysid_qsys_control_slave_agent:cp_data
	wire          cmd_mux_001_src_ready;                                                      // sysid_qsys_control_slave_agent:cp_ready -> cmd_mux_001:src_ready
	wire    [3:0] cmd_mux_001_src_channel;                                                    // cmd_mux_001:src_channel -> sysid_qsys_control_slave_agent:cp_channel
	wire          cmd_mux_001_src_startofpacket;                                              // cmd_mux_001:src_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                // cmd_mux_001:src_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
	wire   [31:0] pio_sw_s1_agent_m0_readdata;                                                // pio_sw_s1_translator:uav_readdata -> pio_sw_s1_agent:m0_readdata
	wire          pio_sw_s1_agent_m0_waitrequest;                                             // pio_sw_s1_translator:uav_waitrequest -> pio_sw_s1_agent:m0_waitrequest
	wire          pio_sw_s1_agent_m0_debugaccess;                                             // pio_sw_s1_agent:m0_debugaccess -> pio_sw_s1_translator:uav_debugaccess
	wire   [18:0] pio_sw_s1_agent_m0_address;                                                 // pio_sw_s1_agent:m0_address -> pio_sw_s1_translator:uav_address
	wire    [3:0] pio_sw_s1_agent_m0_byteenable;                                              // pio_sw_s1_agent:m0_byteenable -> pio_sw_s1_translator:uav_byteenable
	wire          pio_sw_s1_agent_m0_read;                                                    // pio_sw_s1_agent:m0_read -> pio_sw_s1_translator:uav_read
	wire          pio_sw_s1_agent_m0_readdatavalid;                                           // pio_sw_s1_translator:uav_readdatavalid -> pio_sw_s1_agent:m0_readdatavalid
	wire          pio_sw_s1_agent_m0_lock;                                                    // pio_sw_s1_agent:m0_lock -> pio_sw_s1_translator:uav_lock
	wire   [31:0] pio_sw_s1_agent_m0_writedata;                                               // pio_sw_s1_agent:m0_writedata -> pio_sw_s1_translator:uav_writedata
	wire          pio_sw_s1_agent_m0_write;                                                   // pio_sw_s1_agent:m0_write -> pio_sw_s1_translator:uav_write
	wire    [2:0] pio_sw_s1_agent_m0_burstcount;                                              // pio_sw_s1_agent:m0_burstcount -> pio_sw_s1_translator:uav_burstcount
	wire          pio_sw_s1_agent_rf_source_valid;                                            // pio_sw_s1_agent:rf_source_valid -> pio_sw_s1_agent_rsp_fifo:in_valid
	wire  [118:0] pio_sw_s1_agent_rf_source_data;                                             // pio_sw_s1_agent:rf_source_data -> pio_sw_s1_agent_rsp_fifo:in_data
	wire          pio_sw_s1_agent_rf_source_ready;                                            // pio_sw_s1_agent_rsp_fifo:in_ready -> pio_sw_s1_agent:rf_source_ready
	wire          pio_sw_s1_agent_rf_source_startofpacket;                                    // pio_sw_s1_agent:rf_source_startofpacket -> pio_sw_s1_agent_rsp_fifo:in_startofpacket
	wire          pio_sw_s1_agent_rf_source_endofpacket;                                      // pio_sw_s1_agent:rf_source_endofpacket -> pio_sw_s1_agent_rsp_fifo:in_endofpacket
	wire          pio_sw_s1_agent_rsp_fifo_out_valid;                                         // pio_sw_s1_agent_rsp_fifo:out_valid -> pio_sw_s1_agent:rf_sink_valid
	wire  [118:0] pio_sw_s1_agent_rsp_fifo_out_data;                                          // pio_sw_s1_agent_rsp_fifo:out_data -> pio_sw_s1_agent:rf_sink_data
	wire          pio_sw_s1_agent_rsp_fifo_out_ready;                                         // pio_sw_s1_agent:rf_sink_ready -> pio_sw_s1_agent_rsp_fifo:out_ready
	wire          pio_sw_s1_agent_rsp_fifo_out_startofpacket;                                 // pio_sw_s1_agent_rsp_fifo:out_startofpacket -> pio_sw_s1_agent:rf_sink_startofpacket
	wire          pio_sw_s1_agent_rsp_fifo_out_endofpacket;                                   // pio_sw_s1_agent_rsp_fifo:out_endofpacket -> pio_sw_s1_agent:rf_sink_endofpacket
	wire          pio_sw_s1_agent_rdata_fifo_src_valid;                                       // pio_sw_s1_agent:rdata_fifo_src_valid -> pio_sw_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] pio_sw_s1_agent_rdata_fifo_src_data;                                        // pio_sw_s1_agent:rdata_fifo_src_data -> pio_sw_s1_agent:rdata_fifo_sink_data
	wire          pio_sw_s1_agent_rdata_fifo_src_ready;                                       // pio_sw_s1_agent:rdata_fifo_sink_ready -> pio_sw_s1_agent:rdata_fifo_src_ready
	wire          cmd_mux_002_src_valid;                                                      // cmd_mux_002:src_valid -> pio_sw_s1_agent:cp_valid
	wire  [117:0] cmd_mux_002_src_data;                                                       // cmd_mux_002:src_data -> pio_sw_s1_agent:cp_data
	wire          cmd_mux_002_src_ready;                                                      // pio_sw_s1_agent:cp_ready -> cmd_mux_002:src_ready
	wire    [3:0] cmd_mux_002_src_channel;                                                    // cmd_mux_002:src_channel -> pio_sw_s1_agent:cp_channel
	wire          cmd_mux_002_src_startofpacket;                                              // cmd_mux_002:src_startofpacket -> pio_sw_s1_agent:cp_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                // cmd_mux_002:src_endofpacket -> pio_sw_s1_agent:cp_endofpacket
	wire   [31:0] spi_master_spi_control_port_agent_m0_readdata;                              // spi_master_spi_control_port_translator:uav_readdata -> spi_master_spi_control_port_agent:m0_readdata
	wire          spi_master_spi_control_port_agent_m0_waitrequest;                           // spi_master_spi_control_port_translator:uav_waitrequest -> spi_master_spi_control_port_agent:m0_waitrequest
	wire          spi_master_spi_control_port_agent_m0_debugaccess;                           // spi_master_spi_control_port_agent:m0_debugaccess -> spi_master_spi_control_port_translator:uav_debugaccess
	wire   [18:0] spi_master_spi_control_port_agent_m0_address;                               // spi_master_spi_control_port_agent:m0_address -> spi_master_spi_control_port_translator:uav_address
	wire    [3:0] spi_master_spi_control_port_agent_m0_byteenable;                            // spi_master_spi_control_port_agent:m0_byteenable -> spi_master_spi_control_port_translator:uav_byteenable
	wire          spi_master_spi_control_port_agent_m0_read;                                  // spi_master_spi_control_port_agent:m0_read -> spi_master_spi_control_port_translator:uav_read
	wire          spi_master_spi_control_port_agent_m0_readdatavalid;                         // spi_master_spi_control_port_translator:uav_readdatavalid -> spi_master_spi_control_port_agent:m0_readdatavalid
	wire          spi_master_spi_control_port_agent_m0_lock;                                  // spi_master_spi_control_port_agent:m0_lock -> spi_master_spi_control_port_translator:uav_lock
	wire   [31:0] spi_master_spi_control_port_agent_m0_writedata;                             // spi_master_spi_control_port_agent:m0_writedata -> spi_master_spi_control_port_translator:uav_writedata
	wire          spi_master_spi_control_port_agent_m0_write;                                 // spi_master_spi_control_port_agent:m0_write -> spi_master_spi_control_port_translator:uav_write
	wire    [2:0] spi_master_spi_control_port_agent_m0_burstcount;                            // spi_master_spi_control_port_agent:m0_burstcount -> spi_master_spi_control_port_translator:uav_burstcount
	wire          spi_master_spi_control_port_agent_rf_source_valid;                          // spi_master_spi_control_port_agent:rf_source_valid -> spi_master_spi_control_port_agent_rsp_fifo:in_valid
	wire  [118:0] spi_master_spi_control_port_agent_rf_source_data;                           // spi_master_spi_control_port_agent:rf_source_data -> spi_master_spi_control_port_agent_rsp_fifo:in_data
	wire          spi_master_spi_control_port_agent_rf_source_ready;                          // spi_master_spi_control_port_agent_rsp_fifo:in_ready -> spi_master_spi_control_port_agent:rf_source_ready
	wire          spi_master_spi_control_port_agent_rf_source_startofpacket;                  // spi_master_spi_control_port_agent:rf_source_startofpacket -> spi_master_spi_control_port_agent_rsp_fifo:in_startofpacket
	wire          spi_master_spi_control_port_agent_rf_source_endofpacket;                    // spi_master_spi_control_port_agent:rf_source_endofpacket -> spi_master_spi_control_port_agent_rsp_fifo:in_endofpacket
	wire          spi_master_spi_control_port_agent_rsp_fifo_out_valid;                       // spi_master_spi_control_port_agent_rsp_fifo:out_valid -> spi_master_spi_control_port_agent:rf_sink_valid
	wire  [118:0] spi_master_spi_control_port_agent_rsp_fifo_out_data;                        // spi_master_spi_control_port_agent_rsp_fifo:out_data -> spi_master_spi_control_port_agent:rf_sink_data
	wire          spi_master_spi_control_port_agent_rsp_fifo_out_ready;                       // spi_master_spi_control_port_agent:rf_sink_ready -> spi_master_spi_control_port_agent_rsp_fifo:out_ready
	wire          spi_master_spi_control_port_agent_rsp_fifo_out_startofpacket;               // spi_master_spi_control_port_agent_rsp_fifo:out_startofpacket -> spi_master_spi_control_port_agent:rf_sink_startofpacket
	wire          spi_master_spi_control_port_agent_rsp_fifo_out_endofpacket;                 // spi_master_spi_control_port_agent_rsp_fifo:out_endofpacket -> spi_master_spi_control_port_agent:rf_sink_endofpacket
	wire          spi_master_spi_control_port_agent_rdata_fifo_src_valid;                     // spi_master_spi_control_port_agent:rdata_fifo_src_valid -> spi_master_spi_control_port_agent:rdata_fifo_sink_valid
	wire   [33:0] spi_master_spi_control_port_agent_rdata_fifo_src_data;                      // spi_master_spi_control_port_agent:rdata_fifo_src_data -> spi_master_spi_control_port_agent:rdata_fifo_sink_data
	wire          spi_master_spi_control_port_agent_rdata_fifo_src_ready;                     // spi_master_spi_control_port_agent:rdata_fifo_sink_ready -> spi_master_spi_control_port_agent:rdata_fifo_src_ready
	wire          cmd_mux_003_src_valid;                                                      // cmd_mux_003:src_valid -> spi_master_spi_control_port_agent:cp_valid
	wire  [117:0] cmd_mux_003_src_data;                                                       // cmd_mux_003:src_data -> spi_master_spi_control_port_agent:cp_data
	wire          cmd_mux_003_src_ready;                                                      // spi_master_spi_control_port_agent:cp_ready -> cmd_mux_003:src_ready
	wire    [3:0] cmd_mux_003_src_channel;                                                    // cmd_mux_003:src_channel -> spi_master_spi_control_port_agent:cp_channel
	wire          cmd_mux_003_src_startofpacket;                                              // cmd_mux_003:src_startofpacket -> spi_master_spi_control_port_agent:cp_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                // cmd_mux_003:src_endofpacket -> spi_master_spi_control_port_agent:cp_endofpacket
	wire          mm_bridge_peripheral_m0_agent_cp_valid;                                     // mm_bridge_peripheral_m0_agent:cp_valid -> router:sink_valid
	wire  [117:0] mm_bridge_peripheral_m0_agent_cp_data;                                      // mm_bridge_peripheral_m0_agent:cp_data -> router:sink_data
	wire          mm_bridge_peripheral_m0_agent_cp_ready;                                     // router:sink_ready -> mm_bridge_peripheral_m0_agent:cp_ready
	wire          mm_bridge_peripheral_m0_agent_cp_startofpacket;                             // mm_bridge_peripheral_m0_agent:cp_startofpacket -> router:sink_startofpacket
	wire          mm_bridge_peripheral_m0_agent_cp_endofpacket;                               // mm_bridge_peripheral_m0_agent:cp_endofpacket -> router:sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_valid;                                 // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_001:sink_valid
	wire  [117:0] jtag_uart_avalon_jtag_slave_agent_rp_data;                                  // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_001:sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rp_ready;                                 // router_001:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rp_startofpacket;                         // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_endofpacket;                           // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                       // router_001:src_valid -> rsp_demux:sink_valid
	wire  [117:0] router_001_src_data;                                                        // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                       // rsp_demux:sink_ready -> router_001:src_ready
	wire    [3:0] router_001_src_channel;                                                     // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                               // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                 // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          sysid_qsys_control_slave_agent_rp_valid;                                    // sysid_qsys_control_slave_agent:rp_valid -> router_002:sink_valid
	wire  [117:0] sysid_qsys_control_slave_agent_rp_data;                                     // sysid_qsys_control_slave_agent:rp_data -> router_002:sink_data
	wire          sysid_qsys_control_slave_agent_rp_ready;                                    // router_002:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
	wire          sysid_qsys_control_slave_agent_rp_startofpacket;                            // sysid_qsys_control_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
	wire          sysid_qsys_control_slave_agent_rp_endofpacket;                              // sysid_qsys_control_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                       // router_002:src_valid -> rsp_demux_001:sink_valid
	wire  [117:0] router_002_src_data;                                                        // router_002:src_data -> rsp_demux_001:sink_data
	wire          router_002_src_ready;                                                       // rsp_demux_001:sink_ready -> router_002:src_ready
	wire    [3:0] router_002_src_channel;                                                     // router_002:src_channel -> rsp_demux_001:sink_channel
	wire          router_002_src_startofpacket;                                               // router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_002_src_endofpacket;                                                 // router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          pio_sw_s1_agent_rp_valid;                                                   // pio_sw_s1_agent:rp_valid -> router_003:sink_valid
	wire  [117:0] pio_sw_s1_agent_rp_data;                                                    // pio_sw_s1_agent:rp_data -> router_003:sink_data
	wire          pio_sw_s1_agent_rp_ready;                                                   // router_003:sink_ready -> pio_sw_s1_agent:rp_ready
	wire          pio_sw_s1_agent_rp_startofpacket;                                           // pio_sw_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
	wire          pio_sw_s1_agent_rp_endofpacket;                                             // pio_sw_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
	wire          router_003_src_valid;                                                       // router_003:src_valid -> rsp_demux_002:sink_valid
	wire  [117:0] router_003_src_data;                                                        // router_003:src_data -> rsp_demux_002:sink_data
	wire          router_003_src_ready;                                                       // rsp_demux_002:sink_ready -> router_003:src_ready
	wire    [3:0] router_003_src_channel;                                                     // router_003:src_channel -> rsp_demux_002:sink_channel
	wire          router_003_src_startofpacket;                                               // router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_003_src_endofpacket;                                                 // router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          spi_master_spi_control_port_agent_rp_valid;                                 // spi_master_spi_control_port_agent:rp_valid -> router_004:sink_valid
	wire  [117:0] spi_master_spi_control_port_agent_rp_data;                                  // spi_master_spi_control_port_agent:rp_data -> router_004:sink_data
	wire          spi_master_spi_control_port_agent_rp_ready;                                 // router_004:sink_ready -> spi_master_spi_control_port_agent:rp_ready
	wire          spi_master_spi_control_port_agent_rp_startofpacket;                         // spi_master_spi_control_port_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          spi_master_spi_control_port_agent_rp_endofpacket;                           // spi_master_spi_control_port_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                       // router_004:src_valid -> rsp_demux_003:sink_valid
	wire  [117:0] router_004_src_data;                                                        // router_004:src_data -> rsp_demux_003:sink_data
	wire          router_004_src_ready;                                                       // rsp_demux_003:sink_ready -> router_004:src_ready
	wire    [3:0] router_004_src_channel;                                                     // router_004:src_channel -> rsp_demux_003:sink_channel
	wire          router_004_src_startofpacket;                                               // router_004:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_004_src_endofpacket;                                                 // router_004:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_src_valid;                                                           // router:src_valid -> mm_bridge_peripheral_m0_limiter:cmd_sink_valid
	wire  [117:0] router_src_data;                                                            // router:src_data -> mm_bridge_peripheral_m0_limiter:cmd_sink_data
	wire          router_src_ready;                                                           // mm_bridge_peripheral_m0_limiter:cmd_sink_ready -> router:src_ready
	wire    [3:0] router_src_channel;                                                         // router:src_channel -> mm_bridge_peripheral_m0_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                   // router:src_startofpacket -> mm_bridge_peripheral_m0_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                     // router:src_endofpacket -> mm_bridge_peripheral_m0_limiter:cmd_sink_endofpacket
	wire  [117:0] mm_bridge_peripheral_m0_limiter_cmd_src_data;                               // mm_bridge_peripheral_m0_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          mm_bridge_peripheral_m0_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> mm_bridge_peripheral_m0_limiter:cmd_src_ready
	wire    [3:0] mm_bridge_peripheral_m0_limiter_cmd_src_channel;                            // mm_bridge_peripheral_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          mm_bridge_peripheral_m0_limiter_cmd_src_startofpacket;                      // mm_bridge_peripheral_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          mm_bridge_peripheral_m0_limiter_cmd_src_endofpacket;                        // mm_bridge_peripheral_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                          // rsp_mux:src_valid -> mm_bridge_peripheral_m0_limiter:rsp_sink_valid
	wire  [117:0] rsp_mux_src_data;                                                           // rsp_mux:src_data -> mm_bridge_peripheral_m0_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                          // mm_bridge_peripheral_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [3:0] rsp_mux_src_channel;                                                        // rsp_mux:src_channel -> mm_bridge_peripheral_m0_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                  // rsp_mux:src_startofpacket -> mm_bridge_peripheral_m0_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                    // rsp_mux:src_endofpacket -> mm_bridge_peripheral_m0_limiter:rsp_sink_endofpacket
	wire          mm_bridge_peripheral_m0_limiter_rsp_src_valid;                              // mm_bridge_peripheral_m0_limiter:rsp_src_valid -> mm_bridge_peripheral_m0_agent:rp_valid
	wire  [117:0] mm_bridge_peripheral_m0_limiter_rsp_src_data;                               // mm_bridge_peripheral_m0_limiter:rsp_src_data -> mm_bridge_peripheral_m0_agent:rp_data
	wire          mm_bridge_peripheral_m0_limiter_rsp_src_ready;                              // mm_bridge_peripheral_m0_agent:rp_ready -> mm_bridge_peripheral_m0_limiter:rsp_src_ready
	wire    [3:0] mm_bridge_peripheral_m0_limiter_rsp_src_channel;                            // mm_bridge_peripheral_m0_limiter:rsp_src_channel -> mm_bridge_peripheral_m0_agent:rp_channel
	wire          mm_bridge_peripheral_m0_limiter_rsp_src_startofpacket;                      // mm_bridge_peripheral_m0_limiter:rsp_src_startofpacket -> mm_bridge_peripheral_m0_agent:rp_startofpacket
	wire          mm_bridge_peripheral_m0_limiter_rsp_src_endofpacket;                        // mm_bridge_peripheral_m0_limiter:rsp_src_endofpacket -> mm_bridge_peripheral_m0_agent:rp_endofpacket
	wire          cmd_demux_src0_valid;                                                       // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [117:0] cmd_demux_src0_data;                                                        // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                       // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [3:0] cmd_demux_src0_channel;                                                     // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                               // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                 // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                       // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [117:0] cmd_demux_src1_data;                                                        // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                       // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [3:0] cmd_demux_src1_channel;                                                     // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                               // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                 // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                                       // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [117:0] cmd_demux_src2_data;                                                        // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                                       // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire    [3:0] cmd_demux_src2_channel;                                                     // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                               // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                                 // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                                       // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [117:0] cmd_demux_src3_data;                                                        // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                                       // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire    [3:0] cmd_demux_src3_channel;                                                     // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                               // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                                 // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                       // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [117:0] rsp_demux_src0_data;                                                        // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                       // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [3:0] rsp_demux_src0_channel;                                                     // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                               // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                 // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                   // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [117:0] rsp_demux_001_src0_data;                                                    // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                   // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [3:0] rsp_demux_001_src0_channel;                                                 // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                           // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                             // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                                   // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [117:0] rsp_demux_002_src0_data;                                                    // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                                   // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire    [3:0] rsp_demux_002_src0_channel;                                                 // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                           // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                             // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_003_src0_valid;                                                   // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [117:0] rsp_demux_003_src0_data;                                                    // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                                   // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire    [3:0] rsp_demux_003_src0_channel;                                                 // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                           // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                             // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire    [3:0] mm_bridge_peripheral_m0_limiter_cmd_valid_data;                             // mm_bridge_peripheral_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid

	nios_system_altera_merlin_master_translator_193_lgcew2q #(
		.AV_ADDRESS_W                (19),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (19),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) mm_bridge_peripheral_m0_translator (
		.clk                    (iopll_outclk0_clk),                                                          //   input,   width = 1,                       clk.clk
		.reset                  (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset),                     //   input,   width = 1,                     reset.reset
		.uav_address            (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_address),       //  output,  width = 19, avalon_universal_master_0.address
		.uav_burstcount         (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (mm_bridge_peripheral_m0_address),                                            //   input,  width = 19,      avalon_anti_master_0.address
		.av_waitrequest         (mm_bridge_peripheral_m0_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_burstcount          (mm_bridge_peripheral_m0_burstcount),                                         //   input,   width = 1,                          .burstcount
		.av_byteenable          (mm_bridge_peripheral_m0_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (mm_bridge_peripheral_m0_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (mm_bridge_peripheral_m0_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (mm_bridge_peripheral_m0_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (mm_bridge_peripheral_m0_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (mm_bridge_peripheral_m0_writedata),                                          //   input,  width = 32,                          .writedata
		.av_debugaccess         (mm_bridge_peripheral_m0_debugaccess),                                        //   input,   width = 1,                          .debugaccess
		.av_beginbursttransfer  (1'b0),                                                                       // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                       // (terminated),                                        
		.av_chipselect          (1'b0),                                                                       // (terminated),                                        
		.av_lock                (1'b0),                                                                       // (terminated),                                        
		.uav_outputenable       (1'b0),                                                                       // (terminated),                                        
		.uav_clken              (),                                                                           // (terminated),                                        
		.av_clken               (1'b1),                                                                       // (terminated),                                        
		.uav_response           (2'b00),                                                                      // (terminated),                                        
		.av_response            (),                                                                           // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                       // (terminated),                                        
		.av_writeresponsevalid  ()                                                                            // (terminated),                                        
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (19),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) jtag_uart_avalon_jtag_slave_translator (
		.clk                    (iopll_outclk0_clk),                                      //   input,   width = 1,                      clk.clk
		.reset                  (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (jtag_uart_avalon_jtag_slave_agent_m0_address),           //   input,  width = 19, avalon_universal_slave_0.address
		.uav_burstcount         (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),        //   input,   width = 3,                         .burstcount
		.uav_read               (jtag_uart_avalon_jtag_slave_agent_m0_read),              //   input,   width = 1,                         .read
		.uav_write              (jtag_uart_avalon_jtag_slave_agent_m0_write),             //   input,   width = 1,                         .write
		.uav_waitrequest        (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),       //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),     //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),        //   input,   width = 4,                         .byteenable
		.uav_readdata           (jtag_uart_avalon_jtag_slave_agent_m0_readdata),          //  output,  width = 32,                         .readdata
		.uav_writedata          (jtag_uart_avalon_jtag_slave_agent_m0_writedata),         //   input,  width = 32,                         .writedata
		.uav_lock               (jtag_uart_avalon_jtag_slave_agent_m0_lock),              //   input,   width = 1,                         .lock
		.uav_debugaccess        (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),       //   input,   width = 1,                         .debugaccess
		.av_address             (jtag_uart_avalon_jtag_slave_address),                    //  output,   width = 1,      avalon_anti_slave_0.address
		.av_write               (jtag_uart_avalon_jtag_slave_write),                      //  output,   width = 1,                         .write
		.av_read                (jtag_uart_avalon_jtag_slave_read),                       //  output,   width = 1,                         .read
		.av_readdata            (jtag_uart_avalon_jtag_slave_readdata),                   //   input,  width = 32,                         .readdata
		.av_writedata           (jtag_uart_avalon_jtag_slave_writedata),                  //  output,  width = 32,                         .writedata
		.av_waitrequest         (jtag_uart_avalon_jtag_slave_waitrequest),                //   input,   width = 1,                         .waitrequest
		.av_chipselect          (jtag_uart_avalon_jtag_slave_chipselect),                 //  output,   width = 1,                         .chipselect
		.av_begintransfer       (),                                                       // (terminated),                                       
		.av_beginbursttransfer  (),                                                       // (terminated),                                       
		.av_burstcount          (),                                                       // (terminated),                                       
		.av_byteenable          (),                                                       // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                   // (terminated),                                       
		.av_writebyteenable     (),                                                       // (terminated),                                       
		.av_lock                (),                                                       // (terminated),                                       
		.av_clken               (),                                                       // (terminated),                                       
		.uav_clken              (1'b0),                                                   // (terminated),                                       
		.av_debugaccess         (),                                                       // (terminated),                                       
		.av_outputenable        (),                                                       // (terminated),                                       
		.uav_response           (),                                                       // (terminated),                                       
		.av_response            (2'b00),                                                  // (terminated),                                       
		.uav_writeresponsevalid (),                                                       // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                    // (terminated),                                       
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (19),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) sysid_qsys_control_slave_translator (
		.clk                    (iopll_outclk0_clk),                                      //   input,   width = 1,                      clk.clk
		.reset                  (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (sysid_qsys_control_slave_agent_m0_address),              //   input,  width = 19, avalon_universal_slave_0.address
		.uav_burstcount         (sysid_qsys_control_slave_agent_m0_burstcount),           //   input,   width = 3,                         .burstcount
		.uav_read               (sysid_qsys_control_slave_agent_m0_read),                 //   input,   width = 1,                         .read
		.uav_write              (sysid_qsys_control_slave_agent_m0_write),                //   input,   width = 1,                         .write
		.uav_waitrequest        (sysid_qsys_control_slave_agent_m0_waitrequest),          //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (sysid_qsys_control_slave_agent_m0_readdatavalid),        //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (sysid_qsys_control_slave_agent_m0_byteenable),           //   input,   width = 4,                         .byteenable
		.uav_readdata           (sysid_qsys_control_slave_agent_m0_readdata),             //  output,  width = 32,                         .readdata
		.uav_writedata          (sysid_qsys_control_slave_agent_m0_writedata),            //   input,  width = 32,                         .writedata
		.uav_lock               (sysid_qsys_control_slave_agent_m0_lock),                 //   input,   width = 1,                         .lock
		.uav_debugaccess        (sysid_qsys_control_slave_agent_m0_debugaccess),          //   input,   width = 1,                         .debugaccess
		.av_address             (sysid_qsys_control_slave_address),                       //  output,   width = 1,      avalon_anti_slave_0.address
		.av_readdata            (sysid_qsys_control_slave_readdata),                      //   input,  width = 32,                         .readdata
		.av_write               (),                                                       // (terminated),                                       
		.av_read                (),                                                       // (terminated),                                       
		.av_writedata           (),                                                       // (terminated),                                       
		.av_begintransfer       (),                                                       // (terminated),                                       
		.av_beginbursttransfer  (),                                                       // (terminated),                                       
		.av_burstcount          (),                                                       // (terminated),                                       
		.av_byteenable          (),                                                       // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                   // (terminated),                                       
		.av_waitrequest         (1'b0),                                                   // (terminated),                                       
		.av_writebyteenable     (),                                                       // (terminated),                                       
		.av_lock                (),                                                       // (terminated),                                       
		.av_chipselect          (),                                                       // (terminated),                                       
		.av_clken               (),                                                       // (terminated),                                       
		.uav_clken              (1'b0),                                                   // (terminated),                                       
		.av_debugaccess         (),                                                       // (terminated),                                       
		.av_outputenable        (),                                                       // (terminated),                                       
		.uav_response           (),                                                       // (terminated),                                       
		.av_response            (2'b00),                                                  // (terminated),                                       
		.uav_writeresponsevalid (),                                                       // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                    // (terminated),                                       
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (19),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) pio_sw_s1_translator (
		.clk                    (iopll_outclk0_clk),                                      //   input,   width = 1,                      clk.clk
		.reset                  (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (pio_sw_s1_agent_m0_address),                             //   input,  width = 19, avalon_universal_slave_0.address
		.uav_burstcount         (pio_sw_s1_agent_m0_burstcount),                          //   input,   width = 3,                         .burstcount
		.uav_read               (pio_sw_s1_agent_m0_read),                                //   input,   width = 1,                         .read
		.uav_write              (pio_sw_s1_agent_m0_write),                               //   input,   width = 1,                         .write
		.uav_waitrequest        (pio_sw_s1_agent_m0_waitrequest),                         //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (pio_sw_s1_agent_m0_readdatavalid),                       //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (pio_sw_s1_agent_m0_byteenable),                          //   input,   width = 4,                         .byteenable
		.uav_readdata           (pio_sw_s1_agent_m0_readdata),                            //  output,  width = 32,                         .readdata
		.uav_writedata          (pio_sw_s1_agent_m0_writedata),                           //   input,  width = 32,                         .writedata
		.uav_lock               (pio_sw_s1_agent_m0_lock),                                //   input,   width = 1,                         .lock
		.uav_debugaccess        (pio_sw_s1_agent_m0_debugaccess),                         //   input,   width = 1,                         .debugaccess
		.av_address             (pio_sw_s1_address),                                      //  output,   width = 2,      avalon_anti_slave_0.address
		.av_write               (pio_sw_s1_write),                                        //  output,   width = 1,                         .write
		.av_readdata            (pio_sw_s1_readdata),                                     //   input,  width = 32,                         .readdata
		.av_writedata           (pio_sw_s1_writedata),                                    //  output,  width = 32,                         .writedata
		.av_chipselect          (pio_sw_s1_chipselect),                                   //  output,   width = 1,                         .chipselect
		.av_read                (),                                                       // (terminated),                                       
		.av_begintransfer       (),                                                       // (terminated),                                       
		.av_beginbursttransfer  (),                                                       // (terminated),                                       
		.av_burstcount          (),                                                       // (terminated),                                       
		.av_byteenable          (),                                                       // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                   // (terminated),                                       
		.av_waitrequest         (1'b0),                                                   // (terminated),                                       
		.av_writebyteenable     (),                                                       // (terminated),                                       
		.av_lock                (),                                                       // (terminated),                                       
		.av_clken               (),                                                       // (terminated),                                       
		.uav_clken              (1'b0),                                                   // (terminated),                                       
		.av_debugaccess         (),                                                       // (terminated),                                       
		.av_outputenable        (),                                                       // (terminated),                                       
		.uav_response           (),                                                       // (terminated),                                       
		.av_response            (2'b00),                                                  // (terminated),                                       
		.uav_writeresponsevalid (),                                                       // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                    // (terminated),                                       
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (19),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (1),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) spi_master_spi_control_port_translator (
		.clk                    (iopll_outclk0_clk),                                      //   input,   width = 1,                      clk.clk
		.reset                  (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (spi_master_spi_control_port_agent_m0_address),           //   input,  width = 19, avalon_universal_slave_0.address
		.uav_burstcount         (spi_master_spi_control_port_agent_m0_burstcount),        //   input,   width = 3,                         .burstcount
		.uav_read               (spi_master_spi_control_port_agent_m0_read),              //   input,   width = 1,                         .read
		.uav_write              (spi_master_spi_control_port_agent_m0_write),             //   input,   width = 1,                         .write
		.uav_waitrequest        (spi_master_spi_control_port_agent_m0_waitrequest),       //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (spi_master_spi_control_port_agent_m0_readdatavalid),     //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (spi_master_spi_control_port_agent_m0_byteenable),        //   input,   width = 4,                         .byteenable
		.uav_readdata           (spi_master_spi_control_port_agent_m0_readdata),          //  output,  width = 32,                         .readdata
		.uav_writedata          (spi_master_spi_control_port_agent_m0_writedata),         //   input,  width = 32,                         .writedata
		.uav_lock               (spi_master_spi_control_port_agent_m0_lock),              //   input,   width = 1,                         .lock
		.uav_debugaccess        (spi_master_spi_control_port_agent_m0_debugaccess),       //   input,   width = 1,                         .debugaccess
		.av_address             (spi_master_spi_control_port_address),                    //  output,   width = 3,      avalon_anti_slave_0.address
		.av_write               (spi_master_spi_control_port_write),                      //  output,   width = 1,                         .write
		.av_read                (spi_master_spi_control_port_read),                       //  output,   width = 1,                         .read
		.av_readdata            (spi_master_spi_control_port_readdata),                   //   input,  width = 16,                         .readdata
		.av_writedata           (spi_master_spi_control_port_writedata),                  //  output,  width = 16,                         .writedata
		.av_chipselect          (spi_master_spi_control_port_chipselect),                 //  output,   width = 1,                         .chipselect
		.av_begintransfer       (),                                                       // (terminated),                                       
		.av_beginbursttransfer  (),                                                       // (terminated),                                       
		.av_burstcount          (),                                                       // (terminated),                                       
		.av_byteenable          (),                                                       // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                   // (terminated),                                       
		.av_waitrequest         (1'b0),                                                   // (terminated),                                       
		.av_writebyteenable     (),                                                       // (terminated),                                       
		.av_lock                (),                                                       // (terminated),                                       
		.av_clken               (),                                                       // (terminated),                                       
		.uav_clken              (1'b0),                                                   // (terminated),                                       
		.av_debugaccess         (),                                                       // (terminated),                                       
		.av_outputenable        (),                                                       // (terminated),                                       
		.uav_response           (),                                                       // (terminated),                                       
		.av_response            (2'b00),                                                  // (terminated),                                       
		.uav_writeresponsevalid (),                                                       // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                    // (terminated),                                       
	);

	nios_system_altera_merlin_master_agent_1931_jtx3eyy #(
		.PKT_WUNIQUE               (99),
		.PKT_DOMAIN_H              (98),
		.PKT_DOMAIN_L              (97),
		.PKT_SNOOP_H               (96),
		.PKT_SNOOP_L               (93),
		.PKT_BARRIER_H             (92),
		.PKT_BARRIER_L             (91),
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_QOS_H                 (73),
		.PKT_QOS_L                 (73),
		.PKT_DATA_SIDEBAND_H       (71),
		.PKT_DATA_SIDEBAND_L       (71),
		.PKT_ADDR_SIDEBAND_H       (70),
		.PKT_ADDR_SIDEBAND_L       (70),
		.PKT_BURST_TYPE_H          (69),
		.PKT_BURST_TYPE_L          (68),
		.PKT_CACHE_H               (85),
		.PKT_CACHE_L               (82),
		.PKT_THREAD_ID_H           (78),
		.PKT_THREAD_ID_L           (78),
		.PKT_BURST_SIZE_H          (67),
		.PKT_BURST_SIZE_L          (65),
		.PKT_TRANS_EXCLUSIVE       (60),
		.PKT_TRANS_LOCK            (59),
		.PKT_BEGIN_BURST           (72),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (64),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (54),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (55),
		.PKT_TRANS_POSTED          (56),
		.PKT_TRANS_WRITE           (57),
		.PKT_TRANS_READ            (58),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (74),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (76),
		.PKT_POISON_H              (100),
		.PKT_POISON_L              (100),
		.PKT_DATACHK_H             (101),
		.PKT_DATACHK_L             (101),
		.PKT_ADDRCHK_H             (104),
		.PKT_ADDRCHK_L             (103),
		.PKT_SAI_H                 (105),
		.PKT_SAI_L                 (105),
		.PKT_USER_DATA_H           (102),
		.PKT_USER_DATA_L           (102),
		.PKT_ATRACE                (115),
		.PKT_TRACE                 (116),
		.PKT_AWAKEUP               (117),
		.ST_DATA_W                 (118),
		.ST_CHANNEL_W              (4),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.OPTIMIZED_READS_WITH_BE   (0)
	) mm_bridge_peripheral_m0_agent (
		.clk                   (iopll_outclk0_clk),                                                          //   input,    width = 1,       clk.clk
		.reset                 (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset),                     //   input,    width = 1, clk_reset.reset
		.av_address            (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_address),       //   input,   width = 19,        av.address
		.av_write              (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (mm_bridge_peripheral_m0_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (mm_bridge_peripheral_m0_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (mm_bridge_peripheral_m0_agent_cp_data),                                      //  output,  width = 118,          .data
		.cp_startofpacket      (mm_bridge_peripheral_m0_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (mm_bridge_peripheral_m0_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (mm_bridge_peripheral_m0_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (mm_bridge_peripheral_m0_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (mm_bridge_peripheral_m0_limiter_rsp_src_data),                               //   input,  width = 118,          .data
		.rp_channel            (mm_bridge_peripheral_m0_limiter_rsp_src_channel),                            //   input,    width = 4,          .channel
		.rp_startofpacket      (mm_bridge_peripheral_m0_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (mm_bridge_peripheral_m0_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (mm_bridge_peripheral_m0_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                           // (terminated),                         
		.av_writeresponsevalid ()                                                                            // (terminated),                         
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (67),
		.PKT_BURST_SIZE_L          (65),
		.PKT_TRANS_LOCK            (59),
		.PKT_BEGIN_BURST           (72),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (64),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (54),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (55),
		.PKT_TRANS_POSTED          (56),
		.PKT_TRANS_WRITE           (57),
		.PKT_TRANS_READ            (58),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (74),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (76),
		.PKT_POISON_H              (100),
		.PKT_POISON_L              (100),
		.PKT_DATACHK_H             (101),
		.PKT_DATACHK_L             (101),
		.PKT_SAI_H                 (105),
		.PKT_SAI_L                 (105),
		.PKT_ADDRCHK_H             (104),
		.PKT_ADDRCHK_L             (103),
		.PKT_USER_DATA_H           (102),
		.PKT_USER_DATA_L           (102),
		.PKT_ATRACE                (115),
		.PKT_TRACE                 (116),
		.PKT_AWAKEUP               (117),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (118),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) jtag_uart_avalon_jtag_slave_agent (
		.clk                     (iopll_outclk0_clk),                                            //   input,    width = 1,             clk.clk
		.reset                   (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset),       //   input,    width = 1,       clk_reset.reset
		.m0_address              (jtag_uart_avalon_jtag_slave_agent_m0_address),                 //  output,   width = 19,              m0.address
		.m0_burstcount           (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (jtag_uart_avalon_jtag_slave_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (jtag_uart_avalon_jtag_slave_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (jtag_uart_avalon_jtag_slave_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (jtag_uart_avalon_jtag_slave_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (jtag_uart_avalon_jtag_slave_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (jtag_uart_avalon_jtag_slave_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (jtag_uart_avalon_jtag_slave_agent_rp_data),                    //  output,  width = 118,                .data
		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                            //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                            //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_src_data),                                             //   input,  width = 118,                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                    //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                      //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                          //   input,    width = 4,                .channel
		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //   input,  width = 119,                .data
		.rf_source_ready         (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //  output,  width = 119,                .data
		.rdata_fifo_sink_ready   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                        // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                         // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                          // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (119),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                            //   input,    width = 1,       clk.clk
		.reset             (jtag_uart_reset_reset_bridge_in_reset_reset),                  //   input,    width = 1, clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //   input,  width = 119,        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //  output,  width = 119,       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated),                         
		.csr_read          (1'b0),                                                         // (terminated),                         
		.csr_write         (1'b0),                                                         // (terminated),                         
		.csr_readdata      (),                                                             // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated),                         
		.almost_full_data  (),                                                             // (terminated),                         
		.almost_empty_data (),                                                             // (terminated),                         
		.in_empty          (1'b0),                                                         // (terminated),                         
		.out_empty         (),                                                             // (terminated),                         
		.in_error          (1'b0),                                                         // (terminated),                         
		.out_error         (),                                                             // (terminated),                         
		.in_channel        (1'b0),                                                         // (terminated),                         
		.out_channel       ()                                                              // (terminated),                         
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (67),
		.PKT_BURST_SIZE_L          (65),
		.PKT_TRANS_LOCK            (59),
		.PKT_BEGIN_BURST           (72),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (64),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (54),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (55),
		.PKT_TRANS_POSTED          (56),
		.PKT_TRANS_WRITE           (57),
		.PKT_TRANS_READ            (58),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (74),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (76),
		.PKT_POISON_H              (100),
		.PKT_POISON_L              (100),
		.PKT_DATACHK_H             (101),
		.PKT_DATACHK_L             (101),
		.PKT_SAI_H                 (105),
		.PKT_SAI_L                 (105),
		.PKT_ADDRCHK_H             (104),
		.PKT_ADDRCHK_L             (103),
		.PKT_USER_DATA_H           (102),
		.PKT_USER_DATA_L           (102),
		.PKT_ATRACE                (115),
		.PKT_TRACE                 (116),
		.PKT_AWAKEUP               (117),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (118),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) sysid_qsys_control_slave_agent (
		.clk                     (iopll_outclk0_clk),                                         //   input,    width = 1,             clk.clk
		.reset                   (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset),    //   input,    width = 1,       clk_reset.reset
		.m0_address              (sysid_qsys_control_slave_agent_m0_address),                 //  output,   width = 19,              m0.address
		.m0_burstcount           (sysid_qsys_control_slave_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (sysid_qsys_control_slave_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (sysid_qsys_control_slave_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (sysid_qsys_control_slave_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (sysid_qsys_control_slave_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (sysid_qsys_control_slave_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (sysid_qsys_control_slave_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (sysid_qsys_control_slave_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (sysid_qsys_control_slave_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (sysid_qsys_control_slave_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (sysid_qsys_control_slave_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (sysid_qsys_control_slave_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (sysid_qsys_control_slave_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (sysid_qsys_control_slave_agent_rp_data),                    //  output,  width = 118,                .data
		.rp_startofpacket        (sysid_qsys_control_slave_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_001_src_ready),                                     //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_001_src_valid),                                     //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_001_src_data),                                      //   input,  width = 118,                .data
		.cp_startofpacket        (cmd_mux_001_src_startofpacket),                             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_001_src_endofpacket),                               //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_001_src_channel),                                   //   input,    width = 4,                .channel
		.rf_sink_ready           (sysid_qsys_control_slave_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (sysid_qsys_control_slave_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (sysid_qsys_control_slave_agent_rsp_fifo_out_data),          //   input,  width = 119,                .data
		.rf_source_ready         (sysid_qsys_control_slave_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (sysid_qsys_control_slave_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (sysid_qsys_control_slave_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (sysid_qsys_control_slave_agent_rf_source_data),             //  output,  width = 119,                .data
		.rdata_fifo_sink_ready   (sysid_qsys_control_slave_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sysid_qsys_control_slave_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (sysid_qsys_control_slave_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (sysid_qsys_control_slave_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sysid_qsys_control_slave_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (sysid_qsys_control_slave_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                     // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                      // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                       // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (119),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) sysid_qsys_control_slave_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                         //   input,    width = 1,       clk.clk
		.reset             (jtag_uart_reset_reset_bridge_in_reset_reset),               //   input,    width = 1, clk_reset.reset
		.in_data           (sysid_qsys_control_slave_agent_rf_source_data),             //   input,  width = 119,        in.data
		.in_valid          (sysid_qsys_control_slave_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (sysid_qsys_control_slave_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (sysid_qsys_control_slave_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (sysid_qsys_control_slave_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (sysid_qsys_control_slave_agent_rsp_fifo_out_data),          //  output,  width = 119,       out.data
		.out_valid         (sysid_qsys_control_slave_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (sysid_qsys_control_slave_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated),                         
		.csr_read          (1'b0),                                                      // (terminated),                         
		.csr_write         (1'b0),                                                      // (terminated),                         
		.csr_readdata      (),                                                          // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated),                         
		.almost_full_data  (),                                                          // (terminated),                         
		.almost_empty_data (),                                                          // (terminated),                         
		.in_empty          (1'b0),                                                      // (terminated),                         
		.out_empty         (),                                                          // (terminated),                         
		.in_error          (1'b0),                                                      // (terminated),                         
		.out_error         (),                                                          // (terminated),                         
		.in_channel        (1'b0),                                                      // (terminated),                         
		.out_channel       ()                                                           // (terminated),                         
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (67),
		.PKT_BURST_SIZE_L          (65),
		.PKT_TRANS_LOCK            (59),
		.PKT_BEGIN_BURST           (72),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (64),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (54),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (55),
		.PKT_TRANS_POSTED          (56),
		.PKT_TRANS_WRITE           (57),
		.PKT_TRANS_READ            (58),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (74),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (76),
		.PKT_POISON_H              (100),
		.PKT_POISON_L              (100),
		.PKT_DATACHK_H             (101),
		.PKT_DATACHK_L             (101),
		.PKT_SAI_H                 (105),
		.PKT_SAI_L                 (105),
		.PKT_ADDRCHK_H             (104),
		.PKT_ADDRCHK_L             (103),
		.PKT_USER_DATA_H           (102),
		.PKT_USER_DATA_L           (102),
		.PKT_ATRACE                (115),
		.PKT_TRACE                 (116),
		.PKT_AWAKEUP               (117),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (118),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) pio_sw_s1_agent (
		.clk                     (iopll_outclk0_clk),                                      //   input,    width = 1,             clk.clk
		.reset                   (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (pio_sw_s1_agent_m0_address),                             //  output,   width = 19,              m0.address
		.m0_burstcount           (pio_sw_s1_agent_m0_burstcount),                          //  output,    width = 3,                .burstcount
		.m0_byteenable           (pio_sw_s1_agent_m0_byteenable),                          //  output,    width = 4,                .byteenable
		.m0_debugaccess          (pio_sw_s1_agent_m0_debugaccess),                         //  output,    width = 1,                .debugaccess
		.m0_lock                 (pio_sw_s1_agent_m0_lock),                                //  output,    width = 1,                .lock
		.m0_readdata             (pio_sw_s1_agent_m0_readdata),                            //   input,   width = 32,                .readdata
		.m0_readdatavalid        (pio_sw_s1_agent_m0_readdatavalid),                       //   input,    width = 1,                .readdatavalid
		.m0_read                 (pio_sw_s1_agent_m0_read),                                //  output,    width = 1,                .read
		.m0_waitrequest          (pio_sw_s1_agent_m0_waitrequest),                         //   input,    width = 1,                .waitrequest
		.m0_writedata            (pio_sw_s1_agent_m0_writedata),                           //  output,   width = 32,                .writedata
		.m0_write                (pio_sw_s1_agent_m0_write),                               //  output,    width = 1,                .write
		.rp_endofpacket          (pio_sw_s1_agent_rp_endofpacket),                         //  output,    width = 1,              rp.endofpacket
		.rp_ready                (pio_sw_s1_agent_rp_ready),                               //   input,    width = 1,                .ready
		.rp_valid                (pio_sw_s1_agent_rp_valid),                               //  output,    width = 1,                .valid
		.rp_data                 (pio_sw_s1_agent_rp_data),                                //  output,  width = 118,                .data
		.rp_startofpacket        (pio_sw_s1_agent_rp_startofpacket),                       //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_002_src_ready),                                  //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_002_src_valid),                                  //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_002_src_data),                                   //   input,  width = 118,                .data
		.cp_startofpacket        (cmd_mux_002_src_startofpacket),                          //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_002_src_endofpacket),                            //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_002_src_channel),                                //   input,    width = 4,                .channel
		.rf_sink_ready           (pio_sw_s1_agent_rsp_fifo_out_ready),                     //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (pio_sw_s1_agent_rsp_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (pio_sw_s1_agent_rsp_fifo_out_startofpacket),             //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (pio_sw_s1_agent_rsp_fifo_out_endofpacket),               //   input,    width = 1,                .endofpacket
		.rf_sink_data            (pio_sw_s1_agent_rsp_fifo_out_data),                      //   input,  width = 119,                .data
		.rf_source_ready         (pio_sw_s1_agent_rf_source_ready),                        //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (pio_sw_s1_agent_rf_source_valid),                        //  output,    width = 1,                .valid
		.rf_source_startofpacket (pio_sw_s1_agent_rf_source_startofpacket),                //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (pio_sw_s1_agent_rf_source_endofpacket),                  //  output,    width = 1,                .endofpacket
		.rf_source_data          (pio_sw_s1_agent_rf_source_data),                         //  output,  width = 119,                .data
		.rdata_fifo_sink_ready   (pio_sw_s1_agent_rdata_fifo_src_ready),                   //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (pio_sw_s1_agent_rdata_fifo_src_valid),                   //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (pio_sw_s1_agent_rdata_fifo_src_data),                    //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (pio_sw_s1_agent_rdata_fifo_src_ready),                   //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (pio_sw_s1_agent_rdata_fifo_src_valid),                   //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (pio_sw_s1_agent_rdata_fifo_src_data),                    //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                  // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                   // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                    // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (119),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) pio_sw_s1_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                           //   input,    width = 1,       clk.clk
		.reset             (jtag_uart_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_data           (pio_sw_s1_agent_rf_source_data),              //   input,  width = 119,        in.data
		.in_valid          (pio_sw_s1_agent_rf_source_valid),             //   input,    width = 1,          .valid
		.in_ready          (pio_sw_s1_agent_rf_source_ready),             //  output,    width = 1,          .ready
		.in_startofpacket  (pio_sw_s1_agent_rf_source_startofpacket),     //   input,    width = 1,          .startofpacket
		.in_endofpacket    (pio_sw_s1_agent_rf_source_endofpacket),       //   input,    width = 1,          .endofpacket
		.out_data          (pio_sw_s1_agent_rsp_fifo_out_data),           //  output,  width = 119,       out.data
		.out_valid         (pio_sw_s1_agent_rsp_fifo_out_valid),          //  output,    width = 1,          .valid
		.out_ready         (pio_sw_s1_agent_rsp_fifo_out_ready),          //   input,    width = 1,          .ready
		.out_startofpacket (pio_sw_s1_agent_rsp_fifo_out_startofpacket),  //  output,    width = 1,          .startofpacket
		.out_endofpacket   (pio_sw_s1_agent_rsp_fifo_out_endofpacket),    //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                       // (terminated),                         
		.csr_read          (1'b0),                                        // (terminated),                         
		.csr_write         (1'b0),                                        // (terminated),                         
		.csr_readdata      (),                                            // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),        // (terminated),                         
		.almost_full_data  (),                                            // (terminated),                         
		.almost_empty_data (),                                            // (terminated),                         
		.in_empty          (1'b0),                                        // (terminated),                         
		.out_empty         (),                                            // (terminated),                         
		.in_error          (1'b0),                                        // (terminated),                         
		.out_error         (),                                            // (terminated),                         
		.in_channel        (1'b0),                                        // (terminated),                         
		.out_channel       ()                                             // (terminated),                         
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (90),
		.PKT_ORI_BURST_SIZE_L      (88),
		.PKT_RESPONSE_STATUS_H     (87),
		.PKT_RESPONSE_STATUS_L     (86),
		.PKT_BURST_SIZE_H          (67),
		.PKT_BURST_SIZE_L          (65),
		.PKT_TRANS_LOCK            (59),
		.PKT_BEGIN_BURST           (72),
		.PKT_PROTECTION_H          (81),
		.PKT_PROTECTION_L          (79),
		.PKT_BURSTWRAP_H           (64),
		.PKT_BURSTWRAP_L           (64),
		.PKT_BYTE_CNT_H            (63),
		.PKT_BYTE_CNT_L            (61),
		.PKT_ADDR_H                (54),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (55),
		.PKT_TRANS_POSTED          (56),
		.PKT_TRANS_WRITE           (57),
		.PKT_TRANS_READ            (58),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (75),
		.PKT_SRC_ID_L              (74),
		.PKT_DEST_ID_H             (77),
		.PKT_DEST_ID_L             (76),
		.PKT_POISON_H              (100),
		.PKT_POISON_L              (100),
		.PKT_DATACHK_H             (101),
		.PKT_DATACHK_L             (101),
		.PKT_SAI_H                 (105),
		.PKT_SAI_L                 (105),
		.PKT_ADDRCHK_H             (104),
		.PKT_ADDRCHK_L             (103),
		.PKT_USER_DATA_H           (102),
		.PKT_USER_DATA_L           (102),
		.PKT_ATRACE                (115),
		.PKT_TRACE                 (116),
		.PKT_AWAKEUP               (117),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (4),
		.ST_DATA_W                 (118),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) spi_master_spi_control_port_agent (
		.clk                     (iopll_outclk0_clk),                                            //   input,    width = 1,             clk.clk
		.reset                   (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset),       //   input,    width = 1,       clk_reset.reset
		.m0_address              (spi_master_spi_control_port_agent_m0_address),                 //  output,   width = 19,              m0.address
		.m0_burstcount           (spi_master_spi_control_port_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (spi_master_spi_control_port_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (spi_master_spi_control_port_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (spi_master_spi_control_port_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (spi_master_spi_control_port_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (spi_master_spi_control_port_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (spi_master_spi_control_port_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (spi_master_spi_control_port_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (spi_master_spi_control_port_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (spi_master_spi_control_port_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (spi_master_spi_control_port_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (spi_master_spi_control_port_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (spi_master_spi_control_port_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (spi_master_spi_control_port_agent_rp_data),                    //  output,  width = 118,                .data
		.rp_startofpacket        (spi_master_spi_control_port_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_003_src_ready),                                        //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_003_src_valid),                                        //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_003_src_data),                                         //   input,  width = 118,                .data
		.cp_startofpacket        (cmd_mux_003_src_startofpacket),                                //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_003_src_endofpacket),                                  //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_003_src_channel),                                      //   input,    width = 4,                .channel
		.rf_sink_ready           (spi_master_spi_control_port_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (spi_master_spi_control_port_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (spi_master_spi_control_port_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (spi_master_spi_control_port_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (spi_master_spi_control_port_agent_rsp_fifo_out_data),          //   input,  width = 119,                .data
		.rf_source_ready         (spi_master_spi_control_port_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (spi_master_spi_control_port_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (spi_master_spi_control_port_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (spi_master_spi_control_port_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (spi_master_spi_control_port_agent_rf_source_data),             //  output,  width = 119,                .data
		.rdata_fifo_sink_ready   (spi_master_spi_control_port_agent_rdata_fifo_src_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (spi_master_spi_control_port_agent_rdata_fifo_src_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (spi_master_spi_control_port_agent_rdata_fifo_src_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (spi_master_spi_control_port_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (spi_master_spi_control_port_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (spi_master_spi_control_port_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                        // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                         // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                          // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (119),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) spi_master_spi_control_port_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                            //   input,    width = 1,       clk.clk
		.reset             (jtag_uart_reset_reset_bridge_in_reset_reset),                  //   input,    width = 1, clk_reset.reset
		.in_data           (spi_master_spi_control_port_agent_rf_source_data),             //   input,  width = 119,        in.data
		.in_valid          (spi_master_spi_control_port_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (spi_master_spi_control_port_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (spi_master_spi_control_port_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (spi_master_spi_control_port_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (spi_master_spi_control_port_agent_rsp_fifo_out_data),          //  output,  width = 119,       out.data
		.out_valid         (spi_master_spi_control_port_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (spi_master_spi_control_port_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (spi_master_spi_control_port_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (spi_master_spi_control_port_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated),                         
		.csr_read          (1'b0),                                                         // (terminated),                         
		.csr_write         (1'b0),                                                         // (terminated),                         
		.csr_readdata      (),                                                             // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated),                         
		.almost_full_data  (),                                                             // (terminated),                         
		.almost_empty_data (),                                                             // (terminated),                         
		.in_empty          (1'b0),                                                         // (terminated),                         
		.out_empty         (),                                                             // (terminated),                         
		.in_error          (1'b0),                                                         // (terminated),                         
		.out_error         (),                                                             // (terminated),                         
		.in_channel        (1'b0),                                                         // (terminated),                         
		.out_channel       ()                                                              // (terminated),                         
	);

	nios_system_altera_merlin_router_1921_r4sqfxq router (
		.sink_ready         (mm_bridge_peripheral_m0_agent_cp_ready),                 //  output,    width = 1,      sink.ready
		.sink_valid         (mm_bridge_peripheral_m0_agent_cp_valid),                 //   input,    width = 1,          .valid
		.sink_data          (mm_bridge_peripheral_m0_agent_cp_data),                  //   input,  width = 118,          .data
		.sink_startofpacket (mm_bridge_peripheral_m0_agent_cp_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (mm_bridge_peripheral_m0_agent_cp_endofpacket),           //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                       //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                       //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                        //  output,  width = 118,          .data
		.src_channel        (router_src_channel),                                     //  output,    width = 4,          .channel
		.src_startofpacket  (router_src_startofpacket),                               //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                  //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_pfc4ega router_001 (
		.sink_ready         (jtag_uart_avalon_jtag_slave_agent_rp_ready),             //  output,    width = 1,      sink.ready
		.sink_valid         (jtag_uart_avalon_jtag_slave_agent_rp_valid),             //   input,    width = 1,          .valid
		.sink_data          (jtag_uart_avalon_jtag_slave_agent_rp_data),              //   input,  width = 118,          .data
		.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),       //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                   //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                   //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                    //  output,  width = 118,          .data
		.src_channel        (router_001_src_channel),                                 //  output,    width = 4,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                              //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_pfc4ega router_002 (
		.sink_ready         (sysid_qsys_control_slave_agent_rp_ready),                //  output,    width = 1,      sink.ready
		.sink_valid         (sysid_qsys_control_slave_agent_rp_valid),                //   input,    width = 1,          .valid
		.sink_data          (sysid_qsys_control_slave_agent_rp_data),                 //   input,  width = 118,          .data
		.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket),        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sysid_qsys_control_slave_agent_rp_endofpacket),          //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                   //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                   //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                    //  output,  width = 118,          .data
		.src_channel        (router_002_src_channel),                                 //  output,    width = 4,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                              //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_pfc4ega router_003 (
		.sink_ready         (pio_sw_s1_agent_rp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (pio_sw_s1_agent_rp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (pio_sw_s1_agent_rp_data),                                //   input,  width = 118,          .data
		.sink_startofpacket (pio_sw_s1_agent_rp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (pio_sw_s1_agent_rp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                                   //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                                   //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                                    //  output,  width = 118,          .data
		.src_channel        (router_003_src_channel),                                 //  output,    width = 4,          .channel
		.src_startofpacket  (router_003_src_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                              //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_pfc4ega router_004 (
		.sink_ready         (spi_master_spi_control_port_agent_rp_ready),             //  output,    width = 1,      sink.ready
		.sink_valid         (spi_master_spi_control_port_agent_rp_valid),             //   input,    width = 1,          .valid
		.sink_data          (spi_master_spi_control_port_agent_rp_data),              //   input,  width = 118,          .data
		.sink_startofpacket (spi_master_spi_control_port_agent_rp_startofpacket),     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (spi_master_spi_control_port_agent_rp_endofpacket),       //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                                   //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                                   //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                                    //  output,  width = 118,          .data
		.src_channel        (router_004_src_channel),                                 //  output,    width = 4,          .channel
		.src_startofpacket  (router_004_src_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                              //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_traffic_limiter_1921_p3fvlba #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (77),
		.PKT_DEST_ID_L                        (76),
		.PKT_SRC_ID_H                         (75),
		.PKT_SRC_ID_L                         (74),
		.PKT_BYTE_CNT_H                       (63),
		.PKT_BYTE_CNT_L                       (61),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (56),
		.PKT_TRANS_WRITE                      (57),
		.PKT_TRANS_SEQ_H                      (114),
		.PKT_TRANS_SEQ_L                      (108),
		.MAX_OUTSTANDING_RESPONSES            (2),
		.PIPELINED                            (0),
		.ST_DATA_W                            (118),
		.ST_CHANNEL_W                         (4),
		.VALID_WIDTH                          (4),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) mm_bridge_peripheral_m0_limiter (
		.clk                    (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset                  (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                       //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                       //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                        //   input,  width = 118,          .data
		.cmd_sink_channel       (router_src_channel),                                     //   input,    width = 4,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                               //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (mm_bridge_peripheral_m0_limiter_cmd_src_ready),          //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (mm_bridge_peripheral_m0_limiter_cmd_src_data),           //  output,  width = 118,          .data
		.cmd_src_channel        (mm_bridge_peripheral_m0_limiter_cmd_src_channel),        //  output,    width = 4,          .channel
		.cmd_src_startofpacket  (mm_bridge_peripheral_m0_limiter_cmd_src_startofpacket),  //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (mm_bridge_peripheral_m0_limiter_cmd_src_endofpacket),    //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                      //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                      //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                    //   input,    width = 4,          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                       //   input,  width = 118,          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                              //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (mm_bridge_peripheral_m0_limiter_rsp_src_ready),          //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (mm_bridge_peripheral_m0_limiter_rsp_src_valid),          //  output,    width = 1,          .valid
		.rsp_src_data           (mm_bridge_peripheral_m0_limiter_rsp_src_data),           //  output,  width = 118,          .data
		.rsp_src_channel        (mm_bridge_peripheral_m0_limiter_rsp_src_channel),        //  output,    width = 4,          .channel
		.rsp_src_startofpacket  (mm_bridge_peripheral_m0_limiter_rsp_src_startofpacket),  //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (mm_bridge_peripheral_m0_limiter_rsp_src_endofpacket),    //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (mm_bridge_peripheral_m0_limiter_cmd_valid_data)          //  output,    width = 4, cmd_valid.data
	);

	nios_system_altera_merlin_demultiplexer_1921_bixj62q cmd_demux (
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,        clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1,  clk_reset.reset
		.sink_ready         (mm_bridge_peripheral_m0_limiter_cmd_src_ready),          //  output,    width = 1,       sink.ready
		.sink_channel       (mm_bridge_peripheral_m0_limiter_cmd_src_channel),        //   input,    width = 4,           .channel
		.sink_data          (mm_bridge_peripheral_m0_limiter_cmd_src_data),           //   input,  width = 118,           .data
		.sink_startofpacket (mm_bridge_peripheral_m0_limiter_cmd_src_startofpacket),  //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (mm_bridge_peripheral_m0_limiter_cmd_src_endofpacket),    //   input,    width = 1,           .endofpacket
		.sink_valid         (mm_bridge_peripheral_m0_limiter_cmd_valid_data),         //   input,    width = 4, sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                   //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                   //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_src0_data),                                    //  output,  width = 118,           .data
		.src0_channel       (cmd_demux_src0_channel),                                 //  output,    width = 4,           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                           //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                             //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                   //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                   //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_src1_data),                                    //  output,  width = 118,           .data
		.src1_channel       (cmd_demux_src1_channel),                                 //  output,    width = 4,           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                           //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                             //  output,    width = 1,           .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                                   //   input,    width = 1,       src2.ready
		.src2_valid         (cmd_demux_src2_valid),                                   //  output,    width = 1,           .valid
		.src2_data          (cmd_demux_src2_data),                                    //  output,  width = 118,           .data
		.src2_channel       (cmd_demux_src2_channel),                                 //  output,    width = 4,           .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                           //  output,    width = 1,           .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket),                             //  output,    width = 1,           .endofpacket
		.src3_ready         (cmd_demux_src3_ready),                                   //   input,    width = 1,       src3.ready
		.src3_valid         (cmd_demux_src3_valid),                                   //  output,    width = 1,           .valid
		.src3_data          (cmd_demux_src3_data),                                    //  output,  width = 118,           .data
		.src3_channel       (cmd_demux_src3_channel),                                 //  output,    width = 4,           .channel
		.src3_startofpacket (cmd_demux_src3_startofpacket),                           //  output,    width = 1,           .startofpacket
		.src3_endofpacket   (cmd_demux_src3_endofpacket)                              //  output,    width = 1,           .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_vgugpha cmd_mux (
		.clk                 (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset               (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                      //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                      //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                       //  output,  width = 118,          .data
		.src_channel         (cmd_mux_src_channel),                                    //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                   //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                   //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                 //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src0_data),                                    //   input,  width = 118,          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                              //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_vgugpha cmd_mux_001 (
		.clk                 (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset               (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                  //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                  //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                   //  output,  width = 118,          .data
		.src_channel         (cmd_mux_001_src_channel),                                //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                          //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                            //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                                   //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                                   //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src1_channel),                                 //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src1_data),                                    //   input,  width = 118,          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                              //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_vgugpha cmd_mux_002 (
		.clk                 (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset               (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                                  //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                                  //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                                   //  output,  width = 118,          .data
		.src_channel         (cmd_mux_002_src_channel),                                //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                          //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                            //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                                   //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                                   //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src2_channel),                                 //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src2_data),                                    //   input,  width = 118,          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket)                              //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_vgugpha cmd_mux_003 (
		.clk                 (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset               (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                                  //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                                  //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                                   //  output,  width = 118,          .data
		.src_channel         (cmd_mux_003_src_channel),                                //  output,    width = 4,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                          //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                            //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                                   //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                                   //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src3_channel),                                 //   input,    width = 4,          .channel
		.sink0_data          (cmd_demux_src3_data),                                    //   input,  width = 118,          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket)                              //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_jqica2q rsp_demux (
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                                   //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                                 //   input,    width = 4,          .channel
		.sink_data          (router_001_src_data),                                    //   input,  width = 118,          .data
		.sink_startofpacket (router_001_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                                   //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                   //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                   //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                    //  output,  width = 118,          .data
		.src0_channel       (rsp_demux_src0_channel),                                 //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                              //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_jqica2q rsp_demux_001 (
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                                   //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                                 //   input,    width = 4,          .channel
		.sink_data          (router_002_src_data),                                    //   input,  width = 118,          .data
		.sink_startofpacket (router_002_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                                   //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                               //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                               //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                                //  output,  width = 118,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                             //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                          //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_jqica2q rsp_demux_002 (
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_003_src_ready),                                   //  output,    width = 1,      sink.ready
		.sink_channel       (router_003_src_channel),                                 //   input,    width = 4,          .channel
		.sink_data          (router_003_src_data),                                    //   input,  width = 118,          .data
		.sink_startofpacket (router_003_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_003_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.sink_valid         (router_003_src_valid),                                   //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                               //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                               //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                                //  output,  width = 118,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                             //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket)                          //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_jqica2q rsp_demux_003 (
		.clk                (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_004_src_ready),                                   //  output,    width = 1,      sink.ready
		.sink_channel       (router_004_src_channel),                                 //   input,    width = 4,          .channel
		.sink_data          (router_004_src_data),                                    //   input,  width = 118,          .data
		.sink_startofpacket (router_004_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.sink_valid         (router_004_src_valid),                                   //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                               //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                               //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                                //  output,  width = 118,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                             //  output,    width = 4,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket)                          //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_dcphjea rsp_mux (
		.clk                 (iopll_outclk0_clk),                                      //   input,    width = 1,       clk.clk
		.reset               (mm_bridge_peripheral_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                      //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                      //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                       //  output,  width = 118,          .data
		.src_channel         (rsp_mux_src_channel),                                    //  output,    width = 4,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                              //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                   //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                   //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_src0_channel),                                 //   input,    width = 4,          .channel
		.sink0_data          (rsp_demux_src0_data),                                    //   input,  width = 118,          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                           //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                             //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                               //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                               //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                             //   input,    width = 4,          .channel
		.sink1_data          (rsp_demux_001_src0_data),                                //   input,  width = 118,          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket),                         //   input,    width = 1,          .endofpacket
		.sink2_ready         (rsp_demux_002_src0_ready),                               //  output,    width = 1,     sink2.ready
		.sink2_valid         (rsp_demux_002_src0_valid),                               //   input,    width = 1,          .valid
		.sink2_channel       (rsp_demux_002_src0_channel),                             //   input,    width = 4,          .channel
		.sink2_data          (rsp_demux_002_src0_data),                                //   input,  width = 118,          .data
		.sink2_startofpacket (rsp_demux_002_src0_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (rsp_demux_002_src0_endofpacket),                         //   input,    width = 1,          .endofpacket
		.sink3_ready         (rsp_demux_003_src0_ready),                               //  output,    width = 1,     sink3.ready
		.sink3_valid         (rsp_demux_003_src0_valid),                               //   input,    width = 1,          .valid
		.sink3_channel       (rsp_demux_003_src0_channel),                             //   input,    width = 4,          .channel
		.sink3_data          (rsp_demux_003_src0_data),                                //   input,  width = 118,          .data
		.sink3_startofpacket (rsp_demux_003_src0_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (rsp_demux_003_src0_endofpacket)                          //   input,    width = 1,          .endofpacket
	);

endmodule
