// onchip_memory.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module onchip_memory (
		input  wire        clk,        //   clk1.clk
		input  wire [15:0] address,    //     s1.address
		input  wire        read,       //       .read
		output wire [31:0] readdata,   //       .readdata
		input  wire [3:0]  byteenable, //       .byteenable
		input  wire        write,      //       .write
		input  wire [31:0] writedata,  //       .writedata
		input  wire        reset,      // reset1.reset
		input  wire        reset_req   //       .reset_req
	);

	onchip_memory_intel_onchip_memory_1410_lxuro4q #(
		.deviceFamily ("Agilex 3"),
		.INIT_FILE    ("onchip_memory_onchip_memory.hex")
	) onchip_memory (
		.clk        (clk),        //   input,   width = 1,   clk1.clk
		.address    (address),    //   input,  width = 16,     s1.address
		.read       (read),       //   input,   width = 1,       .read
		.readdata   (readdata),   //  output,  width = 32,       .readdata
		.byteenable (byteenable), //   input,   width = 4,       .byteenable
		.write      (write),      //   input,   width = 1,       .write
		.writedata  (writedata),  //   input,  width = 32,       .writedata
		.reset      (reset),      //   input,   width = 1, reset1.reset
		.reset_req  (reset_req)   //   input,   width = 1,       .reset_req
	);

endmodule
