| ed_synth |
|
| 2025.10.16.09:25:44 | Datasheet |
| mm_ccb_0 | |
| m0 | |
| ed_synth_emif_io96b_lpddr4b | |
| s0_axi4 | 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff |
| s0_axi4lite | |
| mm_ccb_0 | |
| s0 |
| user_pll | outclk0 | clock_bridge_0 |
| in_clk |
Parameters
|
Software Assignments(none) |
| mm_ccb_0 | m0 | ed_synth_emif_io96b_lpddr4b | |
| s0_axi4 | |||
| user_pll | outclk0 | ||
| s0_axi4_clock_in | |||
| outclk0 | |||
| s0_axi4lite_clock | |||
| reset_handler | reset_n_out | ||
| core_init_n | |||
| reset_n_out | |||
| s0_axi4lite_reset_n | |||
| s0_axi4_ctrl_ready | reset_bridge_0 | ||
| in_reset | |||
| s0_axi4_ctrl_ready | mm_ccb_0 | ||
| m0_reset | |||
| s0_axi4_ctrl_ready | |||
| s0_reset |
Parameters
|
Software Assignments(none) |
| user_pll | outclk0 | mm_ccb_0 | |
| m0_clk | |||
| outclk0 | |||
| s0_clk | |||
| ed_synth_emif_io96b_lpddr4b | s0_axi4_ctrl_ready | ||
| m0_reset | |||
| s0_axi4_ctrl_ready | |||
| s0_reset | |||
| m0 | ed_synth_emif_io96b_lpddr4b | ||
| s0_axi4 |
Parameters
|
Software Assignments(none) |
| ed_synth_emif_io96b_lpddr4b | s0_axi4_ctrl_ready | reset_bridge_0 |
| in_reset |
Parameters
|
Software Assignments(none) |
| user_pll | outclk0 | reset_handler | |
| clk | |||
| locked | |||
| conduit_0 | |||
| rrip | ninit_done | ||
| reset_n_0 | |||
| reset_n_out | ed_synth_emif_io96b_lpddr4b | ||
| core_init_n | |||
| reset_n_out | |||
| s0_axi4lite_reset_n |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
| rrip | ninit_done | user_pll | |
| reset | |||
| outclk0 | reset_handler | ||
| clk | |||
| locked | |||
| conduit_0 | |||
| outclk0 | clock_bridge_0 | ||
| in_clk | |||
| outclk0 | mm_ccb_0 | ||
| m0_clk | |||
| outclk0 | |||
| s0_clk | |||
| outclk0 | ed_synth_emif_io96b_lpddr4b | ||
| s0_axi4_clock_in | |||
| outclk0 | |||
| s0_axi4lite_clock |
Parameters
|
Software Assignments(none) |
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