{ "Info" "IDMS_INIT_MSG_DB" "" "Initialized Quartus Message Database" {  } {  } 0 21958 "Initialized Quartus Message Database" 0 0 "Design Software" 0 -1 0 ""}
{ "Info" "0" "" "Analyzing source files" {  } {  } 0 0 "Analyzing source files" 0 0 "0" 0 0 1768898242914 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_rrip/altera_s10_user_rst_clkgate_1949/synth/altera_s10_user_rst_clkgate.sv D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/reset_release/reset_release/altera_s10_user_rst_clkgate_1949/synth/altera_s10_user_rst_clkgate.sv " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_rrip/altera_s10_user_rst_clkgate_1949/synth/altera_s10_user_rst_clkgate.sv\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/reset_release/reset_release/altera_s10_user_rst_clkgate_1949/synth/altera_s10_user_rst_clkgate.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264225 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_traffic_limiter_1921/synth/altera_merlin_reorder_memory.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264235 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_traffic_limiter_1921/synth/altera_avalon_st_pipeline_base.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264235 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264235 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_reset_controller_1924/synth/altera_reset_controller.v D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264236 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264238 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/altera_reset_controller_1924/synth/altera_reset_controller.v D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_controller.v " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/altera_reset_controller_1924/synth/altera_reset_controller.v\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_controller.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264245 ""}
{ "Info" "IQIS_SKIPPING_DUP_FILE" "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/altera_reset_controller_1924/synth/altera_reset_synchronizer.v D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_synchronizer.v " "File \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" is a duplicate of already analyzed file \"D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_reset_controller_1924/synth/altera_reset_synchronizer.v\" (same filename, same library name and same md5 digest). Skipping analysis of this file." {  } {  } 0 18237 "File \"%1!s!\" is a duplicate of already analyzed file \"%2!s!\" (same filename, same library name and same md5 digest). Skipping analysis of this file." 0 0 "Design Software" 0 -1 1768898264246 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "rtl/slec/slec3_rx_gcc_define.h slec3_rx_top_enc.v(404) " "Verilog HDL info at slec3_rx_top_enc.v(404): analyzing included file rtl/slec/slec3_rx_gcc_define.h" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 404 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1768898265882 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "rtl/slec/slec3_rx_top_enc.v slec3_rx_top_enc.v(404) " "Verilog HDL info at slec3_rx_top_enc.v(404): back to file 'rtl/slec/slec3_rx_top_enc.v'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 404 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1768898265882 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "rtl/slec/slec3_rx_link_define.h slec3_rx_top_enc.v(6666) " "Verilog HDL info at slec3_rx_top_enc.v(6666): analyzing included file rtl/slec/slec3_rx_link_define.h" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 6666 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1768898266030 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "rtl/slec/slec3_rx_top_enc.v slec3_rx_top_enc.v(6666) " "Verilog HDL info at slec3_rx_top_enc.v(6666): back to file 'rtl/slec/slec3_rx_top_enc.v'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 6666 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1768898266030 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "rtl/slec/slec3_rx_link_define.h slec3_rx_top_enc.v(8840) " "Verilog HDL info at slec3_rx_top_enc.v(8840): analyzing included file rtl/slec/slec3_rx_link_define.h" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 8840 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1768898266086 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "rtl/slec/slec3_rx_top_enc.v slec3_rx_top_enc.v(8840) " "Verilog HDL info at slec3_rx_top_enc.v(8840): back to file 'rtl/slec/slec3_rx_top_enc.v'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 8840 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1768898266086 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "rtl/slec/slec3_rx_link_define.h slec3_rx_top_enc.v(13473) " "Verilog HDL info at slec3_rx_top_enc.v(13473): analyzing included file rtl/slec/slec3_rx_link_define.h" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 13473 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1768898266216 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "rtl/slec/slec3_rx_top_enc.v slec3_rx_top_enc.v(13473) " "Verilog HDL info at slec3_rx_top_enc.v(13473): back to file 'rtl/slec/slec3_rx_top_enc.v'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 13473 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1768898266216 ""}
{ "Info" "IVRFX2_VERI_2142_UNCONVERTED" "module altera_reset_controller altera_reset_controller.v(364) " "Verilog HDL info at altera_reset_controller.v(364): previous definition of module module altera_reset_controller is here" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/altera_reset_controller_1924/synth/altera_reset_controller.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/altera_reset_controller_1924/synth/altera_reset_controller.v" 364 0 0 0 } }  } 0 18437 "Verilog HDL info at %3!s!: previous definition of module %1!s! %2!s! is here" 0 0 "Design Software" 0 -1 1768898268216 ""}
{ "Info" "IVRFX2_VERI_2142_UNCONVERTED" "module altera_reset_synchronizer altera_reset_synchronizer.v(85) " "Verilog HDL info at altera_reset_synchronizer.v(85): previous definition of module module altera_reset_synchronizer is here" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/altera_reset_controller_1924/synth/altera_reset_synchronizer.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/altera_reset_controller_1924/synth/altera_reset_synchronizer.v" 85 0 0 0 } }  } 0 18437 "Verilog HDL info at %3!s!: previous definition of module %1!s! %2!s! is here" 0 0 "Design Software" 0 -1 1768898268217 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/cal_io96b_interface.svh ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv(17) " "Verilog HDL info at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv(17): analyzing included file ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/cal_io96b_interface.svh" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv" 17 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1768898268300 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv(17) " "Verilog HDL info at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv(17): back to file 'ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq.sv" 17 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1768898268301 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/emif_io96b_interface.svh ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv(17) " "Verilog HDL info at ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv(17): analyzing included file ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/emif_io96b_interface.svh" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv" 17 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1768898268393 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv(17) " "Verilog HDL info at ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv(17): back to file 'ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_arch_top.sv" 17 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1768898268394 ""}
{ "Info" "0" "" "Elaborating from top-level entity \"slvs_ec_rx_to_hdmi\"" {  } {  } 0 0 "Elaborating from top-level entity \"slvs_ec_rx_to_hdmi\"" 0 0 "0" 0 0 1768898268610 ""}
{ "Info" "IVRFX2_USER_LIBRARY_SEARCH_ORDER" "intel_adme_gts_100; intel_directphy_gts_1000; pcs_hal_2100; one_lane_hal_2100; fec_hal_2100; pldif_hal_2100; phy_hal_2100; hal_top_2100; n_channel_superset_2100; xcvr_rx; intel_srcss_gts_500; reset_seq; altera_s10_user_rst_clkgate_1949; reset_release; altera_iopll_2100; pll; altera_avalon_spi_1926; niosv_ss_spi_0; slec_rx_csr_10; niosv_ss_slec_rx_csr_0; niosv_ss_reset_in; altera_avalon_pio_1924; niosv_ss_pio_1; niosv_ss_pio_0; altera_avalon_jtag_uart_1931; niosv_ss_jtag_uart_0; intel_onchip_memory_1410; niosv_ss_intel_onchip_memory_0; altera_reset_controller_1924; intel_niosv_m_unit_2600; intel_niosv_timer_msip_120; intel_niosv_dbg_mod_210; altera_irq_mapper_2001; intel_niosv_m_2600; niosv_ss_intel_niosv_m_0; niosv_ss_clock_in; altera_merlin_axi_translator_1983; altera_merlin_slave_translator_191; altera_merlin_axi_master_ni_19113; altera_merlin_slave_agent_1930; altera_avalon_sc_fifo_1932; altera_merlin_router_1921; altera_merlin_traffic_limiter_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1922; altera_mm_interconnect_1920; niosv_ss; ed_synth_user_pll; ed_synth_rrip; mem_reset_handler_100; ed_synth_reset_handler; ed_synth_reset_bridge_0; st_dc_fifo_1953; mm_ccb_1930; ed_synth_mm_ccb_0; ed_synth_clock_bridge_0; altera_merlin_master_translator_193; altera_merlin_master_agent_1940; altera_merlin_axi_slave_ni_19123; altera_avalon_st_pipeline_stage_1930; ed_synth; altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; alt_mem_if_jtag_master_191; emif_io96b_cal_230; emif_io96b_lpddr4_410; ed_synth_emif_io96b_lpddr4b " "Library search order is as follows: \"intel_adme_gts_100; intel_directphy_gts_1000; pcs_hal_2100; one_lane_hal_2100; fec_hal_2100; pldif_hal_2100; phy_hal_2100; hal_top_2100; n_channel_superset_2100; xcvr_rx; intel_srcss_gts_500; reset_seq; altera_s10_user_rst_clkgate_1949; reset_release; altera_iopll_2100; pll; altera_avalon_spi_1926; niosv_ss_spi_0; slec_rx_csr_10; niosv_ss_slec_rx_csr_0; niosv_ss_reset_in; altera_avalon_pio_1924; niosv_ss_pio_1; niosv_ss_pio_0; altera_avalon_jtag_uart_1931; niosv_ss_jtag_uart_0; intel_onchip_memory_1410; niosv_ss_intel_onchip_memory_0; altera_reset_controller_1924; intel_niosv_m_unit_2600; intel_niosv_timer_msip_120; intel_niosv_dbg_mod_210; altera_irq_mapper_2001; intel_niosv_m_2600; niosv_ss_intel_niosv_m_0; niosv_ss_clock_in; altera_merlin_axi_translator_1983; altera_merlin_slave_translator_191; altera_merlin_axi_master_ni_19113; altera_merlin_slave_agent_1930; altera_avalon_sc_fifo_1932; altera_merlin_router_1921; altera_merlin_traffic_limiter_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1922; altera_mm_interconnect_1920; niosv_ss; ed_synth_user_pll; ed_synth_rrip; mem_reset_handler_100; ed_synth_reset_handler; ed_synth_reset_bridge_0; st_dc_fifo_1953; mm_ccb_1930; ed_synth_mm_ccb_0; ed_synth_clock_bridge_0; altera_merlin_master_translator_193; altera_merlin_master_agent_1940; altera_merlin_axi_slave_ni_19123; altera_avalon_st_pipeline_stage_1930; ed_synth; altera_jtag_dc_streaming_191; timing_adapter_1950; altera_avalon_st_bytes_to_packets_1922; altera_avalon_st_packets_to_bytes_1922; altera_avalon_packets_to_master_1922; channel_adapter_1922; alt_mem_if_jtag_master_191; emif_io96b_cal_230; emif_io96b_lpddr4_410; ed_synth_emif_io96b_lpddr4b\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." {  } {  } 0 18235 "Library search order is as follows: \"%1!s!\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." 0 0 "Design Software" 0 -1 1768898268621 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_agilex_config_reset_release_endpoint rtl altera_agilex_config_reset_release_endpoint.vhd(122) " "VHDL info at altera_agilex_config_reset_release_endpoint.vhd(122): executing entity \"altera_agilex_config_reset_release_endpoint\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270311 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric agilex_config_reset_release dir agent psig 142e1a3c\}\")(1,60)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270311 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 3 TFP410_I2C.v(152) " "Verilog HDL assignment warning at TFP410_I2C.v(152): truncated value with size 4 to match size of target (3)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/TFP410_I2C.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/TFP410_I2C.v" 152 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270312 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "11 10 TFP410_I2C.v(192) " "Verilog HDL assignment warning at TFP410_I2C.v(192): truncated value with size 11 to match size of target (10)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/TFP410_I2C.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/TFP410_I2C.v" 192 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270312 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_WRITE.v(69) " "Verilog HDL assignment warning at I2C_WRITE.v(69): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE.v" 69 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270315 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_WRITE.v(141) " "Verilog HDL assignment warning at I2C_WRITE.v(141): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE.v" 141 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270315 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_WRITE.v(151) " "Verilog HDL assignment warning at I2C_WRITE.v(151): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE.v" 151 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270315 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_WRITE_POINTER.v(68) " "Verilog HDL assignment warning at I2C_WRITE_POINTER.v(68): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE_POINTER.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE_POINTER.v" 68 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270325 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_WRITE_POINTER.v(133) " "Verilog HDL assignment warning at I2C_WRITE_POINTER.v(133): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE_POINTER.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE_POINTER.v" 133 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270326 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_WRITE_POINTER.v(143) " "Verilog HDL assignment warning at I2C_WRITE_POINTER.v(143): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE_POINTER.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_WRITE_POINTER.v" 143 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270326 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_READ_DATA.v(70) " "Verilog HDL assignment warning at I2C_READ_DATA.v(70): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" 70 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270326 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_READ_DATA.v(93) " "Verilog HDL assignment warning at I2C_READ_DATA.v(93): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" 93 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270326 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "9 8 I2C_READ_DATA.v(96) " "Verilog HDL assignment warning at I2C_READ_DATA.v(96): truncated value with size 9 to match size of target (8)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" 96 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270326 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 I2C_READ_DATA.v(107) " "Verilog HDL assignment warning at I2C_READ_DATA.v(107): truncated value with size 5 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/hdmi_i2c/I2C_READ_DATA.v" 107 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270326 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_config_clock_source_endpoint(1,1)(1,1) rtl altera_config_clock_source_endpoint.vhd(122) " "VHDL info at altera_config_clock_source_endpoint.vhd(122): executing entity \"altera_config_clock_source_endpoint(1,1)(1,1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_config_clock_source_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_config_clock_source_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270330 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric config_clock dir agent type_name \{0\} instance_name \{0\} psig b4c631e1\}\")(1,77) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=0,receive_width=1,settings=\"\{fabric config_clock dir agent type_name \{0\} instance_name \{0\} psig b4c631e1\}\")(1,77)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270330 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "48 32 altera_avalon_jtag_uart.sv(243) " "Verilog HDL assignment warning at altera_avalon_jtag_uart.sv(243): truncated value with size 48 to match size of target (32)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_jtag_uart_0/altera_avalon_jtag_uart_1931/synth/altera_avalon_jtag_uart.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_jtag_uart_0/altera_avalon_jtag_uart_1931/synth/altera_avalon_jtag_uart.sv" 243 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1768898270333 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_endpoint_adapter(sld_ir_width=1,sld_auto_instance_index=\"YES\",sld_node_info_internal=201354752)(1,1)(1,3) rtl sld_jtag_endpoint_adapter.vhd(96) " "VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity \"sld_jtag_endpoint_adapter(sld_ir_width=1,sld_auto_instance_index=\"YES\",sld_node_info_internal=201354752)(1,1)(1,3)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 96 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270334 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_sld_agent_endpoint(mfr_code=110,type_code=128,version=1,ir_width=1)(1,1)(1,1)(1,1) rtl altera_sld_agent_endpoint.vhd(122) " "VHDL info at altera_sld_agent_endpoint.vhd(122): executing entity \"altera_sld_agent_endpoint(mfr_code=110,type_code=128,version=1,ir_width=1)(1,1)(1,1)(1,1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270334 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=3,receive_width=24,settings=\"\{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance -1 ir_width 1 bridge_agent 0 prefer_host \{ \} type_name \{0\} instance_name \{0\} psig 9b67919e\}\")(1,159) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=3,receive_width=24,settings=\"\{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance -1 ir_width 1 bridge_agent 0 prefer_host \{ \} type_name \{0\} instance_name \{0\} psig 9b67919e\}\")(1,159)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270334 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "queue_mem niosv_instr_buffer.sv(58) " "Verilog HDL info at niosv_instr_buffer.sv(58): extracting RAM for identifier 'queue_mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_m_unit_2600/synth/niosv_instr_buffer.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_m_unit_2600/synth/niosv_instr_buffer.sv" 58 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270340 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_endpoint_adapter(sld_ir_width=5,sld_auto_instance_index=\"YES\",sld_node_info_internal=144207360)(1,1)(1,3) rtl sld_jtag_endpoint_adapter.vhd(96) " "VHDL info at sld_jtag_endpoint_adapter.vhd(96): executing entity \"sld_jtag_endpoint_adapter(sld_ir_width=5,sld_auto_instance_index=\"YES\",sld_node_info_internal=144207360)(1,1)(1,3)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 96 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270384 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_sld_agent_endpoint(mfr_code=110,type_code=19,version=1,ir_width=5)(1,1)(1,1)(1,1) rtl altera_sld_agent_endpoint.vhd(122) " "VHDL info at altera_sld_agent_endpoint.vhd(122): executing entity \"altera_sld_agent_endpoint(mfr_code=110,type_code=19,version=1,ir_width=5)(1,1)(1,1)(1,1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_sld_agent_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270384 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=7,receive_width=28,settings=\"\{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance -1 ir_width 5 bridge_agent 0 prefer_host \{ \} type_name \{0\} instance_name \{0\} psig 9b67919e\}\")(1,158) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=7,receive_width=28,settings=\"\{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance -1 ir_width 5 bridge_agent 0 prefer_host \{ \} type_name \{0\} instance_name \{0\} psig 9b67919e\}\")(1,158)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898270384 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "nxt_prog_buf niosv_debug_module.sv(140) " "Verilog HDL info at niosv_debug_module.sv(140): extracting RAM for identifier 'nxt_prog_buf'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" 140 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270391 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "prog_buf niosv_debug_module.sv(141) " "Verilog HDL info at niosv_debug_module.sv(141): extracting RAM for identifier 'prog_buf'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" 141 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270391 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "nxt_data_reg niosv_debug_module.sv(143) " "Verilog HDL info at niosv_debug_module.sv(143): extracting RAM for identifier 'nxt_data_reg'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" 143 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270391 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "data_reg niosv_debug_module.sv(144) " "Verilog HDL info at niosv_debug_module.sv(144): extracting RAM for identifier 'data_reg'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_intel_niosv_m_0/intel_niosv_dbg_mod_210/synth/niosv_debug_module.sv" 144 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270391 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v(317) " "Verilog HDL assignment warning at niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v(317): truncated value with size 7 to match size of target (6)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_spi_0/altera_avalon_spi_1926/synth/niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_spi_0/altera_avalon_spi_1926/synth/niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v" 317 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1768898270409 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v(324) " "Verilog HDL assignment warning at niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v(324): truncated value with size 32 to match size of target (1)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_spi_0/altera_avalon_spi_1926/synth/niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_spi_0/altera_avalon_spi_1926/synth/niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v" 324 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1768898270409 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v(357) " "Verilog HDL assignment warning at niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v(357): truncated value with size 32 to match size of target (24)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_spi_0/altera_avalon_spi_1926/synth/niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/ip/niosv_ss/niosv_ss_spi_0/altera_avalon_spi_1926/synth/niosv_ss_spi_0_altera_avalon_spi_1926_t6qkcmq.v" 357 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 1 0 "Design Software" 0 -1 1768898270409 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv(806) " "Verilog HDL assignment warning at niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv(806): truncated value with size 4 to match size of target (1)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_axi_translator_1983/synth/niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_axi_translator_1983/synth/niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv" 806 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270417 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv(807) " "Verilog HDL assignment warning at niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv(807): truncated value with size 4 to match size of target (1)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_axi_translator_1983/synth/niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_axi_translator_1983/synth/niosv_ss_altera_merlin_axi_translator_1983_ay2bjbi.sv" 807 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270417 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270440 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270443 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270445 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_avalon_sc_fifo_1932/synth/niosv_ss_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270450 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(135) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(135): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 135 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270462 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(142) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(142): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 142 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270462 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(149) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(149): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 149 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270462 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(156) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(156): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 156 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270462 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(163) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(163): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 163 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270462 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(170) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(170): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 170 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270462 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(177) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(177): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 177 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270465 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(184) " "Verilog HDL warning at niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv(184): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_demultiplexer_1921/synth/niosv_ss_altera_merlin_demultiplexer_1921_feouyxa.sv" 184 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898270465 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "niosv_ss_altera_merlin_multiplexer_1922_r4ye4pa.sv(307) " "Verilog HDL Case Statement warning at niosv_ss_altera_merlin_multiplexer_1922_r4ye4pa.sv(307): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_r4ye4pa.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_r4ye4pa.sv" 307 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1768898270470 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "niosv_ss_altera_merlin_multiplexer_1922_isv3q2y.sv(337) " "Verilog HDL Case Statement warning at niosv_ss_altera_merlin_multiplexer_1922_isv3q2y.sv(337): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_isv3q2y.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_isv3q2y.sv" 337 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1768898270473 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "niosv_ss_altera_merlin_multiplexer_1922_pv7zubq.sv(433) " "Verilog HDL Case Statement warning at niosv_ss_altera_merlin_multiplexer_1922_pv7zubq.sv(433): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_pv7zubq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_pv7zubq.sv" 433 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1768898270481 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "niosv_ss_altera_merlin_multiplexer_1922_3zypodi.sv(331) " "Verilog HDL Case Statement warning at niosv_ss_altera_merlin_multiplexer_1922_3zypodi.sv(331): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_3zypodi.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/niosv_ss/niosv_ss/altera_merlin_multiplexer_1922/synth/niosv_ss_altera_merlin_multiplexer_1922_3zypodi.sv" 331 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1768898270485 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "uxwrap_bus_out_phy_shared\[3\]\[703\] xcvr_rx_hal_top_2100_3wceqwq.sv(561) " "Net \"uxwrap_bus_out_phy_shared\[3\]\[703\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(561)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 561 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270670 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_addr_phy_shared\[3\]\[19\] xcvr_rx_hal_top_2100_3wceqwq.sv(562) " "Net \"lavmm_addr_phy_shared\[3\]\[19\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(562)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 562 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270671 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_be_phy_shared\[3\]\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(563) " "Net \"lavmm_be_phy_shared\[3\]\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(563)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 563 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270671 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_clk_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(564) " "Net \"lavmm_clk_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(564)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 564 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270671 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_read_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(565) " "Net \"lavmm_read_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(565)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 565 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270671 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_rstn_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(566) " "Net \"lavmm_rstn_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(566)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 566 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270671 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_wdata_phy_shared\[3\]\[31\] xcvr_rx_hal_top_2100_3wceqwq.sv(567) " "Net \"lavmm_wdata_phy_shared\[3\]\[31\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(567)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 567 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270671 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "lavmm_write_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(568) " "Net \"lavmm_write_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(568)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 568 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "dat_pcs_measlatrndtripbit_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(572) " "Net \"dat_pcs_measlatrndtripbit_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(572)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 572 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "sclk_return_sel_rx_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(573) " "Net \"sclk_return_sel_rx_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(573)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 573 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "sclk_return_sel_tx_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(574) " "Net \"sclk_return_sel_tx_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(574)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 574 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "s_o_ick_sclk_rx_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(575) " "Net \"s_o_ick_sclk_rx_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(575)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 575 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ft_rx_sclk_sync_ch_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(577) " "Net \"ft_rx_sclk_sync_ch_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(577)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 577 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ft_tx_sclk_sync_ch_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(578) " "Net \"ft_tx_sclk_sync_ch_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(578)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 578 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rst_ux_rx_pma_rst_n_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(579) " "Net \"rst_ux_rx_pma_rst_n_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(579)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 579 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rst_ux_tx_pma_rst_n_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(580) " "Net \"rst_ux_tx_pma_rst_n_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(580)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 580 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ick_pcs_txword_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(581) " "Net \"ick_pcs_txword_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(581)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 581 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "tx_dl_ch_bit_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(582) " "Net \"tx_dl_ch_bit_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(582)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 582 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "octl_pcs_txstatus_a_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(591) " "Net \"octl_pcs_txstatus_a_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(591)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 591 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "tx_data_phy_shared\[3\]\[79\] xcvr_rx_hal_top_2100_3wceqwq.sv(595) " "Net \"tx_data_phy_shared\[3\]\[79\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(595)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 595 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "sm_flux_ingress_phy_shared\[3\]\[319\] xcvr_rx_hal_top_2100_3wceqwq.sv(597) " "Net \"sm_flux_ingress_phy_shared\[3\]\[319\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(597)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 597 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ick_sclk_tx_phy_shared\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(602) " "Net \"ick_sclk_tx_phy_shared\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(602)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 602 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_addr_fec_wrap\[3\]\[19\] xcvr_rx_hal_top_2100_3wceqwq.sv(609) " "Net \"ch_lavmm_fec_addr_fec_wrap\[3\]\[19\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(609)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 609 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_be_fec_wrap\[3\]\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(610) " "Net \"ch_lavmm_fec_be_fec_wrap\[3\]\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(610)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 610 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_clk_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(611) " "Net \"ch_lavmm_fec_clk_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(611)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 611 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_read_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(612) " "Net \"ch_lavmm_fec_read_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(612)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 612 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_rstn_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(613) " "Net \"ch_lavmm_fec_rstn_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(613)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 613 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_wdata_fec_wrap\[3\]\[31\] xcvr_rx_hal_top_2100_3wceqwq.sv(614) " "Net \"ch_lavmm_fec_wdata_fec_wrap\[3\]\[31\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(614)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 614 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_lavmm_fec_write_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(615) " "Net \"ch_lavmm_fec_write_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(615)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 615 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_eth_fec_tx_async_fec_wrap\[3\]\[6\] xcvr_rx_hal_top_2100_3wceqwq.sv(621) " "Net \"ch_eth_fec_tx_async_fec_wrap\[3\]\[6\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(621)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 621 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ch_eth_fec_tx_direct_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(622) " "Net \"ch_eth_fec_tx_direct_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(622)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 622 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rstfec_fec_csr_ret_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(623) " "Net \"rstfec_fec_csr_ret_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(623)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 623 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rstfec_fec_rx_rst_n_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(625) " "Net \"rstfec_fec_rx_rst_n_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(625)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 625 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rstfec_fec_tx_rst_n_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(626) " "Net \"rstfec_fec_tx_rst_n_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(626)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 626 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rstfec_rx_fec_sfrz_n_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(627) " "Net \"rstfec_rx_fec_sfrz_n_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(627)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 627 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "rstfec_tx_fec_sfrz_n_fec_wrap\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(628) " "Net \"rstfec_tx_fec_sfrz_n_fec_wrap\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(628)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 628 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "fec_i_tx_mux_data_fec_wrap\[3\]\[42\] xcvr_rx_hal_top_2100_3wceqwq.sv(631) " "Net \"fec_i_tx_mux_data_fec_wrap\[3\]\[42\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(631)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 631 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "xcvr_rx_data\[3\]\[42\] xcvr_rx_hal_top_2100_3wceqwq.sv(632) " "Net \"xcvr_rx_data\[3\]\[42\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(632)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 632 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pma_rx_sf\[3\] xcvr_rx_hal_top_2100_3wceqwq.sv(634) " "Net \"pma_rx_sf\[3\]\" does not have a driver at xcvr_rx_hal_top_2100_3wceqwq.sv(634)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/xcvr_rx/xcvr_rx/hal_top_2100/synth/xcvr_rx_hal_top_2100_3wceqwq.sv" 634 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898270685 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "80 40 slec3_rx_top_enc.v(4794) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(4794): truncated value with size 80 to match size of target (40)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 4794 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270729 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3804) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3804): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3804 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270736 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3805) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3805): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3805 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270736 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3806) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3806): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3806 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270736 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "96 32 slec3_rx_top_enc.v(3807) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3807): truncated value with size 96 to match size of target (32)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3807 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270736 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 4 slec3_rx_top_enc.v(3808) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3808): truncated value with size 12 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3808 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270736 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff slec3_rx_top_enc.v(4373) " "Verilog HDL info at slec3_rx_top_enc.v(4373): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 4373 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270738 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3804) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3804): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3804 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270739 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3805) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3805): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3805 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270739 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3806) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3806): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3806 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270739 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "96 32 slec3_rx_top_enc.v(3807) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3807): truncated value with size 96 to match size of target (32)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3807 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270739 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 4 slec3_rx_top_enc.v(3808) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3808): truncated value with size 12 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3808 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270739 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3804) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3804): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3804 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270741 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3805) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3805): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3805 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270741 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3806) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3806): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3806 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270741 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "96 32 slec3_rx_top_enc.v(3807) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3807): truncated value with size 96 to match size of target (32)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3807 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270741 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 4 slec3_rx_top_enc.v(3808) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3808): truncated value with size 12 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3808 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270741 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3804) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3804): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3804 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270742 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3805) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3805): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3805 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270742 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 4 slec3_rx_top_enc.v(3806) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3806): truncated value with size 8 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3806 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270742 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "96 32 slec3_rx_top_enc.v(3807) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3807): truncated value with size 96 to match size of target (32)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3807 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270742 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 4 slec3_rx_top_enc.v(3808) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(3808): truncated value with size 12 to match size of target (4)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 3808 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270742 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 slec3_rx_top_enc.v(12798) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(12798): truncated value with size 32 to match size of target (3)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 12798 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270756 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff slec3_rx_top_enc.v(13404) " "Verilog HDL info at slec3_rx_top_enc.v(13404): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 13404 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270759 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 slec3_rx_top_enc.v(12798) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(12798): truncated value with size 32 to match size of target (3)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 12798 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270760 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 slec3_rx_top_enc.v(12798) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(12798): truncated value with size 32 to match size of target (3)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 12798 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270762 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 slec3_rx_top_enc.v(12798) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(12798): truncated value with size 32 to match size of target (3)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 12798 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270763 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff slec3_rx_top_enc.v(13404) " "Verilog HDL info at slec3_rx_top_enc.v(13404): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 13404 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898270873 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "1792 256 slec3_rx_top_enc.v(7393) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(7393): truncated value with size 1792 to match size of target (256)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 7393 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270895 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "1792 256 slec3_rx_top_enc.v(7413) " "Verilog HDL assignment warning at slec3_rx_top_enc.v(7413): truncated value with size 1792 to match size of target (256)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/slec/slec3_rx_top_enc.v" 7413 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898270895 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff srd_swr_ram.v(74) " "Verilog HDL info at srd_swr_ram.v(74): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/reference/srd_swr_ram.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/reference/srd_swr_ram.v" 74 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898271101 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff srd_swr_ram.v(74) " "Verilog HDL info at srd_swr_ram.v(74): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/reference/srd_swr_ram.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/reference/srd_swr_ram.v" 74 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898271102 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 13 scl16_din_ctl.v(751) " "Verilog HDL assignment warning at scl16_din_ctl.v(751): truncated value with size 14 to match size of target (13)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 751 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271116 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "14 13 scl16_din_ctl.v(899) " "Verilog HDL assignment warning at scl16_din_ctl.v(899): truncated value with size 14 to match size of target (13)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 899 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271118 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "32 13 dataa_i scl16_din_ctl.v(953) " "Verilog HDL warning at scl16_din_ctl.v(953): actual bit length 32 differs from formal bit length 13 for port \"dataa_i\"" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 953 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1768898271121 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1000) " "Verilog HDL assignment warning at scl16_din_ctl.v(1000): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1000 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271121 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1002) " "Verilog HDL assignment warning at scl16_din_ctl.v(1002): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1002 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1004) " "Verilog HDL assignment warning at scl16_din_ctl.v(1004): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1004 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1006) " "Verilog HDL assignment warning at scl16_din_ctl.v(1006): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1006 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "32 13 dataa_i scl16_din_ctl.v(953) " "Verilog HDL warning at scl16_din_ctl.v(953): actual bit length 32 differs from formal bit length 13 for port \"dataa_i\"" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 953 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1000) " "Verilog HDL assignment warning at scl16_din_ctl.v(1000): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1000 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1002) " "Verilog HDL assignment warning at scl16_din_ctl.v(1002): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1002 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1004) " "Verilog HDL assignment warning at scl16_din_ctl.v(1004): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1004 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1006) " "Verilog HDL assignment warning at scl16_din_ctl.v(1006): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1006 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271122 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "32 13 dataa_i scl16_din_ctl.v(953) " "Verilog HDL warning at scl16_din_ctl.v(953): actual bit length 32 differs from formal bit length 13 for port \"dataa_i\"" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 953 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1768898271123 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1000) " "Verilog HDL assignment warning at scl16_din_ctl.v(1000): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1000 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271123 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1002) " "Verilog HDL assignment warning at scl16_din_ctl.v(1002): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1002 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271123 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1004) " "Verilog HDL assignment warning at scl16_din_ctl.v(1004): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1004 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271123 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1006) " "Verilog HDL assignment warning at scl16_din_ctl.v(1006): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1006 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271123 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "32 13 dataa_i scl16_din_ctl.v(953) " "Verilog HDL warning at scl16_din_ctl.v(953): actual bit length 32 differs from formal bit length 13 for port \"dataa_i\"" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 953 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1768898271123 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1000) " "Verilog HDL assignment warning at scl16_din_ctl.v(1000): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1000 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271124 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1002) " "Verilog HDL assignment warning at scl16_din_ctl.v(1002): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1002 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271124 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1004) " "Verilog HDL assignment warning at scl16_din_ctl.v(1004): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1004 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271124 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "33 14 scl16_din_ctl.v(1006) " "Verilog HDL assignment warning at scl16_din_ctl.v(1006): truncated value with size 33 to match size of target (14)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_din_ctl.v" 1006 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271124 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "13 11 scl16_dout_ctl.v(557) " "Verilog HDL assignment warning at scl16_dout_ctl.v(557): truncated value with size 13 to match size of target (11)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_dout_ctl.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_dout_ctl.v" 557 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271154 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff scl16_srd_swr_ram.v(97) " "Verilog HDL info at scl16_srd_swr_ram.v(97): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_srd_swr_ram.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/scl16/scl16_srd_swr_ram.v" 97 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898271163 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 sfb16_packer.v(415) " "Verilog HDL assignment warning at sfb16_packer.v(415): truncated value with size 32 to match size of target (13)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_packer.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_packer.v" 415 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271166 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff sfb16_srd_swr_ram.v(93) " "Verilog HDL info at sfb16_srd_swr_ram.v(93): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_srd_swr_ram.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_srd_swr_ram.v" 93 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898271181 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "15 13 sfb16_timing_gen.v(584) " "Verilog HDL assignment warning at sfb16_timing_gen.v(584): truncated value with size 15 to match size of target (13)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_timing_gen.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_timing_gen.v" 584 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271212 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 sfb16_timing_gen.v(586) " "Verilog HDL assignment warning at sfb16_timing_gen.v(586): truncated value with size 32 to match size of target (13)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_timing_gen.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_timing_gen.v" 586 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271212 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 sfb16_timing_gen.v(587) " "Verilog HDL assignment warning at sfb16_timing_gen.v(587): truncated value with size 32 to match size of target (13)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_timing_gen.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/sfb/sfb16_timing_gen.v" 587 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898271212 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "core_avl_readdata\[7\] io0_ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_atom_inst_pll.sv(71) " "Net \"core_avl_readdata\[7\]\" does not have a driver at io0_ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_atom_inst_pll.sv(71)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/io96b_0/io0_ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_atom_inst_pll.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_lpddr4_410/synth/io96b_0/io0_ed_synth_emif_io96b_lpddr4b_emif_io96b_lpddr4_410_oln6iay_atom_inst_pll.sv" 71 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898271663 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "comp_to_seq__avl_readdata\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(194) " "Net \"comp_to_seq__avl_readdata\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(194)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 194 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272458 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane0\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(202) " "Net \"periph0_to_seq__avl_readdata_lane0\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(202)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 202 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272458 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane1\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(203) " "Net \"periph0_to_seq__avl_readdata_lane1\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(203)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 203 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272458 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane2\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(204) " "Net \"periph0_to_seq__avl_readdata_lane2\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(204)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 204 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272458 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane3\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(205) " "Net \"periph0_to_seq__avl_readdata_lane3\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(205)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 205 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272458 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane4\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(206) " "Net \"periph0_to_seq__avl_readdata_lane4\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(206)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 206 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane5\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(207) " "Net \"periph0_to_seq__avl_readdata_lane5\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(207)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 207 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane6\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(208) " "Net \"periph0_to_seq__avl_readdata_lane6\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(208)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 208 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_lane7\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(209) " "Net \"periph0_to_seq__avl_readdata_lane7\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(209)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 209 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pll0_to_seq__avl_readdata\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(216) " "Net \"pll0_to_seq__avl_readdata\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(216)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 216 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pll1_to_seq__avl_readdata\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(217) " "Net \"pll1_to_seq__avl_readdata\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(217)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 217 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "pll2_to_seq__avl_readdata\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(218) " "Net \"pll2_to_seq__avl_readdata\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(218)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 218 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__avl_readdata_ckgen\[31\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(225) " "Net \"periph0_to_seq__avl_readdata_ckgen\[31\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(225)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 225 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__phy_clk ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(226) " "Net \"periph0_to_seq__phy_clk\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(226)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 226 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_to_seq__phy_clksync ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(227) " "Net \"periph0_to_seq__phy_clksync\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(227)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 227 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph1_to_seq__phy_clk ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(228) " "Net \"periph1_to_seq__phy_clk\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(228)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 228 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph1_to_seq__phy_clksync ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(229) " "Net \"periph1_to_seq__phy_clksync\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(229)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 229 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa0_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(230) " "Net \"periph0_pa0_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(230)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 230 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272469 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa1_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(231) " "Net \"periph0_pa1_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(231)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 231 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa2_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(232) " "Net \"periph0_pa2_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(232)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 232 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa3_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(233) " "Net \"periph0_pa3_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(233)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 233 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa4_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(234) " "Net \"periph0_pa4_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(234)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 234 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa5_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(235) " "Net \"periph0_pa5_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(235)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 235 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa6_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(236) " "Net \"periph0_pa6_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(236)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 236 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph0_pa7_to_seq__rddata\[95\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(237) " "Net \"periph0_pa7_to_seq__rddata\[95\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(237)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 237 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "cpa_to_fa__lock\[1\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(289) " "Net \"cpa_to_fa__lock\[1\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(289)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 289 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "periph_calbus_0_b\[1097\] ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(566) " "Net \"periph_calbus_0_b\[1097\]\" does not have a driver at ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv(566)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_emif_io96b_lpddr4b/emif_io96b_cal_230/synth/ed_synth_emif_io96b_lpddr4b_emif_io96b_cal_230_wsiollq_cal_arch_fp_top.sv" 566 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898272470 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v(166) " "Verilog HDL info at ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v(166): extracting RAM for identifier 'mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_mm_ccb_0/st_dc_fifo_1953/synth/ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_mm_ccb_0/st_dc_fifo_1953/synth/ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v" 166 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898272545 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 ed_synth_mm_ccb_0_mm_ccb_1930_rqqepci.v(265) " "Verilog HDL assignment warning at ed_synth_mm_ccb_0_mm_ccb_1930_rqqepci.v(265): truncated value with size 32 to match size of target (5)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_mm_ccb_0/mm_ccb_1930/synth/ed_synth_mm_ccb_0_mm_ccb_1930_rqqepci.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_mm_ccb_0/mm_ccb_1930/synth/ed_synth_mm_ccb_0_mm_ccb_1930_rqqepci.v" 265 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1768898272556 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v(166) " "Verilog HDL info at ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v(166): extracting RAM for identifier 'mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_mm_ccb_0/st_dc_fifo_1953/synth/ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ip/ed_synth/ed_synth_mm_ccb_0/st_dc_fifo_1953/synth/ed_synth_mm_ccb_0_st_dc_fifo_1953_phmrs5y.v" 166 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898272557 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "infer_mem ed_synth_altera_avalon_sc_fifo_1932_22gxxgi.v(127) " "Verilog HDL info at ed_synth_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_avalon_sc_fifo_1932/synth/ed_synth_altera_avalon_sc_fifo_1932_22gxxgi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_avalon_sc_fifo_1932/synth/ed_synth_altera_avalon_sc_fifo_1932_22gxxgi.v" 127 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898272597 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv(93) " "Verilog HDL warning at ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv(93): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_demultiplexer_1921/synth/ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_demultiplexer_1921/synth/ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv" 93 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898272923 ""}
{ "Warning" "WVRFX2_VERI_SHIFT_GREATER_THAN_WIDTH" "right ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv(100) " "Verilog HDL warning at ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv(100): right shift count is greater than or equal to the width of the value" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_demultiplexer_1921/synth/ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_demultiplexer_1921/synth/ed_synth_altera_merlin_demultiplexer_1921_edss4by.sv" 100 0 0 0 } }  } 0 16753 "Verilog HDL warning at %2!s!: %1!s! shift count is greater than or equal to the width of the value" 1 0 "Design Software" 0 -1 1768898272923 ""}
{ "Warning" "WVRFX2_L2_VERI_PARALLEL_CASE_DIRECTIVE_EFFECTIVE" "ed_synth_altera_merlin_multiplexer_1922_6dcil5i.sv(331) " "Verilog HDL Case Statement warning at ed_synth_altera_merlin_multiplexer_1922_6dcil5i.sv(331): honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_multiplexer_1922/synth/ed_synth_altera_merlin_multiplexer_1922_6dcil5i.sv" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ip_intel/ed_synth/ed_synth/altera_merlin_multiplexer_1922/synth/ed_synth_altera_merlin_multiplexer_1922_6dcil5i.sv" 331 0 0 0 } }  } 0 13448 "Verilog HDL Case Statement warning at %1!s!: honored parallel_case synthesis attribute - differences between design synthesis and simulation may occur" 1 0 "Design Software" 0 -1 1768898272928 ""}
{ "Info" "IVRFX2_VERI_2571_UNCONVERTED" "mem_ff vtg11_srd_swr_ram.v(70) " "Verilog HDL info at vtg11_srd_swr_ram.v(70): extracting RAM for identifier 'mem_ff'" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/vtg/vtg11_srd_swr_ram.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/rtl/vtg/vtg11_srd_swr_ram.v" 70 0 0 0 } }  } 0 22567 "Verilog HDL info at %2!s!: extracting RAM for identifier '%1!s!'" 0 0 "Design Software" 0 -1 1768898272971 ""}
{ "Info" "IVRFX2_VRFX_FSM_HAS_UNCLEAN_RESET" "mgr_c_st " "Can't recognize finite state machine \"mgr_c_st\" because it has a complex reset state" {  } {  } 0 13246 "Can't recognize finite state machine \"%1!s!\" because it has a complex reset state" 0 0 "Design Software" 0 -1 1768898277570 ""}
{ "Info" "IVRFX2_VRFX_FSM_HAS_UNCLEAN_RESET" "sub_c_st " "Can't recognize finite state machine \"sub_c_st\" because it has a complex reset state" {  } {  } 0 13246 "Can't recognize finite state machine \"%1!s!\" because it has a complex reset state" 0 0 "Design Software" 0 -1 1768898277570 ""}
{ "Warning" "WMIO_MIO_HEX_DATA_WRAPPING_HEAD" "ram.hex 16384 10 " "Width of data items in \"ram.hex\" is greater than the memory width. Wrapping data items to subsequent addresses. Found 16384 warnings, reporting 10" { { "Warning" "WMIO_MIO_DATA_WRAPPING" "2 ram.hex " "Data at line (2) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 2 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "3 ram.hex " "Data at line (3) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 3 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "4 ram.hex " "Data at line (4) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 4 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "5 ram.hex " "Data at line (5) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 5 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "6 ram.hex " "Data at line (6) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 6 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "7 ram.hex " "Data at line (7) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 7 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "8 ram.hex " "Data at line (8) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 8 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "9 ram.hex " "Data at line (9) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 9 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "10 ram.hex " "Data at line (10) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 10 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""} { "Warning" "WMIO_MIO_DATA_WRAPPING" "11 ram.hex " "Data at line (11) of memory initialization file \"ram.hex\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 11 -1 0 0 } }  } 0 113009 "Data at line (%1!d!) of memory initialization file \"%2!s!\" is too wide to fit in one memory word. Wrapping data to subsequent addresses." 0 0 "Design Software" 0 -1 1768898280644 ""}  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/ram.hex" 1 -1 0 0 } }  } 0 113015 "Width of data items in \"%1!s!\" is greater than the memory width. Wrapping data items to subsequent addresses. Found %2!u! warnings, reporting %3!u!" 0 0 "Design Software" 0 -1 1768898280644 ""}
{ "Info" "0" "" "Found 660 design entities" {  } {  } 0 0 "Found 660 design entities" 0 0 "0" 0 0 1768898282281 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "HDMI_EDGE_HPD slvs_ec_rx_to_hdmi gnd top-level " "Output port \"HDMI_EDGE_HPD\" in top-level entity \"slvs_ec_rx_to_hdmi\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" 130 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1768898284480 "HDMI_EDGE_HPD"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "SLVS_EC_OMODE slvs_ec_rx_to_hdmi gnd top-level " "Output port \"SLVS_EC_OMODE\" in top-level entity \"slvs_ec_rx_to_hdmi\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" 141 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1768898284480 "SLVS_EC_OMODE"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_SCLK slvs_ec_rx_to_hdmi gnd top-level " "Output port \"INFO_SPI_SCLK\" in top-level entity \"slvs_ec_rx_to_hdmi\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" 308 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1768898284480 "INFO_SPI_SCLK"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_MOSI slvs_ec_rx_to_hdmi gnd top-level " "Output port \"INFO_SPI_MOSI\" in top-level entity \"slvs_ec_rx_to_hdmi\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" 310 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1768898284480 "INFO_SPI_MOSI"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_CS_n slvs_ec_rx_to_hdmi gnd top-level " "Output port \"INFO_SPI_CS_n\" in top-level entity \"slvs_ec_rx_to_hdmi\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/slvs_ec_rx_to_hdmi.v" 311 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1768898284480 "INFO_SPI_CS_n"}
{ "Info" "0" "" "There are 1771 partitions after elaboration." {  } {  } 0 0 "There are 1771 partitions after elaboration." 0 0 "0" 0 0 1768898284915 ""}
{ "Info" "" "Running rule checking for Agilex5 protocol IPs... " "Running rule checking for Agilex5 protocol IPs..." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1768898286423 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_ocp_endpoint(sld_ocp_timeout=3600,sld_ocp_ip_info=\"01000011011011100000000000101101\")(1,32) rtl altera_ocp_endpoint.vhd(122) " "VHDL info at altera_ocp_endpoint.vhd(122): executing entity \"altera_ocp_endpoint(sld_ocp_timeout=3600,sld_ocp_ip_info=\"01000011011011100000000000101101\")(1,32)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_ocp_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_ocp_endpoint.vhd" 122 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898290598 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_fabric_endpoint(send_width=2,receive_width=1,settings=\"\{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info \{01000011011011100000000000101101\} type_name \{0\} instance_name \{0\} psig 89ac057a\}\")(1,163) rtl altera_fabric_endpoint.vhd(126) " "VHDL info at altera_fabric_endpoint.vhd(126): executing entity \"altera_fabric_endpoint(send_width=2,receive_width=1,settings=\"\{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info \{01000011011011100000000000101101\} type_name \{0\} instance_name \{0\} psig 89ac057a\}\")(1,163)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd" 126 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898290598 ""}
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab_0 " "Starting IP generation for the debug fabric: alt_sld_fab_0." {  } {  } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Design Software" 0 -1 1768898291633 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Quartus is a registered trademark of Intel Corporation in the " "Quartus is a registered trademark of Intel Corporation in the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "US and other countries.  Portions of the Quartus Prime software " "US and other countries.  Portions of the Quartus Prime software" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Code, and other portions of the code included in this download " "Code, and other portions of the code included in this download" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Or on this DVD, are licensed to Intel Corporation and are the " "Or on this DVD, are licensed to Intel Corporation and are the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Copyrighted property of third parties. For license details, " "Copyrighted property of third parties. For license details," {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Refer to the End User License Agreement at " "Refer to the End User License Agreement at" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Http://fpgasoftware.intel.com/eula. " "Http://fpgasoftware.intel.com/eula." {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898291848 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302001 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302017 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302018 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302918 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302933 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302934 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898302997 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303012 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303013 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303090 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Deploying alt_sld_fab_0 to D:\\Downloads\\b\\SLVS_EC_RX_to_HDMI_IMX901_0120\\dni\\sandboxes\\JOHNNY2_11752_0\\sld\\ipgen\\alt_sld_fab_0.ip " "Deploying alt_sld_fab_0 to D:\\Downloads\\b\\SLVS_EC_RX_to_HDMI_IMX901_0120\\dni\\sandboxes\\JOHNNY2_11752_0\\sld\\ipgen\\alt_sld_fab_0.ip" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898303106 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Quartus is a registered trademark of Intel Corporation in the " "Quartus is a registered trademark of Intel Corporation in the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "US and other countries.  Portions of the Quartus Prime software " "US and other countries.  Portions of the Quartus Prime software" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Code, and other portions of the code included in this download " "Code, and other portions of the code included in this download" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Or on this DVD, are licensed to Intel Corporation and are the " "Or on this DVD, are licensed to Intel Corporation and are the" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Copyrighted property of third parties. For license details, " "Copyrighted property of third parties. For license details," {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Refer to the End User License Agreement at " "Refer to the End User License Agreement at" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Http://fpgasoftware.intel.com/eula. " "Http://fpgasoftware.intel.com/eula." {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "*************************************************************** " "***************************************************************" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898304673 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314683 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314699 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314702 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314703 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314704 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898314704 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315599 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315600 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315738 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315739 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315754 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315757 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315758 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315759 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315759 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Saving generation log to D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt " "Saving generation log to D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315910 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Generated by version: 25.3 build 109 " "Generated by version: 25.3 build 109" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315910 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Starting: Create HDL design files for synthesis " "Starting: Create HDL design files for synthesis" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315910 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Qsys-generate D:\\Downloads\\b\\SLVS_EC_RX_to_HDMI_IMX901_0120\\dni\\sandboxes\\JOHNNY2_11752_0\\sld\\ipgen\\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\\Downloads\\b\\SLVS_EC_RX_to_HDMI_IMX901_0120\\dni\\sandboxes\\JOHNNY2_11752_0\\sld\\ipgen\\alt_sld_fab_0 --family=\"Agilex 5\" --part=A5ED065BB32AE4SR0 " "Qsys-generate D:\\Downloads\\b\\SLVS_EC_RX_to_HDMI_IMX901_0120\\dni\\sandboxes\\JOHNNY2_11752_0\\sld\\ipgen\\alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=D:\\Downloads\\b\\SLVS_EC_RX_to_HDMI_IMX901_0120\\dni\\sandboxes\\JOHNNY2_11752_0\\sld\\ipgen\\alt_sld_fab_0 --family=\"Agilex 5\" --part=A5ED065BB32AE4SR0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898315910 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316082 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316098 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316175 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316190 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316190 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316190 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316190 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316190 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316190 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316191 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316192 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316192 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316192 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance splitter altera_sld_splitter " "Add_instance splitter altera_sld_splitter" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316267 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1 " "Set_instance_parameter_value splitter ADD_INTERFACE_ASGN 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ocpfabric altera_ocp_fabric " "Add_instance ocpfabric altera_ocp_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric COUNT 1 " "Set_instance_parameter_value ocpfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ocpfabric SETTINGS \{\{sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\} " "Send_message info \{SLD fabric agents which did not specify prefer_host were connected to JTAG\}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance jtagpins altera_jtag_wys_atom " "Add_instance jtagpins altera_jtag_wys_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance sldfabric altera_sld_jtag_hub " "Add_instance sldfabric altera_sld_jtag_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric COUNT 3 " "Set_instance_parameter_value sldfabric COUNT 3" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \} " "Set_instance_parameter_value sldfabric SETTINGS \{\{mfr_code 110 type_code 1 version 1 instance 0 ir_width 2 bridge_agent 0 prefer_host JTAG type_name 0 instance_name 0\} \{mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric CONN_INDEX 0 " "Set_instance_parameter_value sldfabric CONN_INDEX 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0 " "Set_instance_parameter_value sldfabric ENABLE_SOFT_CORE_CONTROLLER 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric BRIDGE_HOST 0 " "Set_instance_parameter_value sldfabric BRIDGE_HOST 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316268 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric USE_TCK_ENA 0 " "Set_instance_parameter_value sldfabric USE_TCK_ENA 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316283 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0 " "Set_instance_parameter_value sldfabric NEGEDGE_TDO_LATCH 0" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance ident altera_connection_identification_hub " "Add_instance ident altera_connection_identification_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237 " "Set_instance_parameter_value ident DESIGN_HASH 69fc99d8b78ec5850237" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident COUNT 1 " "Set_instance_parameter_value ident COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value ident SETTINGS \{\{width 4 latency 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance configresetfabric intel_configuration_debug_reset_release_hub " "Add_instance configresetfabric intel_configuration_debug_reset_release_hub" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric COUNT 1 " "Set_instance_parameter_value configresetfabric COUNT 1" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \} " "Set_instance_parameter_value configresetfabric SETTINGS \{\{is_source 0 type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance intosc altera_internal_oscillator_atom " "Add_instance intosc altera_internal_oscillator_atom" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance clockfabric altera_config_clock_fabric " "Add_instance clockfabric altera_config_clock_fabric" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value clockfabric SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm " "Add_instance agilexconfigreset intel_agilex_reset_release_from_sdm" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \} " "Set_instance_parameter_value agilexconfigreset SETTINGS \{\{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \{type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value agilexconfigreset COUNT 11 " "Set_instance_parameter_value agilexconfigreset COUNT 11" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \} " "Set_instance_parameter_value splitter FRAGMENTS \{\{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 1 23\} \{irq irq out 1 1\} \{ir_out ir_out out 1 2\} \} clock clock assign \{debug.controlledBy \{link_3\} \} moduleassign \{debug.virtualInterface.link_3 \{debug.endpointLink \{fabric sld index 1\} \} \} \} \} \{\{name clock type clock dir end ports \{ \{tck clk in 1 0\} \} \} \{name node type conduit dir end ports \{ \{tms tms in 1 1\} \{tdi tdi in 1 2\} \{tdo tdo out 1 0\} \{ena ena in 1 3\} \{usr1 usr1 in 1 4\} \{clr clr in 1 5\} \{clrn clrn in 1 6\} \{jtag_state_tlr jtag_state_tlr in 1 7\} \{jtag_state_rti jtag_state_rti in 1 8\} \{jtag_state_sdrs jtag_state_sdrs in 1 9\} \{jtag_state_cdr jtag_state_cdr in 1 10\} \{jtag_state_sdr jtag_state_sdr in 1 11\} \{jtag_state_e1dr jtag_state_e1dr in 1 12\} \{jtag_state_pdr jtag_state_pdr in 1 13\} \{jtag_state_e2dr jtag_state_e2dr in 1 14\} \{jtag_state_udr jtag_state_udr in 1 15\} \{jtag_state_sirs jtag_state_sirs in 1 16\} \{jtag_state_cir jtag_state_cir in 1 17\} \{jtag_state_sir jtag_state_sir in 1 18\} \{jtag_state_e1ir jtag_state_e1ir in 1 19\} \{jtag_state_pir jtag_state_pir in 1 20\} \{jtag_state_e2ir jtag_state_e2ir in 1 21\} \{jtag_state_uir jtag_state_uir in 1 22\} \{ir_in ir_in in 5 23\} \{irq irq out 1 1\} \{ir_out ir_out out 5 2\} \} clock clock assign \{debug.controlledBy \{link_4\} \} moduleassign \{debug.virtualInterface.link_4 \{debug.endpointLink \{fabric sld index 2\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name clk type clock dir end ports \{ \{clk clk in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \{\{name ocp type conduit dir end ports \{ \{ip_timeout ip_timeout in 1 0\} \} \} \} \{\{name conf_reset type reset dir end ports \{ \{conf_reset reset in 1 0\} \} properties \{ \{synchronousEdges \{None\} \} \} \} \} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316287 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit " "Add_connection ocpfabric.ocp_0 splitter.ocp_21 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.clock sldfabric.clock clock " "Add_connection jtagpins.clock sldfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection jtagpins.node sldfabric.node conduit " "Add_connection jtagpins.node sldfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_0 ocpfabric.clock clock " "Add_connection sldfabric.clock_0 ocpfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_0 ocpfabric.node conduit " "Add_connection sldfabric.node_0 ocpfabric.node conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_1 splitter.clock_4 clock " "Add_connection sldfabric.clock_1 splitter.clock_4 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_1 splitter.node_4 conduit " "Add_connection sldfabric.node_1 splitter.node_4 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.clock_2 splitter.clock_3 clock " "Add_connection sldfabric.clock_2 splitter.clock_3 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.node_2 splitter.node_3 conduit " "Add_connection sldfabric.node_2 splitter.node_3 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection sldfabric.ident ident.ident_0 conduit " "Add_connection sldfabric.ident ident.ident_0 conduit" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset " "Add_connection configresetfabric.conf_reset_out_0 sldfabric.conf_reset_out reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection intosc.clock clockfabric.clock clock " "Add_connection intosc.clock clockfabric.clock clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_0 splitter.clk_1 clock " "Add_connection clockfabric.clk_0 splitter.clk_1 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_1 splitter.clk_5 clock " "Add_connection clockfabric.clk_1 splitter.clk_5 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_2 splitter.clk_7 clock " "Add_connection clockfabric.clk_2 splitter.clk_7 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_3 splitter.clk_9 clock " "Add_connection clockfabric.clk_3 splitter.clk_9 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_4 splitter.clk_11 clock " "Add_connection clockfabric.clk_4 splitter.clk_11 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_5 splitter.clk_13 clock " "Add_connection clockfabric.clk_5 splitter.clk_13 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_6 splitter.clk_15 clock " "Add_connection clockfabric.clk_6 splitter.clk_15 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_7 splitter.clk_17 clock " "Add_connection clockfabric.clk_7 splitter.clk_17 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection clockfabric.clk_8 splitter.clk_19 clock " "Add_connection clockfabric.clk_8 splitter.clk_19 clock" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset " "Add_connection agilexconfigreset.conf_reset_0 splitter.conf_reset_0 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset " "Add_connection agilexconfigreset.conf_reset_1 splitter.conf_reset_2 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset " "Add_connection agilexconfigreset.conf_reset_2 splitter.conf_reset_6 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset " "Add_connection agilexconfigreset.conf_reset_3 splitter.conf_reset_8 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset " "Add_connection agilexconfigreset.conf_reset_4 splitter.conf_reset_10 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset " "Add_connection agilexconfigreset.conf_reset_5 splitter.conf_reset_12 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset " "Add_connection agilexconfigreset.conf_reset_6 splitter.conf_reset_14 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset " "Add_connection agilexconfigreset.conf_reset_7 splitter.conf_reset_16 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset " "Add_connection agilexconfigreset.conf_reset_8 splitter.conf_reset_18 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset " "Add_connection agilexconfigreset.conf_reset_9 splitter.conf_reset_20 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset " "Add_connection agilexconfigreset.conf_reset_10 splitter.conf_reset_22 reset" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \} " "Set_parameter_value COMPOSED_SETTINGS \{\{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric sld dir agent mfr_code 110 type_code 19 version 1 instance 0 ir_width 5 bridge_agent 0 prefer_host \{\} type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric config_clock dir agent type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \{fabric ocp dir agent sld_ocp_timeout 3600 sld_ocp_soft_timeout 1 sld_ocp_ip_info 01000011011011100000000000101101 type_name 0 instance_name 0\} \{fabric agilex_config_reset_release dir agent type_name 0 instance_name 0\} \}" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316288 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316424 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Transforming system: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Transforming system: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316534 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Naming system components in system: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Naming system components in system: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316627 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Processing generation queue\" " "Alt_sld_fab_0: \"Processing generation queue\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316630 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316631 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316658 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_1920_d5z3z7i\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_alt_sld_fab_1920_d5z3z7i\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316689 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_splitter_1920_2oanlby\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_splitter_1920_2oanlby\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316768 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: altera_ocp_fabric\" " "Alt_sld_fab_0: \"Generating: altera_ocp_fabric\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316783 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: altera_jtag_wys_atom\" " "Alt_sld_fab_0: \"Generating: altera_jtag_wys_atom\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316786 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316814 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_26yxm3y\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_altera_connection_identification_hub_1920_26yxm3y\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316830 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_ku24h5y\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_configuration_debug_reset_release_hub_203_ku24h5y\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316832 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Conf_reset_src: \"Generating: conf_reset_src\" " "Conf_reset_src: \"Generating: conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316834 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Grounded_conf_reset_src: \"Generating: grounded_conf_reset_src\" " "Grounded_conf_reset_src: \"Generating: grounded_conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316835 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: altera_internal_oscillator_atom\" " "Alt_sld_fab_0: \"Generating: altera_internal_oscillator_atom\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316835 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_bh2zisq\" " "Alt_sld_fab_0: \"Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_bh2zisq\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316838 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: conf_reset_src\" " "Alt_sld_fab_0: \"Generating: conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316842 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: grounded_conf_reset_src\" " "Alt_sld_fab_0: \"Generating: grounded_conf_reset_src\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316861 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_for_debug\" " "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_for_debug\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316862 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_to_debug_logic\" " "Alt_sld_fab_0: \"Generating: intel_configuration_reset_release_to_debug_logic\"" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316864 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab_0: Done \"alt_sld_fab_0\" with 15 modules, 17 files " "Alt_sld_fab_0: Done \"alt_sld_fab_0\" with 15 modules, 17 files" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898316866 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Finished: Create HDL design files for synthesis " "Finished: Create HDL design files for synthesis" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898317000 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Generation of D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 1123 ms " "Generation of D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 1123 ms" {  } {  } 0 11172 "%1!s!" 0 0 "Design Software" 0 -1 1768898317000 ""}
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab_0 " "Finished IP generation for the debug fabric: alt_sld_fab_0." {  } {  } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Design Software" 0 -1 1768898317860 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "altera_ocp_fabric(family=14,sld_ocp_timeout=3600,sld_ocp_timeout_width=12,sld_ocp_soft_timeout=1) rtl altera_ocp_fabric.vhd(12) " "VHDL info at altera_ocp_fabric.vhd(12): executing entity \"altera_ocp_fabric(family=14,sld_ocp_timeout=3600,sld_ocp_timeout_width=12,sld_ocp_soft_timeout=1)\" with architecture \"rtl\"" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/altera_ocp_fabric_1920/synth/altera_ocp_fabric.vhd" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/altera_ocp_fabric_1920/synth/altera_ocp_fabric.vhd" 12 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318271 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "pzdyqx(pzdyqx0=14,pzdyqx6=\"01000011011011100000000000101101\",pzdyqx1=3600,pzdyqx3=12,pzdyqx2=1)(31,0) rtl pzdyqx.vhd(116) " "VHDL info at pzdyqx.vhd(116): executing entity \"pzdyqx(pzdyqx0=14,pzdyqx6=\"01000011011011100000000000101101\",pzdyqx1=3600,pzdyqx3=12,pzdyqx2=1)(31,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 116 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318272 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "pzdyqx_impl(pzdyqx0=14,pzdyqx6=\"01000011011011100000000000101101\",pzdyqx1=3600,pzdyqx3=12,pzdyqx2=1)(31,0) rtl pzdyqx.vhd(267) " "VHDL info at pzdyqx.vhd(267): executing entity \"pzdyqx_impl(pzdyqx0=14,pzdyqx6=\"01000011011011100000000000101101\",pzdyqx1=3600,pzdyqx3=12,pzdyqx2=1)(31,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 267 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318272 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "YPHP7743(osc_stages=27,osc_prescaler=8,clk_gen_width=27) rtl pzdyqx.vhd(891) " "VHDL info at pzdyqx.vhd(891): executing entity \"YPHP7743(osc_stages=27,osc_prescaler=8,clk_gen_width=27)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 891 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318272 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "ZNZS8187(width=19,modulus=0) rtl pzdyqx.vhd(1079) " "VHDL info at pzdyqx.vhd(1079): executing entity \"ZNZS8187(width=19,modulus=0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 1079 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318273 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "ZNZS8187(width=12,modulus=3600) rtl pzdyqx.vhd(1079) " "VHDL info at pzdyqx.vhd(1079): executing entity \"ZNZS8187(width=12,modulus=3600)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 1079 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318275 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "ZNZS8187(width=1,modulus=1) rtl pzdyqx.vhd(1079) " "VHDL info at pzdyqx.vhd(1079): executing entity \"ZNZS8187(width=1,modulus=1)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 1079 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318276 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "FLAU0828(width=13) rtl pzdyqx.vhd(1184) " "VHDL info at pzdyqx.vhd(1184): executing entity \"FLAU0828(width=13)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 1184 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318276 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "YMSB9588(n_bits=72) INFO_REG pzdyqx.vhd(1251) " "VHDL info at pzdyqx.vhd(1251): executing entity \"YMSB9588(n_bits=72)\" with architecture \"INFO_REG\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/pzdyqx.vhd" 1251 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318277 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000000000001101110000000000000100010011000011011100000000000001000000010000110111000000000\",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(1,0)(1,96) rtl alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd(13) " "VHDL info at alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd(13): executing entity \"alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000000000001101110000000000000100010011000011011100000000000001000000010000110111000000000\",compilation_mode=0,force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(1,0)(1,96)\" with architecture \"rtl\"" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd" 13 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318278 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_jtag_hub(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000000000001101110000000000000100010011000011011100000000000001000000010000110111000000000\",force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(95,0) rtl sld_jtag_hub.vhd(89) " "VHDL info at sld_jtag_hub.vhd(89): executing entity \"sld_jtag_hub(device_family=\"Agilex 5\",n_node_ir_bits=5,node_info=\"000011000000000001101110000000000000100010011000011011100000000000001000000010000110111000000000\",force_pre_1_4_feature=0,negedge_tdo_latch=0)(1,8)(95,0)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_jtag_hub.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 89 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318279 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_shadow_jsm(ip_major_version=1,ip_minor_version=5) rtl sld_hub.vhd(1554) " "VHDL info at sld_hub.vhd(1554): executing entity \"sld_shadow_jsm(ip_major_version=1,ip_minor_version=5)\" with architecture \"rtl\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_hub.vhd" 1554 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318279 ""}
{ "Info" "IVRFX2_VHDL_ARCH_USED_FOR_ENTITY" "sld_rom_sr(n_bits=128) INFO_REG sld_rom_sr.vhd(5) " "VHDL info at sld_rom_sr.vhd(5): executing entity \"sld_rom_sr(n_bits=128)\" with architecture \"INFO_REG\"" {  } { { "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera_pro/25.3/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 0 0 0 } }  } 0 19337 "VHDL info at %3!s!: executing entity \"%1!s!\" with architecture \"%2!s!\"" 0 0 "Design Software" 0 -1 1768898318280 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "ir_in_2d\[3\]\[4\] alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd(283) " "Net \"ir_in_2d\[3\]\[4\]\" does not have a driver at alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd(283)" {  } { { "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd" "" { Text "D:/Downloads/b/SLVS_EC_RX_to_HDMI_IMX901_0120/dni/sandboxes/JOHNNY2_11752_0/sld/ipgen/alt_sld_fab_0/altera_sld_jtag_hub_1920/synth/alt_sld_fab_0_altera_sld_jtag_hub_1920_on6w5qi.vhd" 283 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 1 0 "Design Software" 0 -1 1768898318283 ""}
{ "Warning" "WDSLD_USE_OPENCORE_PLUS" "" "Intel FPGA IP Evaluation Mode feature is turned on for the following cores:" { { "Warning" "WDSLD_FOUND_OCP_CORE" "slec3_rx_top " "\"slec3_rx_top\" will use the Intel FPGA IP Evaluation Mode feature." {  } {  } 0 23196 "\"%1!s!\" will use the Intel FPGA IP Evaluation Mode feature." 0 0 "Design Software" 0 -1 1768898319734 ""}  } {  } 0 23195 "Intel FPGA IP Evaluation Mode feature is turned on for the following cores:" 0 0 "Design Software" 0 -1 1768898319734 ""}
{ "Warning" "WSCI_OPENCORE_USER_MSG_ROOT" "" "Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature" { { "Warning" "WSCI_OPENCORE_USER_MSG_CORE_ROOT" "slec3_rx_top " "Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature slec3_rx_top" { { "Warning" "WSCI_OPENCORE_USER_MSG_SUB" "This IP will have outputs tied to high when the hardware evaluation time expires. " "This IP will have outputs tied to high when the hardware evaluation time expires." {  } {  } 0 265074 "%1!s!" 0 0 "Design Software" 0 -1 1768898319734 ""}  } {  } 0 265073 "Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature %1!s!" 0 0 "Design Software" 0 -1 1768898319734 ""}  } {  } 0 265072 "Messages from megafunction that supports Intel FPGA IP Evaluation Mode feature" 0 0 "Design Software" 0 -1 1768898319734 ""}
{ "Warning" "WSCI_OPENCORE_HARD_TIMEOUT_INFO" "1 hour " "Megafunction that supports Intel FPGA IP Evaluation Mode feature will stop functioning in 1 hour after device is programmed" {  } {  } 0 265069 "Megafunction that supports Intel FPGA IP Evaluation Mode feature will stop functioning in %1!s! after device is programmed" 0 0 "Design Software" 0 -1 1768898319734 ""}
{ "Info" "0" "" "DA report generation in native DNI mode" {  } {  } 0 0 "DA report generation in native DNI mode" 0 0 "0" 0 0 1768898329961 ""}
{ "Info" "IDRC_START_RUN_DA_DRC" "partitioned " "Running Design Assistant Rules for snapshot 'partitioned'" {  } {  } 0 21615 "Running Design Assistant Rules for snapshot '%1!s!'" 0 0 "Design Software" 0 -1 17688