niosv_ss

2025.10.22.09:30:48 Datasheet
Overview
Processor
   niosv Abbotts Lake 26.0.0
All Components
   jtag_uart altera_avalon_jtag_uart 19.3.0
   niosv intel_niosv_m 26.0.0
   pio_0 altera_avalon_pio 19.2.4
   pio_1 altera_avalon_pio 19.2.4
   ram intel_onchip_memory 1.4.10
   slec_rx_csr slec_rx_csr 1.0
   spi altera_avalon_spi 19.2.6
Memory Map
niosv
 instruction_manager  data_manager
  jtag_uart
avalon_jtag_slave  0x0009_0180 - 0x0009_0187
  niosv
timer_sw_agent  0x0009_0100 - 0x0009_013f
dm_agent  0x0008_0000 - 0x0008_ffff 0x0008_0000 - 0x0008_ffff
  pio_0
s1  0x0009_0170 - 0x0009_017f
  pio_1
s1  0x0009_0160 - 0x0009_016f
  ram
s1  0x0000_0000 - 0x0007_ffff 0x0000_0000 - 0x0007_ffff
  slec_rx_csr
avsi_csr  0x0009_0000 - 0x0009_00ff
  spi
spi_control_port  0x0009_0140 - 0x0009_015f

clk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.3.0
niosv data_manager   jtag_uart
  avalon_jtag_slave
platform_irq_rx  
  irq
clk out_clk  
  clk
rst_n out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

niosv

intel_niosv_m v26.0.0
clk out_clk   niosv
  clk
rst_n out_reset  
  ndm_reset_in
out_reset  
  reset
data_manager   jtag_uart
  avalon_jtag_slave
platform_irq_rx  
  irq
data_manager   slec_rx_csr
  avsi_csr
data_manager   ram
  s1
instruction_manager  
  s1
data_manager   pio_0
  s1
data_manager   pio_1
  s1
data_manager   spi
  spi_control_port
platform_irq_rx  
  irq


Parameters

generateLegacySim false
  

Software Assignments

CPU_FREQ 50000000u
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 0
DCACHE_LINE_SIZE_LOG2 0
DCACHE_SIZE 0
HAS_CSR_SUPPORT 1
HAS_DEBUG_STUB
ICACHE_LINE_SIZE 0
ICACHE_LINE_SIZE_LOG2 0
ICACHE_SIZE 0
INST_ADDR_WIDTH 32
INT_MODE 0
MTIME_OFFSET 0x00090100
NIOSV_CORE_VARIANT 1
NUM_GPR 32
RESET_ADDR 0x00000000
TICKS_PER_SEC no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE 2

pio_0

altera_avalon_pio v19.2.4
niosv data_manager   pio_0
  s1
clk out_clk  
  clk
rst_n out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_1

altera_avalon_pio v19.2.4
niosv data_manager   pio_1
  s1
clk out_clk  
  clk
rst_n out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 32
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 50000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

ram

intel_onchip_memory v1.4.10
niosv data_manager   ram
  s1
instruction_manager  
  s1
clk out_clk  
  clk1
rst_n out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ram
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 1
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

rst_n

altera_reset_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

slec_rx_csr

slec_rx_csr v1.0
niosv data_manager   slec_rx_csr
  avsi_csr
clk out_clk  
  clk
rst_n out_reset  
  rst_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

spi

altera_avalon_spi v19.2.6
niosv data_manager   spi
  spi_control_port
platform_irq_rx  
  irq
clk out_clk  
  clk
rst_n out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

CLOCKMULT 1
CLOCKPHASE 1
CLOCKPOLARITY 1
CLOCKUNITS "Hz"
DATABITS 24
DATAWIDTH 32
DELAYMULT "1.0E-9"
DELAYUNITS "ns"
EXTRADELAY 1
INSERT_SYNC 0
ISMASTER 1
LSBFIRST 1
NUMSLAVES 1
PREFIX "spi_"
SYNC_REG_DEPTH 2
TARGETCLOCK 10000000u
TARGETSSDELAY "20.0"
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