spi_0
altera_avalon_spi v19.2.6
Parameters
| clockPhase |
1 |
| clockPolarity |
1 |
| dataWidth |
24 |
| insertDelayBetweenSlaveSelectAndSClk |
true |
| insertSync |
false |
| lsbOrderedFirst |
true |
| masterSPI |
true |
| numberOfSlaves |
1 |
| syncRegDepth |
2 |
| targetClockRate |
10000000 |
| targetSlaveSelectToSClkDelay |
20.0 |
| actualClockRate |
8333333.0 |
| actualSlaveSelectToSClkDelay |
60.0000024000001 |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |
|
Software Assignments
| CLOCKMULT |
1 |
| CLOCKPHASE |
1 |
| CLOCKPOLARITY |
1 |
| CLOCKUNITS |
"Hz" |
| DATABITS |
24 |
| DATAWIDTH |
32 |
| DELAYMULT |
"1.0E-9" |
| DELAYUNITS |
"ns" |
| EXTRADELAY |
1 |
| INSERT_SYNC |
0 |
| ISMASTER |
1 |
| LSBFIRST |
1 |
| NUMSLAVES |
1 |
| PREFIX |
"spi_" |
| SYNC_REG_DEPTH |
2 |
| TARGETCLOCK |
10000000u |
| TARGETSSDELAY |
"20.0" |
|