| axi_lite_clk_freq_user_p0_hwtcl |
250 |
| axi_st_clk_freq_user_p0_hwtcl |
300MHz |
| axi_lite_clk_freq_user_p1_hwtcl |
250 |
| axi_st_clk_freq_user_p1_hwtcl |
300MHz |
| DefaultMemory |
0 |
| pciess_bp_debug_en_hwtcl |
0 |
| pciess_perfmon_en_hwtcl |
0 |
| mif_devatt_port0_lower32b |
|
| mif_devatt_port0_upper32b |
|
| core16_ctrl_shadow_en_hwtcl |
1 |
| core16_comp_timeout_en_hwtcl |
1 |
| core16_ceb_en_hwtcl |
0 |
| core16_cii_en_hwtcl |
1 |
| core16_cii_pf_std_cap_last_ptr_hwtcl |
0 |
| core16_cii_vf_std_cap_last_ptr_hwtcl |
0 |
| core16_cii_ack_latency_hwtcl |
100 |
| core16_virtio_pci_cfg_acc_intf_en_hwtcl |
0 |
| core8_ctrl_shadow_en_hwtcl |
0 |
| core8_comp_timeout_en_hwtcl |
0 |
| core8_ceb_en_hwtcl |
0 |
| core8_cii_en_hwtcl |
0 |
| core8_virtio_pci_cfg_acc_intf_en_hwtcl |
0 |
| core16_device_att_en_hwtcl |
0 |
| core16_cpl_timeout_thru_axist_en_hwtcl |
0 |
| core16_cpl_reordering_en_hwtcl |
0 |
| core16_reorder_buff_size_hwtcl |
64 |
| core16_msi_msg_gen_en_hwtcl |
0 |
| core8_device_att_en_hwtcl |
0 |
| core8_cpl_timeout_thru_axist_en_hwtcl |
0 |
| core8_cpl_reordering_en_hwtcl |
0 |
| core8_reorder_buff_size_hwtcl |
64 |
| core8_msi_msg_gen_en_hwtcl |
0 |
| core16_dfl_en_hwtcl |
0 |
| core16_dfh_fid_hwtcl |
0 |
| core16_dfh_major_ver_hwtcl |
0 |
| core16_dfh_next_byte_offset_hwtcl |
0 |
| core16_dfh_end_hwtcl |
0 |
| core16_dfh_minor_rev_hwtcl |
0 |
| core16_dfh_ver_hwtcl |
0 |
| core16_dfh_feature_type_hwtcl |
0 |
| core16_inst_id_hwtcl |
0 |
| core8_dfl_en_hwtcl |
0 |
| core8_dfh_fid_hwtcl |
0 |
| core8_dfh_major_ver_hwtcl |
0 |
| core8_dfh_next_byte_offset_hwtcl |
0 |
| core8_dfh_end_hwtcl |
0 |
| core8_dfh_minor_rev_hwtcl |
0 |
| core8_dfh_ver_hwtcl |
0 |
| core8_dfh_feature_type_hwtcl |
0 |
| core8_inst_id_hwtcl |
0 |
| core16_hip_native_mode_user_hwtcl |
1 |
| core8_hip_native_mode_user_hwtcl |
1 |
| core16_ST_readyLatency_hwtcl |
0 |
| core16_Header_Packing_scheme_hwtcl |
Simple |
| core16_segment_size_hwtcl |
16 |
| core16_sbh_en_hwtcl |
1 |
| core16_LiteSlvDWD_byte_hwtcl |
4 |
| core8_ST_readyLatency_hwtcl |
0 |
| core8_Header_Packing_scheme_hwtcl |
Simple |
| core8_segment_size_hwtcl |
16 |
| core8_sbh_en_hwtcl |
1 |
| core8_LiteSlvDWD_byte_hwtcl |
4 |
| top_topology_hwtcl |
Gen4 x4 Interface 256 bit |
| virtual_tlp_bypass_en_user_hwtcl |
0 |
| virtual_rp_ep_mode_hwtcl |
Native Endpoint |
| debug_toolkit_hwtcl |
0 |
| g4_pld_clkfreq_user_hwtcl |
300MHz |
| virtual_sris_enable_en_hwtcl |
0 |
| pipemode_sim_hwtcl |
0 |
| enable_example_design_sim_hwtcl |
0 |
| enable_example_design_synth_hwtcl |
1 |
| select_design_example_rtl_lang_hwtcl |
Verilog |
| chosen_devkit_hwtcl |
NONE |
| example_design_mode_hwtcl |
PIO/SRIOV |
| pipemode_sim_for_ed_hwtcl |
1 |
| core16_pf0_gen3_eq_pset_req_vec_user_hwtcl |
292 |
| core16_pf0_gen3_eq_pset_req_vec_atg4_user_hwtcl |
352 |
| core16_virtual_maxpayload_size_hwtcl |
512 |
| core16_pcie_cvp_attr_hwtcl |
0 |
| core16_cii_monitor_en_hwtcl |
0 |
| core16_enable_error_intf_hwtcl |
0 |
| core8_pf0_gen3_eq_pset_req_vec_user_hwtcl |
292 |
| core8_virtual_maxpayload_size_hwtcl |
512 |
| core8_enable_error_intf_hwtcl |
0 |
| core16_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| core16_pf0_bar0_address_width_user_hwtcl |
22 |
| core16_pf0_bar1_type_user_hwtcl |
Disabled |
| core16_pf0_bar2_type_user_hwtcl |
64-bit prefetchable memory |
| core16_pf0_bar2_address_width_user_hwtcl |
24 |
| core16_pf0_bar3_type_user_hwtcl |
Disabled |
| core16_pf0_bar4_type_user_hwtcl |
Disabled |
| core16_pf0_bar5_type_user_hwtcl |
Disabled |
| core16_pf0_expansion_base_address_register_hwtcl |
0 |
| core8_pf0_bar0_type_user_hwtcl |
64-bit prefetchable memory |
| core8_pf0_bar1_type_user_hwtcl |
Disabled |
| core8_pf0_bar2_type_user_hwtcl |
Disabled |
| core8_pf0_bar3_type_user_hwtcl |
Disabled |
| core8_pf0_bar4_type_user_hwtcl |
Disabled |
| core8_pf0_bar5_type_user_hwtcl |
Disabled |
| core8_pf0_expansion_base_address_register_hwtcl |
0 |
| core16_enable_multi_func_hwtcl |
0 |
| core16_enable_sriov_hwtcl |
0 |
| core8_enable_multi_func_hwtcl |
0 |
| core8_enable_sriov_hwtcl |
0 |
| core16_cap_port_num_hwtcl |
1 |
| core16_cap_slot_clk_config_hwtcl |
1 |
| core16_virtual_pf0_msi_enable_user_hwtcl |
0 |
| core16_virtual_pf1_msi_enable_user_hwtcl |
0 |
| core16_virtual_pf2_msi_enable_user_hwtcl |
0 |
| core16_virtual_pf3_msi_enable_user_hwtcl |
0 |
| core16_virtual_pf0_msix_enable_user_hwtcl |
1 |
| core16_virtual_pf1_msix_enable_user_hwtcl |
0 |
| core16_virtual_pf2_msix_enable_user_hwtcl |
0 |
| core16_virtual_pf3_msix_enable_user_hwtcl |
0 |
| core16_pf0_pci_msix_table_size_hwtcl |
15 |
| core16_pf1_pci_msix_table_size_hwtcl |
0 |
| core16_pf2_pci_msix_table_size_hwtcl |
0 |
| core16_pf3_pci_msix_table_size_hwtcl |
0 |
| core16_pf0_pci_msix_table_offset_hwtcl |
131072 |
| core16_pf1_pci_msix_table_offset_hwtcl |
0 |
| core16_pf2_pci_msix_table_offset_hwtcl |
0 |
| core16_pf3_pci_msix_table_offset_hwtcl |
0 |
| core16_pf0_pci_msix_bir_hwtcl |
0 |
| core16_pf1_pci_msix_bir_hwtcl |
0 |
| core16_pf2_pci_msix_bir_hwtcl |
0 |
| core16_pf3_pci_msix_bir_hwtcl |
0 |
| core16_pf0_pci_msix_pba_hwtcl |
0 |
| core16_pf1_pci_msix_pba_hwtcl |
0 |
| core16_pf2_pci_msix_pba_hwtcl |
0 |
| core16_pf3_pci_msix_pba_hwtcl |
0 |
| core16_pf0_pci_msix_pba_offset_hwtcl |
196608 |
| core16_pf1_pci_msix_pba_offset_hwtcl |
0 |
| core16_pf2_pci_msix_pba_offset_hwtcl |
0 |
| core16_pf3_pci_msix_pba_offset_hwtcl |
0 |
| core16_virtual_pf0_exvf_msix_cap_enable_hwtcl |
0 |
| core16_virtual_pf1_exvf_msix_cap_enable_hwtcl |
0 |
| core16_virtual_pf2_exvf_msix_cap_enable_hwtcl |
0 |
| core16_virtual_pf3_exvf_msix_cap_enable_hwtcl |
0 |
| core16_exvf_msix_tablesize_pf0 |
0 |
| core16_exvf_msix_tablesize_pf1 |
0 |
| core16_exvf_msix_tablesize_pf2 |
0 |
| core16_exvf_msix_tablesize_pf3 |
0 |
| core16_exvf_msixtable_offset_pf0 |
0 |
| core16_exvf_msixtable_offset_pf1 |
0 |
| core16_exvf_msixtable_offset_pf2 |
0 |
| core16_exvf_msixtable_offset_pf3 |
0 |
| core16_exvf_msixtable_bir_pf0 |
0 |
| core16_exvf_msixtable_bir_pf1 |
0 |
| core16_exvf_msixtable_bir_pf2 |
0 |
| core16_exvf_msixtable_bir_pf3 |
0 |
| core16_exvf_msixpba_offset_pf0 |
0 |
| core16_exvf_msixpba_offset_pf1 |
0 |
| core16_exvf_msixpba_offset_pf2 |
0 |
| core16_exvf_msixpba_offset_pf3 |
0 |
| core16_exvf_msixpba_bir_pf0 |
0 |
| core16_exvf_msixpba_bir_pf1 |
0 |
| core16_exvf_msixpba_bir_pf2 |
0 |
| core16_exvf_msixpba_bir_pf3 |
0 |
| core16_pf0_pcie_slot_imp_hwtcl |
0 |
| core16_pf0_pcie_cap_slot_power_limit_scale_hwtcl |
0 |
| core16_pf0_pcie_cap_slot_power_limit_value_hwtcl |
0 |
| core16_pf0_pcie_cap_phy_slot_num_hwtcl |
0 |
| core16_user_pcie_cap_ep_l0s_accpt_latency_hwtcl |
0 |
| core16_user_pcie_cap_ep_l1_accpt_latency_hwtcl |
0 |
| core16_user_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl |
7 |
| core16_user_pcie_cap_l1_exit_latency_commclk_dis_hwtcl |
7 |
| core16_virtual_aspm_support_hwtcl |
L0s and L1 |
| core16_virtual_pf0_prs_ext_cap_enable_hwtcl |
0 |
| core16_virtual_pf1_prs_ext_cap_enable_hwtcl |
0 |
| core16_virtual_pf2_prs_ext_cap_enable_hwtcl |
0 |
| core16_virtual_pf3_prs_ext_cap_enable_hwtcl |
0 |
| core16_virtual_dbi_ro_wr_disable_hwtcl |
0 |
| core16_virtual_sn_cap_enable_hwtcl |
0 |
| core16_sn_ser_num_reg_1_dw_hwtcl |
0 |
| core16_sn_ser_num_reg_2_dw_hwtcl |
0 |
| core16_virtual_pf0_pasid_cap_enable_hwtcl |
0 |
| core16_virtual_pf1_pasid_cap_enable_hwtcl |
0 |
| core16_virtual_pf2_pasid_cap_enable_hwtcl |
0 |
| core16_virtual_pf3_pasid_cap_enable_hwtcl |
0 |
| core16_virtual_pf0_ltr_cap_enable_hwtcl |
0 |
| core16_virtual_ptm_hwtcl |
0 |
| core16_cfg_ptm_auto_update_period_hwtcl |
Disable |
| core8_cap_port_num_hwtcl |
1 |
| core8_cap_slot_clk_config_hwtcl |
1 |
| core8_virtual_pf0_msi_enable_user_hwtcl |
0 |
| core8_virtual_pf1_msi_enable_user_hwtcl |
0 |
| core8_virtual_pf2_msi_enable_user_hwtcl |
0 |
| core8_virtual_pf3_msi_enable_user_hwtcl |
0 |
| core8_virtual_pf0_msix_enable_user_hwtcl |
0 |
| core8_virtual_pf1_msix_enable_user_hwtcl |
0 |
| core8_virtual_pf2_msix_enable_user_hwtcl |
0 |
| core8_virtual_pf3_msix_enable_user_hwtcl |
0 |
| core8_pf0_pci_msix_table_size_hwtcl |
0 |
| core8_pf1_pci_msix_table_size_hwtcl |
0 |
| core8_pf2_pci_msix_table_size_hwtcl |
0 |
| core8_pf3_pci_msix_table_size_hwtcl |
0 |
| core8_pf0_pci_msix_table_offset_hwtcl |
0 |
| core8_pf1_pci_msix_table_offset_hwtcl |
0 |
| core8_pf2_pci_msix_table_offset_hwtcl |
0 |
| core8_pf3_pci_msix_table_offset_hwtcl |
0 |
| core8_pf0_pci_msix_bir_hwtcl |
0 |
| core8_pf1_pci_msix_bir_hwtcl |
0 |
| core8_pf2_pci_msix_bir_hwtcl |
0 |
| core8_pf3_pci_msix_bir_hwtcl |
0 |
| core8_pf0_pci_msix_pba_hwtcl |
0 |
| core8_pf1_pci_msix_pba_hwtcl |
0 |
| core8_pf2_pci_msix_pba_hwtcl |
0 |
| core8_pf3_pci_msix_pba_hwtcl |
0 |
| core8_pf0_pci_msix_pba_offset_hwtcl |
0 |
| core8_pf1_pci_msix_pba_offset_hwtcl |
0 |
| core8_pf2_pci_msix_pba_offset_hwtcl |
0 |
| core8_pf3_pci_msix_pba_offset_hwtcl |
0 |
| core8_virtual_pf0_exvf_msix_cap_enable_hwtcl |
0 |
| core8_virtual_pf1_exvf_msix_cap_enable_hwtcl |
0 |
| core8_virtual_pf2_exvf_msix_cap_enable_hwtcl |
0 |
| core8_virtual_pf3_exvf_msix_cap_enable_hwtcl |
0 |
| core8_exvf_msix_tablesize_pf0 |
0 |
| core8_exvf_msix_tablesize_pf1 |
0 |
| core8_exvf_msix_tablesize_pf2 |
0 |
| core8_exvf_msix_tablesize_pf3 |
0 |
| core8_exvf_msixtable_offset_pf0 |
0 |
| core8_exvf_msixtable_offset_pf1 |
0 |
| core8_exvf_msixtable_offset_pf2 |
0 |
| core8_exvf_msixtable_offset_pf3 |
0 |
| core8_exvf_msixtable_bir_pf0 |
0 |
| core8_exvf_msixtable_bir_pf1 |
0 |
| core8_exvf_msixtable_bir_pf2 |
0 |
| core8_exvf_msixtable_bir_pf3 |
0 |
| core8_exvf_msixpba_offset_pf0 |
0 |
| core8_exvf_msixpba_offset_pf1 |
0 |
| core8_exvf_msixpba_offset_pf2 |
0 |
| core8_exvf_msixpba_offset_pf3 |
0 |
| core8_exvf_msixpba_bir_pf0 |
0 |
| core8_exvf_msixpba_bir_pf1 |
0 |
| core8_exvf_msixpba_bir_pf2 |
0 |
| core8_exvf_msixpba_bir_pf3 |
0 |
| core8_pf0_pcie_slot_imp_hwtcl |
0 |
| core8_pf0_pcie_cap_slot_power_limit_scale_hwtcl |
0 |
| core8_pf0_pcie_cap_slot_power_limit_value_hwtcl |
0 |
| core8_pf0_pcie_cap_phy_slot_num_hwtcl |
0 |
| core8_user_pcie_cap_ep_l0s_accpt_latency_hwtcl |
0 |
| core8_user_pcie_cap_ep_l1_accpt_latency_hwtcl |
0 |
| core8_user_pcie_cap_l0s_exit_latency_commclk_dis_hwtcl |
7 |
| core8_user_pcie_cap_l1_exit_latency_commclk_dis_hwtcl |
7 |
| core8_virtual_aspm_support_hwtcl |
L0s and L1 |
| core8_virtual_pf0_prs_ext_cap_enable_hwtcl |
0 |
| core8_virtual_pf1_prs_ext_cap_enable_hwtcl |
0 |
| core8_virtual_pf2_prs_ext_cap_enable_hwtcl |
0 |
| core8_virtual_pf3_prs_ext_cap_enable_hwtcl |
0 |
| core8_virtual_dbi_ro_wr_disable_hwtcl |
0 |
| core8_virtual_sn_cap_enable_hwtcl |
0 |
| core8_sn_ser_num_reg_1_dw_hwtcl |
0 |
| core8_sn_ser_num_reg_2_dw_hwtcl |
0 |
| core8_virtual_pf0_pasid_cap_enable_hwtcl |
0 |
| core8_virtual_pf1_pasid_cap_enable_hwtcl |
0 |
| core8_virtual_pf2_pasid_cap_enable_hwtcl |
0 |
| core8_virtual_pf3_pasid_cap_enable_hwtcl |
0 |
| core8_virtual_pf0_ltr_cap_enable_hwtcl |
0 |
| core8_virtual_ptm_hwtcl |
0 |
| core8_cfg_ptm_auto_update_period_hwtcl |
Disable |
| core16_pf0_pci_type0_vendor_id_hwtcl |
4466 |
| core16_pf0_pci_type0_device_id_hwtcl |
2500 |
| core16_pf0_revision_id_hwtcl |
1 |
| core16_pf0_class_code_hwtcl |
16711680 |
| core16_pf0_subsys_vendor_id_hwtcl |
0 |
| core16_pf0_subsys_dev_id_hwtcl |
0 |
| core16_pf0_sriov_vf_device_id |
0 |
| core16_exvf_subsysid_pf0 |
0 |
| core16_pf1_pci_type0_vendor_id_hwtcl |
0 |
| core16_pf1_pci_type0_device_id_hwtcl |
0 |
| core16_pf1_revision_id_hwtcl |
0 |
| core16_pf1_class_code_hwtcl |
16711680 |
| core16_pf1_subsys_vendor_id_hwtcl |
0 |
| core16_pf1_subsys_dev_id_hwtcl |
0 |
| core16_pf1_sriov_vf_device_id |
0 |
| core16_exvf_subsysid_pf1 |
0 |
| core16_pf2_pci_type0_vendor_id_hwtcl |
0 |
| core16_pf2_pci_type0_device_id_hwtcl |
0 |
| core16_pf2_revision_id_hwtcl |
0 |
| core16_pf2_class_code_hwtcl |
16711680 |
| core16_pf2_subsys_vendor_id_hwtcl |
0 |
| core16_pf2_subsys_dev_id_hwtcl |
0 |
| core16_pf2_sriov_vf_device_id |
0 |
| core16_exvf_subsysid_pf2 |
0 |
| core16_pf3_pci_type0_vendor_id_hwtcl |
0 |
| core16_pf3_pci_type0_device_id_hwtcl |
0 |
| core16_pf3_revision_id_hwtcl |
0 |
| core16_pf3_class_code_hwtcl |
16711680 |
| core16_pf3_subsys_vendor_id_hwtcl |
0 |
| core16_pf3_subsys_dev_id_hwtcl |
0 |
| core16_pf3_sriov_vf_device_id |
0 |
| core16_exvf_subsysid_pf3 |
0 |
| core8_pf0_pci_type0_vendor_id_hwtcl |
0 |
| core8_pf0_pci_type0_device_id_hwtcl |
0 |
| core8_pf0_revision_id_hwtcl |
0 |
| core8_pf0_class_code_hwtcl |
16711680 |
| core8_pf0_subsys_vendor_id_hwtcl |
0 |
| core8_pf0_subsys_dev_id_hwtcl |
0 |
| core8_pf0_sriov_vf_device_id |
0 |
| core8_exvf_subsysid_pf0 |
0 |
| core8_pf1_pci_type0_vendor_id_hwtcl |
0 |
| core8_pf1_pci_type0_device_id_hwtcl |
0 |
| core8_pf1_revision_id_hwtcl |
0 |
| core8_pf1_class_code_hwtcl |
16711680 |
| core8_pf1_subsys_vendor_id_hwtcl |
0 |
| core8_pf1_subsys_dev_id_hwtcl |
0 |
| core8_pf1_sriov_vf_device_id |
0 |
| core8_exvf_subsysid_pf1 |
0 |
| core8_pf2_pci_type0_vendor_id_hwtcl |
0 |
| core8_pf2_pci_type0_device_id_hwtcl |
0 |
| core8_pf2_revision_id_hwtcl |
0 |
| core8_pf2_class_code_hwtcl |
16711680 |
| core8_pf2_subsys_vendor_id_hwtcl |
0 |
| core8_pf2_subsys_dev_id_hwtcl |
0 |
| core8_pf2_sriov_vf_device_id |
0 |
| core8_exvf_subsysid_pf2 |
0 |
| core8_pf3_pci_type0_vendor_id_hwtcl |
0 |
| core8_pf3_pci_type0_device_id_hwtcl |
0 |
| core8_pf3_revision_id_hwtcl |
0 |
| core8_pf3_class_code_hwtcl |
16711680 |
| core8_pf3_subsys_vendor_id_hwtcl |
0 |
| core8_pf3_subsys_dev_id_hwtcl |
0 |
| core8_pf3_sriov_vf_device_id |
0 |
| core8_exvf_subsysid_pf3 |
0 |
| core16_user_vsec_cap_enable_hwtcl |
0 |
| core16_cvp_user_id_hwtcl |
0 |
| core16_virtual_drop_vendor0_msg_hwtcl |
0 |
| core16_virtual_drop_vendor1_msg_hwtcl |
0 |
| core8_user_vsec_cap_enable_hwtcl |
0 |
| core8_cvp_user_id_hwtcl |
0 |
| core8_virtual_drop_vendor0_msg_hwtcl |
0 |
| core8_virtual_drop_vendor1_msg_hwtcl |
0 |
| core16_virtual_pf0_ats_cap_enable_hwtcl |
0 |
| core16_virtual_pf1_ats_cap_enable_hwtcl |
0 |
| core16_virtual_pf2_ats_cap_enable_hwtcl |
0 |
| core16_virtual_pf3_ats_cap_enable_hwtcl |
0 |
| core16_pf0_vf_ats_cap_enable_hwtcl |
0 |
| core16_pf1_vf_ats_cap_enable_hwtcl |
0 |
| core16_pf2_vf_ats_cap_enable_hwtcl |
0 |
| core16_pf3_vf_ats_cap_enable_hwtcl |
0 |
| core16_virtual_pf0_tph_cap_enable_hwtcl |
0 |
| core16_pf0_vf_tph_cap_enable_hwtcl |
0 |
| core16_virtual_pf1_tph_cap_enable_hwtcl |
0 |
| core16_pf1_vf_tph_cap_enable_hwtcl |
0 |
| core16_virtual_pf2_tph_cap_enable_hwtcl |
0 |
| core16_pf2_vf_tph_cap_enable_hwtcl |
0 |
| core16_virtual_pf3_tph_cap_enable_hwtcl |
0 |
| core16_pf3_vf_tph_cap_enable_hwtcl |
0 |
| core16_virtual_pf0_acs_cap_enable_hwtcl |
0 |
| core16_pf0_vf_acs_cap_enable_hwtcl |
0 |
| core16_virtual_pf1_acs_cap_enable_hwtcl |
0 |
| core16_pf1_vf_acs_cap_enable_hwtcl |
0 |
| core16_virtual_pf2_acs_cap_enable_hwtcl |
0 |
| core16_pf2_vf_acs_cap_enable_hwtcl |
0 |
| core16_virtual_pf3_acs_cap_enable_hwtcl |
0 |
| core16_pf3_vf_acs_cap_enable_hwtcl |
0 |
| core8_virtual_pf0_ats_cap_enable_hwtcl |
0 |
| core8_virtual_pf1_ats_cap_enable_hwtcl |
0 |
| core8_virtual_pf2_ats_cap_enable_hwtcl |
0 |
| core8_virtual_pf3_ats_cap_enable_hwtcl |
0 |
| core8_pf0_vf_ats_cap_enable_hwtcl |
0 |
| core8_pf1_vf_ats_cap_enable_hwtcl |
0 |
| core8_pf2_vf_ats_cap_enable_hwtcl |
0 |
| core8_pf3_vf_ats_cap_enable_hwtcl |
0 |
| core8_virtual_pf0_tph_cap_enable_hwtcl |
0 |
| core8_pf0_vf_tph_cap_enable_hwtcl |
0 |
| core8_virtual_pf1_tph_cap_enable_hwtcl |
0 |
| core8_pf1_vf_tph_cap_enable_hwtcl |
0 |
| core8_virtual_pf2_tph_cap_enable_hwtcl |
0 |
| core8_pf2_vf_tph_cap_enable_hwtcl |
0 |
| core8_virtual_pf3_tph_cap_enable_hwtcl |
0 |
| core8_pf3_vf_tph_cap_enable_hwtcl |
0 |
| core8_virtual_pf0_acs_cap_enable_hwtcl |
0 |
| core8_pf0_vf_acs_cap_enable_hwtcl |
0 |
| core8_virtual_pf1_acs_cap_enable_hwtcl |
0 |
| core8_pf1_vf_acs_cap_enable_hwtcl |
0 |
| core8_virtual_pf2_acs_cap_enable_hwtcl |
0 |
| core8_pf2_vf_acs_cap_enable_hwtcl |
0 |
| core8_virtual_pf3_acs_cap_enable_hwtcl |
0 |
| core8_pf3_vf_acs_cap_enable_hwtcl |
0 |
| core16_virtual_num_of_lanes_4_hwtcl |
4 |
| core16_pf0_int_pin_hwtcl |
NO INT |
| core8_pf0_int_pin_hwtcl |
NO INT |
| core16_enable_virtio_hwtcl |
0 |
| core16_pf0_virtio_capability_present_hwtcl |
0 |
| core16_pf0_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf0_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf0_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf0_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf0_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf0_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf0_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf1_virtio_capability_present_hwtcl |
0 |
| core16_pf1_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf1_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf1_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf1_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf1_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf1_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf1_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf1_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf1_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf1_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf1_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf1_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf1_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf1_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf1_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf1_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf1_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf2_virtio_capability_present_hwtcl |
0 |
| core16_pf2_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf2_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf2_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf2_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf2_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf2_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf2_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf2_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf2_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf2_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf2_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf2_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf2_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf2_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf2_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf2_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf2_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf3_virtio_capability_present_hwtcl |
0 |
| core16_pf3_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf3_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf3_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf3_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf3_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf3_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf3_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf3_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf3_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf3_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf3_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf3_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf3_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf3_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf3_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf3_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf3_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_capability_present_hwtcl |
0 |
| core16_pf0vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf0vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf0vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf0vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_capability_present_hwtcl |
0 |
| core16_pf1vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf1vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf1vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf1vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_capability_present_hwtcl |
0 |
| core16_pf2vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf2vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf2vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf2vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_capability_present_hwtcl |
0 |
| core16_pf3vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core16_pf3vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_notification_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_notification_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core16_pf3vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core16_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core16_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core16_pf3vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_enable_virtio_hwtcl |
0 |
| core8_pf0_virtio_capability_present_hwtcl |
0 |
| core8_pf0_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf0_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf0_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf0_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf0_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf0_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf0_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf0_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf0_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf0_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf0_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf0_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf0_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf0_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf0_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf0_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf0_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf1_virtio_capability_present_hwtcl |
0 |
| core8_pf1_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf1_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf1_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf1_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf1_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf1_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf1_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf1_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf1_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf1_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf1_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf1_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf1_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf1_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf1_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf1_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf1_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf2_virtio_capability_present_hwtcl |
0 |
| core8_pf2_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf2_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf2_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf2_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf2_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf2_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf2_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf2_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf2_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf2_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf2_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf2_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf2_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf2_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf2_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf2_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf2_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf3_virtio_capability_present_hwtcl |
0 |
| core8_pf3_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf3_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf3_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf3_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf3_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf3_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf3_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf3_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf3_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf3_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf3_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf3_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf3_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf3_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf3_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf3_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf3_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf0vf_virtio_capability_present_hwtcl |
0 |
| core8_pf0vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf0vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf0vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf0vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf0vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf0vf_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf0vf_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf0vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf0vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf0vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf0vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf0vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf0vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf0vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf0vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf0vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf0vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf1vf_virtio_capability_present_hwtcl |
0 |
| core8_pf1vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf1vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf1vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf1vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf1vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf1vf_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf1vf_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf1vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf1vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf1vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf1vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf1vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf1vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf1vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf1vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf1vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf1vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf2vf_virtio_capability_present_hwtcl |
0 |
| core8_pf2vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf2vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf2vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf2vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf2vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf2vf_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf2vf_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf2vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf2vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf2vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf2vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf2vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf2vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf2vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf2vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf2vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf2vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| core8_pf3vf_virtio_capability_present_hwtcl |
0 |
| core8_pf3vf_virtio_device_specific_cap_present_hwtcl |
0 |
| core8_pf3vf_virtio_cmn_config_bar_indicator_hwtcl |
0 |
| core8_pf3vf_virtio_cmn_config_bar_offset_hwtcl |
0 |
| core8_pf3vf_virtio_cmn_config_structure_length_hwtcl |
0 |
| core8_pf3vf_virtio_notification_bar_indicator_hwtcl |
0 |
| core8_pf3vf_virtio_notification_bar_offset_hwtcl |
0 |
| core8_pf3vf_virtio_notification_structure_length_hwtcl |
0 |
| core8_pf3vf_virtio_notify_off_multiplier_hwtcl |
0 |
| core8_pf3vf_virtio_isrstatus_bar_indicator_hwtcl |
0 |
| core8_pf3vf_virtio_isrstatus_bar_offset_hwtcl |
0 |
| core8_pf3vf_virtio_isrstatus_structure_length_hwtcl |
0 |
| core8_pf3vf_virtio_devspecific_bar_indicator_hwtcl |
0 |
| core8_pf3vf_virtio_devspecific_bar_offset_hwtcl |
0 |
| core8_pf3vf_virtio_devspecific_structure_length_hwtcl |
0 |
| core8_pf3vf_virtio_pciconfig_access_bar_indicator_hwtcl |
0 |
| core8_pf3vf_virtio_pciconfig_access_bar_offset_hwtcl |
0 |
| core8_pf3vf_virtio_pciconfig_access_structure_length_hwtcl |
0 |
| ch0_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch1_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch2_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch3_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch0_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch1_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch2_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ch3_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN4 |
| ipfluxtop_uxtop_wrap_ch0_rx_invert_pin_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch1_rx_invert_pin_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch2_rx_invert_pin_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch3_rx_invert_pin_hwtcl |
DISABLE |
| dr_enabled_hwtcl |
DR_DISABLED |
| ch0_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| ch1_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| ch2_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| ch3_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| ipfluxtop_uxtop_wrap_ch0_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch1_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch2_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch3_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch0_rx_postdiv_clk_en_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch1_rx_postdiv_clk_en_hwtcl |
ENABLE |
| ipfluxtop_uxtop_wrap_ch2_rx_postdiv_clk_en_hwtcl |
ENABLE |
| ipfluxtop_uxtop_wrap_ch3_rx_postdiv_clk_en_hwtcl |
ENABLE |
| ipfluxtop_uxtop_wrap_ch0_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch1_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch2_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch3_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| ipfluxtop_uxtop_wrap_ch0_xcvr_rx_force_cdr_ltr_hwtcl |
TRUE |
| ipfluxtop_uxtop_wrap_ch1_xcvr_rx_force_cdr_ltr_hwtcl |
TRUE |
| ipfluxtop_uxtop_wrap_ch2_xcvr_rx_force_cdr_ltr_hwtcl |
FALSE |
| ipfluxtop_uxtop_wrap_ch3_xcvr_rx_force_cdr_ltr_hwtcl |
FALSE |
| ch0_tx_pll_f_out_hz_hwtcl |
0 |
| ch1_tx_pll_f_out_hz_hwtcl |
0 |
| ch2_tx_pll_f_out_hz_hwtcl |
0 |
| ch3_tx_pll_f_out_hz_hwtcl |
0 |
| ch0_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch1_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch2_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch3_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch0_phy_loopback_mode_hwtcl |
DISABLED |
| ch1_phy_loopback_mode_hwtcl |
DISABLED |
| ch2_phy_loopback_mode_hwtcl |
DISABLED |
| ch3_phy_loopback_mode_hwtcl |
DISABLED |
| ch0_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| ch1_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| ch2_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| ch3_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| ch0_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| ch1_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| ch2_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| ch3_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| ch0_tx_pll_f_ref_hz_hwtcl |
100000000 |
| ch1_tx_pll_f_ref_hz_hwtcl |
100000000 |
| ch2_tx_pll_f_ref_hz_hwtcl |
100000000 |
| ch3_tx_pll_f_ref_hz_hwtcl |
100000000 |
| ch0_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| ch1_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| ch2_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| ch3_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| ch0_xcvr_rx_datarate_bps_hwtcl |
16000 |
| ch1_xcvr_rx_datarate_bps_hwtcl |
16000 |
| ch2_xcvr_rx_datarate_bps_hwtcl |
16000 |
| ch3_xcvr_rx_datarate_bps_hwtcl |
16000 |
| ch0_xcvr_tx_datarate_bps_hwtcl |
16000 |
| ch1_xcvr_tx_datarate_bps_hwtcl |
16000 |
| ch2_xcvr_tx_datarate_bps_hwtcl |
16000 |
| ch3_xcvr_tx_datarate_bps_hwtcl |
16000 |
| ch0_rx_postdiv_clk_divider_hwtcl |
12 |
| ch1_rx_postdiv_clk_divider_hwtcl |
12 |
| ch2_rx_postdiv_clk_divider_hwtcl |
12 |
| ch3_rx_postdiv_clk_divider_hwtcl |
12 |
| ch0_tx_postdiv_clk_divider_hwtcl |
52 |
| ch1_tx_postdiv_clk_divider_hwtcl |
137 |
| ch2_tx_postdiv_clk_divider_hwtcl |
73 |
| ch3_tx_postdiv_clk_divider_hwtcl |
4 |
| ch0_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| ch1_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| ch2_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| ch3_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| ch0_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| ch1_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| ch2_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| ch3_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| ch0_xcvr_rx_width_hwtcl |
16 |
| ch1_xcvr_rx_width_hwtcl |
16 |
| ch2_xcvr_rx_width_hwtcl |
16 |
| ch3_xcvr_rx_width_hwtcl |
16 |
| ch0_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch1_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch2_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch3_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| ch0_tx_invert_pin_hwtcl |
DISABLE |
| ch1_tx_invert_pin_hwtcl |
DISABLE |
| ch2_tx_invert_pin_hwtcl |
DISABLE |
| ch3_tx_invert_pin_hwtcl |
DISABLE |
| ch0_sim_mode_hwtcl |
DISABLE |
| ch1_sim_mode_hwtcl |
DISABLE |
| ch2_sim_mode_hwtcl |
DISABLE |
| ch3_sim_mode_hwtcl |
DISABLE |
| ch_dpma_f_ref_hz |
250000000 |
| core8_ch0_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch1_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch2_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch3_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch4_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch5_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch6_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch7_xcvr_rx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch0_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch1_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch2_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch3_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch4_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch5_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch6_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ch7_xcvr_tx_protocol_hint_user_hwtcl |
PCIE_GEN3 |
| core8_ipfluxtop_uxtop_wrap_ch0_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch1_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch2_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch3_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch4_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch5_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch6_rx_invert_pin_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch7_rx_invert_pin_hwtcl |
DISABLE |
| core8_dr_enabled_hwtcl |
DR_DISABLED |
| core8_ch0_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch1_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch2_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch3_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch4_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch5_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch6_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ch7_flux_mode_hwtcl |
FLUX_MODE_BYPASS |
| core8_ipfluxtop_uxtop_wrap_ch0_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch1_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch2_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch3_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch4_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch5_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch6_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch7_xcvr_rx_cdrdivout_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch0_rx_postdiv_clk_en_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch1_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch2_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch3_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch4_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch5_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch6_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch7_rx_postdiv_clk_en_hwtcl |
ENABLE |
| core8_ipfluxtop_uxtop_wrap_ch0_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch1_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch2_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch3_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch4_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch5_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch6_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch7_xcvr_tx_user_clk_only_mode_hwtcl |
DISABLE |
| core8_ipfluxtop_uxtop_wrap_ch0_xcvr_rx_force_cdr_ltr_hwtcl |
TRUE |
| core8_ipfluxtop_uxtop_wrap_ch1_xcvr_rx_force_cdr_ltr_hwtcl |
TRUE |
| core8_ipfluxtop_uxtop_wrap_ch2_xcvr_rx_force_cdr_ltr_hwtcl |
FALSE |
| core8_ipfluxtop_uxtop_wrap_ch3_xcvr_rx_force_cdr_ltr_hwtcl |
FALSE |
| core8_ipfluxtop_uxtop_wrap_ch4_xcvr_rx_force_cdr_ltr_hwtcl |
TRUE |
| core8_ipfluxtop_uxtop_wrap_ch5_xcvr_rx_force_cdr_ltr_hwtcl |
TRUE |
| core8_ipfluxtop_uxtop_wrap_ch6_xcvr_rx_force_cdr_ltr_hwtcl |
FALSE |
| core8_ipfluxtop_uxtop_wrap_ch7_xcvr_rx_force_cdr_ltr_hwtcl |
FALSE |
| core8_ch0_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch1_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch2_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch3_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch4_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch5_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch6_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch7_tx_pll_f_out_hz_hwtcl |
0 |
| core8_ch0_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch1_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch2_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch3_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch4_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch5_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch6_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch7_cdr_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch0_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch1_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch2_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch3_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch4_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch5_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch6_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch7_phy_loopback_mode_hwtcl |
DISABLED |
| core8_ch0_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch1_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch2_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch3_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch4_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch5_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch6_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch7_xcvr_tx_spread_spectrum_en_hwtcl |
ENABLE |
| core8_ch0_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch1_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch2_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch3_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch4_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch5_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch6_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch7_xcvr_cdr_f_ref_hz_hwtcl |
100000000 |
| core8_ch0_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch1_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch2_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch3_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch4_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch5_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch6_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch7_tx_pll_f_ref_hz_hwtcl |
100000000 |
| core8_ch0_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch1_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch2_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch3_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch4_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch5_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch6_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch7_xcvr_cdr_f_vco_hz_hwtcl |
1410065408 |
| core8_ch0_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch1_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch2_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch3_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch4_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch5_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch6_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch7_xcvr_rx_datarate_bps_hwtcl |
8000 |
| core8_ch0_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch1_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch2_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch3_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch4_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch5_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch6_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch7_xcvr_tx_datarate_bps_hwtcl |
8000 |
| core8_ch0_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch1_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch2_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch3_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch4_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch5_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch6_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch7_rx_postdiv_clk_divider_hwtcl |
12 |
| core8_ch0_tx_postdiv_clk_divider_hwtcl |
52 |
| core8_ch1_tx_postdiv_clk_divider_hwtcl |
137 |
| core8_ch2_tx_postdiv_clk_divider_hwtcl |
73 |
| core8_ch3_tx_postdiv_clk_divider_hwtcl |
4 |
| core8_ch4_tx_postdiv_clk_divider_hwtcl |
52 |
| core8_ch5_tx_postdiv_clk_divider_hwtcl |
137 |
| core8_ch6_tx_postdiv_clk_divider_hwtcl |
73 |
| core8_ch7_tx_postdiv_clk_divider_hwtcl |
4 |
| core8_ch0_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch1_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch2_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch3_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch4_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch5_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch6_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch7_xcvr_tx_prbs_pattern_hwtcl |
DISABLE |
| core8_ch0_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch1_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch2_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch3_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch4_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch5_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch6_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch7_xcvr_rx_adaptation_mode_hwtcl |
UX_NATIVE_ADAPTATION |
| core8_ch0_xcvr_rx_width_hwtcl |
16 |
| core8_ch1_xcvr_rx_width_hwtcl |
16 |
| core8_ch2_xcvr_rx_width_hwtcl |
16 |
| core8_ch3_xcvr_rx_width_hwtcl |
16 |
| core8_ch4_xcvr_rx_width_hwtcl |
16 |
| core8_ch5_xcvr_rx_width_hwtcl |
16 |
| core8_ch6_xcvr_rx_width_hwtcl |
16 |
| core8_ch7_xcvr_rx_width_hwtcl |
16 |
| core8_ch0_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch1_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch2_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch3_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch4_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch5_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch6_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch7_tx_pll_refclk_select_hwtcl |
GLOBAL_REFCLK0 |
| core8_ch0_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch1_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch2_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch3_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch4_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch5_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch6_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch7_tx_invert_pin_hwtcl |
DISABLE |
| core8_ch0_sim_mode_hwtcl |
DISABLE |
| core8_ch1_sim_mode_hwtcl |
DISABLE |
| core8_ch2_sim_mode_hwtcl |
DISABLE |
| core8_ch3_sim_mode_hwtcl |
DISABLE |
| core8_ch4_sim_mode_hwtcl |
DISABLE |
| core8_ch5_sim_mode_hwtcl |
DISABLE |
| core8_ch6_sim_mode_hwtcl |
DISABLE |
| core8_ch7_sim_mode_hwtcl |
DISABLE |
| protocol_hard_pcie_lowloss |
DISABLE |
| deviceFamily |
UNKNOWN |
| generateLegacySim |
false |