pcie_ed

2025.12.12.14:57:25 Datasheet
Overview

All Components
   pio_button altera_avalon_pio 19.2.4
   pio_led altera_avalon_pio 19.2.4
Memory Map
axi_bridge_ddr4a axi_bridge_ddr4b axi_bridge_ddr4c dma pcie_ed_axi_pipe_onchip_mem
 m0  m0  m0  ss_csr_lite  dma_mm_initatr  pio_lite_initatr  m0
  axi_bridge_ddr4a
s0  0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff
  axi_bridge_ddr4b
s0  0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff
  axi_bridge_ddr4c
s0  0x0000_0012_0000_0000 - 0x0000_0012_ffff_ffff
  dut
p0_lite_csr  0x0000_0000 - 0x000f_ffff
  emif_lpddr4a
s0_axi4  0x0000_0000 - 0xffff_ffff 0x0000_0010_0000_0000 - 0x0000_0010_ffff_ffff
s0_axi4lite 
  emif_lpddr4b
s0_axi4  0x0000_0000 - 0xffff_ffff 0x0000_0011_0000_0000 - 0x0000_0011_ffff_ffff
s0_axi4lite 
  emif_lpddr4c
s0_axi4  0x0000_0000 - 0xffff_ffff 0x0000_0012_0000_0000 - 0x0000_0012_ffff_ffff
s0_axi4lite 
  intel_onchip_memory
axi_s1  0x0000_0000_0010_0000 - 0x0000_0000_0017_ffff 0x0000_0000 - 0x0007_ffff
  pcie_ed_axi_pipe_onchip_mem
s0  0x0000_0000_0010_0000 - 0x0000_0000_0017_ffff
  pio_button
s1  0x0080_0040 - 0x0080_004f
  pio_led
s1  0x0080_0000 - 0x0080_000f

axi_bridge_ddr4a

altera_axi_bridge v19.10.0
dma dma_mm_initatr   axi_bridge_ddr4a
  s0
dut p0_coreclkout_hip_toapp  
  clk
rst_ctrl_0 rst_n_sys  
  clk_reset
emif_lpddr4a s0_axi4_ctrl_ready  
  clk_reset
m0   emif_lpddr4a
  s0_axi4


Parameters

generateLegacySim false
  

Software Assignments

(none)

axi_bridge_ddr4b

altera_axi_bridge v19.10.0
dma dma_mm_initatr   axi_bridge_ddr4b
  s0
dut p0_coreclkout_hip_toapp  
  clk
rst_ctrl_0 rst_n_sys  
  clk_reset
emif_lpddr4b s0_axi4_ctrl_ready  
  clk_reset
m0   emif_lpddr4b
  s0_axi4


Parameters

generateLegacySim false
  

Software Assignments

(none)

axi_bridge_ddr4c

altera_axi_bridge v19.10.0
dma dma_mm_initatr   axi_bridge_ddr4c
  s0
dut p0_coreclkout_hip_toapp  
  clk
rst_ctrl_0 rst_n_sys  
  clk_reset
emif_lpddr4c s0_axi4_ctrl_ready  
  clk_reset
m0   emif_lpddr4c
  s0_axi4


Parameters

generateLegacySim false
  

Software Assignments

(none)

dma

pcie_gts_mcdma v1.2.0
dut p0_st_ciireq   dma
  p0_st_ciireq
p0_st_cplto  
  ss_cplto
p0_st_ctrlshadow  
  ss_ctrlshadow
p0_st_rx  
  ss_rx_st
p0_st_txcrdt  
  ss_txcrdt
p0_coreclkout_hip_toapp  
  axi_mm_clk
p0_coreclkout_hip_toapp  
  axi_st_clk
p0_ss_app_st_rx_tuser_hdr  
  st_rx_tuser_hdr
p0_ss_app_st_rx_tuser_hvalid  
  st_rx_tuser_hvalid
iopll0 outclk0  
  axi_lite_clk
rst_ctrl_0 rst_n_100m  
  axi_lite_areset_n
rst_n_sys  
  axi_mm_areset_n
rst_n_sys  
  axi_st_areset_n
dma_mm_initatr   pcie_ed_axi_pipe_onchip_mem
  s0
dma_mm_initatr   axi_bridge_ddr4a
  s0
dma_mm_initatr   axi_bridge_ddr4b
  s0
dma_mm_initatr   axi_bridge_ddr4c
  s0
pio_lite_initatr   pio_led
  s1
pio_lite_initatr   pio_button
  s1
ss_csr_lite   dut
  p0_lite_csr
p0_st_ciiresp  
  p0_st_ciiresp
ss_tx_st  
  p0_st_tx
app_ss_st_rx_tuser_halt  
  p0_app_ss_st_rx_tuser_halt
st_tx_tuser_hdr  
  p0_app_ss_st_tx_tuser_hdr
st_tx_tuser_hvalid  
  p0_app_ss_st_tx_tuser_hvalid


Parameters

generateLegacySim false
  

Software Assignments

(none)

dut

intel_pcie_gts v9.1.0
dma ss_csr_lite   dut
  p0_lite_csr
p0_st_ciiresp  
  p0_st_ciiresp
ss_tx_st  
  p0_st_tx
app_ss_st_rx_tuser_halt  
  p0_app_ss_st_rx_tuser_halt
st_tx_tuser_hdr  
  p0_app_ss_st_tx_tuser_hdr
st_tx_tuser_hvalid  
  p0_app_ss_st_tx_tuser_hvalid
syspll_inst0 o_syspll_c0  
  p0_i_syspll_c0_clk
o_pll_lock  
  p0_i_ss_vccl_syspll_locked
iopll0 outclk0  
  p0_axi_lite_clk
rst_ctrl_0 initiate_rst_req_rdy  
  p0_initiate_rst_req_rdy
subsystem_rst_rdy  
  p0_subsystem_rst_rdy
pcie_cold_rst_n  
  p0_subsystem_cold_rst_n
pcie_warm_rst_n  
  p0_subsystem_warm_rst_n
rst_n_100m  
  p0_axi_lite_areset_n
rst_n_sys  
  p0_axi_st_areset_n
resetIP ninit_done  
  ninit_done
p0_st_ciireq   dma
  p0_st_ciireq
p0_st_cplto  
  ss_cplto
p0_st_ctrlshadow  
  ss_ctrlshadow
p0_st_rx  
  ss_rx_st
p0_st_txcrdt  
  ss_txcrdt
p0_coreclkout_hip_toapp  
  axi_mm_clk
p0_coreclkout_hip_toapp  
  axi_st_clk
p0_ss_app_st_rx_tuser_hdr  
  st_rx_tuser_hdr
p0_ss_app_st_rx_tuser_hvalid  
  st_rx_tuser_hvalid
p0_coreclkout_hip_toapp   pcie_ed_axi_pipe_onchip_mem
  clk
p0_coreclkout_hip_toapp   axi_bridge_ddr4a
  clk
p0_coreclkout_hip_toapp   axi_bridge_ddr4b
  clk
p0_coreclkout_hip_toapp   axi_bridge_ddr4c
  clk
p0_coreclkout_hip_toapp   intel_onchip_memory
  clk1
p0_coreclkout_hip_toapp   rst_ctrl_0
  clk_sys
p0_initiate_warmrst_req  
  initiate_warmrst_req
p0_subsystem_cold_rst_ack_n  
  pcie_cold_rst_ack_n
p0_subsystem_rst_req  
  subsystem_rst_req
p0_subsystem_warm_rst_ack_n  
  pcie_warm_rst_ack_n
p0_reset_status_n  
  pcie_reset_status
p0_coreclkout_hip_toapp   emif_lpddr4c
  s0_axi4_clock_in
p0_coreclkout_hip_toapp   emif_lpddr4b
  s0_axi4_clock_in
p0_coreclkout_hip_toapp   emif_lpddr4a
  s0_axi4_clock_in
i_flux_clk   srcssIP
  o_pma_cu_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4a

emif_io96b_lpddr4 v4.1.0
axi_bridge_ddr4a m0   emif_lpddr4a
  s0_axi4
iopll0 outclk0  
  s0_axi4lite_clock
dut p0_coreclkout_hip_toapp  
  s0_axi4_clock_in
resetIP ninit_done  
  core_init_n
rst_ctrl_0 rst_n_100m  
  s0_axi4lite_reset_n
s0_axi4_ctrl_ready   axi_bridge_ddr4a
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4b

emif_io96b_lpddr4 v4.1.0
axi_bridge_ddr4b m0   emif_lpddr4b
  s0_axi4
iopll0 outclk0  
  s0_axi4lite_clock
dut p0_coreclkout_hip_toapp  
  s0_axi4_clock_in
resetIP ninit_done  
  core_init_n
rst_ctrl_0 rst_n_100m  
  s0_axi4lite_reset_n
s0_axi4_ctrl_ready   axi_bridge_ddr4b
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4c

emif_io96b_lpddr4 v4.1.0
axi_bridge_ddr4c m0   emif_lpddr4c
  s0_axi4
iopll0 outclk0  
  s0_axi4lite_clock
dut p0_coreclkout_hip_toapp  
  s0_axi4_clock_in
resetIP ninit_done  
  core_init_n
rst_ctrl_0 rst_n_100m  
  s0_axi4lite_reset_n
s0_axi4_ctrl_ready   axi_bridge_ddr4c
  clk_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_onchip_memory

intel_onchip_memory v1.4.10
pcie_ed_axi_pipe_onchip_mem m0   intel_onchip_memory
  axi_s1
dut p0_coreclkout_hip_toapp  
  clk1
rst_ctrl_0 rst_n_sys  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE UNUSED
INIT_MEM_CONTENT 0
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 0
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524288
WRITABLE 1

iopll0

altera_iopll v21.0.0
resetIP ninit_done   iopll0
  reset
outclk0   dma
  axi_lite_clk
outclk0   pio_led
  clk
outclk0   pio_button
  clk
outclk0   rst_ctrl_0
  clk_100m
locked  
  pll_locked
outclk0   dut
  p0_axi_lite_clk
outclk0   emif_lpddr4a
  s0_axi4lite_clock
outclk0   emif_lpddr4b
  s0_axi4lite_clock
outclk0   emif_lpddr4c
  s0_axi4lite_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

pcie_ed_axi_pipe_onchip_mem

altera_axi_bridge v19.10.0
dma dma_mm_initatr   pcie_ed_axi_pipe_onchip_mem
  s0
dut p0_coreclkout_hip_toapp  
  clk
rst_ctrl_0 rst_n_sys  
  clk_reset
m0   intel_onchip_memory
  axi_s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

pio_button

altera_avalon_pio v19.2.4
dma pio_lite_initatr   pio_button
  s1
iopll0 outclk0  
  clk
rst_ctrl_0 rst_n_100m  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_led

altera_avalon_pio v19.2.4
dma pio_lite_initatr   pio_led
  s1
iopll0 outclk0  
  clk
rst_ctrl_0 rst_n_100m  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 250000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

resetIP

altera_s10_user_rst_clkgate v19.4.9


Parameters

generateLegacySim false
  

Software Assignments

(none)

rst_ctrl_0

rst_ctrl_0 v1.0
iopll0 outclk0   rst_ctrl_0
  clk_100m
locked  
  pll_locked
dut p0_coreclkout_hip_toapp  
  clk_sys
p0_initiate_warmrst_req  
  initiate_warmrst_req
p0_subsystem_cold_rst_ack_n  
  pcie_cold_rst_ack_n
p0_subsystem_rst_req  
  subsystem_rst_req
p0_subsystem_warm_rst_ack_n  
  pcie_warm_rst_ack_n
p0_reset_status_n  
  pcie_reset_status
resetIP ninit_done  
  ninit_done
initiate_rst_req_rdy   dut
  p0_initiate_rst_req_rdy
subsystem_rst_rdy  
  p0_subsystem_rst_rdy
pcie_cold_rst_n  
  p0_subsystem_cold_rst_n
pcie_warm_rst_n  
  p0_subsystem_warm_rst_n
rst_n_100m  
  p0_axi_lite_areset_n
rst_n_sys  
  p0_axi_st_areset_n
rst_n_100m   dma
  axi_lite_areset_n
rst_n_sys  
  axi_mm_areset_n
rst_n_sys  
  axi_st_areset_n
rst_n_100m   pio_led
  reset
rst_n_100m   pio_button
  reset
rst_n_100m   emif_lpddr4a
  s0_axi4lite_reset_n
rst_n_100m   emif_lpddr4b
  s0_axi4lite_reset_n
rst_n_100m   emif_lpddr4c
  s0_axi4lite_reset_n
rst_n_sys   pcie_ed_axi_pipe_onchip_mem
  clk_reset
rst_n_sys   axi_bridge_ddr4a
  clk_reset
rst_n_sys   axi_bridge_ddr4b
  clk_reset
rst_n_sys   axi_bridge_ddr4c
  clk_reset
rst_n_sys   intel_onchip_memory
  reset1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

srcssIP

intel_srcss_gts v5.0.0
dut i_flux_clk   srcssIP
  o_pma_cu_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

syspll_inst0

intel_systemclk_gts v5.1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)
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