pcie_ed_axi_pipe_ddr4

2025.12.12.14:57:27 Datasheet
Overview

Memory Map
pcie_ed_axi_pipe_onchip_mem
 m0
  pcie_ed_axi_pipe_onchip_mem
s0 

pcie_ed_axi_pipe_onchip_mem

altera_axi_bridge v19.10.0


Parameters

USE_PIPELINE 1
USE_M0_AWID 1
USE_M0_AWREGION 0
USE_M0_AWLEN 1
USE_M0_AWSIZE 1
USE_M0_AWBURST 1
USE_M0_AWLOCK 1
USE_M0_AWCACHE 0
USE_M0_AWQOS 1
USE_M0_AWUNIQUE 0
USE_S0_AWREGION 0
USE_S0_AWLOCK 1
USE_S0_AWCACHE 0
USE_S0_AWQOS 0
USE_S0_AWPROT 1
USE_M0_WSTRB 1
USE_S0_WLAST 1
USE_M0_BID 1
USE_M0_BRESP 1
USE_S0_BRESP 1
USE_M0_ARID 1
USE_M0_ARREGION 0
USE_M0_ARLEN 1
USE_M0_ARSIZE 1
USE_M0_ARBURST 1
USE_M0_ARLOCK 1
USE_M0_ARCACHE 0
USE_M0_ARQOS 1
USE_S0_ARREGION 0
USE_S0_ARLOCK 1
USE_S0_ARCACHE 0
USE_S0_ARQOS 0
USE_S0_ARPROT 1
USE_M0_RID 1
USE_M0_RRESP 1
USE_M0_RLAST 1
USE_S0_RRESP 1
M0_ID_WIDTH 7
S0_ID_WIDTH 7
DATA_WIDTH 256
UNTRANSLATED_TXN 0
CACHESTASHING_TXN 0
ATOMIC_TXN 0
SID_WIDTH 1
WRITE_ADDR_USER_WIDTH 14
READ_ADDR_USER_WIDTH 14
WRITE_DATA_USER_WIDTH 1
WRITE_RESP_USER_WIDTH 1
READ_DATA_USER_WIDTH 1
ADDR_WIDTH 32
USE_S0_AWUSER 0
USE_S0_ARUSER 0
USE_S0_WUSER 0
USE_S0_RUSER 0
USE_S0_BUSER 0
USE_M0_AWUSER 1
USE_M0_ARUSER 1
USE_M0_ARSNOOP 0
USE_M0_AWSNOOP 0
USE_M0_WUSER 0
USE_M0_RUSER 0
USE_M0_BUSER 0
BITSPERBYTE 0
SAI_WIDTH 1
USE_M0_ADDRCHK 0
USE_M0_DATACHK 0
USE_M0_SAI 0
USE_M0_POISON 0
USE_M0_USER_DATA 0
USE_M0_AWAKEUP 0
USE_M0_TRACE 0
USE_S0_ADDRCHK 0
USE_S0_DATACHK 0
USE_S0_SAI 0
USE_S0_POISON 0
USE_S0_USER_DATA 0
USE_S0_AWAKEUP 0
USE_S0_TRACE 0
AXI_VERSION AXI4
WRITE_ISSUING_CAPABILITY 16
READ_ISSUING_CAPABILITY 16
COMBINED_ISSUING_CAPABILITY 16
WRITE_ACCEPTANCE_CAPABILITY 16
READ_ACCEPTANCE_CAPABILITY 16
COMBINED_ACCEPTANCE_CAPABILITY 16
READ_DATA_REORDERING_DEPTH 1
ACE_LITE_SUPPORT 0
ACE5_LITE_SUPPORT 0
SYNC_RESET 1
ENABLE_CONCURRENT_SUBORDINATE_ACCESS 0
NO_REPEATED_IDS_BETWEEN_SUBORDINATES 0
BACKPRESSURE_DURING_RESET 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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