golden top Board Configuration

golden top Board Configuration

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Pin Assignments:

CLOCK
Name Location Direction IO Standard
CLK_100_p BM71 input 1.2-V TRUE DIFFERENTIAL SIGNALING
CLK_50_B5B BE107 input 3.3-V LVCMOS
CLK_50_B6A BK31 input 3.3-V LVCMOS
CLK_50_B6C D8 input 3.3-V LVCMOS

Buttons
Name Location Direction IO Standard
USER_BUTTON CA118 input 3.3-V LVCMOS
BUTTON BK112 input 3.3-V LVCMOS

Swtiches
Name Location Direction IO Standard
USER_SW[0] BR118 input 3.3-V LVCMOS
USER_SW[1] BW118 input 3.3-V LVCMOS

LED
Name Location Direction IO Standard
USER_LED CF121 output 3.3-V LVCMOS
LED BF120 output 3.3-V LVCMOS

SD Card
Name Location Direction IO Standard
SD_MMC_SEL BK118 inout 3.3-V LVCMOS

LPDDR4A
Name Location Direction IO Standard
LPDDR4A_REFCLK_p M105 input 1.1-V TRUE DIFFERENTIAL SIGNALING
LPDDR4A_CS_n T105 output 1.1-V LVSTL
LPDDR4A_CA[0] T114 output 1.1-V LVSTL
LPDDR4A_CA[1] P114 output 1.1-V LVSTL
LPDDR4A_CA[2] V117 output 1.1-V LVSTL
LPDDR4A_CA[3] T117 output 1.1-V LVSTL
LPDDR4A_CA[4] M114 output 1.1-V LVSTL
LPDDR4A_CA[5] K114 output 1.1-V LVSTL
LPDDR4A_CK AK107 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_CKE V108 output 1.1-V LVSTL
LPDDR4A_CK_n AK104 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DM[0] B119 inout 1.1-V LVSTL
LPDDR4A_DM[1] F105 inout 1.1-V LVSTL
LPDDR4A_DM[2] B97 inout 1.1-V LVSTL
LPDDR4A_DM[3] H87 inout 1.1-V LVSTL
LPDDR4A_DQ[0] A116 inout 1.1-V LVSTL
LPDDR4A_DQ[1] A128 inout 1.1-V LVSTL
LPDDR4A_DQ[2] B130 inout 1.1-V LVSTL
LPDDR4A_DQ[3] A130 inout 1.1-V LVSTL
LPDDR4A_DQ[4] A113 inout 1.1-V LVSTL
LPDDR4A_DQ[5] B128 inout 1.1-V LVSTL
LPDDR4A_DQ[6] B116 inout 1.1-V LVSTL
LPDDR4A_DQ[7] B113 inout 1.1-V LVSTL
LPDDR4A_DQ[8] K108 inout 1.1-V LVSTL
LPDDR4A_DQ[9] H108 inout 1.1-V LVSTL
LPDDR4A_DQ[10] F117 inout 1.1-V LVSTL
LPDDR4A_DQ[11] K117 inout 1.1-V LVSTL
LPDDR4A_DQ[12] M117 inout 1.1-V LVSTL
LPDDR4A_DQ[13] H117 inout 1.1-V LVSTL
LPDDR4A_DQ[14] M108 inout 1.1-V LVSTL
LPDDR4A_DQ[15] F108 inout 1.1-V LVSTL
LPDDR4A_DQ[16] B106 inout 1.1-V LVSTL
LPDDR4A_DQ[17] A110 inout 1.1-V LVSTL
LPDDR4A_DQ[18] A106 inout 1.1-V LVSTL
LPDDR4A_DQ[19] B103 inout 1.1-V LVSTL
LPDDR4A_DQ[20] A94 inout 1.1-V LVSTL
LPDDR4A_DQ[21] B91 inout 1.1-V LVSTL
LPDDR4A_DQ[22] A91 inout 1.1-V LVSTL
LPDDR4A_DQ[23] B88 inout 1.1-V LVSTL
LPDDR4A_DQ[24] M87 inout 1.1-V LVSTL
LPDDR4A_DQ[25] K87 inout 1.1-V LVSTL
LPDDR4A_DQ[26] D84 inout 1.1-V LVSTL
LPDDR4A_DQ[27] F84 inout 1.1-V LVSTL
LPDDR4A_DQ[28] M98 inout 1.1-V LVSTL
LPDDR4A_DQ[29] K98 inout 1.1-V LVSTL
LPDDR4A_DQ[30] F98 inout 1.1-V LVSTL
LPDDR4A_DQ[31] H98 inout 1.1-V LVSTL
LPDDR4A_DQS[0] B122 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS[1] F114 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS[2] A101 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS[3] F95 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[0] A125 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[1] D114 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[2] B101 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[3] D95 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_RESET_n AG111 output 1.1-V LVSTL
LPDDR4A_RZQ AK111 input 1.1-V

LPDDR4B
Name Location Direction IO Standard
LPDDR4B_REFCLK_p T65 input 1.1-V TRUE DIFFERENTIAL SIGNALING
LPDDR4B_CS_n M65 output 1.1-V LVSTL
LPDDR4B_CA[0] P74 output 1.1-V LVSTL
LPDDR4B_CA[1] T74 output 1.1-V LVSTL
LPDDR4B_CA[2] V77 output 1.1-V LVSTL
LPDDR4B_CA[3] T77 output 1.1-V LVSTL
LPDDR4B_CA[4] M74 output 1.1-V LVSTL
LPDDR4B_CA[5] K74 output 1.1-V LVSTL
LPDDR4B_CK AG83 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_CKE V67 output 1.1-V LVSTL
LPDDR4B_CK_n AC83 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DM[0] B73 inout 1.1-V LVSTL
LPDDR4B_DM[1] M67 inout 1.1-V LVSTL
LPDDR4B_DM[2] B51 inout 1.1-V LVSTL
LPDDR4B_DM[3] M47 inout 1.1-V LVSTL
LPDDR4B_DQ[0] A70 inout 1.1-V LVSTL
LPDDR4B_DQ[1] B82 inout 1.1-V LVSTL
LPDDR4B_DQ[2] A82 inout 1.1-V LVSTL
LPDDR4B_DQ[3] A85 inout 1.1-V LVSTL
LPDDR4B_DQ[4] B85 inout 1.1-V LVSTL
LPDDR4B_DQ[5] A66 inout 1.1-V LVSTL
LPDDR4B_DQ[6] B70 inout 1.1-V LVSTL
LPDDR4B_DQ[7] B66 inout 1.1-V LVSTL
LPDDR4B_DQ[8] H67 inout 1.1-V LVSTL
LPDDR4B_DQ[9] F65 inout 1.1-V LVSTL
LPDDR4B_DQ[10] H77 inout 1.1-V LVSTL
LPDDR4B_DQ[11] M77 inout 1.1-V LVSTL
LPDDR4B_DQ[12] K77 inout 1.1-V LVSTL
LPDDR4B_DQ[13] F77 inout 1.1-V LVSTL
LPDDR4B_DQ[14] F67 inout 1.1-V LVSTL
LPDDR4B_DQ[15] D65 inout 1.1-V LVSTL
LPDDR4B_DQ[16] A60 inout 1.1-V LVSTL
LPDDR4B_DQ[17] A63 inout 1.1-V LVSTL
LPDDR4B_DQ[18] B60 inout 1.1-V LVSTL
LPDDR4B_DQ[19] B56 inout 1.1-V LVSTL
LPDDR4B_DQ[20] A48 inout 1.1-V LVSTL
LPDDR4B_DQ[21] A45 inout 1.1-V LVSTL
LPDDR4B_DQ[22] B45 inout 1.1-V LVSTL
LPDDR4B_DQ[23] B42 inout 1.1-V LVSTL
LPDDR4B_DQ[24] H47 inout 1.1-V LVSTL
LPDDR4B_DQ[25] F44 inout 1.1-V LVSTL
LPDDR4B_DQ[26] D44 inout 1.1-V LVSTL
LPDDR4B_DQ[27] F47 inout 1.1-V LVSTL
LPDDR4B_DQ[28] K58 inout 1.1-V LVSTL
LPDDR4B_DQ[29] M58 inout 1.1-V LVSTL
LPDDR4B_DQ[30] F58 inout 1.1-V LVSTL
LPDDR4B_DQ[31] H58 inout 1.1-V LVSTL
LPDDR4B_DQS[0] A80 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS[1] D74 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS[2] A54 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS[3] F55 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS_n[0] B76 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS_n[1] F74 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS_n[2] B54 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS_n[3] D55 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_RESET_n AG79 output 1.1-V LVSTL
LPDDR4B_RZQ AC79 input 1.1-V

LPDDR4C
Name Location Direction IO Standard
LPDDR4C_REFCLK_p CH38 input 1.1-V TRUE DIFFERENTIAL SIGNALING
LPDDR4C_CS_n CC41 output 1.1-V LVSTL
LPDDR4C_CA[0] CF52 output 1.1-V LVSTL
LPDDR4C_CA[1] CH52 output 1.1-V LVSTL
LPDDR4C_CA[2] CC52 output 1.1-V LVSTL
LPDDR4C_CA[3] CA52 output 1.1-V LVSTL
LPDDR4C_CA[4] CF49 output 1.1-V LVSTL
LPDDR4C_CA[5] CH49 output 1.1-V LVSTL
LPDDR4C_CK BR41 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_CKE CH41 output 1.1-V LVSTL
LPDDR4C_CK_n BU41 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DM[0] CK35 inout 1.1-V LVSTL
LPDDR4C_DM[1] CL56 inout 1.1-V LVSTL
LPDDR4C_DM[2] CL14 inout 1.1-V LVSTL
LPDDR4C_DM[3] CC22 inout 1.1-V LVSTL
LPDDR4C_DQ[0] CL30 inout 1.1-V LVSTL
LPDDR4C_DQ[1] CK33 inout 1.1-V LVSTL
LPDDR4C_DQ[2] CL26 inout 1.1-V LVSTL
LPDDR4C_DQ[3] CK30 inout 1.1-V LVSTL
LPDDR4C_DQ[4] CK45 inout 1.1-V LVSTL
LPDDR4C_DQ[5] CK48 inout 1.1-V LVSTL
LPDDR4C_DQ[6] CL45 inout 1.1-V LVSTL
LPDDR4C_DQ[7] CL42 inout 1.1-V LVSTL
LPDDR4C_DQ[8] CK56 inout 1.1-V LVSTL
LPDDR4C_DQ[9] CL54 inout 1.1-V LVSTL
LPDDR4C_DQ[10] CL70 inout 1.1-V LVSTL
LPDDR4C_DQ[11] CL73 inout 1.1-V LVSTL
LPDDR4C_DQ[12] CK66 inout 1.1-V LVSTL
LPDDR4C_DQ[13] CK54 inout 1.1-V LVSTL
LPDDR4C_DQ[14] CL51 inout 1.1-V LVSTL
LPDDR4C_DQ[15] CK73 inout 1.1-V LVSTL
LPDDR4C_DQ[16] CL23 inout 1.1-V LVSTL
LPDDR4C_DQ[17] CL20 inout 1.1-V LVSTL
LPDDR4C_DQ[18] CK26 inout 1.1-V LVSTL
LPDDR4C_DQ[19] CK20 inout 1.1-V LVSTL
LPDDR4C_DQ[20] CL8 inout 1.1-V LVSTL
LPDDR4C_DQ[21] CL6 inout 1.1-V LVSTL
LPDDR4C_DQ[22] CK8 inout 1.1-V LVSTL
LPDDR4C_DQ[23] CK11 inout 1.1-V LVSTL
LPDDR4C_DQ[24] CC31 inout 1.1-V LVSTL
LPDDR4C_DQ[25] CF31 inout 1.1-V LVSTL
LPDDR4C_DQ[26] CF19 inout 1.1-V LVSTL
LPDDR4C_DQ[27] CH31 inout 1.1-V LVSTL
LPDDR4C_DQ[28] CH22 inout 1.1-V LVSTL
LPDDR4C_DQ[29] CF22 inout 1.1-V LVSTL
LPDDR4C_DQ[30] CC19 inout 1.1-V LVSTL
LPDDR4C_DQ[31] CA31 inout 1.1-V LVSTL
LPDDR4C_DQS[0] CK39 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS[1] CK63 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS[2] CK17 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS[3] CF28 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS_n[0] CL39 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS_n[1] CL66 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS_n[2] CL17 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_DQS_n[3] CC28 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4C_RESET_n BU52 output 1.1-V LVSTL
LPDDR4C_RZQ BR52 input 1.1-V

HDMI
Name Location Direction IO Standard
DDC_I2C_SCL CL130 inout 3.3-V LVCMOS
DDC_I2C_SDA CL125 inout 3.3-V LVCMOS
HDMI_I2C_SCL CG135 inout 3.3-V LVCMOS
HDMI_I2C_SDA BU118 inout 3.3-V LVCMOS
HDMI_TX_HS BM69 output 1.2-V
HDMI_TX_VS BM62 output 1.2-V
HDMI_TX_D[0] CF62 output 1.2-V
HDMI_TX_D[1] CH62 output 1.2-V
HDMI_TX_D[2] CA62 output 1.2-V
HDMI_TX_D[3] CC62 output 1.2-V
HDMI_TX_D[4] CC71 output 1.2-V
HDMI_TX_D[5] CA71 output 1.2-V
HDMI_TX_D[6] CF71 output 1.2-V
HDMI_TX_D[7] CH71 output 1.2-V
HDMI_TX_D[8] BW59 output 1.2-V
HDMI_TX_D[9] CA59 output 1.2-V
HDMI_TX_D[10] BU59 output 1.2-V
HDMI_TX_D[11] BR59 output 1.2-V
HDMI_TX_D[12] BU62 output 1.2-V
HDMI_TX_D[13] BR62 output 1.2-V
HDMI_TX_D[14] BW69 output 1.2-V
HDMI_TX_D[15] CA69 output 1.2-V
HDMI_TX_D[16] BR71 output 1.2-V
HDMI_TX_D[17] BU71 output 1.2-V
HDMI_TX_D[18] BR69 output 1.2-V
HDMI_TX_D[19] BU69 output 1.2-V
HDMI_TX_D[20] BM59 output 1.2-V
HDMI_TX_D[21] BK59 output 1.2-V
HDMI_TX_D[22] BH62 output 1.2-V
HDMI_TX_D[23] BH59 output 1.2-V
HDMI_TX_DE BP62 output 1.2-V
HDMI_TX_CLK_p BE83 output DIFFERENTIAL 1.2-V SSTL
HDMI_EDGE_HPD CG134 output 3.3-V LVCMOS
HDMI_ISEL CK134 output 3.3-V LVCMOS
HDMI_PD_n CK128 output 3.3-V LVCMOS

SLVS
Name Location Direction IO Standard
SLVS_EC_RX_p[0] BV135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[1] BN135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[2] BJ135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[3] BF135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[4] BD135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[5] BB135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[6] AY135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_p[7] AV135 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[0] BV133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[1] BN133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[2] BJ133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[3] BF133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[4] BD133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[5] BB133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[6] AY133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_RX_n[7] AV133 input HIGH SPEED DIFFERENTIAL I/O
SLVS_EC_SDO A20 input 1.8-V LVCMOS
SLVS_EC_REFCLK_p BC111 input CURRENT MODE LOGIC (CML)
SLVS_EC_INCK_OE A14 output 1.8-V LVCMOS
SLVS_EC_OMODE B35 output 1.8-V LVCMOS
SLVS_EC_SCK_SCL B11 inout 1.8-V LVCMOS
SLVS_EC_SDI_SDA A35 inout 1.8-V LVCMOS
SLVS_EC_SENSOR_PGOOD B20 input 1.8-V LVCMOS
SLVS_EC_SENSOR_PON B23 output 1.8-V LVCMOS
SLVS_EC_XCE B14 output 1.8-V LVCMOS
SLVS_EC_XCLR A39 output 1.8-V LVCMOS
SLVS_EC_XHS A8 output 1.8-V LVCMOS
SLVS_EC_XMASTER A23 output 1.8-V LVCMOS
SLVS_EC_XTRIG[1] A17 output 1.8-V LVCMOS
SLVS_EC_XTRIG[2] B4 output 1.8-V LVCMOS
SLVS_EC_XVS A11 output 1.8-V LVCMOS

ENET
Name Location Direction IO Standard
ENET_88E2110_TX_p AL129 output HIGH SPEED DIFFERENTIAL I/O
ENET_88E2110_TX_n AL126 output HIGH SPEED DIFFERENTIAL I/O
ENET_88E2110_RX_p AK135 input HIGH SPEED DIFFERENTIAL I/O
ENET_88E2110_RX_n AK133 input HIGH SPEED DIFFERENTIAL I/O
ENET_88E2110_REFCLK_156M25_p AT120 input CURRENT MODE LOGIC (CML)
ENET_88E2110_INT_n F8 input 3.3-V LVCMOS
ENET_88E2110_MDC K4 output 3.3-V LVCMOS
ENET_88E2110_MDIO H18 inout 3.3-V LVCMOS
ENET_88E2110_RESET_n D15 output 3.3-V LVCMOS

SI5332B
Name Location Direction IO Standard
SI5332B_I2C_SCL BP112 inout 3.3-V LVCMOS
SI5332B_I2C_SDA BM118 inout 3.3-V LVCMOS

SI5340B
Name Location Direction IO Standard
SI5340B_I2C_SCL BE111 inout 3.3-V LVCMOS
SI5340B_I2C_SDA BK109 inout 3.3-V LVCMOS
SI5340B_OE_n BR112 output 3.3-V LVCMOS
SI5340B_RST_n BM109 output 3.3-V LVCMOS

SI564
Name Location Direction IO Standard
SI564_SCL A30 inout 1.8-V LVCMOS
SI564_SDA D34 inout 1.8-V LVCMOS

GPIO
Name Location Direction IO Standard
GPIO_D[0] BF29 inout 3.3-V LVCMOS
GPIO_D[1] BE43 inout 3.3-V LVCMOS
GPIO_D[2] BP22 inout 3.3-V LVCMOS
GPIO_D[3] BF40 inout 3.3-V LVCMOS
GPIO_D[4] BF16 inout 3.3-V LVCMOS
GPIO_D[5] BF21 inout 3.3-V LVCMOS
GPIO_D[6] BE21 inout 3.3-V LVCMOS
GPIO_D[7] BF25 inout 3.3-V LVCMOS
GPIO_D[8] BF32 inout 3.3-V LVCMOS
GPIO_D[9] BF36 inout 3.3-V LVCMOS
GPIO_D[10] BH28 inout 3.3-V LVCMOS
GPIO_D[11] BH19 inout 3.3-V LVCMOS
GPIO_D[12] BM19 inout 3.3-V LVCMOS
GPIO_D[13] BK28 inout 3.3-V LVCMOS
GPIO_D[14] BK22 inout 3.3-V LVCMOS
GPIO_D[15] CH4 inout 3.3-V LVCMOS
GPIO_D[16] BR19 inout 3.3-V LVCMOS
GPIO_D[17] CK4 inout 3.3-V LVCMOS
GPIO_D[18] BM31 inout 3.3-V LVCMOS
GPIO_D[19] BU19 inout 3.3-V LVCMOS
GPIO_D[20] BM28 inout 3.3-V LVCMOS
GPIO_D[21] BK19 inout 3.3-V LVCMOS
GPIO_D[22] CJ2 inout 3.3-V LVCMOS
GPIO_D[23] CF9 inout 3.3-V LVCMOS
GPIO_D[24] CH12 inout 3.3-V LVCMOS
GPIO_D[25] CK2 inout 3.3-V LVCMOS
GPIO_D[26] BU28 inout 3.3-V LVCMOS
GPIO_D[27] BW28 inout 3.3-V LVCMOS
GPIO_D[28] BP31 inout 3.3-V LVCMOS
GPIO_D[29] BM22 inout 3.3-V LVCMOS
GPIO_D[30] BR31 inout 3.3-V LVCMOS
GPIO_D[31] BR28 inout 3.3-V LVCMOS
GPIO_D[32] BR22 inout 3.3-V LVCMOS
GPIO_D[33] BW19 inout 3.3-V LVCMOS
GPIO_D[34] BU22 inout 3.3-V LVCMOS
GPIO_D[35] CF12 inout 3.3-V LVCMOS

SMA
Name Location Direction IO Standard
SMA_CLKIN_p Y44 input 1.1-V TRUE DIFFERENTIAL SIGNALING

QTH
Name Location Direction IO Standard
QTH_30_p[0] BW89 inout 1.2-V
QTH_30_p[1] BE79 inout 1.2-V
QTH_30_p[2] BM81 inout 1.2-V
QTH_30_p[3] BH89 inout 1.2-V
QTH_30_p[4] BF93 inout 1.2-V
QTH_30_p[5] BE96 inout 1.2-V
QTH_30_p[6] BW78 inout 1.2-V
QTH_30_p[7] BK89 inout 1.2-V
QTH_30_p[8] BR78 inout 1.2-V
QTH_30_p[9] BP92 inout 1.2-V
QTH_30_p[10] BR81 inout 1.2-V
QTH_30_p[11] BF86 inout 1.2-V
QTH_30_p[12] BR89 inout 1.2-V
QTH_30_p[13] BF75 inout 1.2-V
QTH_30_p[14] BM78 inout 1.2-V
QTH_30_p[15] BH81 inout 1.2-V
QTH_30_n[0] CA89 inout 1.2-V
QTH_30_n[1] BE75 inout 1.2-V
QTH_30_n[2] BP81 inout 1.2-V
QTH_30_n[3] BH92 inout 1.2-V
QTH_30_n[4] BF90 inout 1.2-V
QTH_30_n[5] BE93 inout 1.2-V
QTH_30_n[6] CA78 inout 1.2-V
QTH_30_n[7] BM89 inout 1.2-V
QTH_30_n[8] BU78 inout 1.2-V
QTH_30_n[9] BM92 inout 1.2-V
QTH_30_n[10] BU81 inout 1.2-V
QTH_30_n[11] BE86 inout 1.2-V
QTH_30_n[12] BU89 inout 1.2-V
QTH_30_n[13] BF72 inout 1.2-V
QTH_30_n[14] BK78 inout 1.2-V
QTH_30_n[15] BH78 inout 1.2-V
QTH_30_D[0] BU92 inout 1.2-V
QTH_30_D[1] CK76 inout 1.2-V
QTH_30_D[2] CF59 inout 1.2-V
QTH_30_D[3] CF69 inout 1.2-V

PCIE
Name Location Direction IO Standard
PCIE_SMBCLK K8 inout 3.3-V LVCMOS
PCIE_SMBDAT D4 inout 3.3-V LVCMOS
PCIE_TX_p[0] BY7 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_p[1] BT7 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_p[2] BL7 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_p[3] BG7 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_n[0] BY10 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_n[1] BT10 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_n[2] BL10 output HIGH SPEED DIFFERENTIAL I/O
PCIE_TX_n[3] BG10 output HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_p[0] CB1 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_p[1] BV1 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_p[2] BN1 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_p[3] BJ1 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_n[0] CB3 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_n[1] BV3 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_n[2] BN3 input HIGH SPEED DIFFERENTIAL I/O
PCIE_RX_n[3] BJ3 input HIGH SPEED DIFFERENTIAL I/O
PCIE_REFCLK_p BC29 input CURRENT MODE LOGIC (CML)
PCIE_PERST_n BE29 input 3.3-V LVCMOS

QSFP
Name Location Direction IO Standard
QSFP_TX_p[0] BE7 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_p[1] BC7 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_p[2] BA7 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_p[3] AW7 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_n[0] BE10 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_n[1] BC10 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_n[2] BA10 output HIGH SPEED DIFFERENTIAL I/O
QSFP_TX_n[3] AW10 output HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_p[0] BF1 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_p[1] BD1 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_p[2] BB1 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_p[3] AY1 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_n[0] BF3 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_n[1] BD3 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_n[2] BB3 input HIGH SPEED DIFFERENTIAL I/O
QSFP_RX_n[3] AY3 input HIGH SPEED DIFFERENTIAL I/O
CIPRI_REFCLK_p AV16 input CURRENT MODE LOGIC (CML)
QSFP_REFCLK_p AY16 input CURRENT MODE LOGIC (CML)
QSFP_INTERRUPT_n J2 input 3.3-V LVCMOS
QSFP_LP_MODE G1 output 3.3-V LVCMOS
QSFP_MOD_PRS_n G2 input 3.3-V LVCMOS
QSFP_MOD_SEL_n F4 output 3.3-V LVCMOS
QSFP_RST_n H8 output 3.3-V LVCMOS
QSFP_SCL F18 inout 3.3-V LVCMOS
QSFP_SDA H27 inout 3.3-V LVCMOS

CAM
Name Location Direction IO Standard
CAM_RZQ1 BH69 input 1.2-V

CAM1
Name Location Direction IO Standard
CAM1_CLK_p CL88 input DPHY
CAM1_CLK_n CK88 input DPHY
CAM1_D_p[0] CL91 input DPHY
CAM1_D_p[1] CK97 input DPHY
CAM1_D_p[2] CK85 input DPHY
CAM1_D_p[3] CK80 input DPHY
CAM1_D_n[0] CK94 input DPHY
CAM1_D_n[1] CL97 input DPHY
CAM1_D_n[2] CL85 input DPHY
CAM1_D_n[3] CL82 input DPHY
CAM1_I2C_SCL C2 inout 3.3-V LVCMOS
CAM1_I2C_SDA F15 inout 3.3-V LVCMOS
CAM1_GPIO D24 inout 3.3-V LVCMOS

CAM2
Name Location Direction IO Standard
CAM2_CLK_p CH89 input DPHY
CAM2_CLK_n CF89 input DPHY
CAM2_D_p[0] CC92 input DPHY
CAM2_D_p[1] CF92 input DPHY
CAM2_D_p[2] CF81 input DPHY
CAM2_D_p[3] CA81 input DPHY
CAM2_D_n[0] CA92 input DPHY
CAM2_D_n[1] CH92 input DPHY
CAM2_D_n[2] CH81 input DPHY
CAM2_D_n[3] CC81 input DPHY
CAM2_I2C_SCL J1 inout 3.3-V LVCMOS
CAM2_I2C_SDA F27 inout 3.3-V LVCMOS
CAM2_GPIO F24 inout 3.3-V LVCMOS

GTSL1A
Name Location Direction IO Standard
GTSL1A_REFCLK_100M_p BB120 input CURRENT MODE LOGIC (CML)

GTSL1B
Name Location Direction IO Standard
GTSL1B_REFCLK_156M25_p AY120 input CURRENT MODE LOGIC (CML)

GTSL1C
Name Location Direction IO Standard
GTSL1C_REFCLK_100M_p AP120 input CURRENT MODE LOGIC (CML)

GTSR4A
Name Location Direction IO Standard
GTSR4A_REFCLK_148M5_p BB16 input CURRENT MODE LOGIC (CML)

GTSR4C
Name Location Direction IO Standard
GTSR4C_REFCLK_100M_p AT16 input CURRENT MODE LOGIC (CML)

HPS
Name Location Direction IO Standard
HPS_ENET_MDC D124 output 1.8-V
HPS_ENET_MDIO F124 inout 1.8-V
HPS_ENET_RX_CLK J135 input 1.8-V
HPS_ENET_RX_CTL AD135 input 1.8-V
HPS_ENET_RX_DATA[0] K132 input 1.8-V
HPS_ENET_RX_DATA[1] AG129 input 1.8-V
HPS_ENET_RX_DATA[2] G134 input 1.8-V
HPS_ENET_RX_DATA[3] G135 input 1.8-V
HPS_ENET_TX_CLK P132 output 1.8-V
HPS_ENET_TX_CTL L135 output 1.8-V
HPS_ENET_TX_DATA[0] M132 output 1.8-V
HPS_ENET_TX_DATA[1] AD134 output 1.8-V
HPS_ENET_TX_DATA[2] J134 output 1.8-V
HPS_ENET_TX_DATA[3] AG120 output 1.8-V
HPS_IOB_10 Y132 inout 1.8-V
HPS_IOB_11 T124 inout 1.8-V
HPS_IOB_12 P124 inout 1.8-V
HPS_IOB_13 M127 inout 1.8-V
HPS_IOB_14 K127 inout 1.8-V
HPS_IOB_19 H127 inout 1.8-V
HPS_IOB_20 AB124 inout 1.8-V
HPS_IOB_21 F127 inout 1.8-V
HPS_IOB_22 Y124 inout 1.8-V
HPS_IOB_9 T127 inout 1.8-V
HPS_KEY B134 inout 1.8-V
HPS_LED Y127 inout 1.8-V
HPS_LED2 K124 inout 1.8-V
HPS_OSC_CLK AG123 input 1.8-V
HPS_SDMMC_CLK D132 output 1.8-V
HPS_SDMMC_CMD AB132 inout 1.8-V
HPS_SDMMC_DATA[0] E135 inout 1.8-V
HPS_SDMMC_DATA[1] F132 inout 1.8-V
HPS_SDMMC_DATA[2] AA135 inout 1.8-V
HPS_SDMMC_DATA[3] V127 inout 1.8-V
HPS_UART_RX AB127 input 1.8-V
HPS_UART_TX M124 output 1.8-V
HPS_USB_CLK W135 input 1.8-V
HPS_USB_DATA[0] AK115 inout 1.8-V
HPS_USB_DATA[1] U134 inout 1.8-V
HPS_USB_DATA[2] R134 inout 1.8-V
HPS_USB_DATA[3] AG115 inout 1.8-V
HPS_USB_DATA[4] N135 inout 1.8-V
HPS_USB_DATA[5] AK120 inout 1.8-V
HPS_USB_DATA[6] N134 inout 1.8-V
HPS_USB_DATA[7] T132 inout 1.8-V
HPS_USB_DIR W134 input 1.8-V
HPS_USB_NXT AL120 input 1.8-V
HPS_USB_STP U135 output 1.8-V

INFO
Name Location Direction IO Standard
INFO_SPI_SCLK BF111 output 3.3-V LVCMOS
INFO_SPI_MISO BR109 input 3.3-V LVCMOS
INFO_SPI_MOSI BE115 output 3.3-V LVCMOS
INFO_SPI_CS_n BH109 output 3.3-V LVCMOS