tsn_subsys

2026.03.13.14:26:58 Datasheet
Overview

All Components
   intel_mge_phy_0 intel_mge_phy 9.0.0
   mm_bridge_0 altera_avalon_mm_bridge 20.1.0
   mm_bridge_1 altera_avalon_mm_bridge 20.1.0
   mm_bridge_2 altera_avalon_mm_bridge 20.1.0
   mm_bridge_3 altera_avalon_mm_bridge 20.1.0
   mm_bridge_4 altera_avalon_mm_bridge 20.1.0
   mm_bridge_5 altera_avalon_mm_bridge 20.1.0
   mm_bridge_6 altera_avalon_mm_bridge 20.1.0
Memory Map
axi_bridge_0 mm_bridge_0 mm_bridge_1 mm_bridge_2 mm_bridge_3 mm_bridge_4 mm_bridge_5 mm_bridge_6
 m0  m0  m0  m0  m0  m0  m0  m0
  axi_bridge_0
s0 
  intel_mge_phy_0
avalon_mm_csr  0x0002_0100 - 0x0002_013f 0x0000 - 0x003f
reconfig 
  mm_bridge_0
s0  0x0002_0300 - 0x0002_037f
  mm_bridge_1
s0  0x0002_0100 - 0x0002_013f
  mm_bridge_2
s0  0x0002_0140 - 0x0002_017f
  mm_bridge_3
s0  0x0002_0180 - 0x0002_01ff
  mm_bridge_4
s0  0x0002_0200 - 0x0002_02ff
  mm_bridge_5
s0  0x0002_0380 - 0x0002_03ff
  mm_bridge_6
s0  0x0002_0400 - 0x0002_07ff

axi_bridge_0

altera_axi_bridge v19.10.0
clock_bridge_0 out_clk   axi_bridge_0
  clk
reset_in out_reset  
  clk_reset
m0   mm_bridge_0
  s0
m0   mm_bridge_1
  s0
m0   mm_bridge_2
  s0
m0   mm_bridge_3
  s0
m0   mm_bridge_4
  s0
m0   mm_bridge_5
  s0
m0   mm_bridge_6
  s0


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_bridge_0

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_mge_phy_0

intel_mge_phy v9.0.0
mm_bridge_1 m0   intel_mge_phy_0
  avalon_mm_csr
intel_systemclk_gts_0 o_syspll_c0  
  i_system_pll_clk
clock_bridge_0 out_clk  
  csr_clk
out_clk  
  reconfig_clk
iopll_0 outclk0  
  latency_measure_clk
outclk1  
  latency_sclk
reset_in out_reset  
  reconfig_reset
reset_bridge_0 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_systemclk_gts_0

intel_systemclk_gts v5.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll_0

altera_iopll v21.0.0
clock_bridge_0 out_clk   iopll_0
  refclk
outclk0   intel_mge_phy_0
  latency_measure_clk
outclk1  
  latency_sclk


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_0

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_0
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_1

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_1
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset
m0   intel_mge_phy_0
  avalon_mm_csr


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_2

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_2
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_3

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_3
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_4

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_4
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_5

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_5
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

mm_bridge_6

altera_avalon_mm_bridge v20.1.0
axi_bridge_0 m0   mm_bridge_6
  s0
clock_bridge_0 out_clk  
  clk
reset_bridge_1 out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_bridge_0

altera_reset_bridge v19.2.0
clock_bridge_0 out_clk   reset_bridge_0
  clk
out_reset   intel_mge_phy_0
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_bridge_1

altera_reset_bridge v19.2.0
clock_bridge_0 out_clk   reset_bridge_1
  clk
out_reset   mm_bridge_0
  reset
out_reset   mm_bridge_1
  reset
out_reset   mm_bridge_2
  reset
out_reset   mm_bridge_3
  reset
out_reset   mm_bridge_4
  reset
out_reset   mm_bridge_5
  reset
out_reset   mm_bridge_6
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_bridge_0 out_clk   reset_in
  clk
out_reset   axi_bridge_0
  clk_reset
out_reset   intel_mge_phy_0
  reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_ip

altera_s10_user_rst_clkgate v19.4.9


Parameters

generateLegacySim false
  

Software Assignments

(none)
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