---

intel_mge_phy_0

intel_mge_phy v9.0.0

Parameters ETH_LAYER 0 PHY_IDENTIFIER 0 ENABLE_IEEE1588 1 ENABLE_SGMII 0 ENABLE_HVIO_PLL 0 refclk_recovery_en 0 ENABLE_GMII_ADAPTER 1 SPEED_VARIANT 0 DEFAULT_MODE 1 PMA_PLL_REFCLK 0 syspll_outclk_freq_mhz 2 EXT_PHY_MGBASET 1 EXT_PHY_NBASET 0 tx_spread_spectrum_en DISABLE tx_invert_pin DISABLE ux_txeq_post_tap_1 5 ux_txeq_main_tap 52 ux_txeq_pre_tap_1 0 ux_txeq_pre_tap_2 0 rx_adaptation_mode manual rx_invert_pin DISABLE rx_external_couple_type AC rx_termination_mode GROUNDED rx_onchip_termination R_2 rxeq_vga_gain 0 rxeq_hf_boost 0 rxeq_dfe_tap_1 0 prof0_tx_spread_spectrum_en DISABLE prof0_tx_invert_pin DISABLE prof0_ux_txeq_post_tap_1 5 prof0_ux_txeq_main_tap 52 prof0_ux_txeq_pre_tap_1 0 prof0_ux_txeq_pre_tap_2 0 prof0_rx_adaptation_mode auto prof0_rx_invert_pin DISABLE prof0_rx_external_couple_type AC prof0_rx_onchip_termination R_2 prof1_tx_spread_spectrum_en DISABLE prof1_tx_invert_pin DISABLE prof1_ux_txeq_post_tap_1 5 prof1_ux_txeq_main_tap 52 prof1_ux_txeq_pre_tap_1 0 prof1_ux_txeq_pre_tap_2 0 prof1_rx_adaptation_mode auto prof1_rx_invert_pin DISABLE prof1_rx_external_couple_type AC prof1_rx_onchip_termination R_2 prof2_tx_spread_spectrum_en DISABLE prof2_tx_invert_pin DISABLE prof2_ux_txeq_post_tap_1 5 prof2_ux_txeq_main_tap 52 prof2_ux_txeq_pre_tap_1 0 prof2_ux_txeq_pre_tap_2 0 prof2_rx_adaptation_mode auto prof2_rx_invert_pin DISABLE prof2_rx_external_couple_type AC prof2_rx_onchip_termination R_2 prof3_tx_spread_spectrum_en DISABLE prof3_tx_invert_pin DISABLE prof3_ux_txeq_post_tap_1 5 prof3_ux_txeq_main_tap 52 prof3_ux_txeq_pre_tap_1 0 prof3_ux_txeq_pre_tap_2 0 prof3_rx_adaptation_mode auto prof3_rx_invert_pin DISABLE prof3_rx_external_couple_type AC prof3_rx_onchip_termination R_2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_mge_pcs

intel_mge_phy_pcs v1.0.0

Parameters PHY_IDENTIFIER 0 ENABLE_IEEE1588 1 ENABLE_SGMII 0 ENABLE_GMII_ADAPTER 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_xcvr_term

intel_mge_phy_xcvr_term v1.0.0

Parameters ENABLE_IEEE1588 1 ENABLE_GMII_ADAPTER 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_alt_mge_xcvr_directphy

intel_directphy_gts v11.0.0

Parameters tx_pll_fout_hz 1562.500000 tx_pll_vco_MHz 12500.000000 tx_pll_cascade_enable 0 tx_pll_frac_mode_enable 0 tx_pll_realtime_lock_enable 0 tx_pll_refclk_freq_mhz 156.250000 tx_pll_refclk_freq_itxt 156.250000 rx_pll_fout_hz 1562.500000 rx_pll_vco_MHz 12500.000000 rx_pll_refclk_freq_mhz 156.250000 refclk_recovery_en 0 mode_directphy mode_dphygen rcfg_group lanes-1 duplex_mode_rphy duplex fec_en_rphy 0 custom_pcs_en_rphy 0 syspll_outclk_freq_mhz_rphy 322.265625 hvio_pll_enable_rphy 0 num_of_sec_profiles 1 protocol_mode DISABLED num_xcvr_per_sys 1 clocking_mode syspll syspll_outclk_freq_mhz 322.265625 duplex_mode duplex ed_sel None ed_ack 0 ed_hdl_sel Verilog ed_board None pma_data_rate 3125 pma_outclk_freq_mhz 156.25 pma_width 20 enable_split_interface 0 custom_pcs_en 0 custom_pcs_mode IEEE MII Interface enable_refclock_to_core 0 serdes_lpbk_mode LOOPBACK_MODE_DISABLED tx_serdes_prbs_gen_mode DISABLE tx_pll_txuserclk_div 100 tx_pll_txuserclk_freq_mhz 125.0 rx_serdes_prbs_mon_mode DISABLE enable_port_rx_cdr_divclk_link0 0 hvio_pll_enable 0 rx_cdr_lock_mode auto enable_port_rx_set_locktoref 0 enable_port_rx_set_locktodata 0 rx_cdr_rxuserclk_div 40 rx_cdr_rxuserclk_freq_mhz 312.5 pmaif_tx_fifo_mode_s elastic enable_port_tx_pmaif_fifo_empty 0 enable_port_tx_pmaif_fifo_pempty 0 enable_port_tx_pmaif_fifo_pfull 0 pmaif_rx_fifo_mode_s elastic enable_port_rx_pmaif_fifo_empty 0 enable_port_rx_pmaif_fifo_pempty 0 enable_port_rx_pmaif_fifo_pfull 0 fec_en 0 l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) fec_lpbk_en 0 l_av1_enable 1 avmm1_soft_csr_enable 1 avmm1_readdv_enable 1 avmm1_split 0 avmm1_jtag_enable 0 l_av1_enable_rphy 0 avmm1_soft_csr_enable_rphy 0 avmm1_readdv_enable_rphy 1 avmm1_jtag_enable_rphy 0 enable_port_latency_measurement 1 ch_rx_dl_rx_lat_bit_for_async 0 ch_rx_dl_rxbit_cntr_pma DISABLE ch_rx_dl_rxbit_rollover 5280 prof0_rcfg_subset 1xG-1 prof0_use_profile_startup 1 prof0_pmaif_tx_fifo_mode_s elastic prof0_enable_port_tx_pmaif_fifo_empty 0 prof0_enable_port_tx_pmaif_fifo_pempty 0 prof0_enable_port_tx_pmaif_fifo_pfull 0 prof0_tx_pll_txuserclk_div 100 prof0_tx_pll_txuserclk_freq_mhz 103.125 prof0_pmaif_rx_fifo_mode_s elastic prof0_enable_port_rx_pmaif_fifo_empty 0 prof0_enable_port_rx_pmaif_fifo_pempty 0 prof0_enable_port_rx_pmaif_fifo_pfull 0 prof0_rx_cdr_rxuserclk_div 100 prof0_rx_cdr_rxuserclk_freq_mhz 103.125 prof0_fec_en 0 prof0_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof0_custom_pcs_en 0 prof0_custom_pcs_mode IEEE MII Interface prof0_tx_pll_fout_hz 5156.250000 prof0_tx_pll_vco_MHz 10312.500000 prof0_tx_pll_cascade_enable 0 prof0_tx_pll_frac_mode_enable 0 prof0_tx_pll_realtime_lock_enable 0 prof0_tx_pll_refclk_freq_mhz 156.250000 prof0_tx_pll_refclk_freq_itxt 156.250000 prof0_rx_pll_fout_hz 5156.250000 prof0_rx_pll_vco_MHz 10312.500000 prof0_rx_pll_refclk_freq_mhz 156.250000 prof0_enable_port_rx_cdr_divclk_link0 0 prof0_rx_cdr_lock_mode auto prof0_enable_port_rx_set_locktoref 0 prof0_enable_port_rx_set_locktodata 0 prof0_enable_port_latency_measurement 0 prof0_ch_rx_dl_rx_lat_bit_for_async 0 prof0_ch_rx_dl_rxbit_cntr_pma DISABLE prof0_ch_rx_dl_rxbit_rollover 0 prof1_tx_pll_fout_hz 5156.250000 prof1_tx_pll_vco_MHz 10312.500000 prof1_tx_pll_cascade_enable 0 prof1_tx_pll_frac_mode_enable 0 prof1_tx_pll_realtime_lock_enable 0 prof1_tx_pll_refclk_freq_mhz 156.250000 prof1_tx_pll_refclk_freq_itxt 156.250000 prof1_rx_pll_fout_hz 5156.250000 prof1_rx_pll_vco_MHz 10312.500000 prof1_rx_pll_refclk_freq_mhz 156.250000 prof2_tx_pll_fout_hz prof2_tx_pll_vco_MHz prof2_tx_pll_cascade_enable 0 prof2_tx_pll_frac_mode_enable 0 prof2_tx_pll_realtime_lock_enable 0 prof2_tx_pll_refclk_freq_mhz 156.250000 prof2_tx_pll_refclk_freq_itxt 156.250000 prof2_rx_pll_fout_hz 0 prof2_rx_pll_vco_MHz prof2_rx_pll_refclk_freq_mhz 156.250000 prof3_tx_pll_fout_hz prof3_tx_pll_vco_MHz prof3_tx_pll_cascade_enable 0 prof3_tx_pll_frac_mode_enable 0 prof3_tx_pll_realtime_lock_enable 0 prof3_tx_pll_refclk_freq_mhz 156.250000 prof3_tx_pll_refclk_freq_itxt 156.250000 prof3_rx_pll_fout_hz 0 prof3_rx_pll_vco_MHz prof3_rx_pll_refclk_freq_mhz 156.250000 prof4_tx_pll_fout_hz prof4_tx_pll_vco_MHz prof4_tx_pll_cascade_enable 0 prof4_tx_pll_frac_mode_enable 0 prof4_tx_pll_realtime_lock_enable 0 prof4_tx_pll_refclk_freq_mhz 156.250000 prof4_tx_pll_refclk_freq_itxt 156.250000 prof4_rx_pll_fout_hz 0 prof4_rx_pll_vco_MHz prof4_rx_pll_refclk_freq_mhz 156.250000 prof5_tx_pll_fout_hz prof5_tx_pll_vco_MHz prof5_tx_pll_cascade_enable 0 prof5_tx_pll_frac_mode_enable 0 prof5_tx_pll_realtime_lock_enable 0 prof5_tx_pll_refclk_freq_mhz 156.250000 prof5_tx_pll_refclk_freq_itxt 156.250000 prof5_rx_pll_fout_hz 0 prof5_rx_pll_vco_MHz prof5_rx_pll_refclk_freq_mhz 156.250000 prof6_tx_pll_fout_hz prof6_tx_pll_vco_MHz prof6_tx_pll_cascade_enable 0 prof6_tx_pll_frac_mode_enable 0 prof6_tx_pll_realtime_lock_enable 0 prof6_tx_pll_refclk_freq_mhz 156.250000 prof6_tx_pll_refclk_freq_itxt 156.250000 prof6_rx_pll_fout_hz 0 prof6_rx_pll_vco_MHz prof6_rx_pll_refclk_freq_mhz 156.250000 prof7_tx_pll_fout_hz prof7_tx_pll_vco_MHz prof7_tx_pll_cascade_enable 0 prof7_tx_pll_frac_mode_enable 0 prof7_tx_pll_realtime_lock_enable 0 prof7_tx_pll_refclk_freq_mhz 156.250000 prof7_tx_pll_refclk_freq_itxt 156.250000 prof7_rx_pll_fout_hz 0 prof7_rx_pll_vco_MHz prof7_rx_pll_refclk_freq_mhz 156.250000 prof8_tx_pll_fout_hz prof8_tx_pll_vco_MHz prof8_tx_pll_cascade_enable 0 prof8_tx_pll_frac_mode_enable 0 prof8_tx_pll_realtime_lock_enable 0 prof8_tx_pll_refclk_freq_mhz 156.250000 prof8_tx_pll_refclk_freq_itxt 156.250000 prof8_rx_pll_fout_hz 0 prof8_rx_pll_vco_MHz prof8_rx_pll_refclk_freq_mhz 156.250000 prof9_tx_pll_fout_hz prof9_tx_pll_vco_MHz prof9_tx_pll_cascade_enable 0 prof9_tx_pll_frac_mode_enable 0 prof9_tx_pll_realtime_lock_enable 0 prof9_tx_pll_refclk_freq_mhz 156.250000 prof9_tx_pll_refclk_freq_itxt 156.250000 prof9_rx_pll_fout_hz 0 prof9_rx_pll_vco_MHz prof9_rx_pll_refclk_freq_mhz 156.250000 prof10_tx_pll_fout_hz prof10_tx_pll_vco_MHz prof10_tx_pll_cascade_enable 0 prof10_tx_pll_frac_mode_enable 0 prof10_tx_pll_realtime_lock_enable 0 prof10_tx_pll_refclk_freq_mhz 156.250000 prof10_tx_pll_refclk_freq_itxt 156.250000 prof10_rx_pll_fout_hz 0 prof10_rx_pll_vco_MHz prof10_rx_pll_refclk_freq_mhz 156.250000 prof11_tx_pll_fout_hz prof11_tx_pll_vco_MHz prof11_tx_pll_cascade_enable 0 prof11_tx_pll_frac_mode_enable 0 prof11_tx_pll_realtime_lock_enable 0 prof11_tx_pll_refclk_freq_mhz 156.250000 prof11_tx_pll_refclk_freq_itxt 156.250000 prof11_rx_pll_fout_hz 0 prof11_rx_pll_vco_MHz prof11_rx_pll_refclk_freq_mhz 156.250000 prof1_rcfg_subset 1xG-1 prof1_use_profile_startup 0 prof1_tx_pll_txuserclk_div 100 prof1_tx_pll_txuserclk_freq_mhz 103.125 prof1_rx_cdr_rxuserclk_div 100 prof1_rx_cdr_rxuserclk_freq_mhz 103.125 prof1_fec_en 0 prof1_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof1_custom_pcs_en 0 prof1_custom_pcs_mode IEEE MII Interface prof1_pma_secondary_profile_refclk_en 0 prof1_rx_cdr_lock_mode auto prof1_ch_rx_dl_rx_lat_bit_for_async 0 prof1_ch_rx_dl_rxbit_cntr_pma DISABLE prof1_ch_rx_dl_rxbit_rollover 0 prof2_rcfg_subset 1xG-1 prof2_use_profile_startup 0 prof2_tx_pll_txuserclk_div 100 prof2_tx_pll_txuserclk_freq_mhz Disabled prof2_rx_cdr_rxuserclk_div 100 prof2_rx_cdr_rxuserclk_freq_mhz prof2_fec_en 0 prof2_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof2_custom_pcs_en 0 prof2_custom_pcs_mode IEEE MII Interface prof2_pma_secondary_profile_refclk_en 0 prof2_rx_cdr_lock_mode auto prof2_ch_rx_dl_rx_lat_bit_for_async 0 prof2_ch_rx_dl_rxbit_cntr_pma DISABLE prof2_ch_rx_dl_rxbit_rollover 0 prof3_rcfg_subset 1xG-1 prof3_use_profile_startup 0 prof3_tx_pll_txuserclk_div 100 prof3_tx_pll_txuserclk_freq_mhz Disabled prof3_rx_cdr_rxuserclk_div 100 prof3_rx_cdr_rxuserclk_freq_mhz prof3_fec_en 0 prof3_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof3_custom_pcs_en 0 prof3_custom_pcs_mode IEEE MII Interface prof3_pma_secondary_profile_refclk_en 0 prof3_rx_cdr_lock_mode auto prof3_ch_rx_dl_rx_lat_bit_for_async 0 prof3_ch_rx_dl_rxbit_cntr_pma DISABLE prof3_ch_rx_dl_rxbit_rollover 0 prof4_rcfg_subset 1xG-1 prof4_use_profile_startup 0 prof4_tx_pll_txuserclk_div 100 prof4_tx_pll_txuserclk_freq_mhz Disabled prof4_rx_cdr_rxuserclk_div 100 prof4_rx_cdr_rxuserclk_freq_mhz prof4_fec_en 0 prof4_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof4_custom_pcs_en 0 prof4_custom_pcs_mode IEEE MII Interface prof4_pma_secondary_profile_refclk_en 0 prof4_rx_cdr_lock_mode auto prof4_ch_rx_dl_rx_lat_bit_for_async 0 prof4_ch_rx_dl_rxbit_cntr_pma DISABLE prof4_ch_rx_dl_rxbit_rollover 0 prof5_rcfg_subset 1xG-1 prof5_use_profile_startup 0 prof5_tx_pll_txuserclk_div 100 prof5_tx_pll_txuserclk_freq_mhz Disabled prof5_rx_cdr_rxuserclk_div 100 prof5_rx_cdr_rxuserclk_freq_mhz prof5_fec_en 0 prof5_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof5_custom_pcs_en 0 prof5_custom_pcs_mode IEEE MII Interface prof5_pma_secondary_profile_refclk_en 0 prof5_rx_cdr_lock_mode auto prof5_ch_rx_dl_rx_lat_bit_for_async 0 prof5_ch_rx_dl_rxbit_cntr_pma DISABLE prof5_ch_rx_dl_rxbit_rollover 0 prof6_rcfg_subset 1xG-1 prof6_use_profile_startup 0 prof6_tx_pll_txuserclk_div 100 prof6_tx_pll_txuserclk_freq_mhz Disabled prof6_rx_cdr_rxuserclk_div 100 prof6_rx_cdr_rxuserclk_freq_mhz prof6_fec_en 0 prof6_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof6_custom_pcs_en 0 prof6_custom_pcs_mode IEEE MII Interface prof6_pma_secondary_profile_refclk_en 0 prof6_rx_cdr_lock_mode auto prof6_ch_rx_dl_rx_lat_bit_for_async 0 prof6_ch_rx_dl_rxbit_cntr_pma DISABLE prof6_ch_rx_dl_rxbit_rollover 0 prof7_rcfg_subset 1xG-1 prof7_use_profile_startup 0 prof7_tx_pll_txuserclk_div 100 prof7_tx_pll_txuserclk_freq_mhz Disabled prof7_rx_cdr_rxuserclk_div 100 prof7_rx_cdr_rxuserclk_freq_mhz prof7_fec_en 0 prof7_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof7_custom_pcs_en 0 prof7_custom_pcs_mode IEEE MII Interface prof7_pma_secondary_profile_refclk_en 0 prof7_rx_cdr_lock_mode auto prof7_ch_rx_dl_rx_lat_bit_for_async 0 prof7_ch_rx_dl_rxbit_cntr_pma DISABLE prof7_ch_rx_dl_rxbit_rollover 0 prof8_rcfg_subset 1xG-1 prof8_use_profile_startup 0 prof8_tx_pll_txuserclk_div 100 prof8_tx_pll_txuserclk_freq_mhz Disabled prof8_rx_cdr_rxuserclk_div 100 prof8_rx_cdr_rxuserclk_freq_mhz prof8_fec_en 0 prof8_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof8_custom_pcs_en 0 prof8_custom_pcs_mode IEEE MII Interface prof8_pma_secondary_profile_refclk_en 0 prof8_rx_cdr_lock_mode auto prof8_ch_rx_dl_rx_lat_bit_for_async 0 prof8_ch_rx_dl_rxbit_cntr_pma DISABLE prof8_ch_rx_dl_rxbit_rollover 0 prof9_rcfg_subset 1xG-1 prof9_use_profile_startup 0 prof9_tx_pll_txuserclk_div 100 prof9_tx_pll_txuserclk_freq_mhz Disabled prof9_rx_cdr_rxuserclk_div 100 prof9_rx_cdr_rxuserclk_freq_mhz prof9_fec_en 0 prof9_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof9_custom_pcs_en 0 prof9_custom_pcs_mode IEEE MII Interface prof9_pma_secondary_profile_refclk_en 0 prof9_rx_cdr_lock_mode auto prof9_ch_rx_dl_rx_lat_bit_for_async 0 prof9_ch_rx_dl_rxbit_cntr_pma DISABLE prof9_ch_rx_dl_rxbit_rollover 0 prof10_rcfg_subset 1xG-1 prof10_use_profile_startup 0 prof10_tx_pll_txuserclk_div 100 prof10_tx_pll_txuserclk_freq_mhz Disabled prof10_rx_cdr_rxuserclk_div 100 prof10_rx_cdr_rxuserclk_freq_mhz prof10_fec_en 0 prof10_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof10_custom_pcs_en 0 prof10_custom_pcs_mode IEEE MII Interface prof10_pma_secondary_profile_refclk_en 0 prof10_rx_cdr_lock_mode auto prof10_ch_rx_dl_rx_lat_bit_for_async 0 prof10_ch_rx_dl_rxbit_cntr_pma DISABLE prof10_ch_rx_dl_rxbit_rollover 0 prof11_rcfg_subset 1xG-1 prof11_use_profile_startup 0 prof11_tx_pll_txuserclk_div 100 prof11_tx_pll_txuserclk_freq_mhz Disabled prof11_rx_cdr_rxuserclk_div 100 prof11_rx_cdr_rxuserclk_freq_mhz prof11_fec_en 0 prof11_l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74) prof11_custom_pcs_en 0 prof11_custom_pcs_mode IEEE MII Interface prof11_pma_secondary_profile_refclk_en 0 prof11_rx_cdr_lock_mode auto prof11_ch_rx_dl_rx_lat_bit_for_async 0 prof11_ch_rx_dl_rxbit_cntr_pma DISABLE prof11_ch_rx_dl_rxbit_rollover 0 tx_custom_cadence_enable 0 enable_port_tx_cadence_slow_clk_locked 0 pldif_tx_fifo_mode phase_comp pldif_tx_double_width_transfer_enable 1 enable_port_tx_fifo_full 0 enable_port_tx_fifo_empty 0 enable_port_tx_fifo_pfull 0 enable_port_tx_fifo_pempty 0 pldif_tx_clkout_sel PLL_DIV1 pldif_tx_clkout_div 2 pldif_tx_clkout_freq_mhz 161.132812 enable_port_tx_clkout2 1 pldif_tx_clkout2_sel TX_WORD_CLK pldif_tx_clkout2_div 1 pldif_tx_clkout2_freq_mhz 156.25 pldif_rx_fifo_mode phase_comp pldif_rx_double_width_transfer_enable 1 enable_port_rx_fifo_full 0 enable_port_rx_fifo_empty 0 enable_port_rx_fifo_pfull 0 enable_port_rx_fifo_pempty 0 enable_port_rx_fifo_rd_en 0 pldif_rx_clkout_sel RX_WORD_CLK pldif_rx_clkout_div 1 pldif_rx_clkout_freq_mhz 156.25 enable_port_rx_clkout2 1 pldif_rx_clkout2_sel RX_USER_CLK1 pldif_rx_clkout2_div 1 pldif_rx_clkout2_freq_mhz 312.5 prof0_tx_custom_cadence_enable 0 prof0_enable_port_tx_cadence_slow_clk_locked 0 prof0_pldif_tx_fifo_mode phase_comp prof0_enable_port_tx_fifo_full 0 prof0_enable_port_tx_fifo_empty 0 prof0_enable_port_tx_fifo_pfull 0 prof0_enable_port_tx_fifo_pempty 0 prof0_pldif_tx_clkout_sel PLL_DIV1 prof0_pldif_tx_clkout_div 2 prof0_pldif_tx_clkout_freq_mhz 161.132812 prof0_enable_port_tx_clkout2 0 prof0_pldif_rx_fifo_mode phase_comp prof0_enable_port_rx_fifo_full 0 prof0_enable_port_rx_fifo_empty 0 prof0_enable_port_rx_fifo_pfull 0 prof0_enable_port_rx_fifo_pempty 0 prof0_enable_port_rx_fifo_rd_en 0 prof0_pldif_rx_clkout_sel PLL_DIV1 prof0_pldif_rx_clkout_div 2 prof0_pldif_rx_clkout_freq_mhz 161.132812 prof0_enable_port_rx_clkout2 0 prof1_pldif_tx_clkout_sel PLL_DIV1 prof1_pldif_tx_clkout_div 2 prof1_pldif_tx_clkout_freq_mhz 161.132812 prof1_pldif_rx_clkout_sel PLL_DIV1 prof1_pldif_rx_clkout_div 2 prof1_pldif_rx_clkout_freq_mhz 161.132812 prof2_pldif_tx_clkout_sel PLL_DIV1 prof2_pldif_tx_clkout_div 2 prof2_pldif_tx_clkout_freq_mhz prof2_pldif_rx_clkout_sel PLL_DIV1 prof2_pldif_rx_clkout_div 2 prof2_pldif_rx_clkout_freq_mhz prof3_pldif_tx_clkout_sel PLL_DIV1 prof3_pldif_tx_clkout_div 2 prof3_pldif_tx_clkout_freq_mhz prof3_pldif_rx_clkout_sel PLL_DIV1 prof3_pldif_rx_clkout_div 2 prof3_pldif_rx_clkout_freq_mhz prof4_pldif_tx_clkout_sel PLL_DIV1 prof4_pldif_tx_clkout_div 2 prof4_pldif_tx_clkout_freq_mhz prof4_pldif_rx_clkout_sel PLL_DIV1 prof4_pldif_rx_clkout_div 2 prof4_pldif_rx_clkout_freq_mhz prof5_pldif_tx_clkout_sel PLL_DIV1 prof5_pldif_tx_clkout_div 2 prof5_pldif_tx_clkout_freq_mhz prof5_pldif_rx_clkout_sel PLL_DIV1 prof5_pldif_rx_clkout_div 2 prof5_pldif_rx_clkout_freq_mhz prof6_pldif_tx_clkout_sel PLL_DIV1 prof6_pldif_tx_clkout_div 2 prof6_pldif_tx_clkout_freq_mhz prof6_pldif_rx_clkout_sel PLL_DIV1 prof6_pldif_rx_clkout_div 2 prof6_pldif_rx_clkout_freq_mhz prof7_pldif_tx_clkout_sel PLL_DIV1 prof7_pldif_tx_clkout_div 2 prof7_pldif_tx_clkout_freq_mhz prof7_pldif_rx_clkout_sel PLL_DIV1 prof7_pldif_rx_clkout_div 2 prof7_pldif_rx_clkout_freq_mhz prof8_pldif_tx_clkout_sel PLL_DIV1 prof8_pldif_tx_clkout_div 2 prof8_pldif_tx_clkout_freq_mhz prof8_pldif_rx_clkout_sel PLL_DIV1 prof8_pldif_rx_clkout_div 2 prof8_pldif_rx_clkout_freq_mhz prof9_pldif_tx_clkout_sel PLL_DIV1 prof9_pldif_tx_clkout_div 2 prof9_pldif_tx_clkout_freq_mhz prof9_pldif_rx_clkout_sel PLL_DIV1 prof9_pldif_rx_clkout_div 2 prof9_pldif_rx_clkout_freq_mhz prof10_pldif_tx_clkout_sel PLL_DIV1 prof10_pldif_tx_clkout_div 2 prof10_pldif_tx_clkout_freq_mhz prof10_pldif_rx_clkout_sel PLL_DIV1 prof10_pldif_rx_clkout_div 2 prof10_pldif_rx_clkout_freq_mhz prof11_pldif_tx_clkout_sel PLL_DIV1 prof11_pldif_tx_clkout_div 2 prof11_pldif_tx_clkout_freq_mhz prof11_pldif_rx_clkout_sel PLL_DIV1 prof11_pldif_rx_clkout_div 2 prof11_pldif_rx_clkout_freq_mhz tx_spread_spectrum_en DISABLE tx_invert_pin DISABLE ux_txeq_post_tap_1 5 ux_txeq_main_tap 52 ux_txeq_pre_tap_1 0 ux_txeq_pre_tap_2 0 rx_adaptation_mode manual rx_invert_pin DISABLE rx_external_couple_type AC rx_termination_mode GROUNDED rx_onchip_termination R_2 rxeq_vga_gain 0 rxeq_hf_boost 0 rxeq_dfe_tap_1 0 prof0_tx_spread_spectrum_en DISABLE prof0_tx_invert_pin DISABLE prof0_ux_txeq_post_tap_1 0 prof0_ux_txeq_main_tap 55 prof0_ux_txeq_pre_tap_1 0 prof0_ux_txeq_pre_tap_2 0 prof0_rx_adaptation_mode auto prof0_rx_invert_pin DISABLE prof0_rx_external_couple_type AC prof0_rx_onchip_termination R_2 prof1_tx_spread_spectrum_en DISABLE prof1_tx_invert_pin DISABLE prof1_ux_txeq_post_tap_1 0 prof1_ux_txeq_main_tap 55 prof1_ux_txeq_pre_tap_1 0 prof1_ux_txeq_pre_tap_2 0 prof1_rx_adaptation_mode auto prof1_rx_invert_pin DISABLE prof1_rx_external_couple_type AC prof1_rx_onchip_termination R_2 prof2_tx_spread_spectrum_en DISABLE prof2_tx_invert_pin DISABLE prof2_ux_txeq_post_tap_1 0 prof2_ux_txeq_main_tap 55 prof2_ux_txeq_pre_tap_1 0 prof2_ux_txeq_pre_tap_2 0 prof2_rx_adaptation_mode auto prof2_rx_invert_pin DISABLE prof2_rx_external_couple_type AC prof2_rx_onchip_termination R_2 prof3_tx_spread_spectrum_en DISABLE prof3_tx_invert_pin DISABLE prof3_ux_txeq_post_tap_1 0 prof3_ux_txeq_main_tap 55 prof3_ux_txeq_pre_tap_1 0 prof3_ux_txeq_pre_tap_2 0 prof3_rx_adaptation_mode auto prof3_rx_invert_pin DISABLE prof3_rx_external_couple_type AC prof3_rx_onchip_termination R_2 prof4_tx_spread_spectrum_en DISABLE prof4_tx_invert_pin DISABLE prof4_ux_txeq_post_tap_1 0 prof4_ux_txeq_main_tap 55 prof4_ux_txeq_pre_tap_1 0 prof4_ux_txeq_pre_tap_2 0 prof4_rx_adaptation_mode auto prof4_rx_invert_pin DISABLE prof4_rx_external_couple_type AC prof4_rx_onchip_termination R_2 prof5_tx_spread_spectrum_en DISABLE prof5_tx_invert_pin DISABLE prof5_ux_txeq_post_tap_1 0 prof5_ux_txeq_main_tap 55 prof5_ux_txeq_pre_tap_1 0 prof5_ux_txeq_pre_tap_2 0 prof5_rx_adaptation_mode auto prof5_rx_invert_pin DISABLE prof5_rx_external_couple_type AC prof5_rx_onchip_termination R_2 prof6_tx_spread_spectrum_en DISABLE prof6_tx_invert_pin DISABLE prof6_ux_txeq_post_tap_1 0 prof6_ux_txeq_main_tap 55 prof6_ux_txeq_pre_tap_1 0 prof6_ux_txeq_pre_tap_2 0 prof6_rx_adaptation_mode auto prof6_rx_invert_pin DISABLE prof6_rx_external_couple_type AC prof6_rx_onchip_termination R_2 prof7_tx_spread_spectrum_en DISABLE prof7_tx_invert_pin DISABLE prof7_ux_txeq_post_tap_1 0 prof7_ux_txeq_main_tap 55 prof7_ux_txeq_pre_tap_1 0 prof7_ux_txeq_pre_tap_2 0 prof7_rx_adaptation_mode auto prof7_rx_invert_pin DISABLE prof7_rx_external_couple_type AC prof7_rx_onchip_termination R_2 prof8_tx_spread_spectrum_en DISABLE prof8_tx_invert_pin DISABLE prof8_ux_txeq_post_tap_1 0 prof8_ux_txeq_main_tap 55 prof8_ux_txeq_pre_tap_1 0 prof8_ux_txeq_pre_tap_2 0 prof8_rx_adaptation_mode auto prof8_rx_invert_pin DISABLE prof8_rx_external_couple_type AC prof8_rx_onchip_termination R_2 prof9_tx_spread_spectrum_en DISABLE prof9_tx_invert_pin DISABLE prof9_ux_txeq_post_tap_1 0 prof9_ux_txeq_main_tap 55 prof9_ux_txeq_pre_tap_1 0 prof9_ux_txeq_pre_tap_2 0 prof9_rx_adaptation_mode auto prof9_rx_invert_pin DISABLE prof9_rx_external_couple_type AC prof9_rx_onchip_termination R_2 prof10_tx_spread_spectrum_en DISABLE prof10_tx_invert_pin DISABLE prof10_ux_txeq_post_tap_1 0 prof10_ux_txeq_main_tap 55 prof10_ux_txeq_pre_tap_1 0 prof10_ux_txeq_pre_tap_2 0 prof10_rx_adaptation_mode auto prof10_rx_invert_pin DISABLE prof10_rx_external_couple_type AC prof10_rx_onchip_termination R_2 prof11_tx_spread_spectrum_en DISABLE prof11_tx_invert_pin DISABLE prof11_ux_txeq_post_tap_1 0 prof11_ux_txeq_main_tap 55 prof11_ux_txeq_pre_tap_1 0 prof11_ux_txeq_pre_tap_2 0 prof11_rx_adaptation_mode auto prof11_rx_invert_pin DISABLE prof11_rx_external_couple_type AC prof11_rx_onchip_termination R_2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_alt_mge_xcvr_directphy_dphy_adme

intel_directphy_gts_intel_adme_gts v11.0.0

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_alt_mge_xcvr_directphy_dphy_adme_dphy_adme

intel_adme_gts v1.0.0

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_alt_mge_xcvr_directphy_n_channel_superset_top_wrapper

intel_directphy_gts_n_channel_superset v11.0.0

Parameters num_of_lanes 1 relative_index 0 dr_enable DR_ENABLED SRC_SIM_SCALE_DOWN 0 device_die_type MAIN_SM7 device_die_revisions MAIN_SM7_REVB mac_use_case 0 hide_ptp_atoms FALSE mode_ethernet REFCLK_RECOVERY_EN 0 ch0_lane_id 0 ch0_fec_clk_en DISABLE ch0_tx_channel_mode PMAD ch0_rx_channel_mode PMAD ch0_duplex_mode DUPLEX ch0_rate_mode RATE_25G ch0_ptp_mode DISABLED ch0_fec_mode 0 ch0_tx_dl_enable ENABLE ch0_rx_dl_enable ENABLE ch0_sup_mode USER_MODE ch0_sim_mode ENABLE ch0_syspll_rx_clk_hz 322265625 ch0_syspll_tx_clk_hz 322265625 ch0_tx_user1_clk_dynamic_mux PLL_C0 ch0_tx_user2_clk_dynamic_mux WORD_CLK ch0_rx_user1_clk_dynamic_mux WORD_CLK ch0_rx_user2_clk_dynamic_mux POSTDIV_CLK ch0_tx_bond_size 1 ch0_rx_bond_size 1 ch0_xcvr_tx_protocol_hint DISABLED ch0_xcvr_tx_datarate_bps 3125 ch0_xcvr_tx_prbs_pattern DISABLE ch0_xcvr_tx_user_clk_only_mode DISABLE ch0_xcvr_tx_width 20 ch0_xcvr_rx_protocol_hint DISABLED ch0_xcvr_rx_datarate_bps 3125 ch0_xcvr_rx_prbs_pattern DISABLE ch0_xcvr_rx_width 20 ch0_xcvr_rx_force_cdr_ltr FALSE ch0_xcvr_rx_adaptation_mode DISABLED ch0_xcvr_rx_adaptation_mode_hw MANUAL_ADAPTATION ch0_xcvr_cdr_f_ref_hz 156250000 ch0_xcvr_cdr_f_vco_hz 1562500000 ch0_rx_postdiv_clk_en ENABLE ch0_rx_postdiv_clk_divider 40 ch0_tx_postdiv_clk_divider 100 ch0_tx_pll_f_ref_hz 156250000 ch0_tx_pll_f_out_hz 1562500000 ch0_dpma_f_ref_hz 250000000 ch0_tx_pll_refclk_select GLOBAL_REFCLK0 ch0_cdr_refclk_select GLOBAL_REFCLK1 ch0_phy_loopback_mode DISABLED ch0_flux_mode FLUX_MODE_BYPASS ch0_flux_mode_hw FLUX_MODE_BYPASS ch0_xcvrif_tx_fifo_mode ELASTIC ch0_xcvrif_rx_fifo_mode ELASTIC ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK ch0_xcvr_tx_spread_spectrum_en DISABLE ch0_xcvr_tx_cascade_en DISABLE ch0_tx_pcs_mode DISABLED ch0_rx_pcs_mode DISABLED ch0_mac_link_fault_mode OFF ch0_mac_remove_pads DISABLE ch0_mac_keep_rx_crc DISABLE ch0_mac_forward_rx_pause_requests DISABLE ch0_mac_source_address_insertion DISABLE ch0_mac_tx_vlan_detection DISABLE ch0_mac_rx_vlan_detection DISABLE ch0_mac_flow_control DISABLE FLOW CONTROL ch0_mac_tx_max_frame_size 65 ch0_mac_rx_max_frame_size 65 ch0_mac_enforce_max_frame_size DISABLE ch0_mac_tx_preamble_passthrough DISABLE ch0_mac_rx_preamble_passthrough DISABLE ch0_mac_strict_preamble_checking DISABLE ch0_mac_strict_sfd_checking DISABLE ch0_mac_tx_ipg_size 12 ch0_mac_ipg_removed_per_am_period 0 ch0_mac_custom_cadence DISABLE ch0_ptp0_en DISABLED ch0_ptp1_en DISABLED ch0_mac_sim_mode ENABLE ch0_ptp0_sim_mode ENABLE ch0_ptp1_sim_mode ENABLE ch0_mac_tx_mac_data_flow DISABLE ch0_mac_sf_en DISABLED ch0_ehip_loopback_mode NO_LOOPBACK ch0_mac_txmac_saddr 001122334455 ch0_pldif_tx_fifo_mode PHASE_COMP ch0_pldif_tx_fifo_width DOUBLE_WIDTH ch0_pldif_rx_fifo_mode PHASE_COMP ch0_pldif_rx_fifo_width DOUBLE_WIDTH ch0_pldif_tx_clkout1_divider DIV2 ch0_pldif_tx_clkout2_divider DIV1 ch0_pldif_rx_clkout1_divider DIV1 ch0_pldif_rx_clkout2_divider DIV1 ch0_pldif_channel_identifier GENERIC ch0_pldif_sf_en ENABLED ch0_pldif_loopback_mode NO_LOOPBACK ch0_pcs_loopback_mode NO_LOOPBACK ch0_pcs_sf_en DISABLED ch0_fec_spec DISABLED ch0_fec_fracture UNUSED ch0_fec_tx_en FALSE ch0_fec_rx_en FALSE ch0_fec_loopback_mode DISABLE ch0_tx_pll_frac_mode_en DISABLE ch0_rx_invert_pin DISABLE ch0_tx_invert_pin DISABLE ch0_xcvr_rx_cdrdivout_en DISABLE ch0_xcvr_tx_eq_main_tap 52 ch0_xcvr_tx_eq_post_tap_1 5 ch0_xcvr_tx_eq_pre_tap_1 0 ch0_xcvr_tx_eq_pre_tap_2 0 ch0_tx_pll_feed_forward_gain 1 ch0_xcvr_rx_termination_mode GROUNDED ch0_xcvr_rx_onchip_termination_setting R_2 ch0_xcvr_rx_eq_vga_gain 0 ch0_xcvr_x_eq_hf_boost 0 ch0_xcvr_rx_eq_dfe_tap_1 0 ch0_xcvr_rx_external_couple_type AC ch0_sequencer_reg_en DISABLE ch0_rx_dl_rx_lat_bit_for_async 0 ch0_rx_dl_rxbit_rollover 5280 ch0_rx_dl_rxbit_cntr_pma DISABLE ch0_hw_fec 0 ch0_vsr_mode DISABLED CH0_SRC_TX_ENABLE 1 CH0_SRC_RX_ENABLE 1 CH0_SRC_TX_INITIATOR 1 CH0_SRC_RX_INITIATOR 1 CH0_SRC_TX_INITIATOR_INDEX 0 CH0_SRC_RX_INITIATOR_INDEX 0 CH0_SRC_TX_TARGET_ENABLE 0 CH0_SRC_RX_TARGET_ENABLE 0 CH0_SRC_TX_LANE_FUCTIONAL_MODE 0 CH0_SRC_RX_LANE_FUCTIONAL_MODE 0 CH0_SRC_NON_PTP_CHANNEL 1 CH0_SRC_TX_PCS_EN 0 CH0_SRC_RX_PCS_EN 0 CH0_SRC_UX_EN 1 CH0_SRC_TX_DL_EN 1 CH0_SRC_RX_DL_EN 1 CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION 0 CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 0 CH0_SRC_PTP_EN 0 CH0_SRC_TX_FEC_EN 0 CH0_SRC_RX_FEC_EN 0 CH0_SRC_ETHERNET_SYSPLL_CLK_MODE 1 CH0_SRC_UX_USING_SYSPLL_CLK 0 CH0_SRC_FLUX_USING_SYSPLL_CLK 0 CH0_SRC_FLUX_EN 0 CH0_SRC_FLUX_EN_HW 0 CH0_SRC_TX_AVMM_ENABLE 1 CH0_SRC_RX_AVMM_ENABLE 1 CH0_SRC_SRC_LANE_INDEX 0 CH0_SRC_LEADER_LANE 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_alt_mge_xcvr_directphy_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper

n_channel_superset v21.0.0

Parameters num_of_lanes 1 relative_index 0 dr_enable DR_ENABLED SRC_SIM_SCALE_DOWN 0 device_die_type MAIN_SM7 device_die_revisions MAIN_SM7_REVB mac_use_case 0 hide_ptp_atoms FALSE mode_ethernet REFCLK_RECOVERY_EN 0 ch0_lane_id 0 ch0_fec_clk_en DISABLE ch0_tx_channel_mode PMAD ch0_rx_channel_mode PMAD ch0_duplex_mode DUPLEX ch0_rate_mode RATE_25G ch0_ptp_mode DISABLED ch0_fec_mode 0 ch0_tx_dl_enable ENABLE ch0_rx_dl_enable ENABLE ch0_sup_mode USER_MODE ch0_sim_mode ENABLE ch0_syspll_rx_clk_hz 322265625 ch0_syspll_tx_clk_hz 322265625 ch0_tx_user1_clk_dynamic_mux PLL_C0 ch0_tx_user2_clk_dynamic_mux WORD_CLK ch0_rx_user1_clk_dynamic_mux WORD_CLK ch0_rx_user2_clk_dynamic_mux POSTDIV_CLK ch0_tx_bond_size 1 ch0_rx_bond_size 1 ch0_xcvr_tx_protocol_hint DISABLED ch0_xcvr_tx_datarate_bps 3125 ch0_xcvr_tx_prbs_pattern DISABLE ch0_xcvr_tx_user_clk_only_mode DISABLE ch0_xcvr_tx_width 20 ch0_xcvr_rx_protocol_hint DISABLED ch0_xcvr_rx_datarate_bps 3125 ch0_xcvr_rx_prbs_pattern DISABLE ch0_xcvr_rx_width 20 ch0_xcvr_rx_force_cdr_ltr FALSE ch0_xcvr_rx_adaptation_mode DISABLED ch0_xcvr_rx_adaptation_mode_hw MANUAL_ADAPTATION ch0_xcvr_cdr_f_ref_hz 156250000 ch0_xcvr_cdr_f_vco_hz 1562500000 ch0_rx_postdiv_clk_en ENABLE ch0_rx_postdiv_clk_divider 40 ch0_tx_postdiv_clk_divider 100 ch0_tx_pll_f_ref_hz 156250000 ch0_tx_pll_f_out_hz 1562500000 ch0_dpma_f_ref_hz 250000000 ch0_tx_pll_refclk_select GLOBAL_REFCLK0 ch0_cdr_refclk_select GLOBAL_REFCLK1 ch0_phy_loopback_mode DISABLED ch0_flux_mode FLUX_MODE_BYPASS ch0_flux_mode_hw FLUX_MODE_BYPASS ch0_xcvrif_tx_fifo_mode ELASTIC ch0_xcvrif_rx_fifo_mode ELASTIC ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK ch0_xcvr_tx_spread_spectrum_en DISABLE ch0_xcvr_tx_cascade_en DISABLE ch0_tx_pcs_mode DISABLED ch0_rx_pcs_mode DISABLED ch0_mac_link_fault_mode OFF ch0_mac_remove_pads DISABLE ch0_mac_keep_rx_crc DISABLE ch0_mac_forward_rx_pause_requests DISABLE ch0_mac_source_address_insertion DISABLE ch0_mac_tx_vlan_detection DISABLE ch0_mac_rx_vlan_detection DISABLE ch0_mac_flow_control DISABLE FLOW CONTROL ch0_mac_tx_max_frame_size 65 ch0_mac_rx_max_frame_size 65 ch0_mac_enforce_max_frame_size DISABLE ch0_mac_tx_preamble_passthrough DISABLE ch0_mac_rx_preamble_passthrough DISABLE ch0_mac_strict_preamble_checking DISABLE ch0_mac_strict_sfd_checking DISABLE ch0_mac_tx_ipg_size 12 ch0_mac_ipg_removed_per_am_period 0 ch0_mac_custom_cadence DISABLE ch0_ptp0_en DISABLED ch0_ptp1_en DISABLED ch0_mac_sim_mode ENABLE ch0_ptp0_sim_mode ENABLE ch0_ptp1_sim_mode ENABLE ch0_mac_tx_mac_data_flow DISABLE ch0_mac_sf_en DISABLED ch0_ehip_loopback_mode NO_LOOPBACK ch0_mac_txmac_saddr 001122334455 ch0_pldif_tx_fifo_mode PHASE_COMP ch0_pldif_tx_fifo_width DOUBLE_WIDTH ch0_pldif_rx_fifo_mode PHASE_COMP ch0_pldif_rx_fifo_width DOUBLE_WIDTH ch0_pldif_tx_clkout1_divider DIV2 ch0_pldif_tx_clkout2_divider DIV1 ch0_pldif_rx_clkout1_divider DIV1 ch0_pldif_rx_clkout2_divider DIV1 ch0_pldif_channel_identifier GENERIC ch0_pldif_sf_en ENABLED ch0_pldif_loopback_mode NO_LOOPBACK ch0_pcs_loopback_mode NO_LOOPBACK ch0_pcs_sf_en DISABLED ch0_fec_spec DISABLED ch0_fec_fracture UNUSED ch0_fec_tx_en FALSE ch0_fec_rx_en FALSE ch0_fec_loopback_mode DISABLE ch0_tx_pll_frac_mode_en DISABLE ch0_rx_invert_pin DISABLE ch0_tx_invert_pin DISABLE ch0_xcvr_rx_cdrdivout_en DISABLE ch0_xcvr_tx_eq_main_tap 52 ch0_xcvr_tx_eq_post_tap_1 5 ch0_xcvr_tx_eq_pre_tap_1 0 ch0_xcvr_tx_eq_pre_tap_2 0 ch0_tx_pll_feed_forward_gain 1 ch0_xcvr_rx_termination_mode GROUNDED ch0_xcvr_rx_onchip_termination_setting R_2 ch0_xcvr_rx_eq_vga_gain 0 ch0_xcvr_x_eq_hf_boost 0 ch0_xcvr_rx_eq_dfe_tap_1 0 ch0_xcvr_rx_external_couple_type AC ch0_sequencer_reg_en DISABLE ch0_rx_dl_rx_lat_bit_for_async 0 ch0_rx_dl_rxbit_rollover 5280 ch0_rx_dl_rxbit_cntr_pma DISABLE ch0_hw_fec 0 ch0_vsr_mode DISABLED CH0_SRC_TX_ENABLE 1 CH0_SRC_RX_ENABLE 1 CH0_SRC_TX_INITIATOR 1 CH0_SRC_RX_INITIATOR 1 CH0_SRC_TX_INITIATOR_INDEX 0 CH0_SRC_RX_INITIATOR_INDEX 0 CH0_SRC_TX_TARGET_ENABLE 0 CH0_SRC_RX_TARGET_ENABLE 0 CH0_SRC_TX_LANE_FUCTIONAL_MODE 0 CH0_SRC_RX_LANE_FUCTIONAL_MODE 0 CH0_SRC_NON_PTP_CHANNEL 1 CH0_SRC_TX_PCS_EN 0 CH0_SRC_RX_PCS_EN 0 CH0_SRC_UX_EN 1 CH0_SRC_TX_DL_EN 1 CH0_SRC_RX_DL_EN 1 CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION 0 CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 0 CH0_SRC_PTP_EN 0 CH0_SRC_TX_FEC_EN 0 CH0_SRC_RX_FEC_EN 0 CH0_SRC_ETHERNET_SYSPLL_CLK_MODE 1 CH0_SRC_UX_USING_SYSPLL_CLK 0 CH0_SRC_FLUX_USING_SYSPLL_CLK 0 CH0_SRC_FLUX_EN 0 CH0_SRC_FLUX_EN_HW 0 CH0_SRC_TX_AVMM_ENABLE 1 CH0_SRC_RX_AVMM_ENABLE 1 CH0_SRC_SRC_LANE_INDEX 0 CH0_SRC_LEADER_LANE 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

intel_mge_phy_0_alt_mge_xcvr_directphy_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip

n_channel_superset_hal_top v21.0.0

Parameters tx_pll_fout_hz 1562.500000 tx_pll_vco_MHz 12500.000000 tx_pll_cascade_enable 0 tx_pll_frac_mode_enable 0 tx_pll_realtime_lock_enable 0 tx_pll_refclk_freq_mhz 156.250000 tx_pll_refclk_freq_itxt 156.250000 rx_pll_fout_hz 1562.500000 rx_pll_vco_MHz 12500.000000 rx_pll_refclk_freq_mhz 156.250000 dr_enable DR_ENABLED relative_index 0 num_of_lanes 1 device_die_type MAIN_SM7 device_die_revisions MAIN_SM7_REVB mac_use_case 0 hide_ptp_atoms FALSE mode_ethernet ch0_fec_clk_en DISABLE ch0_tx_channel_mode PMAD ch0_rx_channel_mode PMAD ch0_duplex_mode DUPLEX ch0_rate_mode RATE_25G ch0_ptp_mode DISABLED ch0_fec_mode 0 ch0_tx_dl_enable ENABLE ch0_rx_dl_enable ENABLE ch0_sup_mode USER_MODE ch0_sim_mode ENABLE ch0_tx_user1_clk_dynamic_mux PLL_C0 ch0_tx_user2_clk_dynamic_mux WORD_CLK ch0_rx_user1_clk_dynamic_mux WORD_CLK ch0_rx_user2_clk_dynamic_mux POSTDIV_CLK ch0_tx_bond_size 1 ch0_rx_bond_size 1 ch0_tx_pcs_mode DISABLED ch0_rx_pcs_mode DISABLED ch0_syspll_rx_clk_hz 322265625 ch0_syspll_tx_clk_hz 322265625 ch0_mac_link_fault_mode OFF ch0_mac_remove_pads DISABLE ch0_mac_keep_rx_crc DISABLE ch0_mac_forward_rx_pause_requests DISABLE ch0_mac_source_address_insertion DISABLE ch0_mac_tx_vlan_detection DISABLE ch0_mac_rx_vlan_detection DISABLE ch0_mac_flow_control DISABLE FLOW CONTROL ch0_mac_tx_max_frame_size 65 ch0_mac_rx_max_frame_size 65 ch0_mac_enforce_max_frame_size DISABLE ch0_mac_tx_preamble_passthrough DISABLE ch0_mac_rx_preamble_passthrough DISABLE ch0_mac_strict_preamble_checking DISABLE ch0_mac_strict_sfd_checking DISABLE ch0_mac_tx_ipg_size 12 ch0_mac_ipg_removed_per_am_period 0 ch0_mac_custom_cadence DISABLE ch0_ptp0_en DISABLED ch0_ptp1_en DISABLED ch0_mac_sim_mode ENABLE ch0_ptp0_sim_mode ENABLE ch0_ptp1_sim_mode ENABLE ch0_mac_tx_mac_data_flow DISABLE ch0_mac_sf_en DISABLED ch0_ehip_loopback_mode NO_LOOPBACK ch0_mac_txmac_saddr 001122334455 ch0_pldif_tx_fifo_mode PHASE_COMP ch0_pldif_tx_fifo_width DOUBLE_WIDTH ch0_pldif_rx_fifo_mode PHASE_COMP ch0_pldif_rx_fifo_width DOUBLE_WIDTH ch0_pldif_tx_clkout1_divider DIV2 ch0_pldif_tx_clkout2_divider DIV1 ch0_pldif_rx_clkout1_divider DIV1 ch0_pldif_rx_clkout2_divider DIV1 ch0_pldif_channel_identifier GENERIC ch0_pldif_sf_en ENABLED ch0_pldif_loopback_mode NO_LOOPBACK ch0_pcs_loopback_mode NO_LOOPBACK ch0_pcs_sf_en DISABLED ch0_fec_spec DISABLED ch0_fec_fracture UNUSED ch0_fec_tx_en FALSE ch0_fec_rx_en FALSE ch0_fec_loopback_mode DISABLE ch0_xcvr_tx_protocol_hint DISABLED ch0_xcvr_tx_datarate_bps 3125 ch0_xcvr_tx_prbs_pattern DISABLE ch0_xcvr_tx_user_clk_only_mode DISABLE ch0_xcvr_tx_width 20 ch0_xcvr_rx_protocol_hint DISABLED ch0_xcvr_rx_datarate_bps 3125 ch0_xcvr_rx_prbs_pattern DISABLE ch0_xcvr_rx_width 20 ch0_xcvr_rx_force_cdr_ltr FALSE ch0_xcvr_rx_adaptation_mode DISABLED ch0_xcvr_rx_adaptation_mode_hw MANUAL_ADAPTATION ch0_xcvr_cdr_f_ref_hz 156250000 ch0_xcvr_cdr_f_vco_hz 1562500000 ch0_rx_postdiv_clk_en ENABLE ch0_rx_postdiv_clk_divider 40 ch0_tx_postdiv_clk_divider 100 ch0_tx_pll_f_ref_hz 156250000 ch0_tx_pll_f_out_hz 1562500000 ch0_dpma_f_ref_hz 250000000 ch0_tx_pll_refclk_select GLOBAL_REFCLK0 ch0_cdr_refclk_select GLOBAL_REFCLK1 ch0_phy_loopback_mode DISABLED ch0_flux_mode FLUX_MODE_BYPASS ch0_flux_mode_hw FLUX_MODE_BYPASS ch0_xcvrif_tx_fifo_mode ELASTIC ch0_xcvrif_rx_fifo_mode ELASTIC ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK ch0_tx_pll_frac_mode_en DISABLE ch0_xcvr_tx_spread_spectrum_en DISABLE ch0_xcvr_tx_cascade_en DISABLE ch0_rx_invert_pin DISABLE ch0_tx_invert_pin DISABLE ch0_vsr_mode DISABLED ch0_xcvr_rx_cdrdivout_en DISABLE ch0_xcvr_tx_eq_main_tap 52 ch0_xcvr_tx_eq_post_tap_1 5 ch0_xcvr_tx_eq_pre_tap_1 0 ch0_xcvr_tx_eq_pre_tap_2 0 ch0_tx_pll_feed_forward_gain 1 ch0_xcvr_rx_termination_mode GROUNDED ch0_xcvr_rx_onchip_termination_setting R_2 ch0_xcvr_rx_eq_vga_gain 0 ch0_xcvr_x_eq_hf_boost 0 ch0_xcvr_rx_eq_dfe_tap_1 0 ch0_xcvr_rx_external_couple_type AC ch0_sequencer_reg_en DISABLE ch0_rx_dl_rx_lat_bit_for_async 0 ch0_rx_dl_rxbit_rollover 5280 ch0_rx_dl_rxbit_cntr_pma DISABLE ch0_hw_fec 0 deviceFamily UNKNOWN generateLegacySim false

  

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