golden top Board Configuration

golden top Board Configuration

               www.terasic.com

Copyright © 2003-2025 Terasic Inc. All Rights Reserved.

Pin Assignments:

CLOCK
Name Location Direction IO Standard
CLK_100_B2A_p BM71 input 1.1-V TRUE DIFFERENTIAL SIGNALING
CLK_100_p BP92 input 1.2-V TRUE DIFFERENTIAL SIGNALING
CLK_50_B5A CH128 input 3.3-V LVCMOS
CLK_50_B6A BK31 input 3.3-V LVCMOS
CLK_50_B6C D8 input 3.3-V LVCMOS
CLK_50_B6F Y4 input 3.3-V LVCMOS
CLK_50_B6H V27 input 3.3-V LVCMOS

Buttons
Name Location Direction IO Standard
USER_BUTTON BK112 input 3.3-V LVCMOS

Swtiches
Name Location Direction IO Standard
USER_SW[0] BP112 input 3.3-V LVCMOS
USER_SW[1] BM112 input 3.3-V LVCMOS

LED
Name Location Direction IO Standard
USER_LED BH118 output 3.3-V LVCMOS

SD Card
Name Location Direction IO Standard
SD_MMC_SEL K15 inout 3.3-V LVCMOS

LPDDR4A
Name Location Direction IO Standard
LPDDR4A_REFCLK_p M105 input 1.1-V TRUE DIFFERENTIAL SIGNALING
LPDDR4A_CS0_n T105 output 1.1-V LVSTL
LPDDR4A_CS1_n P105 output 1.1-V LVSTL
LPDDR4A_CA[0] T114 output 1.1-V LVSTL
LPDDR4A_CA[1] P114 output 1.1-V LVSTL
LPDDR4A_CA[2] V117 output 1.1-V LVSTL
LPDDR4A_CA[3] T117 output 1.1-V LVSTL
LPDDR4A_CA[4] M114 output 1.1-V LVSTL
LPDDR4A_CA[5] K114 output 1.1-V LVSTL
LPDDR4A_CK AK107 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_CKE[0] V108 output 1.1-V LVSTL
LPDDR4A_CKE[1] T108 output 1.1-V LVSTL
LPDDR4A_CK_n AK104 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DM[0] B119 inout 1.1-V LVSTL
LPDDR4A_DM[1] F105 inout 1.1-V LVSTL
LPDDR4A_DM[2] B97 inout 1.1-V LVSTL
LPDDR4A_DM[3] H87 inout 1.1-V LVSTL
LPDDR4A_DQ[0] A128 inout 1.1-V LVSTL
LPDDR4A_DQ[1] A130 inout 1.1-V LVSTL
LPDDR4A_DQ[2] A116 inout 1.1-V LVSTL
LPDDR4A_DQ[3] A113 inout 1.1-V LVSTL
LPDDR4A_DQ[4] B113 inout 1.1-V LVSTL
LPDDR4A_DQ[5] B116 inout 1.1-V LVSTL
LPDDR4A_DQ[6] B130 inout 1.1-V LVSTL
LPDDR4A_DQ[7] B128 inout 1.1-V LVSTL
LPDDR4A_DQ[8] K117 inout 1.1-V LVSTL
LPDDR4A_DQ[9] H117 inout 1.1-V LVSTL
LPDDR4A_DQ[10] M108 inout 1.1-V LVSTL
LPDDR4A_DQ[11] F117 inout 1.1-V LVSTL
LPDDR4A_DQ[12] F108 inout 1.1-V LVSTL
LPDDR4A_DQ[13] H108 inout 1.1-V LVSTL
LPDDR4A_DQ[14] K108 inout 1.1-V LVSTL
LPDDR4A_DQ[15] M117 inout 1.1-V LVSTL
LPDDR4A_DQ[16] B88 inout 1.1-V LVSTL
LPDDR4A_DQ[17] A91 inout 1.1-V LVSTL
LPDDR4A_DQ[18] B106 inout 1.1-V LVSTL
LPDDR4A_DQ[19] A110 inout 1.1-V LVSTL
LPDDR4A_DQ[20] A106 inout 1.1-V LVSTL
LPDDR4A_DQ[21] B103 inout 1.1-V LVSTL
LPDDR4A_DQ[22] A94 inout 1.1-V LVSTL
LPDDR4A_DQ[23] B91 inout 1.1-V LVSTL
LPDDR4A_DQ[24] M87 inout 1.1-V LVSTL
LPDDR4A_DQ[25] K87 inout 1.1-V LVSTL
LPDDR4A_DQ[26] K98 inout 1.1-V LVSTL
LPDDR4A_DQ[27] H98 inout 1.1-V LVSTL
LPDDR4A_DQ[28] F98 inout 1.1-V LVSTL
LPDDR4A_DQ[29] M98 inout 1.1-V LVSTL
LPDDR4A_DQ[30] D84 inout 1.1-V LVSTL
LPDDR4A_DQ[31] F84 inout 1.1-V LVSTL
LPDDR4A_DQS[0] B122 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS[1] F114 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS[2] A101 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS[3] F95 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[0] A125 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[1] D114 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[2] B101 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_DQS_n[3] D95 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4A_RESET_n AG111 output 1.1-V LVSTL
LPDDR4A_RZQ AK111 input 1.1-V

LPDDR4B
Name Location Direction IO Standard
LPDDR4B_REFCLK_p BF75 input 1.1-V TRUE DIFFERENTIAL SIGNALING
LPDDR4B_CS_n BE79 output 1.1-V LVSTL
LPDDR4B_CA[0] BE96 output 1.1-V LVSTL
LPDDR4B_CA[1] BE93 output 1.1-V LVSTL
LPDDR4B_CA[2] BF93 output 1.1-V LVSTL
LPDDR4B_CA[3] BF90 output 1.1-V LVSTL
LPDDR4B_CA[4] BF86 output 1.1-V LVSTL
LPDDR4B_CA[5] BE86 output 1.1-V LVSTL
LPDDR4B_CK BM62 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_CKE BE83 output 1.1-V LVSTL
LPDDR4B_CK_n BP62 output DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DM[0] BU62 inout 1.1-V LVSTL
LPDDR4B_DM[1] CA62 inout 1.1-V LVSTL
LPDDR4B_DQ[0] BW59 inout 1.1-V LVSTL
LPDDR4B_DQ[1] BU59 inout 1.1-V LVSTL
LPDDR4B_DQ[2] CA59 inout 1.1-V LVSTL
LPDDR4B_DQ[3] BR69 inout 1.1-V LVSTL
LPDDR4B_DQ[4] BR71 inout 1.1-V LVSTL
LPDDR4B_DQ[5] BU71 inout 1.1-V LVSTL
LPDDR4B_DQ[6] BU69 inout 1.1-V LVSTL
LPDDR4B_DQ[7] BR59 inout 1.1-V LVSTL
LPDDR4B_DQ[8] CH62 inout 1.1-V LVSTL
LPDDR4B_DQ[9] CF62 inout 1.1-V LVSTL
LPDDR4B_DQ[10] CH71 inout 1.1-V LVSTL
LPDDR4B_DQ[11] CF71 inout 1.1-V LVSTL
LPDDR4B_DQ[12] CA71 inout 1.1-V LVSTL
LPDDR4B_DQ[13] CC71 inout 1.1-V LVSTL
LPDDR4B_DQ[14] CF59 inout 1.1-V LVSTL
LPDDR4B_DQ[15] CH59 inout 1.1-V LVSTL
LPDDR4B_DQS[0] BW69 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS[1] CH69 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS_n[0] CA69 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_DQS_n[1] CF69 inout DIFFERENTIAL 1.1-V LVSTL
LPDDR4B_RESET_n BH71 output 1.1-V LVSTL
LPDDR4B_RZQ BH69 input 1.1-V

HDMI
Name Location Direction IO Standard
DDC_I2C_SCL BR109 inout 3.3-V LVCMOS
DDC_I2C_SDA BF104 inout 3.3-V LVCMOS
HDMI_I2C_SCL BU109 inout 3.3-V LVCMOS
HDMI_I2C_SDA BE115 inout 3.3-V LVCMOS
HDMI_TX_HS CK94 output 1.2-V
HDMI_TX_VS CL97 output 1.2-V
HDMI_TX_D[0] BK78 output 1.2-V
HDMI_TX_D[1] BM78 output 1.2-V
HDMI_TX_D[2] BH78 output 1.2-V
HDMI_TX_D[3] BH81 output 1.2-V
HDMI_TX_D[4] BP81 output 1.2-V
HDMI_TX_D[5] BM81 output 1.2-V
HDMI_TX_D[6] CC81 output 1.2-V
HDMI_TX_D[7] CA81 output 1.2-V
HDMI_TX_D[8] CA78 output 1.2-V
HDMI_TX_D[9] CF78 output 1.2-V
HDMI_TX_D[10] CL82 output 1.2-V
HDMI_TX_D[11] CH81 output 1.2-V
HDMI_TX_D[12] CF81 output 1.2-V
HDMI_TX_D[13] CL85 output 1.2-V
HDMI_TX_D[14] CK85 output 1.2-V
HDMI_TX_D[15] CH92 output 1.2-V
HDMI_TX_D[16] CF92 output 1.2-V
HDMI_TX_D[17] CA92 output 1.2-V
HDMI_TX_D[18] CC92 output 1.2-V
HDMI_TX_D[19] CL76 output 1.2-V
HDMI_TX_D[20] CK76 output 1.2-V
HDMI_TX_D[21] CK80 output 1.2-V
HDMI_TX_D[22] CK88 output 1.2-V
HDMI_TX_D[23] CL88 output 1.2-V
HDMI_TX_DE CL91 output 1.2-V
HDMI_TX_CLK_p BK89 output DIFFERENTIAL 1.2-V SSTL
HDMI_EDGE_HPD BF115 input 3.3-V LVCMOS
HDMI_ISEL BF111 output 3.3-V LVCMOS
HDMI_PD_n BH109 output 3.3-V LVCMOS

I2Cs
Name Location Direction IO Standard
FAN_I2C_SCL V8 inout 3.3-V LVCMOS
FAN_I2C_SDA M15 inout 3.3-V LVCMOS
FAN_ALERT_n T8 input 3.3-V LVCMOS

PM
Name Location Direction IO Standard
PM_I2C_SCL CD135 inout 3.3-V LVCMOS
PM_I2C_SDA CG135 inout 3.3-V LVCMOS
PM_ALERT CG134 input 3.3-V LVCMOS

GPIO
Name Location Direction IO Standard
GPIO_D[0] BF29 inout 3.3-V LVCMOS
GPIO_D[1] BF21 inout 3.3-V LVCMOS
GPIO_D[2] BP22 inout 3.3-V LVCMOS
GPIO_D[3] BE43 inout 3.3-V LVCMOS
GPIO_D[4] BF40 inout 3.3-V LVCMOS
GPIO_D[5] BE29 inout 3.3-V LVCMOS
GPIO_D[6] BE25 inout 3.3-V LVCMOS
GPIO_D[7] BF32 inout 3.3-V LVCMOS
GPIO_D[8] BF36 inout 3.3-V LVCMOS
GPIO_D[9] BF25 inout 3.3-V LVCMOS
GPIO_D[10] BF16 inout 3.3-V LVCMOS
GPIO_D[11] BH19 inout 3.3-V LVCMOS
GPIO_D[12] BK22 inout 3.3-V LVCMOS
GPIO_D[13] BM19 inout 3.3-V LVCMOS
GPIO_D[14] BU19 inout 3.3-V LVCMOS
GPIO_D[15] BR19 inout 3.3-V LVCMOS
GPIO_D[16] CK2 inout 3.3-V LVCMOS
GPIO_D[17] CJ2 inout 3.3-V LVCMOS
GPIO_D[18] BU28 inout 3.3-V LVCMOS
GPIO_D[19] BP31 inout 3.3-V LVCMOS
GPIO_D[20] BR28 inout 3.3-V LVCMOS
GPIO_D[21] BR31 inout 3.3-V LVCMOS
GPIO_D[22] BU31 inout 3.3-V LVCMOS
GPIO_D[23] BM28 inout 3.3-V LVCMOS
GPIO_D[24] BW28 inout 3.3-V LVCMOS
GPIO_D[25] BM31 inout 3.3-V LVCMOS
GPIO_D[26] BK28 inout 3.3-V LVCMOS
GPIO_D[27] BR22 inout 3.3-V LVCMOS
GPIO_D[28] CH12 inout 3.3-V LVCMOS
GPIO_D[29] BU22 inout 3.3-V LVCMOS
GPIO_D[30] BW19 inout 3.3-V LVCMOS
GPIO_D[31] BH28 inout 3.3-V LVCMOS
GPIO_D[32] BM22 inout 3.3-V LVCMOS
GPIO_D[33] CF12 inout 3.3-V LVCMOS
GPIO_D[34] BK19 inout 3.3-V LVCMOS
GPIO_D[35] CF9 inout 3.3-V LVCMOS

CAM
Name Location Direction IO Standard
CAM_CLK_p BW89 input DPHY
CAM_CLK_n CA89 input DPHY
CAM_D_p[0] BR89 input DPHY
CAM_D_p[1] BR92 input DPHY
CAM_D_p[2] BR81 input DPHY
CAM_D_p[3] BR78 input DPHY
CAM_D_n[0] BU89 input DPHY
CAM_D_n[1] BU92 input DPHY
CAM_D_n[2] BU81 input DPHY
CAM_D_n[3] BU78 input DPHY
CAM_I2C_SCL BR112 inout 3.3-V LVCMOS
CAM_I2C_SDA BM109 inout 3.3-V LVCMOS
CAM_GPIO BE111 inout 3.3-V LVCMOS
CAM_RZQ1 BH89 input 1.2-V

HPS
Name Location Direction IO Standard
HPS_ENET_MDC AG115 output 1.8-V
HPS_ENET_MDIO R134 inout 1.8-V
HPS_ENET_RX_CLK M124 input 1.8-V
HPS_ENET_RX_CTL AB127 input 1.8-V
HPS_ENET_RX_DATA[0] H127 input 1.8-V
HPS_ENET_RX_DATA[1] AB124 input 1.8-V
HPS_ENET_RX_DATA[2] F124 input 1.8-V
HPS_ENET_RX_DATA[3] D124 input 1.8-V
HPS_ENET_TX_CLK M127 output 1.8-V
HPS_ENET_TX_CTL K127 output 1.8-V
HPS_ENET_TX_DATA[0] K124 output 1.8-V
HPS_ENET_TX_DATA[1] Y127 output 1.8-V
HPS_ENET_TX_DATA[2] F127 output 1.8-V
HPS_ENET_TX_DATA[3] Y124 output 1.8-V
HPS_IOA_10 AK120 inout 1.8-V
HPS_IOA_11 N134 inout 1.8-V
HPS_IOA_12 T132 inout 1.8-V
HPS_IOA_5 U134 inout 1.8-V
HPS_IOA_6 AL120 inout 1.8-V
HPS_IOA_9 N135 inout 1.8-V
HPS_IOB_10 Y132 inout 1.8-V
HPS_IOB_11 T124 inout 1.8-V
HPS_IOB_12 P124 inout 1.8-V
HPS_IOB_9 T127 inout 1.8-V
HPS_KEY B134 inout 1.8-V
HPS_LED W135 inout 1.8-V
HPS_LED2 U135 inout 1.8-V
HPS_OSC_CLK AG123 input 1.8-V
HPS_SDMMC_CLK D132 output 1.8-V
HPS_SDMMC_CMD AB132 inout 1.8-V
HPS_SDMMC_DATA[0] E135 inout 1.8-V
HPS_SDMMC_DATA[1] F132 inout 1.8-V
HPS_SDMMC_DATA[2] AA135 inout 1.8-V
HPS_SDMMC_DATA[3] V127 inout 1.8-V
HPS_UART_RX AK115 input 1.8-V
HPS_UART_TX W134 output 1.8-V
HPS_USB3_REFCLK_100M_p AP120 input CURRENT MODE LOGIC (CML)
HPS_USB3_SS_RX_n AM133 input HIGH SPEED DIFFERENTIAL I/O
HPS_USB3_SS_RX_p AM135 input HIGH SPEED DIFFERENTIAL I/O
HPS_USB3_SS_TX_n AN126 output HIGH SPEED DIFFERENTIAL I/O
HPS_USB3_SS_TX_p AN129 output HIGH SPEED DIFFERENTIAL I/O
HPS_USB_CLK P132 input 1.8-V
HPS_USB_DATA[0] AD135 inout 1.8-V
HPS_USB_DATA[1] M132 inout 1.8-V
HPS_USB_DATA[2] K132 inout 1.8-V
HPS_USB_DATA[3] AG129 inout 1.8-V
HPS_USB_DATA[4] J134 inout 1.8-V
HPS_USB_DATA[5] AG120 inout 1.8-V
HPS_USB_DATA[6] G134 inout 1.8-V
HPS_USB_DATA[7] G135 inout 1.8-V
HPS_USB_DIR J135 input 1.8-V
HPS_USB_ID BW118 input 3.3-V
HPS_USB_NXT AD134 input 1.8-V
HPS_USB_STP L135 output 1.8-V
HPS_USB_VBUS_CTRL CA118 output 3.3-V
HPS_USB_VBUS_DET BU118 input 3.3-V
HPS_USB_VBUS_FLT_n CF118 input 3.3-V