Qsys

2026.01.13.15:01:42 Datasheet
Overview
Memory Map
  emif_lpddr4a
s0_axi4 
s0_axi4lite 
  emif_lpddr4b
s0_axi4 
s0_axi4lite 

clock_310m

altera_clock_bridge v19.2.0
iopll outclk0   clock_310m
  in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4a

emif_io96b_lpddr4 v4.1.0
iopll outclk0   emif_lpddr4a
  s0_axi4_clock_in
reset_in out_reset  
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_lpddr4b

emif_io96b_lpddr4 v4.1.0
iopll outclk0   emif_lpddr4b
  s0_axi4_clock_in
reset_in out_reset  
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll

altera_iopll v21.0.0
clock_in out_clk   iopll
  refclk
reset_in out_reset  
  reset
outclk0   clock_310m
  in_clk
outclk0   emif_lpddr4a
  s0_axi4_clock_in
outclk0   emif_lpddr4b
  s0_axi4_clock_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   emif_lpddr4a
  core_init_n
out_reset   emif_lpddr4b
  core_init_n
out_reset   iopll
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
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