nios_system

2025.07.17.14:38:31 Datasheet
Overview
Processor
   niosv_g Bantam Lake 4.0.0
All Components
   intel_vvp_vfr intel_vvp_vfr 24.5.0
   jtag_uart altera_avalon_jtag_uart 19.3.0
   mm_bridge_peripheral altera_avalon_mm_bridge 20.1.0
   niosv_g intel_niosv_g 4.0.0
   onchip_memory intel_onchip_memory 1.4.10
   pio_fsync_out altera_avalon_pio 19.2.4
   pio_key altera_avalon_pio 19.2.4
   pio_led altera_avalon_pio 19.2.4
   pio_sw altera_avalon_pio 19.2.4
   sysid_qsys altera_avalon_sysid_qsys 19.1.8
   terasic_sdcard terasic_sdio 1.0
Memory Map
intel_vvp_vfr mm_bridge_peripheral niosv_g
 av_mm_mem_read_host  m0  instruction_manager  data_manager
  intel_vvp_vfr
av_mm_control_agent  0x0000_0000 - 0x0000_03ff 0x0008_0000 - 0x0008_03ff
  jtag_uart
avalon_jtag_slave  0x0000_0448 - 0x0000_044f 0x0008_0448 - 0x0008_044f
  mm_bridge_peripheral
s0  0x0008_0000 - 0x000b_ffff
  niosv_g
timer_sw_agent  0x0001_1000 - 0x0001_103f
dm_agent  0x0000_0000 - 0x0000_ffff 0x0000_0000 - 0x0000_ffff
  onchip_memory
s1  0x0010_0000 - 0x0017_fff7 0x0010_0000 - 0x0017_fff7
  pio_fsync_out
s1  0x0000_0400 - 0x0000_040f 0x0008_0400 - 0x0008_040f
  pio_key
s1  0x0000_0410 - 0x0000_041f 0x0008_0410 - 0x0008_041f
  pio_led
s1  0x0000_0420 - 0x0000_042f 0x0008_0420 - 0x0008_042f
  pio_sw
s1  0x0000_0430 - 0x0000_043f 0x0008_0430 - 0x0008_043f
  sdram
axi4_slave  0x0400_0000 - 0x07ff_ffff 0x0400_0000 - 0x07ff_ffff
  sysid_qsys
control_slave  0x0000_0440 - 0x0000_0447 0x0008_0440 - 0x0008_0447
  terasic_sdcard
avalon_slave  0x0001_0000 - 0x0001_0fff 0x0009_0000 - 0x0009_0fff

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_cvo

intel_vvp_cvo v24.4.0
intel_vvp_scaler axi4s_vid_out   intel_vvp_cvo
  axi4s_vid_in
iopll_vga outclk0  
  fr_clock
outclk0  
  vid_clock
reset_bridge out_reset  
  fr_reset
out_reset  
  vid_reset
axi4s_fr_vid_out   intel_vvp_fr2cv
  axi4s_fr_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_fr2cv

intel_vvp_fr2cv v24.3.0
intel_vvp_cvo axi4s_fr_vid_out   intel_vvp_fr2cv
  axi4s_fr_vid_in
iopll_vga outclk0  
  vid_clock
reset_bridge out_reset  
  vid_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_scaler

intel_vvp_scaler v24.5.0
intel_vvp_vfr axi4s_vid_out   intel_vvp_scaler
  axi4s_vid_in
iopll_vga outclk0  
  main_clock
reset_bridge out_reset  
  main_reset
axi4s_vid_out   intel_vvp_cvo
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_vvp_vfr

intel_vvp_vfr v24.5.0
mm_bridge_peripheral m0   intel_vvp_vfr
  av_mm_control_agent
iopll outclk0  
  control_clock
outclk0  
  mem_clock
iopll_vga outclk0  
  main_clock
reset_bridge out_reset  
  control_reset
out_reset  
  main_reset
out_reset  
  mem_reset
av_mm_mem_read_host   sdram
  axi4_slave
axi4s_vid_out   intel_vvp_scaler
  axi4s_vid_in


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll

altera_iopll v20.0.0
clock_in out_clk   iopll
  refclk
reset_bridge out_reset  
  reset
outclk0   pio_sw
  clk
outclk0   jtag_uart
  clk
outclk0   sysid_qsys
  clk
outclk0   mm_bridge_peripheral
  clk
outclk0   pio_led
  clk
outclk0   pio_key
  clk
outclk0   niosv_g
  clk
outclk0   pio_fsync_out
  clk
outclk0   onchip_memory
  clk1
outclk0   sdram
  clock_sink
outclk2  
  clock_sample_sink
outclk0   intel_vvp_vfr
  control_clock
outclk0  
  mem_clock
outclk3   terasic_sdcard
  clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll_vga

altera_iopll v20.0.0
clock_in out_clk   iopll_vga
  refclk
reset_bridge out_reset  
  reset
outclk0   intel_vvp_cvo
  fr_clock
outclk0  
  vid_clock
outclk0   intel_vvp_scaler
  main_clock
outclk0   intel_vvp_vfr
  main_clock
outclk0   intel_vvp_fr2cv
  vid_clock


Parameters

generateLegacySim false
  

Software Assignments

(none)

jtag_uart

altera_avalon_jtag_uart v19.3.0
mm_bridge_peripheral m0   jtag_uart
  avalon_jtag_slave
iopll outclk0  
  clk
niosv_g platform_irq_rx  
  irq
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

READ_DEPTH 64
READ_THRESHOLD 8
WRITE_DEPTH 64
WRITE_THRESHOLD 8

mm_bridge_peripheral

altera_avalon_mm_bridge v20.1.0
niosv_g data_manager   mm_bridge_peripheral
  s0
iopll outclk0  
  clk
reset_bridge out_reset  
  reset
m0   intel_vvp_vfr
  av_mm_control_agent
m0   jtag_uart
  avalon_jtag_slave
m0   terasic_sdcard
  avalon_slave
m0   sysid_qsys
  control_slave
m0   pio_sw
  s1
m0   pio_led
  s1
m0   pio_key
  s1
m0   pio_fsync_out
  s1


Parameters

generateLegacySim false
  

Software Assignments

(none)

niosv_g

intel_niosv_g v4.0.0
iopll outclk0   niosv_g
  clk
reset_bridge out_reset  
  ndm_reset_in
out_reset  
  reset
data_manager   sdram
  axi4_slave
data_manager   mm_bridge_peripheral
  s0
data_manager   onchip_memory
  s1
instruction_manager  
  s1
platform_irq_rx   jtag_uart
  irq
platform_irq_rx   pio_key
  irq
platform_irq_rx   pio_sw
  irq


Parameters

generateLegacySim false
  

Software Assignments

CLIC_EN false
CPU_FREQ 80000000u
DATA_ADDR_WIDTH 32
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 4096
HAS_CSR_SUPPORT 1
HAS_DEBUG_STUB
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
INST_ADDR_WIDTH 32
INT_MODE 0
MTIME_OFFSET 0x00011000
NIOSV_CORE_VARIANT 3
NUM_GPR 32
NUM_SRF_BANKS 1
RESET_ADDR 0x00100000
TICKS_PER_SEC no_quote(NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND)
TIMER_DEVICE_TYPE 2

onchip_memory

intel_onchip_memory v1.4.10
niosv_g data_manager   onchip_memory
  s1
instruction_manager  
  s1
iopll outclk0  
  clk1
reset_bridge out_reset  
  reset1


Parameters

generateLegacySim false
  

Software Assignments

ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
CONTENTS_INFO ""
DUAL_PORT 0
GUI_RAM_BLOCK_TYPE AUTO
INIT_CONTENTS_FILE ram
INIT_MEM_CONTENT 1
INSTANCE_ID NONE
NON_DEFAULT_INIT_FILE_ENABLED 1
RAM_BLOCK_TYPE AUTO
READ_DURING_WRITE_MODE DONT_CARE
SINGLE_CLOCK_OP 0
SIZE_MULTIPLE 1
SIZE_VALUE 524280
WRITABLE 1

pio_fsync_out

altera_avalon_pio v19.2.4
mm_bridge_peripheral m0   pio_fsync_out
  s1
iopll outclk0  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 1
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 80000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_key

altera_avalon_pio v19.2.4
mm_bridge_peripheral m0   pio_key
  s1
iopll outclk0  
  clk
niosv_g platform_irq_rx  
  irq
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 4
EDGE_TYPE FALLING
FREQ 80000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

pio_led

altera_avalon_pio v19.2.4
mm_bridge_peripheral m0   pio_led
  s1
iopll outclk0  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 0
DATA_WIDTH 4
DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0
EDGE_TYPE NONE
FREQ 80000000
HAS_IN 0
HAS_OUT 1
HAS_TRI 0
IRQ_TYPE NONE
RESET_VALUE 0

pio_sw

altera_avalon_pio v19.2.4
mm_bridge_peripheral m0   pio_sw
  s1
iopll outclk0  
  clk
niosv_g platform_irq_rx  
  irq
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
CAPTURE 1
DATA_WIDTH 2
DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0
EDGE_TYPE ANY
FREQ 80000000
HAS_IN 1
HAS_OUT 0
HAS_TRI 0
IRQ_TYPE EDGE
RESET_VALUE 0

reset_bridge

altera_reset_bridge v19.2.0
clock_in out_clk   reset_bridge
  clk
reset_release ninit_done  
  in_reset
reset_in out_reset  
  in_reset
out_reset   intel_vvp_vfr
  control_reset
out_reset  
  main_reset
out_reset  
  mem_reset
out_reset   intel_vvp_cvo
  fr_reset
out_reset  
  vid_reset
out_reset   intel_vvp_scaler
  main_reset
out_reset   niosv_g
  ndm_reset_in
out_reset  
  reset
out_reset   iopll
  reset
out_reset   sysid_qsys
  reset
out_reset   jtag_uart
  reset
out_reset   pio_sw
  reset
out_reset   mm_bridge_peripheral
  reset
out_reset   pio_led
  reset
out_reset   pio_key
  reset
out_reset   pio_fsync_out
  reset
out_reset   iopll_vga
  reset
out_reset   terasic_sdcard
  reset
out_reset   onchip_memory
  reset1
out_reset   sdram
  reset_sink
out_reset   intel_vvp_fr2cv
  vid_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   reset_bridge
  in_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_release

intel_user_rst_clkgate v1.0.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

sdram

core_sdram_axi4 v1.3
intel_vvp_vfr av_mm_mem_read_host   sdram
  axi4_slave
niosv_g data_manager  
  axi4_slave
iopll outclk0  
  clock_sink
outclk2  
  clock_sample_sink
reset_bridge out_reset  
  reset_sink


Parameters

generateLegacySim false
  

Software Assignments

(none)

sysid_qsys

altera_avalon_sysid_qsys v19.1.8
mm_bridge_peripheral m0   sysid_qsys
  control_slave
iopll outclk0  
  clk
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

ID 0
TIMESTAMP 0

terasic_sdcard

terasic_sdio v1.0
mm_bridge_peripheral m0   terasic_sdcard
  avalon_slave
iopll outclk3  
  clock
reset_bridge out_reset  
  reset


Parameters

generateLegacySim false
  

Software Assignments

(none)
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