// nios_system_intel_vvp_vfr_0_intel_vvp_vfr_2450_ha3ggia.v

// This file was auto-generated from intel_vvp_vfr_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_vfr_0_intel_vvp_vfr_2450_ha3ggia #(
		parameter MAX_HEIGHT             = 720,
		parameter MAX_WIDTH              = 1280,
		parameter BPS                    = 8,
		parameter NUMBER_OF_COLOR_PLANES = 3,
		parameter PIXELS_IN_PARALLEL     = 1,
		parameter CLOCKS_ARE_SEPARATE    = 1,
		parameter P_AV_MM_DATA_WIDTH     = 256,
		parameter P_AV_MM_ADDR_WIDTH     = 32,
		parameter READ_BURST_TARGET      = 32,
		parameter MAX_BUFFER_SETS        = 2
	) (
		input  wire         main_clock_clk,                    //          main_clock.clk,          Clock Input
		input  wire         main_reset_reset,                  //          main_reset.reset
		input  wire         mem_clock_clk,                     //           mem_clock.clk,          Clock Input
		input  wire         mem_reset_reset,                   //           mem_reset.reset
		output wire [23:0]  axi4s_vid_out_tdata,               //       axi4s_vid_out.tdata
		output wire         axi4s_vid_out_tvalid,              //                    .tvalid
		input  wire         axi4s_vid_out_tready,              //                    .tready
		output wire         axi4s_vid_out_tlast,               //                    .tlast
		output wire [2:0]   axi4s_vid_out_tuser,               //                    .tuser
		input  wire         fsync_in_read,                     //            fsync_in.read
		output wire         frame_reader_int_irq,              //    frame_reader_int.irq
		output wire [31:0]  av_mm_mem_read_host_address,       // av_mm_mem_read_host.address
		input  wire         av_mm_mem_read_host_waitrequest,   //                    .waitrequest
		output wire [5:0]   av_mm_mem_read_host_burstcount,    //                    .burstcount
		output wire         av_mm_mem_read_host_read,          //                    .read
		input  wire [255:0] av_mm_mem_read_host_readdata,      //                    .readdata
		input  wire         av_mm_mem_read_host_readdatavalid, //                    .readdatavalid
		input  wire [7:0]   av_mm_control_agent_address,       // av_mm_control_agent.address
		input  wire         av_mm_control_agent_write,         //                    .write
		input  wire [3:0]   av_mm_control_agent_byteenable,    //                    .byteenable
		input  wire [31:0]  av_mm_control_agent_writedata,     //                    .writedata
		input  wire         av_mm_control_agent_read,          //                    .read
		output wire [31:0]  av_mm_control_agent_readdata,      //                    .readdata
		output wire         av_mm_control_agent_readdatavalid, //                    .readdatavalid
		output wire         av_mm_control_agent_waitrequest,   //                    .waitrequest
		input  wire         control_clock_clk,                 //       control_clock.clk,          Clock Input
		input  wire         control_reset_reset                //       control_reset.reset
	);

	wire         axi_st_reset_bridge_out_reset_reset;                   // axi_st_reset_bridge:out_rst -> [mm_interconnect_0:scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset, oib:rst, packet_reader:rst, scheduler:rst]
	wire         av_mm_reset_bridge_out_reset_reset;                    // av_mm_reset_bridge:out_rst -> packet_reader:mm_rst
	wire         scheduler_axi_st_cmd_pkt_rd_tvalid;                    // scheduler:axi_st_cmd_pkt_rd_tvalid -> packet_reader:axi_st_cmd_tvalid
	wire         scheduler_axi_st_cmd_pkt_rd_tready;                    // packet_reader:axi_st_cmd_tready -> scheduler:axi_st_cmd_pkt_rd_tready
	wire  [71:0] scheduler_axi_st_cmd_pkt_rd_tdata;                     // scheduler:axi_st_cmd_pkt_rd_tdata -> packet_reader:axi_st_cmd_tdata
	wire         packet_reader_axi_st_resp_tvalid;                      // packet_reader:axi_st_resp_tvalid -> scheduler:axi_st_resp_pkt_rd_tvalid
	wire         packet_reader_axi_st_resp_tready;                      // scheduler:axi_st_resp_pkt_rd_tready -> packet_reader:axi_st_resp_tready
	wire   [7:0] packet_reader_axi_st_resp_tdata;                       // packet_reader:axi_st_resp_tdata -> scheduler:axi_st_resp_pkt_rd_tdata
	wire         scheduler_axi_st_ctrl_out_tvalid;                      // scheduler:axi_st_ctrl_out_tvalid -> oib:axi_st_ctrl_in_tvalid
	wire   [1:0] scheduler_axi_st_ctrl_out_tuser;                       // scheduler:axi_st_ctrl_out_tuser -> oib:axi_st_ctrl_in_tuser
	wire         scheduler_axi_st_ctrl_out_tready;                      // oib:axi_st_ctrl_in_tready -> scheduler:axi_st_ctrl_out_tready
	wire  [15:0] scheduler_axi_st_ctrl_out_tdata;                       // scheduler:axi_st_ctrl_out_tdata -> oib:axi_st_ctrl_in_tdata
	wire         scheduler_axi_st_ctrl_out_tlast;                       // scheduler:axi_st_ctrl_out_tlast -> oib:axi_st_ctrl_in_tlast
	wire         packet_reader_axi_st_data_out_tvalid;                  // packet_reader:axi_st_data_out_tvalid -> oib:axi_st_data_in_tvalid
	wire   [2:0] packet_reader_axi_st_data_out_tuser;                   // packet_reader:axi_st_data_out_tuser -> oib:axi_st_data_in_tuser
	wire         packet_reader_axi_st_data_out_tready;                  // oib:axi_st_data_in_tready -> packet_reader:axi_st_data_out_tready
	wire  [23:0] packet_reader_axi_st_data_out_tdata;                   // packet_reader:axi_st_data_out_tdata -> oib:axi_st_data_in_tdata
	wire         packet_reader_axi_st_data_out_tlast;                   // packet_reader:axi_st_data_out_tlast -> oib:axi_st_data_in_tlast
	wire         mm_rst_bridge_out_reset_reset;                         // mm_rst_bridge:out_rst -> [mm_interconnect_0:ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset, ro_reg_servicer:rst]
	wire         ro_reg_servicer_av_mm_master_waitrequest;              // mm_interconnect_0:ro_reg_servicer_av_mm_master_waitrequest -> ro_reg_servicer:av_mm_master_waitrequest
	wire  [31:0] ro_reg_servicer_av_mm_master_readdata;                 // mm_interconnect_0:ro_reg_servicer_av_mm_master_readdata -> ro_reg_servicer:av_mm_master_readdata
	wire   [8:0] ro_reg_servicer_av_mm_master_address;                  // ro_reg_servicer:av_mm_master_address -> mm_interconnect_0:ro_reg_servicer_av_mm_master_address
	wire   [3:0] ro_reg_servicer_av_mm_master_byteenable;               // ro_reg_servicer:av_mm_master_byteenable -> mm_interconnect_0:ro_reg_servicer_av_mm_master_byteenable
	wire         ro_reg_servicer_av_mm_master_read;                     // ro_reg_servicer:av_mm_master_read -> mm_interconnect_0:ro_reg_servicer_av_mm_master_read
	wire         ro_reg_servicer_av_mm_master_readdatavalid;            // mm_interconnect_0:ro_reg_servicer_av_mm_master_readdatavalid -> ro_reg_servicer:av_mm_master_readdatavalid
	wire         ro_reg_servicer_av_mm_master_write;                    // ro_reg_servicer:av_mm_master_write -> mm_interconnect_0:ro_reg_servicer_av_mm_master_write
	wire  [31:0] ro_reg_servicer_av_mm_master_writedata;                // ro_reg_servicer:av_mm_master_writedata -> mm_interconnect_0:ro_reg_servicer_av_mm_master_writedata
	wire  [31:0] mm_interconnect_0_scheduler_av_mm_agent_readdata;      // scheduler:av_mm_agent_readdata -> mm_interconnect_0:scheduler_av_mm_agent_readdata
	wire         mm_interconnect_0_scheduler_av_mm_agent_waitrequest;   // scheduler:av_mm_agent_waitrequest -> mm_interconnect_0:scheduler_av_mm_agent_waitrequest
	wire   [6:0] mm_interconnect_0_scheduler_av_mm_agent_address;       // mm_interconnect_0:scheduler_av_mm_agent_address -> scheduler:av_mm_agent_address
	wire         mm_interconnect_0_scheduler_av_mm_agent_read;          // mm_interconnect_0:scheduler_av_mm_agent_read -> scheduler:av_mm_agent_read
	wire   [3:0] mm_interconnect_0_scheduler_av_mm_agent_byteenable;    // mm_interconnect_0:scheduler_av_mm_agent_byteenable -> scheduler:av_mm_agent_byteenable
	wire         mm_interconnect_0_scheduler_av_mm_agent_readdatavalid; // scheduler:av_mm_agent_readdatavalid -> mm_interconnect_0:scheduler_av_mm_agent_readdatavalid
	wire         mm_interconnect_0_scheduler_av_mm_agent_write;         // mm_interconnect_0:scheduler_av_mm_agent_write -> scheduler:av_mm_agent_write
	wire  [31:0] mm_interconnect_0_scheduler_av_mm_agent_writedata;     // mm_interconnect_0:scheduler_av_mm_agent_writedata -> scheduler:av_mm_agent_writedata

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (MAX_HEIGHT != 720)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					max_height_check ( .error(1'b1) );
		end
		if (MAX_WIDTH != 1280)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					max_width_check ( .error(1'b1) );
		end
		if (BPS != 8)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					bps_check ( .error(1'b1) );
		end
		if (NUMBER_OF_COLOR_PLANES != 3)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					number_of_color_planes_check ( .error(1'b1) );
		end
		if (PIXELS_IN_PARALLEL != 1)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					pixels_in_parallel_check ( .error(1'b1) );
		end
		if (CLOCKS_ARE_SEPARATE != 1)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					clocks_are_separate_check ( .error(1'b1) );
		end
		if (P_AV_MM_DATA_WIDTH != 256)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					p_av_mm_data_width_check ( .error(1'b1) );
		end
		if (P_AV_MM_ADDR_WIDTH != 32)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					p_av_mm_addr_width_check ( .error(1'b1) );
		end
		if (READ_BURST_TARGET != 32)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					read_burst_target_check ( .error(1'b1) );
		end
		if (MAX_BUFFER_SETS != 2)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					max_buffer_sets_check ( .error(1'b1) );
		end
	endgenerate

	intel_vvp_reset_sync #(
		.SYNC_LEN (3)
	) axi_st_reset_bridge (
		.clk     (main_clock_clk),                      //   input,  width = 1,       clk.clk
		.in_rst  (main_reset_reset),                    //   input,  width = 1,  in_reset.reset
		.out_rst (axi_st_reset_bridge_out_reset_reset)  //  output,  width = 1, out_reset.reset
	);

	intel_vvp_reset_sync #(
		.SYNC_LEN (3)
	) av_mm_reset_bridge (
		.clk     (mem_clock_clk),                      //   input,  width = 1,       clk.clk
		.in_rst  (mem_reset_reset),                    //   input,  width = 1,  in_reset.reset
		.out_rst (av_mm_reset_bridge_out_reset_reset)  //  output,  width = 1, out_reset.reset
	);

	intel_vvp_output_interface_bridge #(
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.PIPELINE_READY         (1),
		.EXTERNAL_MODE          (0)
	) oib (
		.clk                   (main_clock_clk),                       //   input,   width = 1,     main_clock.clk
		.rst                   (axi_st_reset_bridge_out_reset_reset),  //   input,   width = 1,     main_reset.reset
		.axi_st_ctrl_in_tdata  (scheduler_axi_st_ctrl_out_tdata),      //   input,  width = 16, axi_st_ctrl_in.tdata
		.axi_st_ctrl_in_tvalid (scheduler_axi_st_ctrl_out_tvalid),     //   input,   width = 1,               .tvalid
		.axi_st_ctrl_in_tready (scheduler_axi_st_ctrl_out_tready),     //  output,   width = 1,               .tready
		.axi_st_ctrl_in_tlast  (scheduler_axi_st_ctrl_out_tlast),      //   input,   width = 1,               .tlast
		.axi_st_ctrl_in_tuser  (scheduler_axi_st_ctrl_out_tuser),      //   input,   width = 2,               .tuser
		.axi_st_data_in_tdata  (packet_reader_axi_st_data_out_tdata),  //   input,  width = 24, axi_st_data_in.tdata
		.axi_st_data_in_tvalid (packet_reader_axi_st_data_out_tvalid), //   input,   width = 1,               .tvalid
		.axi_st_data_in_tready (packet_reader_axi_st_data_out_tready), //  output,   width = 1,               .tready
		.axi_st_data_in_tlast  (packet_reader_axi_st_data_out_tlast),  //   input,   width = 1,               .tlast
		.axi_st_data_in_tuser  (packet_reader_axi_st_data_out_tuser),  //   input,   width = 3,               .tuser
		.axi_st_ccd_out_tdata  (axi4s_vid_out_tdata),                  //  output,  width = 24, axi_st_ccd_out.tdata
		.axi_st_ccd_out_tvalid (axi4s_vid_out_tvalid),                 //  output,   width = 1,               .tvalid
		.axi_st_ccd_out_tready (axi4s_vid_out_tready),                 //   input,   width = 1,               .tready
		.axi_st_ccd_out_tlast  (axi4s_vid_out_tlast),                  //  output,   width = 1,               .tlast
		.axi_st_ccd_out_tuser  (axi4s_vid_out_tuser)                   //  output,   width = 3,               .tuser
	);

	intel_vvp_vfr_scheduler #(
		.MAX_HEIGHT      (720),
		.MAX_WIDTH       (1280),
		.EXTERNAL_MODE   (0),
		.PIPELINE_READY  (1),
		.ENABLE_DEBUG    (1),
		.MAX_BUFFER_SETS (2)
	) scheduler (
		.clk                        (main_clock_clk),                                                       //   input,   width = 1,         main_clock.clk
		.rst                        (axi_st_reset_bridge_out_reset_reset),                                  //   input,   width = 1,         main_reset.reset
		.av_mm_agent_address        (mm_interconnect_0_scheduler_av_mm_agent_address),                      //   input,   width = 7,        av_mm_agent.address
		.av_mm_agent_write          (mm_interconnect_0_scheduler_av_mm_agent_write),                        //   input,   width = 1,                   .write
		.av_mm_agent_byteenable     (mm_interconnect_0_scheduler_av_mm_agent_byteenable),                   //   input,   width = 4,                   .byteenable
		.av_mm_agent_writedata      (mm_interconnect_0_scheduler_av_mm_agent_writedata),                    //   input,  width = 32,                   .writedata
		.av_mm_agent_read           (mm_interconnect_0_scheduler_av_mm_agent_read),                         //   input,   width = 1,                   .read
		.av_mm_agent_readdata       (mm_interconnect_0_scheduler_av_mm_agent_readdata),                     //  output,  width = 32,                   .readdata
		.av_mm_agent_readdatavalid  (mm_interconnect_0_scheduler_av_mm_agent_readdatavalid),                //  output,   width = 1,                   .readdatavalid
		.av_mm_agent_waitrequest    (mm_interconnect_0_scheduler_av_mm_agent_waitrequest),                  //  output,   width = 1,                   .waitrequest
		.axi_st_ctrl_out_tdata      (scheduler_axi_st_ctrl_out_tdata),                                      //  output,  width = 16,    axi_st_ctrl_out.tdata
		.axi_st_ctrl_out_tvalid     (scheduler_axi_st_ctrl_out_tvalid),                                     //  output,   width = 1,                   .tvalid
		.axi_st_ctrl_out_tready     (scheduler_axi_st_ctrl_out_tready),                                     //   input,   width = 1,                   .tready
		.axi_st_ctrl_out_tlast      (scheduler_axi_st_ctrl_out_tlast),                                      //  output,   width = 1,                   .tlast
		.axi_st_ctrl_out_tuser      (scheduler_axi_st_ctrl_out_tuser),                                      //  output,   width = 2,                   .tuser
		.axi_st_cmd_pkt_rd_tdata    (scheduler_axi_st_cmd_pkt_rd_tdata),                                    //  output,  width = 72,  axi_st_cmd_pkt_rd.tdata
		.axi_st_cmd_pkt_rd_tvalid   (scheduler_axi_st_cmd_pkt_rd_tvalid),                                   //  output,   width = 1,                   .tvalid
		.axi_st_cmd_pkt_rd_tready   (scheduler_axi_st_cmd_pkt_rd_tready),                                   //   input,   width = 1,                   .tready
		.axi_st_resp_pkt_rd_tdata   (packet_reader_axi_st_resp_tdata),                                      //   input,   width = 8, axi_st_resp_pkt_rd.tdata
		.axi_st_resp_pkt_rd_tvalid  (packet_reader_axi_st_resp_tvalid),                                     //   input,   width = 1,                   .tvalid
		.axi_st_resp_pkt_rd_tready  (packet_reader_axi_st_resp_tready),                                     //  output,   width = 1,                   .tready
		.fsync_in                   (fsync_in_read),                                                        //   input,   width = 1,           fsync_in.read
		.frame_reader_int           (frame_reader_int_irq),                                                 //  output,   width = 1,   frame_reader_int.irq
		.axi_st_cmd_wr_to_rd_tdata  (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated),                                 
		.axi_st_cmd_wr_to_rd_tvalid (1'b0),                                                                 // (terminated),                                 
		.axi_st_cmd_wr_to_rd_tready (),                                                                     // (terminated),                                 
		.axi_st_cmd_rd_to_wr_tdata  (),                                                                     // (terminated),                                 
		.axi_st_cmd_rd_to_wr_tvalid (),                                                                     // (terminated),                                 
		.axi_st_cmd_rd_to_wr_tready (1'b0)                                                                  // (terminated),                                 
	);

	intel_vvp_packet_reader #(
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.PIPELINE_READY         (1),
		.CLOCKS_ARE_SEPARATE    (1),
		.P_AV_MM_DATA_WIDTH     (256),
		.P_AV_MM_ADDR_WIDTH     (32),
		.BURST_TARGET           (32),
		.FIFO_DEPTH             (2048),
		.PACKING_LEVEL          (1),
		.ENABLE_RESPONSES       (1),
		.DEVICE_FAMILY          ("Agilex 3")
	) packet_reader (
		.clk                        (main_clock_clk),                       //   input,    width = 1,      main_clock.clk
		.rst                        (axi_st_reset_bridge_out_reset_reset),  //   input,    width = 1,      main_reset.reset
		.mm_clk                     (mem_clock_clk),                        //   input,    width = 1,    master_clock.clk
		.mm_rst                     (av_mm_reset_bridge_out_reset_reset),   //   input,    width = 1,    master_reset.reset
		.axi_st_cmd_tdata           (scheduler_axi_st_cmd_pkt_rd_tdata),    //   input,   width = 72,      axi_st_cmd.tdata
		.axi_st_cmd_tvalid          (scheduler_axi_st_cmd_pkt_rd_tvalid),   //   input,    width = 1,                .tvalid
		.axi_st_cmd_tready          (scheduler_axi_st_cmd_pkt_rd_tready),   //  output,    width = 1,                .tready
		.axi_st_resp_tdata          (packet_reader_axi_st_resp_tdata),      //  output,    width = 8,     axi_st_resp.tdata
		.axi_st_resp_tvalid         (packet_reader_axi_st_resp_tvalid),     //  output,    width = 1,                .tvalid
		.axi_st_resp_tready         (packet_reader_axi_st_resp_tready),     //   input,    width = 1,                .tready
		.axi_st_data_out_tdata      (packet_reader_axi_st_data_out_tdata),  //  output,   width = 24, axi_st_data_out.tdata
		.axi_st_data_out_tvalid     (packet_reader_axi_st_data_out_tvalid), //  output,    width = 1,                .tvalid
		.axi_st_data_out_tready     (packet_reader_axi_st_data_out_tready), //   input,    width = 1,                .tready
		.axi_st_data_out_tlast      (packet_reader_axi_st_data_out_tlast),  //  output,    width = 1,                .tlast
		.axi_st_data_out_tuser      (packet_reader_axi_st_data_out_tuser),  //  output,    width = 3,                .tuser
		.av_mm_master_address       (av_mm_mem_read_host_address),          //  output,   width = 32,    av_mm_master.address
		.av_mm_master_waitrequest   (av_mm_mem_read_host_waitrequest),      //   input,    width = 1,                .waitrequest
		.av_mm_master_burstcount    (av_mm_mem_read_host_burstcount),       //  output,    width = 6,                .burstcount
		.av_mm_master_read          (av_mm_mem_read_host_read),             //  output,    width = 1,                .read
		.av_mm_master_readdata      (av_mm_mem_read_host_readdata),         //   input,  width = 256,                .readdata
		.av_mm_master_readdatavalid (av_mm_mem_read_host_readdatavalid)     //   input,    width = 1,                .readdatavalid
	);

	nios_system_intel_vvp_vfr_0_intel_vvp_ro_reg_servicer_2440_e73yalq #(
		.P_VID_PID                 (1794572874),
		.P_VERSION_NUMBER          (402980865),
		.P_AV_MM_SLAVE_ADDR_WIDTH  (8),
		.P_AV_MM_MASTER_ADDR_WIDTH (9)
	) ro_reg_servicer (
		.clk                        (control_clock_clk),                          //   input,   width = 1,   main_clock.clk
		.rst                        (mm_rst_bridge_out_reset_reset),              //   input,   width = 1,   main_reset.reset
		.av_mm_master_address       (ro_reg_servicer_av_mm_master_address),       //  output,   width = 9, av_mm_master.address
		.av_mm_master_waitrequest   (ro_reg_servicer_av_mm_master_waitrequest),   //   input,   width = 1,             .waitrequest
		.av_mm_master_write         (ro_reg_servicer_av_mm_master_write),         //  output,   width = 1,             .write
		.av_mm_master_writedata     (ro_reg_servicer_av_mm_master_writedata),     //  output,  width = 32,             .writedata
		.av_mm_master_byteenable    (ro_reg_servicer_av_mm_master_byteenable),    //  output,   width = 4,             .byteenable
		.av_mm_master_read          (ro_reg_servicer_av_mm_master_read),          //  output,   width = 1,             .read
		.av_mm_master_readdata      (ro_reg_servicer_av_mm_master_readdata),      //   input,  width = 32,             .readdata
		.av_mm_master_readdatavalid (ro_reg_servicer_av_mm_master_readdatavalid), //   input,   width = 1,             .readdatavalid
		.av_mm_slave_address        (av_mm_control_agent_address),                //   input,   width = 8,  av_mm_slave.address
		.av_mm_slave_write          (av_mm_control_agent_write),                  //   input,   width = 1,             .write
		.av_mm_slave_byteenable     (av_mm_control_agent_byteenable),             //   input,   width = 4,             .byteenable
		.av_mm_slave_writedata      (av_mm_control_agent_writedata),              //   input,  width = 32,             .writedata
		.av_mm_slave_read           (av_mm_control_agent_read),                   //   input,   width = 1,             .read
		.av_mm_slave_readdata       (av_mm_control_agent_readdata),               //  output,  width = 32,             .readdata
		.av_mm_slave_readdatavalid  (av_mm_control_agent_readdatavalid),          //  output,   width = 1,             .readdatavalid
		.av_mm_slave_waitrequest    (av_mm_control_agent_waitrequest)             //  output,   width = 1,             .waitrequest
	);

	intel_vvp_reset_sync #(
		.SYNC_LEN (3)
	) mm_rst_bridge (
		.clk     (control_clock_clk),             //   input,  width = 1,       clk.clk
		.in_rst  (control_reset_reset),           //   input,  width = 1,  in_reset.reset
		.out_rst (mm_rst_bridge_out_reset_reset)  //  output,  width = 1, out_reset.reset
	);

	nios_system_intel_vvp_vfr_0_altera_mm_interconnect_1920_azourty mm_interconnect_0 (
		.ro_reg_servicer_av_mm_master_address                                      (ro_reg_servicer_av_mm_master_address),                  //   input,   width = 9,                                        ro_reg_servicer_av_mm_master.address
		.ro_reg_servicer_av_mm_master_waitrequest                                  (ro_reg_servicer_av_mm_master_waitrequest),              //  output,   width = 1,                                                                    .waitrequest
		.ro_reg_servicer_av_mm_master_byteenable                                   (ro_reg_servicer_av_mm_master_byteenable),               //   input,   width = 4,                                                                    .byteenable
		.ro_reg_servicer_av_mm_master_read                                         (ro_reg_servicer_av_mm_master_read),                     //   input,   width = 1,                                                                    .read
		.ro_reg_servicer_av_mm_master_readdata                                     (ro_reg_servicer_av_mm_master_readdata),                 //  output,  width = 32,                                                                    .readdata
		.ro_reg_servicer_av_mm_master_readdatavalid                                (ro_reg_servicer_av_mm_master_readdatavalid),            //  output,   width = 1,                                                                    .readdatavalid
		.ro_reg_servicer_av_mm_master_write                                        (ro_reg_servicer_av_mm_master_write),                    //   input,   width = 1,                                                                    .write
		.ro_reg_servicer_av_mm_master_writedata                                    (ro_reg_servicer_av_mm_master_writedata),                //   input,  width = 32,                                                                    .writedata
		.scheduler_av_mm_agent_address                                             (mm_interconnect_0_scheduler_av_mm_agent_address),       //  output,   width = 7,                                               scheduler_av_mm_agent.address
		.scheduler_av_mm_agent_write                                               (mm_interconnect_0_scheduler_av_mm_agent_write),         //  output,   width = 1,                                                                    .write
		.scheduler_av_mm_agent_read                                                (mm_interconnect_0_scheduler_av_mm_agent_read),          //  output,   width = 1,                                                                    .read
		.scheduler_av_mm_agent_readdata                                            (mm_interconnect_0_scheduler_av_mm_agent_readdata),      //   input,  width = 32,                                                                    .readdata
		.scheduler_av_mm_agent_writedata                                           (mm_interconnect_0_scheduler_av_mm_agent_writedata),     //  output,  width = 32,                                                                    .writedata
		.scheduler_av_mm_agent_byteenable                                          (mm_interconnect_0_scheduler_av_mm_agent_byteenable),    //  output,   width = 4,                                                                    .byteenable
		.scheduler_av_mm_agent_readdatavalid                                       (mm_interconnect_0_scheduler_av_mm_agent_readdatavalid), //   input,   width = 1,                                                                    .readdatavalid
		.scheduler_av_mm_agent_waitrequest                                         (mm_interconnect_0_scheduler_av_mm_agent_waitrequest),   //   input,   width = 1,                                                                    .waitrequest
		.ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset (mm_rst_bridge_out_reset_reset),                         //   input,   width = 1, ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset.reset
		.scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset        (axi_st_reset_bridge_out_reset_reset),                   //   input,   width = 1,        scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset.reset
		.mm_clk_bridge_out_clk_clk                                                 (control_clock_clk),                                     //   input,   width = 1,                                               mm_clk_bridge_out_clk.clk
		.axi_st_clk_bridge_out_clk_clk                                             (main_clock_clk)                                         //   input,   width = 1,                                           axi_st_clk_bridge_out_clk.clk
	);

endmodule
