// iopll.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module iopll (
		input  wire  refclk,   //  refclk.clk,   The reference clock source that drives the I/O PLL.
		input  wire  rst,      //   reset.reset, The asynchronous reset port for the output clocks. Drive this port high to reset all output clocks to the value of 0.
		output wire  outclk_0, // outclk0.clk,   Output clock Channel 0 from I/O PLL.
		output wire  outclk_1, // outclk1.clk,   Output clock Channel 1 from I/O PLL.
		output wire  outclk_2, // outclk2.clk,   Output clock Channel 2 from I/O PLL.
		output wire  outclk_3  // outclk3.clk,   Output clock Channel 3 from I/O PLL.
	);

	iopll_altera_iopll_2000_n7oyoxq iopll (
		.refclk   (refclk),   //   input,  width = 1,  refclk.clk
		.rst      (rst),      //   input,  width = 1,   reset.reset
		.outclk_0 (outclk_0), //  output,  width = 1, outclk0.clk
		.outclk_1 (outclk_1), //  output,  width = 1, outclk1.clk
		.outclk_2 (outclk_2), //  output,  width = 1, outclk2.clk
		.outclk_3 (outclk_3)  //  output,  width = 1, outclk3.clk
	);

endmodule
