// system.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module system (
		input  wire       clk50_clk,                          //                       clk50.clk
		input  wire [1:0] pio_key_external_connection_export, // pio_key_external_connection.export
		output wire [3:0] pio_led_external_connection_export, // pio_led_external_connection.export
		input  wire       reset_n_reset_n,                    //                     reset_n.reset_n
		output wire       sd_clk_external_connection_export,  //  sd_clk_external_connection.export
		inout  wire       sd_cmd_external_connection_export,  //  sd_cmd_external_connection.export
		inout  wire [3:0] sd_dat_external_connection_export,  //  sd_dat_external_connection.export
		output wire       terasic_sdcard_conduit_end_sd_clk,  //  terasic_sdcard_conduit_end.sd_clk
		inout  wire       terasic_sdcard_conduit_end_sd_cmd,  //                            .sd_cmd
		inout  wire [3:0] terasic_sdcard_conduit_end_sd_data  //                            .sd_data
	);

	wire         clock_in_out_clk_clk;                                         // clock_in:out_clk -> [iopll_system:refclk, reset_in:clk]
	wire         iopll_system_outclk0_clk;                                     // iopll_system:outclk_0 -> [intel_niosv_m:clk, intel_onchip_memory:clk, irq_mapper:clk, jtag_uart:clk, mm_interconnect_0:iopll_system_outclk0_clk, pio_key:clk, pio_led:clk, rst_controller:clk, rst_controller_001:clk, rst_controller_003:clk, sd_clk:clk, sd_cmd:clk, sd_dat:clk, sysid_qsys:clock, timer:clk]
	wire         iopll_system_outclk1_clk;                                     // iopll_system:outclk_1 -> [mm_interconnect_0:iopll_system_outclk1_clk, rst_controller_002:clk, rst_controller_004:clk, terasic_sdcard:clk]
	wire         reset_in_out_reset_reset;                                     // reset_in:out_reset_n -> [iopll_system:rst, rst_controller:reset_in0, rst_controller_001:reset_in1, rst_controller_002:reset_in0, rst_controller_003:reset_in0, rst_controller_004:reset_in0]
	wire  [31:0] intel_niosv_m_data_manager_awaddr;                            // intel_niosv_m:data_manager_awaddr -> mm_interconnect_0:intel_niosv_m_data_manager_awaddr
	wire   [1:0] intel_niosv_m_data_manager_bresp;                             // mm_interconnect_0:intel_niosv_m_data_manager_bresp -> intel_niosv_m:data_manager_bresp
	wire         intel_niosv_m_data_manager_arready;                           // mm_interconnect_0:intel_niosv_m_data_manager_arready -> intel_niosv_m:data_manager_arready
	wire  [31:0] intel_niosv_m_data_manager_rdata;                             // mm_interconnect_0:intel_niosv_m_data_manager_rdata -> intel_niosv_m:data_manager_rdata
	wire   [3:0] intel_niosv_m_data_manager_wstrb;                             // intel_niosv_m:data_manager_wstrb -> mm_interconnect_0:intel_niosv_m_data_manager_wstrb
	wire         intel_niosv_m_data_manager_wready;                            // mm_interconnect_0:intel_niosv_m_data_manager_wready -> intel_niosv_m:data_manager_wready
	wire         intel_niosv_m_data_manager_awready;                           // mm_interconnect_0:intel_niosv_m_data_manager_awready -> intel_niosv_m:data_manager_awready
	wire         intel_niosv_m_data_manager_rready;                            // intel_niosv_m:data_manager_rready -> mm_interconnect_0:intel_niosv_m_data_manager_rready
	wire         intel_niosv_m_data_manager_bready;                            // intel_niosv_m:data_manager_bready -> mm_interconnect_0:intel_niosv_m_data_manager_bready
	wire         intel_niosv_m_data_manager_wvalid;                            // intel_niosv_m:data_manager_wvalid -> mm_interconnect_0:intel_niosv_m_data_manager_wvalid
	wire  [31:0] intel_niosv_m_data_manager_araddr;                            // intel_niosv_m:data_manager_araddr -> mm_interconnect_0:intel_niosv_m_data_manager_araddr
	wire   [2:0] intel_niosv_m_data_manager_arprot;                            // intel_niosv_m:data_manager_arprot -> mm_interconnect_0:intel_niosv_m_data_manager_arprot
	wire   [1:0] intel_niosv_m_data_manager_rresp;                             // mm_interconnect_0:intel_niosv_m_data_manager_rresp -> intel_niosv_m:data_manager_rresp
	wire   [2:0] intel_niosv_m_data_manager_awprot;                            // intel_niosv_m:data_manager_awprot -> mm_interconnect_0:intel_niosv_m_data_manager_awprot
	wire  [31:0] intel_niosv_m_data_manager_wdata;                             // intel_niosv_m:data_manager_wdata -> mm_interconnect_0:intel_niosv_m_data_manager_wdata
	wire         intel_niosv_m_data_manager_arvalid;                           // intel_niosv_m:data_manager_arvalid -> mm_interconnect_0:intel_niosv_m_data_manager_arvalid
	wire         intel_niosv_m_data_manager_bvalid;                            // mm_interconnect_0:intel_niosv_m_data_manager_bvalid -> intel_niosv_m:data_manager_bvalid
	wire         intel_niosv_m_data_manager_awvalid;                           // intel_niosv_m:data_manager_awvalid -> mm_interconnect_0:intel_niosv_m_data_manager_awvalid
	wire         intel_niosv_m_data_manager_rvalid;                            // mm_interconnect_0:intel_niosv_m_data_manager_rvalid -> intel_niosv_m:data_manager_rvalid
	wire  [31:0] intel_niosv_m_instruction_manager_awaddr;                     // intel_niosv_m:instruction_manager_awaddr -> mm_interconnect_0:intel_niosv_m_instruction_manager_awaddr
	wire   [1:0] intel_niosv_m_instruction_manager_bresp;                      // mm_interconnect_0:intel_niosv_m_instruction_manager_bresp -> intel_niosv_m:instruction_manager_bresp
	wire         intel_niosv_m_instruction_manager_arready;                    // mm_interconnect_0:intel_niosv_m_instruction_manager_arready -> intel_niosv_m:instruction_manager_arready
	wire  [31:0] intel_niosv_m_instruction_manager_rdata;                      // mm_interconnect_0:intel_niosv_m_instruction_manager_rdata -> intel_niosv_m:instruction_manager_rdata
	wire   [3:0] intel_niosv_m_instruction_manager_wstrb;                      // intel_niosv_m:instruction_manager_wstrb -> mm_interconnect_0:intel_niosv_m_instruction_manager_wstrb
	wire         intel_niosv_m_instruction_manager_wready;                     // mm_interconnect_0:intel_niosv_m_instruction_manager_wready -> intel_niosv_m:instruction_manager_wready
	wire         intel_niosv_m_instruction_manager_awready;                    // mm_interconnect_0:intel_niosv_m_instruction_manager_awready -> intel_niosv_m:instruction_manager_awready
	wire         intel_niosv_m_instruction_manager_rready;                     // intel_niosv_m:instruction_manager_rready -> mm_interconnect_0:intel_niosv_m_instruction_manager_rready
	wire         intel_niosv_m_instruction_manager_bready;                     // intel_niosv_m:instruction_manager_bready -> mm_interconnect_0:intel_niosv_m_instruction_manager_bready
	wire         intel_niosv_m_instruction_manager_wvalid;                     // intel_niosv_m:instruction_manager_wvalid -> mm_interconnect_0:intel_niosv_m_instruction_manager_wvalid
	wire  [31:0] intel_niosv_m_instruction_manager_araddr;                     // intel_niosv_m:instruction_manager_araddr -> mm_interconnect_0:intel_niosv_m_instruction_manager_araddr
	wire   [2:0] intel_niosv_m_instruction_manager_arprot;                     // intel_niosv_m:instruction_manager_arprot -> mm_interconnect_0:intel_niosv_m_instruction_manager_arprot
	wire   [1:0] intel_niosv_m_instruction_manager_rresp;                      // mm_interconnect_0:intel_niosv_m_instruction_manager_rresp -> intel_niosv_m:instruction_manager_rresp
	wire   [2:0] intel_niosv_m_instruction_manager_awprot;                     // intel_niosv_m:instruction_manager_awprot -> mm_interconnect_0:intel_niosv_m_instruction_manager_awprot
	wire  [31:0] intel_niosv_m_instruction_manager_wdata;                      // intel_niosv_m:instruction_manager_wdata -> mm_interconnect_0:intel_niosv_m_instruction_manager_wdata
	wire         intel_niosv_m_instruction_manager_arvalid;                    // intel_niosv_m:instruction_manager_arvalid -> mm_interconnect_0:intel_niosv_m_instruction_manager_arvalid
	wire         intel_niosv_m_instruction_manager_bvalid;                     // mm_interconnect_0:intel_niosv_m_instruction_manager_bvalid -> intel_niosv_m:instruction_manager_bvalid
	wire         intel_niosv_m_instruction_manager_awvalid;                    // intel_niosv_m:instruction_manager_awvalid -> mm_interconnect_0:intel_niosv_m_instruction_manager_awvalid
	wire         intel_niosv_m_instruction_manager_rvalid;                     // mm_interconnect_0:intel_niosv_m_instruction_manager_rvalid -> intel_niosv_m:instruction_manager_rvalid
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect;     // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata;       // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest;    // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address;        // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;           // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;          // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata;      // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
	wire   [7:0] mm_interconnect_0_terasic_sdcard_avalon_slave_readdata;       // terasic_sdcard:avs_readdata -> mm_interconnect_0:terasic_sdcard_avalon_slave_readdata
	wire  [11:0] mm_interconnect_0_terasic_sdcard_avalon_slave_address;        // mm_interconnect_0:terasic_sdcard_avalon_slave_address -> terasic_sdcard:avs_address
	wire         mm_interconnect_0_terasic_sdcard_avalon_slave_read;           // mm_interconnect_0:terasic_sdcard_avalon_slave_read -> terasic_sdcard:avs_read
	wire         mm_interconnect_0_terasic_sdcard_avalon_slave_write;          // mm_interconnect_0:terasic_sdcard_avalon_slave_write -> terasic_sdcard:avs_write
	wire   [7:0] mm_interconnect_0_terasic_sdcard_avalon_slave_writedata;      // mm_interconnect_0:terasic_sdcard_avalon_slave_writedata -> terasic_sdcard:avs_writedata
	wire  [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata;          // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_qsys_control_slave_address;           // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
	wire  [31:0] mm_interconnect_0_intel_niosv_m_dm_agent_readdata;            // intel_niosv_m:dm_agent_readdata -> mm_interconnect_0:intel_niosv_m_dm_agent_readdata
	wire         mm_interconnect_0_intel_niosv_m_dm_agent_waitrequest;         // intel_niosv_m:dm_agent_waitrequest -> mm_interconnect_0:intel_niosv_m_dm_agent_waitrequest
	wire  [15:0] mm_interconnect_0_intel_niosv_m_dm_agent_address;             // mm_interconnect_0:intel_niosv_m_dm_agent_address -> intel_niosv_m:dm_agent_address
	wire         mm_interconnect_0_intel_niosv_m_dm_agent_read;                // mm_interconnect_0:intel_niosv_m_dm_agent_read -> intel_niosv_m:dm_agent_read
	wire         mm_interconnect_0_intel_niosv_m_dm_agent_readdatavalid;       // intel_niosv_m:dm_agent_readdatavalid -> mm_interconnect_0:intel_niosv_m_dm_agent_readdatavalid
	wire         mm_interconnect_0_intel_niosv_m_dm_agent_write;               // mm_interconnect_0:intel_niosv_m_dm_agent_write -> intel_niosv_m:dm_agent_write
	wire  [31:0] mm_interconnect_0_intel_niosv_m_dm_agent_writedata;           // mm_interconnect_0:intel_niosv_m_dm_agent_writedata -> intel_niosv_m:dm_agent_writedata
	wire  [31:0] mm_interconnect_0_intel_onchip_memory_s1_readdata;            // intel_onchip_memory:readdata -> mm_interconnect_0:intel_onchip_memory_s1_readdata
	wire  [16:0] mm_interconnect_0_intel_onchip_memory_s1_address;             // mm_interconnect_0:intel_onchip_memory_s1_address -> intel_onchip_memory:address
	wire         mm_interconnect_0_intel_onchip_memory_s1_read;                // mm_interconnect_0:intel_onchip_memory_s1_read -> intel_onchip_memory:read
	wire   [3:0] mm_interconnect_0_intel_onchip_memory_s1_byteenable;          // mm_interconnect_0:intel_onchip_memory_s1_byteenable -> intel_onchip_memory:byteenable
	wire         mm_interconnect_0_intel_onchip_memory_s1_write;               // mm_interconnect_0:intel_onchip_memory_s1_write -> intel_onchip_memory:write
	wire  [31:0] mm_interconnect_0_intel_onchip_memory_s1_writedata;           // mm_interconnect_0:intel_onchip_memory_s1_writedata -> intel_onchip_memory:writedata
	wire         mm_interconnect_0_timer_s1_chipselect;                        // mm_interconnect_0:timer_s1_chipselect -> timer:chipselect
	wire  [15:0] mm_interconnect_0_timer_s1_readdata;                          // timer:readdata -> mm_interconnect_0:timer_s1_readdata
	wire   [2:0] mm_interconnect_0_timer_s1_address;                           // mm_interconnect_0:timer_s1_address -> timer:address
	wire         mm_interconnect_0_timer_s1_write;                             // mm_interconnect_0:timer_s1_write -> timer:write_n
	wire  [15:0] mm_interconnect_0_timer_s1_writedata;                         // mm_interconnect_0:timer_s1_writedata -> timer:writedata
	wire         mm_interconnect_0_sd_dat_s1_chipselect;                       // mm_interconnect_0:sd_dat_s1_chipselect -> sd_dat:chipselect
	wire  [31:0] mm_interconnect_0_sd_dat_s1_readdata;                         // sd_dat:readdata -> mm_interconnect_0:sd_dat_s1_readdata
	wire   [1:0] mm_interconnect_0_sd_dat_s1_address;                          // mm_interconnect_0:sd_dat_s1_address -> sd_dat:address
	wire         mm_interconnect_0_sd_dat_s1_write;                            // mm_interconnect_0:sd_dat_s1_write -> sd_dat:write_n
	wire  [31:0] mm_interconnect_0_sd_dat_s1_writedata;                        // mm_interconnect_0:sd_dat_s1_writedata -> sd_dat:writedata
	wire         mm_interconnect_0_sd_cmd_s1_chipselect;                       // mm_interconnect_0:sd_cmd_s1_chipselect -> sd_cmd:chipselect
	wire  [31:0] mm_interconnect_0_sd_cmd_s1_readdata;                         // sd_cmd:readdata -> mm_interconnect_0:sd_cmd_s1_readdata
	wire   [1:0] mm_interconnect_0_sd_cmd_s1_address;                          // mm_interconnect_0:sd_cmd_s1_address -> sd_cmd:address
	wire         mm_interconnect_0_sd_cmd_s1_write;                            // mm_interconnect_0:sd_cmd_s1_write -> sd_cmd:write_n
	wire  [31:0] mm_interconnect_0_sd_cmd_s1_writedata;                        // mm_interconnect_0:sd_cmd_s1_writedata -> sd_cmd:writedata
	wire         mm_interconnect_0_sd_clk_s1_chipselect;                       // mm_interconnect_0:sd_clk_s1_chipselect -> sd_clk:chipselect
	wire  [31:0] mm_interconnect_0_sd_clk_s1_readdata;                         // sd_clk:readdata -> mm_interconnect_0:sd_clk_s1_readdata
	wire   [1:0] mm_interconnect_0_sd_clk_s1_address;                          // mm_interconnect_0:sd_clk_s1_address -> sd_clk:address
	wire         mm_interconnect_0_sd_clk_s1_write;                            // mm_interconnect_0:sd_clk_s1_write -> sd_clk:write_n
	wire  [31:0] mm_interconnect_0_sd_clk_s1_writedata;                        // mm_interconnect_0:sd_clk_s1_writedata -> sd_clk:writedata
	wire         mm_interconnect_0_pio_led_s1_chipselect;                      // mm_interconnect_0:pio_led_s1_chipselect -> pio_led:chipselect
	wire  [31:0] mm_interconnect_0_pio_led_s1_readdata;                        // pio_led:readdata -> mm_interconnect_0:pio_led_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_led_s1_address;                         // mm_interconnect_0:pio_led_s1_address -> pio_led:address
	wire         mm_interconnect_0_pio_led_s1_write;                           // mm_interconnect_0:pio_led_s1_write -> pio_led:write_n
	wire  [31:0] mm_interconnect_0_pio_led_s1_writedata;                       // mm_interconnect_0:pio_led_s1_writedata -> pio_led:writedata
	wire  [31:0] mm_interconnect_0_pio_key_s1_readdata;                        // pio_key:readdata -> mm_interconnect_0:pio_key_s1_readdata
	wire   [1:0] mm_interconnect_0_pio_key_s1_address;                         // mm_interconnect_0:pio_key_s1_address -> pio_key:address
	wire  [31:0] mm_interconnect_0_intel_niosv_m_timer_sw_agent_readdata;      // intel_niosv_m:timer_sw_agent_readdata -> mm_interconnect_0:intel_niosv_m_timer_sw_agent_readdata
	wire         mm_interconnect_0_intel_niosv_m_timer_sw_agent_waitrequest;   // intel_niosv_m:timer_sw_agent_waitrequest -> mm_interconnect_0:intel_niosv_m_timer_sw_agent_waitrequest
	wire   [5:0] mm_interconnect_0_intel_niosv_m_timer_sw_agent_address;       // mm_interconnect_0:intel_niosv_m_timer_sw_agent_address -> intel_niosv_m:timer_sw_agent_address
	wire         mm_interconnect_0_intel_niosv_m_timer_sw_agent_read;          // mm_interconnect_0:intel_niosv_m_timer_sw_agent_read -> intel_niosv_m:timer_sw_agent_read
	wire   [3:0] mm_interconnect_0_intel_niosv_m_timer_sw_agent_byteenable;    // mm_interconnect_0:intel_niosv_m_timer_sw_agent_byteenable -> intel_niosv_m:timer_sw_agent_byteenable
	wire         mm_interconnect_0_intel_niosv_m_timer_sw_agent_readdatavalid; // intel_niosv_m:timer_sw_agent_readdatavalid -> mm_interconnect_0:intel_niosv_m_timer_sw_agent_readdatavalid
	wire         mm_interconnect_0_intel_niosv_m_timer_sw_agent_write;         // mm_interconnect_0:intel_niosv_m_timer_sw_agent_write -> intel_niosv_m:timer_sw_agent_write
	wire  [31:0] mm_interconnect_0_intel_niosv_m_timer_sw_agent_writedata;     // mm_interconnect_0:intel_niosv_m_timer_sw_agent_writedata -> intel_niosv_m:timer_sw_agent_writedata
	wire         irq_mapper_receiver0_irq;                                     // jtag_uart:av_irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                     // timer:irq -> irq_mapper:receiver1_irq
	wire  [15:0] intel_niosv_m_platform_irq_rx_irq;                            // irq_mapper:sender_irq -> intel_niosv_m:platform_irq_rx_irq
	wire         rst_controller_reset_out_reset;                               // rst_controller:reset_out -> [intel_niosv_m:reset_reset, intel_onchip_memory:reset, irq_mapper:reset, jtag_uart:rst_n, pio_key:reset_n, pio_led:reset_n, rst_translator:in_reset, sd_clk:reset_n, sd_cmd:reset_n, sd_dat:reset_n, sysid_qsys:reset_n, timer:reset_n]
	wire         rst_controller_reset_out_reset_req;                           // rst_controller:reset_req -> [intel_onchip_memory:reset_req, rst_translator:reset_req_in]
	wire         rst_controller_001_reset_out_reset;                           // rst_controller_001:reset_out -> intel_niosv_m:ndm_reset_in_reset
	wire         intel_niosv_m_dbg_reset_out_reset;                            // intel_niosv_m:dbg_reset_out_reset -> rst_controller_001:reset_in0
	wire         rst_controller_002_reset_out_reset;                           // rst_controller_002:reset_out -> terasic_sdcard:reset_n
	wire         rst_controller_003_reset_out_reset;                           // rst_controller_003:reset_out -> [mm_interconnect_0:intel_niosv_m_reset_reset_bridge_in_reset_reset, mm_interconnect_0:jtag_uart_avalon_jtag_slave_translator_reset_reset_bridge_in_reset_reset]
	wire         rst_controller_004_reset_out_reset;                           // rst_controller_004:reset_out -> [mm_interconnect_0:terasic_sdcard_avalon_slave_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_0:terasic_sdcard_reset_reset_bridge_in_reset_reset]

	system_clock_in clock_in (
		.in_clk  (clk50_clk),            //   input,  width = 1,  in_clk.clk
		.out_clk (clock_in_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	system_intel_niosv_m_0 intel_niosv_m (
		.clk                          (iopll_system_outclk0_clk),                                     //   input,   width = 1,                 clk.clk
		.reset_reset                  (rst_controller_reset_out_reset),                               //   input,   width = 1,               reset.reset
		.platform_irq_rx_irq          (intel_niosv_m_platform_irq_rx_irq),                            //   input,  width = 16,     platform_irq_rx.irq
		.instruction_manager_awaddr   (intel_niosv_m_instruction_manager_awaddr),                     //  output,  width = 32, instruction_manager.awaddr
		.instruction_manager_awprot   (intel_niosv_m_instruction_manager_awprot),                     //  output,   width = 3,                    .awprot
		.instruction_manager_awvalid  (intel_niosv_m_instruction_manager_awvalid),                    //  output,   width = 1,                    .awvalid
		.instruction_manager_awready  (intel_niosv_m_instruction_manager_awready),                    //   input,   width = 1,                    .awready
		.instruction_manager_wdata    (intel_niosv_m_instruction_manager_wdata),                      //  output,  width = 32,                    .wdata
		.instruction_manager_wstrb    (intel_niosv_m_instruction_manager_wstrb),                      //  output,   width = 4,                    .wstrb
		.instruction_manager_wvalid   (intel_niosv_m_instruction_manager_wvalid),                     //  output,   width = 1,                    .wvalid
		.instruction_manager_wready   (intel_niosv_m_instruction_manager_wready),                     //   input,   width = 1,                    .wready
		.instruction_manager_bresp    (intel_niosv_m_instruction_manager_bresp),                      //   input,   width = 2,                    .bresp
		.instruction_manager_bvalid   (intel_niosv_m_instruction_manager_bvalid),                     //   input,   width = 1,                    .bvalid
		.instruction_manager_bready   (intel_niosv_m_instruction_manager_bready),                     //  output,   width = 1,                    .bready
		.instruction_manager_araddr   (intel_niosv_m_instruction_manager_araddr),                     //  output,  width = 32,                    .araddr
		.instruction_manager_arprot   (intel_niosv_m_instruction_manager_arprot),                     //  output,   width = 3,                    .arprot
		.instruction_manager_arvalid  (intel_niosv_m_instruction_manager_arvalid),                    //  output,   width = 1,                    .arvalid
		.instruction_manager_arready  (intel_niosv_m_instruction_manager_arready),                    //   input,   width = 1,                    .arready
		.instruction_manager_rdata    (intel_niosv_m_instruction_manager_rdata),                      //   input,  width = 32,                    .rdata
		.instruction_manager_rresp    (intel_niosv_m_instruction_manager_rresp),                      //   input,   width = 2,                    .rresp
		.instruction_manager_rvalid   (intel_niosv_m_instruction_manager_rvalid),                     //   input,   width = 1,                    .rvalid
		.instruction_manager_rready   (intel_niosv_m_instruction_manager_rready),                     //  output,   width = 1,                    .rready
		.data_manager_awaddr          (intel_niosv_m_data_manager_awaddr),                            //  output,  width = 32,        data_manager.awaddr
		.data_manager_awprot          (intel_niosv_m_data_manager_awprot),                            //  output,   width = 3,                    .awprot
		.data_manager_awvalid         (intel_niosv_m_data_manager_awvalid),                           //  output,   width = 1,                    .awvalid
		.data_manager_awready         (intel_niosv_m_data_manager_awready),                           //   input,   width = 1,                    .awready
		.data_manager_wdata           (intel_niosv_m_data_manager_wdata),                             //  output,  width = 32,                    .wdata
		.data_manager_wstrb           (intel_niosv_m_data_manager_wstrb),                             //  output,   width = 4,                    .wstrb
		.data_manager_wvalid          (intel_niosv_m_data_manager_wvalid),                            //  output,   width = 1,                    .wvalid
		.data_manager_wready          (intel_niosv_m_data_manager_wready),                            //   input,   width = 1,                    .wready
		.data_manager_bresp           (intel_niosv_m_data_manager_bresp),                             //   input,   width = 2,                    .bresp
		.data_manager_bvalid          (intel_niosv_m_data_manager_bvalid),                            //   input,   width = 1,                    .bvalid
		.data_manager_bready          (intel_niosv_m_data_manager_bready),                            //  output,   width = 1,                    .bready
		.data_manager_araddr          (intel_niosv_m_data_manager_araddr),                            //  output,  width = 32,                    .araddr
		.data_manager_arprot          (intel_niosv_m_data_manager_arprot),                            //  output,   width = 3,                    .arprot
		.data_manager_arvalid         (intel_niosv_m_data_manager_arvalid),                           //  output,   width = 1,                    .arvalid
		.data_manager_arready         (intel_niosv_m_data_manager_arready),                           //   input,   width = 1,                    .arready
		.data_manager_rdata           (intel_niosv_m_data_manager_rdata),                             //   input,  width = 32,                    .rdata
		.data_manager_rresp           (intel_niosv_m_data_manager_rresp),                             //   input,   width = 2,                    .rresp
		.data_manager_rvalid          (intel_niosv_m_data_manager_rvalid),                            //   input,   width = 1,                    .rvalid
		.data_manager_rready          (intel_niosv_m_data_manager_rready),                            //  output,   width = 1,                    .rready
		.timer_sw_agent_address       (mm_interconnect_0_intel_niosv_m_timer_sw_agent_address),       //   input,   width = 6,      timer_sw_agent.address
		.timer_sw_agent_byteenable    (mm_interconnect_0_intel_niosv_m_timer_sw_agent_byteenable),    //   input,   width = 4,                    .byteenable
		.timer_sw_agent_read          (mm_interconnect_0_intel_niosv_m_timer_sw_agent_read),          //   input,   width = 1,                    .read
		.timer_sw_agent_readdata      (mm_interconnect_0_intel_niosv_m_timer_sw_agent_readdata),      //  output,  width = 32,                    .readdata
		.timer_sw_agent_write         (mm_interconnect_0_intel_niosv_m_timer_sw_agent_write),         //   input,   width = 1,                    .write
		.timer_sw_agent_writedata     (mm_interconnect_0_intel_niosv_m_timer_sw_agent_writedata),     //   input,  width = 32,                    .writedata
		.timer_sw_agent_waitrequest   (mm_interconnect_0_intel_niosv_m_timer_sw_agent_waitrequest),   //  output,   width = 1,                    .waitrequest
		.timer_sw_agent_readdatavalid (mm_interconnect_0_intel_niosv_m_timer_sw_agent_readdatavalid), //  output,   width = 1,                    .readdatavalid
		.dm_agent_address             (mm_interconnect_0_intel_niosv_m_dm_agent_address),             //   input,  width = 16,            dm_agent.address
		.dm_agent_read                (mm_interconnect_0_intel_niosv_m_dm_agent_read),                //   input,   width = 1,                    .read
		.dm_agent_readdata            (mm_interconnect_0_intel_niosv_m_dm_agent_readdata),            //  output,  width = 32,                    .readdata
		.dm_agent_write               (mm_interconnect_0_intel_niosv_m_dm_agent_write),               //   input,   width = 1,                    .write
		.dm_agent_writedata           (mm_interconnect_0_intel_niosv_m_dm_agent_writedata),           //   input,  width = 32,                    .writedata
		.dm_agent_waitrequest         (mm_interconnect_0_intel_niosv_m_dm_agent_waitrequest),         //  output,   width = 1,                    .waitrequest
		.dm_agent_readdatavalid       (mm_interconnect_0_intel_niosv_m_dm_agent_readdatavalid),       //  output,   width = 1,                    .readdatavalid
		.dbg_reset_out_reset          (intel_niosv_m_dbg_reset_out_reset),                            //  output,   width = 1,       dbg_reset_out.reset
		.ndm_reset_in_reset           (rst_controller_001_reset_out_reset)                            //   input,   width = 1,        ndm_reset_in.reset
	);

	system_intel_onchip_memory_0 intel_onchip_memory (
		.clk        (iopll_system_outclk0_clk),                            //   input,   width = 1,   clk1.clk
		.address    (mm_interconnect_0_intel_onchip_memory_s1_address),    //   input,  width = 17,     s1.address
		.read       (mm_interconnect_0_intel_onchip_memory_s1_read),       //   input,   width = 1,       .read
		.readdata   (mm_interconnect_0_intel_onchip_memory_s1_readdata),   //  output,  width = 32,       .readdata
		.byteenable (mm_interconnect_0_intel_onchip_memory_s1_byteenable), //   input,   width = 4,       .byteenable
		.write      (mm_interconnect_0_intel_onchip_memory_s1_write),      //   input,   width = 1,       .write
		.writedata  (mm_interconnect_0_intel_onchip_memory_s1_writedata),  //   input,  width = 32,       .writedata
		.reset      (rst_controller_reset_out_reset),                      //   input,   width = 1, reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)                   //   input,   width = 1,       .reset_req
	);

	system_iopll_0 iopll_system (
		.refclk   (clock_in_out_clk_clk),      //   input,  width = 1,  refclk.clk
		.locked   (),                          //  output,  width = 1,  locked.export
		.rst      (~reset_in_out_reset_reset), //   input,  width = 1,   reset.reset
		.outclk_0 (iopll_system_outclk0_clk),  //  output,  width = 1, outclk0.clk
		.outclk_1 (iopll_system_outclk1_clk)   //  output,  width = 1, outclk1.clk
	);

	system_jtag_uart_0 jtag_uart (
		.clk            (iopll_system_outclk0_clk),                                  //   input,   width = 1,               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                           //   input,   width = 1,             reset.reset_n
		.av_chipselect  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),  //   input,   width = 1, avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),     //   input,   width = 1,                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),       //   input,   width = 1,                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),    //  output,  width = 32,                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),      //   input,   width = 1,                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),   //   input,  width = 32,                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), //  output,   width = 1,                  .waitrequest
		.av_irq         (irq_mapper_receiver0_irq)                                   //  output,   width = 1,               irq.irq
	);

	system_pio_4 pio_key (
		.clk      (iopll_system_outclk0_clk),              //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),       //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_pio_key_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_pio_key_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (pio_key_external_connection_export)     //   input,   width = 2, external_connection.export
	);

	system_pio_3 pio_led (
		.clk        (iopll_system_outclk0_clk),                //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_pio_led_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_pio_led_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_pio_led_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_pio_led_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_pio_led_s1_readdata),   //  output,  width = 32,                    .readdata
		.out_port   (pio_led_external_connection_export)       //  output,   width = 4, external_connection.export
	);

	system_reset_in reset_in (
		.clk         (clock_in_out_clk_clk),     //   input,  width = 1,       clk.clk
		.in_reset_n  (reset_n_reset_n),          //   input,  width = 1,  in_reset.reset_n
		.out_reset_n (reset_in_out_reset_reset)  //  output,  width = 1, out_reset.reset_n
	);

	system_pio_2 sd_clk (
		.clk        (iopll_system_outclk0_clk),               //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),        //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_sd_clk_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_sd_clk_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_sd_clk_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_sd_clk_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_sd_clk_s1_readdata),   //  output,  width = 32,                    .readdata
		.out_port   (sd_clk_external_connection_export)       //  output,   width = 1, external_connection.export
	);

	system_pio_1 sd_cmd (
		.clk        (iopll_system_outclk0_clk),               //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),        //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_sd_cmd_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_sd_cmd_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_sd_cmd_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_sd_cmd_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_sd_cmd_s1_readdata),   //  output,  width = 32,                    .readdata
		.bidir_port (sd_cmd_external_connection_export)       //   inout,   width = 1, external_connection.export
	);

	system_pio_0 sd_dat (
		.clk        (iopll_system_outclk0_clk),               //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),        //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_sd_dat_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_sd_dat_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_sd_dat_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_sd_dat_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_sd_dat_s1_readdata),   //  output,  width = 32,                    .readdata
		.bidir_port (sd_dat_external_connection_export)       //   inout,   width = 4, external_connection.export
	);

	system_sysid_qsys_0 sysid_qsys (
		.clock    (iopll_system_outclk0_clk),                            //   input,   width = 1,           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //   input,   width = 1,         reset.reset_n
		.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), //  output,  width = 32, control_slave.readdata
		.address  (mm_interconnect_0_sysid_qsys_control_slave_address)   //   input,   width = 1,              .address
	);

	system_terasic_sdio_0 terasic_sdcard (
		.clk           (iopll_system_outclk1_clk),                                //   input,   width = 1,        clock.clk
		.reset_n       (~rst_controller_002_reset_out_reset),                     //   input,   width = 1,        reset.reset_n
		.avs_address   (mm_interconnect_0_terasic_sdcard_avalon_slave_address),   //   input,  width = 12, avalon_slave.address
		.avs_write     (mm_interconnect_0_terasic_sdcard_avalon_slave_write),     //   input,   width = 1,             .write
		.avs_read      (mm_interconnect_0_terasic_sdcard_avalon_slave_read),      //   input,   width = 1,             .read
		.avs_writedata (mm_interconnect_0_terasic_sdcard_avalon_slave_writedata), //   input,   width = 8,             .writedata
		.avs_readdata  (mm_interconnect_0_terasic_sdcard_avalon_slave_readdata),  //  output,   width = 8,             .readdata
		.sd_clk        (terasic_sdcard_conduit_end_sd_clk),                       //  output,   width = 1,  conduit_end.sd_clk
		.sd_cmd        (terasic_sdcard_conduit_end_sd_cmd),                       //   inout,   width = 1,             .sd_cmd
		.sd_data       (terasic_sdcard_conduit_end_sd_data)                       //   inout,   width = 4,             .sd_data
	);

	system_timer_0 timer (
		.clk        (iopll_system_outclk0_clk),              //   input,   width = 1,   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //   input,   width = 1, reset.reset_n
		.address    (mm_interconnect_0_timer_s1_address),    //   input,   width = 3,    s1.address
		.writedata  (mm_interconnect_0_timer_s1_writedata),  //   input,  width = 16,      .writedata
		.readdata   (mm_interconnect_0_timer_s1_readdata),   //  output,  width = 16,      .readdata
		.chipselect (mm_interconnect_0_timer_s1_chipselect), //   input,   width = 1,      .chipselect
		.write_n    (~mm_interconnect_0_timer_s1_write),     //   input,   width = 1,      .write_n
		.irq        (irq_mapper_receiver1_irq)               //  output,   width = 1,   irq.irq
	);

	system_altera_mm_interconnect_1920_cmrp36a mm_interconnect_0 (
		.jtag_uart_avalon_jtag_slave_address                                      (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),        //  output,   width = 1,                                        jtag_uart_avalon_jtag_slave.address
		.jtag_uart_avalon_jtag_slave_write                                        (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),          //  output,   width = 1,                                                                   .write
		.jtag_uart_avalon_jtag_slave_read                                         (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),           //  output,   width = 1,                                                                   .read
		.jtag_uart_avalon_jtag_slave_readdata                                     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),       //   input,  width = 32,                                                                   .readdata
		.jtag_uart_avalon_jtag_slave_writedata                                    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),      //  output,  width = 32,                                                                   .writedata
		.jtag_uart_avalon_jtag_slave_waitrequest                                  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest),    //   input,   width = 1,                                                                   .waitrequest
		.jtag_uart_avalon_jtag_slave_chipselect                                   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),     //  output,   width = 1,                                                                   .chipselect
		.terasic_sdcard_avalon_slave_address                                      (mm_interconnect_0_terasic_sdcard_avalon_slave_address),        //  output,  width = 12,                                        terasic_sdcard_avalon_slave.address
		.terasic_sdcard_avalon_slave_write                                        (mm_interconnect_0_terasic_sdcard_avalon_slave_write),          //  output,   width = 1,                                                                   .write
		.terasic_sdcard_avalon_slave_read                                         (mm_interconnect_0_terasic_sdcard_avalon_slave_read),           //  output,   width = 1,                                                                   .read
		.terasic_sdcard_avalon_slave_readdata                                     (mm_interconnect_0_terasic_sdcard_avalon_slave_readdata),       //   input,   width = 8,                                                                   .readdata
		.terasic_sdcard_avalon_slave_writedata                                    (mm_interconnect_0_terasic_sdcard_avalon_slave_writedata),      //  output,   width = 8,                                                                   .writedata
		.sysid_qsys_control_slave_address                                         (mm_interconnect_0_sysid_qsys_control_slave_address),           //  output,   width = 1,                                           sysid_qsys_control_slave.address
		.sysid_qsys_control_slave_readdata                                        (mm_interconnect_0_sysid_qsys_control_slave_readdata),          //   input,  width = 32,                                                                   .readdata
		.intel_niosv_m_dm_agent_address                                           (mm_interconnect_0_intel_niosv_m_dm_agent_address),             //  output,  width = 16,                                             intel_niosv_m_dm_agent.address
		.intel_niosv_m_dm_agent_write                                             (mm_interconnect_0_intel_niosv_m_dm_agent_write),               //  output,   width = 1,                                                                   .write
		.intel_niosv_m_dm_agent_read                                              (mm_interconnect_0_intel_niosv_m_dm_agent_read),                //  output,   width = 1,                                                                   .read
		.intel_niosv_m_dm_agent_readdata                                          (mm_interconnect_0_intel_niosv_m_dm_agent_readdata),            //   input,  width = 32,                                                                   .readdata
		.intel_niosv_m_dm_agent_writedata                                         (mm_interconnect_0_intel_niosv_m_dm_agent_writedata),           //  output,  width = 32,                                                                   .writedata
		.intel_niosv_m_dm_agent_readdatavalid                                     (mm_interconnect_0_intel_niosv_m_dm_agent_readdatavalid),       //   input,   width = 1,                                                                   .readdatavalid
		.intel_niosv_m_dm_agent_waitrequest                                       (mm_interconnect_0_intel_niosv_m_dm_agent_waitrequest),         //   input,   width = 1,                                                                   .waitrequest
		.intel_onchip_memory_s1_address                                           (mm_interconnect_0_intel_onchip_memory_s1_address),             //  output,  width = 17,                                             intel_onchip_memory_s1.address
		.intel_onchip_memory_s1_write                                             (mm_interconnect_0_intel_onchip_memory_s1_write),               //  output,   width = 1,                                                                   .write
		.intel_onchip_memory_s1_read                                              (mm_interconnect_0_intel_onchip_memory_s1_read),                //  output,   width = 1,                                                                   .read
		.intel_onchip_memory_s1_readdata                                          (mm_interconnect_0_intel_onchip_memory_s1_readdata),            //   input,  width = 32,                                                                   .readdata
		.intel_onchip_memory_s1_writedata                                         (mm_interconnect_0_intel_onchip_memory_s1_writedata),           //  output,  width = 32,                                                                   .writedata
		.intel_onchip_memory_s1_byteenable                                        (mm_interconnect_0_intel_onchip_memory_s1_byteenable),          //  output,   width = 4,                                                                   .byteenable
		.timer_s1_address                                                         (mm_interconnect_0_timer_s1_address),                           //  output,   width = 3,                                                           timer_s1.address
		.timer_s1_write                                                           (mm_interconnect_0_timer_s1_write),                             //  output,   width = 1,                                                                   .write
		.timer_s1_readdata                                                        (mm_interconnect_0_timer_s1_readdata),                          //   input,  width = 16,                                                                   .readdata
		.timer_s1_writedata                                                       (mm_interconnect_0_timer_s1_writedata),                         //  output,  width = 16,                                                                   .writedata
		.timer_s1_chipselect                                                      (mm_interconnect_0_timer_s1_chipselect),                        //  output,   width = 1,                                                                   .chipselect
		.sd_dat_s1_address                                                        (mm_interconnect_0_sd_dat_s1_address),                          //  output,   width = 2,                                                          sd_dat_s1.address
		.sd_dat_s1_write                                                          (mm_interconnect_0_sd_dat_s1_write),                            //  output,   width = 1,                                                                   .write
		.sd_dat_s1_readdata                                                       (mm_interconnect_0_sd_dat_s1_readdata),                         //   input,  width = 32,                                                                   .readdata
		.sd_dat_s1_writedata                                                      (mm_interconnect_0_sd_dat_s1_writedata),                        //  output,  width = 32,                                                                   .writedata
		.sd_dat_s1_chipselect                                                     (mm_interconnect_0_sd_dat_s1_chipselect),                       //  output,   width = 1,                                                                   .chipselect
		.sd_cmd_s1_address                                                        (mm_interconnect_0_sd_cmd_s1_address),                          //  output,   width = 2,                                                          sd_cmd_s1.address
		.sd_cmd_s1_write                                                          (mm_interconnect_0_sd_cmd_s1_write),                            //  output,   width = 1,                                                                   .write
		.sd_cmd_s1_readdata                                                       (mm_interconnect_0_sd_cmd_s1_readdata),                         //   input,  width = 32,                                                                   .readdata
		.sd_cmd_s1_writedata                                                      (mm_interconnect_0_sd_cmd_s1_writedata),                        //  output,  width = 32,                                                                   .writedata
		.sd_cmd_s1_chipselect                                                     (mm_interconnect_0_sd_cmd_s1_chipselect),                       //  output,   width = 1,                                                                   .chipselect
		.sd_clk_s1_address                                                        (mm_interconnect_0_sd_clk_s1_address),                          //  output,   width = 2,                                                          sd_clk_s1.address
		.sd_clk_s1_write                                                          (mm_interconnect_0_sd_clk_s1_write),                            //  output,   width = 1,                                                                   .write
		.sd_clk_s1_readdata                                                       (mm_interconnect_0_sd_clk_s1_readdata),                         //   input,  width = 32,                                                                   .readdata
		.sd_clk_s1_writedata                                                      (mm_interconnect_0_sd_clk_s1_writedata),                        //  output,  width = 32,                                                                   .writedata
		.sd_clk_s1_chipselect                                                     (mm_interconnect_0_sd_clk_s1_chipselect),                       //  output,   width = 1,                                                                   .chipselect
		.pio_led_s1_address                                                       (mm_interconnect_0_pio_led_s1_address),                         //  output,   width = 2,                                                         pio_led_s1.address
		.pio_led_s1_write                                                         (mm_interconnect_0_pio_led_s1_write),                           //  output,   width = 1,                                                                   .write
		.pio_led_s1_readdata                                                      (mm_interconnect_0_pio_led_s1_readdata),                        //   input,  width = 32,                                                                   .readdata
		.pio_led_s1_writedata                                                     (mm_interconnect_0_pio_led_s1_writedata),                       //  output,  width = 32,                                                                   .writedata
		.pio_led_s1_chipselect                                                    (mm_interconnect_0_pio_led_s1_chipselect),                      //  output,   width = 1,                                                                   .chipselect
		.pio_key_s1_address                                                       (mm_interconnect_0_pio_key_s1_address),                         //  output,   width = 2,                                                         pio_key_s1.address
		.pio_key_s1_readdata                                                      (mm_interconnect_0_pio_key_s1_readdata),                        //   input,  width = 32,                                                                   .readdata
		.intel_niosv_m_timer_sw_agent_address                                     (mm_interconnect_0_intel_niosv_m_timer_sw_agent_address),       //  output,   width = 6,                                       intel_niosv_m_timer_sw_agent.address
		.intel_niosv_m_timer_sw_agent_write                                       (mm_interconnect_0_intel_niosv_m_timer_sw_agent_write),         //  output,   width = 1,                                                                   .write
		.intel_niosv_m_timer_sw_agent_read                                        (mm_interconnect_0_intel_niosv_m_timer_sw_agent_read),          //  output,   width = 1,                                                                   .read
		.intel_niosv_m_timer_sw_agent_readdata                                    (mm_interconnect_0_intel_niosv_m_timer_sw_agent_readdata),      //   input,  width = 32,                                                                   .readdata
		.intel_niosv_m_timer_sw_agent_writedata                                   (mm_interconnect_0_intel_niosv_m_timer_sw_agent_writedata),     //  output,  width = 32,                                                                   .writedata
		.intel_niosv_m_timer_sw_agent_byteenable                                  (mm_interconnect_0_intel_niosv_m_timer_sw_agent_byteenable),    //  output,   width = 4,                                                                   .byteenable
		.intel_niosv_m_timer_sw_agent_readdatavalid                               (mm_interconnect_0_intel_niosv_m_timer_sw_agent_readdatavalid), //   input,   width = 1,                                                                   .readdatavalid
		.intel_niosv_m_timer_sw_agent_waitrequest                                 (mm_interconnect_0_intel_niosv_m_timer_sw_agent_waitrequest),   //   input,   width = 1,                                                                   .waitrequest
		.intel_niosv_m_data_manager_awaddr                                        (intel_niosv_m_data_manager_awaddr),                            //   input,  width = 32,                                         intel_niosv_m_data_manager.awaddr
		.intel_niosv_m_data_manager_awprot                                        (intel_niosv_m_data_manager_awprot),                            //   input,   width = 3,                                                                   .awprot
		.intel_niosv_m_data_manager_awvalid                                       (intel_niosv_m_data_manager_awvalid),                           //   input,   width = 1,                                                                   .awvalid
		.intel_niosv_m_data_manager_awready                                       (intel_niosv_m_data_manager_awready),                           //  output,   width = 1,                                                                   .awready
		.intel_niosv_m_data_manager_wdata                                         (intel_niosv_m_data_manager_wdata),                             //   input,  width = 32,                                                                   .wdata
		.intel_niosv_m_data_manager_wstrb                                         (intel_niosv_m_data_manager_wstrb),                             //   input,   width = 4,                                                                   .wstrb
		.intel_niosv_m_data_manager_wvalid                                        (intel_niosv_m_data_manager_wvalid),                            //   input,   width = 1,                                                                   .wvalid
		.intel_niosv_m_data_manager_wready                                        (intel_niosv_m_data_manager_wready),                            //  output,   width = 1,                                                                   .wready
		.intel_niosv_m_data_manager_bresp                                         (intel_niosv_m_data_manager_bresp),                             //  output,   width = 2,                                                                   .bresp
		.intel_niosv_m_data_manager_bvalid                                        (intel_niosv_m_data_manager_bvalid),                            //  output,   width = 1,                                                                   .bvalid
		.intel_niosv_m_data_manager_bready                                        (intel_niosv_m_data_manager_bready),                            //   input,   width = 1,                                                                   .bready
		.intel_niosv_m_data_manager_araddr                                        (intel_niosv_m_data_manager_araddr),                            //   input,  width = 32,                                                                   .araddr
		.intel_niosv_m_data_manager_arprot                                        (intel_niosv_m_data_manager_arprot),                            //   input,   width = 3,                                                                   .arprot
		.intel_niosv_m_data_manager_arvalid                                       (intel_niosv_m_data_manager_arvalid),                           //   input,   width = 1,                                                                   .arvalid
		.intel_niosv_m_data_manager_arready                                       (intel_niosv_m_data_manager_arready),                           //  output,   width = 1,                                                                   .arready
		.intel_niosv_m_data_manager_rdata                                         (intel_niosv_m_data_manager_rdata),                             //  output,  width = 32,                                                                   .rdata
		.intel_niosv_m_data_manager_rresp                                         (intel_niosv_m_data_manager_rresp),                             //  output,   width = 2,                                                                   .rresp
		.intel_niosv_m_data_manager_rvalid                                        (intel_niosv_m_data_manager_rvalid),                            //  output,   width = 1,                                                                   .rvalid
		.intel_niosv_m_data_manager_rready                                        (intel_niosv_m_data_manager_rready),                            //   input,   width = 1,                                                                   .rready
		.intel_niosv_m_instruction_manager_awaddr                                 (intel_niosv_m_instruction_manager_awaddr),                     //   input,  width = 32,                                  intel_niosv_m_instruction_manager.awaddr
		.intel_niosv_m_instruction_manager_awprot                                 (intel_niosv_m_instruction_manager_awprot),                     //   input,   width = 3,                                                                   .awprot
		.intel_niosv_m_instruction_manager_awvalid                                (intel_niosv_m_instruction_manager_awvalid),                    //   input,   width = 1,                                                                   .awvalid
		.intel_niosv_m_instruction_manager_awready                                (intel_niosv_m_instruction_manager_awready),                    //  output,   width = 1,                                                                   .awready
		.intel_niosv_m_instruction_manager_wdata                                  (intel_niosv_m_instruction_manager_wdata),                      //   input,  width = 32,                                                                   .wdata
		.intel_niosv_m_instruction_manager_wstrb                                  (intel_niosv_m_instruction_manager_wstrb),                      //   input,   width = 4,                                                                   .wstrb
		.intel_niosv_m_instruction_manager_wvalid                                 (intel_niosv_m_instruction_manager_wvalid),                     //   input,   width = 1,                                                                   .wvalid
		.intel_niosv_m_instruction_manager_wready                                 (intel_niosv_m_instruction_manager_wready),                     //  output,   width = 1,                                                                   .wready
		.intel_niosv_m_instruction_manager_bresp                                  (intel_niosv_m_instruction_manager_bresp),                      //  output,   width = 2,                                                                   .bresp
		.intel_niosv_m_instruction_manager_bvalid                                 (intel_niosv_m_instruction_manager_bvalid),                     //  output,   width = 1,                                                                   .bvalid
		.intel_niosv_m_instruction_manager_bready                                 (intel_niosv_m_instruction_manager_bready),                     //   input,   width = 1,                                                                   .bready
		.intel_niosv_m_instruction_manager_araddr                                 (intel_niosv_m_instruction_manager_araddr),                     //   input,  width = 32,                                                                   .araddr
		.intel_niosv_m_instruction_manager_arprot                                 (intel_niosv_m_instruction_manager_arprot),                     //   input,   width = 3,                                                                   .arprot
		.intel_niosv_m_instruction_manager_arvalid                                (intel_niosv_m_instruction_manager_arvalid),                    //   input,   width = 1,                                                                   .arvalid
		.intel_niosv_m_instruction_manager_arready                                (intel_niosv_m_instruction_manager_arready),                    //  output,   width = 1,                                                                   .arready
		.intel_niosv_m_instruction_manager_rdata                                  (intel_niosv_m_instruction_manager_rdata),                      //  output,  width = 32,                                                                   .rdata
		.intel_niosv_m_instruction_manager_rresp                                  (intel_niosv_m_instruction_manager_rresp),                      //  output,   width = 2,                                                                   .rresp
		.intel_niosv_m_instruction_manager_rvalid                                 (intel_niosv_m_instruction_manager_rvalid),                     //  output,   width = 1,                                                                   .rvalid
		.intel_niosv_m_instruction_manager_rready                                 (intel_niosv_m_instruction_manager_rready),                     //   input,   width = 1,                                                                   .rready
		.intel_niosv_m_reset_reset_bridge_in_reset_reset                          (rst_controller_003_reset_out_reset),                           //   input,   width = 1,                          intel_niosv_m_reset_reset_bridge_in_reset.reset
		.terasic_sdcard_reset_reset_bridge_in_reset_reset                         (rst_controller_004_reset_out_reset),                           //   input,   width = 1,                         terasic_sdcard_reset_reset_bridge_in_reset.reset
		.jtag_uart_avalon_jtag_slave_translator_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset),                           //   input,   width = 1, jtag_uart_avalon_jtag_slave_translator_reset_reset_bridge_in_reset.reset
		.terasic_sdcard_avalon_slave_translator_reset_reset_bridge_in_reset_reset (rst_controller_004_reset_out_reset),                           //   input,   width = 1, terasic_sdcard_avalon_slave_translator_reset_reset_bridge_in_reset.reset
		.iopll_system_outclk0_clk                                                 (iopll_system_outclk0_clk),                                     //   input,   width = 1,                                               iopll_system_outclk0.clk
		.iopll_system_outclk1_clk                                                 (iopll_system_outclk1_clk)                                      //   input,   width = 1,                                               iopll_system_outclk1.clk
	);

	system_altera_irq_mapper_2001_qylhc4a irq_mapper (
		.clk           (iopll_system_outclk0_clk),          //   input,   width = 1,       clk.clk
		.reset         (rst_controller_reset_out_reset),    //   input,   width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),          //   input,   width = 1, receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),          //   input,   width = 1, receiver1.irq
		.sender_irq    (intel_niosv_m_platform_irq_rx_irq)  //  output,  width = 16,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_in_out_reset_reset),          //   input,  width = 1, reset_in0.reset
		.clk            (iopll_system_outclk0_clk),           //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset),     //  output,  width = 1, reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req), //  output,  width = 1,          .reset_req
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (intel_niosv_m_dbg_reset_out_reset),  //   input,  width = 1, reset_in0.reset
		.reset_in1      (~reset_in_out_reset_reset),          //   input,  width = 1, reset_in1.reset
		.clk            (iopll_system_outclk0_clk),           //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_002 (
		.reset_in0      (~reset_in_out_reset_reset),          //   input,  width = 1, reset_in0.reset
		.clk            (iopll_system_outclk1_clk),           //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_002_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_003 (
		.reset_in0      (~reset_in_out_reset_reset),          //   input,  width = 1, reset_in0.reset
		.clk            (iopll_system_outclk0_clk),           //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_003_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_004 (
		.reset_in0      (~reset_in_out_reset_reset),          //   input,  width = 1, reset_in0.reset
		.clk            (iopll_system_outclk1_clk),           //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_004_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
