// nios_system_intel_vvp_vfr_0_altera_mm_interconnect_1920_azourty.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_vfr_0_altera_mm_interconnect_1920_azourty (
		input  wire [8:0]  ro_reg_servicer_av_mm_master_address,                                      //                                        ro_reg_servicer_av_mm_master.address
		output wire        ro_reg_servicer_av_mm_master_waitrequest,                                  //                                                                    .waitrequest
		input  wire [3:0]  ro_reg_servicer_av_mm_master_byteenable,                                   //                                                                    .byteenable
		input  wire        ro_reg_servicer_av_mm_master_read,                                         //                                                                    .read
		output wire [31:0] ro_reg_servicer_av_mm_master_readdata,                                     //                                                                    .readdata
		output wire        ro_reg_servicer_av_mm_master_readdatavalid,                                //                                                                    .readdatavalid
		input  wire        ro_reg_servicer_av_mm_master_write,                                        //                                                                    .write
		input  wire [31:0] ro_reg_servicer_av_mm_master_writedata,                                    //                                                                    .writedata
		output wire [6:0]  scheduler_av_mm_agent_address,                                             //                                               scheduler_av_mm_agent.address
		output wire        scheduler_av_mm_agent_write,                                               //                                                                    .write
		output wire        scheduler_av_mm_agent_read,                                                //                                                                    .read
		input  wire [31:0] scheduler_av_mm_agent_readdata,                                            //                                                                    .readdata
		output wire [31:0] scheduler_av_mm_agent_writedata,                                           //                                                                    .writedata
		output wire [3:0]  scheduler_av_mm_agent_byteenable,                                          //                                                                    .byteenable
		input  wire        scheduler_av_mm_agent_readdatavalid,                                       //                                                                    .readdatavalid
		input  wire        scheduler_av_mm_agent_waitrequest,                                         //                                                                    .waitrequest
		input  wire        ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset, // ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset,        //        scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        mm_clk_bridge_out_clk_clk,                                                 //                                               mm_clk_bridge_out_clk.clk,          Clock Input
		input  wire        axi_st_clk_bridge_out_clk_clk                                              //                                           axi_st_clk_bridge_out_clk.clk,          Clock Input
	);

	wire          ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_waitrequest;   // ro_reg_servicer_av_mm_master_agent:av_waitrequest -> ro_reg_servicer_av_mm_master_translator:uav_waitrequest
	wire   [31:0] ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_readdata;      // ro_reg_servicer_av_mm_master_agent:av_readdata -> ro_reg_servicer_av_mm_master_translator:uav_readdata
	wire          ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_debugaccess;   // ro_reg_servicer_av_mm_master_translator:uav_debugaccess -> ro_reg_servicer_av_mm_master_agent:av_debugaccess
	wire    [8:0] ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_address;       // ro_reg_servicer_av_mm_master_translator:uav_address -> ro_reg_servicer_av_mm_master_agent:av_address
	wire          ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_read;          // ro_reg_servicer_av_mm_master_translator:uav_read -> ro_reg_servicer_av_mm_master_agent:av_read
	wire    [3:0] ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_byteenable;    // ro_reg_servicer_av_mm_master_translator:uav_byteenable -> ro_reg_servicer_av_mm_master_agent:av_byteenable
	wire          ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_readdatavalid; // ro_reg_servicer_av_mm_master_agent:av_readdatavalid -> ro_reg_servicer_av_mm_master_translator:uav_readdatavalid
	wire          ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_lock;          // ro_reg_servicer_av_mm_master_translator:uav_lock -> ro_reg_servicer_av_mm_master_agent:av_lock
	wire          ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_write;         // ro_reg_servicer_av_mm_master_translator:uav_write -> ro_reg_servicer_av_mm_master_agent:av_write
	wire   [31:0] ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_writedata;     // ro_reg_servicer_av_mm_master_translator:uav_writedata -> ro_reg_servicer_av_mm_master_agent:av_writedata
	wire    [2:0] ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_burstcount;    // ro_reg_servicer_av_mm_master_translator:uav_burstcount -> ro_reg_servicer_av_mm_master_agent:av_burstcount
	wire          rsp_mux_src_valid;                                                               // rsp_mux:src_valid -> ro_reg_servicer_av_mm_master_agent:rp_valid
	wire  [105:0] rsp_mux_src_data;                                                                // rsp_mux:src_data -> ro_reg_servicer_av_mm_master_agent:rp_data
	wire          rsp_mux_src_ready;                                                               // ro_reg_servicer_av_mm_master_agent:rp_ready -> rsp_mux:src_ready
	wire    [0:0] rsp_mux_src_channel;                                                             // rsp_mux:src_channel -> ro_reg_servicer_av_mm_master_agent:rp_channel
	wire          rsp_mux_src_startofpacket;                                                       // rsp_mux:src_startofpacket -> ro_reg_servicer_av_mm_master_agent:rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                                         // rsp_mux:src_endofpacket -> ro_reg_servicer_av_mm_master_agent:rp_endofpacket
	wire   [31:0] scheduler_av_mm_agent_agent_m0_readdata;                                         // scheduler_av_mm_agent_translator:uav_readdata -> scheduler_av_mm_agent_agent:m0_readdata
	wire          scheduler_av_mm_agent_agent_m0_waitrequest;                                      // scheduler_av_mm_agent_translator:uav_waitrequest -> scheduler_av_mm_agent_agent:m0_waitrequest
	wire          scheduler_av_mm_agent_agent_m0_debugaccess;                                      // scheduler_av_mm_agent_agent:m0_debugaccess -> scheduler_av_mm_agent_translator:uav_debugaccess
	wire    [8:0] scheduler_av_mm_agent_agent_m0_address;                                          // scheduler_av_mm_agent_agent:m0_address -> scheduler_av_mm_agent_translator:uav_address
	wire    [3:0] scheduler_av_mm_agent_agent_m0_byteenable;                                       // scheduler_av_mm_agent_agent:m0_byteenable -> scheduler_av_mm_agent_translator:uav_byteenable
	wire          scheduler_av_mm_agent_agent_m0_read;                                             // scheduler_av_mm_agent_agent:m0_read -> scheduler_av_mm_agent_translator:uav_read
	wire          scheduler_av_mm_agent_agent_m0_readdatavalid;                                    // scheduler_av_mm_agent_translator:uav_readdatavalid -> scheduler_av_mm_agent_agent:m0_readdatavalid
	wire          scheduler_av_mm_agent_agent_m0_lock;                                             // scheduler_av_mm_agent_agent:m0_lock -> scheduler_av_mm_agent_translator:uav_lock
	wire   [31:0] scheduler_av_mm_agent_agent_m0_writedata;                                        // scheduler_av_mm_agent_agent:m0_writedata -> scheduler_av_mm_agent_translator:uav_writedata
	wire          scheduler_av_mm_agent_agent_m0_write;                                            // scheduler_av_mm_agent_agent:m0_write -> scheduler_av_mm_agent_translator:uav_write
	wire    [2:0] scheduler_av_mm_agent_agent_m0_burstcount;                                       // scheduler_av_mm_agent_agent:m0_burstcount -> scheduler_av_mm_agent_translator:uav_burstcount
	wire          scheduler_av_mm_agent_agent_rf_source_valid;                                     // scheduler_av_mm_agent_agent:rf_source_valid -> scheduler_av_mm_agent_agent_rsp_fifo:in_valid
	wire  [106:0] scheduler_av_mm_agent_agent_rf_source_data;                                      // scheduler_av_mm_agent_agent:rf_source_data -> scheduler_av_mm_agent_agent_rsp_fifo:in_data
	wire          scheduler_av_mm_agent_agent_rf_source_ready;                                     // scheduler_av_mm_agent_agent_rsp_fifo:in_ready -> scheduler_av_mm_agent_agent:rf_source_ready
	wire          scheduler_av_mm_agent_agent_rf_source_startofpacket;                             // scheduler_av_mm_agent_agent:rf_source_startofpacket -> scheduler_av_mm_agent_agent_rsp_fifo:in_startofpacket
	wire          scheduler_av_mm_agent_agent_rf_source_endofpacket;                               // scheduler_av_mm_agent_agent:rf_source_endofpacket -> scheduler_av_mm_agent_agent_rsp_fifo:in_endofpacket
	wire          scheduler_av_mm_agent_agent_rsp_fifo_out_valid;                                  // scheduler_av_mm_agent_agent_rsp_fifo:out_valid -> scheduler_av_mm_agent_agent:rf_sink_valid
	wire  [106:0] scheduler_av_mm_agent_agent_rsp_fifo_out_data;                                   // scheduler_av_mm_agent_agent_rsp_fifo:out_data -> scheduler_av_mm_agent_agent:rf_sink_data
	wire          scheduler_av_mm_agent_agent_rsp_fifo_out_ready;                                  // scheduler_av_mm_agent_agent:rf_sink_ready -> scheduler_av_mm_agent_agent_rsp_fifo:out_ready
	wire          scheduler_av_mm_agent_agent_rsp_fifo_out_startofpacket;                          // scheduler_av_mm_agent_agent_rsp_fifo:out_startofpacket -> scheduler_av_mm_agent_agent:rf_sink_startofpacket
	wire          scheduler_av_mm_agent_agent_rsp_fifo_out_endofpacket;                            // scheduler_av_mm_agent_agent_rsp_fifo:out_endofpacket -> scheduler_av_mm_agent_agent:rf_sink_endofpacket
	wire          scheduler_av_mm_agent_agent_rdata_fifo_src_valid;                                // scheduler_av_mm_agent_agent:rdata_fifo_src_valid -> scheduler_av_mm_agent_agent_rdata_fifo:in_valid
	wire   [33:0] scheduler_av_mm_agent_agent_rdata_fifo_src_data;                                 // scheduler_av_mm_agent_agent:rdata_fifo_src_data -> scheduler_av_mm_agent_agent_rdata_fifo:in_data
	wire          scheduler_av_mm_agent_agent_rdata_fifo_src_ready;                                // scheduler_av_mm_agent_agent_rdata_fifo:in_ready -> scheduler_av_mm_agent_agent:rdata_fifo_src_ready
	wire          scheduler_av_mm_agent_agent_rdata_fifo_out_valid;                                // scheduler_av_mm_agent_agent_rdata_fifo:out_valid -> scheduler_av_mm_agent_agent:rdata_fifo_sink_valid
	wire   [33:0] scheduler_av_mm_agent_agent_rdata_fifo_out_data;                                 // scheduler_av_mm_agent_agent_rdata_fifo:out_data -> scheduler_av_mm_agent_agent:rdata_fifo_sink_data
	wire          scheduler_av_mm_agent_agent_rdata_fifo_out_ready;                                // scheduler_av_mm_agent_agent:rdata_fifo_sink_ready -> scheduler_av_mm_agent_agent_rdata_fifo:out_ready
	wire          cmd_mux_src_valid;                                                               // cmd_mux:src_valid -> scheduler_av_mm_agent_agent:cp_valid
	wire  [105:0] cmd_mux_src_data;                                                                // cmd_mux:src_data -> scheduler_av_mm_agent_agent:cp_data
	wire          cmd_mux_src_ready;                                                               // scheduler_av_mm_agent_agent:cp_ready -> cmd_mux:src_ready
	wire    [0:0] cmd_mux_src_channel;                                                             // cmd_mux:src_channel -> scheduler_av_mm_agent_agent:cp_channel
	wire          cmd_mux_src_startofpacket;                                                       // cmd_mux:src_startofpacket -> scheduler_av_mm_agent_agent:cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                         // cmd_mux:src_endofpacket -> scheduler_av_mm_agent_agent:cp_endofpacket
	wire          ro_reg_servicer_av_mm_master_agent_cp_valid;                                     // ro_reg_servicer_av_mm_master_agent:cp_valid -> router:sink_valid
	wire  [105:0] ro_reg_servicer_av_mm_master_agent_cp_data;                                      // ro_reg_servicer_av_mm_master_agent:cp_data -> router:sink_data
	wire          ro_reg_servicer_av_mm_master_agent_cp_ready;                                     // router:sink_ready -> ro_reg_servicer_av_mm_master_agent:cp_ready
	wire          ro_reg_servicer_av_mm_master_agent_cp_startofpacket;                             // ro_reg_servicer_av_mm_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          ro_reg_servicer_av_mm_master_agent_cp_endofpacket;                               // ro_reg_servicer_av_mm_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                // router:src_valid -> cmd_demux:sink_valid
	wire  [105:0] router_src_data;                                                                 // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                                // cmd_demux:sink_ready -> router:src_ready
	wire    [0:0] router_src_channel;                                                              // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                                        // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                                          // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          scheduler_av_mm_agent_agent_rp_valid;                                            // scheduler_av_mm_agent_agent:rp_valid -> router_001:sink_valid
	wire  [105:0] scheduler_av_mm_agent_agent_rp_data;                                             // scheduler_av_mm_agent_agent:rp_data -> router_001:sink_data
	wire          scheduler_av_mm_agent_agent_rp_ready;                                            // router_001:sink_ready -> scheduler_av_mm_agent_agent:rp_ready
	wire          scheduler_av_mm_agent_agent_rp_startofpacket;                                    // scheduler_av_mm_agent_agent:rp_startofpacket -> router_001:sink_startofpacket
	wire          scheduler_av_mm_agent_agent_rp_endofpacket;                                      // scheduler_av_mm_agent_agent:rp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                            // router_001:src_valid -> rsp_demux:sink_valid
	wire  [105:0] router_001_src_data;                                                             // router_001:src_data -> rsp_demux:sink_data
	wire          router_001_src_ready;                                                            // rsp_demux:sink_ready -> router_001:src_ready
	wire    [0:0] router_001_src_channel;                                                          // router_001:src_channel -> rsp_demux:sink_channel
	wire          router_001_src_startofpacket;                                                    // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_001_src_endofpacket;                                                      // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                            // cmd_demux:src0_valid -> crosser:in_valid
	wire  [105:0] cmd_demux_src0_data;                                                             // cmd_demux:src0_data -> crosser:in_data
	wire          cmd_demux_src0_ready;                                                            // crosser:in_ready -> cmd_demux:src0_ready
	wire    [0:0] cmd_demux_src0_channel;                                                          // cmd_demux:src0_channel -> crosser:in_channel
	wire          cmd_demux_src0_startofpacket;                                                    // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                      // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
	wire          crosser_out_valid;                                                               // crosser:out_valid -> cmd_mux:sink0_valid
	wire  [105:0] crosser_out_data;                                                                // crosser:out_data -> cmd_mux:sink0_data
	wire          crosser_out_ready;                                                               // cmd_mux:sink0_ready -> crosser:out_ready
	wire    [0:0] crosser_out_channel;                                                             // crosser:out_channel -> cmd_mux:sink0_channel
	wire          crosser_out_startofpacket;                                                       // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          crosser_out_endofpacket;                                                         // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                            // rsp_demux:src0_valid -> crosser_001:in_valid
	wire  [105:0] rsp_demux_src0_data;                                                             // rsp_demux:src0_data -> crosser_001:in_data
	wire          rsp_demux_src0_ready;                                                            // crosser_001:in_ready -> rsp_demux:src0_ready
	wire    [0:0] rsp_demux_src0_channel;                                                          // rsp_demux:src0_channel -> crosser_001:in_channel
	wire          rsp_demux_src0_startofpacket;                                                    // rsp_demux:src0_startofpacket -> crosser_001:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                      // rsp_demux:src0_endofpacket -> crosser_001:in_endofpacket
	wire          crosser_001_out_valid;                                                           // crosser_001:out_valid -> rsp_mux:sink0_valid
	wire  [105:0] crosser_001_out_data;                                                            // crosser_001:out_data -> rsp_mux:sink0_data
	wire          crosser_001_out_ready;                                                           // rsp_mux:sink0_ready -> crosser_001:out_ready
	wire    [0:0] crosser_001_out_channel;                                                         // crosser_001:out_channel -> rsp_mux:sink0_channel
	wire          crosser_001_out_startofpacket;                                                   // crosser_001:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          crosser_001_out_endofpacket;                                                     // crosser_001:out_endofpacket -> rsp_mux:sink0_endofpacket

	nios_system_intel_vvp_vfr_0_altera_merlin_master_translator_193_lgcew2q #(
		.AV_ADDRESS_W                (9),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (9),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (0),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) ro_reg_servicer_av_mm_master_translator (
		.clk                    (mm_clk_bridge_out_clk_clk),                                                       //   input,   width = 1,                       clk.clk
		.reset                  (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset),       //   input,   width = 1,                     reset.reset
		.uav_address            (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_address),       //  output,   width = 9, avalon_universal_master_0.address
		.uav_burstcount         (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (ro_reg_servicer_av_mm_master_address),                                            //   input,   width = 9,      avalon_anti_master_0.address
		.av_waitrequest         (ro_reg_servicer_av_mm_master_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_byteenable          (ro_reg_servicer_av_mm_master_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (ro_reg_servicer_av_mm_master_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (ro_reg_servicer_av_mm_master_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (ro_reg_servicer_av_mm_master_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (ro_reg_servicer_av_mm_master_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (ro_reg_servicer_av_mm_master_writedata),                                          //   input,  width = 32,                          .writedata
		.av_burstcount          (1'b1),                                                                            // (terminated),                                        
		.av_beginbursttransfer  (1'b0),                                                                            // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                            // (terminated),                                        
		.av_chipselect          (1'b0),                                                                            // (terminated),                                        
		.av_lock                (1'b0),                                                                            // (terminated),                                        
		.av_debugaccess         (1'b0),                                                                            // (terminated),                                        
		.uav_outputenable       (1'b0),                                                                            // (terminated),                                        
		.uav_clken              (),                                                                                // (terminated),                                        
		.av_clken               (1'b1),                                                                            // (terminated),                                        
		.uav_response           (2'b00),                                                                           // (terminated),                                        
		.av_response            (),                                                                                // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                            // (terminated),                                        
		.av_writeresponsevalid  ()                                                                                 // (terminated),                                        
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (7),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (9),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (0)
	) scheduler_av_mm_agent_translator (
		.clk                    (axi_st_clk_bridge_out_clk_clk),                                      //   input,   width = 1,                      clk.clk
		.reset                  (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (scheduler_av_mm_agent_agent_m0_address),                             //   input,   width = 9, avalon_universal_slave_0.address
		.uav_burstcount         (scheduler_av_mm_agent_agent_m0_burstcount),                          //   input,   width = 3,                         .burstcount
		.uav_read               (scheduler_av_mm_agent_agent_m0_read),                                //   input,   width = 1,                         .read
		.uav_write              (scheduler_av_mm_agent_agent_m0_write),                               //   input,   width = 1,                         .write
		.uav_waitrequest        (scheduler_av_mm_agent_agent_m0_waitrequest),                         //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (scheduler_av_mm_agent_agent_m0_readdatavalid),                       //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (scheduler_av_mm_agent_agent_m0_byteenable),                          //   input,   width = 4,                         .byteenable
		.uav_readdata           (scheduler_av_mm_agent_agent_m0_readdata),                            //  output,  width = 32,                         .readdata
		.uav_writedata          (scheduler_av_mm_agent_agent_m0_writedata),                           //   input,  width = 32,                         .writedata
		.uav_lock               (scheduler_av_mm_agent_agent_m0_lock),                                //   input,   width = 1,                         .lock
		.uav_debugaccess        (scheduler_av_mm_agent_agent_m0_debugaccess),                         //   input,   width = 1,                         .debugaccess
		.av_address             (scheduler_av_mm_agent_address),                                      //  output,   width = 7,      avalon_anti_slave_0.address
		.av_write               (scheduler_av_mm_agent_write),                                        //  output,   width = 1,                         .write
		.av_read                (scheduler_av_mm_agent_read),                                         //  output,   width = 1,                         .read
		.av_readdata            (scheduler_av_mm_agent_readdata),                                     //   input,  width = 32,                         .readdata
		.av_writedata           (scheduler_av_mm_agent_writedata),                                    //  output,  width = 32,                         .writedata
		.av_byteenable          (scheduler_av_mm_agent_byteenable),                                   //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (scheduler_av_mm_agent_readdatavalid),                                //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (scheduler_av_mm_agent_waitrequest),                                  //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                                   // (terminated),                                       
		.av_beginbursttransfer  (),                                                                   // (terminated),                                       
		.av_burstcount          (),                                                                   // (terminated),                                       
		.av_writebyteenable     (),                                                                   // (terminated),                                       
		.av_lock                (),                                                                   // (terminated),                                       
		.av_chipselect          (),                                                                   // (terminated),                                       
		.av_clken               (),                                                                   // (terminated),                                       
		.uav_clken              (1'b0),                                                               // (terminated),                                       
		.av_debugaccess         (),                                                                   // (terminated),                                       
		.av_outputenable        (),                                                                   // (terminated),                                       
		.uav_response           (),                                                                   // (terminated),                                       
		.av_response            (2'b00),                                                              // (terminated),                                       
		.uav_writeresponsevalid (),                                                                   // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                // (terminated),                                       
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_master_agent_1931_jtx3eyy #(
		.PKT_WUNIQUE               (87),
		.PKT_DOMAIN_H              (86),
		.PKT_DOMAIN_L              (85),
		.PKT_SNOOP_H               (84),
		.PKT_SNOOP_L               (81),
		.PKT_BARRIER_H             (80),
		.PKT_BARRIER_L             (79),
		.PKT_ORI_BURST_SIZE_H      (78),
		.PKT_ORI_BURST_SIZE_L      (76),
		.PKT_RESPONSE_STATUS_H     (75),
		.PKT_RESPONSE_STATUS_L     (74),
		.PKT_QOS_H                 (63),
		.PKT_QOS_L                 (63),
		.PKT_DATA_SIDEBAND_H       (61),
		.PKT_DATA_SIDEBAND_L       (61),
		.PKT_ADDR_SIDEBAND_H       (60),
		.PKT_ADDR_SIDEBAND_L       (60),
		.PKT_BURST_TYPE_H          (59),
		.PKT_BURST_TYPE_L          (58),
		.PKT_CACHE_H               (73),
		.PKT_CACHE_L               (70),
		.PKT_THREAD_ID_H           (66),
		.PKT_THREAD_ID_L           (66),
		.PKT_BURST_SIZE_H          (57),
		.PKT_BURST_SIZE_L          (55),
		.PKT_TRANS_EXCLUSIVE       (50),
		.PKT_TRANS_LOCK            (49),
		.PKT_BEGIN_BURST           (62),
		.PKT_PROTECTION_H          (69),
		.PKT_PROTECTION_L          (67),
		.PKT_BURSTWRAP_H           (54),
		.PKT_BURSTWRAP_L           (54),
		.PKT_BYTE_CNT_H            (53),
		.PKT_BYTE_CNT_L            (51),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (64),
		.PKT_SRC_ID_L              (64),
		.PKT_DEST_ID_H             (65),
		.PKT_DEST_ID_L             (65),
		.PKT_POISON_H              (88),
		.PKT_POISON_L              (88),
		.PKT_DATACHK_H             (89),
		.PKT_DATACHK_L             (89),
		.PKT_ADDRCHK_H             (92),
		.PKT_ADDRCHK_L             (91),
		.PKT_SAI_H                 (93),
		.PKT_SAI_L                 (93),
		.PKT_USER_DATA_H           (90),
		.PKT_USER_DATA_L           (90),
		.PKT_ATRACE                (103),
		.PKT_TRACE                 (104),
		.PKT_AWAKEUP               (105),
		.ST_DATA_W                 (106),
		.ST_CHANNEL_W              (1),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (0),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (1),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.OPTIMIZED_READS_WITH_BE   (0)
	) ro_reg_servicer_av_mm_master_agent (
		.clk                   (mm_clk_bridge_out_clk_clk),                                                       //   input,    width = 1,       clk.clk
		.reset                 (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset),       //   input,    width = 1, clk_reset.reset
		.av_address            (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_address),       //   input,    width = 9,        av.address
		.av_write              (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (ro_reg_servicer_av_mm_master_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (ro_reg_servicer_av_mm_master_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (ro_reg_servicer_av_mm_master_agent_cp_data),                                      //  output,  width = 106,          .data
		.cp_startofpacket      (ro_reg_servicer_av_mm_master_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (ro_reg_servicer_av_mm_master_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (ro_reg_servicer_av_mm_master_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (rsp_mux_src_valid),                                                               //   input,    width = 1,        rp.valid
		.rp_data               (rsp_mux_src_data),                                                                //   input,  width = 106,          .data
		.rp_channel            (rsp_mux_src_channel),                                                             //   input,    width = 1,          .channel
		.rp_startofpacket      (rsp_mux_src_startofpacket),                                                       //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (rsp_mux_src_endofpacket),                                                         //   input,    width = 1,          .endofpacket
		.rp_ready              (rsp_mux_src_ready),                                                               //  output,    width = 1,          .ready
		.av_response           (),                                                                                // (terminated),                         
		.av_writeresponsevalid ()                                                                                 // (terminated),                         
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (78),
		.PKT_ORI_BURST_SIZE_L      (76),
		.PKT_RESPONSE_STATUS_H     (75),
		.PKT_RESPONSE_STATUS_L     (74),
		.PKT_BURST_SIZE_H          (57),
		.PKT_BURST_SIZE_L          (55),
		.PKT_TRANS_LOCK            (49),
		.PKT_BEGIN_BURST           (62),
		.PKT_PROTECTION_H          (69),
		.PKT_PROTECTION_L          (67),
		.PKT_BURSTWRAP_H           (54),
		.PKT_BURSTWRAP_L           (54),
		.PKT_BYTE_CNT_H            (53),
		.PKT_BYTE_CNT_L            (51),
		.PKT_ADDR_H                (44),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (45),
		.PKT_TRANS_POSTED          (46),
		.PKT_TRANS_WRITE           (47),
		.PKT_TRANS_READ            (48),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (64),
		.PKT_SRC_ID_L              (64),
		.PKT_DEST_ID_H             (65),
		.PKT_DEST_ID_L             (65),
		.PKT_POISON_H              (88),
		.PKT_POISON_L              (88),
		.PKT_DATACHK_H             (89),
		.PKT_DATACHK_L             (89),
		.PKT_SAI_H                 (93),
		.PKT_SAI_L                 (93),
		.PKT_ADDRCHK_H             (92),
		.PKT_ADDRCHK_L             (91),
		.PKT_USER_DATA_H           (90),
		.PKT_USER_DATA_L           (90),
		.PKT_ATRACE                (103),
		.PKT_TRACE                 (104),
		.PKT_AWAKEUP               (105),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (1),
		.ST_DATA_W                 (106),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (0),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (0),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) scheduler_av_mm_agent_agent (
		.clk                     (axi_st_clk_bridge_out_clk_clk),                                      //   input,    width = 1,             clk.clk
		.reset                   (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (scheduler_av_mm_agent_agent_m0_address),                             //  output,    width = 9,              m0.address
		.m0_burstcount           (scheduler_av_mm_agent_agent_m0_burstcount),                          //  output,    width = 3,                .burstcount
		.m0_byteenable           (scheduler_av_mm_agent_agent_m0_byteenable),                          //  output,    width = 4,                .byteenable
		.m0_debugaccess          (scheduler_av_mm_agent_agent_m0_debugaccess),                         //  output,    width = 1,                .debugaccess
		.m0_lock                 (scheduler_av_mm_agent_agent_m0_lock),                                //  output,    width = 1,                .lock
		.m0_readdata             (scheduler_av_mm_agent_agent_m0_readdata),                            //   input,   width = 32,                .readdata
		.m0_readdatavalid        (scheduler_av_mm_agent_agent_m0_readdatavalid),                       //   input,    width = 1,                .readdatavalid
		.m0_read                 (scheduler_av_mm_agent_agent_m0_read),                                //  output,    width = 1,                .read
		.m0_waitrequest          (scheduler_av_mm_agent_agent_m0_waitrequest),                         //   input,    width = 1,                .waitrequest
		.m0_writedata            (scheduler_av_mm_agent_agent_m0_writedata),                           //  output,   width = 32,                .writedata
		.m0_write                (scheduler_av_mm_agent_agent_m0_write),                               //  output,    width = 1,                .write
		.rp_endofpacket          (scheduler_av_mm_agent_agent_rp_endofpacket),                         //  output,    width = 1,              rp.endofpacket
		.rp_ready                (scheduler_av_mm_agent_agent_rp_ready),                               //   input,    width = 1,                .ready
		.rp_valid                (scheduler_av_mm_agent_agent_rp_valid),                               //  output,    width = 1,                .valid
		.rp_data                 (scheduler_av_mm_agent_agent_rp_data),                                //  output,  width = 106,                .data
		.rp_startofpacket        (scheduler_av_mm_agent_agent_rp_startofpacket),                       //  output,    width = 1,                .startofpacket
		.cp_ready                (cmd_mux_src_ready),                                                  //  output,    width = 1,              cp.ready
		.cp_valid                (cmd_mux_src_valid),                                                  //   input,    width = 1,                .valid
		.cp_data                 (cmd_mux_src_data),                                                   //   input,  width = 106,                .data
		.cp_startofpacket        (cmd_mux_src_startofpacket),                                          //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (cmd_mux_src_endofpacket),                                            //   input,    width = 1,                .endofpacket
		.cp_channel              (cmd_mux_src_channel),                                                //   input,    width = 1,                .channel
		.rf_sink_ready           (scheduler_av_mm_agent_agent_rsp_fifo_out_ready),                     //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (scheduler_av_mm_agent_agent_rsp_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (scheduler_av_mm_agent_agent_rsp_fifo_out_startofpacket),             //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (scheduler_av_mm_agent_agent_rsp_fifo_out_endofpacket),               //   input,    width = 1,                .endofpacket
		.rf_sink_data            (scheduler_av_mm_agent_agent_rsp_fifo_out_data),                      //   input,  width = 107,                .data
		.rf_source_ready         (scheduler_av_mm_agent_agent_rf_source_ready),                        //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (scheduler_av_mm_agent_agent_rf_source_valid),                        //  output,    width = 1,                .valid
		.rf_source_startofpacket (scheduler_av_mm_agent_agent_rf_source_startofpacket),                //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (scheduler_av_mm_agent_agent_rf_source_endofpacket),                  //  output,    width = 1,                .endofpacket
		.rf_source_data          (scheduler_av_mm_agent_agent_rf_source_data),                         //  output,  width = 107,                .data
		.rdata_fifo_sink_ready   (scheduler_av_mm_agent_agent_rdata_fifo_out_ready),                   //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (scheduler_av_mm_agent_agent_rdata_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (scheduler_av_mm_agent_agent_rdata_fifo_out_data),                    //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (scheduler_av_mm_agent_agent_rdata_fifo_src_ready),                   //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (scheduler_av_mm_agent_agent_rdata_fifo_src_valid),                   //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (scheduler_av_mm_agent_agent_rdata_fifo_src_data),                    //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                              // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                               // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                // (terminated),                               
	);

	nios_system_intel_vvp_vfr_0_altera_avalon_sc_fifo_1932_onpcouq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (107),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (0)
	) scheduler_av_mm_agent_agent_rsp_fifo (
		.clk               (axi_st_clk_bridge_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset             (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_data           (scheduler_av_mm_agent_agent_rf_source_data),                         //   input,  width = 107,        in.data
		.in_valid          (scheduler_av_mm_agent_agent_rf_source_valid),                        //   input,    width = 1,          .valid
		.in_ready          (scheduler_av_mm_agent_agent_rf_source_ready),                        //  output,    width = 1,          .ready
		.in_startofpacket  (scheduler_av_mm_agent_agent_rf_source_startofpacket),                //   input,    width = 1,          .startofpacket
		.in_endofpacket    (scheduler_av_mm_agent_agent_rf_source_endofpacket),                  //   input,    width = 1,          .endofpacket
		.out_data          (scheduler_av_mm_agent_agent_rsp_fifo_out_data),                      //  output,  width = 107,       out.data
		.out_valid         (scheduler_av_mm_agent_agent_rsp_fifo_out_valid),                     //  output,    width = 1,          .valid
		.out_ready         (scheduler_av_mm_agent_agent_rsp_fifo_out_ready),                     //   input,    width = 1,          .ready
		.out_startofpacket (scheduler_av_mm_agent_agent_rsp_fifo_out_startofpacket),             //  output,    width = 1,          .startofpacket
		.out_endofpacket   (scheduler_av_mm_agent_agent_rsp_fifo_out_endofpacket),               //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                              // (terminated),                         
		.csr_read          (1'b0),                                                               // (terminated),                         
		.csr_write         (1'b0),                                                               // (terminated),                         
		.csr_readdata      (),                                                                   // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                               // (terminated),                         
		.almost_full_data  (),                                                                   // (terminated),                         
		.almost_empty_data (),                                                                   // (terminated),                         
		.in_empty          (1'b0),                                                               // (terminated),                         
		.out_empty         (),                                                                   // (terminated),                         
		.in_error          (1'b0),                                                               // (terminated),                         
		.out_error         (),                                                                   // (terminated),                         
		.in_channel        (1'b0),                                                               // (terminated),                         
		.out_channel       ()                                                                    // (terminated),                         
	);

	nios_system_intel_vvp_vfr_0_altera_avalon_sc_fifo_1932_onpcouq #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (0)
	) scheduler_av_mm_agent_agent_rdata_fifo (
		.clk               (axi_st_clk_bridge_out_clk_clk),                                      //   input,   width = 1,       clk.clk
		.reset             (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset
		.in_data           (scheduler_av_mm_agent_agent_rdata_fifo_src_data),                    //   input,  width = 34,        in.data
		.in_valid          (scheduler_av_mm_agent_agent_rdata_fifo_src_valid),                   //   input,   width = 1,          .valid
		.in_ready          (scheduler_av_mm_agent_agent_rdata_fifo_src_ready),                   //  output,   width = 1,          .ready
		.out_data          (scheduler_av_mm_agent_agent_rdata_fifo_out_data),                    //  output,  width = 34,       out.data
		.out_valid         (scheduler_av_mm_agent_agent_rdata_fifo_out_valid),                   //  output,   width = 1,          .valid
		.out_ready         (scheduler_av_mm_agent_agent_rdata_fifo_out_ready),                   //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                              // (terminated),                        
		.csr_read          (1'b0),                                                               // (terminated),                        
		.csr_write         (1'b0),                                                               // (terminated),                        
		.csr_readdata      (),                                                                   // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                               // (terminated),                        
		.almost_full_data  (),                                                                   // (terminated),                        
		.almost_empty_data (),                                                                   // (terminated),                        
		.in_startofpacket  (1'b0),                                                               // (terminated),                        
		.in_endofpacket    (1'b0),                                                               // (terminated),                        
		.out_startofpacket (),                                                                   // (terminated),                        
		.out_endofpacket   (),                                                                   // (terminated),                        
		.in_empty          (1'b0),                                                               // (terminated),                        
		.out_empty         (),                                                                   // (terminated),                        
		.in_error          (1'b0),                                                               // (terminated),                        
		.out_error         (),                                                                   // (terminated),                        
		.in_channel        (1'b0),                                                               // (terminated),                        
		.out_channel       ()                                                                    // (terminated),                        
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_router_1921_cq2muai router (
		.sink_ready         (ro_reg_servicer_av_mm_master_agent_cp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (ro_reg_servicer_av_mm_master_agent_cp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (ro_reg_servicer_av_mm_master_agent_cp_data),                                //   input,  width = 106,          .data
		.sink_startofpacket (ro_reg_servicer_av_mm_master_agent_cp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (ro_reg_servicer_av_mm_master_agent_cp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (mm_clk_bridge_out_clk_clk),                                                 //   input,    width = 1,       clk.clk
		.reset              (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                                          //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                                          //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                                           //  output,  width = 106,          .data
		.src_channel        (router_src_channel),                                                        //  output,    width = 1,          .channel
		.src_startofpacket  (router_src_startofpacket),                                                  //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                                     //  output,    width = 1,          .endofpacket
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_router_1921_3gv6laq router_001 (
		.sink_ready         (scheduler_av_mm_agent_agent_rp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (scheduler_av_mm_agent_agent_rp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (scheduler_av_mm_agent_agent_rp_data),                                //   input,  width = 106,          .data
		.sink_startofpacket (scheduler_av_mm_agent_agent_rp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (scheduler_av_mm_agent_agent_rp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (axi_st_clk_bridge_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                               //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                               //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                                //  output,  width = 106,          .data
		.src_channel        (router_001_src_channel),                                             //  output,    width = 1,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                       //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                          //  output,    width = 1,          .endofpacket
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_demultiplexer_1921_57dntwa cmd_demux (
		.clk                (mm_clk_bridge_out_clk_clk),                                                 //   input,    width = 1,       clk.clk
		.reset              (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_src_ready),                                                          //  output,    width = 1,      sink.ready
		.sink_channel       (router_src_channel),                                                        //   input,    width = 1,          .channel
		.sink_data          (router_src_data),                                                           //   input,  width = 106,          .data
		.sink_startofpacket (router_src_startofpacket),                                                  //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_src_endofpacket),                                                    //   input,    width = 1,          .endofpacket
		.sink_valid         (router_src_valid),                                                          //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                      //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                      //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_src0_data),                                                       //  output,  width = 106,          .data
		.src0_channel       (cmd_demux_src0_channel),                                                    //  output,    width = 1,          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket)                                                 //  output,    width = 1,          .endofpacket
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_multiplexer_1922_tjsswvi cmd_mux (
		.clk                 (axi_st_clk_bridge_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset               (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                  //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                                  //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                                   //  output,  width = 106,          .data
		.src_channel         (cmd_mux_src_channel),                                                //  output,    width = 1,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                          //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                            //  output,    width = 1,          .endofpacket
		.sink0_ready         (crosser_out_ready),                                                  //  output,    width = 1,     sink0.ready
		.sink0_valid         (crosser_out_valid),                                                  //   input,    width = 1,          .valid
		.sink0_channel       (crosser_out_channel),                                                //   input,    width = 1,          .channel
		.sink0_data          (crosser_out_data),                                                   //   input,  width = 106,          .data
		.sink0_startofpacket (crosser_out_startofpacket),                                          //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (crosser_out_endofpacket)                                             //   input,    width = 1,          .endofpacket
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_demultiplexer_1921_57dntwa rsp_demux (
		.clk                (axi_st_clk_bridge_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset              (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                                               //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                                             //   input,    width = 1,          .channel
		.sink_data          (router_001_src_data),                                                //   input,  width = 106,          .data
		.sink_startofpacket (router_001_src_startofpacket),                                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                                         //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                                               //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                               //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                               //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                                //  output,  width = 106,          .data
		.src0_channel       (rsp_demux_src0_channel),                                             //  output,    width = 1,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                       //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                          //  output,    width = 1,          .endofpacket
	);

	nios_system_intel_vvp_vfr_0_altera_merlin_multiplexer_1922_2qe5ida rsp_mux (
		.clk                 (mm_clk_bridge_out_clk_clk),                                                 //   input,    width = 1,       clk.clk
		.reset               (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                         //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                                         //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                                          //  output,  width = 106,          .data
		.src_channel         (rsp_mux_src_channel),                                                       //  output,    width = 1,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                                   //  output,    width = 1,          .endofpacket
		.sink0_ready         (crosser_001_out_ready),                                                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (crosser_001_out_valid),                                                     //   input,    width = 1,          .valid
		.sink0_channel       (crosser_001_out_channel),                                                   //   input,    width = 1,          .channel
		.sink0_data          (crosser_001_out_data),                                                      //   input,  width = 106,          .data
		.sink0_startofpacket (crosser_001_out_startofpacket),                                             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (crosser_001_out_endofpacket)                                                //   input,    width = 1,          .endofpacket
	);

	nios_system_intel_vvp_vfr_0_hs_clk_xer_1941_jple52y #(
		.DATA_WIDTH          (106),
		.BITS_PER_SYMBOL     (106),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (1),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0),
		.SYNC_RESET          (0)
	) crosser (
		.in_clk            (mm_clk_bridge_out_clk_clk),                                                 //   input,    width = 1,        in_clk.clk
		.in_reset          (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,  in_clk_reset.reset
		.out_clk           (axi_st_clk_bridge_out_clk_clk),                                             //   input,    width = 1,       out_clk.clk
		.out_reset         (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset),        //   input,    width = 1, out_clk_reset.reset
		.in_ready          (cmd_demux_src0_ready),                                                      //  output,    width = 1,            in.ready
		.in_valid          (cmd_demux_src0_valid),                                                      //   input,    width = 1,              .valid
		.in_startofpacket  (cmd_demux_src0_startofpacket),                                              //   input,    width = 1,              .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                                                //   input,    width = 1,              .endofpacket
		.in_channel        (cmd_demux_src0_channel),                                                    //   input,    width = 1,              .channel
		.in_data           (cmd_demux_src0_data),                                                       //   input,  width = 106,              .data
		.out_ready         (crosser_out_ready),                                                         //   input,    width = 1,           out.ready
		.out_valid         (crosser_out_valid),                                                         //  output,    width = 1,              .valid
		.out_startofpacket (crosser_out_startofpacket),                                                 //  output,    width = 1,              .startofpacket
		.out_endofpacket   (crosser_out_endofpacket),                                                   //  output,    width = 1,              .endofpacket
		.out_channel       (crosser_out_channel),                                                       //  output,    width = 1,              .channel
		.out_data          (crosser_out_data),                                                          //  output,  width = 106,              .data
		.in_empty          (1'b0),                                                                      // (terminated),                             
		.in_error          (1'b0),                                                                      // (terminated),                             
		.out_empty         (),                                                                          // (terminated),                             
		.out_error         ()                                                                           // (terminated),                             
	);

	nios_system_intel_vvp_vfr_0_hs_clk_xer_1941_jple52y #(
		.DATA_WIDTH          (106),
		.BITS_PER_SYMBOL     (106),
		.USE_PACKETS         (1),
		.USE_CHANNEL         (1),
		.CHANNEL_WIDTH       (1),
		.USE_ERROR           (0),
		.ERROR_WIDTH         (1),
		.VALID_SYNC_DEPTH    (2),
		.READY_SYNC_DEPTH    (2),
		.USE_OUTPUT_PIPELINE (0),
		.SYNC_RESET          (0)
	) crosser_001 (
		.in_clk            (axi_st_clk_bridge_out_clk_clk),                                             //   input,    width = 1,        in_clk.clk
		.in_reset          (scheduler_av_mm_agent_translator_reset_reset_bridge_in_reset_reset),        //   input,    width = 1,  in_clk_reset.reset
		.out_clk           (mm_clk_bridge_out_clk_clk),                                                 //   input,    width = 1,       out_clk.clk
		.out_reset         (ro_reg_servicer_av_mm_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, out_clk_reset.reset
		.in_ready          (rsp_demux_src0_ready),                                                      //  output,    width = 1,            in.ready
		.in_valid          (rsp_demux_src0_valid),                                                      //   input,    width = 1,              .valid
		.in_startofpacket  (rsp_demux_src0_startofpacket),                                              //   input,    width = 1,              .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                                                //   input,    width = 1,              .endofpacket
		.in_channel        (rsp_demux_src0_channel),                                                    //   input,    width = 1,              .channel
		.in_data           (rsp_demux_src0_data),                                                       //   input,  width = 106,              .data
		.out_ready         (crosser_001_out_ready),                                                     //   input,    width = 1,           out.ready
		.out_valid         (crosser_001_out_valid),                                                     //  output,    width = 1,              .valid
		.out_startofpacket (crosser_001_out_startofpacket),                                             //  output,    width = 1,              .startofpacket
		.out_endofpacket   (crosser_001_out_endofpacket),                                               //  output,    width = 1,              .endofpacket
		.out_channel       (crosser_001_out_channel),                                                   //  output,    width = 1,              .channel
		.out_data          (crosser_001_out_data),                                                      //  output,  width = 106,              .data
		.in_empty          (1'b0),                                                                      // (terminated),                             
		.in_error          (1'b0),                                                                      // (terminated),                             
		.out_empty         (),                                                                          // (terminated),                             
		.out_error         ()                                                                           // (terminated),                             
	);

endmodule
