// niosv_g_intel_niosv_g_400_vqhbypy.v

// This file was auto-generated from intel_niosv_g_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module niosv_g_intel_niosv_g_400_vqhbypy (
		input  wire        clk,                          //                 clk.clk,           Clock Input
		input  wire        reset_reset,                  //               reset.reset,         Reset Input
		input  wire [15:0] platform_irq_rx_irq,          //     platform_irq_rx.irq
		output wire [2:0]  instruction_manager_awsize,   // instruction_manager.awsize
		output wire [7:0]  instruction_manager_awlen,    //                    .awlen
		output wire [1:0]  instruction_manager_awburst,  //                    .awburst
		output wire        instruction_manager_wlast,    //                    .wlast
		output wire [2:0]  instruction_manager_arsize,   //                    .arsize
		output wire [7:0]  instruction_manager_arlen,    //                    .arlen
		output wire [1:0]  instruction_manager_arburst,  //                    .arburst
		input  wire        instruction_manager_rlast,    //                    .rlast
		output wire [31:0] instruction_manager_awaddr,   //                    .awaddr
		output wire [2:0]  instruction_manager_awprot,   //                    .awprot
		output wire        instruction_manager_awvalid,  //                    .awvalid
		input  wire        instruction_manager_awready,  //                    .awready
		output wire [31:0] instruction_manager_wdata,    //                    .wdata
		output wire [3:0]  instruction_manager_wstrb,    //                    .wstrb
		output wire        instruction_manager_wvalid,   //                    .wvalid
		input  wire        instruction_manager_wready,   //                    .wready
		input  wire [1:0]  instruction_manager_bresp,    //                    .bresp
		input  wire        instruction_manager_bvalid,   //                    .bvalid
		output wire        instruction_manager_bready,   //                    .bready
		output wire [31:0] instruction_manager_araddr,   //                    .araddr
		output wire [2:0]  instruction_manager_arprot,   //                    .arprot
		output wire        instruction_manager_arvalid,  //                    .arvalid
		input  wire        instruction_manager_arready,  //                    .arready
		input  wire [31:0] instruction_manager_rdata,    //                    .rdata
		input  wire [1:0]  instruction_manager_rresp,    //                    .rresp
		input  wire        instruction_manager_rvalid,   //                    .rvalid
		output wire        instruction_manager_rready,   //                    .rready
		output wire [2:0]  data_manager_awsize,          //        data_manager.awsize
		output wire [7:0]  data_manager_awlen,           //                    .awlen
		output wire        data_manager_wlast,           //                    .wlast
		output wire [2:0]  data_manager_arsize,          //                    .arsize
		output wire [7:0]  data_manager_arlen,           //                    .arlen
		input  wire        data_manager_rlast,           //                    .rlast
		output wire [31:0] data_manager_awaddr,          //                    .awaddr
		output wire [2:0]  data_manager_awprot,          //                    .awprot
		output wire        data_manager_awvalid,         //                    .awvalid
		input  wire        data_manager_awready,         //                    .awready
		output wire [31:0] data_manager_wdata,           //                    .wdata
		output wire [3:0]  data_manager_wstrb,           //                    .wstrb
		output wire        data_manager_wvalid,          //                    .wvalid
		input  wire        data_manager_wready,          //                    .wready
		input  wire [1:0]  data_manager_bresp,           //                    .bresp
		input  wire        data_manager_bvalid,          //                    .bvalid
		output wire        data_manager_bready,          //                    .bready
		output wire [31:0] data_manager_araddr,          //                    .araddr
		output wire [2:0]  data_manager_arprot,          //                    .arprot
		output wire        data_manager_arvalid,         //                    .arvalid
		input  wire        data_manager_arready,         //                    .arready
		input  wire [31:0] data_manager_rdata,           //                    .rdata
		input  wire [1:0]  data_manager_rresp,           //                    .rresp
		input  wire        data_manager_rvalid,          //                    .rvalid
		output wire        data_manager_rready,          //                    .rready
		input  wire [5:0]  timer_sw_agent_address,       //      timer_sw_agent.address,       The address in the Timer and Software Interrupt Module that the core wants to write to or read from. This is relative to the Timer and Software Interrupt Module base address.
		input  wire [3:0]  timer_sw_agent_byteenable,    //                    .byteenable,    Store byte enable.
		input  wire        timer_sw_agent_read,          //                    .read,          Indicates if the core wants to load from "timer_sw_agent_address" in the Timer and Software Interrupt Module.
		output wire [31:0] timer_sw_agent_readdata,      //                    .readdata,      Load data from the Timer and Software Interrupt Module sent to the core.
		input  wire        timer_sw_agent_write,         //                    .write,         Indicates if the core wants to store to "timer_sw_agent_address" in the Timer and Software Interrupt Module.
		input  wire [31:0] timer_sw_agent_writedata,     //                    .writedata,     Store data to the Timer and Software Interrupt Module sent from the core.
		output wire        timer_sw_agent_waitrequest,   //                    .waitrequest,   Timer and Software Interrupt Module not ready to receive write or read request from the core.
		output wire        timer_sw_agent_readdatavalid, //                    .readdatavalid, Load data valid.
		input  wire [15:0] dm_agent_address,             //            dm_agent.address,       The address in the Debug Module that the core wants to write to or read from. This is relative to the Debug Module base address.
		input  wire        dm_agent_read,                //                    .read,          Indicates if the core wants to load from "dm_agent_address" in the Debug Module.
		output wire [31:0] dm_agent_readdata,            //                    .readdata,      Load data from the Debug Module sent to the core.
		input  wire        dm_agent_write,               //                    .write,         Indicates if the core wants to store to "dm_agent_address" in the Debug Module.
		input  wire [31:0] dm_agent_writedata,           //                    .writedata,     Store data to the Debug Module sent from the core.
		output wire        dm_agent_waitrequest,         //                    .waitrequest,   Debug Module not ready to receive write or read request from the core.
		output wire        dm_agent_readdatavalid,       //                    .readdatavalid, Load data valid.
		output wire        dbg_reset_out_reset,          //       dbg_reset_out.reset,         This signal provides a reset originating from the Debug Module. It is triggered by the JTAG debugger or the "niosv-download -r" command. It can be connected to "ndm_reset_in_reset" to reset the core and the Timer and Software Interrupt Module. It can also be connected to the reset inputs of other system components as needed.
		input  wire        ndm_reset_in_reset            //        ndm_reset_in.reset,         Reset Input
	);

	wire    irq_mapper_receiver0_irq;           // dbg_mod:dbg_irq -> irq_mapper:receiver0_irq
	wire    hart_debug_irq_rx_irq;              // irq_mapper:sender_irq -> hart:irq_debug
	wire    irq_mapper_001_receiver0_irq;       // timer_module:timer_irq -> irq_mapper_001:receiver0_irq
	wire    hart_timer_irq_rx_irq;              // irq_mapper_001:sender_irq -> hart:irq_timer
	wire    irq_mapper_002_receiver0_irq;       // timer_module:sw_irq -> irq_mapper_002:receiver0_irq
	wire    hart_sw_irq_rx_irq;                 // irq_mapper_002:sender_irq -> hart:irq_sw
	wire    rst_controller_reset_out_reset;     // rst_controller:reset_out -> hart:reset
	wire    rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [irq_mapper:reset, irq_mapper_001:reset, irq_mapper_002:reset, timer_module:reset]

	niosv_g_intel_niosv_g_unit_400_j375vgi #(
		.RESET_VECTOR             (32'b00000000000100000000000000000000),
		.DBG_EXPN_VECTOR          (32'b00000000000000000000000000000000),
		.HARTID                   (32'b00000000000000000000000000000000),
		.CORE_EXTN                (4352),
		.DEBUG_ENABLED            (1),
		.DEVICE_FAMILY            ("Agilex 3"),
		.USE_RESET_REQ            (0),
		.ECC_EN                   (0),
		.ECC_FULL                 (0),
		.BRANCHPREDICTION_EN      (1),
		.BLIND_WINDOW_PERIOD      (1000),
		.DEFAULT_TIMEOUT_PERIOD   (255),
		.DATA_CACHE_SIZE          (4096),
		.INST_CACHE_SIZE          (4096),
		.ITCM1_SIZE               (0),
		.ITCM1_BASE               (32'b00000000000000000000000000000000),
		.ITCM1_INIT_FILE          (""),
		.ITCM2_SIZE               (0),
		.ITCM2_BASE               (32'b00000000000000000000000000000000),
		.ITCM2_INIT_FILE          (""),
		.PERIPHERAL_REGION_A_SIZE (524288),
		.PERIPHERAL_REGION_A_BASE (32'b00000000000010000000000000000000),
		.PERIPHERAL_REGION_B_SIZE (0),
		.PERIPHERAL_REGION_B_BASE (32'b00000000000000000000000000000000),
		.DBG_DATA_S_BASE          (32'b00000000000000000000000000000000),
		.TIMER_MSIP_DATA_S_BASE   (32'b00000000000000010001000000000000),
		.DTCM1_SIZE               (0),
		.DTCM1_BASE               (32'b00000000000000000000000000000000),
		.DTCM1_INIT_FILE          (""),
		.DTCM2_SIZE               (0),
		.DTCM2_BASE               (32'b00000000000000000000000000000000),
		.DTCM2_INIT_FILE          (""),
		.ITCS1_ADDR_WIDTH         (10),
		.ITCS2_ADDR_WIDTH         (10),
		.DTCS1_ADDR_WIDTH         (10),
		.DTCS2_ADDR_WIDTH         (10),
		.DISABLE_FSQRT_FDIV       (0),
		.NUM_PLATFORM_INTERRUPTS  (16),
		.NUM_SRF_BANKS            (1),
		.CLIC_EN                  (0),
		.CLIC_NUM_LEVELS          (2),
		.CLIC_NUM_PRIORITIES      (8),
		.CLIC_NUM_DEBUG_TRIGGERS  (0),
		.CLIC_TRIGGER_POLARITY_EN (0),
		.CLIC_EDGE_TRIGGER_EN     (0),
		.CLIC_VT_ALIGN            (8),
		.CLIC_SHV_EN              (0)
	) hart (
		.clk             (clk),                                  //   input,   width = 1,             cpu_clk.clk
		.reset           (rst_controller_reset_out_reset),       //   input,   width = 1,           cpu_reset.reset
		.irq_debug       (hart_debug_irq_rx_irq),                //   input,   width = 1,        debug_irq_rx.irq
		.irq_plat_vec    (platform_irq_rx_irq),                  //   input,  width = 16,     platform_irq_rx.irq
		.irq_timer       (hart_timer_irq_rx_irq),                //   input,   width = 1,        timer_irq_rx.irq
		.irq_sw          (hart_sw_irq_rx_irq),                   //   input,   width = 1,           sw_irq_rx.irq
		.instr_awsize    (instruction_manager_awsize),           //  output,   width = 3, instruction_manager.awsize
		.instr_awlen     (instruction_manager_awlen),            //  output,   width = 8,                    .awlen
		.instr_awburst   (instruction_manager_awburst),          //  output,   width = 2,                    .awburst
		.instr_wlast     (instruction_manager_wlast),            //  output,   width = 1,                    .wlast
		.instr_arsize    (instruction_manager_arsize),           //  output,   width = 3,                    .arsize
		.instr_arlen     (instruction_manager_arlen),            //  output,   width = 8,                    .arlen
		.instr_arburst   (instruction_manager_arburst),          //  output,   width = 2,                    .arburst
		.instr_rlast     (instruction_manager_rlast),            //   input,   width = 1,                    .rlast
		.instr_awaddr    (instruction_manager_awaddr),           //  output,  width = 32,                    .awaddr
		.instr_awprot    (instruction_manager_awprot),           //  output,   width = 3,                    .awprot
		.instr_awvalid   (instruction_manager_awvalid),          //  output,   width = 1,                    .awvalid
		.instr_awready   (instruction_manager_awready),          //   input,   width = 1,                    .awready
		.instr_wdata     (instruction_manager_wdata),            //  output,  width = 32,                    .wdata
		.instr_wstrb     (instruction_manager_wstrb),            //  output,   width = 4,                    .wstrb
		.instr_wvalid    (instruction_manager_wvalid),           //  output,   width = 1,                    .wvalid
		.instr_wready    (instruction_manager_wready),           //   input,   width = 1,                    .wready
		.instr_bresp     (instruction_manager_bresp),            //   input,   width = 2,                    .bresp
		.instr_bvalid    (instruction_manager_bvalid),           //   input,   width = 1,                    .bvalid
		.instr_bready    (instruction_manager_bready),           //  output,   width = 1,                    .bready
		.instr_araddr    (instruction_manager_araddr),           //  output,  width = 32,                    .araddr
		.instr_arprot    (instruction_manager_arprot),           //  output,   width = 3,                    .arprot
		.instr_arvalid   (instruction_manager_arvalid),          //  output,   width = 1,                    .arvalid
		.instr_arready   (instruction_manager_arready),          //   input,   width = 1,                    .arready
		.instr_rdata     (instruction_manager_rdata),            //   input,  width = 32,                    .rdata
		.instr_rresp     (instruction_manager_rresp),            //   input,   width = 2,                    .rresp
		.instr_rvalid    (instruction_manager_rvalid),           //   input,   width = 1,                    .rvalid
		.instr_rready    (instruction_manager_rready),           //  output,   width = 1,                    .rready
		.data_awsize     (data_manager_awsize),                  //  output,   width = 3,        data_manager.awsize
		.data_awlen      (data_manager_awlen),                   //  output,   width = 8,                    .awlen
		.data_wlast      (data_manager_wlast),                   //  output,   width = 1,                    .wlast
		.data_arsize     (data_manager_arsize),                  //  output,   width = 3,                    .arsize
		.data_arlen      (data_manager_arlen),                   //  output,   width = 8,                    .arlen
		.data_rlast      (data_manager_rlast),                   //   input,   width = 1,                    .rlast
		.data_awaddr     (data_manager_awaddr),                  //  output,  width = 32,                    .awaddr
		.data_awprot     (data_manager_awprot),                  //  output,   width = 3,                    .awprot
		.data_awvalid    (data_manager_awvalid),                 //  output,   width = 1,                    .awvalid
		.data_awready    (data_manager_awready),                 //   input,   width = 1,                    .awready
		.data_wdata      (data_manager_wdata),                   //  output,  width = 32,                    .wdata
		.data_wstrb      (data_manager_wstrb),                   //  output,   width = 4,                    .wstrb
		.data_wvalid     (data_manager_wvalid),                  //  output,   width = 1,                    .wvalid
		.data_wready     (data_manager_wready),                  //   input,   width = 1,                    .wready
		.data_bresp      (data_manager_bresp),                   //   input,   width = 2,                    .bresp
		.data_bvalid     (data_manager_bvalid),                  //   input,   width = 1,                    .bvalid
		.data_bready     (data_manager_bready),                  //  output,   width = 1,                    .bready
		.data_araddr     (data_manager_araddr),                  //  output,  width = 32,                    .araddr
		.data_arprot     (data_manager_arprot),                  //  output,   width = 3,                    .arprot
		.data_arvalid    (data_manager_arvalid),                 //  output,   width = 1,                    .arvalid
		.data_arready    (data_manager_arready),                 //   input,   width = 1,                    .arready
		.data_rdata      (data_manager_rdata),                   //   input,  width = 32,                    .rdata
		.data_rresp      (data_manager_rresp),                   //   input,   width = 2,                    .rresp
		.data_rvalid     (data_manager_rvalid),                  //   input,   width = 1,                    .rvalid
		.data_rready     (data_manager_rready),                  //  output,   width = 1,                    .rready
		.reset_req       (1'b0),                                 // (terminated),                                  
		.reset_req_ack   (),                                     // (terminated),                                  
		.core_ecc_status (),                                     // (terminated),                                  
		.core_ecc_src    (),                                     // (terminated),                                  
		.itcs1_awaddr    (10'b0000000000),                       // (terminated),                                  
		.itcs1_awprot    (3'b000),                               // (terminated),                                  
		.itcs1_awvalid   (1'b0),                                 // (terminated),                                  
		.itcs1_awready   (),                                     // (terminated),                                  
		.itcs1_wdata     (32'b00000000000000000000000000000000), // (terminated),                                  
		.itcs1_wstrb     (4'b0000),                              // (terminated),                                  
		.itcs1_wvalid    (1'b0),                                 // (terminated),                                  
		.itcs1_wready    (),                                     // (terminated),                                  
		.itcs1_bresp     (),                                     // (terminated),                                  
		.itcs1_bvalid    (),                                     // (terminated),                                  
		.itcs1_bready    (1'b0),                                 // (terminated),                                  
		.itcs1_araddr    (10'b0000000000),                       // (terminated),                                  
		.itcs1_arprot    (3'b000),                               // (terminated),                                  
		.itcs1_arvalid   (1'b0),                                 // (terminated),                                  
		.itcs1_arready   (),                                     // (terminated),                                  
		.itcs1_rdata     (),                                     // (terminated),                                  
		.itcs1_rresp     (),                                     // (terminated),                                  
		.itcs1_rvalid    (),                                     // (terminated),                                  
		.itcs1_rready    (1'b0),                                 // (terminated),                                  
		.itcs2_awaddr    (10'b0000000000),                       // (terminated),                                  
		.itcs2_awprot    (3'b000),                               // (terminated),                                  
		.itcs2_awvalid   (1'b0),                                 // (terminated),                                  
		.itcs2_awready   (),                                     // (terminated),                                  
		.itcs2_wdata     (32'b00000000000000000000000000000000), // (terminated),                                  
		.itcs2_wstrb     (4'b0000),                              // (terminated),                                  
		.itcs2_wvalid    (1'b0),                                 // (terminated),                                  
		.itcs2_wready    (),                                     // (terminated),                                  
		.itcs2_bresp     (),                                     // (terminated),                                  
		.itcs2_bvalid    (),                                     // (terminated),                                  
		.itcs2_bready    (1'b0),                                 // (terminated),                                  
		.itcs2_araddr    (10'b0000000000),                       // (terminated),                                  
		.itcs2_arprot    (3'b000),                               // (terminated),                                  
		.itcs2_arvalid   (1'b0),                                 // (terminated),                                  
		.itcs2_arready   (),                                     // (terminated),                                  
		.itcs2_rdata     (),                                     // (terminated),                                  
		.itcs2_rresp     (),                                     // (terminated),                                  
		.itcs2_rvalid    (),                                     // (terminated),                                  
		.itcs2_rready    (1'b0),                                 // (terminated),                                  
		.dtcs1_awaddr    (10'b0000000000),                       // (terminated),                                  
		.dtcs1_awprot    (3'b000),                               // (terminated),                                  
		.dtcs1_awvalid   (1'b0),                                 // (terminated),                                  
		.dtcs1_awready   (),                                     // (terminated),                                  
		.dtcs1_wdata     (32'b00000000000000000000000000000000), // (terminated),                                  
		.dtcs1_wstrb     (4'b0000),                              // (terminated),                                  
		.dtcs1_wvalid    (1'b0),                                 // (terminated),                                  
		.dtcs1_wready    (),                                     // (terminated),                                  
		.dtcs1_bresp     (),                                     // (terminated),                                  
		.dtcs1_bvalid    (),                                     // (terminated),                                  
		.dtcs1_bready    (1'b0),                                 // (terminated),                                  
		.dtcs1_araddr    (10'b0000000000),                       // (terminated),                                  
		.dtcs1_arprot    (3'b000),                               // (terminated),                                  
		.dtcs1_arvalid   (1'b0),                                 // (terminated),                                  
		.dtcs1_arready   (),                                     // (terminated),                                  
		.dtcs1_rdata     (),                                     // (terminated),                                  
		.dtcs1_rresp     (),                                     // (terminated),                                  
		.dtcs1_rvalid    (),                                     // (terminated),                                  
		.dtcs1_rready    (1'b0),                                 // (terminated),                                  
		.dtcs2_awaddr    (10'b0000000000),                       // (terminated),                                  
		.dtcs2_awprot    (3'b000),                               // (terminated),                                  
		.dtcs2_awvalid   (1'b0),                                 // (terminated),                                  
		.dtcs2_awready   (),                                     // (terminated),                                  
		.dtcs2_wdata     (32'b00000000000000000000000000000000), // (terminated),                                  
		.dtcs2_wstrb     (4'b0000),                              // (terminated),                                  
		.dtcs2_wvalid    (1'b0),                                 // (terminated),                                  
		.dtcs2_wready    (),                                     // (terminated),                                  
		.dtcs2_bresp     (),                                     // (terminated),                                  
		.dtcs2_bvalid    (),                                     // (terminated),                                  
		.dtcs2_bready    (1'b0),                                 // (terminated),                                  
		.dtcs2_araddr    (10'b0000000000),                       // (terminated),                                  
		.dtcs2_arprot    (3'b000),                               // (terminated),                                  
		.dtcs2_arvalid   (1'b0),                                 // (terminated),                                  
		.dtcs2_arready   (),                                     // (terminated),                                  
		.dtcs2_rdata     (),                                     // (terminated),                                  
		.dtcs2_rresp     (),                                     // (terminated),                                  
		.dtcs2_rvalid    (),                                     // (terminated),                                  
		.dtcs2_rready    (1'b0),                                 // (terminated),                                  
		.irq_ext         (1'b0)                                  // (terminated),                                  
	);

	niosv_timer_msip #(
		.IRQ_EN     (1),
		.HARTID     (0),
		.ADDR_WIDTH (6)
	) timer_module (
		.clk                (clk),                                //   input,   width = 1,            clk.clk
		.reset              (rst_controller_001_reset_out_reset), //   input,   width = 1,          reset.reset
		.hart_address       (timer_sw_agent_address),             //   input,   width = 6, timer_sw_agent.address
		.hart_byteen        (timer_sw_agent_byteenable),          //   input,   width = 4,               .byteenable
		.hart_read          (timer_sw_agent_read),                //   input,   width = 1,               .read
		.hart_readdata      (timer_sw_agent_readdata),            //  output,  width = 32,               .readdata
		.hart_write         (timer_sw_agent_write),               //   input,   width = 1,               .write
		.hart_writedata     (timer_sw_agent_writedata),           //   input,  width = 32,               .writedata
		.hart_waitrequest   (timer_sw_agent_waitrequest),         //  output,   width = 1,               .waitrequest
		.hart_readdatavalid (timer_sw_agent_readdatavalid),       //  output,   width = 1,               .readdatavalid
		.timer_irq          (irq_mapper_001_receiver0_irq),       //  output,   width = 1,      timer_irq.irq
		.sw_irq             (irq_mapper_002_receiver0_irq)        //  output,   width = 1,         sw_irq.irq
	);

	niosv_dm_top #(
		.DEBUG_RESET_EN (1),
		.FPU_EN         (0),
		.DEVICE_FAMILY  ("Agilex 3")
	) dbg_mod (
		.clk                (clk),                      //   input,   width = 1,           clk.clk
		.reset              (reset_reset),              //   input,   width = 1,         reset.reset
		.hart_address       (dm_agent_address),         //   input,  width = 16,      dm_agent.address
		.hart_read          (dm_agent_read),            //   input,   width = 1,              .read
		.hart_readdata      (dm_agent_readdata),        //  output,  width = 32,              .readdata
		.hart_write         (dm_agent_write),           //   input,   width = 1,              .write
		.hart_writedata     (dm_agent_writedata),       //   input,  width = 32,              .writedata
		.hart_waitrequest   (dm_agent_waitrequest),     //  output,   width = 1,              .waitrequest
		.hart_readdatavalid (dm_agent_readdatavalid),   //  output,   width = 1,              .readdatavalid
		.dbg_irq            (irq_mapper_receiver0_irq), //  output,   width = 1,       dbg_irq.irq
		.dbg_reset          (dbg_reset_out_reset)       //  output,   width = 1, dbg_reset_out.reset
	);

	niosv_g_altera_irq_mapper_2001_wgtbcyy irq_mapper (
		.clk           (clk),                                //   input,  width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,  width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),           //   input,  width = 1, receiver0.irq
		.sender_irq    (hart_debug_irq_rx_irq)               //  output,  width = 1,    sender.irq
	);

	niosv_g_altera_irq_mapper_2001_wgtbcyy irq_mapper_001 (
		.clk           (clk),                                //   input,  width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,  width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_001_receiver0_irq),       //   input,  width = 1, receiver0.irq
		.sender_irq    (hart_timer_irq_rx_irq)               //  output,  width = 1,    sender.irq
	);

	niosv_g_altera_irq_mapper_2001_wgtbcyy irq_mapper_002 (
		.clk           (clk),                                //   input,  width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,  width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_002_receiver0_irq),       //   input,  width = 1, receiver0.irq
		.sender_irq    (hart_sw_irq_rx_irq)                  //  output,  width = 1,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("none"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (reset_reset),                    //   input,  width = 1, reset_in0.reset
		.reset_in1      (ndm_reset_in_reset),             //   input,  width = 1, reset_in1.reset
		.clk            (),                               //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                               // (terminated),                       
		.reset_req_in0  (1'b0),                           // (terminated),                       
		.reset_req_in1  (1'b0),                           // (terminated),                       
		.reset_in2      (1'b0),                           // (terminated),                       
		.reset_req_in2  (1'b0),                           // (terminated),                       
		.reset_in3      (1'b0),                           // (terminated),                       
		.reset_req_in3  (1'b0),                           // (terminated),                       
		.reset_in4      (1'b0),                           // (terminated),                       
		.reset_req_in4  (1'b0),                           // (terminated),                       
		.reset_in5      (1'b0),                           // (terminated),                       
		.reset_req_in5  (1'b0),                           // (terminated),                       
		.reset_in6      (1'b0),                           // (terminated),                       
		.reset_req_in6  (1'b0),                           // (terminated),                       
		.reset_in7      (1'b0),                           // (terminated),                       
		.reset_req_in7  (1'b0),                           // (terminated),                       
		.reset_in8      (1'b0),                           // (terminated),                       
		.reset_req_in8  (1'b0),                           // (terminated),                       
		.reset_in9      (1'b0),                           // (terminated),                       
		.reset_req_in9  (1'b0),                           // (terminated),                       
		.reset_in10     (1'b0),                           // (terminated),                       
		.reset_req_in10 (1'b0),                           // (terminated),                       
		.reset_in11     (1'b0),                           // (terminated),                       
		.reset_req_in11 (1'b0),                           // (terminated),                       
		.reset_in12     (1'b0),                           // (terminated),                       
		.reset_req_in12 (1'b0),                           // (terminated),                       
		.reset_in13     (1'b0),                           // (terminated),                       
		.reset_req_in13 (1'b0),                           // (terminated),                       
		.reset_in14     (1'b0),                           // (terminated),                       
		.reset_req_in14 (1'b0),                           // (terminated),                       
		.reset_in15     (1'b0),                           // (terminated),                       
		.reset_req_in15 (1'b0)                            // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (reset_reset),                        //   input,  width = 1, reset_in0.reset
		.reset_in1      (ndm_reset_in_reset),                 //   input,  width = 1, reset_in1.reset
		.clk            (clk),                                //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
