// system_pio_4.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module system_pio_4 (
		input  wire        clk,      //                 clk.clk
		input  wire        reset_n,  //               reset.reset_n
		input  wire [1:0]  address,  //                  s1.address
		output wire [31:0] readdata, //                    .readdata
		input  wire [1:0]  in_port   // external_connection.export
	);

	system_pio_4_altera_avalon_pio_1924_5wvwhoq pio_4 (
		.clk      (clk),      //   input,   width = 1,                 clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,               reset.reset_n
		.address  (address),  //   input,   width = 2,                  s1.address
		.readdata (readdata), //  output,  width = 32,                    .readdata
		.in_port  (in_port)   //   input,   width = 2, external_connection.export
	);

endmodule
