// nios_system_intel_vvp_cvo_0.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_cvo_0 (
		input  wire [23:0] axi4s_vid_in_tdata,           //     axi4s_vid_in.tdata
		input  wire        axi4s_vid_in_tvalid,          //                 .tvalid
		output wire        axi4s_vid_in_tready,          //                 .tready
		input  wire        axi4s_vid_in_tlast,           //                 .tlast
		input  wire [2:0]  axi4s_vid_in_tuser,           //                 .tuser
		output wire [31:0] axi4s_fr_vid_out_tdata,       // axi4s_fr_vid_out.tdata
		output wire        axi4s_fr_vid_out_tvalid,      //                 .tvalid
		input  wire        axi4s_fr_vid_out_tready,      //                 .tready
		output wire        axi4s_fr_vid_out_tlast,       //                 .tlast
		output wire [3:0]  axi4s_fr_vid_out_tuser,       //                 .tuser
		output wire        vid_status_vid_locked,        //       vid_status.vid_locked
		output wire        vid_status_vid_is_full,       //                 .vid_is_full
		output wire        vid_status_vid_stall_error,   //                 .vid_stall_error
		output wire        vid_status_vid_size_mismatch, //                 .vid_size_mismatch
		input  wire        frame_start_conduit,          //      frame_start.conduit
		input  wire        fr_clock_clk,                 //         fr_clock.clk,              Clock Input
		input  wire        fr_reset_reset,               //         fr_reset.reset
		input  wire        vid_clock_clk,                //        vid_clock.clk,              Clock Input
		input  wire        vid_reset_reset               //        vid_reset.reset
	);

	nios_system_intel_vvp_cvo_0_intel_vvp_cvo_2440_m7wcanq #(
		.BPS                              (8),
		.NUMBER_OF_COLOR_PLANES           (3),
		.PIXELS_IN_PARALLEL               (1),
		.RUNTIME_CONTROL                  (0),
		.C_CVO_DEFAULT_BLACK_0            (0),
		.C_CVO_DEFAULT_BLACK_1            (0),
		.C_CVO_DEFAULT_BLACK_2            (0),
		.C_CVO_DEFAULT_BLACK_3            (0),
		.CPU_CLK_FREQ_HZ                  (100000000),
		.ALIGNED_ONLY                     (0),
		.C_BUILD_HARD_FRAME_LOCK          (1),
		.C_BUILD_SOFT_FRAME_LOCK          (1),
		.C_BUILD_VRR                      (1),
		.C_HSIZE                          (14),
		.C_VSIZE                          (14),
		.C_NUM_PULSES                     (0),
		.VIRTUAL_INTERNAL_VTIMING         (1),
		.C_VID_IS_ASYNC                   (1),
		.C_VID_FIFO_DEPTH                 (4096),
		.C_FALL_BACK_INPUT_EN             (0),
		.C_TPG_IS_ASYNC                   (1),
		.C_TPG_FIFO_DEPTH                 (1024),
		.C_TIM_DIMENSIONS                 (0),
		.C_VID_DIMENSIONS                 (0),
		.C_VID_DEBUG                      (0),
		.C_TPG_DIMENSIONS                 (0),
		.C_TPG_DEBUG                      (0),
		.C_DEFAULT_OUT_IS_BLANK           (0),
		.C_DEFAULT_BLACK_0                (0),
		.C_DEFAULT_BLACK_1                (0),
		.C_DEFAULT_BLACK_2                (0),
		.C_DEFAULT_BLACK_3                (0),
		.C_DEFAULT_ENABLE_SOFT_LOCK       (0),
		.C_DEFAULT_ENABLE_VRR_LINEMODE    (0),
		.C_DEFAULT_FRAME_START_PULSE      (0),
		.C_DEFAULT_FRAME_START_MAX_JITTER (8),
		.C_DEFAULT_FRAME_ADJ_IGNORE_LINES (1),
		.C_DEFAULT_FRAME_ADJ_WINDOW_LINES (3),
		.C_TIM_HRESET                     (0),
		.C_TIM_VRESET                     (0),
		.C_TIM_HTOTAL                     (2200),
		.C_TIM_VTOTAL                     (1125),
		.C_TIM_HB_END                     (280),
		.C_TIM_V1B_START                  (1121),
		.C_TIM_V1B_END                    (41),
		.C_TIM_V2B_START                  (9999),
		.C_TIM_V2B_END                    (9999),
		.C_TIM_F1_START                   (0),
		.C_TIM_F2_START                   (9999),
		.C_TIM_HS_START                   (88),
		.C_TIM_HS_END                     (132),
		.C_TIM_V1S_VSTART                 (0),
		.C_TIM_V1S_HSTART                 (88),
		.C_TIM_V1S_VEND                   (5),
		.C_TIM_V1S_HEND                   (88),
		.C_TIM_V2S_VSTART                 (9999),
		.C_TIM_V2S_HSTART                 (9999),
		.C_TIM_V2S_VEND                   (9999),
		.C_TIM_V2S_HEND                   (9999),
		.C_TIM_PULSE0_VSTART              (0),
		.C_TIM_PULSE0_HSTART              (0),
		.C_TIM_PULSE0_VEND                (0),
		.C_TIM_PULSE0_HEND                (0),
		.C_TIM_PULSE1_VSTART              (4),
		.C_TIM_PULSE1_HSTART              (0),
		.C_TIM_PULSE1_VEND                (4),
		.C_TIM_PULSE1_HEND                (0),
		.C_TIM_PULSE2_VSTART              (9999),
		.C_TIM_PULSE2_HSTART              (9999),
		.C_TIM_PULSE2_VEND                (9999),
		.C_TIM_PULSE2_HEND                (9999),
		.C_TIM_PULSE3_VSTART              (9999),
		.C_TIM_PULSE3_HSTART              (9999),
		.C_TIM_PULSE3_VEND                (9999),
		.C_TIM_PULSE3_HEND                (9999),
		.C_TIM_PULSE4_VSTART              (9999),
		.C_TIM_PULSE4_HSTART              (9999),
		.C_TIM_PULSE4_VEND                (9999),
		.C_TIM_PULSE4_HEND                (9999),
		.C_TIM_PULSE5_VSTART              (9999),
		.C_TIM_PULSE5_HSTART              (9999),
		.C_TIM_PULSE5_VEND                (9999),
		.C_TIM_PULSE5_HEND                (9999),
		.C_TIM_PULSE6_VSTART              (9999),
		.C_TIM_PULSE6_HSTART              (9999),
		.C_TIM_PULSE6_VEND                (9999),
		.C_TIM_PULSE6_HEND                (9999),
		.C_TIM_PULSE7_VSTART              (9999),
		.C_TIM_PULSE7_HSTART              (9999),
		.C_TIM_PULSE7_VEND                (9999),
		.C_TIM_PULSE7_HEND                (9999)
	) intel_vvp_cvo_0 (
		.axi4s_vid_in_tdata           (axi4s_vid_in_tdata),           //   input,  width = 24,     axi4s_vid_in.tdata
		.axi4s_vid_in_tvalid          (axi4s_vid_in_tvalid),          //   input,   width = 1,                 .tvalid
		.axi4s_vid_in_tready          (axi4s_vid_in_tready),          //  output,   width = 1,                 .tready
		.axi4s_vid_in_tlast           (axi4s_vid_in_tlast),           //   input,   width = 1,                 .tlast
		.axi4s_vid_in_tuser           (axi4s_vid_in_tuser),           //   input,   width = 3,                 .tuser
		.axi4s_fr_vid_out_tdata       (axi4s_fr_vid_out_tdata),       //  output,  width = 32, axi4s_fr_vid_out.tdata
		.axi4s_fr_vid_out_tvalid      (axi4s_fr_vid_out_tvalid),      //  output,   width = 1,                 .tvalid
		.axi4s_fr_vid_out_tready      (axi4s_fr_vid_out_tready),      //   input,   width = 1,                 .tready
		.axi4s_fr_vid_out_tlast       (axi4s_fr_vid_out_tlast),       //  output,   width = 1,                 .tlast
		.axi4s_fr_vid_out_tuser       (axi4s_fr_vid_out_tuser),       //  output,   width = 4,                 .tuser
		.vid_status_vid_locked        (vid_status_vid_locked),        //  output,   width = 1,       vid_status.vid_locked
		.vid_status_vid_is_full       (vid_status_vid_is_full),       //  output,   width = 1,                 .vid_is_full
		.vid_status_vid_stall_error   (vid_status_vid_stall_error),   //  output,   width = 1,                 .vid_stall_error
		.vid_status_vid_size_mismatch (vid_status_vid_size_mismatch), //  output,   width = 1,                 .vid_size_mismatch
		.frame_start_conduit          (frame_start_conduit),          //   input,   width = 1,      frame_start.conduit
		.fr_clock_clk                 (fr_clock_clk),                 //   input,   width = 1,         fr_clock.clk
		.fr_reset_reset               (fr_reset_reset),               //   input,   width = 1,         fr_reset.reset
		.vid_clock_clk                (vid_clock_clk),                //   input,   width = 1,        vid_clock.clk
		.vid_reset_reset              (vid_reset_reset)               //   input,   width = 1,        vid_reset.reset
	);

endmodule
