module nios_system (
		input  wire        clk_clk,                                    //                               clk.clk
		output wire        intel_vvp_cvo_vid_status_vid_locked,        //          intel_vvp_cvo_vid_status.vid_locked
		output wire        intel_vvp_cvo_vid_status_vid_is_full,       //                                  .vid_is_full
		output wire        intel_vvp_cvo_vid_status_vid_stall_error,   //                                  .vid_stall_error
		output wire        intel_vvp_cvo_vid_status_vid_size_mismatch, //                                  .vid_size_mismatch
		input  wire        intel_vvp_cvo_frame_start_conduit,          //         intel_vvp_cvo_frame_start.conduit
		output wire        intel_vvp_fr2cv_cv_clk_out_clk,             //        intel_vvp_fr2cv_cv_clk_out.clk
		output wire [23:0] intel_vvp_fr2cv_cv_vid_out_vid_data,        //        intel_vvp_fr2cv_cv_vid_out.vid_data
		output wire        intel_vvp_fr2cv_cv_vid_out_underflow,       //                                  .underflow
		output wire        intel_vvp_fr2cv_cv_vid_out_vid_datavalid,   //                                  .vid_datavalid
		output wire        intel_vvp_fr2cv_cv_vid_out_vid_v_sync,      //                                  .vid_v_sync
		output wire        intel_vvp_fr2cv_cv_vid_out_vid_h_sync,      //                                  .vid_h_sync
		output wire        intel_vvp_fr2cv_cv_vid_out_vid_f,           //                                  .vid_f
		output wire        intel_vvp_fr2cv_cv_vid_out_vid_h,           //                                  .vid_h
		output wire        intel_vvp_fr2cv_cv_vid_out_vid_v,           //                                  .vid_v
		input  wire        intel_vvp_vfr_fsync_in_read,                //            intel_vvp_vfr_fsync_in.read
		output wire        sdram_clk_clk,                              //                         sdram_clk.clk
		output wire        iopll_vga_outclk1_clk,                      //                 iopll_vga_outclk1.clk
		output wire        pio_fsync_out_external_connection_export,   // pio_fsync_out_external_connection.export
		input  wire [1:0]  key_external_connection_export,             //           key_external_connection.export
		output wire [3:0]  led_external_connection_export,             //           led_external_connection.export
		input  wire [1:0]  sw_external_connection_export,              //            sw_external_connection.export
		input  wire        reset_reset_n,                              //                             reset.reset_n
		output wire        sdram_cke,                                  //                             sdram.cke
		output wire        sdram_cs_n,                                 //                                  .cs_n
		output wire        sdram_ras_n,                                //                                  .ras_n
		output wire        sdram_cas_n,                                //                                  .cas_n
		output wire        sdram_we_n,                                 //                                  .we_n
		output wire [3:0]  sdram_dqm,                                  //                                  .dqm
		output wire [12:0] sdram_addr,                                 //                                  .addr
		output wire [1:0]  sdram_ba,                                   //                                  .ba
		output wire [31:0] sdram_data_out,                             //                                  .data_out
		output wire        sdram_data_oe,                              //                                  .data_oe
		input  wire [31:0] sdram_data_in,                              //                                  .data_in
		output wire        terasic_sdcard_conduit_end_sd_clk,          //        terasic_sdcard_conduit_end.sd_clk
		inout  wire        terasic_sdcard_conduit_end_sd_cmd,          //                                  .sd_cmd
		inout  wire [3:0]  terasic_sdcard_conduit_end_sd_data          //                                  .sd_data
	);
endmodule

