// nios_system_altera_mm_interconnect_1920_horygoa.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_altera_mm_interconnect_1920_horygoa (
		input  wire [31:0]  intel_vvp_vfr_av_mm_mem_read_host_address,           //             intel_vvp_vfr_av_mm_mem_read_host.address
		output wire         intel_vvp_vfr_av_mm_mem_read_host_waitrequest,       //                                              .waitrequest
		input  wire [5:0]   intel_vvp_vfr_av_mm_mem_read_host_burstcount,        //                                              .burstcount
		input  wire         intel_vvp_vfr_av_mm_mem_read_host_read,              //                                              .read
		output wire [255:0] intel_vvp_vfr_av_mm_mem_read_host_readdata,          //                                              .readdata
		output wire         intel_vvp_vfr_av_mm_mem_read_host_readdatavalid,     //                                              .readdatavalid
		output wire [3:0]   sdram_axi4_slave_awid,                               //                              sdram_axi4_slave.awid
		output wire [25:0]  sdram_axi4_slave_awaddr,                             //                                              .awaddr
		output wire [7:0]   sdram_axi4_slave_awlen,                              //                                              .awlen
		output wire [2:0]   sdram_axi4_slave_awsize,                             //                                              .awsize
		output wire [1:0]   sdram_axi4_slave_awburst,                            //                                              .awburst
		output wire         sdram_axi4_slave_awvalid,                            //                                              .awvalid
		input  wire         sdram_axi4_slave_awready,                            //                                              .awready
		output wire [63:0]  sdram_axi4_slave_wdata,                              //                                              .wdata
		output wire [7:0]   sdram_axi4_slave_wstrb,                              //                                              .wstrb
		output wire         sdram_axi4_slave_wlast,                              //                                              .wlast
		output wire         sdram_axi4_slave_wvalid,                             //                                              .wvalid
		input  wire         sdram_axi4_slave_wready,                             //                                              .wready
		input  wire [3:0]   sdram_axi4_slave_bid,                                //                                              .bid
		input  wire [1:0]   sdram_axi4_slave_bresp,                              //                                              .bresp
		input  wire         sdram_axi4_slave_bvalid,                             //                                              .bvalid
		output wire         sdram_axi4_slave_bready,                             //                                              .bready
		output wire [3:0]   sdram_axi4_slave_arid,                               //                                              .arid
		output wire [25:0]  sdram_axi4_slave_araddr,                             //                                              .araddr
		output wire [7:0]   sdram_axi4_slave_arlen,                              //                                              .arlen
		output wire [2:0]   sdram_axi4_slave_arsize,                             //                                              .arsize
		output wire [1:0]   sdram_axi4_slave_arburst,                            //                                              .arburst
		output wire         sdram_axi4_slave_arvalid,                            //                                              .arvalid
		input  wire         sdram_axi4_slave_arready,                            //                                              .arready
		input  wire [3:0]   sdram_axi4_slave_rid,                                //                                              .rid
		input  wire [63:0]  sdram_axi4_slave_rdata,                              //                                              .rdata
		input  wire [1:0]   sdram_axi4_slave_rresp,                              //                                              .rresp
		input  wire         sdram_axi4_slave_rlast,                              //                                              .rlast
		input  wire         sdram_axi4_slave_rvalid,                             //                                              .rvalid
		output wire         sdram_axi4_slave_rready,                             //                                              .rready
		input  wire         intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset, // intel_vvp_vfr_mem_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire         iopll_outclk0_clk                                    //                                 iopll_outclk0.clk,          Clock Input
	);

	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_waitrequest;   // intel_vvp_vfr_av_mm_mem_read_host_agent:av_waitrequest -> intel_vvp_vfr_av_mm_mem_read_host_translator:uav_waitrequest
	wire  [255:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdata;      // intel_vvp_vfr_av_mm_mem_read_host_agent:av_readdata -> intel_vvp_vfr_av_mm_mem_read_host_translator:uav_readdata
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_debugaccess;   // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_debugaccess -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_debugaccess
	wire   [31:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_address;       // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_address -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_address
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_read;          // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_read -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_read
	wire   [31:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_byteenable;    // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_byteenable -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_byteenable
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdatavalid; // intel_vvp_vfr_av_mm_mem_read_host_agent:av_readdatavalid -> intel_vvp_vfr_av_mm_mem_read_host_translator:uav_readdatavalid
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_lock;          // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_lock -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_lock
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_write;         // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_write -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_write
	wire  [255:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_writedata;     // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_writedata -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_writedata
	wire   [10:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_burstcount;    // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_burstcount -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_burstcount
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_ruser;                                       // sdram_axi4_slave_translator:s0_ruser -> sdram_axi4_slave_agent:ruser
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_wuser;                                       // sdram_axi4_slave_agent:wuser -> sdram_axi4_slave_translator:s0_wuser
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_awburst;                                     // sdram_axi4_slave_agent:awburst -> sdram_axi4_slave_translator:s0_awburst
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arregion;                                    // sdram_axi4_slave_agent:arregion -> sdram_axi4_slave_translator:s0_arregion
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_awuser;                                      // sdram_axi4_slave_agent:awuser -> sdram_axi4_slave_translator:s0_awuser
	wire    [7:0] sdram_axi4_slave_agent_altera_axi_master_arlen;                                       // sdram_axi4_slave_agent:arlen -> sdram_axi4_slave_translator:s0_arlen
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arqos;                                       // sdram_axi4_slave_agent:arqos -> sdram_axi4_slave_translator:s0_arqos
	wire    [7:0] sdram_axi4_slave_agent_altera_axi_master_wstrb;                                       // sdram_axi4_slave_agent:wstrb -> sdram_axi4_slave_translator:s0_wstrb
	wire          sdram_axi4_slave_agent_altera_axi_master_wready;                                      // sdram_axi4_slave_translator:s0_wready -> sdram_axi4_slave_agent:wready
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_rid;                                         // sdram_axi4_slave_translator:s0_rid -> sdram_axi4_slave_agent:rid
	wire          sdram_axi4_slave_agent_altera_axi_master_rready;                                      // sdram_axi4_slave_agent:rready -> sdram_axi4_slave_translator:s0_rready
	wire    [7:0] sdram_axi4_slave_agent_altera_axi_master_awlen;                                       // sdram_axi4_slave_agent:awlen -> sdram_axi4_slave_translator:s0_awlen
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awqos;                                       // sdram_axi4_slave_agent:awqos -> sdram_axi4_slave_translator:s0_awqos
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arcache;                                     // sdram_axi4_slave_agent:arcache -> sdram_axi4_slave_translator:s0_arcache
	wire          sdram_axi4_slave_agent_altera_axi_master_wvalid;                                      // sdram_axi4_slave_agent:wvalid -> sdram_axi4_slave_translator:s0_wvalid
	wire   [31:0] sdram_axi4_slave_agent_altera_axi_master_araddr;                                      // sdram_axi4_slave_agent:araddr -> sdram_axi4_slave_translator:s0_araddr
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_arprot;                                      // sdram_axi4_slave_agent:arprot -> sdram_axi4_slave_translator:s0_arprot
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_awprot;                                      // sdram_axi4_slave_agent:awprot -> sdram_axi4_slave_translator:s0_awprot
	wire   [63:0] sdram_axi4_slave_agent_altera_axi_master_wdata;                                       // sdram_axi4_slave_agent:wdata -> sdram_axi4_slave_translator:s0_wdata
	wire          sdram_axi4_slave_agent_altera_axi_master_arvalid;                                     // sdram_axi4_slave_agent:arvalid -> sdram_axi4_slave_translator:s0_arvalid
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awcache;                                     // sdram_axi4_slave_agent:awcache -> sdram_axi4_slave_translator:s0_awcache
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_arid;                                        // sdram_axi4_slave_agent:arid -> sdram_axi4_slave_translator:s0_arid
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_arlock;                                      // sdram_axi4_slave_agent:arlock -> sdram_axi4_slave_translator:s0_arlock
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_awlock;                                      // sdram_axi4_slave_agent:awlock -> sdram_axi4_slave_translator:s0_awlock
	wire   [31:0] sdram_axi4_slave_agent_altera_axi_master_awaddr;                                      // sdram_axi4_slave_agent:awaddr -> sdram_axi4_slave_translator:s0_awaddr
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_bresp;                                       // sdram_axi4_slave_translator:s0_bresp -> sdram_axi4_slave_agent:bresp
	wire          sdram_axi4_slave_agent_altera_axi_master_arready;                                     // sdram_axi4_slave_translator:s0_arready -> sdram_axi4_slave_agent:arready
	wire   [63:0] sdram_axi4_slave_agent_altera_axi_master_rdata;                                       // sdram_axi4_slave_translator:s0_rdata -> sdram_axi4_slave_agent:rdata
	wire          sdram_axi4_slave_agent_altera_axi_master_awready;                                     // sdram_axi4_slave_translator:s0_awready -> sdram_axi4_slave_agent:awready
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_arburst;                                     // sdram_axi4_slave_agent:arburst -> sdram_axi4_slave_translator:s0_arburst
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_arsize;                                      // sdram_axi4_slave_agent:arsize -> sdram_axi4_slave_translator:s0_arsize
	wire          sdram_axi4_slave_agent_altera_axi_master_bready;                                      // sdram_axi4_slave_agent:bready -> sdram_axi4_slave_translator:s0_bready
	wire          sdram_axi4_slave_agent_altera_axi_master_rlast;                                       // sdram_axi4_slave_translator:s0_rlast -> sdram_axi4_slave_agent:rlast
	wire          sdram_axi4_slave_agent_altera_axi_master_wlast;                                       // sdram_axi4_slave_agent:wlast -> sdram_axi4_slave_translator:s0_wlast
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awregion;                                    // sdram_axi4_slave_agent:awregion -> sdram_axi4_slave_translator:s0_awregion
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_buser;                                       // sdram_axi4_slave_translator:s0_buser -> sdram_axi4_slave_agent:buser
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_rresp;                                       // sdram_axi4_slave_translator:s0_rresp -> sdram_axi4_slave_agent:rresp
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_awid;                                        // sdram_axi4_slave_agent:awid -> sdram_axi4_slave_translator:s0_awid
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_bid;                                         // sdram_axi4_slave_translator:s0_bid -> sdram_axi4_slave_agent:bid
	wire          sdram_axi4_slave_agent_altera_axi_master_bvalid;                                      // sdram_axi4_slave_translator:s0_bvalid -> sdram_axi4_slave_agent:bvalid
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_awsize;                                      // sdram_axi4_slave_agent:awsize -> sdram_axi4_slave_translator:s0_awsize
	wire          sdram_axi4_slave_agent_altera_axi_master_awvalid;                                     // sdram_axi4_slave_agent:awvalid -> sdram_axi4_slave_translator:s0_awvalid
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_aruser;                                      // sdram_axi4_slave_agent:aruser -> sdram_axi4_slave_translator:s0_aruser
	wire          sdram_axi4_slave_agent_altera_axi_master_rvalid;                                      // sdram_axi4_slave_translator:s0_rvalid -> sdram_axi4_slave_agent:rvalid
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_valid;                                     // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_valid -> router:sink_valid
	wire  [399:0] intel_vvp_vfr_av_mm_mem_read_host_agent_cp_data;                                      // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_data -> router:sink_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_ready;                                     // router:sink_ready -> intel_vvp_vfr_av_mm_mem_read_host_agent:cp_ready
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_startofpacket;                             // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_startofpacket -> router:sink_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_endofpacket;                               // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_endofpacket -> router:sink_endofpacket
	wire          sdram_axi4_slave_agent_write_rp_valid;                                                // sdram_axi4_slave_agent:write_rp_valid -> router_001:sink_valid
	wire  [183:0] sdram_axi4_slave_agent_write_rp_data;                                                 // sdram_axi4_slave_agent:write_rp_data -> router_001:sink_data
	wire          sdram_axi4_slave_agent_write_rp_ready;                                                // router_001:sink_ready -> sdram_axi4_slave_agent:write_rp_ready
	wire          sdram_axi4_slave_agent_write_rp_startofpacket;                                        // sdram_axi4_slave_agent:write_rp_startofpacket -> router_001:sink_startofpacket
	wire          sdram_axi4_slave_agent_write_rp_endofpacket;                                          // sdram_axi4_slave_agent:write_rp_endofpacket -> router_001:sink_endofpacket
	wire          sdram_axi4_slave_agent_read_rp_valid;                                                 // sdram_axi4_slave_agent:read_rp_valid -> router_002:sink_valid
	wire  [183:0] sdram_axi4_slave_agent_read_rp_data;                                                  // sdram_axi4_slave_agent:read_rp_data -> router_002:sink_data
	wire          sdram_axi4_slave_agent_read_rp_ready;                                                 // router_002:sink_ready -> sdram_axi4_slave_agent:read_rp_ready
	wire          sdram_axi4_slave_agent_read_rp_startofpacket;                                         // sdram_axi4_slave_agent:read_rp_startofpacket -> router_002:sink_startofpacket
	wire          sdram_axi4_slave_agent_read_rp_endofpacket;                                           // sdram_axi4_slave_agent:read_rp_endofpacket -> router_002:sink_endofpacket
	wire          router_src_valid;                                                                     // router:src_valid -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_valid
	wire  [399:0] router_src_data;                                                                      // router:src_data -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_data
	wire          router_src_ready;                                                                     // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                                   // router:src_channel -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                             // router:src_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                               // router:src_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_endofpacket
	wire  [399:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_data;                               // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_ready;                              // cmd_demux:sink_ready -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_ready
	wire    [1:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_channel;                            // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_startofpacket;                      // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_endofpacket;                        // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                                    // rsp_mux:src_valid -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_valid
	wire  [399:0] rsp_mux_src_data;                                                                     // rsp_mux:src_data -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                                    // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                                  // rsp_mux:src_channel -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                            // rsp_mux:src_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                              // rsp_mux:src_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_endofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_valid;                              // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_valid -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_valid
	wire  [399:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_data;                               // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_data -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_ready;                              // intel_vvp_vfr_av_mm_mem_read_host_agent:rp_ready -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_ready
	wire    [1:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_channel;                            // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_channel -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_channel
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_startofpacket;                      // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_endofpacket;                        // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_endofpacket
	wire          cmd_demux_src0_valid;                                                                 // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [399:0] cmd_demux_src0_data;                                                                  // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                                 // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                                               // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                                         // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                           // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                                 // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [399:0] cmd_demux_src1_data;                                                                  // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                                 // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire    [1:0] cmd_demux_src1_channel;                                                               // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                                         // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                           // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                                 // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [399:0] rsp_demux_src0_data;                                                                  // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                                 // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                                               // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                                         // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                           // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                             // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [399:0] rsp_demux_001_src0_data;                                                              // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                                             // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire    [1:0] rsp_demux_001_src0_channel;                                                           // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                                     // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                       // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          cmd_mux_src_valid;                                                                    // cmd_mux:src_valid -> sdram_axi4_slave_wr_cmd_width_adapter:in_valid
	wire  [399:0] cmd_mux_src_data;                                                                     // cmd_mux:src_data -> sdram_axi4_slave_wr_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                                    // sdram_axi4_slave_wr_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                                  // cmd_mux:src_channel -> sdram_axi4_slave_wr_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                                            // cmd_mux:src_startofpacket -> sdram_axi4_slave_wr_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                              // cmd_mux:src_endofpacket -> sdram_axi4_slave_wr_cmd_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_wr_cmd_width_adapter_src_valid;                                      // sdram_axi4_slave_wr_cmd_width_adapter:out_valid -> sdram_axi4_slave_agent:write_cp_valid
	wire  [183:0] sdram_axi4_slave_wr_cmd_width_adapter_src_data;                                       // sdram_axi4_slave_wr_cmd_width_adapter:out_data -> sdram_axi4_slave_agent:write_cp_data
	wire          sdram_axi4_slave_wr_cmd_width_adapter_src_ready;                                      // sdram_axi4_slave_agent:write_cp_ready -> sdram_axi4_slave_wr_cmd_width_adapter:out_ready
	wire    [1:0] sdram_axi4_slave_wr_cmd_width_adapter_src_channel;                                    // sdram_axi4_slave_wr_cmd_width_adapter:out_channel -> sdram_axi4_slave_agent:write_cp_channel
	wire          sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket;                              // sdram_axi4_slave_wr_cmd_width_adapter:out_startofpacket -> sdram_axi4_slave_agent:write_cp_startofpacket
	wire          sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket;                                // sdram_axi4_slave_wr_cmd_width_adapter:out_endofpacket -> sdram_axi4_slave_agent:write_cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                                // cmd_mux_001:src_valid -> sdram_axi4_slave_rd_cmd_width_adapter:in_valid
	wire  [399:0] cmd_mux_001_src_data;                                                                 // cmd_mux_001:src_data -> sdram_axi4_slave_rd_cmd_width_adapter:in_data
	wire          cmd_mux_001_src_ready;                                                                // sdram_axi4_slave_rd_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
	wire    [1:0] cmd_mux_001_src_channel;                                                              // cmd_mux_001:src_channel -> sdram_axi4_slave_rd_cmd_width_adapter:in_channel
	wire          cmd_mux_001_src_startofpacket;                                                        // cmd_mux_001:src_startofpacket -> sdram_axi4_slave_rd_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                          // cmd_mux_001:src_endofpacket -> sdram_axi4_slave_rd_cmd_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_rd_cmd_width_adapter_src_valid;                                      // sdram_axi4_slave_rd_cmd_width_adapter:out_valid -> sdram_axi4_slave_agent:read_cp_valid
	wire  [183:0] sdram_axi4_slave_rd_cmd_width_adapter_src_data;                                       // sdram_axi4_slave_rd_cmd_width_adapter:out_data -> sdram_axi4_slave_agent:read_cp_data
	wire          sdram_axi4_slave_rd_cmd_width_adapter_src_ready;                                      // sdram_axi4_slave_agent:read_cp_ready -> sdram_axi4_slave_rd_cmd_width_adapter:out_ready
	wire    [1:0] sdram_axi4_slave_rd_cmd_width_adapter_src_channel;                                    // sdram_axi4_slave_rd_cmd_width_adapter:out_channel -> sdram_axi4_slave_agent:read_cp_channel
	wire          sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket;                              // sdram_axi4_slave_rd_cmd_width_adapter:out_startofpacket -> sdram_axi4_slave_agent:read_cp_startofpacket
	wire          sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket;                                // sdram_axi4_slave_rd_cmd_width_adapter:out_endofpacket -> sdram_axi4_slave_agent:read_cp_endofpacket
	wire          router_001_src_valid;                                                                 // router_001:src_valid -> sdram_axi4_slave_wr_rsp_width_adapter:in_valid
	wire  [183:0] router_001_src_data;                                                                  // router_001:src_data -> sdram_axi4_slave_wr_rsp_width_adapter:in_data
	wire          router_001_src_ready;                                                                 // sdram_axi4_slave_wr_rsp_width_adapter:in_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                                               // router_001:src_channel -> sdram_axi4_slave_wr_rsp_width_adapter:in_channel
	wire          router_001_src_startofpacket;                                                         // router_001:src_startofpacket -> sdram_axi4_slave_wr_rsp_width_adapter:in_startofpacket
	wire          router_001_src_endofpacket;                                                           // router_001:src_endofpacket -> sdram_axi4_slave_wr_rsp_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_wr_rsp_width_adapter_src_valid;                                      // sdram_axi4_slave_wr_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [399:0] sdram_axi4_slave_wr_rsp_width_adapter_src_data;                                       // sdram_axi4_slave_wr_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          sdram_axi4_slave_wr_rsp_width_adapter_src_ready;                                      // rsp_demux:sink_ready -> sdram_axi4_slave_wr_rsp_width_adapter:out_ready
	wire    [1:0] sdram_axi4_slave_wr_rsp_width_adapter_src_channel;                                    // sdram_axi4_slave_wr_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          sdram_axi4_slave_wr_rsp_width_adapter_src_startofpacket;                              // sdram_axi4_slave_wr_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          sdram_axi4_slave_wr_rsp_width_adapter_src_endofpacket;                                // sdram_axi4_slave_wr_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          router_002_src_valid;                                                                 // router_002:src_valid -> sdram_axi4_slave_rd_rsp_width_adapter:in_valid
	wire  [183:0] router_002_src_data;                                                                  // router_002:src_data -> sdram_axi4_slave_rd_rsp_width_adapter:in_data
	wire          router_002_src_ready;                                                                 // sdram_axi4_slave_rd_rsp_width_adapter:in_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                                               // router_002:src_channel -> sdram_axi4_slave_rd_rsp_width_adapter:in_channel
	wire          router_002_src_startofpacket;                                                         // router_002:src_startofpacket -> sdram_axi4_slave_rd_rsp_width_adapter:in_startofpacket
	wire          router_002_src_endofpacket;                                                           // router_002:src_endofpacket -> sdram_axi4_slave_rd_rsp_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_rd_rsp_width_adapter_src_valid;                                      // sdram_axi4_slave_rd_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
	wire  [399:0] sdram_axi4_slave_rd_rsp_width_adapter_src_data;                                       // sdram_axi4_slave_rd_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
	wire          sdram_axi4_slave_rd_rsp_width_adapter_src_ready;                                      // rsp_demux_001:sink_ready -> sdram_axi4_slave_rd_rsp_width_adapter:out_ready
	wire    [1:0] sdram_axi4_slave_rd_rsp_width_adapter_src_channel;                                    // sdram_axi4_slave_rd_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
	wire          sdram_axi4_slave_rd_rsp_width_adapter_src_startofpacket;                              // sdram_axi4_slave_rd_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          sdram_axi4_slave_rd_rsp_width_adapter_src_endofpacket;                                // sdram_axi4_slave_rd_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
	wire    [1:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_valid_data;                             // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_valid -> cmd_demux:sink_valid

	nios_system_altera_merlin_master_translator_193_lgcew2q #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (6),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (11),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) intel_vvp_vfr_av_mm_mem_read_host_translator (
		.clk                    (iopll_outclk0_clk),                                                                                                                                                                                                                                                     //   input,    width = 1,                       clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                                                                                                                                                                                                   //   input,    width = 1,                     reset.reset
		.uav_address            (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_address),                                                                                                                                                                                        //  output,   width = 32, avalon_universal_master_0.address
		.uav_burstcount         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_burstcount),                                                                                                                                                                                     //  output,   width = 11,                          .burstcount
		.uav_read               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_read),                                                                                                                                                                                           //  output,    width = 1,                          .read
		.uav_write              (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_write),                                                                                                                                                                                          //  output,    width = 1,                          .write
		.uav_waitrequest        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_waitrequest),                                                                                                                                                                                    //   input,    width = 1,                          .waitrequest
		.uav_readdatavalid      (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdatavalid),                                                                                                                                                                                  //   input,    width = 1,                          .readdatavalid
		.uav_byteenable         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_byteenable),                                                                                                                                                                                     //  output,   width = 32,                          .byteenable
		.uav_readdata           (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdata),                                                                                                                                                                                       //   input,  width = 256,                          .readdata
		.uav_writedata          (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_writedata),                                                                                                                                                                                      //  output,  width = 256,                          .writedata
		.uav_lock               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_lock),                                                                                                                                                                                           //  output,    width = 1,                          .lock
		.uav_debugaccess        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_debugaccess),                                                                                                                                                                                    //  output,    width = 1,                          .debugaccess
		.av_address             (intel_vvp_vfr_av_mm_mem_read_host_address),                                                                                                                                                                                                                             //   input,   width = 32,      avalon_anti_master_0.address
		.av_waitrequest         (intel_vvp_vfr_av_mm_mem_read_host_waitrequest),                                                                                                                                                                                                                         //  output,    width = 1,                          .waitrequest
		.av_burstcount          (intel_vvp_vfr_av_mm_mem_read_host_burstcount),                                                                                                                                                                                                                          //   input,    width = 6,                          .burstcount
		.av_read                (intel_vvp_vfr_av_mm_mem_read_host_read),                                                                                                                                                                                                                                //   input,    width = 1,                          .read
		.av_readdata            (intel_vvp_vfr_av_mm_mem_read_host_readdata),                                                                                                                                                                                                                            //  output,  width = 256,                          .readdata
		.av_readdatavalid       (intel_vvp_vfr_av_mm_mem_read_host_readdatavalid),                                                                                                                                                                                                                       //  output,    width = 1,                          .readdatavalid
		.av_byteenable          (32'b11111111111111111111111111111111),                                                                                                                                                                                                                                  // (terminated),                                         
		.av_beginbursttransfer  (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_begintransfer       (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_chipselect          (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_write               (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_writedata           (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated),                                         
		.av_lock                (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_debugaccess         (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.uav_outputenable       (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.uav_clken              (),                                                                                                                                                                                                                                                                      // (terminated),                                         
		.av_clken               (1'b1),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.uav_response           (2'b00),                                                                                                                                                                                                                                                                 // (terminated),                                         
		.av_response            (),                                                                                                                                                                                                                                                                      // (terminated),                                         
		.uav_writeresponsevalid (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_writeresponsevalid  ()                                                                                                                                                                                                                                                                       // (terminated),                                         
	);

	nios_system_altera_merlin_axi_translator_1974_xfkiwxi #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (1),
		.USE_M0_AWREGION                   (0),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (0),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (0),
		.USE_M0_AWPROT                     (0),
		.USE_S0_AWPROT                     (1),
		.USE_S0_AWQOS                      (1),
		.USE_M0_AWQOS                      (0),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (1),
		.USE_M0_ARREGION                   (0),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (0),
		.USE_M0_ARCACHE                    (0),
		.USE_M0_ARQOS                      (0),
		.USE_M0_ARPROT                     (0),
		.USE_S0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (1),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.USE_S0_AWUSER                     (1),
		.USE_S0_ARUSER                     (1),
		.USE_S0_WUSER                      (1),
		.USE_S0_RUSER                      (1),
		.USE_S0_BUSER                      (1),
		.USE_M0_AWUSER                     (0),
		.USE_M0_ARUSER                     (0),
		.USE_M0_WUSER                      (0),
		.USE_M0_RUSER                      (0),
		.USE_M0_BUSER                      (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_M0_AWAKEUP                    (0),
		.USE_M0_WPOISON                    (0),
		.USE_M0_RPOISON                    (0),
		.USE_M0_AWTRACE                    (0),
		.USE_M0_ARTRACE                    (0),
		.USE_M0_WTRACE                     (0),
		.USE_M0_BTRACE                     (0),
		.USE_M0_RTRACE                     (0),
		.USE_M0_WDATACHK                   (0),
		.USE_M0_RDATACHK                   (0),
		.USE_M0_AWUNIQUE                   (0),
		.USE_S0_AWAKEUP                    (0),
		.USE_S0_WPOISON                    (0),
		.USE_S0_RPOISON                    (0),
		.USE_S0_AWTRACE                    (0),
		.USE_S0_ARTRACE                    (0),
		.USE_S0_WTRACE                     (0),
		.USE_S0_BTRACE                     (0),
		.USE_S0_RTRACE                     (0),
		.USE_S0_WDATACHK                   (0),
		.USE_S0_RDATACHK                   (0),
		.USE_S0_AWUSER_ADDRCHK             (1),
		.USE_S0_AWUSER_SAI                 (1),
		.USE_S0_ARUSER_ADDRCHK             (1),
		.USE_S0_ARUSER_SAI                 (1),
		.USE_S0_WUSER_DATACHK              (1),
		.USE_S0_WUSER_POISON               (1),
		.USE_S0_RUSER_DATACHK              (1),
		.USE_S0_WUSER_DATA                 (1),
		.USE_S0_RUSER_DATA                 (1),
		.USE_S0_RUSER_POISON               (1),
		.USE_S0_AWUNIQUE                   (1),
		.M0_ID_WIDTH                       (4),
		.DATA_WIDTH                        (64),
		.M0_SAI_WIDTH                      (1),
		.S0_SAI_WIDTH                      (1),
		.USER_DATA_WIDTH                   (1),
		.M0_USER_ADDRCHK_WIDTH             (1),
		.S0_USER_ADDRCHK_WIDTH             (1),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (26),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (32),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) sdram_axi4_slave_translator (
		.aclk              (iopll_outclk0_clk),                                    //   input,   width = 1,       clk.clk
		.aresetn           (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (sdram_axi4_slave_awid),                                //  output,   width = 4,        m0.awid
		.m0_awaddr         (sdram_axi4_slave_awaddr),                              //  output,  width = 26,          .awaddr
		.m0_awlen          (sdram_axi4_slave_awlen),                               //  output,   width = 8,          .awlen
		.m0_awsize         (sdram_axi4_slave_awsize),                              //  output,   width = 3,          .awsize
		.m0_awburst        (sdram_axi4_slave_awburst),                             //  output,   width = 2,          .awburst
		.m0_awvalid        (sdram_axi4_slave_awvalid),                             //  output,   width = 1,          .awvalid
		.m0_awready        (sdram_axi4_slave_awready),                             //   input,   width = 1,          .awready
		.m0_wdata          (sdram_axi4_slave_wdata),                               //  output,  width = 64,          .wdata
		.m0_wstrb          (sdram_axi4_slave_wstrb),                               //  output,   width = 8,          .wstrb
		.m0_wlast          (sdram_axi4_slave_wlast),                               //  output,   width = 1,          .wlast
		.m0_wvalid         (sdram_axi4_slave_wvalid),                              //  output,   width = 1,          .wvalid
		.m0_wready         (sdram_axi4_slave_wready),                              //   input,   width = 1,          .wready
		.m0_bid            (sdram_axi4_slave_bid),                                 //   input,   width = 4,          .bid
		.m0_bresp          (sdram_axi4_slave_bresp),                               //   input,   width = 2,          .bresp
		.m0_bvalid         (sdram_axi4_slave_bvalid),                              //   input,   width = 1,          .bvalid
		.m0_bready         (sdram_axi4_slave_bready),                              //  output,   width = 1,          .bready
		.m0_arid           (sdram_axi4_slave_arid),                                //  output,   width = 4,          .arid
		.m0_araddr         (sdram_axi4_slave_araddr),                              //  output,  width = 26,          .araddr
		.m0_arlen          (sdram_axi4_slave_arlen),                               //  output,   width = 8,          .arlen
		.m0_arsize         (sdram_axi4_slave_arsize),                              //  output,   width = 3,          .arsize
		.m0_arburst        (sdram_axi4_slave_arburst),                             //  output,   width = 2,          .arburst
		.m0_arvalid        (sdram_axi4_slave_arvalid),                             //  output,   width = 1,          .arvalid
		.m0_arready        (sdram_axi4_slave_arready),                             //   input,   width = 1,          .arready
		.m0_rid            (sdram_axi4_slave_rid),                                 //   input,   width = 4,          .rid
		.m0_rdata          (sdram_axi4_slave_rdata),                               //   input,  width = 64,          .rdata
		.m0_rresp          (sdram_axi4_slave_rresp),                               //   input,   width = 2,          .rresp
		.m0_rlast          (sdram_axi4_slave_rlast),                               //   input,   width = 1,          .rlast
		.m0_rvalid         (sdram_axi4_slave_rvalid),                              //   input,   width = 1,          .rvalid
		.m0_rready         (sdram_axi4_slave_rready),                              //  output,   width = 1,          .rready
		.s0_awid           (sdram_axi4_slave_agent_altera_axi_master_awid),        //   input,   width = 1,        s0.awid
		.s0_awaddr         (sdram_axi4_slave_agent_altera_axi_master_awaddr),      //   input,  width = 32,          .awaddr
		.s0_awlen          (sdram_axi4_slave_agent_altera_axi_master_awlen),       //   input,   width = 8,          .awlen
		.s0_awsize         (sdram_axi4_slave_agent_altera_axi_master_awsize),      //   input,   width = 3,          .awsize
		.s0_awburst        (sdram_axi4_slave_agent_altera_axi_master_awburst),     //   input,   width = 2,          .awburst
		.s0_awlock         (sdram_axi4_slave_agent_altera_axi_master_awlock),      //   input,   width = 1,          .awlock
		.s0_awcache        (sdram_axi4_slave_agent_altera_axi_master_awcache),     //   input,   width = 4,          .awcache
		.s0_awprot         (sdram_axi4_slave_agent_altera_axi_master_awprot),      //   input,   width = 3,          .awprot
		.s0_awuser         (sdram_axi4_slave_agent_altera_axi_master_awuser),      //   input,   width = 1,          .awuser
		.s0_awqos          (sdram_axi4_slave_agent_altera_axi_master_awqos),       //   input,   width = 4,          .awqos
		.s0_awregion       (sdram_axi4_slave_agent_altera_axi_master_awregion),    //   input,   width = 4,          .awregion
		.s0_awvalid        (sdram_axi4_slave_agent_altera_axi_master_awvalid),     //   input,   width = 1,          .awvalid
		.s0_awready        (sdram_axi4_slave_agent_altera_axi_master_awready),     //  output,   width = 1,          .awready
		.s0_wdata          (sdram_axi4_slave_agent_altera_axi_master_wdata),       //   input,  width = 64,          .wdata
		.s0_wstrb          (sdram_axi4_slave_agent_altera_axi_master_wstrb),       //   input,   width = 8,          .wstrb
		.s0_wlast          (sdram_axi4_slave_agent_altera_axi_master_wlast),       //   input,   width = 1,          .wlast
		.s0_wvalid         (sdram_axi4_slave_agent_altera_axi_master_wvalid),      //   input,   width = 1,          .wvalid
		.s0_wuser          (sdram_axi4_slave_agent_altera_axi_master_wuser),       //   input,   width = 1,          .wuser
		.s0_wready         (sdram_axi4_slave_agent_altera_axi_master_wready),      //  output,   width = 1,          .wready
		.s0_bid            (sdram_axi4_slave_agent_altera_axi_master_bid),         //  output,   width = 1,          .bid
		.s0_bresp          (sdram_axi4_slave_agent_altera_axi_master_bresp),       //  output,   width = 2,          .bresp
		.s0_buser          (sdram_axi4_slave_agent_altera_axi_master_buser),       //  output,   width = 1,          .buser
		.s0_bvalid         (sdram_axi4_slave_agent_altera_axi_master_bvalid),      //  output,   width = 1,          .bvalid
		.s0_bready         (sdram_axi4_slave_agent_altera_axi_master_bready),      //   input,   width = 1,          .bready
		.s0_arid           (sdram_axi4_slave_agent_altera_axi_master_arid),        //   input,   width = 1,          .arid
		.s0_araddr         (sdram_axi4_slave_agent_altera_axi_master_araddr),      //   input,  width = 32,          .araddr
		.s0_arlen          (sdram_axi4_slave_agent_altera_axi_master_arlen),       //   input,   width = 8,          .arlen
		.s0_arsize         (sdram_axi4_slave_agent_altera_axi_master_arsize),      //   input,   width = 3,          .arsize
		.s0_arburst        (sdram_axi4_slave_agent_altera_axi_master_arburst),     //   input,   width = 2,          .arburst
		.s0_arlock         (sdram_axi4_slave_agent_altera_axi_master_arlock),      //   input,   width = 1,          .arlock
		.s0_arcache        (sdram_axi4_slave_agent_altera_axi_master_arcache),     //   input,   width = 4,          .arcache
		.s0_arprot         (sdram_axi4_slave_agent_altera_axi_master_arprot),      //   input,   width = 3,          .arprot
		.s0_aruser         (sdram_axi4_slave_agent_altera_axi_master_aruser),      //   input,   width = 1,          .aruser
		.s0_arqos          (sdram_axi4_slave_agent_altera_axi_master_arqos),       //   input,   width = 4,          .arqos
		.s0_arregion       (sdram_axi4_slave_agent_altera_axi_master_arregion),    //   input,   width = 4,          .arregion
		.s0_arvalid        (sdram_axi4_slave_agent_altera_axi_master_arvalid),     //   input,   width = 1,          .arvalid
		.s0_arready        (sdram_axi4_slave_agent_altera_axi_master_arready),     //  output,   width = 1,          .arready
		.s0_rid            (sdram_axi4_slave_agent_altera_axi_master_rid),         //  output,   width = 1,          .rid
		.s0_rdata          (sdram_axi4_slave_agent_altera_axi_master_rdata),       //  output,  width = 64,          .rdata
		.s0_rresp          (sdram_axi4_slave_agent_altera_axi_master_rresp),       //  output,   width = 2,          .rresp
		.s0_rlast          (sdram_axi4_slave_agent_altera_axi_master_rlast),       //  output,   width = 1,          .rlast
		.s0_rvalid         (sdram_axi4_slave_agent_altera_axi_master_rvalid),      //  output,   width = 1,          .rvalid
		.s0_rready         (sdram_axi4_slave_agent_altera_axi_master_rready),      //   input,   width = 1,          .rready
		.s0_ruser          (sdram_axi4_slave_agent_altera_axi_master_ruser),       //  output,   width = 1,          .ruser
		.m0_awlock         (),                                                     // (terminated),                        
		.m0_awcache        (),                                                     // (terminated),                        
		.m0_awprot         (),                                                     // (terminated),                        
		.m0_awuser         (),                                                     // (terminated),                        
		.m0_awuser_addrchk (),                                                     // (terminated),                        
		.m0_awuser_sai     (),                                                     // (terminated),                        
		.m0_awqos          (),                                                     // (terminated),                        
		.m0_awregion       (),                                                     // (terminated),                        
		.m0_wuser          (),                                                     // (terminated),                        
		.m0_wuser_datachk  (),                                                     // (terminated),                        
		.m0_wuser_data     (),                                                     // (terminated),                        
		.m0_wuser_poison   (),                                                     // (terminated),                        
		.m0_buser          (1'b0),                                                 // (terminated),                        
		.m0_arlock         (),                                                     // (terminated),                        
		.m0_arcache        (),                                                     // (terminated),                        
		.m0_arprot         (),                                                     // (terminated),                        
		.m0_aruser         (),                                                     // (terminated),                        
		.m0_aruser_addrchk (),                                                     // (terminated),                        
		.m0_aruser_sai     (),                                                     // (terminated),                        
		.m0_arqos          (),                                                     // (terminated),                        
		.m0_arregion       (),                                                     // (terminated),                        
		.m0_ruser          (1'b0),                                                 // (terminated),                        
		.m0_ruser_datachk  (8'b00000000),                                          // (terminated),                        
		.m0_ruser_data     (1'b0),                                                 // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                 // (terminated),                        
		.s0_awuser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_awuser_sai     (1'b0),                                                 // (terminated),                        
		.s0_wuser_datachk  (8'b00000000),                                          // (terminated),                        
		.s0_wuser_data     (1'b0),                                                 // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                 // (terminated),                        
		.s0_aruser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_aruser_sai     (1'b0),                                                 // (terminated),                        
		.s0_ruser_datachk  (),                                                     // (terminated),                        
		.s0_ruser_data     (),                                                     // (terminated),                        
		.s0_ruser_poison   (),                                                     // (terminated),                        
		.m0_awakeup        (),                                                     // (terminated),                        
		.m0_awtrace        (),                                                     // (terminated),                        
		.m0_artrace        (),                                                     // (terminated),                        
		.m0_wpoison        (),                                                     // (terminated),                        
		.m0_wdatachk       (),                                                     // (terminated),                        
		.m0_wtrace         (),                                                     // (terminated),                        
		.m0_btrace         (1'b0),                                                 // (terminated),                        
		.m0_rpoison        (1'b0),                                                 // (terminated),                        
		.m0_rdatachk       (8'b00000000),                                          // (terminated),                        
		.m0_rtrace         (1'b0),                                                 // (terminated),                        
		.m0_wid            (),                                                     // (terminated),                        
		.m0_ardomain       (),                                                     // (terminated),                        
		.m0_arsnoop        (),                                                     // (terminated),                        
		.m0_arbar          (),                                                     // (terminated),                        
		.m0_awdomain       (),                                                     // (terminated),                        
		.m0_awsnoop        (),                                                     // (terminated),                        
		.m0_awbar          (),                                                     // (terminated),                        
		.m0_awunique       (),                                                     // (terminated),                        
		.s0_awakeup        (1'b0),                                                 // (terminated),                        
		.s0_awtrace        (1'b0),                                                 // (terminated),                        
		.s0_artrace        (1'b0),                                                 // (terminated),                        
		.s0_wpoison        (1'b0),                                                 // (terminated),                        
		.s0_wdatachk       (8'b00000000),                                          // (terminated),                        
		.s0_wtrace         (1'b0),                                                 // (terminated),                        
		.s0_btrace         (),                                                     // (terminated),                        
		.s0_rpoison        (),                                                     // (terminated),                        
		.s0_rdatachk       (),                                                     // (terminated),                        
		.s0_rtrace         (),                                                     // (terminated),                        
		.s0_wid            (1'b0),                                                 // (terminated),                        
		.s0_ardomain       (2'b00),                                                // (terminated),                        
		.s0_arsnoop        (4'b0000),                                              // (terminated),                        
		.s0_arbar          (2'b00),                                                // (terminated),                        
		.s0_awdomain       (2'b00),                                                // (terminated),                        
		.s0_awsnoop        (3'b000),                                               // (terminated),                        
		.s0_awbar          (2'b00),                                                // (terminated),                        
		.s0_awunique       (1'b0)                                                  // (terminated),                        
	);

	nios_system_altera_merlin_master_agent_1931_szfayly #(
		.PKT_WUNIQUE               (381),
		.PKT_DOMAIN_H              (380),
		.PKT_DOMAIN_L              (379),
		.PKT_SNOOP_H               (378),
		.PKT_SNOOP_L               (375),
		.PKT_BARRIER_H             (374),
		.PKT_BARRIER_L             (373),
		.PKT_ORI_BURST_SIZE_H      (372),
		.PKT_ORI_BURST_SIZE_L      (370),
		.PKT_RESPONSE_STATUS_H     (369),
		.PKT_RESPONSE_STATUS_L     (368),
		.PKT_QOS_H                 (357),
		.PKT_QOS_L                 (354),
		.PKT_DATA_SIDEBAND_H       (352),
		.PKT_DATA_SIDEBAND_L       (352),
		.PKT_ADDR_SIDEBAND_H       (351),
		.PKT_ADDR_SIDEBAND_L       (351),
		.PKT_BURST_TYPE_H          (350),
		.PKT_BURST_TYPE_L          (349),
		.PKT_CACHE_H               (367),
		.PKT_CACHE_L               (364),
		.PKT_THREAD_ID_H           (360),
		.PKT_THREAD_ID_L           (360),
		.PKT_BURST_SIZE_H          (348),
		.PKT_BURST_SIZE_L          (346),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (353),
		.PKT_PROTECTION_H          (363),
		.PKT_PROTECTION_L          (361),
		.PKT_BURSTWRAP_H           (345),
		.PKT_BURSTWRAP_L           (338),
		.PKT_BYTE_CNT_H            (337),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (358),
		.PKT_SRC_ID_L              (358),
		.PKT_DEST_ID_H             (359),
		.PKT_DEST_ID_L             (359),
		.PKT_POISON_H              (382),
		.PKT_POISON_L              (382),
		.PKT_DATACHK_H             (383),
		.PKT_DATACHK_L             (383),
		.PKT_ADDRCHK_H             (386),
		.PKT_ADDRCHK_L             (385),
		.PKT_SAI_H                 (387),
		.PKT_SAI_L                 (387),
		.PKT_USER_DATA_H           (384),
		.PKT_USER_DATA_L           (384),
		.PKT_ATRACE                (397),
		.PKT_TRACE                 (398),
		.PKT_AWAKEUP               (399),
		.ST_DATA_W                 (400),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (11),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (255),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.OPTIMIZED_READS_WITH_BE   (0)
	) intel_vvp_vfr_av_mm_mem_read_host_agent (
		.clk                   (iopll_outclk0_clk),                                                                    //   input,    width = 1,       clk.clk
		.reset                 (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                  //   input,    width = 1, clk_reset.reset
		.av_address            (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_address),       //   input,   width = 32,        av.address
		.av_write              (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_writedata),     //   input,  width = 256,          .writedata
		.av_readdata           (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdata),      //  output,  width = 256,          .readdata
		.av_waitrequest        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_byteenable),    //   input,   width = 32,          .byteenable
		.av_burstcount         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_burstcount),    //   input,   width = 11,          .burstcount
		.av_debugaccess        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_data),                                      //  output,  width = 400,          .data
		.cp_startofpacket      (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_data),                               //   input,  width = 400,          .data
		.rp_channel            (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_channel),                            //   input,    width = 2,          .channel
		.rp_startofpacket      (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                                     // (terminated),                         
		.av_writeresponsevalid ()                                                                                      // (terminated),                         
	);

	nios_system_altera_merlin_axi_slave_ni_19112_pzcr2iy #(
		.PKT_QOS_H                   (141),
		.PKT_QOS_L                   (138),
		.PKT_THREAD_ID_H             (144),
		.PKT_THREAD_ID_L             (144),
		.PKT_RESPONSE_STATUS_H       (153),
		.PKT_RESPONSE_STATUS_L       (152),
		.PKT_BEGIN_BURST             (137),
		.PKT_CACHE_H                 (151),
		.PKT_CACHE_L                 (148),
		.PKT_DATA_SIDEBAND_H         (136),
		.PKT_DATA_SIDEBAND_L         (136),
		.PKT_ADDR_SIDEBAND_H         (135),
		.PKT_ADDR_SIDEBAND_L         (135),
		.PKT_BURST_TYPE_H            (134),
		.PKT_BURST_TYPE_L            (133),
		.PKT_PROTECTION_H            (147),
		.PKT_PROTECTION_L            (145),
		.PKT_BURST_SIZE_H            (132),
		.PKT_BURST_SIZE_L            (130),
		.PKT_BURSTWRAP_H             (129),
		.PKT_BURSTWRAP_L             (122),
		.PKT_BYTE_CNT_H              (121),
		.PKT_BYTE_CNT_L              (110),
		.PKT_ADDR_H                  (103),
		.PKT_ADDR_L                  (72),
		.PKT_TRANS_EXCLUSIVE         (109),
		.PKT_TRANS_LOCK              (108),
		.PKT_TRANS_COMPRESSED_READ   (104),
		.PKT_TRANS_POSTED            (105),
		.PKT_TRANS_WRITE             (106),
		.PKT_TRANS_READ              (107),
		.PKT_DATA_H                  (63),
		.PKT_DATA_L                  (0),
		.PKT_BYTEEN_H                (71),
		.PKT_BYTEEN_L                (64),
		.PKT_SRC_ID_H                (142),
		.PKT_SRC_ID_L                (142),
		.PKT_DEST_ID_H               (143),
		.PKT_DEST_ID_L               (143),
		.PKT_ORI_BURST_SIZE_L        (154),
		.PKT_ORI_BURST_SIZE_H        (156),
		.PKT_DOMAIN_L                (163),
		.PKT_DOMAIN_H                (164),
		.PKT_SNOOP_L                 (159),
		.PKT_SNOOP_H                 (162),
		.PKT_BARRIER_L               (157),
		.PKT_BARRIER_H               (158),
		.PKT_WUNIQUE                 (165),
		.PKT_EOP_OOO                 (172),
		.PKT_SOP_OOO                 (173),
		.PKT_AWAKEUP                 (183),
		.PKT_ATRACE                  (181),
		.PKT_TRACE                   (182),
		.PKT_POISON_H                (166),
		.PKT_POISON_L                (166),
		.PKT_DATACHK_H               (167),
		.PKT_DATACHK_L               (167),
		.PKT_ADDRCHK_H               (170),
		.PKT_ADDRCHK_L               (169),
		.PKT_SAI_H                   (171),
		.PKT_SAI_L                   (171),
		.PKT_USER_DATA_H             (168),
		.PKT_USER_DATA_L             (168),
		.SAI_WIDTH                   (1),
		.ADDRCHK_WIDTH               (1),
		.USER_DATA_WIDTH             (1),
		.ADDR_USER_WIDTH             (1),
		.DATA_USER_WIDTH             (1),
		.ST_DATA_W                   (184),
		.ADDR_WIDTH                  (32),
		.RDATA_WIDTH                 (64),
		.WDATA_WIDTH                 (64),
		.ST_CHANNEL_W                (2),
		.AXI_SLAVE_ID_W              (1),
		.ACE_LITE_SUPPORT            (0),
		.PASS_ID_TO_SLAVE            (1),
		.AXI_VERSION                 ("AXI4"),
		.WRITE_ACCEPTANCE_CAPABILITY (1),
		.READ_ACCEPTANCE_CAPABILITY  (1),
		.USE_PKT_DATACHK             (0),
		.USE_PKT_ADDRCHK             (0),
		.SYNC_RESET                  (1),
		.USE_MEMORY_BLOCKS           (0),
		.ROLE_BASED_USER             (0),
		.ENABLE_OOO                  (0),
		.REORDER_BUFFER              (0)
	) sdram_axi4_slave_agent (
		.aclk                   (iopll_outclk0_clk),                                       //   input,    width = 1,        clock_sink.clk
		.aresetn                (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),    //   input,    width = 1,        reset_sink.reset_n
		.read_cp_valid          (sdram_axi4_slave_rd_cmd_width_adapter_src_valid),         //   input,    width = 1,           read_cp.valid
		.read_cp_ready          (sdram_axi4_slave_rd_cmd_width_adapter_src_ready),         //  output,    width = 1,                  .ready
		.read_cp_data           (sdram_axi4_slave_rd_cmd_width_adapter_src_data),          //   input,  width = 184,                  .data
		.read_cp_channel        (sdram_axi4_slave_rd_cmd_width_adapter_src_channel),       //   input,    width = 2,                  .channel
		.read_cp_startofpacket  (sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket), //   input,    width = 1,                  .startofpacket
		.read_cp_endofpacket    (sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,                  .endofpacket
		.write_cp_ready         (sdram_axi4_slave_wr_cmd_width_adapter_src_ready),         //  output,    width = 1,          write_cp.ready
		.write_cp_valid         (sdram_axi4_slave_wr_cmd_width_adapter_src_valid),         //   input,    width = 1,                  .valid
		.write_cp_data          (sdram_axi4_slave_wr_cmd_width_adapter_src_data),          //   input,  width = 184,                  .data
		.write_cp_channel       (sdram_axi4_slave_wr_cmd_width_adapter_src_channel),       //   input,    width = 2,                  .channel
		.write_cp_startofpacket (sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket), //   input,    width = 1,                  .startofpacket
		.write_cp_endofpacket   (sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,                  .endofpacket
		.read_rp_ready          (sdram_axi4_slave_agent_read_rp_ready),                    //   input,    width = 1,           read_rp.ready
		.read_rp_valid          (sdram_axi4_slave_agent_read_rp_valid),                    //  output,    width = 1,                  .valid
		.read_rp_data           (sdram_axi4_slave_agent_read_rp_data),                     //  output,  width = 184,                  .data
		.read_rp_startofpacket  (sdram_axi4_slave_agent_read_rp_startofpacket),            //  output,    width = 1,                  .startofpacket
		.read_rp_endofpacket    (sdram_axi4_slave_agent_read_rp_endofpacket),              //  output,    width = 1,                  .endofpacket
		.write_rp_ready         (sdram_axi4_slave_agent_write_rp_ready),                   //   input,    width = 1,          write_rp.ready
		.write_rp_valid         (sdram_axi4_slave_agent_write_rp_valid),                   //  output,    width = 1,                  .valid
		.write_rp_data          (sdram_axi4_slave_agent_write_rp_data),                    //  output,  width = 184,                  .data
		.write_rp_startofpacket (sdram_axi4_slave_agent_write_rp_startofpacket),           //  output,    width = 1,                  .startofpacket
		.write_rp_endofpacket   (sdram_axi4_slave_agent_write_rp_endofpacket),             //  output,    width = 1,                  .endofpacket
		.awid                   (sdram_axi4_slave_agent_altera_axi_master_awid),           //  output,    width = 1, altera_axi_master.awid
		.awaddr                 (sdram_axi4_slave_agent_altera_axi_master_awaddr),         //  output,   width = 32,                  .awaddr
		.awlen                  (sdram_axi4_slave_agent_altera_axi_master_awlen),          //  output,    width = 8,                  .awlen
		.awsize                 (sdram_axi4_slave_agent_altera_axi_master_awsize),         //  output,    width = 3,                  .awsize
		.awburst                (sdram_axi4_slave_agent_altera_axi_master_awburst),        //  output,    width = 2,                  .awburst
		.awlock                 (sdram_axi4_slave_agent_altera_axi_master_awlock),         //  output,    width = 1,                  .awlock
		.awcache                (sdram_axi4_slave_agent_altera_axi_master_awcache),        //  output,    width = 4,                  .awcache
		.awprot                 (sdram_axi4_slave_agent_altera_axi_master_awprot),         //  output,    width = 3,                  .awprot
		.awuser                 (sdram_axi4_slave_agent_altera_axi_master_awuser),         //  output,    width = 1,                  .awuser
		.awvalid                (sdram_axi4_slave_agent_altera_axi_master_awvalid),        //  output,    width = 1,                  .awvalid
		.awready                (sdram_axi4_slave_agent_altera_axi_master_awready),        //   input,    width = 1,                  .awready
		.wdata                  (sdram_axi4_slave_agent_altera_axi_master_wdata),          //  output,   width = 64,                  .wdata
		.wstrb                  (sdram_axi4_slave_agent_altera_axi_master_wstrb),          //  output,    width = 8,                  .wstrb
		.wlast                  (sdram_axi4_slave_agent_altera_axi_master_wlast),          //  output,    width = 1,                  .wlast
		.wvalid                 (sdram_axi4_slave_agent_altera_axi_master_wvalid),         //  output,    width = 1,                  .wvalid
		.wready                 (sdram_axi4_slave_agent_altera_axi_master_wready),         //   input,    width = 1,                  .wready
		.bid                    (sdram_axi4_slave_agent_altera_axi_master_bid),            //   input,    width = 1,                  .bid
		.bresp                  (sdram_axi4_slave_agent_altera_axi_master_bresp),          //   input,    width = 2,                  .bresp
		.bvalid                 (sdram_axi4_slave_agent_altera_axi_master_bvalid),         //   input,    width = 1,                  .bvalid
		.bready                 (sdram_axi4_slave_agent_altera_axi_master_bready),         //  output,    width = 1,                  .bready
		.arid                   (sdram_axi4_slave_agent_altera_axi_master_arid),           //  output,    width = 1,                  .arid
		.araddr                 (sdram_axi4_slave_agent_altera_axi_master_araddr),         //  output,   width = 32,                  .araddr
		.arlen                  (sdram_axi4_slave_agent_altera_axi_master_arlen),          //  output,    width = 8,                  .arlen
		.arsize                 (sdram_axi4_slave_agent_altera_axi_master_arsize),         //  output,    width = 3,                  .arsize
		.arburst                (sdram_axi4_slave_agent_altera_axi_master_arburst),        //  output,    width = 2,                  .arburst
		.arlock                 (sdram_axi4_slave_agent_altera_axi_master_arlock),         //  output,    width = 1,                  .arlock
		.arcache                (sdram_axi4_slave_agent_altera_axi_master_arcache),        //  output,    width = 4,                  .arcache
		.arprot                 (sdram_axi4_slave_agent_altera_axi_master_arprot),         //  output,    width = 3,                  .arprot
		.aruser                 (sdram_axi4_slave_agent_altera_axi_master_aruser),         //  output,    width = 1,                  .aruser
		.arvalid                (sdram_axi4_slave_agent_altera_axi_master_arvalid),        //  output,    width = 1,                  .arvalid
		.arready                (sdram_axi4_slave_agent_altera_axi_master_arready),        //   input,    width = 1,                  .arready
		.rid                    (sdram_axi4_slave_agent_altera_axi_master_rid),            //   input,    width = 1,                  .rid
		.rdata                  (sdram_axi4_slave_agent_altera_axi_master_rdata),          //   input,   width = 64,                  .rdata
		.rresp                  (sdram_axi4_slave_agent_altera_axi_master_rresp),          //   input,    width = 2,                  .rresp
		.rlast                  (sdram_axi4_slave_agent_altera_axi_master_rlast),          //   input,    width = 1,                  .rlast
		.rvalid                 (sdram_axi4_slave_agent_altera_axi_master_rvalid),         //   input,    width = 1,                  .rvalid
		.rready                 (sdram_axi4_slave_agent_altera_axi_master_rready),         //  output,    width = 1,                  .rready
		.wuser                  (sdram_axi4_slave_agent_altera_axi_master_wuser),          //  output,    width = 1,                  .wuser
		.awqos                  (sdram_axi4_slave_agent_altera_axi_master_awqos),          //  output,    width = 4,                  .awqos
		.awregion               (sdram_axi4_slave_agent_altera_axi_master_awregion),       //  output,    width = 4,                  .awregion
		.ruser                  (sdram_axi4_slave_agent_altera_axi_master_ruser),          //   input,    width = 1,                  .ruser
		.buser                  (sdram_axi4_slave_agent_altera_axi_master_buser),          //   input,    width = 1,                  .buser
		.arqos                  (sdram_axi4_slave_agent_altera_axi_master_arqos),          //  output,    width = 4,                  .arqos
		.arregion               (sdram_axi4_slave_agent_altera_axi_master_arregion),       //  output,    width = 4,                  .arregion
		.awuser_addrchk         (),                                                        // (terminated),                                 
		.awuser_sai             (),                                                        // (terminated),                                 
		.wuser_datachk          (),                                                        // (terminated),                                 
		.wuser_data             (),                                                        // (terminated),                                 
		.wuser_poison           (),                                                        // (terminated),                                 
		.aruser_addrchk         (),                                                        // (terminated),                                 
		.aruser_sai             (),                                                        // (terminated),                                 
		.ruser_datachk          (8'b00000000),                                             // (terminated),                                 
		.ruser_data             (1'b0),                                                    // (terminated),                                 
		.ruser_poison           (1'b0),                                                    // (terminated),                                 
		.awakeup                (),                                                        // (terminated),                                 
		.awtrace                (),                                                        // (terminated),                                 
		.artrace                (),                                                        // (terminated),                                 
		.wpoison                (),                                                        // (terminated),                                 
		.wdatachk               (),                                                        // (terminated),                                 
		.wtrace                 (),                                                        // (terminated),                                 
		.btrace                 (1'b0),                                                    // (terminated),                                 
		.rpoison                (1'b0),                                                    // (terminated),                                 
		.rdatachk               (8'b00000000),                                             // (terminated),                                 
		.rtrace                 (1'b0),                                                    // (terminated),                                 
		.wid                    (),                                                        // (terminated),                                 
		.arsnoop                (),                                                        // (terminated),                                 
		.ardomain               (),                                                        // (terminated),                                 
		.arbar                  (),                                                        // (terminated),                                 
		.awsnoop                (),                                                        // (terminated),                                 
		.awdomain               (),                                                        // (terminated),                                 
		.awbar                  (),                                                        // (terminated),                                 
		.awunique               ()                                                         // (terminated),                                 
	);

	nios_system_altera_merlin_router_1921_pifiqoa router (
		.sink_ready         (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_data),          //   input,  width = 400,          .data
		.sink_startofpacket (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                        //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),      //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                         //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                          //  output,  width = 400,          .data
		.src_channel        (router_src_channel),                                       //  output,    width = 2,          .channel
		.src_startofpacket  (router_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                    //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_isl3fli router_001 (
		.sink_ready         (sdram_axi4_slave_agent_write_rp_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (sdram_axi4_slave_agent_write_rp_valid),               //   input,    width = 1,          .valid
		.sink_data          (sdram_axi4_slave_agent_write_rp_data),                //   input,  width = 184,          .data
		.sink_startofpacket (sdram_axi4_slave_agent_write_rp_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sdram_axi4_slave_agent_write_rp_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                 //  output,  width = 184,          .data
		.src_channel        (router_001_src_channel),                              //  output,    width = 2,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_isl3fli router_002 (
		.sink_ready         (sdram_axi4_slave_agent_read_rp_ready),                //  output,    width = 1,      sink.ready
		.sink_valid         (sdram_axi4_slave_agent_read_rp_valid),                //   input,    width = 1,          .valid
		.sink_data          (sdram_axi4_slave_agent_read_rp_data),                 //   input,  width = 184,          .data
		.sink_startofpacket (sdram_axi4_slave_agent_read_rp_startofpacket),        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sdram_axi4_slave_agent_read_rp_endofpacket),          //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                 //  output,  width = 184,          .data
		.src_channel        (router_002_src_channel),                              //  output,    width = 2,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_traffic_limiter_1921_p3fvlba #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (359),
		.PKT_DEST_ID_L                        (359),
		.PKT_SRC_ID_H                         (358),
		.PKT_SRC_ID_L                         (358),
		.PKT_BYTE_CNT_H                       (337),
		.PKT_BYTE_CNT_L                       (326),
		.PKT_BYTEEN_H                         (287),
		.PKT_BYTEEN_L                         (256),
		.PKT_TRANS_POSTED                     (321),
		.PKT_TRANS_WRITE                      (322),
		.PKT_TRANS_SEQ_H                      (396),
		.PKT_TRANS_SEQ_L                      (390),
		.MAX_OUTSTANDING_RESPONSES            (2),
		.PIPELINED                            (0),
		.ST_DATA_W                            (400),
		.ST_CHANNEL_W                         (2),
		.VALID_WIDTH                          (2),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (1),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) intel_vvp_vfr_av_mm_mem_read_host_limiter (
		.clk                    (iopll_outclk0_clk),                                               //   input,    width = 1,       clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                                //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                                //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                                 //   input,  width = 400,          .data
		.cmd_sink_channel       (router_src_channel),                                              //   input,    width = 2,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                        //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                          //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_data),          //  output,  width = 400,          .data
		.cmd_src_channel        (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_channel),       //  output,    width = 2,          .channel
		.cmd_src_startofpacket  (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                               //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                               //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                             //   input,    width = 2,          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                                //   input,  width = 400,          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                       //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                         //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_data),          //  output,  width = 400,          .data
		.rsp_src_channel        (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_channel),       //  output,    width = 2,          .channel
		.rsp_src_startofpacket  (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_valid_data)         //  output,    width = 2, cmd_valid.data
	);

	nios_system_altera_merlin_demultiplexer_1921_3yiqwyq cmd_demux (
		.clk                (iopll_outclk0_clk),                                               //   input,    width = 1,        clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),             //   input,    width = 1,  clk_reset.reset
		.sink_ready         (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_ready),         //  output,    width = 1,       sink.ready
		.sink_channel       (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_channel),       //   input,    width = 2,           .channel
		.sink_data          (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_data),          //   input,  width = 400,           .data
		.sink_startofpacket (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_startofpacket), //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_endofpacket),   //   input,    width = 1,           .endofpacket
		.sink_valid         (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_valid_data),        //   input,    width = 2, sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                            //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                            //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_src0_data),                                             //  output,  width = 400,           .data
		.src0_channel       (cmd_demux_src0_channel),                                          //  output,    width = 2,           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                    //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                      //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                            //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                            //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_src1_data),                                             //  output,  width = 400,           .data
		.src1_channel       (cmd_demux_src1_channel),                                          //  output,    width = 2,           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                    //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                       //  output,    width = 1,           .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_aanjxii cmd_mux (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                   //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                   //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                    //  output,  width = 400,          .data
		.src_channel         (cmd_mux_src_channel),                                 //  output,    width = 2,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                             //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src0_channel),                              //   input,    width = 2,          .channel
		.sink0_data          (cmd_demux_src0_data),                                 //   input,  width = 400,          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket)                           //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_aanjxii cmd_mux_001 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                //  output,  width = 400,          .data
		.src_channel         (cmd_mux_001_src_channel),                             //  output,    width = 2,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                                //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                                //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src1_channel),                              //   input,    width = 2,          .channel
		.sink0_data          (cmd_demux_src1_data),                                 //   input,  width = 400,          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket)                           //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_emdldva rsp_demux (
		.clk                (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.sink_ready         (sdram_axi4_slave_wr_rsp_width_adapter_src_ready),         //  output,    width = 1,      sink.ready
		.sink_channel       (sdram_axi4_slave_wr_rsp_width_adapter_src_channel),       //   input,    width = 2,          .channel
		.sink_data          (sdram_axi4_slave_wr_rsp_width_adapter_src_data),          //   input,  width = 400,          .data
		.sink_startofpacket (sdram_axi4_slave_wr_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sdram_axi4_slave_wr_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink_valid         (sdram_axi4_slave_wr_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                     //  output,  width = 400,          .data
		.src0_channel       (rsp_demux_src0_channel),                                  //  output,    width = 2,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                               //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_emdldva rsp_demux_001 (
		.clk                (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.sink_ready         (sdram_axi4_slave_rd_rsp_width_adapter_src_ready),         //  output,    width = 1,      sink.ready
		.sink_channel       (sdram_axi4_slave_rd_rsp_width_adapter_src_channel),       //   input,    width = 2,          .channel
		.sink_data          (sdram_axi4_slave_rd_rsp_width_adapter_src_data),          //   input,  width = 400,          .data
		.sink_startofpacket (sdram_axi4_slave_rd_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sdram_axi4_slave_rd_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink_valid         (sdram_axi4_slave_rd_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                                 //  output,  width = 400,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                              //  output,    width = 2,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_jizzjsa rsp_mux (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                   //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                   //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                    //  output,  width = 400,          .data
		.src_channel         (rsp_mux_src_channel),                                 //  output,    width = 2,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                           //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                             //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_src0_ready),                                //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_src0_valid),                                //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_src0_channel),                              //   input,    width = 2,          .channel
		.sink0_data          (rsp_demux_src0_data),                                 //   input,  width = 400,          .data
		.sink0_startofpacket (rsp_demux_src0_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_src0_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_001_src0_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_001_src0_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_001_src0_channel),                          //   input,    width = 2,          .channel
		.sink1_data          (rsp_demux_001_src0_data),                             //   input,  width = 400,          .data
		.sink1_startofpacket (rsp_demux_001_src0_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_001_src0_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_width_adapter_1950_lginhky #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (337),
		.IN_PKT_BYTE_CNT_L             (326),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_TRANS_WRITE            (322),
		.IN_PKT_BURSTWRAP_H            (345),
		.IN_PKT_BURSTWRAP_L            (338),
		.IN_PKT_BURST_SIZE_H           (348),
		.IN_PKT_BURST_SIZE_L           (346),
		.IN_PKT_RESPONSE_STATUS_H      (369),
		.IN_PKT_RESPONSE_STATUS_L      (368),
		.IN_PKT_TRANS_EXCLUSIVE        (325),
		.IN_PKT_BURST_TYPE_H           (350),
		.IN_PKT_BURST_TYPE_L           (349),
		.IN_PKT_ORI_BURST_SIZE_L       (370),
		.IN_PKT_ORI_BURST_SIZE_H       (372),
		.IN_PKT_POISON_H               (382),
		.IN_PKT_POISON_L               (382),
		.IN_PKT_DATACHK_H              (383),
		.IN_PKT_DATACHK_L              (383),
		.IN_PKT_ADDRCHK_H              (386),
		.IN_PKT_ADDRCHK_L              (385),
		.IN_PKT_SAI_H                  (387),
		.IN_PKT_SAI_L                  (387),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (384),
		.IN_PKT_USER_DATA_L            (384),
		.IN_ST_DATA_W                  (400),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (121),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (153),
		.OUT_PKT_RESPONSE_STATUS_L     (152),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_PKT_ORI_BURST_SIZE_L      (154),
		.OUT_PKT_ORI_BURST_SIZE_H      (156),
		.OUT_PKT_POISON_H              (166),
		.OUT_PKT_POISON_L              (166),
		.OUT_PKT_DATACHK_H             (167),
		.OUT_PKT_DATACHK_L             (167),
		.OUT_PKT_ADDRCHK_H             (170),
		.OUT_PKT_ADDRCHK_L             (169),
		.OUT_PKT_SAI_H                 (171),
		.OUT_PKT_SAI_L                 (171),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (172),
		.OUT_PKT_SOP_OOO               (173),
		.OUT_PKT_USER_DATA_H           (168),
		.OUT_PKT_USER_DATA_L           (168),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (184),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_wr_cmd_width_adapter (
		.clk                  (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                       //   input,    width = 1,      sink.valid
		.in_channel           (cmd_mux_src_channel),                                     //   input,    width = 2,          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                               //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                       //  output,    width = 1,          .ready
		.in_data              (cmd_mux_src_data),                                        //   input,  width = 400,          .data
		.out_endofpacket      (sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_wr_cmd_width_adapter_src_data),          //  output,  width = 184,          .data
		.out_channel          (sdram_axi4_slave_wr_cmd_width_adapter_src_channel),       //  output,    width = 2,          .channel
		.out_valid            (sdram_axi4_slave_wr_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_wr_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                   // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_lginhky #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (337),
		.IN_PKT_BYTE_CNT_L             (326),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_TRANS_WRITE            (322),
		.IN_PKT_BURSTWRAP_H            (345),
		.IN_PKT_BURSTWRAP_L            (338),
		.IN_PKT_BURST_SIZE_H           (348),
		.IN_PKT_BURST_SIZE_L           (346),
		.IN_PKT_RESPONSE_STATUS_H      (369),
		.IN_PKT_RESPONSE_STATUS_L      (368),
		.IN_PKT_TRANS_EXCLUSIVE        (325),
		.IN_PKT_BURST_TYPE_H           (350),
		.IN_PKT_BURST_TYPE_L           (349),
		.IN_PKT_ORI_BURST_SIZE_L       (370),
		.IN_PKT_ORI_BURST_SIZE_H       (372),
		.IN_PKT_POISON_H               (382),
		.IN_PKT_POISON_L               (382),
		.IN_PKT_DATACHK_H              (383),
		.IN_PKT_DATACHK_L              (383),
		.IN_PKT_ADDRCHK_H              (386),
		.IN_PKT_ADDRCHK_L              (385),
		.IN_PKT_SAI_H                  (387),
		.IN_PKT_SAI_L                  (387),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (384),
		.IN_PKT_USER_DATA_L            (384),
		.IN_ST_DATA_W                  (400),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (121),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (132),
		.OUT_PKT_BURST_SIZE_L          (130),
		.OUT_PKT_RESPONSE_STATUS_H     (153),
		.OUT_PKT_RESPONSE_STATUS_L     (152),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (134),
		.OUT_PKT_BURST_TYPE_L          (133),
		.OUT_PKT_ORI_BURST_SIZE_L      (154),
		.OUT_PKT_ORI_BURST_SIZE_H      (156),
		.OUT_PKT_POISON_H              (166),
		.OUT_PKT_POISON_L              (166),
		.OUT_PKT_DATACHK_H             (167),
		.OUT_PKT_DATACHK_L             (167),
		.OUT_PKT_ADDRCHK_H             (170),
		.OUT_PKT_ADDRCHK_L             (169),
		.OUT_PKT_SAI_H                 (171),
		.OUT_PKT_SAI_L                 (171),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (172),
		.OUT_PKT_SOP_OOO               (173),
		.OUT_PKT_USER_DATA_H           (168),
		.OUT_PKT_USER_DATA_L           (168),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (184),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_rd_cmd_width_adapter (
		.clk                  (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_mux_001_src_valid),                                   //   input,    width = 1,      sink.valid
		.in_channel           (cmd_mux_001_src_channel),                                 //   input,    width = 2,          .channel
		.in_startofpacket     (cmd_mux_001_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_mux_001_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_mux_001_src_ready),                                   //  output,    width = 1,          .ready
		.in_data              (cmd_mux_001_src_data),                                    //   input,  width = 400,          .data
		.out_endofpacket      (sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_rd_cmd_width_adapter_src_data),          //  output,  width = 184,          .data
		.out_channel          (sdram_axi4_slave_rd_cmd_width_adapter_src_channel),       //  output,    width = 2,          .channel
		.out_valid            (sdram_axi4_slave_rd_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_rd_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                   // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_7yy2dry #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (121),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (122),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (153),
		.IN_PKT_RESPONSE_STATUS_L      (152),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_PKT_ORI_BURST_SIZE_L       (154),
		.IN_PKT_ORI_BURST_SIZE_H       (156),
		.IN_PKT_POISON_H               (166),
		.IN_PKT_POISON_L               (166),
		.IN_PKT_DATACHK_H              (167),
		.IN_PKT_DATACHK_L              (167),
		.IN_PKT_ADDRCHK_H              (170),
		.IN_PKT_ADDRCHK_L              (169),
		.IN_PKT_SAI_H                  (171),
		.IN_PKT_SAI_L                  (171),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (168),
		.IN_PKT_USER_DATA_L            (168),
		.IN_ST_DATA_W                  (184),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (337),
		.OUT_PKT_BYTE_CNT_L            (326),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_PKT_BURST_SIZE_H          (348),
		.OUT_PKT_BURST_SIZE_L          (346),
		.OUT_PKT_RESPONSE_STATUS_H     (369),
		.OUT_PKT_RESPONSE_STATUS_L     (368),
		.OUT_PKT_TRANS_EXCLUSIVE       (325),
		.OUT_PKT_BURST_TYPE_H          (350),
		.OUT_PKT_BURST_TYPE_L          (349),
		.OUT_PKT_ORI_BURST_SIZE_L      (370),
		.OUT_PKT_ORI_BURST_SIZE_H      (372),
		.OUT_PKT_POISON_H              (382),
		.OUT_PKT_POISON_L              (382),
		.OUT_PKT_DATACHK_H             (383),
		.OUT_PKT_DATACHK_L             (383),
		.OUT_PKT_ADDRCHK_H             (386),
		.OUT_PKT_ADDRCHK_L             (385),
		.OUT_PKT_SAI_H                 (387),
		.OUT_PKT_SAI_L                 (387),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (388),
		.OUT_PKT_SOP_OOO               (389),
		.OUT_PKT_USER_DATA_H           (384),
		.OUT_PKT_USER_DATA_L           (384),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (400),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_wr_rsp_width_adapter (
		.clk                  (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.in_valid             (router_001_src_valid),                                    //   input,    width = 1,      sink.valid
		.in_channel           (router_001_src_channel),                                  //   input,    width = 2,          .channel
		.in_startofpacket     (router_001_src_startofpacket),                            //   input,    width = 1,          .startofpacket
		.in_endofpacket       (router_001_src_endofpacket),                              //   input,    width = 1,          .endofpacket
		.in_ready             (router_001_src_ready),                                    //  output,    width = 1,          .ready
		.in_data              (router_001_src_data),                                     //   input,  width = 184,          .data
		.out_endofpacket      (sdram_axi4_slave_wr_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_wr_rsp_width_adapter_src_data),          //  output,  width = 400,          .data
		.out_channel          (sdram_axi4_slave_wr_rsp_width_adapter_src_channel),       //  output,    width = 2,          .channel
		.out_valid            (sdram_axi4_slave_wr_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_wr_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_wr_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                   // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_7yy2dry #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (121),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (129),
		.IN_PKT_BURSTWRAP_L            (122),
		.IN_PKT_BURST_SIZE_H           (132),
		.IN_PKT_BURST_SIZE_L           (130),
		.IN_PKT_RESPONSE_STATUS_H      (153),
		.IN_PKT_RESPONSE_STATUS_L      (152),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (134),
		.IN_PKT_BURST_TYPE_L           (133),
		.IN_PKT_ORI_BURST_SIZE_L       (154),
		.IN_PKT_ORI_BURST_SIZE_H       (156),
		.IN_PKT_POISON_H               (166),
		.IN_PKT_POISON_L               (166),
		.IN_PKT_DATACHK_H              (167),
		.IN_PKT_DATACHK_L              (167),
		.IN_PKT_ADDRCHK_H              (170),
		.IN_PKT_ADDRCHK_L              (169),
		.IN_PKT_SAI_H                  (171),
		.IN_PKT_SAI_L                  (171),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (168),
		.IN_PKT_USER_DATA_L            (168),
		.IN_ST_DATA_W                  (184),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (337),
		.OUT_PKT_BYTE_CNT_L            (326),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_PKT_BURST_SIZE_H          (348),
		.OUT_PKT_BURST_SIZE_L          (346),
		.OUT_PKT_RESPONSE_STATUS_H     (369),
		.OUT_PKT_RESPONSE_STATUS_L     (368),
		.OUT_PKT_TRANS_EXCLUSIVE       (325),
		.OUT_PKT_BURST_TYPE_H          (350),
		.OUT_PKT_BURST_TYPE_L          (349),
		.OUT_PKT_ORI_BURST_SIZE_L      (370),
		.OUT_PKT_ORI_BURST_SIZE_H      (372),
		.OUT_PKT_POISON_H              (382),
		.OUT_PKT_POISON_L              (382),
		.OUT_PKT_DATACHK_H             (383),
		.OUT_PKT_DATACHK_L             (383),
		.OUT_PKT_ADDRCHK_H             (386),
		.OUT_PKT_ADDRCHK_L             (385),
		.OUT_PKT_SAI_H                 (387),
		.OUT_PKT_SAI_L                 (387),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (388),
		.OUT_PKT_SOP_OOO               (389),
		.OUT_PKT_USER_DATA_H           (384),
		.OUT_PKT_USER_DATA_L           (384),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (400),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_rd_rsp_width_adapter (
		.clk                  (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.in_valid             (router_002_src_valid),                                    //   input,    width = 1,      sink.valid
		.in_channel           (router_002_src_channel),                                  //   input,    width = 2,          .channel
		.in_startofpacket     (router_002_src_startofpacket),                            //   input,    width = 1,          .startofpacket
		.in_endofpacket       (router_002_src_endofpacket),                              //   input,    width = 1,          .endofpacket
		.in_ready             (router_002_src_ready),                                    //  output,    width = 1,          .ready
		.in_data              (router_002_src_data),                                     //   input,  width = 184,          .data
		.out_endofpacket      (sdram_axi4_slave_rd_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_rd_rsp_width_adapter_src_data),          //  output,  width = 400,          .data
		.out_channel          (sdram_axi4_slave_rd_rsp_width_adapter_src_channel),       //  output,    width = 2,          .channel
		.out_valid            (sdram_axi4_slave_rd_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_rd_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_rd_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                   // (terminated),                         
	);

endmodule
