// system_intel_niosv_m_0_intel_niosv_m_2600_6xl5jua.v

// This file was auto-generated from intel_niosv_m_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module system_intel_niosv_m_0_intel_niosv_m_2600_6xl5jua (
		input  wire        clk,                          //                 clk.clk,           Clock Input
		input  wire        reset_reset,                  //               reset.reset,         Reset Input
		input  wire [15:0] platform_irq_rx_irq,          //     platform_irq_rx.irq,           Level-sensitive interrupt request lines.
		output wire [31:0] instruction_manager_awaddr,   // instruction_manager.awaddr,        Write Address Channel -- Write Address. This is unused.
		output wire [2:0]  instruction_manager_awprot,   //                    .awprot,        Write Address Channel -- Protection Type. This is unused.
		output wire        instruction_manager_awvalid,  //                    .awvalid,       Write Address Channel -- Write Address Valid. This is unused.
		input  wire        instruction_manager_awready,  //                    .awready,       Write Address Channel -- Write Address Ready. This is unused.
		output wire [31:0] instruction_manager_wdata,    //                    .wdata,         Write Data Channel -- Write Data. This is unused.
		output wire [3:0]  instruction_manager_wstrb,    //                    .wstrb,         Write Data Channel -- Write Strobes. This is unused.
		output wire        instruction_manager_wvalid,   //                    .wvalid,        Write Data Channel -- Write Valid. This is unused.
		input  wire        instruction_manager_wready,   //                    .wready,        Write Data Channel -- Write Ready. This is unused.
		input  wire [1:0]  instruction_manager_bresp,    //                    .bresp,         Write Response Channel -- Write Response. This is unused.
		input  wire        instruction_manager_bvalid,   //                    .bvalid,        Write Response Channel -- Write Response Valid. This is unused.
		output wire        instruction_manager_bready,   //                    .bready,        Write Response Channel -- Write Response Ready. This is unused.
		output wire [31:0] instruction_manager_araddr,   //                    .araddr,        Read Address Channel -- Read Address. Instruction address (program counter).
		output wire [2:0]  instruction_manager_arprot,   //                    .arprot,        Read Address Channel -- Protection Type. This is unused.
		output wire        instruction_manager_arvalid,  //                    .arvalid,       Read Address Channel -- Read Address Valid. Instruction address valid.
		input  wire        instruction_manager_arready,  //                    .arready,       Read Address Channel -- Read Address Ready. Instruction address ready (from memory).
		input  wire [31:0] instruction_manager_rdata,    //                    .rdata,         Read Data Channel -- Read Data. Instruction word.
		input  wire [1:0]  instruction_manager_rresp,    //                    .rresp,         Read Data Channel -- Read Response. Instruction response. A non-zero value indicates an instruction access fault exception.
		input  wire        instruction_manager_rvalid,   //                    .rvalid,        Read Data Channel -- Read Valid. Instruction valid.
		output wire        instruction_manager_rready,   //                    .rready,        Read Data Channel -- Read Ready. This is tied high since the core is always ready to receive an instruction.
		output wire [31:0] data_manager_awaddr,          //        data_manager.awaddr,        Write Address Channel -- Write Address. Store address.
		output wire [2:0]  data_manager_awprot,          //                    .awprot,        Write Address Channel -- Protection Type. This is unused.
		output wire        data_manager_awvalid,         //                    .awvalid,       Write Address Channel -- Write Address Valid. Store address valid.
		input  wire        data_manager_awready,         //                    .awready,       Write Address Channel -- Write Address Ready. Store address ready (from memory).
		output wire [31:0] data_manager_wdata,           //                    .wdata,         Write Data Channel -- Write Data. Store data.
		output wire [3:0]  data_manager_wstrb,           //                    .wstrb,         Write Data Channel -- Write Strobes. Byte position in word.
		output wire        data_manager_wvalid,          //                    .wvalid,        Write Data Channel -- Write Valid. Store data valid.
		input  wire        data_manager_wready,          //                    .wready,        Write Data Channel -- Write Ready. Store data ready (from memory).
		input  wire [1:0]  data_manager_bresp,           //                    .bresp,         Write Response Channel -- Write Response. Store response. A non-zero value indicates a store access fault exception.
		input  wire        data_manager_bvalid,          //                    .bvalid,        Write Response Channel -- Write Response Valid. Store response valid.
		output wire        data_manager_bready,          //                    .bready,        Write Response Channel -- Write Response Ready. This is tied high since the core is always ready to receive a store response.
		output wire [31:0] data_manager_araddr,          //                    .araddr,        Read Address Channel -- Read Address. Load address.
		output wire [2:0]  data_manager_arprot,          //                    .arprot,        Read Address Channel -- Protection Type. This is unused.
		output wire        data_manager_arvalid,         //                    .arvalid,       Read Address Channel -- Read Address Valid. Load address valid.
		input  wire        data_manager_arready,         //                    .arready,       Read Address Channel -- Read Address Ready. Load address ready (from agents).
		input  wire [31:0] data_manager_rdata,           //                    .rdata,         Read Data Channel -- Read Data. Load data.
		input  wire [1:0]  data_manager_rresp,           //                    .rresp,         Read Data Channel -- Read Response. Load response. A non-zero value indicates a load access fault exception.
		input  wire        data_manager_rvalid,          //                    .rvalid,        Read Data Channel -- Read Valid. Load data valid.
		output wire        data_manager_rready,          //                    .rready,        Read Data Channel -- Read Ready. This is tied high since the core is always ready to receive the load data.
		input  wire [5:0]  timer_sw_agent_address,       //      timer_sw_agent.address,       The address in the Timer and Software Interrupt Module that the core wants to write to or read from. This is relative to the Timer and Software Interrupt Module base address.
		input  wire [3:0]  timer_sw_agent_byteenable,    //                    .byteenable,    Store byte enable.
		input  wire        timer_sw_agent_read,          //                    .read,          Indicates if the core wants to load from "timer_sw_agent_address" in the Timer and Software Interrupt Module.
		output wire [31:0] timer_sw_agent_readdata,      //                    .readdata,      Load data from the Timer and Software Interrupt Module sent to the core.
		input  wire        timer_sw_agent_write,         //                    .write,         Indicates if the core wants to store to "timer_sw_agent_address" in the Timer and Software Interrupt Module.
		input  wire [31:0] timer_sw_agent_writedata,     //                    .writedata,     Store data to the Timer and Software Interrupt Module sent from the core.
		output wire        timer_sw_agent_waitrequest,   //                    .waitrequest,   Timer and Software Interrupt Module not ready to receive write or read request from the core.
		output wire        timer_sw_agent_readdatavalid, //                    .readdatavalid, Load data valid.
		input  wire [15:0] dm_agent_address,             //            dm_agent.address,       The address in the Debug Module that the core wants to write to or read from. This is relative to the Debug Module base address.
		input  wire        dm_agent_read,                //                    .read,          Indicates if the core wants to load from "dm_agent_address" in the Debug Module.
		output wire [31:0] dm_agent_readdata,            //                    .readdata,      Load data from the Debug Module sent to the core.
		input  wire        dm_agent_write,               //                    .write,         Indicates if the core wants to store to "dm_agent_address" in the Debug Module.
		input  wire [31:0] dm_agent_writedata,           //                    .writedata,     Store data to the Debug Module sent from the core.
		output wire        dm_agent_waitrequest,         //                    .waitrequest,   Debug Module not ready to receive write or read request from the core.
		output wire        dm_agent_readdatavalid,       //                    .readdatavalid, Load data valid.
		output wire        dbg_reset_out_reset,          //       dbg_reset_out.reset,         This signal provides a reset originating from the Debug Module. It is triggered by the JTAG debugger or the "niosv-download -r" command. It can be connected to "ndm_reset_in_reset" to reset the core and the Timer and Software Interrupt Module. It can also be connected to the reset inputs of other system components as needed.
		input  wire        ndm_reset_in_reset            //        ndm_reset_in.reset,         Reset Input
	);

	wire    irq_mapper_receiver0_irq;           // dbg_mod:dbg_irq -> irq_mapper:receiver0_irq
	wire    hart_debug_irq_rx_irq;              // irq_mapper:sender_irq -> hart:irq_debug
	wire    irq_mapper_001_receiver0_irq;       // timer_module:timer_irq -> irq_mapper_001:receiver0_irq
	wire    hart_timer_irq_rx_irq;              // irq_mapper_001:sender_irq -> hart:irq_timer
	wire    irq_mapper_002_receiver0_irq;       // timer_module:sw_irq -> irq_mapper_002:receiver0_irq
	wire    hart_sw_irq_rx_irq;                 // irq_mapper_002:sender_irq -> hart:irq_sw
	wire    rst_controller_reset_out_reset;     // rst_controller:reset_out -> hart:reset
	wire    rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [irq_mapper:reset, irq_mapper_001:reset, irq_mapper_002:reset, timer_module:reset]

	system_intel_niosv_m_0_intel_niosv_m_unit_2600_esx7cqy #(
		.RESET_VECTOR    (32'b00000000000000000000000000000000),
		.DBG_EXPN_VECTOR (32'b00000000000010000000000000000000),
		.HARTID          (32'b00000000000000000000000000000000),
		.CORE_EXTN       (256),
		.DEBUG_ENABLED   (1),
		.DEVICE_FAMILY   ("Agilex 3"),
		.USE_RESET_REQ   (0),
		.ECC_EN          (0),
		.SMALL_CORE      (0)
	) hart (
		.clk             (clk),                            //   input,   width = 1,             cpu_clk.clk
		.reset           (rst_controller_reset_out_reset), //   input,   width = 1,           cpu_reset.reset
		.irq_plat_vec    (platform_irq_rx_irq),            //   input,  width = 16,     platform_irq_rx.irq
		.irq_debug       (hart_debug_irq_rx_irq),          //   input,   width = 1,        debug_irq_rx.irq
		.irq_timer       (hart_timer_irq_rx_irq),          //   input,   width = 1,        timer_irq_rx.irq
		.irq_sw          (hart_sw_irq_rx_irq),             //   input,   width = 1,           sw_irq_rx.irq
		.instr_awaddr    (instruction_manager_awaddr),     //  output,  width = 32, instruction_manager.awaddr
		.instr_awprot    (instruction_manager_awprot),     //  output,   width = 3,                    .awprot
		.instr_awvalid   (instruction_manager_awvalid),    //  output,   width = 1,                    .awvalid
		.instr_awready   (instruction_manager_awready),    //   input,   width = 1,                    .awready
		.instr_wdata     (instruction_manager_wdata),      //  output,  width = 32,                    .wdata
		.instr_wstrb     (instruction_manager_wstrb),      //  output,   width = 4,                    .wstrb
		.instr_wvalid    (instruction_manager_wvalid),     //  output,   width = 1,                    .wvalid
		.instr_wready    (instruction_manager_wready),     //   input,   width = 1,                    .wready
		.instr_bresp     (instruction_manager_bresp),      //   input,   width = 2,                    .bresp
		.instr_bvalid    (instruction_manager_bvalid),     //   input,   width = 1,                    .bvalid
		.instr_bready    (instruction_manager_bready),     //  output,   width = 1,                    .bready
		.instr_araddr    (instruction_manager_araddr),     //  output,  width = 32,                    .araddr
		.instr_arprot    (instruction_manager_arprot),     //  output,   width = 3,                    .arprot
		.instr_arvalid   (instruction_manager_arvalid),    //  output,   width = 1,                    .arvalid
		.instr_arready   (instruction_manager_arready),    //   input,   width = 1,                    .arready
		.instr_rdata     (instruction_manager_rdata),      //   input,  width = 32,                    .rdata
		.instr_rresp     (instruction_manager_rresp),      //   input,   width = 2,                    .rresp
		.instr_rvalid    (instruction_manager_rvalid),     //   input,   width = 1,                    .rvalid
		.instr_rready    (instruction_manager_rready),     //  output,   width = 1,                    .rready
		.data_awaddr     (data_manager_awaddr),            //  output,  width = 32,        data_manager.awaddr
		.data_awprot     (data_manager_awprot),            //  output,   width = 3,                    .awprot
		.data_awvalid    (data_manager_awvalid),           //  output,   width = 1,                    .awvalid
		.data_awready    (data_manager_awready),           //   input,   width = 1,                    .awready
		.data_wdata      (data_manager_wdata),             //  output,  width = 32,                    .wdata
		.data_wstrb      (data_manager_wstrb),             //  output,   width = 4,                    .wstrb
		.data_wvalid     (data_manager_wvalid),            //  output,   width = 1,                    .wvalid
		.data_wready     (data_manager_wready),            //   input,   width = 1,                    .wready
		.data_bresp      (data_manager_bresp),             //   input,   width = 2,                    .bresp
		.data_bvalid     (data_manager_bvalid),            //   input,   width = 1,                    .bvalid
		.data_bready     (data_manager_bready),            //  output,   width = 1,                    .bready
		.data_araddr     (data_manager_araddr),            //  output,  width = 32,                    .araddr
		.data_arprot     (data_manager_arprot),            //  output,   width = 3,                    .arprot
		.data_arvalid    (data_manager_arvalid),           //  output,   width = 1,                    .arvalid
		.data_arready    (data_manager_arready),           //   input,   width = 1,                    .arready
		.data_rdata      (data_manager_rdata),             //   input,  width = 32,                    .rdata
		.data_rresp      (data_manager_rresp),             //   input,   width = 2,                    .rresp
		.data_rvalid     (data_manager_rvalid),            //   input,   width = 1,                    .rvalid
		.data_rready     (data_manager_rready),            //  output,   width = 1,                    .rready
		.reset_req       (1'b0),                           // (terminated),                                  
		.reset_req_ack   (),                               // (terminated),                                  
		.core_ecc_status (),                               // (terminated),                                  
		.core_ecc_src    (),                               // (terminated),                                  
		.instr_awsize    (),                               // (terminated),                                  
		.instr_wlast     (),                               // (terminated),                                  
		.instr_arsize    (),                               // (terminated),                                  
		.data_awsize     (),                               // (terminated),                                  
		.data_wlast      (),                               // (terminated),                                  
		.data_arsize     (),                               // (terminated),                                  
		.irq_ext         (1'b0)                            // (terminated),                                  
	);

	niosv_timer_msip #(
		.IRQ_EN     (1),
		.HARTID     (0),
		.ADDR_WIDTH (6)
	) timer_module (
		.clk                (clk),                                //   input,   width = 1,            clk.clk
		.reset              (rst_controller_001_reset_out_reset), //   input,   width = 1,          reset.reset
		.hart_address       (timer_sw_agent_address),             //   input,   width = 6, timer_sw_agent.address
		.hart_byteen        (timer_sw_agent_byteenable),          //   input,   width = 4,               .byteenable
		.hart_read          (timer_sw_agent_read),                //   input,   width = 1,               .read
		.hart_readdata      (timer_sw_agent_readdata),            //  output,  width = 32,               .readdata
		.hart_write         (timer_sw_agent_write),               //   input,   width = 1,               .write
		.hart_writedata     (timer_sw_agent_writedata),           //   input,  width = 32,               .writedata
		.hart_waitrequest   (timer_sw_agent_waitrequest),         //  output,   width = 1,               .waitrequest
		.hart_readdatavalid (timer_sw_agent_readdatavalid),       //  output,   width = 1,               .readdatavalid
		.timer_irq          (irq_mapper_001_receiver0_irq),       //  output,   width = 1,      timer_irq.irq
		.sw_irq             (irq_mapper_002_receiver0_irq)        //  output,   width = 1,         sw_irq.irq
	);

	niosv_dm_top #(
		.DEBUG_RESET_EN (1),
		.FPU_EN         (0),
		.DEVICE_FAMILY  ("Agilex 3")
	) dbg_mod (
		.clk                (clk),                      //   input,   width = 1,           clk.clk
		.reset              (reset_reset),              //   input,   width = 1,         reset.reset
		.hart_address       (dm_agent_address),         //   input,  width = 16,      dm_agent.address
		.hart_read          (dm_agent_read),            //   input,   width = 1,              .read
		.hart_readdata      (dm_agent_readdata),        //  output,  width = 32,              .readdata
		.hart_write         (dm_agent_write),           //   input,   width = 1,              .write
		.hart_writedata     (dm_agent_writedata),       //   input,  width = 32,              .writedata
		.hart_waitrequest   (dm_agent_waitrequest),     //  output,   width = 1,              .waitrequest
		.hart_readdatavalid (dm_agent_readdatavalid),   //  output,   width = 1,              .readdatavalid
		.dbg_irq            (irq_mapper_receiver0_irq), //  output,   width = 1,       dbg_irq.irq
		.dbg_reset          (dbg_reset_out_reset)       //  output,   width = 1, dbg_reset_out.reset
	);

	system_intel_niosv_m_0_altera_irq_mapper_2001_wgtbcyy irq_mapper (
		.clk           (clk),                                //   input,  width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,  width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),           //   input,  width = 1, receiver0.irq
		.sender_irq    (hart_debug_irq_rx_irq)               //  output,  width = 1,    sender.irq
	);

	system_intel_niosv_m_0_altera_irq_mapper_2001_wgtbcyy irq_mapper_001 (
		.clk           (clk),                                //   input,  width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,  width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_001_receiver0_irq),       //   input,  width = 1, receiver0.irq
		.sender_irq    (hart_timer_irq_rx_irq)               //  output,  width = 1,    sender.irq
	);

	system_intel_niosv_m_0_altera_irq_mapper_2001_wgtbcyy irq_mapper_002 (
		.clk           (clk),                                //   input,  width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,  width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_002_receiver0_irq),       //   input,  width = 1, receiver0.irq
		.sender_irq    (hart_sw_irq_rx_irq)                  //  output,  width = 1,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("none"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (reset_reset),                    //   input,  width = 1, reset_in0.reset
		.reset_in1      (ndm_reset_in_reset),             //   input,  width = 1, reset_in1.reset
		.clk            (),                               //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                               // (terminated),                       
		.reset_req_in0  (1'b0),                           // (terminated),                       
		.reset_req_in1  (1'b0),                           // (terminated),                       
		.reset_in2      (1'b0),                           // (terminated),                       
		.reset_req_in2  (1'b0),                           // (terminated),                       
		.reset_in3      (1'b0),                           // (terminated),                       
		.reset_req_in3  (1'b0),                           // (terminated),                       
		.reset_in4      (1'b0),                           // (terminated),                       
		.reset_req_in4  (1'b0),                           // (terminated),                       
		.reset_in5      (1'b0),                           // (terminated),                       
		.reset_req_in5  (1'b0),                           // (terminated),                       
		.reset_in6      (1'b0),                           // (terminated),                       
		.reset_req_in6  (1'b0),                           // (terminated),                       
		.reset_in7      (1'b0),                           // (terminated),                       
		.reset_req_in7  (1'b0),                           // (terminated),                       
		.reset_in8      (1'b0),                           // (terminated),                       
		.reset_req_in8  (1'b0),                           // (terminated),                       
		.reset_in9      (1'b0),                           // (terminated),                       
		.reset_req_in9  (1'b0),                           // (terminated),                       
		.reset_in10     (1'b0),                           // (terminated),                       
		.reset_req_in10 (1'b0),                           // (terminated),                       
		.reset_in11     (1'b0),                           // (terminated),                       
		.reset_req_in11 (1'b0),                           // (terminated),                       
		.reset_in12     (1'b0),                           // (terminated),                       
		.reset_req_in12 (1'b0),                           // (terminated),                       
		.reset_in13     (1'b0),                           // (terminated),                       
		.reset_req_in13 (1'b0),                           // (terminated),                       
		.reset_in14     (1'b0),                           // (terminated),                       
		.reset_req_in14 (1'b0),                           // (terminated),                       
		.reset_in15     (1'b0),                           // (terminated),                       
		.reset_req_in15 (1'b0)                            // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (reset_reset),                        //   input,  width = 1, reset_in0.reset
		.reset_in1      (ndm_reset_in_reset),                 //   input,  width = 1, reset_in1.reset
		.clk            (clk),                                //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
