	component nios_system_intel_vvp_fr2cv_0 is
		port (
			cv_clk_out_clk           : out std_logic;                                        -- clk
			cv_vid_out_vid_data      : out std_logic_vector(23 downto 0);                    -- vid_data
			cv_vid_out_underflow     : out std_logic;                                        -- underflow
			cv_vid_out_vid_datavalid : out std_logic;                                        -- vid_datavalid
			cv_vid_out_vid_v_sync    : out std_logic;                                        -- vid_v_sync
			cv_vid_out_vid_h_sync    : out std_logic;                                        -- vid_h_sync
			cv_vid_out_vid_f         : out std_logic;                                        -- vid_f
			cv_vid_out_vid_h         : out std_logic;                                        -- vid_h
			cv_vid_out_vid_v         : out std_logic;                                        -- vid_v
			axi4s_fr_vid_in_tdata    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- tdata
			axi4s_fr_vid_in_tvalid   : in  std_logic                     := 'X';             -- tvalid
			axi4s_fr_vid_in_tready   : out std_logic;                                        -- tready
			axi4s_fr_vid_in_tlast    : in  std_logic                     := 'X';             -- tlast
			axi4s_fr_vid_in_tuser    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- tuser
			vid_clock_clk            : in  std_logic                     := 'X';             -- clk
			vid_reset_reset          : in  std_logic                     := 'X'              -- reset
		);
	end component nios_system_intel_vvp_fr2cv_0;

	u0 : component nios_system_intel_vvp_fr2cv_0
		port map (
			cv_clk_out_clk           => CONNECTED_TO_cv_clk_out_clk,           --      cv_clk_out.clk
			cv_vid_out_vid_data      => CONNECTED_TO_cv_vid_out_vid_data,      --      cv_vid_out.vid_data
			cv_vid_out_underflow     => CONNECTED_TO_cv_vid_out_underflow,     --                .underflow
			cv_vid_out_vid_datavalid => CONNECTED_TO_cv_vid_out_vid_datavalid, --                .vid_datavalid
			cv_vid_out_vid_v_sync    => CONNECTED_TO_cv_vid_out_vid_v_sync,    --                .vid_v_sync
			cv_vid_out_vid_h_sync    => CONNECTED_TO_cv_vid_out_vid_h_sync,    --                .vid_h_sync
			cv_vid_out_vid_f         => CONNECTED_TO_cv_vid_out_vid_f,         --                .vid_f
			cv_vid_out_vid_h         => CONNECTED_TO_cv_vid_out_vid_h,         --                .vid_h
			cv_vid_out_vid_v         => CONNECTED_TO_cv_vid_out_vid_v,         --                .vid_v
			axi4s_fr_vid_in_tdata    => CONNECTED_TO_axi4s_fr_vid_in_tdata,    -- axi4s_fr_vid_in.tdata
			axi4s_fr_vid_in_tvalid   => CONNECTED_TO_axi4s_fr_vid_in_tvalid,   --                .tvalid
			axi4s_fr_vid_in_tready   => CONNECTED_TO_axi4s_fr_vid_in_tready,   --                .tready
			axi4s_fr_vid_in_tlast    => CONNECTED_TO_axi4s_fr_vid_in_tlast,    --                .tlast
			axi4s_fr_vid_in_tuser    => CONNECTED_TO_axi4s_fr_vid_in_tuser,    --                .tuser
			vid_clock_clk            => CONNECTED_TO_vid_clock_clk,            --       vid_clock.clk
			vid_reset_reset          => CONNECTED_TO_vid_reset_reset           --       vid_reset.reset
		);

