// nios_system_intel_vvp_scaler_1_intel_vvp_scaler_2450_wy6nz6i.v

// This file was auto-generated from intel_vvp_scaler_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_scaler_1_intel_vvp_scaler_2450_wy6nz6i (
		input  wire        main_clock_clk,       //    main_clock.clk,   Clock Input
		input  wire        main_reset_reset,     //    main_reset.reset
		input  wire [23:0] axi4s_vid_in_tdata,   //  axi4s_vid_in.tdata
		input  wire        axi4s_vid_in_tvalid,  //              .tvalid
		output wire        axi4s_vid_in_tready,  //              .tready
		input  wire        axi4s_vid_in_tlast,   //              .tlast
		input  wire [2:0]  axi4s_vid_in_tuser,   //              .tuser
		output wire [23:0] axi4s_vid_out_tdata,  // axi4s_vid_out.tdata
		output wire        axi4s_vid_out_tvalid, //              .tvalid
		input  wire        axi4s_vid_out_tready, //              .tready
		output wire        axi4s_vid_out_tlast,  //              .tlast
		output wire [2:0]  axi4s_vid_out_tuser   //              .tuser
	);

	wire          main_rst_bridge_out_reset_reset;    // main_rst_bridge:out_rst -> [h_algo_comp:main_reset_reset, in_bridge:rst, line_buffer:rst, out_bridge:rst, scheduler:rst, v_algo_comp:rst, v_round_sat:rst]
	wire          in_bridge_axi_st_data_out_tvalid;   // in_bridge:axi_st_data_out_tvalid -> line_buffer:axi_st_data_in_tvalid
	wire    [2:0] in_bridge_axi_st_data_out_tuser;    // in_bridge:axi_st_data_out_tuser -> line_buffer:axi_st_data_in_tuser
	wire          in_bridge_axi_st_data_out_tready;   // line_buffer:axi_st_data_in_tready -> in_bridge:axi_st_data_out_tready
	wire   [23:0] in_bridge_axi_st_data_out_tdata;    // in_bridge:axi_st_data_out_tdata -> line_buffer:axi_st_data_in_tdata
	wire          in_bridge_axi_st_data_out_tlast;    // in_bridge:axi_st_data_out_tlast -> line_buffer:axi_st_data_in_tlast
	wire          in_bridge_axi_st_ctrl_out_tvalid;   // in_bridge:axi_st_ctrl_out_tvalid -> scheduler:axi_st_ctrl_in_tvalid
	wire    [1:0] in_bridge_axi_st_ctrl_out_tuser;    // in_bridge:axi_st_ctrl_out_tuser -> scheduler:axi_st_ctrl_in_tuser
	wire          in_bridge_axi_st_ctrl_out_tready;   // scheduler:axi_st_ctrl_in_tready -> in_bridge:axi_st_ctrl_out_tready
	wire   [15:0] in_bridge_axi_st_ctrl_out_tdata;    // in_bridge:axi_st_ctrl_out_tdata -> scheduler:axi_st_ctrl_in_tdata
	wire          in_bridge_axi_st_ctrl_out_tlast;    // in_bridge:axi_st_ctrl_out_tlast -> scheduler:axi_st_ctrl_in_tlast
	wire          scheduler_axi_st_ctrl_out_tvalid;   // scheduler:axi_st_ctrl_out_tvalid -> out_bridge:axi_st_ctrl_in_tvalid
	wire    [1:0] scheduler_axi_st_ctrl_out_tuser;    // scheduler:axi_st_ctrl_out_tuser -> out_bridge:axi_st_ctrl_in_tuser
	wire          scheduler_axi_st_ctrl_out_tready;   // out_bridge:axi_st_ctrl_in_tready -> scheduler:axi_st_ctrl_out_tready
	wire   [15:0] scheduler_axi_st_ctrl_out_tdata;    // scheduler:axi_st_ctrl_out_tdata -> out_bridge:axi_st_ctrl_in_tdata
	wire          scheduler_axi_st_ctrl_out_tlast;    // scheduler:axi_st_ctrl_out_tlast -> out_bridge:axi_st_ctrl_in_tlast
	wire          scheduler_axi_st_lb_cmd_tvalid;     // scheduler:axi_st_lb_cmd_tvalid -> line_buffer:axi_st_cmd_tvalid
	wire          scheduler_axi_st_lb_cmd_tready;     // line_buffer:axi_st_cmd_tready -> scheduler:axi_st_lb_cmd_tready
	wire   [23:0] scheduler_axi_st_lb_cmd_tdata;      // scheduler:axi_st_lb_cmd_tdata -> line_buffer:axi_st_cmd_tdata
	wire          line_buffer_axi_st_data_out_tvalid; // line_buffer:axi_st_data_out_tvalid -> v_algo_comp:axi_st_data_in_tvalid
	wire    [5:0] line_buffer_axi_st_data_out_tuser;  // line_buffer:axi_st_data_out_tuser -> v_algo_comp:axi_st_data_in_tuser
	wire          line_buffer_axi_st_data_out_tready; // v_algo_comp:axi_st_data_in_tready -> line_buffer:axi_st_data_out_tready
	wire   [47:0] line_buffer_axi_st_data_out_tdata;  // line_buffer:axi_st_data_out_tdata -> v_algo_comp:axi_st_data_in_tdata
	wire          line_buffer_axi_st_data_out_tlast;  // line_buffer:axi_st_data_out_tlast -> v_algo_comp:axi_st_data_in_tlast
	wire          v_algo_comp_axi_st_data_out_tvalid; // v_algo_comp:axi_st_data_out_tvalid -> v_round_sat:axi_st_data_in_tvalid
	wire    [5:0] v_algo_comp_axi_st_data_out_tuser;  // v_algo_comp:axi_st_data_out_tuser -> v_round_sat:axi_st_data_in_tuser
	wire          v_algo_comp_axi_st_data_out_tready; // v_round_sat:axi_st_data_in_tready -> v_algo_comp:axi_st_data_out_tready
	wire   [47:0] v_algo_comp_axi_st_data_out_tdata;  // v_algo_comp:axi_st_data_out_tdata -> v_round_sat:axi_st_data_in_tdata
	wire          v_algo_comp_axi_st_data_out_tlast;  // v_algo_comp:axi_st_data_out_tlast -> v_round_sat:axi_st_data_in_tlast
	wire          scheduler_axi_st_v_core_cmd_tvalid; // scheduler:axi_st_v_core_cmd_tvalid -> v_algo_comp:axi_st_cmd_tvalid
	wire          scheduler_axi_st_v_core_cmd_tready; // v_algo_comp:axi_st_cmd_tready -> scheduler:axi_st_v_core_cmd_tready
	wire   [55:0] scheduler_axi_st_v_core_cmd_tdata;  // scheduler:axi_st_v_core_cmd_tdata -> v_algo_comp:axi_st_cmd_tdata
	wire          scheduler_axi_st_h_core_cmd_tvalid; // scheduler:axi_st_h_core_cmd_tvalid -> h_algo_comp:axi_st_cmd_tvalid
	wire          scheduler_axi_st_h_core_cmd_tready; // h_algo_comp:axi_st_cmd_tready -> scheduler:axi_st_h_core_cmd_tready
	wire  [127:0] scheduler_axi_st_h_core_cmd_tdata;  // scheduler:axi_st_h_core_cmd_tdata -> h_algo_comp:axi_st_cmd_tdata
	wire          v_round_sat_axi_st_data_out_tvalid; // v_round_sat:axi_st_data_out_tvalid -> h_algo_comp:axi_st_data_in_tvalid
	wire    [3:0] v_round_sat_axi_st_data_out_tuser;  // v_round_sat:axi_st_data_out_tuser -> h_algo_comp:axi_st_data_in_tuser
	wire          v_round_sat_axi_st_data_out_tready; // h_algo_comp:axi_st_data_in_tready -> v_round_sat:axi_st_data_out_tready
	wire   [31:0] v_round_sat_axi_st_data_out_tdata;  // v_round_sat:axi_st_data_out_tdata -> h_algo_comp:axi_st_data_in_tdata
	wire          v_round_sat_axi_st_data_out_tlast;  // v_round_sat:axi_st_data_out_tlast -> h_algo_comp:axi_st_data_in_tlast
	wire          h_algo_comp_axi_st_data_out_tvalid; // h_algo_comp:axi_st_data_out_tvalid -> out_bridge:axi_st_data_in_tvalid
	wire    [2:0] h_algo_comp_axi_st_data_out_tuser;  // h_algo_comp:axi_st_data_out_tuser -> out_bridge:axi_st_data_in_tuser
	wire          h_algo_comp_axi_st_data_out_tready; // out_bridge:axi_st_data_in_tready -> h_algo_comp:axi_st_data_out_tready
	wire   [23:0] h_algo_comp_axi_st_data_out_tdata;  // h_algo_comp:axi_st_data_out_tdata -> out_bridge:axi_st_data_in_tdata
	wire          h_algo_comp_axi_st_data_out_tlast;  // h_algo_comp:axi_st_data_out_tlast -> out_bridge:axi_st_data_in_tlast

	intel_vvp_reset_sync #(
		.SYNC_LEN (3)
	) main_rst_bridge (
		.clk     (main_clock_clk),                  //   input,  width = 1,       clk.clk
		.in_rst  (main_reset_reset),                //   input,  width = 1,  in_reset.reset
		.out_rst (main_rst_bridge_out_reset_reset)  //  output,  width = 1, out_reset.reset
	);

	intel_vvp_input_interface_bridge #(
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.PIPELINE_READY         (1),
		.EXTERNAL_MODE          (0)
	) in_bridge (
		.clk                    (main_clock_clk),                   //   input,   width = 1,      main_clock.clk
		.rst                    (main_rst_bridge_out_reset_reset),  //   input,   width = 1,      main_reset.reset
		.axi_st_ccd_in_tdata    (axi4s_vid_in_tdata),               //   input,  width = 24,   axi_st_ccd_in.tdata
		.axi_st_ccd_in_tvalid   (axi4s_vid_in_tvalid),              //   input,   width = 1,                .tvalid
		.axi_st_ccd_in_tready   (axi4s_vid_in_tready),              //  output,   width = 1,                .tready
		.axi_st_ccd_in_tlast    (axi4s_vid_in_tlast),               //   input,   width = 1,                .tlast
		.axi_st_ccd_in_tuser    (axi4s_vid_in_tuser),               //   input,   width = 3,                .tuser
		.axi_st_ctrl_out_tdata  (in_bridge_axi_st_ctrl_out_tdata),  //  output,  width = 16, axi_st_ctrl_out.tdata
		.axi_st_ctrl_out_tvalid (in_bridge_axi_st_ctrl_out_tvalid), //  output,   width = 1,                .tvalid
		.axi_st_ctrl_out_tready (in_bridge_axi_st_ctrl_out_tready), //   input,   width = 1,                .tready
		.axi_st_ctrl_out_tlast  (in_bridge_axi_st_ctrl_out_tlast),  //  output,   width = 1,                .tlast
		.axi_st_ctrl_out_tuser  (in_bridge_axi_st_ctrl_out_tuser),  //  output,   width = 2,                .tuser
		.axi_st_data_out_tdata  (in_bridge_axi_st_data_out_tdata),  //  output,  width = 24, axi_st_data_out.tdata
		.axi_st_data_out_tvalid (in_bridge_axi_st_data_out_tvalid), //  output,   width = 1,                .tvalid
		.axi_st_data_out_tready (in_bridge_axi_st_data_out_tready), //   input,   width = 1,                .tready
		.axi_st_data_out_tlast  (in_bridge_axi_st_data_out_tlast),  //  output,   width = 1,                .tlast
		.axi_st_data_out_tuser  (in_bridge_axi_st_data_out_tuser)   //  output,   width = 3,                .tuser
	);

	intel_vvp_output_interface_bridge #(
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.PIPELINE_READY         (1),
		.EXTERNAL_MODE          (0)
	) out_bridge (
		.clk                   (main_clock_clk),                     //   input,   width = 1,     main_clock.clk
		.rst                   (main_rst_bridge_out_reset_reset),    //   input,   width = 1,     main_reset.reset
		.axi_st_ctrl_in_tdata  (scheduler_axi_st_ctrl_out_tdata),    //   input,  width = 16, axi_st_ctrl_in.tdata
		.axi_st_ctrl_in_tvalid (scheduler_axi_st_ctrl_out_tvalid),   //   input,   width = 1,               .tvalid
		.axi_st_ctrl_in_tready (scheduler_axi_st_ctrl_out_tready),   //  output,   width = 1,               .tready
		.axi_st_ctrl_in_tlast  (scheduler_axi_st_ctrl_out_tlast),    //   input,   width = 1,               .tlast
		.axi_st_ctrl_in_tuser  (scheduler_axi_st_ctrl_out_tuser),    //   input,   width = 2,               .tuser
		.axi_st_data_in_tdata  (h_algo_comp_axi_st_data_out_tdata),  //   input,  width = 24, axi_st_data_in.tdata
		.axi_st_data_in_tvalid (h_algo_comp_axi_st_data_out_tvalid), //   input,   width = 1,               .tvalid
		.axi_st_data_in_tready (h_algo_comp_axi_st_data_out_tready), //  output,   width = 1,               .tready
		.axi_st_data_in_tlast  (h_algo_comp_axi_st_data_out_tlast),  //   input,   width = 1,               .tlast
		.axi_st_data_in_tuser  (h_algo_comp_axi_st_data_out_tuser),  //   input,   width = 3,               .tuser
		.axi_st_ccd_out_tdata  (axi4s_vid_out_tdata),                //  output,  width = 24, axi_st_ccd_out.tdata
		.axi_st_ccd_out_tvalid (axi4s_vid_out_tvalid),               //  output,   width = 1,               .tvalid
		.axi_st_ccd_out_tready (axi4s_vid_out_tready),               //   input,   width = 1,               .tready
		.axi_st_ccd_out_tlast  (axi4s_vid_out_tlast),                //  output,   width = 1,               .tlast
		.axi_st_ccd_out_tuser  (axi4s_vid_out_tuser)                 //  output,   width = 3,               .tuser
	);

	intel_vvp_line_buffer #(
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.MAX_WIDTH              (2048),
		.NUM_LINES              (2),
		.ENABLE_RESEND          (1),
		.CMD_COMPATIBILITY      (0),
		.ENABLE_RESPONSE        (0),
		.PIPELINE_READY         (1),
		.DEVICE_FAMILY          ("Agilex 3")
	) line_buffer (
		.clk                    (main_clock_clk),                     //   input,   width = 1,      main_clock.clk
		.rst                    (main_rst_bridge_out_reset_reset),    //   input,   width = 1,      main_reset.reset
		.axi_st_cmd_tdata       (scheduler_axi_st_lb_cmd_tdata),      //   input,  width = 24,      axi_st_cmd.tdata
		.axi_st_cmd_tvalid      (scheduler_axi_st_lb_cmd_tvalid),     //   input,   width = 1,                .tvalid
		.axi_st_cmd_tready      (scheduler_axi_st_lb_cmd_tready),     //  output,   width = 1,                .tready
		.axi_st_data_in_tdata   (in_bridge_axi_st_data_out_tdata),    //   input,  width = 24,  axi_st_data_in.tdata
		.axi_st_data_in_tvalid  (in_bridge_axi_st_data_out_tvalid),   //   input,   width = 1,                .tvalid
		.axi_st_data_in_tready  (in_bridge_axi_st_data_out_tready),   //  output,   width = 1,                .tready
		.axi_st_data_in_tlast   (in_bridge_axi_st_data_out_tlast),    //   input,   width = 1,                .tlast
		.axi_st_data_in_tuser   (in_bridge_axi_st_data_out_tuser),    //   input,   width = 3,                .tuser
		.axi_st_data_out_tdata  (line_buffer_axi_st_data_out_tdata),  //  output,  width = 48, axi_st_data_out.tdata
		.axi_st_data_out_tvalid (line_buffer_axi_st_data_out_tvalid), //  output,   width = 1,                .tvalid
		.axi_st_data_out_tready (line_buffer_axi_st_data_out_tready), //   input,   width = 1,                .tready
		.axi_st_data_out_tlast  (line_buffer_axi_st_data_out_tlast),  //  output,   width = 1,                .tlast
		.axi_st_data_out_tuser  (line_buffer_axi_st_data_out_tuser),  //  output,   width = 6,                .tuser
		.axi_st_resp_tdata      (),                                   // (terminated),                              
		.axi_st_resp_tvalid     (),                                   // (terminated),                              
		.axi_st_resp_tready     (1'b0)                                // (terminated),                              
	);

	intel_vvp_vert_scaler_scheduler #(
		.EXTERNAL_MODE          (0),
		.H_PARTIAL_SCALING      (0),
		.V_PARTIAL_SCALING      (0),
		.ENABLE_V_CORE          (1),
		.ENABLE_H_CORE          (1),
		.ENABLE_444             (1),
		.ENABLE_422             (0),
		.ENABLE_420             (0),
		.ENABLE_420_MIRROR      (0),
		.H_TAPS                 (2),
		.V_TAPS                 (2),
		.V_PHASES               (64),
		.NO_BLANKING            (0),
		.PIXELS_IN_PARALLEL     (1),
		.MAX_IN_WIDTH           (1280),
		.MAX_OUT_WIDTH          (1920),
		.OUTPUT_HEIGHT          (1080),
		.RUNTIME_CONTROL        (0),
		.ENABLE_DEBUG           (0),
		.P_UPDATE_CMD_SUPPORTED (0),
		.P_CORE_CTRL_ID         (0),
		.H_BANKS                (1),
		.V_BANKS                (1),
		.PIPELINE_READY         (0),
		.SLAVE_ADDRESS_WIDTH    (6)
	) scheduler (
		.clk                       (main_clock_clk),                       //   input,    width = 1,        main_clock.clk
		.rst                       (main_rst_bridge_out_reset_reset),      //   input,    width = 1,        main_reset.reset
		.axi_st_ctrl_in_tdata      (in_bridge_axi_st_ctrl_out_tdata),      //   input,   width = 16,    axi_st_ctrl_in.tdata
		.axi_st_ctrl_in_tvalid     (in_bridge_axi_st_ctrl_out_tvalid),     //   input,    width = 1,                  .tvalid
		.axi_st_ctrl_in_tready     (in_bridge_axi_st_ctrl_out_tready),     //  output,    width = 1,                  .tready
		.axi_st_ctrl_in_tlast      (in_bridge_axi_st_ctrl_out_tlast),      //   input,    width = 1,                  .tlast
		.axi_st_ctrl_in_tuser      (in_bridge_axi_st_ctrl_out_tuser),      //   input,    width = 2,                  .tuser
		.axi_st_ctrl_out_tdata     (scheduler_axi_st_ctrl_out_tdata),      //  output,   width = 16,   axi_st_ctrl_out.tdata
		.axi_st_ctrl_out_tvalid    (scheduler_axi_st_ctrl_out_tvalid),     //  output,    width = 1,                  .tvalid
		.axi_st_ctrl_out_tready    (scheduler_axi_st_ctrl_out_tready),     //   input,    width = 1,                  .tready
		.axi_st_ctrl_out_tlast     (scheduler_axi_st_ctrl_out_tlast),      //  output,    width = 1,                  .tlast
		.axi_st_ctrl_out_tuser     (scheduler_axi_st_ctrl_out_tuser),      //  output,    width = 2,                  .tuser
		.axi_st_lb_cmd_tdata       (scheduler_axi_st_lb_cmd_tdata),        //  output,   width = 24,     axi_st_lb_cmd.tdata
		.axi_st_lb_cmd_tvalid      (scheduler_axi_st_lb_cmd_tvalid),       //  output,    width = 1,                  .tvalid
		.axi_st_lb_cmd_tready      (scheduler_axi_st_lb_cmd_tready),       //   input,    width = 1,                  .tready
		.axi_st_v_core_cmd_tdata   (scheduler_axi_st_v_core_cmd_tdata),    //  output,   width = 56, axi_st_v_core_cmd.tdata
		.axi_st_v_core_cmd_tvalid  (scheduler_axi_st_v_core_cmd_tvalid),   //  output,    width = 1,                  .tvalid
		.axi_st_v_core_cmd_tready  (scheduler_axi_st_v_core_cmd_tready),   //   input,    width = 1,                  .tready
		.axi_st_h_core_cmd_tdata   (scheduler_axi_st_h_core_cmd_tdata),    //  output,  width = 128, axi_st_h_core_cmd.tdata
		.axi_st_h_core_cmd_tvalid  (scheduler_axi_st_h_core_cmd_tvalid),   //  output,    width = 1,                  .tvalid
		.axi_st_h_core_cmd_tready  (scheduler_axi_st_h_core_cmd_tready),   //   input,    width = 1,                  .tready
		.av_mm_slave_address       (6'b000000),                            // (terminated),                                 
		.av_mm_slave_write         (1'b0),                                 // (terminated),                                 
		.av_mm_slave_byteenable    (4'b0000),                              // (terminated),                                 
		.av_mm_slave_writedata     (32'b00000000000000000000000000000000), // (terminated),                                 
		.av_mm_slave_read          (1'b0),                                 // (terminated),                                 
		.av_mm_slave_readdata      (),                                     // (terminated),                                 
		.av_mm_slave_readdatavalid (),                                     // (terminated),                                 
		.av_mm_slave_waitrequest   (),                                     // (terminated),                                 
		.axi_st_ls_cmd_tdata       (),                                     // (terminated),                                 
		.axi_st_ls_cmd_tvalid      (),                                     // (terminated),                                 
		.axi_st_ls_cmd_tready      (1'b0),                                 // (terminated),                                 
		.axi_st_lb_resp_tdata      (8'b00000000),                          // (terminated),                                 
		.axi_st_lb_resp_tvalid     (1'b0),                                 // (terminated),                                 
		.axi_st_lb_resp_tready     ()                                      // (terminated),                                 
	);

	nios_system_intel_vvp_scaler_1_intel_vvp_vert_scaler_algo_comp_2450_e22xnvi v_algo_comp (
		.clk                    (main_clock_clk),                     //   input,   width = 1,      main_clock.clk
		.rst                    (main_rst_bridge_out_reset_reset),    //   input,   width = 1,      main_reset.reset
		.axi_st_cmd_tdata       (scheduler_axi_st_v_core_cmd_tdata),  //   input,  width = 56,      axi_st_cmd.tdata
		.axi_st_cmd_tvalid      (scheduler_axi_st_v_core_cmd_tvalid), //   input,   width = 1,                .tvalid
		.axi_st_cmd_tready      (scheduler_axi_st_v_core_cmd_tready), //  output,   width = 1,                .tready
		.axi_st_data_in_tdata   (line_buffer_axi_st_data_out_tdata),  //   input,  width = 48,  axi_st_data_in.tdata
		.axi_st_data_in_tvalid  (line_buffer_axi_st_data_out_tvalid), //   input,   width = 1,                .tvalid
		.axi_st_data_in_tready  (line_buffer_axi_st_data_out_tready), //  output,   width = 1,                .tready
		.axi_st_data_in_tlast   (line_buffer_axi_st_data_out_tlast),  //   input,   width = 1,                .tlast
		.axi_st_data_in_tuser   (line_buffer_axi_st_data_out_tuser),  //   input,   width = 6,                .tuser
		.axi_st_data_out_tdata  (v_algo_comp_axi_st_data_out_tdata),  //  output,  width = 48, axi_st_data_out.tdata
		.axi_st_data_out_tvalid (v_algo_comp_axi_st_data_out_tvalid), //  output,   width = 1,                .tvalid
		.axi_st_data_out_tready (v_algo_comp_axi_st_data_out_tready), //   input,   width = 1,                .tready
		.axi_st_data_out_tlast  (v_algo_comp_axi_st_data_out_tlast),  //  output,   width = 1,                .tlast
		.axi_st_data_out_tuser  (v_algo_comp_axi_st_data_out_tuser)   //  output,   width = 6,                .tuser
	);

	intel_vvp_round_sat_algo_comp #(
		.BPS_IN                 (16),
		.BPS_OUT                (9),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.UNSIGNED_INPUT         (1),
		.FRAC_BITS_IN           (6),
		.PRESERVE_BITS          (0),
		.UNSIGNED_OUTPUT        (1),
		.DO_ROUNDING            (1),
		.PIPELINE_READY         (0)
	) v_round_sat (
		.clk                    (main_clock_clk),                     //   input,   width = 1,      main_clock.clk
		.rst                    (main_rst_bridge_out_reset_reset),    //   input,   width = 1,      main_reset.reset
		.axi_st_data_in_tdata   (v_algo_comp_axi_st_data_out_tdata),  //   input,  width = 48,  axi_st_data_in.tdata
		.axi_st_data_in_tvalid  (v_algo_comp_axi_st_data_out_tvalid), //   input,   width = 1,                .tvalid
		.axi_st_data_in_tready  (v_algo_comp_axi_st_data_out_tready), //  output,   width = 1,                .tready
		.axi_st_data_in_tlast   (v_algo_comp_axi_st_data_out_tlast),  //   input,   width = 1,                .tlast
		.axi_st_data_in_tuser   (v_algo_comp_axi_st_data_out_tuser),  //   input,   width = 6,                .tuser
		.axi_st_data_out_tdata  (v_round_sat_axi_st_data_out_tdata),  //  output,  width = 32, axi_st_data_out.tdata
		.axi_st_data_out_tvalid (v_round_sat_axi_st_data_out_tvalid), //  output,   width = 1,                .tvalid
		.axi_st_data_out_tready (v_round_sat_axi_st_data_out_tready), //   input,   width = 1,                .tready
		.axi_st_data_out_tlast  (v_round_sat_axi_st_data_out_tlast),  //  output,   width = 1,                .tlast
		.axi_st_data_out_tuser  (v_round_sat_axi_st_data_out_tuser)   //  output,   width = 4,                .tuser
	);

	nios_system_intel_vvp_scaler_1_intel_vvp_scaler_h_macro_2450_y7uvv7a h_algo_comp (
		.main_clock_clk         (main_clock_clk),                     //   input,    width = 1,      main_clock.clk
		.main_reset_reset       (main_rst_bridge_out_reset_reset),    //   input,    width = 1,      main_reset.reset
		.axi_st_cmd_tdata       (scheduler_axi_st_h_core_cmd_tdata),  //   input,  width = 128,      axi_st_cmd.tdata
		.axi_st_cmd_tvalid      (scheduler_axi_st_h_core_cmd_tvalid), //   input,    width = 1,                .tvalid
		.axi_st_cmd_tready      (scheduler_axi_st_h_core_cmd_tready), //  output,    width = 1,                .tready
		.axi_st_data_in_tdata   (v_round_sat_axi_st_data_out_tdata),  //   input,   width = 32,  axi_st_data_in.tdata
		.axi_st_data_in_tvalid  (v_round_sat_axi_st_data_out_tvalid), //   input,    width = 1,                .tvalid
		.axi_st_data_in_tready  (v_round_sat_axi_st_data_out_tready), //  output,    width = 1,                .tready
		.axi_st_data_in_tlast   (v_round_sat_axi_st_data_out_tlast),  //   input,    width = 1,                .tlast
		.axi_st_data_in_tuser   (v_round_sat_axi_st_data_out_tuser),  //   input,    width = 4,                .tuser
		.axi_st_data_out_tdata  (h_algo_comp_axi_st_data_out_tdata),  //  output,   width = 24, axi_st_data_out.tdata
		.axi_st_data_out_tvalid (h_algo_comp_axi_st_data_out_tvalid), //  output,    width = 1,                .tvalid
		.axi_st_data_out_tready (h_algo_comp_axi_st_data_out_tready), //   input,    width = 1,                .tready
		.axi_st_data_out_tlast  (h_algo_comp_axi_st_data_out_tlast),  //  output,    width = 1,                .tlast
		.axi_st_data_out_tuser  (h_algo_comp_axi_st_data_out_tuser)   //  output,    width = 3,                .tuser
	);

endmodule
