// img_data_mlab.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module img_data_mlab (
		output wire [7:0]  q,       //       q.dataout, Data output of the memory.The q port is required if the operation_mode parameter is set to any of the following values:SINGLE_PORT,DUAL_PORT,BIDIR_DUAL_PORT,QUAD_PORT
		input  wire [14:0] address, // address.address, Adress input of the memory.The address signal is required for all operation modes.
		input  wire        clock    //   clock.clk,     Memory clock, refer to user guide for specific details
	);

	img_data_mlab_rom_1port_2022_la3f3di rom_1port_0 (
		.q       (q),       //  output,   width = 8,       q.dataout
		.address (address), //   input,  width = 15, address.address
		.clock   (clock)    //   input,   width = 1,   clock.clk
	);

endmodule
