module nios_system_intel_vvp_vfr_0 (
		input  wire         main_clock_clk,                    //          main_clock.clk,          Clock Input
		input  wire         main_reset_reset,                  //          main_reset.reset
		input  wire         mem_clock_clk,                     //           mem_clock.clk,          Clock Input
		input  wire         mem_reset_reset,                   //           mem_reset.reset
		output wire [23:0]  axi4s_vid_out_tdata,               //       axi4s_vid_out.tdata
		output wire         axi4s_vid_out_tvalid,              //                    .tvalid
		input  wire         axi4s_vid_out_tready,              //                    .tready
		output wire         axi4s_vid_out_tlast,               //                    .tlast
		output wire [2:0]   axi4s_vid_out_tuser,               //                    .tuser
		input  wire         fsync_in_read,                     //            fsync_in.read
		output wire         frame_reader_int_irq,              //    frame_reader_int.irq
		output wire [31:0]  av_mm_mem_read_host_address,       // av_mm_mem_read_host.address
		input  wire         av_mm_mem_read_host_waitrequest,   //                    .waitrequest
		output wire [5:0]   av_mm_mem_read_host_burstcount,    //                    .burstcount
		output wire         av_mm_mem_read_host_read,          //                    .read
		input  wire [255:0] av_mm_mem_read_host_readdata,      //                    .readdata
		input  wire         av_mm_mem_read_host_readdatavalid, //                    .readdatavalid
		input  wire [7:0]   av_mm_control_agent_address,       // av_mm_control_agent.address
		input  wire         av_mm_control_agent_write,         //                    .write
		input  wire [3:0]   av_mm_control_agent_byteenable,    //                    .byteenable
		input  wire [31:0]  av_mm_control_agent_writedata,     //                    .writedata
		input  wire         av_mm_control_agent_read,          //                    .read
		output wire [31:0]  av_mm_control_agent_readdata,      //                    .readdata
		output wire         av_mm_control_agent_readdatavalid, //                    .readdatavalid
		output wire         av_mm_control_agent_waitrequest,   //                    .waitrequest
		input  wire         control_clock_clk,                 //       control_clock.clk,          Clock Input
		input  wire         control_reset_reset                //       control_reset.reset
	);
endmodule

