	component img_data is
		port (
			q       : out std_logic_vector(7 downto 0);                     -- dataout
			address : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			clock   : in  std_logic                     := 'X'              -- clk
		);
	end component img_data;

	u0 : component img_data
		port map (
			q       => CONNECTED_TO_q,       --       q.dataout
			address => CONNECTED_TO_address, -- address.address
			clock   => CONNECTED_TO_clock    --   clock.clk
		);

