// nios_system_intel_vvp_vfr_0.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_vfr_0 (
		input  wire         main_clock_clk,                    //          main_clock.clk,          Clock Input
		input  wire         main_reset_reset,                  //          main_reset.reset
		input  wire         mem_clock_clk,                     //           mem_clock.clk,          Clock Input
		input  wire         mem_reset_reset,                   //           mem_reset.reset
		output wire [23:0]  axi4s_vid_out_tdata,               //       axi4s_vid_out.tdata
		output wire         axi4s_vid_out_tvalid,              //                    .tvalid
		input  wire         axi4s_vid_out_tready,              //                    .tready
		output wire         axi4s_vid_out_tlast,               //                    .tlast
		output wire [2:0]   axi4s_vid_out_tuser,               //                    .tuser
		input  wire         fsync_in_read,                     //            fsync_in.read
		output wire         frame_reader_int_irq,              //    frame_reader_int.irq
		output wire [31:0]  av_mm_mem_read_host_address,       // av_mm_mem_read_host.address
		input  wire         av_mm_mem_read_host_waitrequest,   //                    .waitrequest
		output wire [5:0]   av_mm_mem_read_host_burstcount,    //                    .burstcount
		output wire         av_mm_mem_read_host_read,          //                    .read
		input  wire [255:0] av_mm_mem_read_host_readdata,      //                    .readdata
		input  wire         av_mm_mem_read_host_readdatavalid, //                    .readdatavalid
		input  wire [7:0]   av_mm_control_agent_address,       // av_mm_control_agent.address
		input  wire         av_mm_control_agent_write,         //                    .write
		input  wire [3:0]   av_mm_control_agent_byteenable,    //                    .byteenable
		input  wire [31:0]  av_mm_control_agent_writedata,     //                    .writedata
		input  wire         av_mm_control_agent_read,          //                    .read
		output wire [31:0]  av_mm_control_agent_readdata,      //                    .readdata
		output wire         av_mm_control_agent_readdatavalid, //                    .readdatavalid
		output wire         av_mm_control_agent_waitrequest,   //                    .waitrequest
		input  wire         control_clock_clk,                 //       control_clock.clk,          Clock Input
		input  wire         control_reset_reset                //       control_reset.reset
	);

	nios_system_intel_vvp_vfr_0_intel_vvp_vfr_2450_ha3ggia #(
		.MAX_HEIGHT             (720),
		.MAX_WIDTH              (1280),
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.CLOCKS_ARE_SEPARATE    (1),
		.P_AV_MM_DATA_WIDTH     (256),
		.P_AV_MM_ADDR_WIDTH     (32),
		.READ_BURST_TARGET      (32),
		.MAX_BUFFER_SETS        (2)
	) intel_vvp_vfr_0 (
		.main_clock_clk                    (main_clock_clk),                    //   input,    width = 1,          main_clock.clk
		.main_reset_reset                  (main_reset_reset),                  //   input,    width = 1,          main_reset.reset
		.mem_clock_clk                     (mem_clock_clk),                     //   input,    width = 1,           mem_clock.clk
		.mem_reset_reset                   (mem_reset_reset),                   //   input,    width = 1,           mem_reset.reset
		.axi4s_vid_out_tdata               (axi4s_vid_out_tdata),               //  output,   width = 24,       axi4s_vid_out.tdata
		.axi4s_vid_out_tvalid              (axi4s_vid_out_tvalid),              //  output,    width = 1,                    .tvalid
		.axi4s_vid_out_tready              (axi4s_vid_out_tready),              //   input,    width = 1,                    .tready
		.axi4s_vid_out_tlast               (axi4s_vid_out_tlast),               //  output,    width = 1,                    .tlast
		.axi4s_vid_out_tuser               (axi4s_vid_out_tuser),               //  output,    width = 3,                    .tuser
		.fsync_in_read                     (fsync_in_read),                     //   input,    width = 1,            fsync_in.read
		.frame_reader_int_irq              (frame_reader_int_irq),              //  output,    width = 1,    frame_reader_int.irq
		.av_mm_mem_read_host_address       (av_mm_mem_read_host_address),       //  output,   width = 32, av_mm_mem_read_host.address
		.av_mm_mem_read_host_waitrequest   (av_mm_mem_read_host_waitrequest),   //   input,    width = 1,                    .waitrequest
		.av_mm_mem_read_host_burstcount    (av_mm_mem_read_host_burstcount),    //  output,    width = 6,                    .burstcount
		.av_mm_mem_read_host_read          (av_mm_mem_read_host_read),          //  output,    width = 1,                    .read
		.av_mm_mem_read_host_readdata      (av_mm_mem_read_host_readdata),      //   input,  width = 256,                    .readdata
		.av_mm_mem_read_host_readdatavalid (av_mm_mem_read_host_readdatavalid), //   input,    width = 1,                    .readdatavalid
		.av_mm_control_agent_address       (av_mm_control_agent_address),       //   input,    width = 8, av_mm_control_agent.address
		.av_mm_control_agent_write         (av_mm_control_agent_write),         //   input,    width = 1,                    .write
		.av_mm_control_agent_byteenable    (av_mm_control_agent_byteenable),    //   input,    width = 4,                    .byteenable
		.av_mm_control_agent_writedata     (av_mm_control_agent_writedata),     //   input,   width = 32,                    .writedata
		.av_mm_control_agent_read          (av_mm_control_agent_read),          //   input,    width = 1,                    .read
		.av_mm_control_agent_readdata      (av_mm_control_agent_readdata),      //  output,   width = 32,                    .readdata
		.av_mm_control_agent_readdatavalid (av_mm_control_agent_readdatavalid), //  output,    width = 1,                    .readdatavalid
		.av_mm_control_agent_waitrequest   (av_mm_control_agent_waitrequest),   //  output,    width = 1,                    .waitrequest
		.control_clock_clk                 (control_clock_clk),                 //   input,    width = 1,       control_clock.clk
		.control_reset_reset               (control_reset_reset)                //   input,    width = 1,       control_reset.reset
	);

endmodule
