// nios_system_intel_vvp_fr2cv_0_intel_vvp_fr2cv_2430_a633opy.v

// This file was auto-generated from intel_vvp_fr2cv_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_fr2cv_0_intel_vvp_fr2cv_2430_a633opy #(
		parameter DEVICE_FAMILY          = "Agilex 3",
		parameter RUNTIME_CONTROL        = 0,
		parameter SEPARATE_SLAVE_CLOCK   = 0,
		parameter BPS                    = 8,
		parameter NUMBER_OF_COLOR_PLANES = 3,
		parameter PIXELS_IN_PARALLEL     = 1,
		parameter CV_STYLE               = "CVO"
	) (
		output wire        cv_clk_out_clk,           //      cv_clk_out.clk
		output wire [23:0] cv_vid_out_vid_data,      //      cv_vid_out.vid_data
		output wire        cv_vid_out_underflow,     //                .underflow
		output wire        cv_vid_out_vid_datavalid, //                .vid_datavalid
		output wire        cv_vid_out_vid_v_sync,    //                .vid_v_sync
		output wire        cv_vid_out_vid_h_sync,    //                .vid_h_sync
		output wire        cv_vid_out_vid_f,         //                .vid_f
		output wire        cv_vid_out_vid_h,         //                .vid_h
		output wire        cv_vid_out_vid_v,         //                .vid_v
		input  wire [31:0] axi4s_fr_vid_in_tdata,    // axi4s_fr_vid_in.tdata
		input  wire        axi4s_fr_vid_in_tvalid,   //                .tvalid
		output wire        axi4s_fr_vid_in_tready,   //                .tready
		input  wire        axi4s_fr_vid_in_tlast,    //                .tlast
		input  wire [3:0]  axi4s_fr_vid_in_tuser,    //                .tuser
		input  wire        vid_clock_clk,            //       vid_clock.clk,          Clock Input
		input  wire        vid_reset_reset           //       vid_reset.reset
	);

	wire    vid_reset_bridge_out_reset_reset; // vid_reset_bridge:out_rst -> core:vid_rst

	generate
		// If any of the display statements (or deliberately broken
		// instantiations) within this generate block triggers then this module
		// has been instantiated this module with a set of parameters different
		// from those it was generated for.  This will usually result in a
		// non-functioning system.
		if (DEVICE_FAMILY != "Agilex 3")
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					device_family_check ( .error(1'b1) );
		end
		if (RUNTIME_CONTROL != 0)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					runtime_control_check ( .error(1'b1) );
		end
		if (SEPARATE_SLAVE_CLOCK != 0)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					separate_slave_clock_check ( .error(1'b1) );
		end
		if (BPS != 8)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					bps_check ( .error(1'b1) );
		end
		if (NUMBER_OF_COLOR_PLANES != 3)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					number_of_color_planes_check ( .error(1'b1) );
		end
		if (PIXELS_IN_PARALLEL != 1)
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					pixels_in_parallel_check ( .error(1'b1) );
		end
		if (CV_STYLE != "CVO")
		begin
		// synthesis translate_off
			initial begin
				$display("Generated module instantiated with wrong parameters");
				$stop;
			end
		// synthesis translate_on
			instantiated_with_wrong_parameters_error_see_comment_above
					cv_style_check ( .error(1'b1) );
		end
	endgenerate

	intel_vvp_fr2cv_core #(
		.DEVICE_FAMILY          ("Agilex 3"),
		.RUNTIME_CONTROL        (0),
		.SEPARATE_SLAVE_CLOCK   (0),
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.CV_STYLE               ("CVO"),
		.CV_USE_VALID           (0),
		.CV_USE_READY           (0),
		.CV_HV_MODE             ("both"),
		.CVO_BUS_HAS_CV_CLK     (0),
		.STD_WIDTH              (1)
	) core (
		.vid_clk                (vid_clock_clk),                    //   input,   width = 1,       vid_clock.clk
		.vid_rst                (vid_reset_bridge_out_reset_reset), //   input,   width = 1,       vid_reset.reset
		.cv_clk                 (cv_clk_out_clk),                   //  output,   width = 1,        cv_clock.clk
		.cvo_vid_data           (cv_vid_out_vid_data),              //  output,  width = 24,      cv_vid_out.vid_data
		.cvo_underflow          (cv_vid_out_underflow),             //  output,   width = 1,                .underflow
		.cvo_vid_datavalid      (cv_vid_out_vid_datavalid),         //  output,   width = 1,                .vid_datavalid
		.cvo_vid_v_sync         (cv_vid_out_vid_v_sync),            //  output,   width = 1,                .vid_v_sync
		.cvo_vid_h_sync         (cv_vid_out_vid_h_sync),            //  output,   width = 1,                .vid_h_sync
		.cvo_vid_f              (cv_vid_out_vid_f),                 //  output,   width = 1,                .vid_f
		.cvo_vid_h              (cv_vid_out_vid_h),                 //  output,   width = 1,                .vid_h
		.cvo_vid_v              (cv_vid_out_vid_v),                 //  output,   width = 1,                .vid_v
		.axi4s_fr_vid_in_tdata  (axi4s_fr_vid_in_tdata),            //   input,  width = 32, axi4s_fr_vid_in.tdata
		.axi4s_fr_vid_in_tvalid (axi4s_fr_vid_in_tvalid),           //   input,   width = 1,                .tvalid
		.axi4s_fr_vid_in_tready (axi4s_fr_vid_in_tready),           //  output,   width = 1,                .tready
		.axi4s_fr_vid_in_tlast  (axi4s_fr_vid_in_tlast),            //   input,   width = 1,                .tlast
		.axi4s_fr_vid_in_tuser  (axi4s_fr_vid_in_tuser),            //   input,   width = 4,                .tuser
		.cvo_vid_clk            (1'b0),                             // (terminated),                              
		.cvo_vid_mode_change    (),                                 // (terminated),                              
		.cvo_vid_vcoclk_div     (),                                 // (terminated),                              
		.cvo_vid_sof_locked     (),                                 // (terminated),                              
		.cvo_vid_sof            (),                                 // (terminated),                              
		.cvo_vid_std            ()                                  // (terminated),                              
	);

	intel_vvp_reset_sync #(
		.SYNC_LEN (3)
	) vid_reset_bridge (
		.clk     (vid_clock_clk),                    //   input,  width = 1,       clk.clk
		.in_rst  (vid_reset_reset),                  //   input,  width = 1,  in_reset.reset
		.out_rst (vid_reset_bridge_out_reset_reset)  //  output,  width = 1, out_reset.reset
	);

endmodule
