// nios_system_altera_mm_interconnect_1920_kcrmkba.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_altera_mm_interconnect_1920_kcrmkba (
		input  wire [31:0]  intel_vvp_vfr_av_mm_mem_read_host_address,           //             intel_vvp_vfr_av_mm_mem_read_host.address
		output wire         intel_vvp_vfr_av_mm_mem_read_host_waitrequest,       //                                              .waitrequest
		input  wire [5:0]   intel_vvp_vfr_av_mm_mem_read_host_burstcount,        //                                              .burstcount
		input  wire         intel_vvp_vfr_av_mm_mem_read_host_read,              //                                              .read
		output wire [255:0] intel_vvp_vfr_av_mm_mem_read_host_readdata,          //                                              .readdata
		output wire         intel_vvp_vfr_av_mm_mem_read_host_readdatavalid,     //                                              .readdatavalid
		input  wire [31:0]  niosv_g_data_manager_awaddr,                         //                          niosv_g_data_manager.awaddr
		input  wire [7:0]   niosv_g_data_manager_awlen,                          //                                              .awlen
		input  wire [2:0]   niosv_g_data_manager_awsize,                         //                                              .awsize
		input  wire [2:0]   niosv_g_data_manager_awprot,                         //                                              .awprot
		input  wire         niosv_g_data_manager_awvalid,                        //                                              .awvalid
		output wire         niosv_g_data_manager_awready,                        //                                              .awready
		input  wire [31:0]  niosv_g_data_manager_wdata,                          //                                              .wdata
		input  wire [3:0]   niosv_g_data_manager_wstrb,                          //                                              .wstrb
		input  wire         niosv_g_data_manager_wlast,                          //                                              .wlast
		input  wire         niosv_g_data_manager_wvalid,                         //                                              .wvalid
		output wire         niosv_g_data_manager_wready,                         //                                              .wready
		output wire [1:0]   niosv_g_data_manager_bresp,                          //                                              .bresp
		output wire         niosv_g_data_manager_bvalid,                         //                                              .bvalid
		input  wire         niosv_g_data_manager_bready,                         //                                              .bready
		input  wire [31:0]  niosv_g_data_manager_araddr,                         //                                              .araddr
		input  wire [7:0]   niosv_g_data_manager_arlen,                          //                                              .arlen
		input  wire [2:0]   niosv_g_data_manager_arsize,                         //                                              .arsize
		input  wire [2:0]   niosv_g_data_manager_arprot,                         //                                              .arprot
		input  wire         niosv_g_data_manager_arvalid,                        //                                              .arvalid
		output wire         niosv_g_data_manager_arready,                        //                                              .arready
		output wire [31:0]  niosv_g_data_manager_rdata,                          //                                              .rdata
		output wire [1:0]   niosv_g_data_manager_rresp,                          //                                              .rresp
		output wire         niosv_g_data_manager_rlast,                          //                                              .rlast
		output wire         niosv_g_data_manager_rvalid,                         //                                              .rvalid
		input  wire         niosv_g_data_manager_rready,                         //                                              .rready
		input  wire [31:0]  niosv_g_instruction_manager_awaddr,                  //                   niosv_g_instruction_manager.awaddr
		input  wire [7:0]   niosv_g_instruction_manager_awlen,                   //                                              .awlen
		input  wire [2:0]   niosv_g_instruction_manager_awsize,                  //                                              .awsize
		input  wire [1:0]   niosv_g_instruction_manager_awburst,                 //                                              .awburst
		input  wire [2:0]   niosv_g_instruction_manager_awprot,                  //                                              .awprot
		input  wire         niosv_g_instruction_manager_awvalid,                 //                                              .awvalid
		output wire         niosv_g_instruction_manager_awready,                 //                                              .awready
		input  wire [31:0]  niosv_g_instruction_manager_wdata,                   //                                              .wdata
		input  wire [3:0]   niosv_g_instruction_manager_wstrb,                   //                                              .wstrb
		input  wire         niosv_g_instruction_manager_wlast,                   //                                              .wlast
		input  wire         niosv_g_instruction_manager_wvalid,                  //                                              .wvalid
		output wire         niosv_g_instruction_manager_wready,                  //                                              .wready
		output wire [1:0]   niosv_g_instruction_manager_bresp,                   //                                              .bresp
		output wire         niosv_g_instruction_manager_bvalid,                  //                                              .bvalid
		input  wire         niosv_g_instruction_manager_bready,                  //                                              .bready
		input  wire [31:0]  niosv_g_instruction_manager_araddr,                  //                                              .araddr
		input  wire [7:0]   niosv_g_instruction_manager_arlen,                   //                                              .arlen
		input  wire [2:0]   niosv_g_instruction_manager_arsize,                  //                                              .arsize
		input  wire [1:0]   niosv_g_instruction_manager_arburst,                 //                                              .arburst
		input  wire [2:0]   niosv_g_instruction_manager_arprot,                  //                                              .arprot
		input  wire         niosv_g_instruction_manager_arvalid,                 //                                              .arvalid
		output wire         niosv_g_instruction_manager_arready,                 //                                              .arready
		output wire [31:0]  niosv_g_instruction_manager_rdata,                   //                                              .rdata
		output wire [1:0]   niosv_g_instruction_manager_rresp,                   //                                              .rresp
		output wire         niosv_g_instruction_manager_rlast,                   //                                              .rlast
		output wire         niosv_g_instruction_manager_rvalid,                  //                                              .rvalid
		input  wire         niosv_g_instruction_manager_rready,                  //                                              .rready
		output wire [3:0]   sdram_axi4_slave_awid,                               //                              sdram_axi4_slave.awid
		output wire [25:0]  sdram_axi4_slave_awaddr,                             //                                              .awaddr
		output wire [7:0]   sdram_axi4_slave_awlen,                              //                                              .awlen
		output wire [2:0]   sdram_axi4_slave_awsize,                             //                                              .awsize
		output wire [1:0]   sdram_axi4_slave_awburst,                            //                                              .awburst
		output wire         sdram_axi4_slave_awvalid,                            //                                              .awvalid
		input  wire         sdram_axi4_slave_awready,                            //                                              .awready
		output wire [63:0]  sdram_axi4_slave_wdata,                              //                                              .wdata
		output wire [7:0]   sdram_axi4_slave_wstrb,                              //                                              .wstrb
		output wire         sdram_axi4_slave_wlast,                              //                                              .wlast
		output wire         sdram_axi4_slave_wvalid,                             //                                              .wvalid
		input  wire         sdram_axi4_slave_wready,                             //                                              .wready
		input  wire [3:0]   sdram_axi4_slave_bid,                                //                                              .bid
		input  wire [1:0]   sdram_axi4_slave_bresp,                              //                                              .bresp
		input  wire         sdram_axi4_slave_bvalid,                             //                                              .bvalid
		output wire         sdram_axi4_slave_bready,                             //                                              .bready
		output wire [3:0]   sdram_axi4_slave_arid,                               //                                              .arid
		output wire [25:0]  sdram_axi4_slave_araddr,                             //                                              .araddr
		output wire [7:0]   sdram_axi4_slave_arlen,                              //                                              .arlen
		output wire [2:0]   sdram_axi4_slave_arsize,                             //                                              .arsize
		output wire [1:0]   sdram_axi4_slave_arburst,                            //                                              .arburst
		output wire         sdram_axi4_slave_arvalid,                            //                                              .arvalid
		input  wire         sdram_axi4_slave_arready,                            //                                              .arready
		input  wire [3:0]   sdram_axi4_slave_rid,                                //                                              .rid
		input  wire [63:0]  sdram_axi4_slave_rdata,                              //                                              .rdata
		input  wire [1:0]   sdram_axi4_slave_rresp,                              //                                              .rresp
		input  wire         sdram_axi4_slave_rlast,                              //                                              .rlast
		input  wire         sdram_axi4_slave_rvalid,                             //                                              .rvalid
		output wire         sdram_axi4_slave_rready,                             //                                              .rready
		output wire [15:0]  niosv_g_dm_agent_address,                            //                              niosv_g_dm_agent.address
		output wire         niosv_g_dm_agent_write,                              //                                              .write
		output wire         niosv_g_dm_agent_read,                               //                                              .read
		input  wire [31:0]  niosv_g_dm_agent_readdata,                           //                                              .readdata
		output wire [31:0]  niosv_g_dm_agent_writedata,                          //                                              .writedata
		input  wire         niosv_g_dm_agent_readdatavalid,                      //                                              .readdatavalid
		input  wire         niosv_g_dm_agent_waitrequest,                        //                                              .waitrequest
		output wire [17:0]  mm_bridge_peripheral_s0_address,                     //                       mm_bridge_peripheral_s0.address
		output wire         mm_bridge_peripheral_s0_write,                       //                                              .write
		output wire         mm_bridge_peripheral_s0_read,                        //                                              .read
		input  wire [31:0]  mm_bridge_peripheral_s0_readdata,                    //                                              .readdata
		output wire [31:0]  mm_bridge_peripheral_s0_writedata,                   //                                              .writedata
		output wire [0:0]   mm_bridge_peripheral_s0_burstcount,                  //                                              .burstcount
		output wire [3:0]   mm_bridge_peripheral_s0_byteenable,                  //                                              .byteenable
		input  wire         mm_bridge_peripheral_s0_readdatavalid,               //                                              .readdatavalid
		input  wire         mm_bridge_peripheral_s0_waitrequest,                 //                                              .waitrequest
		output wire         mm_bridge_peripheral_s0_debugaccess,                 //                                              .debugaccess
		output wire [16:0]  onchip_memory_s1_address,                            //                              onchip_memory_s1.address
		output wire         onchip_memory_s1_write,                              //                                              .write
		output wire         onchip_memory_s1_read,                               //                                              .read
		input  wire [31:0]  onchip_memory_s1_readdata,                           //                                              .readdata
		output wire [31:0]  onchip_memory_s1_writedata,                          //                                              .writedata
		output wire [3:0]   onchip_memory_s1_byteenable,                         //                                              .byteenable
		output wire [5:0]   niosv_g_timer_sw_agent_address,                      //                        niosv_g_timer_sw_agent.address
		output wire         niosv_g_timer_sw_agent_write,                        //                                              .write
		output wire         niosv_g_timer_sw_agent_read,                         //                                              .read
		input  wire [31:0]  niosv_g_timer_sw_agent_readdata,                     //                                              .readdata
		output wire [31:0]  niosv_g_timer_sw_agent_writedata,                    //                                              .writedata
		output wire [3:0]   niosv_g_timer_sw_agent_byteenable,                   //                                              .byteenable
		input  wire         niosv_g_timer_sw_agent_readdatavalid,                //                                              .readdatavalid
		input  wire         niosv_g_timer_sw_agent_waitrequest,                  //                                              .waitrequest
		input  wire         intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset, // intel_vvp_vfr_mem_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire         niosv_g_reset_reset_bridge_in_reset_reset,           //           niosv_g_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire         iopll_outclk0_clk                                    //                                 iopll_outclk0.clk,          Clock Input
	);

	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_waitrequest;           // intel_vvp_vfr_av_mm_mem_read_host_agent:av_waitrequest -> intel_vvp_vfr_av_mm_mem_read_host_translator:uav_waitrequest
	wire  [255:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdata;              // intel_vvp_vfr_av_mm_mem_read_host_agent:av_readdata -> intel_vvp_vfr_av_mm_mem_read_host_translator:uav_readdata
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_debugaccess;           // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_debugaccess -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_debugaccess
	wire   [31:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_address;               // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_address -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_address
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_read;                  // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_read -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_read
	wire   [31:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_byteenable;            // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_byteenable -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_byteenable
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdatavalid;         // intel_vvp_vfr_av_mm_mem_read_host_agent:av_readdatavalid -> intel_vvp_vfr_av_mm_mem_read_host_translator:uav_readdatavalid
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_lock;                  // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_lock -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_lock
	wire          intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_write;                 // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_write -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_write
	wire  [255:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_writedata;             // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_writedata -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_writedata
	wire   [10:0] intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_burstcount;            // intel_vvp_vfr_av_mm_mem_read_host_translator:uav_burstcount -> intel_vvp_vfr_av_mm_mem_read_host_agent:av_burstcount
	wire    [0:0] niosv_g_data_manager_translator_m0_ruser;                                                     // niosv_g_data_manager_agent:ruser -> niosv_g_data_manager_translator:m0_ruser
	wire    [0:0] niosv_g_data_manager_translator_m0_wuser;                                                     // niosv_g_data_manager_translator:m0_wuser -> niosv_g_data_manager_agent:wuser
	wire    [1:0] niosv_g_data_manager_translator_m0_awburst;                                                   // niosv_g_data_manager_translator:m0_awburst -> niosv_g_data_manager_agent:awburst
	wire    [3:0] niosv_g_data_manager_translator_m0_arregion;                                                  // niosv_g_data_manager_translator:m0_arregion -> niosv_g_data_manager_agent:arregion
	wire    [0:0] niosv_g_data_manager_translator_m0_awuser;                                                    // niosv_g_data_manager_translator:m0_awuser -> niosv_g_data_manager_agent:awuser
	wire    [7:0] niosv_g_data_manager_translator_m0_arlen;                                                     // niosv_g_data_manager_translator:m0_arlen -> niosv_g_data_manager_agent:arlen
	wire    [3:0] niosv_g_data_manager_translator_m0_arqos;                                                     // niosv_g_data_manager_translator:m0_arqos -> niosv_g_data_manager_agent:arqos
	wire    [3:0] niosv_g_data_manager_translator_m0_wstrb;                                                     // niosv_g_data_manager_translator:m0_wstrb -> niosv_g_data_manager_agent:wstrb
	wire          niosv_g_data_manager_translator_m0_wready;                                                    // niosv_g_data_manager_agent:wready -> niosv_g_data_manager_translator:m0_wready
	wire    [0:0] niosv_g_data_manager_translator_m0_rid;                                                       // niosv_g_data_manager_agent:rid -> niosv_g_data_manager_translator:m0_rid
	wire          niosv_g_data_manager_translator_m0_rready;                                                    // niosv_g_data_manager_translator:m0_rready -> niosv_g_data_manager_agent:rready
	wire    [7:0] niosv_g_data_manager_translator_m0_awlen;                                                     // niosv_g_data_manager_translator:m0_awlen -> niosv_g_data_manager_agent:awlen
	wire    [3:0] niosv_g_data_manager_translator_m0_awqos;                                                     // niosv_g_data_manager_translator:m0_awqos -> niosv_g_data_manager_agent:awqos
	wire    [3:0] niosv_g_data_manager_translator_m0_arcache;                                                   // niosv_g_data_manager_translator:m0_arcache -> niosv_g_data_manager_agent:arcache
	wire          niosv_g_data_manager_translator_m0_wvalid;                                                    // niosv_g_data_manager_translator:m0_wvalid -> niosv_g_data_manager_agent:wvalid
	wire   [31:0] niosv_g_data_manager_translator_m0_araddr;                                                    // niosv_g_data_manager_translator:m0_araddr -> niosv_g_data_manager_agent:araddr
	wire    [2:0] niosv_g_data_manager_translator_m0_arprot;                                                    // niosv_g_data_manager_translator:m0_arprot -> niosv_g_data_manager_agent:arprot
	wire    [2:0] niosv_g_data_manager_translator_m0_awprot;                                                    // niosv_g_data_manager_translator:m0_awprot -> niosv_g_data_manager_agent:awprot
	wire   [31:0] niosv_g_data_manager_translator_m0_wdata;                                                     // niosv_g_data_manager_translator:m0_wdata -> niosv_g_data_manager_agent:wdata
	wire          niosv_g_data_manager_translator_m0_arvalid;                                                   // niosv_g_data_manager_translator:m0_arvalid -> niosv_g_data_manager_agent:arvalid
	wire    [3:0] niosv_g_data_manager_translator_m0_awcache;                                                   // niosv_g_data_manager_translator:m0_awcache -> niosv_g_data_manager_agent:awcache
	wire    [0:0] niosv_g_data_manager_translator_m0_arid;                                                      // niosv_g_data_manager_translator:m0_arid -> niosv_g_data_manager_agent:arid
	wire    [0:0] niosv_g_data_manager_translator_m0_arlock;                                                    // niosv_g_data_manager_translator:m0_arlock -> niosv_g_data_manager_agent:arlock
	wire    [0:0] niosv_g_data_manager_translator_m0_awlock;                                                    // niosv_g_data_manager_translator:m0_awlock -> niosv_g_data_manager_agent:awlock
	wire   [31:0] niosv_g_data_manager_translator_m0_awaddr;                                                    // niosv_g_data_manager_translator:m0_awaddr -> niosv_g_data_manager_agent:awaddr
	wire    [1:0] niosv_g_data_manager_translator_m0_bresp;                                                     // niosv_g_data_manager_agent:bresp -> niosv_g_data_manager_translator:m0_bresp
	wire          niosv_g_data_manager_translator_m0_arready;                                                   // niosv_g_data_manager_agent:arready -> niosv_g_data_manager_translator:m0_arready
	wire   [31:0] niosv_g_data_manager_translator_m0_rdata;                                                     // niosv_g_data_manager_agent:rdata -> niosv_g_data_manager_translator:m0_rdata
	wire          niosv_g_data_manager_translator_m0_awready;                                                   // niosv_g_data_manager_agent:awready -> niosv_g_data_manager_translator:m0_awready
	wire    [1:0] niosv_g_data_manager_translator_m0_arburst;                                                   // niosv_g_data_manager_translator:m0_arburst -> niosv_g_data_manager_agent:arburst
	wire    [2:0] niosv_g_data_manager_translator_m0_arsize;                                                    // niosv_g_data_manager_translator:m0_arsize -> niosv_g_data_manager_agent:arsize
	wire          niosv_g_data_manager_translator_m0_bready;                                                    // niosv_g_data_manager_translator:m0_bready -> niosv_g_data_manager_agent:bready
	wire          niosv_g_data_manager_translator_m0_rlast;                                                     // niosv_g_data_manager_agent:rlast -> niosv_g_data_manager_translator:m0_rlast
	wire          niosv_g_data_manager_translator_m0_wlast;                                                     // niosv_g_data_manager_translator:m0_wlast -> niosv_g_data_manager_agent:wlast
	wire    [3:0] niosv_g_data_manager_translator_m0_awregion;                                                  // niosv_g_data_manager_translator:m0_awregion -> niosv_g_data_manager_agent:awregion
	wire    [0:0] niosv_g_data_manager_translator_m0_buser;                                                     // niosv_g_data_manager_agent:buser -> niosv_g_data_manager_translator:m0_buser
	wire    [1:0] niosv_g_data_manager_translator_m0_rresp;                                                     // niosv_g_data_manager_agent:rresp -> niosv_g_data_manager_translator:m0_rresp
	wire    [0:0] niosv_g_data_manager_translator_m0_awid;                                                      // niosv_g_data_manager_translator:m0_awid -> niosv_g_data_manager_agent:awid
	wire    [0:0] niosv_g_data_manager_translator_m0_bid;                                                       // niosv_g_data_manager_agent:bid -> niosv_g_data_manager_translator:m0_bid
	wire          niosv_g_data_manager_translator_m0_bvalid;                                                    // niosv_g_data_manager_agent:bvalid -> niosv_g_data_manager_translator:m0_bvalid
	wire    [2:0] niosv_g_data_manager_translator_m0_awsize;                                                    // niosv_g_data_manager_translator:m0_awsize -> niosv_g_data_manager_agent:awsize
	wire          niosv_g_data_manager_translator_m0_awvalid;                                                   // niosv_g_data_manager_translator:m0_awvalid -> niosv_g_data_manager_agent:awvalid
	wire    [0:0] niosv_g_data_manager_translator_m0_aruser;                                                    // niosv_g_data_manager_translator:m0_aruser -> niosv_g_data_manager_agent:aruser
	wire          niosv_g_data_manager_translator_m0_rvalid;                                                    // niosv_g_data_manager_agent:rvalid -> niosv_g_data_manager_translator:m0_rvalid
	wire          rsp_mux_001_src_valid;                                                                        // rsp_mux_001:src_valid -> niosv_g_data_manager_agent:write_rp_valid
	wire  [153:0] rsp_mux_001_src_data;                                                                         // rsp_mux_001:src_data -> niosv_g_data_manager_agent:write_rp_data
	wire          rsp_mux_001_src_ready;                                                                        // niosv_g_data_manager_agent:write_rp_ready -> rsp_mux_001:src_ready
	wire    [5:0] rsp_mux_001_src_channel;                                                                      // rsp_mux_001:src_channel -> niosv_g_data_manager_agent:write_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                                                // rsp_mux_001:src_startofpacket -> niosv_g_data_manager_agent:write_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                                  // rsp_mux_001:src_endofpacket -> niosv_g_data_manager_agent:write_rp_endofpacket
	wire          rsp_mux_002_src_valid;                                                                        // rsp_mux_002:src_valid -> niosv_g_data_manager_agent:read_rp_valid
	wire  [153:0] rsp_mux_002_src_data;                                                                         // rsp_mux_002:src_data -> niosv_g_data_manager_agent:read_rp_data
	wire          rsp_mux_002_src_ready;                                                                        // niosv_g_data_manager_agent:read_rp_ready -> rsp_mux_002:src_ready
	wire    [5:0] rsp_mux_002_src_channel;                                                                      // rsp_mux_002:src_channel -> niosv_g_data_manager_agent:read_rp_channel
	wire          rsp_mux_002_src_startofpacket;                                                                // rsp_mux_002:src_startofpacket -> niosv_g_data_manager_agent:read_rp_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                                  // rsp_mux_002:src_endofpacket -> niosv_g_data_manager_agent:read_rp_endofpacket
	wire    [0:0] niosv_g_instruction_manager_translator_m0_ruser;                                              // niosv_g_instruction_manager_agent:ruser -> niosv_g_instruction_manager_translator:m0_ruser
	wire    [0:0] niosv_g_instruction_manager_translator_m0_wuser;                                              // niosv_g_instruction_manager_translator:m0_wuser -> niosv_g_instruction_manager_agent:wuser
	wire    [1:0] niosv_g_instruction_manager_translator_m0_awburst;                                            // niosv_g_instruction_manager_translator:m0_awburst -> niosv_g_instruction_manager_agent:awburst
	wire    [3:0] niosv_g_instruction_manager_translator_m0_arregion;                                           // niosv_g_instruction_manager_translator:m0_arregion -> niosv_g_instruction_manager_agent:arregion
	wire    [0:0] niosv_g_instruction_manager_translator_m0_awuser;                                             // niosv_g_instruction_manager_translator:m0_awuser -> niosv_g_instruction_manager_agent:awuser
	wire    [7:0] niosv_g_instruction_manager_translator_m0_arlen;                                              // niosv_g_instruction_manager_translator:m0_arlen -> niosv_g_instruction_manager_agent:arlen
	wire    [3:0] niosv_g_instruction_manager_translator_m0_arqos;                                              // niosv_g_instruction_manager_translator:m0_arqos -> niosv_g_instruction_manager_agent:arqos
	wire    [3:0] niosv_g_instruction_manager_translator_m0_wstrb;                                              // niosv_g_instruction_manager_translator:m0_wstrb -> niosv_g_instruction_manager_agent:wstrb
	wire          niosv_g_instruction_manager_translator_m0_wready;                                             // niosv_g_instruction_manager_agent:wready -> niosv_g_instruction_manager_translator:m0_wready
	wire    [0:0] niosv_g_instruction_manager_translator_m0_rid;                                                // niosv_g_instruction_manager_agent:rid -> niosv_g_instruction_manager_translator:m0_rid
	wire          niosv_g_instruction_manager_translator_m0_rready;                                             // niosv_g_instruction_manager_translator:m0_rready -> niosv_g_instruction_manager_agent:rready
	wire    [7:0] niosv_g_instruction_manager_translator_m0_awlen;                                              // niosv_g_instruction_manager_translator:m0_awlen -> niosv_g_instruction_manager_agent:awlen
	wire    [3:0] niosv_g_instruction_manager_translator_m0_awqos;                                              // niosv_g_instruction_manager_translator:m0_awqos -> niosv_g_instruction_manager_agent:awqos
	wire    [3:0] niosv_g_instruction_manager_translator_m0_arcache;                                            // niosv_g_instruction_manager_translator:m0_arcache -> niosv_g_instruction_manager_agent:arcache
	wire          niosv_g_instruction_manager_translator_m0_wvalid;                                             // niosv_g_instruction_manager_translator:m0_wvalid -> niosv_g_instruction_manager_agent:wvalid
	wire   [31:0] niosv_g_instruction_manager_translator_m0_araddr;                                             // niosv_g_instruction_manager_translator:m0_araddr -> niosv_g_instruction_manager_agent:araddr
	wire    [2:0] niosv_g_instruction_manager_translator_m0_arprot;                                             // niosv_g_instruction_manager_translator:m0_arprot -> niosv_g_instruction_manager_agent:arprot
	wire    [2:0] niosv_g_instruction_manager_translator_m0_awprot;                                             // niosv_g_instruction_manager_translator:m0_awprot -> niosv_g_instruction_manager_agent:awprot
	wire   [31:0] niosv_g_instruction_manager_translator_m0_wdata;                                              // niosv_g_instruction_manager_translator:m0_wdata -> niosv_g_instruction_manager_agent:wdata
	wire          niosv_g_instruction_manager_translator_m0_arvalid;                                            // niosv_g_instruction_manager_translator:m0_arvalid -> niosv_g_instruction_manager_agent:arvalid
	wire    [3:0] niosv_g_instruction_manager_translator_m0_awcache;                                            // niosv_g_instruction_manager_translator:m0_awcache -> niosv_g_instruction_manager_agent:awcache
	wire    [0:0] niosv_g_instruction_manager_translator_m0_arid;                                               // niosv_g_instruction_manager_translator:m0_arid -> niosv_g_instruction_manager_agent:arid
	wire    [0:0] niosv_g_instruction_manager_translator_m0_arlock;                                             // niosv_g_instruction_manager_translator:m0_arlock -> niosv_g_instruction_manager_agent:arlock
	wire    [0:0] niosv_g_instruction_manager_translator_m0_awlock;                                             // niosv_g_instruction_manager_translator:m0_awlock -> niosv_g_instruction_manager_agent:awlock
	wire   [31:0] niosv_g_instruction_manager_translator_m0_awaddr;                                             // niosv_g_instruction_manager_translator:m0_awaddr -> niosv_g_instruction_manager_agent:awaddr
	wire    [1:0] niosv_g_instruction_manager_translator_m0_bresp;                                              // niosv_g_instruction_manager_agent:bresp -> niosv_g_instruction_manager_translator:m0_bresp
	wire          niosv_g_instruction_manager_translator_m0_arready;                                            // niosv_g_instruction_manager_agent:arready -> niosv_g_instruction_manager_translator:m0_arready
	wire   [31:0] niosv_g_instruction_manager_translator_m0_rdata;                                              // niosv_g_instruction_manager_agent:rdata -> niosv_g_instruction_manager_translator:m0_rdata
	wire          niosv_g_instruction_manager_translator_m0_awready;                                            // niosv_g_instruction_manager_agent:awready -> niosv_g_instruction_manager_translator:m0_awready
	wire    [1:0] niosv_g_instruction_manager_translator_m0_arburst;                                            // niosv_g_instruction_manager_translator:m0_arburst -> niosv_g_instruction_manager_agent:arburst
	wire    [2:0] niosv_g_instruction_manager_translator_m0_arsize;                                             // niosv_g_instruction_manager_translator:m0_arsize -> niosv_g_instruction_manager_agent:arsize
	wire          niosv_g_instruction_manager_translator_m0_bready;                                             // niosv_g_instruction_manager_translator:m0_bready -> niosv_g_instruction_manager_agent:bready
	wire          niosv_g_instruction_manager_translator_m0_rlast;                                              // niosv_g_instruction_manager_agent:rlast -> niosv_g_instruction_manager_translator:m0_rlast
	wire          niosv_g_instruction_manager_translator_m0_wlast;                                              // niosv_g_instruction_manager_translator:m0_wlast -> niosv_g_instruction_manager_agent:wlast
	wire    [3:0] niosv_g_instruction_manager_translator_m0_awregion;                                           // niosv_g_instruction_manager_translator:m0_awregion -> niosv_g_instruction_manager_agent:awregion
	wire    [0:0] niosv_g_instruction_manager_translator_m0_buser;                                              // niosv_g_instruction_manager_agent:buser -> niosv_g_instruction_manager_translator:m0_buser
	wire    [1:0] niosv_g_instruction_manager_translator_m0_rresp;                                              // niosv_g_instruction_manager_agent:rresp -> niosv_g_instruction_manager_translator:m0_rresp
	wire    [0:0] niosv_g_instruction_manager_translator_m0_awid;                                               // niosv_g_instruction_manager_translator:m0_awid -> niosv_g_instruction_manager_agent:awid
	wire    [0:0] niosv_g_instruction_manager_translator_m0_bid;                                                // niosv_g_instruction_manager_agent:bid -> niosv_g_instruction_manager_translator:m0_bid
	wire          niosv_g_instruction_manager_translator_m0_bvalid;                                             // niosv_g_instruction_manager_agent:bvalid -> niosv_g_instruction_manager_translator:m0_bvalid
	wire    [2:0] niosv_g_instruction_manager_translator_m0_awsize;                                             // niosv_g_instruction_manager_translator:m0_awsize -> niosv_g_instruction_manager_agent:awsize
	wire          niosv_g_instruction_manager_translator_m0_awvalid;                                            // niosv_g_instruction_manager_translator:m0_awvalid -> niosv_g_instruction_manager_agent:awvalid
	wire    [0:0] niosv_g_instruction_manager_translator_m0_aruser;                                             // niosv_g_instruction_manager_translator:m0_aruser -> niosv_g_instruction_manager_agent:aruser
	wire          niosv_g_instruction_manager_translator_m0_rvalid;                                             // niosv_g_instruction_manager_agent:rvalid -> niosv_g_instruction_manager_translator:m0_rvalid
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_ruser;                                               // sdram_axi4_slave_translator:s0_ruser -> sdram_axi4_slave_agent:ruser
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_wuser;                                               // sdram_axi4_slave_agent:wuser -> sdram_axi4_slave_translator:s0_wuser
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_awburst;                                             // sdram_axi4_slave_agent:awburst -> sdram_axi4_slave_translator:s0_awburst
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arregion;                                            // sdram_axi4_slave_agent:arregion -> sdram_axi4_slave_translator:s0_arregion
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_awuser;                                              // sdram_axi4_slave_agent:awuser -> sdram_axi4_slave_translator:s0_awuser
	wire    [7:0] sdram_axi4_slave_agent_altera_axi_master_arlen;                                               // sdram_axi4_slave_agent:arlen -> sdram_axi4_slave_translator:s0_arlen
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arqos;                                               // sdram_axi4_slave_agent:arqos -> sdram_axi4_slave_translator:s0_arqos
	wire    [7:0] sdram_axi4_slave_agent_altera_axi_master_wstrb;                                               // sdram_axi4_slave_agent:wstrb -> sdram_axi4_slave_translator:s0_wstrb
	wire          sdram_axi4_slave_agent_altera_axi_master_wready;                                              // sdram_axi4_slave_translator:s0_wready -> sdram_axi4_slave_agent:wready
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_rid;                                                 // sdram_axi4_slave_translator:s0_rid -> sdram_axi4_slave_agent:rid
	wire          sdram_axi4_slave_agent_altera_axi_master_rready;                                              // sdram_axi4_slave_agent:rready -> sdram_axi4_slave_translator:s0_rready
	wire    [7:0] sdram_axi4_slave_agent_altera_axi_master_awlen;                                               // sdram_axi4_slave_agent:awlen -> sdram_axi4_slave_translator:s0_awlen
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awqos;                                               // sdram_axi4_slave_agent:awqos -> sdram_axi4_slave_translator:s0_awqos
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arcache;                                             // sdram_axi4_slave_agent:arcache -> sdram_axi4_slave_translator:s0_arcache
	wire          sdram_axi4_slave_agent_altera_axi_master_wvalid;                                              // sdram_axi4_slave_agent:wvalid -> sdram_axi4_slave_translator:s0_wvalid
	wire   [25:0] sdram_axi4_slave_agent_altera_axi_master_araddr;                                              // sdram_axi4_slave_agent:araddr -> sdram_axi4_slave_translator:s0_araddr
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_arprot;                                              // sdram_axi4_slave_agent:arprot -> sdram_axi4_slave_translator:s0_arprot
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_awprot;                                              // sdram_axi4_slave_agent:awprot -> sdram_axi4_slave_translator:s0_awprot
	wire   [63:0] sdram_axi4_slave_agent_altera_axi_master_wdata;                                               // sdram_axi4_slave_agent:wdata -> sdram_axi4_slave_translator:s0_wdata
	wire          sdram_axi4_slave_agent_altera_axi_master_arvalid;                                             // sdram_axi4_slave_agent:arvalid -> sdram_axi4_slave_translator:s0_arvalid
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awcache;                                             // sdram_axi4_slave_agent:awcache -> sdram_axi4_slave_translator:s0_awcache
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_arid;                                                // sdram_axi4_slave_agent:arid -> sdram_axi4_slave_translator:s0_arid
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_arlock;                                              // sdram_axi4_slave_agent:arlock -> sdram_axi4_slave_translator:s0_arlock
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_awlock;                                              // sdram_axi4_slave_agent:awlock -> sdram_axi4_slave_translator:s0_awlock
	wire   [25:0] sdram_axi4_slave_agent_altera_axi_master_awaddr;                                              // sdram_axi4_slave_agent:awaddr -> sdram_axi4_slave_translator:s0_awaddr
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_bresp;                                               // sdram_axi4_slave_translator:s0_bresp -> sdram_axi4_slave_agent:bresp
	wire          sdram_axi4_slave_agent_altera_axi_master_arready;                                             // sdram_axi4_slave_translator:s0_arready -> sdram_axi4_slave_agent:arready
	wire   [63:0] sdram_axi4_slave_agent_altera_axi_master_rdata;                                               // sdram_axi4_slave_translator:s0_rdata -> sdram_axi4_slave_agent:rdata
	wire          sdram_axi4_slave_agent_altera_axi_master_awready;                                             // sdram_axi4_slave_translator:s0_awready -> sdram_axi4_slave_agent:awready
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_arburst;                                             // sdram_axi4_slave_agent:arburst -> sdram_axi4_slave_translator:s0_arburst
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_arsize;                                              // sdram_axi4_slave_agent:arsize -> sdram_axi4_slave_translator:s0_arsize
	wire          sdram_axi4_slave_agent_altera_axi_master_bready;                                              // sdram_axi4_slave_agent:bready -> sdram_axi4_slave_translator:s0_bready
	wire          sdram_axi4_slave_agent_altera_axi_master_rlast;                                               // sdram_axi4_slave_translator:s0_rlast -> sdram_axi4_slave_agent:rlast
	wire          sdram_axi4_slave_agent_altera_axi_master_wlast;                                               // sdram_axi4_slave_agent:wlast -> sdram_axi4_slave_translator:s0_wlast
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awregion;                                            // sdram_axi4_slave_agent:awregion -> sdram_axi4_slave_translator:s0_awregion
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_buser;                                               // sdram_axi4_slave_translator:s0_buser -> sdram_axi4_slave_agent:buser
	wire    [1:0] sdram_axi4_slave_agent_altera_axi_master_rresp;                                               // sdram_axi4_slave_translator:s0_rresp -> sdram_axi4_slave_agent:rresp
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_awid;                                                // sdram_axi4_slave_agent:awid -> sdram_axi4_slave_translator:s0_awid
	wire    [3:0] sdram_axi4_slave_agent_altera_axi_master_bid;                                                 // sdram_axi4_slave_translator:s0_bid -> sdram_axi4_slave_agent:bid
	wire          sdram_axi4_slave_agent_altera_axi_master_bvalid;                                              // sdram_axi4_slave_translator:s0_bvalid -> sdram_axi4_slave_agent:bvalid
	wire    [2:0] sdram_axi4_slave_agent_altera_axi_master_awsize;                                              // sdram_axi4_slave_agent:awsize -> sdram_axi4_slave_translator:s0_awsize
	wire          sdram_axi4_slave_agent_altera_axi_master_awvalid;                                             // sdram_axi4_slave_agent:awvalid -> sdram_axi4_slave_translator:s0_awvalid
	wire    [0:0] sdram_axi4_slave_agent_altera_axi_master_aruser;                                              // sdram_axi4_slave_agent:aruser -> sdram_axi4_slave_translator:s0_aruser
	wire          sdram_axi4_slave_agent_altera_axi_master_rvalid;                                              // sdram_axi4_slave_translator:s0_rvalid -> sdram_axi4_slave_agent:rvalid
	wire          cmd_mux_src_valid;                                                                            // cmd_mux:src_valid -> sdram_axi4_slave_agent:write_cp_valid
	wire  [189:0] cmd_mux_src_data;                                                                             // cmd_mux:src_data -> sdram_axi4_slave_agent:write_cp_data
	wire          cmd_mux_src_ready;                                                                            // sdram_axi4_slave_agent:write_cp_ready -> cmd_mux:src_ready
	wire    [5:0] cmd_mux_src_channel;                                                                          // cmd_mux:src_channel -> sdram_axi4_slave_agent:write_cp_channel
	wire          cmd_mux_src_startofpacket;                                                                    // cmd_mux:src_startofpacket -> sdram_axi4_slave_agent:write_cp_startofpacket
	wire          cmd_mux_src_endofpacket;                                                                      // cmd_mux:src_endofpacket -> sdram_axi4_slave_agent:write_cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                                        // cmd_mux_001:src_valid -> sdram_axi4_slave_agent:read_cp_valid
	wire  [189:0] cmd_mux_001_src_data;                                                                         // cmd_mux_001:src_data -> sdram_axi4_slave_agent:read_cp_data
	wire          cmd_mux_001_src_ready;                                                                        // sdram_axi4_slave_agent:read_cp_ready -> cmd_mux_001:src_ready
	wire    [5:0] cmd_mux_001_src_channel;                                                                      // cmd_mux_001:src_channel -> sdram_axi4_slave_agent:read_cp_channel
	wire          cmd_mux_001_src_startofpacket;                                                                // cmd_mux_001:src_startofpacket -> sdram_axi4_slave_agent:read_cp_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                                  // cmd_mux_001:src_endofpacket -> sdram_axi4_slave_agent:read_cp_endofpacket
	wire   [31:0] niosv_g_dm_agent_agent_m0_readdata;                                                           // niosv_g_dm_agent_translator:uav_readdata -> niosv_g_dm_agent_agent:m0_readdata
	wire          niosv_g_dm_agent_agent_m0_waitrequest;                                                        // niosv_g_dm_agent_translator:uav_waitrequest -> niosv_g_dm_agent_agent:m0_waitrequest
	wire          niosv_g_dm_agent_agent_m0_debugaccess;                                                        // niosv_g_dm_agent_agent:m0_debugaccess -> niosv_g_dm_agent_translator:uav_debugaccess
	wire   [31:0] niosv_g_dm_agent_agent_m0_address;                                                            // niosv_g_dm_agent_agent:m0_address -> niosv_g_dm_agent_translator:uav_address
	wire    [3:0] niosv_g_dm_agent_agent_m0_byteenable;                                                         // niosv_g_dm_agent_agent:m0_byteenable -> niosv_g_dm_agent_translator:uav_byteenable
	wire          niosv_g_dm_agent_agent_m0_read;                                                               // niosv_g_dm_agent_agent:m0_read -> niosv_g_dm_agent_translator:uav_read
	wire          niosv_g_dm_agent_agent_m0_readdatavalid;                                                      // niosv_g_dm_agent_translator:uav_readdatavalid -> niosv_g_dm_agent_agent:m0_readdatavalid
	wire          niosv_g_dm_agent_agent_m0_lock;                                                               // niosv_g_dm_agent_agent:m0_lock -> niosv_g_dm_agent_translator:uav_lock
	wire   [31:0] niosv_g_dm_agent_agent_m0_writedata;                                                          // niosv_g_dm_agent_agent:m0_writedata -> niosv_g_dm_agent_translator:uav_writedata
	wire          niosv_g_dm_agent_agent_m0_write;                                                              // niosv_g_dm_agent_agent:m0_write -> niosv_g_dm_agent_translator:uav_write
	wire    [2:0] niosv_g_dm_agent_agent_m0_burstcount;                                                         // niosv_g_dm_agent_agent:m0_burstcount -> niosv_g_dm_agent_translator:uav_burstcount
	wire          niosv_g_dm_agent_agent_rf_source_valid;                                                       // niosv_g_dm_agent_agent:rf_source_valid -> niosv_g_dm_agent_agent_rsp_fifo:in_valid
	wire  [154:0] niosv_g_dm_agent_agent_rf_source_data;                                                        // niosv_g_dm_agent_agent:rf_source_data -> niosv_g_dm_agent_agent_rsp_fifo:in_data
	wire          niosv_g_dm_agent_agent_rf_source_ready;                                                       // niosv_g_dm_agent_agent_rsp_fifo:in_ready -> niosv_g_dm_agent_agent:rf_source_ready
	wire          niosv_g_dm_agent_agent_rf_source_startofpacket;                                               // niosv_g_dm_agent_agent:rf_source_startofpacket -> niosv_g_dm_agent_agent_rsp_fifo:in_startofpacket
	wire          niosv_g_dm_agent_agent_rf_source_endofpacket;                                                 // niosv_g_dm_agent_agent:rf_source_endofpacket -> niosv_g_dm_agent_agent_rsp_fifo:in_endofpacket
	wire          niosv_g_dm_agent_agent_rsp_fifo_out_valid;                                                    // niosv_g_dm_agent_agent_rsp_fifo:out_valid -> niosv_g_dm_agent_agent:rf_sink_valid
	wire  [154:0] niosv_g_dm_agent_agent_rsp_fifo_out_data;                                                     // niosv_g_dm_agent_agent_rsp_fifo:out_data -> niosv_g_dm_agent_agent:rf_sink_data
	wire          niosv_g_dm_agent_agent_rsp_fifo_out_ready;                                                    // niosv_g_dm_agent_agent:rf_sink_ready -> niosv_g_dm_agent_agent_rsp_fifo:out_ready
	wire          niosv_g_dm_agent_agent_rsp_fifo_out_startofpacket;                                            // niosv_g_dm_agent_agent_rsp_fifo:out_startofpacket -> niosv_g_dm_agent_agent:rf_sink_startofpacket
	wire          niosv_g_dm_agent_agent_rsp_fifo_out_endofpacket;                                              // niosv_g_dm_agent_agent_rsp_fifo:out_endofpacket -> niosv_g_dm_agent_agent:rf_sink_endofpacket
	wire          niosv_g_dm_agent_agent_rdata_fifo_src_valid;                                                  // niosv_g_dm_agent_agent:rdata_fifo_src_valid -> niosv_g_dm_agent_agent_rdata_fifo:in_valid
	wire   [33:0] niosv_g_dm_agent_agent_rdata_fifo_src_data;                                                   // niosv_g_dm_agent_agent:rdata_fifo_src_data -> niosv_g_dm_agent_agent_rdata_fifo:in_data
	wire          niosv_g_dm_agent_agent_rdata_fifo_src_ready;                                                  // niosv_g_dm_agent_agent_rdata_fifo:in_ready -> niosv_g_dm_agent_agent:rdata_fifo_src_ready
	wire          niosv_g_dm_agent_agent_rdata_fifo_out_valid;                                                  // niosv_g_dm_agent_agent_rdata_fifo:out_valid -> niosv_g_dm_agent_agent:rdata_fifo_sink_valid
	wire   [33:0] niosv_g_dm_agent_agent_rdata_fifo_out_data;                                                   // niosv_g_dm_agent_agent_rdata_fifo:out_data -> niosv_g_dm_agent_agent:rdata_fifo_sink_data
	wire          niosv_g_dm_agent_agent_rdata_fifo_out_ready;                                                  // niosv_g_dm_agent_agent:rdata_fifo_sink_ready -> niosv_g_dm_agent_agent_rdata_fifo:out_ready
	wire   [31:0] mm_bridge_peripheral_s0_agent_m0_readdata;                                                    // mm_bridge_peripheral_s0_translator:uav_readdata -> mm_bridge_peripheral_s0_agent:m0_readdata
	wire          mm_bridge_peripheral_s0_agent_m0_waitrequest;                                                 // mm_bridge_peripheral_s0_translator:uav_waitrequest -> mm_bridge_peripheral_s0_agent:m0_waitrequest
	wire          mm_bridge_peripheral_s0_agent_m0_debugaccess;                                                 // mm_bridge_peripheral_s0_agent:m0_debugaccess -> mm_bridge_peripheral_s0_translator:uav_debugaccess
	wire   [31:0] mm_bridge_peripheral_s0_agent_m0_address;                                                     // mm_bridge_peripheral_s0_agent:m0_address -> mm_bridge_peripheral_s0_translator:uav_address
	wire    [3:0] mm_bridge_peripheral_s0_agent_m0_byteenable;                                                  // mm_bridge_peripheral_s0_agent:m0_byteenable -> mm_bridge_peripheral_s0_translator:uav_byteenable
	wire          mm_bridge_peripheral_s0_agent_m0_read;                                                        // mm_bridge_peripheral_s0_agent:m0_read -> mm_bridge_peripheral_s0_translator:uav_read
	wire          mm_bridge_peripheral_s0_agent_m0_readdatavalid;                                               // mm_bridge_peripheral_s0_translator:uav_readdatavalid -> mm_bridge_peripheral_s0_agent:m0_readdatavalid
	wire          mm_bridge_peripheral_s0_agent_m0_lock;                                                        // mm_bridge_peripheral_s0_agent:m0_lock -> mm_bridge_peripheral_s0_translator:uav_lock
	wire   [31:0] mm_bridge_peripheral_s0_agent_m0_writedata;                                                   // mm_bridge_peripheral_s0_agent:m0_writedata -> mm_bridge_peripheral_s0_translator:uav_writedata
	wire          mm_bridge_peripheral_s0_agent_m0_write;                                                       // mm_bridge_peripheral_s0_agent:m0_write -> mm_bridge_peripheral_s0_translator:uav_write
	wire    [2:0] mm_bridge_peripheral_s0_agent_m0_burstcount;                                                  // mm_bridge_peripheral_s0_agent:m0_burstcount -> mm_bridge_peripheral_s0_translator:uav_burstcount
	wire          mm_bridge_peripheral_s0_agent_rf_source_valid;                                                // mm_bridge_peripheral_s0_agent:rf_source_valid -> mm_bridge_peripheral_s0_agent_rsp_fifo:in_valid
	wire  [154:0] mm_bridge_peripheral_s0_agent_rf_source_data;                                                 // mm_bridge_peripheral_s0_agent:rf_source_data -> mm_bridge_peripheral_s0_agent_rsp_fifo:in_data
	wire          mm_bridge_peripheral_s0_agent_rf_source_ready;                                                // mm_bridge_peripheral_s0_agent_rsp_fifo:in_ready -> mm_bridge_peripheral_s0_agent:rf_source_ready
	wire          mm_bridge_peripheral_s0_agent_rf_source_startofpacket;                                        // mm_bridge_peripheral_s0_agent:rf_source_startofpacket -> mm_bridge_peripheral_s0_agent_rsp_fifo:in_startofpacket
	wire          mm_bridge_peripheral_s0_agent_rf_source_endofpacket;                                          // mm_bridge_peripheral_s0_agent:rf_source_endofpacket -> mm_bridge_peripheral_s0_agent_rsp_fifo:in_endofpacket
	wire          mm_bridge_peripheral_s0_agent_rsp_fifo_out_valid;                                             // mm_bridge_peripheral_s0_agent_rsp_fifo:out_valid -> mm_bridge_peripheral_s0_agent:rf_sink_valid
	wire  [154:0] mm_bridge_peripheral_s0_agent_rsp_fifo_out_data;                                              // mm_bridge_peripheral_s0_agent_rsp_fifo:out_data -> mm_bridge_peripheral_s0_agent:rf_sink_data
	wire          mm_bridge_peripheral_s0_agent_rsp_fifo_out_ready;                                             // mm_bridge_peripheral_s0_agent:rf_sink_ready -> mm_bridge_peripheral_s0_agent_rsp_fifo:out_ready
	wire          mm_bridge_peripheral_s0_agent_rsp_fifo_out_startofpacket;                                     // mm_bridge_peripheral_s0_agent_rsp_fifo:out_startofpacket -> mm_bridge_peripheral_s0_agent:rf_sink_startofpacket
	wire          mm_bridge_peripheral_s0_agent_rsp_fifo_out_endofpacket;                                       // mm_bridge_peripheral_s0_agent_rsp_fifo:out_endofpacket -> mm_bridge_peripheral_s0_agent:rf_sink_endofpacket
	wire          mm_bridge_peripheral_s0_agent_rdata_fifo_src_valid;                                           // mm_bridge_peripheral_s0_agent:rdata_fifo_src_valid -> mm_bridge_peripheral_s0_agent_rdata_fifo:in_valid
	wire   [33:0] mm_bridge_peripheral_s0_agent_rdata_fifo_src_data;                                            // mm_bridge_peripheral_s0_agent:rdata_fifo_src_data -> mm_bridge_peripheral_s0_agent_rdata_fifo:in_data
	wire          mm_bridge_peripheral_s0_agent_rdata_fifo_src_ready;                                           // mm_bridge_peripheral_s0_agent_rdata_fifo:in_ready -> mm_bridge_peripheral_s0_agent:rdata_fifo_src_ready
	wire          mm_bridge_peripheral_s0_agent_rdata_fifo_out_valid;                                           // mm_bridge_peripheral_s0_agent_rdata_fifo:out_valid -> mm_bridge_peripheral_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] mm_bridge_peripheral_s0_agent_rdata_fifo_out_data;                                            // mm_bridge_peripheral_s0_agent_rdata_fifo:out_data -> mm_bridge_peripheral_s0_agent:rdata_fifo_sink_data
	wire          mm_bridge_peripheral_s0_agent_rdata_fifo_out_ready;                                           // mm_bridge_peripheral_s0_agent:rdata_fifo_sink_ready -> mm_bridge_peripheral_s0_agent_rdata_fifo:out_ready
	wire   [31:0] onchip_memory_s1_agent_m0_readdata;                                                           // onchip_memory_s1_translator:uav_readdata -> onchip_memory_s1_agent:m0_readdata
	wire          onchip_memory_s1_agent_m0_waitrequest;                                                        // onchip_memory_s1_translator:uav_waitrequest -> onchip_memory_s1_agent:m0_waitrequest
	wire          onchip_memory_s1_agent_m0_debugaccess;                                                        // onchip_memory_s1_agent:m0_debugaccess -> onchip_memory_s1_translator:uav_debugaccess
	wire   [31:0] onchip_memory_s1_agent_m0_address;                                                            // onchip_memory_s1_agent:m0_address -> onchip_memory_s1_translator:uav_address
	wire    [3:0] onchip_memory_s1_agent_m0_byteenable;                                                         // onchip_memory_s1_agent:m0_byteenable -> onchip_memory_s1_translator:uav_byteenable
	wire          onchip_memory_s1_agent_m0_read;                                                               // onchip_memory_s1_agent:m0_read -> onchip_memory_s1_translator:uav_read
	wire          onchip_memory_s1_agent_m0_readdatavalid;                                                      // onchip_memory_s1_translator:uav_readdatavalid -> onchip_memory_s1_agent:m0_readdatavalid
	wire          onchip_memory_s1_agent_m0_lock;                                                               // onchip_memory_s1_agent:m0_lock -> onchip_memory_s1_translator:uav_lock
	wire   [31:0] onchip_memory_s1_agent_m0_writedata;                                                          // onchip_memory_s1_agent:m0_writedata -> onchip_memory_s1_translator:uav_writedata
	wire          onchip_memory_s1_agent_m0_write;                                                              // onchip_memory_s1_agent:m0_write -> onchip_memory_s1_translator:uav_write
	wire    [2:0] onchip_memory_s1_agent_m0_burstcount;                                                         // onchip_memory_s1_agent:m0_burstcount -> onchip_memory_s1_translator:uav_burstcount
	wire          onchip_memory_s1_agent_rf_source_valid;                                                       // onchip_memory_s1_agent:rf_source_valid -> onchip_memory_s1_agent_rsp_fifo:in_valid
	wire  [154:0] onchip_memory_s1_agent_rf_source_data;                                                        // onchip_memory_s1_agent:rf_source_data -> onchip_memory_s1_agent_rsp_fifo:in_data
	wire          onchip_memory_s1_agent_rf_source_ready;                                                       // onchip_memory_s1_agent_rsp_fifo:in_ready -> onchip_memory_s1_agent:rf_source_ready
	wire          onchip_memory_s1_agent_rf_source_startofpacket;                                               // onchip_memory_s1_agent:rf_source_startofpacket -> onchip_memory_s1_agent_rsp_fifo:in_startofpacket
	wire          onchip_memory_s1_agent_rf_source_endofpacket;                                                 // onchip_memory_s1_agent:rf_source_endofpacket -> onchip_memory_s1_agent_rsp_fifo:in_endofpacket
	wire          onchip_memory_s1_agent_rsp_fifo_out_valid;                                                    // onchip_memory_s1_agent_rsp_fifo:out_valid -> onchip_memory_s1_agent:rf_sink_valid
	wire  [154:0] onchip_memory_s1_agent_rsp_fifo_out_data;                                                     // onchip_memory_s1_agent_rsp_fifo:out_data -> onchip_memory_s1_agent:rf_sink_data
	wire          onchip_memory_s1_agent_rsp_fifo_out_ready;                                                    // onchip_memory_s1_agent:rf_sink_ready -> onchip_memory_s1_agent_rsp_fifo:out_ready
	wire          onchip_memory_s1_agent_rsp_fifo_out_startofpacket;                                            // onchip_memory_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory_s1_agent:rf_sink_startofpacket
	wire          onchip_memory_s1_agent_rsp_fifo_out_endofpacket;                                              // onchip_memory_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory_s1_agent:rf_sink_endofpacket
	wire          onchip_memory_s1_agent_rdata_fifo_src_valid;                                                  // onchip_memory_s1_agent:rdata_fifo_src_valid -> onchip_memory_s1_agent_rdata_fifo:in_valid
	wire   [33:0] onchip_memory_s1_agent_rdata_fifo_src_data;                                                   // onchip_memory_s1_agent:rdata_fifo_src_data -> onchip_memory_s1_agent_rdata_fifo:in_data
	wire          onchip_memory_s1_agent_rdata_fifo_src_ready;                                                  // onchip_memory_s1_agent_rdata_fifo:in_ready -> onchip_memory_s1_agent:rdata_fifo_src_ready
	wire          onchip_memory_s1_agent_rdata_fifo_out_valid;                                                  // onchip_memory_s1_agent_rdata_fifo:out_valid -> onchip_memory_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] onchip_memory_s1_agent_rdata_fifo_out_data;                                                   // onchip_memory_s1_agent_rdata_fifo:out_data -> onchip_memory_s1_agent:rdata_fifo_sink_data
	wire          onchip_memory_s1_agent_rdata_fifo_out_ready;                                                  // onchip_memory_s1_agent:rdata_fifo_sink_ready -> onchip_memory_s1_agent_rdata_fifo:out_ready
	wire   [31:0] niosv_g_timer_sw_agent_agent_m0_readdata;                                                     // niosv_g_timer_sw_agent_translator:uav_readdata -> niosv_g_timer_sw_agent_agent:m0_readdata
	wire          niosv_g_timer_sw_agent_agent_m0_waitrequest;                                                  // niosv_g_timer_sw_agent_translator:uav_waitrequest -> niosv_g_timer_sw_agent_agent:m0_waitrequest
	wire          niosv_g_timer_sw_agent_agent_m0_debugaccess;                                                  // niosv_g_timer_sw_agent_agent:m0_debugaccess -> niosv_g_timer_sw_agent_translator:uav_debugaccess
	wire   [31:0] niosv_g_timer_sw_agent_agent_m0_address;                                                      // niosv_g_timer_sw_agent_agent:m0_address -> niosv_g_timer_sw_agent_translator:uav_address
	wire    [3:0] niosv_g_timer_sw_agent_agent_m0_byteenable;                                                   // niosv_g_timer_sw_agent_agent:m0_byteenable -> niosv_g_timer_sw_agent_translator:uav_byteenable
	wire          niosv_g_timer_sw_agent_agent_m0_read;                                                         // niosv_g_timer_sw_agent_agent:m0_read -> niosv_g_timer_sw_agent_translator:uav_read
	wire          niosv_g_timer_sw_agent_agent_m0_readdatavalid;                                                // niosv_g_timer_sw_agent_translator:uav_readdatavalid -> niosv_g_timer_sw_agent_agent:m0_readdatavalid
	wire          niosv_g_timer_sw_agent_agent_m0_lock;                                                         // niosv_g_timer_sw_agent_agent:m0_lock -> niosv_g_timer_sw_agent_translator:uav_lock
	wire   [31:0] niosv_g_timer_sw_agent_agent_m0_writedata;                                                    // niosv_g_timer_sw_agent_agent:m0_writedata -> niosv_g_timer_sw_agent_translator:uav_writedata
	wire          niosv_g_timer_sw_agent_agent_m0_write;                                                        // niosv_g_timer_sw_agent_agent:m0_write -> niosv_g_timer_sw_agent_translator:uav_write
	wire    [2:0] niosv_g_timer_sw_agent_agent_m0_burstcount;                                                   // niosv_g_timer_sw_agent_agent:m0_burstcount -> niosv_g_timer_sw_agent_translator:uav_burstcount
	wire          niosv_g_timer_sw_agent_agent_rf_source_valid;                                                 // niosv_g_timer_sw_agent_agent:rf_source_valid -> niosv_g_timer_sw_agent_agent_rsp_fifo:in_valid
	wire  [154:0] niosv_g_timer_sw_agent_agent_rf_source_data;                                                  // niosv_g_timer_sw_agent_agent:rf_source_data -> niosv_g_timer_sw_agent_agent_rsp_fifo:in_data
	wire          niosv_g_timer_sw_agent_agent_rf_source_ready;                                                 // niosv_g_timer_sw_agent_agent_rsp_fifo:in_ready -> niosv_g_timer_sw_agent_agent:rf_source_ready
	wire          niosv_g_timer_sw_agent_agent_rf_source_startofpacket;                                         // niosv_g_timer_sw_agent_agent:rf_source_startofpacket -> niosv_g_timer_sw_agent_agent_rsp_fifo:in_startofpacket
	wire          niosv_g_timer_sw_agent_agent_rf_source_endofpacket;                                           // niosv_g_timer_sw_agent_agent:rf_source_endofpacket -> niosv_g_timer_sw_agent_agent_rsp_fifo:in_endofpacket
	wire          niosv_g_timer_sw_agent_agent_rsp_fifo_out_valid;                                              // niosv_g_timer_sw_agent_agent_rsp_fifo:out_valid -> niosv_g_timer_sw_agent_agent:rf_sink_valid
	wire  [154:0] niosv_g_timer_sw_agent_agent_rsp_fifo_out_data;                                               // niosv_g_timer_sw_agent_agent_rsp_fifo:out_data -> niosv_g_timer_sw_agent_agent:rf_sink_data
	wire          niosv_g_timer_sw_agent_agent_rsp_fifo_out_ready;                                              // niosv_g_timer_sw_agent_agent:rf_sink_ready -> niosv_g_timer_sw_agent_agent_rsp_fifo:out_ready
	wire          niosv_g_timer_sw_agent_agent_rsp_fifo_out_startofpacket;                                      // niosv_g_timer_sw_agent_agent_rsp_fifo:out_startofpacket -> niosv_g_timer_sw_agent_agent:rf_sink_startofpacket
	wire          niosv_g_timer_sw_agent_agent_rsp_fifo_out_endofpacket;                                        // niosv_g_timer_sw_agent_agent_rsp_fifo:out_endofpacket -> niosv_g_timer_sw_agent_agent:rf_sink_endofpacket
	wire          niosv_g_timer_sw_agent_agent_rdata_fifo_src_valid;                                            // niosv_g_timer_sw_agent_agent:rdata_fifo_src_valid -> niosv_g_timer_sw_agent_agent_rdata_fifo:in_valid
	wire   [33:0] niosv_g_timer_sw_agent_agent_rdata_fifo_src_data;                                             // niosv_g_timer_sw_agent_agent:rdata_fifo_src_data -> niosv_g_timer_sw_agent_agent_rdata_fifo:in_data
	wire          niosv_g_timer_sw_agent_agent_rdata_fifo_src_ready;                                            // niosv_g_timer_sw_agent_agent_rdata_fifo:in_ready -> niosv_g_timer_sw_agent_agent:rdata_fifo_src_ready
	wire          niosv_g_timer_sw_agent_agent_rdata_fifo_out_valid;                                            // niosv_g_timer_sw_agent_agent_rdata_fifo:out_valid -> niosv_g_timer_sw_agent_agent:rdata_fifo_sink_valid
	wire   [33:0] niosv_g_timer_sw_agent_agent_rdata_fifo_out_data;                                             // niosv_g_timer_sw_agent_agent_rdata_fifo:out_data -> niosv_g_timer_sw_agent_agent:rdata_fifo_sink_data
	wire          niosv_g_timer_sw_agent_agent_rdata_fifo_out_ready;                                            // niosv_g_timer_sw_agent_agent:rdata_fifo_sink_ready -> niosv_g_timer_sw_agent_agent_rdata_fifo:out_ready
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_valid;                                             // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_valid -> router:sink_valid
	wire  [405:0] intel_vvp_vfr_av_mm_mem_read_host_agent_cp_data;                                              // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_data -> router:sink_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_ready;                                             // router:sink_ready -> intel_vvp_vfr_av_mm_mem_read_host_agent:cp_ready
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_startofpacket;                                     // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_startofpacket -> router:sink_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_agent_cp_endofpacket;                                       // intel_vvp_vfr_av_mm_mem_read_host_agent:cp_endofpacket -> router:sink_endofpacket
	wire          niosv_g_data_manager_agent_write_cp_valid;                                                    // niosv_g_data_manager_agent:write_cp_valid -> router_001:sink_valid
	wire  [153:0] niosv_g_data_manager_agent_write_cp_data;                                                     // niosv_g_data_manager_agent:write_cp_data -> router_001:sink_data
	wire          niosv_g_data_manager_agent_write_cp_ready;                                                    // router_001:sink_ready -> niosv_g_data_manager_agent:write_cp_ready
	wire          niosv_g_data_manager_agent_write_cp_startofpacket;                                            // niosv_g_data_manager_agent:write_cp_startofpacket -> router_001:sink_startofpacket
	wire          niosv_g_data_manager_agent_write_cp_endofpacket;                                              // niosv_g_data_manager_agent:write_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                                         // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [153:0] router_001_src_data;                                                                          // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                                         // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [5:0] router_001_src_channel;                                                                       // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                                                 // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                                   // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          niosv_g_data_manager_agent_read_cp_valid;                                                     // niosv_g_data_manager_agent:read_cp_valid -> router_002:sink_valid
	wire  [153:0] niosv_g_data_manager_agent_read_cp_data;                                                      // niosv_g_data_manager_agent:read_cp_data -> router_002:sink_data
	wire          niosv_g_data_manager_agent_read_cp_ready;                                                     // router_002:sink_ready -> niosv_g_data_manager_agent:read_cp_ready
	wire          niosv_g_data_manager_agent_read_cp_startofpacket;                                             // niosv_g_data_manager_agent:read_cp_startofpacket -> router_002:sink_startofpacket
	wire          niosv_g_data_manager_agent_read_cp_endofpacket;                                               // niosv_g_data_manager_agent:read_cp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                                         // router_002:src_valid -> cmd_demux_002:sink_valid
	wire  [153:0] router_002_src_data;                                                                          // router_002:src_data -> cmd_demux_002:sink_data
	wire          router_002_src_ready;                                                                         // cmd_demux_002:sink_ready -> router_002:src_ready
	wire    [5:0] router_002_src_channel;                                                                       // router_002:src_channel -> cmd_demux_002:sink_channel
	wire          router_002_src_startofpacket;                                                                 // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          router_002_src_endofpacket;                                                                   // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          niosv_g_instruction_manager_agent_write_cp_valid;                                             // niosv_g_instruction_manager_agent:write_cp_valid -> router_003:sink_valid
	wire  [153:0] niosv_g_instruction_manager_agent_write_cp_data;                                              // niosv_g_instruction_manager_agent:write_cp_data -> router_003:sink_data
	wire          niosv_g_instruction_manager_agent_write_cp_ready;                                             // router_003:sink_ready -> niosv_g_instruction_manager_agent:write_cp_ready
	wire          niosv_g_instruction_manager_agent_write_cp_startofpacket;                                     // niosv_g_instruction_manager_agent:write_cp_startofpacket -> router_003:sink_startofpacket
	wire          niosv_g_instruction_manager_agent_write_cp_endofpacket;                                       // niosv_g_instruction_manager_agent:write_cp_endofpacket -> router_003:sink_endofpacket
	wire          niosv_g_instruction_manager_agent_read_cp_valid;                                              // niosv_g_instruction_manager_agent:read_cp_valid -> router_004:sink_valid
	wire  [153:0] niosv_g_instruction_manager_agent_read_cp_data;                                               // niosv_g_instruction_manager_agent:read_cp_data -> router_004:sink_data
	wire          niosv_g_instruction_manager_agent_read_cp_ready;                                              // router_004:sink_ready -> niosv_g_instruction_manager_agent:read_cp_ready
	wire          niosv_g_instruction_manager_agent_read_cp_startofpacket;                                      // niosv_g_instruction_manager_agent:read_cp_startofpacket -> router_004:sink_startofpacket
	wire          niosv_g_instruction_manager_agent_read_cp_endofpacket;                                        // niosv_g_instruction_manager_agent:read_cp_endofpacket -> router_004:sink_endofpacket
	wire          sdram_axi4_slave_agent_write_rp_valid;                                                        // sdram_axi4_slave_agent:write_rp_valid -> router_005:sink_valid
	wire  [189:0] sdram_axi4_slave_agent_write_rp_data;                                                         // sdram_axi4_slave_agent:write_rp_data -> router_005:sink_data
	wire          sdram_axi4_slave_agent_write_rp_ready;                                                        // router_005:sink_ready -> sdram_axi4_slave_agent:write_rp_ready
	wire          sdram_axi4_slave_agent_write_rp_startofpacket;                                                // sdram_axi4_slave_agent:write_rp_startofpacket -> router_005:sink_startofpacket
	wire          sdram_axi4_slave_agent_write_rp_endofpacket;                                                  // sdram_axi4_slave_agent:write_rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                                         // router_005:src_valid -> rsp_demux:sink_valid
	wire  [189:0] router_005_src_data;                                                                          // router_005:src_data -> rsp_demux:sink_data
	wire          router_005_src_ready;                                                                         // rsp_demux:sink_ready -> router_005:src_ready
	wire    [5:0] router_005_src_channel;                                                                       // router_005:src_channel -> rsp_demux:sink_channel
	wire          router_005_src_startofpacket;                                                                 // router_005:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_005_src_endofpacket;                                                                   // router_005:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          sdram_axi4_slave_agent_read_rp_valid;                                                         // sdram_axi4_slave_agent:read_rp_valid -> router_006:sink_valid
	wire  [189:0] sdram_axi4_slave_agent_read_rp_data;                                                          // sdram_axi4_slave_agent:read_rp_data -> router_006:sink_data
	wire          sdram_axi4_slave_agent_read_rp_ready;                                                         // router_006:sink_ready -> sdram_axi4_slave_agent:read_rp_ready
	wire          sdram_axi4_slave_agent_read_rp_startofpacket;                                                 // sdram_axi4_slave_agent:read_rp_startofpacket -> router_006:sink_startofpacket
	wire          sdram_axi4_slave_agent_read_rp_endofpacket;                                                   // sdram_axi4_slave_agent:read_rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                                         // router_006:src_valid -> rsp_demux_001:sink_valid
	wire  [189:0] router_006_src_data;                                                                          // router_006:src_data -> rsp_demux_001:sink_data
	wire          router_006_src_ready;                                                                         // rsp_demux_001:sink_ready -> router_006:src_ready
	wire    [5:0] router_006_src_channel;                                                                       // router_006:src_channel -> rsp_demux_001:sink_channel
	wire          router_006_src_startofpacket;                                                                 // router_006:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_006_src_endofpacket;                                                                   // router_006:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          niosv_g_dm_agent_agent_rp_valid;                                                              // niosv_g_dm_agent_agent:rp_valid -> router_007:sink_valid
	wire  [153:0] niosv_g_dm_agent_agent_rp_data;                                                               // niosv_g_dm_agent_agent:rp_data -> router_007:sink_data
	wire          niosv_g_dm_agent_agent_rp_ready;                                                              // router_007:sink_ready -> niosv_g_dm_agent_agent:rp_ready
	wire          niosv_g_dm_agent_agent_rp_startofpacket;                                                      // niosv_g_dm_agent_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          niosv_g_dm_agent_agent_rp_endofpacket;                                                        // niosv_g_dm_agent_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                                                         // router_007:src_valid -> rsp_demux_002:sink_valid
	wire  [153:0] router_007_src_data;                                                                          // router_007:src_data -> rsp_demux_002:sink_data
	wire          router_007_src_ready;                                                                         // rsp_demux_002:sink_ready -> router_007:src_ready
	wire    [5:0] router_007_src_channel;                                                                       // router_007:src_channel -> rsp_demux_002:sink_channel
	wire          router_007_src_startofpacket;                                                                 // router_007:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_007_src_endofpacket;                                                                   // router_007:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          mm_bridge_peripheral_s0_agent_rp_valid;                                                       // mm_bridge_peripheral_s0_agent:rp_valid -> router_008:sink_valid
	wire  [153:0] mm_bridge_peripheral_s0_agent_rp_data;                                                        // mm_bridge_peripheral_s0_agent:rp_data -> router_008:sink_data
	wire          mm_bridge_peripheral_s0_agent_rp_ready;                                                       // router_008:sink_ready -> mm_bridge_peripheral_s0_agent:rp_ready
	wire          mm_bridge_peripheral_s0_agent_rp_startofpacket;                                               // mm_bridge_peripheral_s0_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire          mm_bridge_peripheral_s0_agent_rp_endofpacket;                                                 // mm_bridge_peripheral_s0_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire          router_008_src_valid;                                                                         // router_008:src_valid -> rsp_demux_003:sink_valid
	wire  [153:0] router_008_src_data;                                                                          // router_008:src_data -> rsp_demux_003:sink_data
	wire          router_008_src_ready;                                                                         // rsp_demux_003:sink_ready -> router_008:src_ready
	wire    [5:0] router_008_src_channel;                                                                       // router_008:src_channel -> rsp_demux_003:sink_channel
	wire          router_008_src_startofpacket;                                                                 // router_008:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_008_src_endofpacket;                                                                   // router_008:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          onchip_memory_s1_agent_rp_valid;                                                              // onchip_memory_s1_agent:rp_valid -> router_009:sink_valid
	wire  [153:0] onchip_memory_s1_agent_rp_data;                                                               // onchip_memory_s1_agent:rp_data -> router_009:sink_data
	wire          onchip_memory_s1_agent_rp_ready;                                                              // router_009:sink_ready -> onchip_memory_s1_agent:rp_ready
	wire          onchip_memory_s1_agent_rp_startofpacket;                                                      // onchip_memory_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
	wire          onchip_memory_s1_agent_rp_endofpacket;                                                        // onchip_memory_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
	wire          router_009_src_valid;                                                                         // router_009:src_valid -> rsp_demux_004:sink_valid
	wire  [153:0] router_009_src_data;                                                                          // router_009:src_data -> rsp_demux_004:sink_data
	wire          router_009_src_ready;                                                                         // rsp_demux_004:sink_ready -> router_009:src_ready
	wire    [5:0] router_009_src_channel;                                                                       // router_009:src_channel -> rsp_demux_004:sink_channel
	wire          router_009_src_startofpacket;                                                                 // router_009:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_009_src_endofpacket;                                                                   // router_009:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          niosv_g_timer_sw_agent_agent_rp_valid;                                                        // niosv_g_timer_sw_agent_agent:rp_valid -> router_010:sink_valid
	wire  [153:0] niosv_g_timer_sw_agent_agent_rp_data;                                                         // niosv_g_timer_sw_agent_agent:rp_data -> router_010:sink_data
	wire          niosv_g_timer_sw_agent_agent_rp_ready;                                                        // router_010:sink_ready -> niosv_g_timer_sw_agent_agent:rp_ready
	wire          niosv_g_timer_sw_agent_agent_rp_startofpacket;                                                // niosv_g_timer_sw_agent_agent:rp_startofpacket -> router_010:sink_startofpacket
	wire          niosv_g_timer_sw_agent_agent_rp_endofpacket;                                                  // niosv_g_timer_sw_agent_agent:rp_endofpacket -> router_010:sink_endofpacket
	wire          router_010_src_valid;                                                                         // router_010:src_valid -> rsp_demux_005:sink_valid
	wire  [153:0] router_010_src_data;                                                                          // router_010:src_data -> rsp_demux_005:sink_data
	wire          router_010_src_ready;                                                                         // rsp_demux_005:sink_ready -> router_010:src_ready
	wire    [5:0] router_010_src_channel;                                                                       // router_010:src_channel -> rsp_demux_005:sink_channel
	wire          router_010_src_startofpacket;                                                                 // router_010:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_010_src_endofpacket;                                                                   // router_010:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          router_src_valid;                                                                             // router:src_valid -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_valid
	wire  [405:0] router_src_data;                                                                              // router:src_data -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_data
	wire          router_src_ready;                                                                             // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_ready -> router:src_ready
	wire    [5:0] router_src_channel;                                                                           // router:src_channel -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                                     // router:src_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                                       // router:src_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_sink_endofpacket
	wire  [405:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_data;                                       // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_data -> cmd_demux:sink_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_ready;                                      // cmd_demux:sink_ready -> intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_ready
	wire    [5:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_channel;                                    // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_channel -> cmd_demux:sink_channel
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_startofpacket;                              // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_endofpacket;                                // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                                            // rsp_mux:src_valid -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_valid
	wire  [405:0] rsp_mux_src_data;                                                                             // rsp_mux:src_data -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_data
	wire          rsp_mux_src_ready;                                                                            // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_ready -> rsp_mux:src_ready
	wire    [5:0] rsp_mux_src_channel;                                                                          // rsp_mux:src_channel -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_channel
	wire          rsp_mux_src_startofpacket;                                                                    // rsp_mux:src_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_startofpacket
	wire          rsp_mux_src_endofpacket;                                                                      // rsp_mux:src_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_sink_endofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_valid;                                      // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_valid -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_valid
	wire  [405:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_data;                                       // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_data -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_ready;                                      // intel_vvp_vfr_av_mm_mem_read_host_agent:rp_ready -> intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_ready
	wire    [5:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_channel;                                    // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_channel -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_channel
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_startofpacket;                              // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_endofpacket;                                // intel_vvp_vfr_av_mm_mem_read_host_limiter:rsp_src_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_agent:rp_endofpacket
	wire          router_003_src_valid;                                                                         // router_003:src_valid -> niosv_g_instruction_manager_wr_limiter:cmd_sink_valid
	wire  [153:0] router_003_src_data;                                                                          // router_003:src_data -> niosv_g_instruction_manager_wr_limiter:cmd_sink_data
	wire          router_003_src_ready;                                                                         // niosv_g_instruction_manager_wr_limiter:cmd_sink_ready -> router_003:src_ready
	wire    [5:0] router_003_src_channel;                                                                       // router_003:src_channel -> niosv_g_instruction_manager_wr_limiter:cmd_sink_channel
	wire          router_003_src_startofpacket;                                                                 // router_003:src_startofpacket -> niosv_g_instruction_manager_wr_limiter:cmd_sink_startofpacket
	wire          router_003_src_endofpacket;                                                                   // router_003:src_endofpacket -> niosv_g_instruction_manager_wr_limiter:cmd_sink_endofpacket
	wire  [153:0] niosv_g_instruction_manager_wr_limiter_cmd_src_data;                                          // niosv_g_instruction_manager_wr_limiter:cmd_src_data -> cmd_demux_003:sink_data
	wire          niosv_g_instruction_manager_wr_limiter_cmd_src_ready;                                         // cmd_demux_003:sink_ready -> niosv_g_instruction_manager_wr_limiter:cmd_src_ready
	wire    [5:0] niosv_g_instruction_manager_wr_limiter_cmd_src_channel;                                       // niosv_g_instruction_manager_wr_limiter:cmd_src_channel -> cmd_demux_003:sink_channel
	wire          niosv_g_instruction_manager_wr_limiter_cmd_src_startofpacket;                                 // niosv_g_instruction_manager_wr_limiter:cmd_src_startofpacket -> cmd_demux_003:sink_startofpacket
	wire          niosv_g_instruction_manager_wr_limiter_cmd_src_endofpacket;                                   // niosv_g_instruction_manager_wr_limiter:cmd_src_endofpacket -> cmd_demux_003:sink_endofpacket
	wire          rsp_mux_003_src_valid;                                                                        // rsp_mux_003:src_valid -> niosv_g_instruction_manager_wr_limiter:rsp_sink_valid
	wire  [153:0] rsp_mux_003_src_data;                                                                         // rsp_mux_003:src_data -> niosv_g_instruction_manager_wr_limiter:rsp_sink_data
	wire          rsp_mux_003_src_ready;                                                                        // niosv_g_instruction_manager_wr_limiter:rsp_sink_ready -> rsp_mux_003:src_ready
	wire    [5:0] rsp_mux_003_src_channel;                                                                      // rsp_mux_003:src_channel -> niosv_g_instruction_manager_wr_limiter:rsp_sink_channel
	wire          rsp_mux_003_src_startofpacket;                                                                // rsp_mux_003:src_startofpacket -> niosv_g_instruction_manager_wr_limiter:rsp_sink_startofpacket
	wire          rsp_mux_003_src_endofpacket;                                                                  // rsp_mux_003:src_endofpacket -> niosv_g_instruction_manager_wr_limiter:rsp_sink_endofpacket
	wire          niosv_g_instruction_manager_wr_limiter_rsp_src_valid;                                         // niosv_g_instruction_manager_wr_limiter:rsp_src_valid -> niosv_g_instruction_manager_agent:write_rp_valid
	wire  [153:0] niosv_g_instruction_manager_wr_limiter_rsp_src_data;                                          // niosv_g_instruction_manager_wr_limiter:rsp_src_data -> niosv_g_instruction_manager_agent:write_rp_data
	wire          niosv_g_instruction_manager_wr_limiter_rsp_src_ready;                                         // niosv_g_instruction_manager_agent:write_rp_ready -> niosv_g_instruction_manager_wr_limiter:rsp_src_ready
	wire    [5:0] niosv_g_instruction_manager_wr_limiter_rsp_src_channel;                                       // niosv_g_instruction_manager_wr_limiter:rsp_src_channel -> niosv_g_instruction_manager_agent:write_rp_channel
	wire          niosv_g_instruction_manager_wr_limiter_rsp_src_startofpacket;                                 // niosv_g_instruction_manager_wr_limiter:rsp_src_startofpacket -> niosv_g_instruction_manager_agent:write_rp_startofpacket
	wire          niosv_g_instruction_manager_wr_limiter_rsp_src_endofpacket;                                   // niosv_g_instruction_manager_wr_limiter:rsp_src_endofpacket -> niosv_g_instruction_manager_agent:write_rp_endofpacket
	wire          router_004_src_valid;                                                                         // router_004:src_valid -> niosv_g_instruction_manager_rd_limiter:cmd_sink_valid
	wire  [153:0] router_004_src_data;                                                                          // router_004:src_data -> niosv_g_instruction_manager_rd_limiter:cmd_sink_data
	wire          router_004_src_ready;                                                                         // niosv_g_instruction_manager_rd_limiter:cmd_sink_ready -> router_004:src_ready
	wire    [5:0] router_004_src_channel;                                                                       // router_004:src_channel -> niosv_g_instruction_manager_rd_limiter:cmd_sink_channel
	wire          router_004_src_startofpacket;                                                                 // router_004:src_startofpacket -> niosv_g_instruction_manager_rd_limiter:cmd_sink_startofpacket
	wire          router_004_src_endofpacket;                                                                   // router_004:src_endofpacket -> niosv_g_instruction_manager_rd_limiter:cmd_sink_endofpacket
	wire  [153:0] niosv_g_instruction_manager_rd_limiter_cmd_src_data;                                          // niosv_g_instruction_manager_rd_limiter:cmd_src_data -> cmd_demux_004:sink_data
	wire          niosv_g_instruction_manager_rd_limiter_cmd_src_ready;                                         // cmd_demux_004:sink_ready -> niosv_g_instruction_manager_rd_limiter:cmd_src_ready
	wire    [5:0] niosv_g_instruction_manager_rd_limiter_cmd_src_channel;                                       // niosv_g_instruction_manager_rd_limiter:cmd_src_channel -> cmd_demux_004:sink_channel
	wire          niosv_g_instruction_manager_rd_limiter_cmd_src_startofpacket;                                 // niosv_g_instruction_manager_rd_limiter:cmd_src_startofpacket -> cmd_demux_004:sink_startofpacket
	wire          niosv_g_instruction_manager_rd_limiter_cmd_src_endofpacket;                                   // niosv_g_instruction_manager_rd_limiter:cmd_src_endofpacket -> cmd_demux_004:sink_endofpacket
	wire          rsp_mux_004_src_valid;                                                                        // rsp_mux_004:src_valid -> niosv_g_instruction_manager_rd_limiter:rsp_sink_valid
	wire  [153:0] rsp_mux_004_src_data;                                                                         // rsp_mux_004:src_data -> niosv_g_instruction_manager_rd_limiter:rsp_sink_data
	wire          rsp_mux_004_src_ready;                                                                        // niosv_g_instruction_manager_rd_limiter:rsp_sink_ready -> rsp_mux_004:src_ready
	wire    [5:0] rsp_mux_004_src_channel;                                                                      // rsp_mux_004:src_channel -> niosv_g_instruction_manager_rd_limiter:rsp_sink_channel
	wire          rsp_mux_004_src_startofpacket;                                                                // rsp_mux_004:src_startofpacket -> niosv_g_instruction_manager_rd_limiter:rsp_sink_startofpacket
	wire          rsp_mux_004_src_endofpacket;                                                                  // rsp_mux_004:src_endofpacket -> niosv_g_instruction_manager_rd_limiter:rsp_sink_endofpacket
	wire          niosv_g_instruction_manager_rd_limiter_rsp_src_valid;                                         // niosv_g_instruction_manager_rd_limiter:rsp_src_valid -> niosv_g_instruction_manager_agent:read_rp_valid
	wire  [153:0] niosv_g_instruction_manager_rd_limiter_rsp_src_data;                                          // niosv_g_instruction_manager_rd_limiter:rsp_src_data -> niosv_g_instruction_manager_agent:read_rp_data
	wire          niosv_g_instruction_manager_rd_limiter_rsp_src_ready;                                         // niosv_g_instruction_manager_agent:read_rp_ready -> niosv_g_instruction_manager_rd_limiter:rsp_src_ready
	wire    [5:0] niosv_g_instruction_manager_rd_limiter_rsp_src_channel;                                       // niosv_g_instruction_manager_rd_limiter:rsp_src_channel -> niosv_g_instruction_manager_agent:read_rp_channel
	wire          niosv_g_instruction_manager_rd_limiter_rsp_src_startofpacket;                                 // niosv_g_instruction_manager_rd_limiter:rsp_src_startofpacket -> niosv_g_instruction_manager_agent:read_rp_startofpacket
	wire          niosv_g_instruction_manager_rd_limiter_rsp_src_endofpacket;                                   // niosv_g_instruction_manager_rd_limiter:rsp_src_endofpacket -> niosv_g_instruction_manager_agent:read_rp_endofpacket
	wire          cmd_mux_002_src_valid;                                                                        // cmd_mux_002:src_valid -> niosv_g_dm_agent_burst_adapter:sink0_valid
	wire  [153:0] cmd_mux_002_src_data;                                                                         // cmd_mux_002:src_data -> niosv_g_dm_agent_burst_adapter:sink0_data
	wire          cmd_mux_002_src_ready;                                                                        // niosv_g_dm_agent_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
	wire    [5:0] cmd_mux_002_src_channel;                                                                      // cmd_mux_002:src_channel -> niosv_g_dm_agent_burst_adapter:sink0_channel
	wire          cmd_mux_002_src_startofpacket;                                                                // cmd_mux_002:src_startofpacket -> niosv_g_dm_agent_burst_adapter:sink0_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                                  // cmd_mux_002:src_endofpacket -> niosv_g_dm_agent_burst_adapter:sink0_endofpacket
	wire          niosv_g_dm_agent_burst_adapter_source0_valid;                                                 // niosv_g_dm_agent_burst_adapter:source0_valid -> niosv_g_dm_agent_agent:cp_valid
	wire  [153:0] niosv_g_dm_agent_burst_adapter_source0_data;                                                  // niosv_g_dm_agent_burst_adapter:source0_data -> niosv_g_dm_agent_agent:cp_data
	wire          niosv_g_dm_agent_burst_adapter_source0_ready;                                                 // niosv_g_dm_agent_agent:cp_ready -> niosv_g_dm_agent_burst_adapter:source0_ready
	wire    [5:0] niosv_g_dm_agent_burst_adapter_source0_channel;                                               // niosv_g_dm_agent_burst_adapter:source0_channel -> niosv_g_dm_agent_agent:cp_channel
	wire          niosv_g_dm_agent_burst_adapter_source0_startofpacket;                                         // niosv_g_dm_agent_burst_adapter:source0_startofpacket -> niosv_g_dm_agent_agent:cp_startofpacket
	wire          niosv_g_dm_agent_burst_adapter_source0_endofpacket;                                           // niosv_g_dm_agent_burst_adapter:source0_endofpacket -> niosv_g_dm_agent_agent:cp_endofpacket
	wire          cmd_mux_003_src_valid;                                                                        // cmd_mux_003:src_valid -> mm_bridge_peripheral_s0_burst_adapter:sink0_valid
	wire  [153:0] cmd_mux_003_src_data;                                                                         // cmd_mux_003:src_data -> mm_bridge_peripheral_s0_burst_adapter:sink0_data
	wire          cmd_mux_003_src_ready;                                                                        // mm_bridge_peripheral_s0_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
	wire    [5:0] cmd_mux_003_src_channel;                                                                      // cmd_mux_003:src_channel -> mm_bridge_peripheral_s0_burst_adapter:sink0_channel
	wire          cmd_mux_003_src_startofpacket;                                                                // cmd_mux_003:src_startofpacket -> mm_bridge_peripheral_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                                  // cmd_mux_003:src_endofpacket -> mm_bridge_peripheral_s0_burst_adapter:sink0_endofpacket
	wire          mm_bridge_peripheral_s0_burst_adapter_source0_valid;                                          // mm_bridge_peripheral_s0_burst_adapter:source0_valid -> mm_bridge_peripheral_s0_agent:cp_valid
	wire  [153:0] mm_bridge_peripheral_s0_burst_adapter_source0_data;                                           // mm_bridge_peripheral_s0_burst_adapter:source0_data -> mm_bridge_peripheral_s0_agent:cp_data
	wire          mm_bridge_peripheral_s0_burst_adapter_source0_ready;                                          // mm_bridge_peripheral_s0_agent:cp_ready -> mm_bridge_peripheral_s0_burst_adapter:source0_ready
	wire    [5:0] mm_bridge_peripheral_s0_burst_adapter_source0_channel;                                        // mm_bridge_peripheral_s0_burst_adapter:source0_channel -> mm_bridge_peripheral_s0_agent:cp_channel
	wire          mm_bridge_peripheral_s0_burst_adapter_source0_startofpacket;                                  // mm_bridge_peripheral_s0_burst_adapter:source0_startofpacket -> mm_bridge_peripheral_s0_agent:cp_startofpacket
	wire          mm_bridge_peripheral_s0_burst_adapter_source0_endofpacket;                                    // mm_bridge_peripheral_s0_burst_adapter:source0_endofpacket -> mm_bridge_peripheral_s0_agent:cp_endofpacket
	wire          cmd_mux_004_src_valid;                                                                        // cmd_mux_004:src_valid -> onchip_memory_s1_burst_adapter:sink0_valid
	wire  [153:0] cmd_mux_004_src_data;                                                                         // cmd_mux_004:src_data -> onchip_memory_s1_burst_adapter:sink0_data
	wire          cmd_mux_004_src_ready;                                                                        // onchip_memory_s1_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
	wire    [5:0] cmd_mux_004_src_channel;                                                                      // cmd_mux_004:src_channel -> onchip_memory_s1_burst_adapter:sink0_channel
	wire          cmd_mux_004_src_startofpacket;                                                                // cmd_mux_004:src_startofpacket -> onchip_memory_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                                                  // cmd_mux_004:src_endofpacket -> onchip_memory_s1_burst_adapter:sink0_endofpacket
	wire          onchip_memory_s1_burst_adapter_source0_valid;                                                 // onchip_memory_s1_burst_adapter:source0_valid -> onchip_memory_s1_agent:cp_valid
	wire  [153:0] onchip_memory_s1_burst_adapter_source0_data;                                                  // onchip_memory_s1_burst_adapter:source0_data -> onchip_memory_s1_agent:cp_data
	wire          onchip_memory_s1_burst_adapter_source0_ready;                                                 // onchip_memory_s1_agent:cp_ready -> onchip_memory_s1_burst_adapter:source0_ready
	wire    [5:0] onchip_memory_s1_burst_adapter_source0_channel;                                               // onchip_memory_s1_burst_adapter:source0_channel -> onchip_memory_s1_agent:cp_channel
	wire          onchip_memory_s1_burst_adapter_source0_startofpacket;                                         // onchip_memory_s1_burst_adapter:source0_startofpacket -> onchip_memory_s1_agent:cp_startofpacket
	wire          onchip_memory_s1_burst_adapter_source0_endofpacket;                                           // onchip_memory_s1_burst_adapter:source0_endofpacket -> onchip_memory_s1_agent:cp_endofpacket
	wire          cmd_mux_005_src_valid;                                                                        // cmd_mux_005:src_valid -> niosv_g_timer_sw_agent_burst_adapter:sink0_valid
	wire  [153:0] cmd_mux_005_src_data;                                                                         // cmd_mux_005:src_data -> niosv_g_timer_sw_agent_burst_adapter:sink0_data
	wire          cmd_mux_005_src_ready;                                                                        // niosv_g_timer_sw_agent_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
	wire    [5:0] cmd_mux_005_src_channel;                                                                      // cmd_mux_005:src_channel -> niosv_g_timer_sw_agent_burst_adapter:sink0_channel
	wire          cmd_mux_005_src_startofpacket;                                                                // cmd_mux_005:src_startofpacket -> niosv_g_timer_sw_agent_burst_adapter:sink0_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                                                  // cmd_mux_005:src_endofpacket -> niosv_g_timer_sw_agent_burst_adapter:sink0_endofpacket
	wire          niosv_g_timer_sw_agent_burst_adapter_source0_valid;                                           // niosv_g_timer_sw_agent_burst_adapter:source0_valid -> niosv_g_timer_sw_agent_agent:cp_valid
	wire  [153:0] niosv_g_timer_sw_agent_burst_adapter_source0_data;                                            // niosv_g_timer_sw_agent_burst_adapter:source0_data -> niosv_g_timer_sw_agent_agent:cp_data
	wire          niosv_g_timer_sw_agent_burst_adapter_source0_ready;                                           // niosv_g_timer_sw_agent_agent:cp_ready -> niosv_g_timer_sw_agent_burst_adapter:source0_ready
	wire    [5:0] niosv_g_timer_sw_agent_burst_adapter_source0_channel;                                         // niosv_g_timer_sw_agent_burst_adapter:source0_channel -> niosv_g_timer_sw_agent_agent:cp_channel
	wire          niosv_g_timer_sw_agent_burst_adapter_source0_startofpacket;                                   // niosv_g_timer_sw_agent_burst_adapter:source0_startofpacket -> niosv_g_timer_sw_agent_agent:cp_startofpacket
	wire          niosv_g_timer_sw_agent_burst_adapter_source0_endofpacket;                                     // niosv_g_timer_sw_agent_burst_adapter:source0_endofpacket -> niosv_g_timer_sw_agent_agent:cp_endofpacket
	wire          cmd_demux_001_src1_valid;                                                                     // cmd_demux_001:src1_valid -> cmd_mux_002:sink0_valid
	wire  [153:0] cmd_demux_001_src1_data;                                                                      // cmd_demux_001:src1_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_001_src1_ready;                                                                     // cmd_mux_002:sink0_ready -> cmd_demux_001:src1_ready
	wire    [5:0] cmd_demux_001_src1_channel;                                                                   // cmd_demux_001:src1_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_001_src1_startofpacket;                                                             // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                                                               // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_001_src2_valid;                                                                     // cmd_demux_001:src2_valid -> cmd_mux_003:sink0_valid
	wire  [153:0] cmd_demux_001_src2_data;                                                                      // cmd_demux_001:src2_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_001_src2_ready;                                                                     // cmd_mux_003:sink0_ready -> cmd_demux_001:src2_ready
	wire    [5:0] cmd_demux_001_src2_channel;                                                                   // cmd_demux_001:src2_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_001_src2_startofpacket;                                                             // cmd_demux_001:src2_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                                                               // cmd_demux_001:src2_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_001_src3_valid;                                                                     // cmd_demux_001:src3_valid -> cmd_mux_004:sink0_valid
	wire  [153:0] cmd_demux_001_src3_data;                                                                      // cmd_demux_001:src3_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_001_src3_ready;                                                                     // cmd_mux_004:sink0_ready -> cmd_demux_001:src3_ready
	wire    [5:0] cmd_demux_001_src3_channel;                                                                   // cmd_demux_001:src3_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_001_src3_startofpacket;                                                             // cmd_demux_001:src3_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_001_src3_endofpacket;                                                               // cmd_demux_001:src3_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_001_src4_valid;                                                                     // cmd_demux_001:src4_valid -> cmd_mux_005:sink0_valid
	wire  [153:0] cmd_demux_001_src4_data;                                                                      // cmd_demux_001:src4_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_001_src4_ready;                                                                     // cmd_mux_005:sink0_ready -> cmd_demux_001:src4_ready
	wire    [5:0] cmd_demux_001_src4_channel;                                                                   // cmd_demux_001:src4_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_001_src4_startofpacket;                                                             // cmd_demux_001:src4_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_001_src4_endofpacket;                                                               // cmd_demux_001:src4_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_002_src1_valid;                                                                     // cmd_demux_002:src1_valid -> cmd_mux_002:sink1_valid
	wire  [153:0] cmd_demux_002_src1_data;                                                                      // cmd_demux_002:src1_data -> cmd_mux_002:sink1_data
	wire          cmd_demux_002_src1_ready;                                                                     // cmd_mux_002:sink1_ready -> cmd_demux_002:src1_ready
	wire    [5:0] cmd_demux_002_src1_channel;                                                                   // cmd_demux_002:src1_channel -> cmd_mux_002:sink1_channel
	wire          cmd_demux_002_src1_startofpacket;                                                             // cmd_demux_002:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          cmd_demux_002_src1_endofpacket;                                                               // cmd_demux_002:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          cmd_demux_002_src2_valid;                                                                     // cmd_demux_002:src2_valid -> cmd_mux_003:sink1_valid
	wire  [153:0] cmd_demux_002_src2_data;                                                                      // cmd_demux_002:src2_data -> cmd_mux_003:sink1_data
	wire          cmd_demux_002_src2_ready;                                                                     // cmd_mux_003:sink1_ready -> cmd_demux_002:src2_ready
	wire    [5:0] cmd_demux_002_src2_channel;                                                                   // cmd_demux_002:src2_channel -> cmd_mux_003:sink1_channel
	wire          cmd_demux_002_src2_startofpacket;                                                             // cmd_demux_002:src2_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire          cmd_demux_002_src2_endofpacket;                                                               // cmd_demux_002:src2_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire          cmd_demux_002_src3_valid;                                                                     // cmd_demux_002:src3_valid -> cmd_mux_004:sink1_valid
	wire  [153:0] cmd_demux_002_src3_data;                                                                      // cmd_demux_002:src3_data -> cmd_mux_004:sink1_data
	wire          cmd_demux_002_src3_ready;                                                                     // cmd_mux_004:sink1_ready -> cmd_demux_002:src3_ready
	wire    [5:0] cmd_demux_002_src3_channel;                                                                   // cmd_demux_002:src3_channel -> cmd_mux_004:sink1_channel
	wire          cmd_demux_002_src3_startofpacket;                                                             // cmd_demux_002:src3_startofpacket -> cmd_mux_004:sink1_startofpacket
	wire          cmd_demux_002_src3_endofpacket;                                                               // cmd_demux_002:src3_endofpacket -> cmd_mux_004:sink1_endofpacket
	wire          cmd_demux_002_src4_valid;                                                                     // cmd_demux_002:src4_valid -> cmd_mux_005:sink1_valid
	wire  [153:0] cmd_demux_002_src4_data;                                                                      // cmd_demux_002:src4_data -> cmd_mux_005:sink1_data
	wire          cmd_demux_002_src4_ready;                                                                     // cmd_mux_005:sink1_ready -> cmd_demux_002:src4_ready
	wire    [5:0] cmd_demux_002_src4_channel;                                                                   // cmd_demux_002:src4_channel -> cmd_mux_005:sink1_channel
	wire          cmd_demux_002_src4_startofpacket;                                                             // cmd_demux_002:src4_startofpacket -> cmd_mux_005:sink1_startofpacket
	wire          cmd_demux_002_src4_endofpacket;                                                               // cmd_demux_002:src4_endofpacket -> cmd_mux_005:sink1_endofpacket
	wire          cmd_demux_003_src0_valid;                                                                     // cmd_demux_003:src0_valid -> cmd_mux_002:sink2_valid
	wire  [153:0] cmd_demux_003_src0_data;                                                                      // cmd_demux_003:src0_data -> cmd_mux_002:sink2_data
	wire          cmd_demux_003_src0_ready;                                                                     // cmd_mux_002:sink2_ready -> cmd_demux_003:src0_ready
	wire    [5:0] cmd_demux_003_src0_channel;                                                                   // cmd_demux_003:src0_channel -> cmd_mux_002:sink2_channel
	wire          cmd_demux_003_src0_startofpacket;                                                             // cmd_demux_003:src0_startofpacket -> cmd_mux_002:sink2_startofpacket
	wire          cmd_demux_003_src0_endofpacket;                                                               // cmd_demux_003:src0_endofpacket -> cmd_mux_002:sink2_endofpacket
	wire          cmd_demux_003_src1_valid;                                                                     // cmd_demux_003:src1_valid -> cmd_mux_004:sink2_valid
	wire  [153:0] cmd_demux_003_src1_data;                                                                      // cmd_demux_003:src1_data -> cmd_mux_004:sink2_data
	wire          cmd_demux_003_src1_ready;                                                                     // cmd_mux_004:sink2_ready -> cmd_demux_003:src1_ready
	wire    [5:0] cmd_demux_003_src1_channel;                                                                   // cmd_demux_003:src1_channel -> cmd_mux_004:sink2_channel
	wire          cmd_demux_003_src1_startofpacket;                                                             // cmd_demux_003:src1_startofpacket -> cmd_mux_004:sink2_startofpacket
	wire          cmd_demux_003_src1_endofpacket;                                                               // cmd_demux_003:src1_endofpacket -> cmd_mux_004:sink2_endofpacket
	wire          cmd_demux_004_src0_valid;                                                                     // cmd_demux_004:src0_valid -> cmd_mux_002:sink3_valid
	wire  [153:0] cmd_demux_004_src0_data;                                                                      // cmd_demux_004:src0_data -> cmd_mux_002:sink3_data
	wire          cmd_demux_004_src0_ready;                                                                     // cmd_mux_002:sink3_ready -> cmd_demux_004:src0_ready
	wire    [5:0] cmd_demux_004_src0_channel;                                                                   // cmd_demux_004:src0_channel -> cmd_mux_002:sink3_channel
	wire          cmd_demux_004_src0_startofpacket;                                                             // cmd_demux_004:src0_startofpacket -> cmd_mux_002:sink3_startofpacket
	wire          cmd_demux_004_src0_endofpacket;                                                               // cmd_demux_004:src0_endofpacket -> cmd_mux_002:sink3_endofpacket
	wire          cmd_demux_004_src1_valid;                                                                     // cmd_demux_004:src1_valid -> cmd_mux_004:sink3_valid
	wire  [153:0] cmd_demux_004_src1_data;                                                                      // cmd_demux_004:src1_data -> cmd_mux_004:sink3_data
	wire          cmd_demux_004_src1_ready;                                                                     // cmd_mux_004:sink3_ready -> cmd_demux_004:src1_ready
	wire    [5:0] cmd_demux_004_src1_channel;                                                                   // cmd_demux_004:src1_channel -> cmd_mux_004:sink3_channel
	wire          cmd_demux_004_src1_startofpacket;                                                             // cmd_demux_004:src1_startofpacket -> cmd_mux_004:sink3_startofpacket
	wire          cmd_demux_004_src1_endofpacket;                                                               // cmd_demux_004:src1_endofpacket -> cmd_mux_004:sink3_endofpacket
	wire          rsp_demux_002_src0_valid;                                                                     // rsp_demux_002:src0_valid -> rsp_mux_001:sink1_valid
	wire  [153:0] rsp_demux_002_src0_data;                                                                      // rsp_demux_002:src0_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_002_src0_ready;                                                                     // rsp_mux_001:sink1_ready -> rsp_demux_002:src0_ready
	wire    [5:0] rsp_demux_002_src0_channel;                                                                   // rsp_demux_002:src0_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_002_src0_startofpacket;                                                             // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                                               // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_002_src1_valid;                                                                     // rsp_demux_002:src1_valid -> rsp_mux_002:sink1_valid
	wire  [153:0] rsp_demux_002_src1_data;                                                                      // rsp_demux_002:src1_data -> rsp_mux_002:sink1_data
	wire          rsp_demux_002_src1_ready;                                                                     // rsp_mux_002:sink1_ready -> rsp_demux_002:src1_ready
	wire    [5:0] rsp_demux_002_src1_channel;                                                                   // rsp_demux_002:src1_channel -> rsp_mux_002:sink1_channel
	wire          rsp_demux_002_src1_startofpacket;                                                             // rsp_demux_002:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                                                               // rsp_demux_002:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
	wire          rsp_demux_002_src2_valid;                                                                     // rsp_demux_002:src2_valid -> rsp_mux_003:sink0_valid
	wire  [153:0] rsp_demux_002_src2_data;                                                                      // rsp_demux_002:src2_data -> rsp_mux_003:sink0_data
	wire          rsp_demux_002_src2_ready;                                                                     // rsp_mux_003:sink0_ready -> rsp_demux_002:src2_ready
	wire    [5:0] rsp_demux_002_src2_channel;                                                                   // rsp_demux_002:src2_channel -> rsp_mux_003:sink0_channel
	wire          rsp_demux_002_src2_startofpacket;                                                             // rsp_demux_002:src2_startofpacket -> rsp_mux_003:sink0_startofpacket
	wire          rsp_demux_002_src2_endofpacket;                                                               // rsp_demux_002:src2_endofpacket -> rsp_mux_003:sink0_endofpacket
	wire          rsp_demux_002_src3_valid;                                                                     // rsp_demux_002:src3_valid -> rsp_mux_004:sink0_valid
	wire  [153:0] rsp_demux_002_src3_data;                                                                      // rsp_demux_002:src3_data -> rsp_mux_004:sink0_data
	wire          rsp_demux_002_src3_ready;                                                                     // rsp_mux_004:sink0_ready -> rsp_demux_002:src3_ready
	wire    [5:0] rsp_demux_002_src3_channel;                                                                   // rsp_demux_002:src3_channel -> rsp_mux_004:sink0_channel
	wire          rsp_demux_002_src3_startofpacket;                                                             // rsp_demux_002:src3_startofpacket -> rsp_mux_004:sink0_startofpacket
	wire          rsp_demux_002_src3_endofpacket;                                                               // rsp_demux_002:src3_endofpacket -> rsp_mux_004:sink0_endofpacket
	wire          rsp_demux_003_src0_valid;                                                                     // rsp_demux_003:src0_valid -> rsp_mux_001:sink2_valid
	wire  [153:0] rsp_demux_003_src0_data;                                                                      // rsp_demux_003:src0_data -> rsp_mux_001:sink2_data
	wire          rsp_demux_003_src0_ready;                                                                     // rsp_mux_001:sink2_ready -> rsp_demux_003:src0_ready
	wire    [5:0] rsp_demux_003_src0_channel;                                                                   // rsp_demux_003:src0_channel -> rsp_mux_001:sink2_channel
	wire          rsp_demux_003_src0_startofpacket;                                                             // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                                               // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
	wire          rsp_demux_003_src1_valid;                                                                     // rsp_demux_003:src1_valid -> rsp_mux_002:sink2_valid
	wire  [153:0] rsp_demux_003_src1_data;                                                                      // rsp_demux_003:src1_data -> rsp_mux_002:sink2_data
	wire          rsp_demux_003_src1_ready;                                                                     // rsp_mux_002:sink2_ready -> rsp_demux_003:src1_ready
	wire    [5:0] rsp_demux_003_src1_channel;                                                                   // rsp_demux_003:src1_channel -> rsp_mux_002:sink2_channel
	wire          rsp_demux_003_src1_startofpacket;                                                             // rsp_demux_003:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
	wire          rsp_demux_003_src1_endofpacket;                                                               // rsp_demux_003:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
	wire          rsp_demux_004_src0_valid;                                                                     // rsp_demux_004:src0_valid -> rsp_mux_001:sink3_valid
	wire  [153:0] rsp_demux_004_src0_data;                                                                      // rsp_demux_004:src0_data -> rsp_mux_001:sink3_data
	wire          rsp_demux_004_src0_ready;                                                                     // rsp_mux_001:sink3_ready -> rsp_demux_004:src0_ready
	wire    [5:0] rsp_demux_004_src0_channel;                                                                   // rsp_demux_004:src0_channel -> rsp_mux_001:sink3_channel
	wire          rsp_demux_004_src0_startofpacket;                                                             // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                                               // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
	wire          rsp_demux_004_src1_valid;                                                                     // rsp_demux_004:src1_valid -> rsp_mux_002:sink3_valid
	wire  [153:0] rsp_demux_004_src1_data;                                                                      // rsp_demux_004:src1_data -> rsp_mux_002:sink3_data
	wire          rsp_demux_004_src1_ready;                                                                     // rsp_mux_002:sink3_ready -> rsp_demux_004:src1_ready
	wire    [5:0] rsp_demux_004_src1_channel;                                                                   // rsp_demux_004:src1_channel -> rsp_mux_002:sink3_channel
	wire          rsp_demux_004_src1_startofpacket;                                                             // rsp_demux_004:src1_startofpacket -> rsp_mux_002:sink3_startofpacket
	wire          rsp_demux_004_src1_endofpacket;                                                               // rsp_demux_004:src1_endofpacket -> rsp_mux_002:sink3_endofpacket
	wire          rsp_demux_004_src2_valid;                                                                     // rsp_demux_004:src2_valid -> rsp_mux_003:sink1_valid
	wire  [153:0] rsp_demux_004_src2_data;                                                                      // rsp_demux_004:src2_data -> rsp_mux_003:sink1_data
	wire          rsp_demux_004_src2_ready;                                                                     // rsp_mux_003:sink1_ready -> rsp_demux_004:src2_ready
	wire    [5:0] rsp_demux_004_src2_channel;                                                                   // rsp_demux_004:src2_channel -> rsp_mux_003:sink1_channel
	wire          rsp_demux_004_src2_startofpacket;                                                             // rsp_demux_004:src2_startofpacket -> rsp_mux_003:sink1_startofpacket
	wire          rsp_demux_004_src2_endofpacket;                                                               // rsp_demux_004:src2_endofpacket -> rsp_mux_003:sink1_endofpacket
	wire          rsp_demux_004_src3_valid;                                                                     // rsp_demux_004:src3_valid -> rsp_mux_004:sink1_valid
	wire  [153:0] rsp_demux_004_src3_data;                                                                      // rsp_demux_004:src3_data -> rsp_mux_004:sink1_data
	wire          rsp_demux_004_src3_ready;                                                                     // rsp_mux_004:sink1_ready -> rsp_demux_004:src3_ready
	wire    [5:0] rsp_demux_004_src3_channel;                                                                   // rsp_demux_004:src3_channel -> rsp_mux_004:sink1_channel
	wire          rsp_demux_004_src3_startofpacket;                                                             // rsp_demux_004:src3_startofpacket -> rsp_mux_004:sink1_startofpacket
	wire          rsp_demux_004_src3_endofpacket;                                                               // rsp_demux_004:src3_endofpacket -> rsp_mux_004:sink1_endofpacket
	wire          rsp_demux_005_src0_valid;                                                                     // rsp_demux_005:src0_valid -> rsp_mux_001:sink4_valid
	wire  [153:0] rsp_demux_005_src0_data;                                                                      // rsp_demux_005:src0_data -> rsp_mux_001:sink4_data
	wire          rsp_demux_005_src0_ready;                                                                     // rsp_mux_001:sink4_ready -> rsp_demux_005:src0_ready
	wire    [5:0] rsp_demux_005_src0_channel;                                                                   // rsp_demux_005:src0_channel -> rsp_mux_001:sink4_channel
	wire          rsp_demux_005_src0_startofpacket;                                                             // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                                               // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
	wire          rsp_demux_005_src1_valid;                                                                     // rsp_demux_005:src1_valid -> rsp_mux_002:sink4_valid
	wire  [153:0] rsp_demux_005_src1_data;                                                                      // rsp_demux_005:src1_data -> rsp_mux_002:sink4_data
	wire          rsp_demux_005_src1_ready;                                                                     // rsp_mux_002:sink4_ready -> rsp_demux_005:src1_ready
	wire    [5:0] rsp_demux_005_src1_channel;                                                                   // rsp_demux_005:src1_channel -> rsp_mux_002:sink4_channel
	wire          rsp_demux_005_src1_startofpacket;                                                             // rsp_demux_005:src1_startofpacket -> rsp_mux_002:sink4_startofpacket
	wire          rsp_demux_005_src1_endofpacket;                                                               // rsp_demux_005:src1_endofpacket -> rsp_mux_002:sink4_endofpacket
	wire          cmd_demux_src0_valid;                                                                         // cmd_demux:src0_valid -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:in_valid
	wire  [405:0] cmd_demux_src0_data;                                                                          // cmd_demux:src0_data -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:in_data
	wire          cmd_demux_src0_ready;                                                                         // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:in_ready -> cmd_demux:src0_ready
	wire    [5:0] cmd_demux_src0_channel;                                                                       // cmd_demux:src0_channel -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:in_channel
	wire          cmd_demux_src0_startofpacket;                                                                 // cmd_demux:src0_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                                   // cmd_demux:src0_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:in_endofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_valid;         // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:out_valid -> cmd_mux:sink0_valid
	wire  [189:0] intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_data;          // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:out_data -> cmd_mux:sink0_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_ready;         // cmd_mux:sink0_ready -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:out_ready
	wire    [5:0] intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_channel;       // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:out_channel -> cmd_mux:sink0_channel
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket; // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket;   // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                                         // cmd_demux:src1_valid -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:in_valid
	wire  [405:0] cmd_demux_src1_data;                                                                          // cmd_demux:src1_data -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:in_data
	wire          cmd_demux_src1_ready;                                                                         // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:in_ready -> cmd_demux:src1_ready
	wire    [5:0] cmd_demux_src1_channel;                                                                       // cmd_demux:src1_channel -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:in_channel
	wire          cmd_demux_src1_startofpacket;                                                                 // cmd_demux:src1_startofpacket -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                                   // cmd_demux:src1_endofpacket -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:in_endofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_valid;         // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:out_valid -> cmd_mux_001:sink0_valid
	wire  [189:0] intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_data;          // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:out_data -> cmd_mux_001:sink0_data
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_ready;         // cmd_mux_001:sink0_ready -> intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:out_ready
	wire    [5:0] intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_channel;       // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:out_channel -> cmd_mux_001:sink0_channel
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket; // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket;   // intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                                     // cmd_demux_001:src0_valid -> niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:in_valid
	wire  [153:0] cmd_demux_001_src0_data;                                                                      // cmd_demux_001:src0_data -> niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:in_data
	wire          cmd_demux_001_src0_ready;                                                                     // niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:in_ready -> cmd_demux_001:src0_ready
	wire    [5:0] cmd_demux_001_src0_channel;                                                                   // cmd_demux_001:src0_channel -> niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:in_channel
	wire          cmd_demux_001_src0_startofpacket;                                                             // cmd_demux_001:src0_startofpacket -> niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                                               // cmd_demux_001:src0_endofpacket -> niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:in_endofpacket
	wire          niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_valid;                   // niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:out_valid -> cmd_mux:sink1_valid
	wire  [189:0] niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_data;                    // niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:out_data -> cmd_mux:sink1_data
	wire          niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_ready;                   // cmd_mux:sink1_ready -> niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:out_ready
	wire    [5:0] niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_channel;                 // niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:out_channel -> cmd_mux:sink1_channel
	wire          niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket;           // niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:out_startofpacket -> cmd_mux:sink1_startofpacket
	wire          niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket;             // niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter:out_endofpacket -> cmd_mux:sink1_endofpacket
	wire          cmd_demux_002_src0_valid;                                                                     // cmd_demux_002:src0_valid -> niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:in_valid
	wire  [153:0] cmd_demux_002_src0_data;                                                                      // cmd_demux_002:src0_data -> niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:in_data
	wire          cmd_demux_002_src0_ready;                                                                     // niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:in_ready -> cmd_demux_002:src0_ready
	wire    [5:0] cmd_demux_002_src0_channel;                                                                   // cmd_demux_002:src0_channel -> niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:in_channel
	wire          cmd_demux_002_src0_startofpacket;                                                             // cmd_demux_002:src0_startofpacket -> niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                                               // cmd_demux_002:src0_endofpacket -> niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:in_endofpacket
	wire          niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_valid;                   // niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:out_valid -> cmd_mux_001:sink1_valid
	wire  [189:0] niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_data;                    // niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:out_data -> cmd_mux_001:sink1_data
	wire          niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_ready;                   // cmd_mux_001:sink1_ready -> niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:out_ready
	wire    [5:0] niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_channel;                 // niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:out_channel -> cmd_mux_001:sink1_channel
	wire          niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket;           // niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:out_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket;             // niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter:out_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          rsp_demux_src0_valid;                                                                         // rsp_demux:src0_valid -> sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_valid
	wire  [189:0] rsp_demux_src0_data;                                                                          // rsp_demux:src0_data -> sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_data
	wire          rsp_demux_src0_ready;                                                                         // sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_ready -> rsp_demux:src0_ready
	wire    [5:0] rsp_demux_src0_channel;                                                                       // rsp_demux:src0_channel -> sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_channel
	wire          rsp_demux_src0_startofpacket;                                                                 // rsp_demux:src0_startofpacket -> sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                                   // rsp_demux:src0_endofpacket -> sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_valid;         // sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_valid -> rsp_mux:sink0_valid
	wire  [405:0] sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_data;          // sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_data -> rsp_mux:sink0_data
	wire          sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_ready;         // rsp_mux:sink0_ready -> sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_ready
	wire    [5:0] sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_channel;       // sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_channel -> rsp_mux:sink0_channel
	wire          sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_startofpacket; // sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_endofpacket;   // sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                                         // rsp_demux:src1_valid -> sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:in_valid
	wire  [189:0] rsp_demux_src1_data;                                                                          // rsp_demux:src1_data -> sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:in_data
	wire          rsp_demux_src1_ready;                                                                         // sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:in_ready -> rsp_demux:src1_ready
	wire    [5:0] rsp_demux_src1_channel;                                                                       // rsp_demux:src1_channel -> sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:in_channel
	wire          rsp_demux_src1_startofpacket;                                                                 // rsp_demux:src1_startofpacket -> sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                                   // rsp_demux:src1_endofpacket -> sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_valid;                   // sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:out_valid -> rsp_mux_001:sink0_valid
	wire  [153:0] sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_data;                    // sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:out_data -> rsp_mux_001:sink0_data
	wire          sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_ready;                   // rsp_mux_001:sink0_ready -> sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:out_ready
	wire    [5:0] sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_channel;                 // sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:out_channel -> rsp_mux_001:sink0_channel
	wire          sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_startofpacket;           // sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:out_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_endofpacket;             // sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter:out_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                                     // rsp_demux_001:src0_valid -> sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_valid
	wire  [189:0] rsp_demux_001_src0_data;                                                                      // rsp_demux_001:src0_data -> sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_data
	wire          rsp_demux_001_src0_ready;                                                                     // sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_ready -> rsp_demux_001:src0_ready
	wire    [5:0] rsp_demux_001_src0_channel;                                                                   // rsp_demux_001:src0_channel -> sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_channel
	wire          rsp_demux_001_src0_startofpacket;                                                             // rsp_demux_001:src0_startofpacket -> sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                               // rsp_demux_001:src0_endofpacket -> sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_valid;         // sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_valid -> rsp_mux:sink1_valid
	wire  [405:0] sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_data;          // sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_data -> rsp_mux:sink1_data
	wire          sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_ready;         // rsp_mux:sink1_ready -> sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_ready
	wire    [5:0] sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_channel;       // sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_channel -> rsp_mux:sink1_channel
	wire          sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_startofpacket; // sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire          sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_endofpacket;   // sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter:out_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                                                     // rsp_demux_001:src1_valid -> sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:in_valid
	wire  [189:0] rsp_demux_001_src1_data;                                                                      // rsp_demux_001:src1_data -> sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:in_data
	wire          rsp_demux_001_src1_ready;                                                                     // sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:in_ready -> rsp_demux_001:src1_ready
	wire    [5:0] rsp_demux_001_src1_channel;                                                                   // rsp_demux_001:src1_channel -> sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:in_channel
	wire          rsp_demux_001_src1_startofpacket;                                                             // rsp_demux_001:src1_startofpacket -> sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                                               // rsp_demux_001:src1_endofpacket -> sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:in_endofpacket
	wire          sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_valid;                   // sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:out_valid -> rsp_mux_002:sink0_valid
	wire  [153:0] sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_data;                    // sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:out_data -> rsp_mux_002:sink0_data
	wire          sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_ready;                   // rsp_mux_002:sink0_ready -> sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:out_ready
	wire    [5:0] sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_channel;                 // sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:out_channel -> rsp_mux_002:sink0_channel
	wire          sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_startofpacket;           // sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:out_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_endofpacket;             // sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter:out_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire    [5:0] intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_valid_data;                                     // intel_vvp_vfr_av_mm_mem_read_host_limiter:cmd_src_valid -> cmd_demux:sink_valid
	wire    [5:0] niosv_g_instruction_manager_wr_limiter_cmd_valid_data;                                        // niosv_g_instruction_manager_wr_limiter:cmd_src_valid -> cmd_demux_003:sink_valid
	wire    [5:0] niosv_g_instruction_manager_rd_limiter_cmd_valid_data;                                        // niosv_g_instruction_manager_rd_limiter:cmd_src_valid -> cmd_demux_004:sink_valid

	nios_system_altera_merlin_master_translator_193_lgcew2q #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (256),
		.AV_BURSTCOUNT_W             (6),
		.AV_BYTEENABLE_W             (32),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (11),
		.USE_READ                    (1),
		.USE_WRITE                   (0),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (32),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (1),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) intel_vvp_vfr_av_mm_mem_read_host_translator (
		.clk                    (iopll_outclk0_clk),                                                                                                                                                                                                                                                     //   input,    width = 1,                       clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                                                                                                                                                                                                   //   input,    width = 1,                     reset.reset
		.uav_address            (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_address),                                                                                                                                                                                        //  output,   width = 32, avalon_universal_master_0.address
		.uav_burstcount         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_burstcount),                                                                                                                                                                                     //  output,   width = 11,                          .burstcount
		.uav_read               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_read),                                                                                                                                                                                           //  output,    width = 1,                          .read
		.uav_write              (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_write),                                                                                                                                                                                          //  output,    width = 1,                          .write
		.uav_waitrequest        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_waitrequest),                                                                                                                                                                                    //   input,    width = 1,                          .waitrequest
		.uav_readdatavalid      (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdatavalid),                                                                                                                                                                                  //   input,    width = 1,                          .readdatavalid
		.uav_byteenable         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_byteenable),                                                                                                                                                                                     //  output,   width = 32,                          .byteenable
		.uav_readdata           (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdata),                                                                                                                                                                                       //   input,  width = 256,                          .readdata
		.uav_writedata          (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_writedata),                                                                                                                                                                                      //  output,  width = 256,                          .writedata
		.uav_lock               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_lock),                                                                                                                                                                                           //  output,    width = 1,                          .lock
		.uav_debugaccess        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_debugaccess),                                                                                                                                                                                    //  output,    width = 1,                          .debugaccess
		.av_address             (intel_vvp_vfr_av_mm_mem_read_host_address),                                                                                                                                                                                                                             //   input,   width = 32,      avalon_anti_master_0.address
		.av_waitrequest         (intel_vvp_vfr_av_mm_mem_read_host_waitrequest),                                                                                                                                                                                                                         //  output,    width = 1,                          .waitrequest
		.av_burstcount          (intel_vvp_vfr_av_mm_mem_read_host_burstcount),                                                                                                                                                                                                                          //   input,    width = 6,                          .burstcount
		.av_read                (intel_vvp_vfr_av_mm_mem_read_host_read),                                                                                                                                                                                                                                //   input,    width = 1,                          .read
		.av_readdata            (intel_vvp_vfr_av_mm_mem_read_host_readdata),                                                                                                                                                                                                                            //  output,  width = 256,                          .readdata
		.av_readdatavalid       (intel_vvp_vfr_av_mm_mem_read_host_readdatavalid),                                                                                                                                                                                                                       //  output,    width = 1,                          .readdatavalid
		.av_byteenable          (32'b11111111111111111111111111111111),                                                                                                                                                                                                                                  // (terminated),                                         
		.av_beginbursttransfer  (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_begintransfer       (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_chipselect          (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_write               (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_writedata           (256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated),                                         
		.av_lock                (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_debugaccess         (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.uav_outputenable       (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.uav_clken              (),                                                                                                                                                                                                                                                                      // (terminated),                                         
		.av_clken               (1'b1),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.uav_response           (2'b00),                                                                                                                                                                                                                                                                 // (terminated),                                         
		.av_response            (),                                                                                                                                                                                                                                                                      // (terminated),                                         
		.uav_writeresponsevalid (1'b0),                                                                                                                                                                                                                                                                  // (terminated),                                         
		.av_writeresponsevalid  ()                                                                                                                                                                                                                                                                       // (terminated),                                         
	);

	nios_system_altera_merlin_axi_translator_1974_xfkiwxi #(
		.USE_S0_AWID                       (0),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (0),
		.USE_S0_AWLOCK                     (0),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (0),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_WLAST                      (1),
		.USE_S0_BID                        (0),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (0),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (0),
		.USE_S0_ARLOCK                     (0),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (0),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (0),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.USE_M0_AWUSER_ADDRCHK             (1),
		.USE_M0_AWUSER_SAI                 (1),
		.USE_M0_ARUSER_ADDRCHK             (1),
		.USE_M0_ARUSER_SAI                 (1),
		.USE_M0_WUSER_DATACHK              (1),
		.USE_M0_WUSER_POISON               (1),
		.USE_M0_RUSER_DATACHK              (1),
		.USE_M0_RUSER_POISON               (1),
		.USE_M0_WUSER_DATA                 (1),
		.USE_M0_RUSER_DATA                 (1),
		.USE_M0_AWAKEUP                    (0),
		.USE_M0_WPOISON                    (0),
		.USE_M0_RPOISON                    (0),
		.USE_M0_AWTRACE                    (0),
		.USE_M0_ARTRACE                    (0),
		.USE_M0_WTRACE                     (0),
		.USE_M0_BTRACE                     (0),
		.USE_M0_RTRACE                     (0),
		.USE_M0_WDATACHK                   (0),
		.USE_M0_RDATACHK                   (0),
		.USE_M0_AWUNIQUE                   (1),
		.USE_S0_AWAKEUP                    (0),
		.USE_S0_WPOISON                    (0),
		.USE_S0_RPOISON                    (0),
		.USE_S0_AWTRACE                    (0),
		.USE_S0_ARTRACE                    (0),
		.USE_S0_WTRACE                     (0),
		.USE_S0_BTRACE                     (0),
		.USE_S0_RTRACE                     (0),
		.USE_S0_WDATACHK                   (0),
		.USE_S0_RDATACHK                   (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.USE_S0_AWUNIQUE                   (0),
		.M0_ID_WIDTH                       (1),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (1),
		.S0_SAI_WIDTH                      (1),
		.USER_DATA_WIDTH                   (1),
		.M0_USER_ADDRCHK_WIDTH             (1),
		.S0_USER_ADDRCHK_WIDTH             (1),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (32),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (32),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) niosv_g_data_manager_translator (
		.aclk              (iopll_outclk0_clk),                                    //   input,   width = 1,       clk.clk
		.aresetn           (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (niosv_g_data_manager_translator_m0_awid),              //  output,   width = 1,        m0.awid
		.m0_awaddr         (niosv_g_data_manager_translator_m0_awaddr),            //  output,  width = 32,          .awaddr
		.m0_awlen          (niosv_g_data_manager_translator_m0_awlen),             //  output,   width = 8,          .awlen
		.m0_awsize         (niosv_g_data_manager_translator_m0_awsize),            //  output,   width = 3,          .awsize
		.m0_awburst        (niosv_g_data_manager_translator_m0_awburst),           //  output,   width = 2,          .awburst
		.m0_awlock         (niosv_g_data_manager_translator_m0_awlock),            //  output,   width = 1,          .awlock
		.m0_awcache        (niosv_g_data_manager_translator_m0_awcache),           //  output,   width = 4,          .awcache
		.m0_awprot         (niosv_g_data_manager_translator_m0_awprot),            //  output,   width = 3,          .awprot
		.m0_awuser         (niosv_g_data_manager_translator_m0_awuser),            //  output,   width = 1,          .awuser
		.m0_awqos          (niosv_g_data_manager_translator_m0_awqos),             //  output,   width = 4,          .awqos
		.m0_awregion       (niosv_g_data_manager_translator_m0_awregion),          //  output,   width = 4,          .awregion
		.m0_awvalid        (niosv_g_data_manager_translator_m0_awvalid),           //  output,   width = 1,          .awvalid
		.m0_awready        (niosv_g_data_manager_translator_m0_awready),           //   input,   width = 1,          .awready
		.m0_wdata          (niosv_g_data_manager_translator_m0_wdata),             //  output,  width = 32,          .wdata
		.m0_wstrb          (niosv_g_data_manager_translator_m0_wstrb),             //  output,   width = 4,          .wstrb
		.m0_wlast          (niosv_g_data_manager_translator_m0_wlast),             //  output,   width = 1,          .wlast
		.m0_wvalid         (niosv_g_data_manager_translator_m0_wvalid),            //  output,   width = 1,          .wvalid
		.m0_wuser          (niosv_g_data_manager_translator_m0_wuser),             //  output,   width = 1,          .wuser
		.m0_wready         (niosv_g_data_manager_translator_m0_wready),            //   input,   width = 1,          .wready
		.m0_bid            (niosv_g_data_manager_translator_m0_bid),               //   input,   width = 1,          .bid
		.m0_bresp          (niosv_g_data_manager_translator_m0_bresp),             //   input,   width = 2,          .bresp
		.m0_buser          (niosv_g_data_manager_translator_m0_buser),             //   input,   width = 1,          .buser
		.m0_bvalid         (niosv_g_data_manager_translator_m0_bvalid),            //   input,   width = 1,          .bvalid
		.m0_bready         (niosv_g_data_manager_translator_m0_bready),            //  output,   width = 1,          .bready
		.m0_arid           (niosv_g_data_manager_translator_m0_arid),              //  output,   width = 1,          .arid
		.m0_araddr         (niosv_g_data_manager_translator_m0_araddr),            //  output,  width = 32,          .araddr
		.m0_arlen          (niosv_g_data_manager_translator_m0_arlen),             //  output,   width = 8,          .arlen
		.m0_arsize         (niosv_g_data_manager_translator_m0_arsize),            //  output,   width = 3,          .arsize
		.m0_arburst        (niosv_g_data_manager_translator_m0_arburst),           //  output,   width = 2,          .arburst
		.m0_arlock         (niosv_g_data_manager_translator_m0_arlock),            //  output,   width = 1,          .arlock
		.m0_arcache        (niosv_g_data_manager_translator_m0_arcache),           //  output,   width = 4,          .arcache
		.m0_arprot         (niosv_g_data_manager_translator_m0_arprot),            //  output,   width = 3,          .arprot
		.m0_aruser         (niosv_g_data_manager_translator_m0_aruser),            //  output,   width = 1,          .aruser
		.m0_arqos          (niosv_g_data_manager_translator_m0_arqos),             //  output,   width = 4,          .arqos
		.m0_arregion       (niosv_g_data_manager_translator_m0_arregion),          //  output,   width = 4,          .arregion
		.m0_arvalid        (niosv_g_data_manager_translator_m0_arvalid),           //  output,   width = 1,          .arvalid
		.m0_arready        (niosv_g_data_manager_translator_m0_arready),           //   input,   width = 1,          .arready
		.m0_rid            (niosv_g_data_manager_translator_m0_rid),               //   input,   width = 1,          .rid
		.m0_rdata          (niosv_g_data_manager_translator_m0_rdata),             //   input,  width = 32,          .rdata
		.m0_rresp          (niosv_g_data_manager_translator_m0_rresp),             //   input,   width = 2,          .rresp
		.m0_rlast          (niosv_g_data_manager_translator_m0_rlast),             //   input,   width = 1,          .rlast
		.m0_rvalid         (niosv_g_data_manager_translator_m0_rvalid),            //   input,   width = 1,          .rvalid
		.m0_rready         (niosv_g_data_manager_translator_m0_rready),            //  output,   width = 1,          .rready
		.m0_ruser          (niosv_g_data_manager_translator_m0_ruser),             //   input,   width = 1,          .ruser
		.s0_awaddr         (niosv_g_data_manager_awaddr),                          //   input,  width = 32,        s0.awaddr
		.s0_awlen          (niosv_g_data_manager_awlen),                           //   input,   width = 8,          .awlen
		.s0_awsize         (niosv_g_data_manager_awsize),                          //   input,   width = 3,          .awsize
		.s0_awprot         (niosv_g_data_manager_awprot),                          //   input,   width = 3,          .awprot
		.s0_awvalid        (niosv_g_data_manager_awvalid),                         //   input,   width = 1,          .awvalid
		.s0_awready        (niosv_g_data_manager_awready),                         //  output,   width = 1,          .awready
		.s0_wdata          (niosv_g_data_manager_wdata),                           //   input,  width = 32,          .wdata
		.s0_wstrb          (niosv_g_data_manager_wstrb),                           //   input,   width = 4,          .wstrb
		.s0_wlast          (niosv_g_data_manager_wlast),                           //   input,   width = 1,          .wlast
		.s0_wvalid         (niosv_g_data_manager_wvalid),                          //   input,   width = 1,          .wvalid
		.s0_wready         (niosv_g_data_manager_wready),                          //  output,   width = 1,          .wready
		.s0_bresp          (niosv_g_data_manager_bresp),                           //  output,   width = 2,          .bresp
		.s0_bvalid         (niosv_g_data_manager_bvalid),                          //  output,   width = 1,          .bvalid
		.s0_bready         (niosv_g_data_manager_bready),                          //   input,   width = 1,          .bready
		.s0_araddr         (niosv_g_data_manager_araddr),                          //   input,  width = 32,          .araddr
		.s0_arlen          (niosv_g_data_manager_arlen),                           //   input,   width = 8,          .arlen
		.s0_arsize         (niosv_g_data_manager_arsize),                          //   input,   width = 3,          .arsize
		.s0_arprot         (niosv_g_data_manager_arprot),                          //   input,   width = 3,          .arprot
		.s0_arvalid        (niosv_g_data_manager_arvalid),                         //   input,   width = 1,          .arvalid
		.s0_arready        (niosv_g_data_manager_arready),                         //  output,   width = 1,          .arready
		.s0_rdata          (niosv_g_data_manager_rdata),                           //  output,  width = 32,          .rdata
		.s0_rresp          (niosv_g_data_manager_rresp),                           //  output,   width = 2,          .rresp
		.s0_rlast          (niosv_g_data_manager_rlast),                           //  output,   width = 1,          .rlast
		.s0_rvalid         (niosv_g_data_manager_rvalid),                          //  output,   width = 1,          .rvalid
		.s0_rready         (niosv_g_data_manager_rready),                          //   input,   width = 1,          .rready
		.m0_awuser_addrchk (),                                                     // (terminated),                        
		.m0_awuser_sai     (),                                                     // (terminated),                        
		.m0_wuser_datachk  (),                                                     // (terminated),                        
		.m0_wuser_data     (),                                                     // (terminated),                        
		.m0_wuser_poison   (),                                                     // (terminated),                        
		.m0_aruser_addrchk (),                                                     // (terminated),                        
		.m0_aruser_sai     (),                                                     // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                              // (terminated),                        
		.m0_ruser_data     (1'b0),                                                 // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                 // (terminated),                        
		.s0_awid           (1'b0),                                                 // (terminated),                        
		.s0_awburst        (2'b00),                                                // (terminated),                        
		.s0_awlock         (1'b0),                                                 // (terminated),                        
		.s0_awcache        (4'b0000),                                              // (terminated),                        
		.s0_awuser         (1'b0),                                                 // (terminated),                        
		.s0_awuser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_awuser_sai     (1'b0),                                                 // (terminated),                        
		.s0_awqos          (4'b0000),                                              // (terminated),                        
		.s0_awregion       (4'b0000),                                              // (terminated),                        
		.s0_wuser          (1'b0),                                                 // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                              // (terminated),                        
		.s0_wuser_data     (1'b0),                                                 // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                 // (terminated),                        
		.s0_bid            (),                                                     // (terminated),                        
		.s0_buser          (),                                                     // (terminated),                        
		.s0_arid           (1'b0),                                                 // (terminated),                        
		.s0_arburst        (2'b01),                                                // (terminated),                        
		.s0_arlock         (1'b0),                                                 // (terminated),                        
		.s0_arcache        (4'b0000),                                              // (terminated),                        
		.s0_aruser         (1'b0),                                                 // (terminated),                        
		.s0_aruser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_aruser_sai     (1'b0),                                                 // (terminated),                        
		.s0_arqos          (4'b0000),                                              // (terminated),                        
		.s0_arregion       (4'b0000),                                              // (terminated),                        
		.s0_rid            (),                                                     // (terminated),                        
		.s0_ruser          (),                                                     // (terminated),                        
		.s0_ruser_datachk  (),                                                     // (terminated),                        
		.s0_ruser_data     (),                                                     // (terminated),                        
		.s0_ruser_poison   (),                                                     // (terminated),                        
		.m0_awakeup        (),                                                     // (terminated),                        
		.m0_awtrace        (),                                                     // (terminated),                        
		.m0_artrace        (),                                                     // (terminated),                        
		.m0_wpoison        (),                                                     // (terminated),                        
		.m0_wdatachk       (),                                                     // (terminated),                        
		.m0_wtrace         (),                                                     // (terminated),                        
		.m0_btrace         (1'b0),                                                 // (terminated),                        
		.m0_rpoison        (1'b0),                                                 // (terminated),                        
		.m0_rdatachk       (4'b0000),                                              // (terminated),                        
		.m0_rtrace         (1'b0),                                                 // (terminated),                        
		.m0_wid            (),                                                     // (terminated),                        
		.m0_ardomain       (),                                                     // (terminated),                        
		.m0_arsnoop        (),                                                     // (terminated),                        
		.m0_arbar          (),                                                     // (terminated),                        
		.m0_awdomain       (),                                                     // (terminated),                        
		.m0_awsnoop        (),                                                     // (terminated),                        
		.m0_awbar          (),                                                     // (terminated),                        
		.m0_awunique       (),                                                     // (terminated),                        
		.s0_awakeup        (1'b0),                                                 // (terminated),                        
		.s0_awtrace        (1'b0),                                                 // (terminated),                        
		.s0_artrace        (1'b0),                                                 // (terminated),                        
		.s0_wpoison        (1'b0),                                                 // (terminated),                        
		.s0_wdatachk       (4'b0000),                                              // (terminated),                        
		.s0_wtrace         (1'b0),                                                 // (terminated),                        
		.s0_btrace         (),                                                     // (terminated),                        
		.s0_rpoison        (),                                                     // (terminated),                        
		.s0_rdatachk       (),                                                     // (terminated),                        
		.s0_rtrace         (),                                                     // (terminated),                        
		.s0_wid            (1'b0),                                                 // (terminated),                        
		.s0_ardomain       (2'b00),                                                // (terminated),                        
		.s0_arsnoop        (4'b0000),                                              // (terminated),                        
		.s0_arbar          (2'b00),                                                // (terminated),                        
		.s0_awdomain       (2'b00),                                                // (terminated),                        
		.s0_awsnoop        (3'b000),                                               // (terminated),                        
		.s0_awbar          (2'b00),                                                // (terminated),                        
		.s0_awunique       (1'b0)                                                  // (terminated),                        
	);

	nios_system_altera_merlin_axi_translator_1974_xfkiwxi #(
		.USE_S0_AWID                       (0),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (0),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (0),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_WLAST                      (1),
		.USE_S0_BID                        (0),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (0),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (0),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (0),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (0),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.USE_M0_AWUSER_ADDRCHK             (1),
		.USE_M0_AWUSER_SAI                 (1),
		.USE_M0_ARUSER_ADDRCHK             (1),
		.USE_M0_ARUSER_SAI                 (1),
		.USE_M0_WUSER_DATACHK              (1),
		.USE_M0_WUSER_POISON               (1),
		.USE_M0_RUSER_DATACHK              (1),
		.USE_M0_RUSER_POISON               (1),
		.USE_M0_WUSER_DATA                 (1),
		.USE_M0_RUSER_DATA                 (1),
		.USE_M0_AWAKEUP                    (0),
		.USE_M0_WPOISON                    (0),
		.USE_M0_RPOISON                    (0),
		.USE_M0_AWTRACE                    (0),
		.USE_M0_ARTRACE                    (0),
		.USE_M0_WTRACE                     (0),
		.USE_M0_BTRACE                     (0),
		.USE_M0_RTRACE                     (0),
		.USE_M0_WDATACHK                   (0),
		.USE_M0_RDATACHK                   (0),
		.USE_M0_AWUNIQUE                   (1),
		.USE_S0_AWAKEUP                    (0),
		.USE_S0_WPOISON                    (0),
		.USE_S0_RPOISON                    (0),
		.USE_S0_AWTRACE                    (0),
		.USE_S0_ARTRACE                    (0),
		.USE_S0_WTRACE                     (0),
		.USE_S0_BTRACE                     (0),
		.USE_S0_RTRACE                     (0),
		.USE_S0_WDATACHK                   (0),
		.USE_S0_RDATACHK                   (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.USE_S0_AWUNIQUE                   (0),
		.M0_ID_WIDTH                       (1),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (1),
		.S0_SAI_WIDTH                      (1),
		.USER_DATA_WIDTH                   (1),
		.M0_USER_ADDRCHK_WIDTH             (1),
		.S0_USER_ADDRCHK_WIDTH             (1),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (32),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (32),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) niosv_g_instruction_manager_translator (
		.aclk              (iopll_outclk0_clk),                                    //   input,   width = 1,       clk.clk
		.aresetn           (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (niosv_g_instruction_manager_translator_m0_awid),       //  output,   width = 1,        m0.awid
		.m0_awaddr         (niosv_g_instruction_manager_translator_m0_awaddr),     //  output,  width = 32,          .awaddr
		.m0_awlen          (niosv_g_instruction_manager_translator_m0_awlen),      //  output,   width = 8,          .awlen
		.m0_awsize         (niosv_g_instruction_manager_translator_m0_awsize),     //  output,   width = 3,          .awsize
		.m0_awburst        (niosv_g_instruction_manager_translator_m0_awburst),    //  output,   width = 2,          .awburst
		.m0_awlock         (niosv_g_instruction_manager_translator_m0_awlock),     //  output,   width = 1,          .awlock
		.m0_awcache        (niosv_g_instruction_manager_translator_m0_awcache),    //  output,   width = 4,          .awcache
		.m0_awprot         (niosv_g_instruction_manager_translator_m0_awprot),     //  output,   width = 3,          .awprot
		.m0_awuser         (niosv_g_instruction_manager_translator_m0_awuser),     //  output,   width = 1,          .awuser
		.m0_awqos          (niosv_g_instruction_manager_translator_m0_awqos),      //  output,   width = 4,          .awqos
		.m0_awregion       (niosv_g_instruction_manager_translator_m0_awregion),   //  output,   width = 4,          .awregion
		.m0_awvalid        (niosv_g_instruction_manager_translator_m0_awvalid),    //  output,   width = 1,          .awvalid
		.m0_awready        (niosv_g_instruction_manager_translator_m0_awready),    //   input,   width = 1,          .awready
		.m0_wdata          (niosv_g_instruction_manager_translator_m0_wdata),      //  output,  width = 32,          .wdata
		.m0_wstrb          (niosv_g_instruction_manager_translator_m0_wstrb),      //  output,   width = 4,          .wstrb
		.m0_wlast          (niosv_g_instruction_manager_translator_m0_wlast),      //  output,   width = 1,          .wlast
		.m0_wvalid         (niosv_g_instruction_manager_translator_m0_wvalid),     //  output,   width = 1,          .wvalid
		.m0_wuser          (niosv_g_instruction_manager_translator_m0_wuser),      //  output,   width = 1,          .wuser
		.m0_wready         (niosv_g_instruction_manager_translator_m0_wready),     //   input,   width = 1,          .wready
		.m0_bid            (niosv_g_instruction_manager_translator_m0_bid),        //   input,   width = 1,          .bid
		.m0_bresp          (niosv_g_instruction_manager_translator_m0_bresp),      //   input,   width = 2,          .bresp
		.m0_buser          (niosv_g_instruction_manager_translator_m0_buser),      //   input,   width = 1,          .buser
		.m0_bvalid         (niosv_g_instruction_manager_translator_m0_bvalid),     //   input,   width = 1,          .bvalid
		.m0_bready         (niosv_g_instruction_manager_translator_m0_bready),     //  output,   width = 1,          .bready
		.m0_arid           (niosv_g_instruction_manager_translator_m0_arid),       //  output,   width = 1,          .arid
		.m0_araddr         (niosv_g_instruction_manager_translator_m0_araddr),     //  output,  width = 32,          .araddr
		.m0_arlen          (niosv_g_instruction_manager_translator_m0_arlen),      //  output,   width = 8,          .arlen
		.m0_arsize         (niosv_g_instruction_manager_translator_m0_arsize),     //  output,   width = 3,          .arsize
		.m0_arburst        (niosv_g_instruction_manager_translator_m0_arburst),    //  output,   width = 2,          .arburst
		.m0_arlock         (niosv_g_instruction_manager_translator_m0_arlock),     //  output,   width = 1,          .arlock
		.m0_arcache        (niosv_g_instruction_manager_translator_m0_arcache),    //  output,   width = 4,          .arcache
		.m0_arprot         (niosv_g_instruction_manager_translator_m0_arprot),     //  output,   width = 3,          .arprot
		.m0_aruser         (niosv_g_instruction_manager_translator_m0_aruser),     //  output,   width = 1,          .aruser
		.m0_arqos          (niosv_g_instruction_manager_translator_m0_arqos),      //  output,   width = 4,          .arqos
		.m0_arregion       (niosv_g_instruction_manager_translator_m0_arregion),   //  output,   width = 4,          .arregion
		.m0_arvalid        (niosv_g_instruction_manager_translator_m0_arvalid),    //  output,   width = 1,          .arvalid
		.m0_arready        (niosv_g_instruction_manager_translator_m0_arready),    //   input,   width = 1,          .arready
		.m0_rid            (niosv_g_instruction_manager_translator_m0_rid),        //   input,   width = 1,          .rid
		.m0_rdata          (niosv_g_instruction_manager_translator_m0_rdata),      //   input,  width = 32,          .rdata
		.m0_rresp          (niosv_g_instruction_manager_translator_m0_rresp),      //   input,   width = 2,          .rresp
		.m0_rlast          (niosv_g_instruction_manager_translator_m0_rlast),      //   input,   width = 1,          .rlast
		.m0_rvalid         (niosv_g_instruction_manager_translator_m0_rvalid),     //   input,   width = 1,          .rvalid
		.m0_rready         (niosv_g_instruction_manager_translator_m0_rready),     //  output,   width = 1,          .rready
		.m0_ruser          (niosv_g_instruction_manager_translator_m0_ruser),      //   input,   width = 1,          .ruser
		.s0_awaddr         (niosv_g_instruction_manager_awaddr),                   //   input,  width = 32,        s0.awaddr
		.s0_awlen          (niosv_g_instruction_manager_awlen),                    //   input,   width = 8,          .awlen
		.s0_awsize         (niosv_g_instruction_manager_awsize),                   //   input,   width = 3,          .awsize
		.s0_awburst        (niosv_g_instruction_manager_awburst),                  //   input,   width = 2,          .awburst
		.s0_awprot         (niosv_g_instruction_manager_awprot),                   //   input,   width = 3,          .awprot
		.s0_awvalid        (niosv_g_instruction_manager_awvalid),                  //   input,   width = 1,          .awvalid
		.s0_awready        (niosv_g_instruction_manager_awready),                  //  output,   width = 1,          .awready
		.s0_wdata          (niosv_g_instruction_manager_wdata),                    //   input,  width = 32,          .wdata
		.s0_wstrb          (niosv_g_instruction_manager_wstrb),                    //   input,   width = 4,          .wstrb
		.s0_wlast          (niosv_g_instruction_manager_wlast),                    //   input,   width = 1,          .wlast
		.s0_wvalid         (niosv_g_instruction_manager_wvalid),                   //   input,   width = 1,          .wvalid
		.s0_wready         (niosv_g_instruction_manager_wready),                   //  output,   width = 1,          .wready
		.s0_bresp          (niosv_g_instruction_manager_bresp),                    //  output,   width = 2,          .bresp
		.s0_bvalid         (niosv_g_instruction_manager_bvalid),                   //  output,   width = 1,          .bvalid
		.s0_bready         (niosv_g_instruction_manager_bready),                   //   input,   width = 1,          .bready
		.s0_araddr         (niosv_g_instruction_manager_araddr),                   //   input,  width = 32,          .araddr
		.s0_arlen          (niosv_g_instruction_manager_arlen),                    //   input,   width = 8,          .arlen
		.s0_arsize         (niosv_g_instruction_manager_arsize),                   //   input,   width = 3,          .arsize
		.s0_arburst        (niosv_g_instruction_manager_arburst),                  //   input,   width = 2,          .arburst
		.s0_arprot         (niosv_g_instruction_manager_arprot),                   //   input,   width = 3,          .arprot
		.s0_arvalid        (niosv_g_instruction_manager_arvalid),                  //   input,   width = 1,          .arvalid
		.s0_arready        (niosv_g_instruction_manager_arready),                  //  output,   width = 1,          .arready
		.s0_rdata          (niosv_g_instruction_manager_rdata),                    //  output,  width = 32,          .rdata
		.s0_rresp          (niosv_g_instruction_manager_rresp),                    //  output,   width = 2,          .rresp
		.s0_rlast          (niosv_g_instruction_manager_rlast),                    //  output,   width = 1,          .rlast
		.s0_rvalid         (niosv_g_instruction_manager_rvalid),                   //  output,   width = 1,          .rvalid
		.s0_rready         (niosv_g_instruction_manager_rready),                   //   input,   width = 1,          .rready
		.m0_awuser_addrchk (),                                                     // (terminated),                        
		.m0_awuser_sai     (),                                                     // (terminated),                        
		.m0_wuser_datachk  (),                                                     // (terminated),                        
		.m0_wuser_data     (),                                                     // (terminated),                        
		.m0_wuser_poison   (),                                                     // (terminated),                        
		.m0_aruser_addrchk (),                                                     // (terminated),                        
		.m0_aruser_sai     (),                                                     // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                              // (terminated),                        
		.m0_ruser_data     (1'b0),                                                 // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                 // (terminated),                        
		.s0_awid           (1'b0),                                                 // (terminated),                        
		.s0_awlock         (1'b0),                                                 // (terminated),                        
		.s0_awcache        (4'b0000),                                              // (terminated),                        
		.s0_awuser         (1'b0),                                                 // (terminated),                        
		.s0_awuser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_awuser_sai     (1'b0),                                                 // (terminated),                        
		.s0_awqos          (4'b0000),                                              // (terminated),                        
		.s0_awregion       (4'b0000),                                              // (terminated),                        
		.s0_wuser          (1'b0),                                                 // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                              // (terminated),                        
		.s0_wuser_data     (1'b0),                                                 // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                 // (terminated),                        
		.s0_bid            (),                                                     // (terminated),                        
		.s0_buser          (),                                                     // (terminated),                        
		.s0_arid           (1'b0),                                                 // (terminated),                        
		.s0_arlock         (1'b0),                                                 // (terminated),                        
		.s0_arcache        (4'b0000),                                              // (terminated),                        
		.s0_aruser         (1'b0),                                                 // (terminated),                        
		.s0_aruser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_aruser_sai     (1'b0),                                                 // (terminated),                        
		.s0_arqos          (4'b0000),                                              // (terminated),                        
		.s0_arregion       (4'b0000),                                              // (terminated),                        
		.s0_rid            (),                                                     // (terminated),                        
		.s0_ruser          (),                                                     // (terminated),                        
		.s0_ruser_datachk  (),                                                     // (terminated),                        
		.s0_ruser_data     (),                                                     // (terminated),                        
		.s0_ruser_poison   (),                                                     // (terminated),                        
		.m0_awakeup        (),                                                     // (terminated),                        
		.m0_awtrace        (),                                                     // (terminated),                        
		.m0_artrace        (),                                                     // (terminated),                        
		.m0_wpoison        (),                                                     // (terminated),                        
		.m0_wdatachk       (),                                                     // (terminated),                        
		.m0_wtrace         (),                                                     // (terminated),                        
		.m0_btrace         (1'b0),                                                 // (terminated),                        
		.m0_rpoison        (1'b0),                                                 // (terminated),                        
		.m0_rdatachk       (4'b0000),                                              // (terminated),                        
		.m0_rtrace         (1'b0),                                                 // (terminated),                        
		.m0_wid            (),                                                     // (terminated),                        
		.m0_ardomain       (),                                                     // (terminated),                        
		.m0_arsnoop        (),                                                     // (terminated),                        
		.m0_arbar          (),                                                     // (terminated),                        
		.m0_awdomain       (),                                                     // (terminated),                        
		.m0_awsnoop        (),                                                     // (terminated),                        
		.m0_awbar          (),                                                     // (terminated),                        
		.m0_awunique       (),                                                     // (terminated),                        
		.s0_awakeup        (1'b0),                                                 // (terminated),                        
		.s0_awtrace        (1'b0),                                                 // (terminated),                        
		.s0_artrace        (1'b0),                                                 // (terminated),                        
		.s0_wpoison        (1'b0),                                                 // (terminated),                        
		.s0_wdatachk       (4'b0000),                                              // (terminated),                        
		.s0_wtrace         (1'b0),                                                 // (terminated),                        
		.s0_btrace         (),                                                     // (terminated),                        
		.s0_rpoison        (),                                                     // (terminated),                        
		.s0_rdatachk       (),                                                     // (terminated),                        
		.s0_rtrace         (),                                                     // (terminated),                        
		.s0_wid            (1'b0),                                                 // (terminated),                        
		.s0_ardomain       (2'b00),                                                // (terminated),                        
		.s0_arsnoop        (4'b0000),                                              // (terminated),                        
		.s0_arbar          (2'b00),                                                // (terminated),                        
		.s0_awdomain       (2'b00),                                                // (terminated),                        
		.s0_awsnoop        (3'b000),                                               // (terminated),                        
		.s0_awbar          (2'b00),                                                // (terminated),                        
		.s0_awunique       (1'b0)                                                  // (terminated),                        
	);

	nios_system_altera_merlin_axi_translator_1974_xfkiwxi #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (1),
		.USE_M0_AWREGION                   (0),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (0),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (0),
		.USE_M0_AWPROT                     (0),
		.USE_S0_AWPROT                     (1),
		.USE_S0_AWQOS                      (1),
		.USE_M0_AWQOS                      (0),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (1),
		.USE_M0_ARREGION                   (0),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (0),
		.USE_M0_ARCACHE                    (0),
		.USE_M0_ARQOS                      (0),
		.USE_M0_ARPROT                     (0),
		.USE_S0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (1),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.USE_S0_AWUSER                     (1),
		.USE_S0_ARUSER                     (1),
		.USE_S0_WUSER                      (1),
		.USE_S0_RUSER                      (1),
		.USE_S0_BUSER                      (1),
		.USE_M0_AWUSER                     (0),
		.USE_M0_ARUSER                     (0),
		.USE_M0_WUSER                      (0),
		.USE_M0_RUSER                      (0),
		.USE_M0_BUSER                      (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_M0_AWAKEUP                    (0),
		.USE_M0_WPOISON                    (0),
		.USE_M0_RPOISON                    (0),
		.USE_M0_AWTRACE                    (0),
		.USE_M0_ARTRACE                    (0),
		.USE_M0_WTRACE                     (0),
		.USE_M0_BTRACE                     (0),
		.USE_M0_RTRACE                     (0),
		.USE_M0_WDATACHK                   (0),
		.USE_M0_RDATACHK                   (0),
		.USE_M0_AWUNIQUE                   (0),
		.USE_S0_AWAKEUP                    (0),
		.USE_S0_WPOISON                    (0),
		.USE_S0_RPOISON                    (0),
		.USE_S0_AWTRACE                    (0),
		.USE_S0_ARTRACE                    (0),
		.USE_S0_WTRACE                     (0),
		.USE_S0_BTRACE                     (0),
		.USE_S0_RTRACE                     (0),
		.USE_S0_WDATACHK                   (0),
		.USE_S0_RDATACHK                   (0),
		.USE_S0_AWUSER_ADDRCHK             (1),
		.USE_S0_AWUSER_SAI                 (1),
		.USE_S0_ARUSER_ADDRCHK             (1),
		.USE_S0_ARUSER_SAI                 (1),
		.USE_S0_WUSER_DATACHK              (1),
		.USE_S0_WUSER_POISON               (1),
		.USE_S0_RUSER_DATACHK              (1),
		.USE_S0_WUSER_DATA                 (1),
		.USE_S0_RUSER_DATA                 (1),
		.USE_S0_RUSER_POISON               (1),
		.USE_S0_AWUNIQUE                   (1),
		.M0_ID_WIDTH                       (4),
		.DATA_WIDTH                        (64),
		.M0_SAI_WIDTH                      (1),
		.S0_SAI_WIDTH                      (1),
		.USER_DATA_WIDTH                   (1),
		.M0_USER_ADDRCHK_WIDTH             (1),
		.S0_USER_ADDRCHK_WIDTH             (1),
		.S0_ID_WIDTH                       (4),
		.M0_ADDR_WIDTH                     (26),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (26),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) sdram_axi4_slave_translator (
		.aclk              (iopll_outclk0_clk),                                    //   input,   width = 1,       clk.clk
		.aresetn           (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (sdram_axi4_slave_awid),                                //  output,   width = 4,        m0.awid
		.m0_awaddr         (sdram_axi4_slave_awaddr),                              //  output,  width = 26,          .awaddr
		.m0_awlen          (sdram_axi4_slave_awlen),                               //  output,   width = 8,          .awlen
		.m0_awsize         (sdram_axi4_slave_awsize),                              //  output,   width = 3,          .awsize
		.m0_awburst        (sdram_axi4_slave_awburst),                             //  output,   width = 2,          .awburst
		.m0_awvalid        (sdram_axi4_slave_awvalid),                             //  output,   width = 1,          .awvalid
		.m0_awready        (sdram_axi4_slave_awready),                             //   input,   width = 1,          .awready
		.m0_wdata          (sdram_axi4_slave_wdata),                               //  output,  width = 64,          .wdata
		.m0_wstrb          (sdram_axi4_slave_wstrb),                               //  output,   width = 8,          .wstrb
		.m0_wlast          (sdram_axi4_slave_wlast),                               //  output,   width = 1,          .wlast
		.m0_wvalid         (sdram_axi4_slave_wvalid),                              //  output,   width = 1,          .wvalid
		.m0_wready         (sdram_axi4_slave_wready),                              //   input,   width = 1,          .wready
		.m0_bid            (sdram_axi4_slave_bid),                                 //   input,   width = 4,          .bid
		.m0_bresp          (sdram_axi4_slave_bresp),                               //   input,   width = 2,          .bresp
		.m0_bvalid         (sdram_axi4_slave_bvalid),                              //   input,   width = 1,          .bvalid
		.m0_bready         (sdram_axi4_slave_bready),                              //  output,   width = 1,          .bready
		.m0_arid           (sdram_axi4_slave_arid),                                //  output,   width = 4,          .arid
		.m0_araddr         (sdram_axi4_slave_araddr),                              //  output,  width = 26,          .araddr
		.m0_arlen          (sdram_axi4_slave_arlen),                               //  output,   width = 8,          .arlen
		.m0_arsize         (sdram_axi4_slave_arsize),                              //  output,   width = 3,          .arsize
		.m0_arburst        (sdram_axi4_slave_arburst),                             //  output,   width = 2,          .arburst
		.m0_arvalid        (sdram_axi4_slave_arvalid),                             //  output,   width = 1,          .arvalid
		.m0_arready        (sdram_axi4_slave_arready),                             //   input,   width = 1,          .arready
		.m0_rid            (sdram_axi4_slave_rid),                                 //   input,   width = 4,          .rid
		.m0_rdata          (sdram_axi4_slave_rdata),                               //   input,  width = 64,          .rdata
		.m0_rresp          (sdram_axi4_slave_rresp),                               //   input,   width = 2,          .rresp
		.m0_rlast          (sdram_axi4_slave_rlast),                               //   input,   width = 1,          .rlast
		.m0_rvalid         (sdram_axi4_slave_rvalid),                              //   input,   width = 1,          .rvalid
		.m0_rready         (sdram_axi4_slave_rready),                              //  output,   width = 1,          .rready
		.s0_awid           (sdram_axi4_slave_agent_altera_axi_master_awid),        //   input,   width = 4,        s0.awid
		.s0_awaddr         (sdram_axi4_slave_agent_altera_axi_master_awaddr),      //   input,  width = 26,          .awaddr
		.s0_awlen          (sdram_axi4_slave_agent_altera_axi_master_awlen),       //   input,   width = 8,          .awlen
		.s0_awsize         (sdram_axi4_slave_agent_altera_axi_master_awsize),      //   input,   width = 3,          .awsize
		.s0_awburst        (sdram_axi4_slave_agent_altera_axi_master_awburst),     //   input,   width = 2,          .awburst
		.s0_awlock         (sdram_axi4_slave_agent_altera_axi_master_awlock),      //   input,   width = 1,          .awlock
		.s0_awcache        (sdram_axi4_slave_agent_altera_axi_master_awcache),     //   input,   width = 4,          .awcache
		.s0_awprot         (sdram_axi4_slave_agent_altera_axi_master_awprot),      //   input,   width = 3,          .awprot
		.s0_awuser         (sdram_axi4_slave_agent_altera_axi_master_awuser),      //   input,   width = 1,          .awuser
		.s0_awqos          (sdram_axi4_slave_agent_altera_axi_master_awqos),       //   input,   width = 4,          .awqos
		.s0_awregion       (sdram_axi4_slave_agent_altera_axi_master_awregion),    //   input,   width = 4,          .awregion
		.s0_awvalid        (sdram_axi4_slave_agent_altera_axi_master_awvalid),     //   input,   width = 1,          .awvalid
		.s0_awready        (sdram_axi4_slave_agent_altera_axi_master_awready),     //  output,   width = 1,          .awready
		.s0_wdata          (sdram_axi4_slave_agent_altera_axi_master_wdata),       //   input,  width = 64,          .wdata
		.s0_wstrb          (sdram_axi4_slave_agent_altera_axi_master_wstrb),       //   input,   width = 8,          .wstrb
		.s0_wlast          (sdram_axi4_slave_agent_altera_axi_master_wlast),       //   input,   width = 1,          .wlast
		.s0_wvalid         (sdram_axi4_slave_agent_altera_axi_master_wvalid),      //   input,   width = 1,          .wvalid
		.s0_wuser          (sdram_axi4_slave_agent_altera_axi_master_wuser),       //   input,   width = 1,          .wuser
		.s0_wready         (sdram_axi4_slave_agent_altera_axi_master_wready),      //  output,   width = 1,          .wready
		.s0_bid            (sdram_axi4_slave_agent_altera_axi_master_bid),         //  output,   width = 4,          .bid
		.s0_bresp          (sdram_axi4_slave_agent_altera_axi_master_bresp),       //  output,   width = 2,          .bresp
		.s0_buser          (sdram_axi4_slave_agent_altera_axi_master_buser),       //  output,   width = 1,          .buser
		.s0_bvalid         (sdram_axi4_slave_agent_altera_axi_master_bvalid),      //  output,   width = 1,          .bvalid
		.s0_bready         (sdram_axi4_slave_agent_altera_axi_master_bready),      //   input,   width = 1,          .bready
		.s0_arid           (sdram_axi4_slave_agent_altera_axi_master_arid),        //   input,   width = 4,          .arid
		.s0_araddr         (sdram_axi4_slave_agent_altera_axi_master_araddr),      //   input,  width = 26,          .araddr
		.s0_arlen          (sdram_axi4_slave_agent_altera_axi_master_arlen),       //   input,   width = 8,          .arlen
		.s0_arsize         (sdram_axi4_slave_agent_altera_axi_master_arsize),      //   input,   width = 3,          .arsize
		.s0_arburst        (sdram_axi4_slave_agent_altera_axi_master_arburst),     //   input,   width = 2,          .arburst
		.s0_arlock         (sdram_axi4_slave_agent_altera_axi_master_arlock),      //   input,   width = 1,          .arlock
		.s0_arcache        (sdram_axi4_slave_agent_altera_axi_master_arcache),     //   input,   width = 4,          .arcache
		.s0_arprot         (sdram_axi4_slave_agent_altera_axi_master_arprot),      //   input,   width = 3,          .arprot
		.s0_aruser         (sdram_axi4_slave_agent_altera_axi_master_aruser),      //   input,   width = 1,          .aruser
		.s0_arqos          (sdram_axi4_slave_agent_altera_axi_master_arqos),       //   input,   width = 4,          .arqos
		.s0_arregion       (sdram_axi4_slave_agent_altera_axi_master_arregion),    //   input,   width = 4,          .arregion
		.s0_arvalid        (sdram_axi4_slave_agent_altera_axi_master_arvalid),     //   input,   width = 1,          .arvalid
		.s0_arready        (sdram_axi4_slave_agent_altera_axi_master_arready),     //  output,   width = 1,          .arready
		.s0_rid            (sdram_axi4_slave_agent_altera_axi_master_rid),         //  output,   width = 4,          .rid
		.s0_rdata          (sdram_axi4_slave_agent_altera_axi_master_rdata),       //  output,  width = 64,          .rdata
		.s0_rresp          (sdram_axi4_slave_agent_altera_axi_master_rresp),       //  output,   width = 2,          .rresp
		.s0_rlast          (sdram_axi4_slave_agent_altera_axi_master_rlast),       //  output,   width = 1,          .rlast
		.s0_rvalid         (sdram_axi4_slave_agent_altera_axi_master_rvalid),      //  output,   width = 1,          .rvalid
		.s0_rready         (sdram_axi4_slave_agent_altera_axi_master_rready),      //   input,   width = 1,          .rready
		.s0_ruser          (sdram_axi4_slave_agent_altera_axi_master_ruser),       //  output,   width = 1,          .ruser
		.m0_awlock         (),                                                     // (terminated),                        
		.m0_awcache        (),                                                     // (terminated),                        
		.m0_awprot         (),                                                     // (terminated),                        
		.m0_awuser         (),                                                     // (terminated),                        
		.m0_awuser_addrchk (),                                                     // (terminated),                        
		.m0_awuser_sai     (),                                                     // (terminated),                        
		.m0_awqos          (),                                                     // (terminated),                        
		.m0_awregion       (),                                                     // (terminated),                        
		.m0_wuser          (),                                                     // (terminated),                        
		.m0_wuser_datachk  (),                                                     // (terminated),                        
		.m0_wuser_data     (),                                                     // (terminated),                        
		.m0_wuser_poison   (),                                                     // (terminated),                        
		.m0_buser          (1'b0),                                                 // (terminated),                        
		.m0_arlock         (),                                                     // (terminated),                        
		.m0_arcache        (),                                                     // (terminated),                        
		.m0_arprot         (),                                                     // (terminated),                        
		.m0_aruser         (),                                                     // (terminated),                        
		.m0_aruser_addrchk (),                                                     // (terminated),                        
		.m0_aruser_sai     (),                                                     // (terminated),                        
		.m0_arqos          (),                                                     // (terminated),                        
		.m0_arregion       (),                                                     // (terminated),                        
		.m0_ruser          (1'b0),                                                 // (terminated),                        
		.m0_ruser_datachk  (8'b00000000),                                          // (terminated),                        
		.m0_ruser_data     (1'b0),                                                 // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                 // (terminated),                        
		.s0_awuser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_awuser_sai     (1'b0),                                                 // (terminated),                        
		.s0_wuser_datachk  (8'b00000000),                                          // (terminated),                        
		.s0_wuser_data     (1'b0),                                                 // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                 // (terminated),                        
		.s0_aruser_addrchk (1'b0),                                                 // (terminated),                        
		.s0_aruser_sai     (1'b0),                                                 // (terminated),                        
		.s0_ruser_datachk  (),                                                     // (terminated),                        
		.s0_ruser_data     (),                                                     // (terminated),                        
		.s0_ruser_poison   (),                                                     // (terminated),                        
		.m0_awakeup        (),                                                     // (terminated),                        
		.m0_awtrace        (),                                                     // (terminated),                        
		.m0_artrace        (),                                                     // (terminated),                        
		.m0_wpoison        (),                                                     // (terminated),                        
		.m0_wdatachk       (),                                                     // (terminated),                        
		.m0_wtrace         (),                                                     // (terminated),                        
		.m0_btrace         (1'b0),                                                 // (terminated),                        
		.m0_rpoison        (1'b0),                                                 // (terminated),                        
		.m0_rdatachk       (8'b00000000),                                          // (terminated),                        
		.m0_rtrace         (1'b0),                                                 // (terminated),                        
		.m0_wid            (),                                                     // (terminated),                        
		.m0_ardomain       (),                                                     // (terminated),                        
		.m0_arsnoop        (),                                                     // (terminated),                        
		.m0_arbar          (),                                                     // (terminated),                        
		.m0_awdomain       (),                                                     // (terminated),                        
		.m0_awsnoop        (),                                                     // (terminated),                        
		.m0_awbar          (),                                                     // (terminated),                        
		.m0_awunique       (),                                                     // (terminated),                        
		.s0_awakeup        (1'b0),                                                 // (terminated),                        
		.s0_awtrace        (1'b0),                                                 // (terminated),                        
		.s0_artrace        (1'b0),                                                 // (terminated),                        
		.s0_wpoison        (1'b0),                                                 // (terminated),                        
		.s0_wdatachk       (8'b00000000),                                          // (terminated),                        
		.s0_wtrace         (1'b0),                                                 // (terminated),                        
		.s0_btrace         (),                                                     // (terminated),                        
		.s0_rpoison        (),                                                     // (terminated),                        
		.s0_rdatachk       (),                                                     // (terminated),                        
		.s0_rtrace         (),                                                     // (terminated),                        
		.s0_wid            (4'b0000),                                              // (terminated),                        
		.s0_ardomain       (2'b00),                                                // (terminated),                        
		.s0_arsnoop        (4'b0000),                                              // (terminated),                        
		.s0_arbar          (2'b00),                                                // (terminated),                        
		.s0_awdomain       (2'b00),                                                // (terminated),                        
		.s0_awsnoop        (3'b000),                                               // (terminated),                        
		.s0_awbar          (2'b00),                                                // (terminated),                        
		.s0_awunique       (1'b0)                                                  // (terminated),                        
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (16),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) niosv_g_dm_agent_translator (
		.clk                    (iopll_outclk0_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (niosv_g_dm_agent_agent_m0_address),                   //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (niosv_g_dm_agent_agent_m0_burstcount),                //   input,   width = 3,                         .burstcount
		.uav_read               (niosv_g_dm_agent_agent_m0_read),                      //   input,   width = 1,                         .read
		.uav_write              (niosv_g_dm_agent_agent_m0_write),                     //   input,   width = 1,                         .write
		.uav_waitrequest        (niosv_g_dm_agent_agent_m0_waitrequest),               //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (niosv_g_dm_agent_agent_m0_readdatavalid),             //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (niosv_g_dm_agent_agent_m0_byteenable),                //   input,   width = 4,                         .byteenable
		.uav_readdata           (niosv_g_dm_agent_agent_m0_readdata),                  //  output,  width = 32,                         .readdata
		.uav_writedata          (niosv_g_dm_agent_agent_m0_writedata),                 //   input,  width = 32,                         .writedata
		.uav_lock               (niosv_g_dm_agent_agent_m0_lock),                      //   input,   width = 1,                         .lock
		.uav_debugaccess        (niosv_g_dm_agent_agent_m0_debugaccess),               //   input,   width = 1,                         .debugaccess
		.av_address             (niosv_g_dm_agent_address),                            //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write               (niosv_g_dm_agent_write),                              //  output,   width = 1,                         .write
		.av_read                (niosv_g_dm_agent_read),                               //  output,   width = 1,                         .read
		.av_readdata            (niosv_g_dm_agent_readdata),                           //   input,  width = 32,                         .readdata
		.av_writedata           (niosv_g_dm_agent_writedata),                          //  output,  width = 32,                         .writedata
		.av_readdatavalid       (niosv_g_dm_agent_readdatavalid),                      //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (niosv_g_dm_agent_waitrequest),                        //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                    // (terminated),                                       
		.av_beginbursttransfer  (),                                                    // (terminated),                                       
		.av_burstcount          (),                                                    // (terminated),                                       
		.av_byteenable          (),                                                    // (terminated),                                       
		.av_writebyteenable     (),                                                    // (terminated),                                       
		.av_lock                (),                                                    // (terminated),                                       
		.av_chipselect          (),                                                    // (terminated),                                       
		.av_clken               (),                                                    // (terminated),                                       
		.uav_clken              (1'b0),                                                // (terminated),                                       
		.av_debugaccess         (),                                                    // (terminated),                                       
		.av_outputenable        (),                                                    // (terminated),                                       
		.uav_response           (),                                                    // (terminated),                                       
		.av_response            (2'b00),                                               // (terminated),                                       
		.uav_writeresponsevalid (),                                                    // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                 // (terminated),                                       
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (18),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) mm_bridge_peripheral_s0_translator (
		.clk                    (iopll_outclk0_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (mm_bridge_peripheral_s0_agent_m0_address),            //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (mm_bridge_peripheral_s0_agent_m0_burstcount),         //   input,   width = 3,                         .burstcount
		.uav_read               (mm_bridge_peripheral_s0_agent_m0_read),               //   input,   width = 1,                         .read
		.uav_write              (mm_bridge_peripheral_s0_agent_m0_write),              //   input,   width = 1,                         .write
		.uav_waitrequest        (mm_bridge_peripheral_s0_agent_m0_waitrequest),        //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (mm_bridge_peripheral_s0_agent_m0_readdatavalid),      //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (mm_bridge_peripheral_s0_agent_m0_byteenable),         //   input,   width = 4,                         .byteenable
		.uav_readdata           (mm_bridge_peripheral_s0_agent_m0_readdata),           //  output,  width = 32,                         .readdata
		.uav_writedata          (mm_bridge_peripheral_s0_agent_m0_writedata),          //   input,  width = 32,                         .writedata
		.uav_lock               (mm_bridge_peripheral_s0_agent_m0_lock),               //   input,   width = 1,                         .lock
		.uav_debugaccess        (mm_bridge_peripheral_s0_agent_m0_debugaccess),        //   input,   width = 1,                         .debugaccess
		.av_address             (mm_bridge_peripheral_s0_address),                     //  output,  width = 18,      avalon_anti_slave_0.address
		.av_write               (mm_bridge_peripheral_s0_write),                       //  output,   width = 1,                         .write
		.av_read                (mm_bridge_peripheral_s0_read),                        //  output,   width = 1,                         .read
		.av_readdata            (mm_bridge_peripheral_s0_readdata),                    //   input,  width = 32,                         .readdata
		.av_writedata           (mm_bridge_peripheral_s0_writedata),                   //  output,  width = 32,                         .writedata
		.av_burstcount          (mm_bridge_peripheral_s0_burstcount),                  //  output,   width = 1,                         .burstcount
		.av_byteenable          (mm_bridge_peripheral_s0_byteenable),                  //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (mm_bridge_peripheral_s0_readdatavalid),               //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (mm_bridge_peripheral_s0_waitrequest),                 //   input,   width = 1,                         .waitrequest
		.av_debugaccess         (mm_bridge_peripheral_s0_debugaccess),                 //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                    // (terminated),                                       
		.av_beginbursttransfer  (),                                                    // (terminated),                                       
		.av_writebyteenable     (),                                                    // (terminated),                                       
		.av_lock                (),                                                    // (terminated),                                       
		.av_chipselect          (),                                                    // (terminated),                                       
		.av_clken               (),                                                    // (terminated),                                       
		.uav_clken              (1'b0),                                                // (terminated),                                       
		.av_outputenable        (),                                                    // (terminated),                                       
		.uav_response           (),                                                    // (terminated),                                       
		.av_response            (2'b00),                                               // (terminated),                                       
		.uav_writeresponsevalid (),                                                    // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                 // (terminated),                                       
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (17),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) onchip_memory_s1_translator (
		.clk                    (iopll_outclk0_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (onchip_memory_s1_agent_m0_address),                   //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (onchip_memory_s1_agent_m0_burstcount),                //   input,   width = 3,                         .burstcount
		.uav_read               (onchip_memory_s1_agent_m0_read),                      //   input,   width = 1,                         .read
		.uav_write              (onchip_memory_s1_agent_m0_write),                     //   input,   width = 1,                         .write
		.uav_waitrequest        (onchip_memory_s1_agent_m0_waitrequest),               //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (onchip_memory_s1_agent_m0_readdatavalid),             //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (onchip_memory_s1_agent_m0_byteenable),                //   input,   width = 4,                         .byteenable
		.uav_readdata           (onchip_memory_s1_agent_m0_readdata),                  //  output,  width = 32,                         .readdata
		.uav_writedata          (onchip_memory_s1_agent_m0_writedata),                 //   input,  width = 32,                         .writedata
		.uav_lock               (onchip_memory_s1_agent_m0_lock),                      //   input,   width = 1,                         .lock
		.uav_debugaccess        (onchip_memory_s1_agent_m0_debugaccess),               //   input,   width = 1,                         .debugaccess
		.av_address             (onchip_memory_s1_address),                            //  output,  width = 17,      avalon_anti_slave_0.address
		.av_write               (onchip_memory_s1_write),                              //  output,   width = 1,                         .write
		.av_read                (onchip_memory_s1_read),                               //  output,   width = 1,                         .read
		.av_readdata            (onchip_memory_s1_readdata),                           //   input,  width = 32,                         .readdata
		.av_writedata           (onchip_memory_s1_writedata),                          //  output,  width = 32,                         .writedata
		.av_byteenable          (onchip_memory_s1_byteenable),                         //  output,   width = 4,                         .byteenable
		.av_begintransfer       (),                                                    // (terminated),                                       
		.av_beginbursttransfer  (),                                                    // (terminated),                                       
		.av_burstcount          (),                                                    // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                // (terminated),                                       
		.av_waitrequest         (1'b0),                                                // (terminated),                                       
		.av_writebyteenable     (),                                                    // (terminated),                                       
		.av_lock                (),                                                    // (terminated),                                       
		.av_chipselect          (),                                                    // (terminated),                                       
		.av_clken               (),                                                    // (terminated),                                       
		.uav_clken              (1'b0),                                                // (terminated),                                       
		.av_debugaccess         (),                                                    // (terminated),                                       
		.av_outputenable        (),                                                    // (terminated),                                       
		.uav_response           (),                                                    // (terminated),                                       
		.av_response            (2'b00),                                               // (terminated),                                       
		.uav_writeresponsevalid (),                                                    // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                 // (terminated),                                       
	);

	nios_system_altera_merlin_slave_translator_191_xg7rzxi #(
		.AV_ADDRESS_W                   (6),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) niosv_g_timer_sw_agent_translator (
		.clk                    (iopll_outclk0_clk),                                   //   input,   width = 1,                      clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (niosv_g_timer_sw_agent_agent_m0_address),             //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (niosv_g_timer_sw_agent_agent_m0_burstcount),          //   input,   width = 3,                         .burstcount
		.uav_read               (niosv_g_timer_sw_agent_agent_m0_read),                //   input,   width = 1,                         .read
		.uav_write              (niosv_g_timer_sw_agent_agent_m0_write),               //   input,   width = 1,                         .write
		.uav_waitrequest        (niosv_g_timer_sw_agent_agent_m0_waitrequest),         //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (niosv_g_timer_sw_agent_agent_m0_readdatavalid),       //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (niosv_g_timer_sw_agent_agent_m0_byteenable),          //   input,   width = 4,                         .byteenable
		.uav_readdata           (niosv_g_timer_sw_agent_agent_m0_readdata),            //  output,  width = 32,                         .readdata
		.uav_writedata          (niosv_g_timer_sw_agent_agent_m0_writedata),           //   input,  width = 32,                         .writedata
		.uav_lock               (niosv_g_timer_sw_agent_agent_m0_lock),                //   input,   width = 1,                         .lock
		.uav_debugaccess        (niosv_g_timer_sw_agent_agent_m0_debugaccess),         //   input,   width = 1,                         .debugaccess
		.av_address             (niosv_g_timer_sw_agent_address),                      //  output,   width = 6,      avalon_anti_slave_0.address
		.av_write               (niosv_g_timer_sw_agent_write),                        //  output,   width = 1,                         .write
		.av_read                (niosv_g_timer_sw_agent_read),                         //  output,   width = 1,                         .read
		.av_readdata            (niosv_g_timer_sw_agent_readdata),                     //   input,  width = 32,                         .readdata
		.av_writedata           (niosv_g_timer_sw_agent_writedata),                    //  output,  width = 32,                         .writedata
		.av_byteenable          (niosv_g_timer_sw_agent_byteenable),                   //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (niosv_g_timer_sw_agent_readdatavalid),                //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (niosv_g_timer_sw_agent_waitrequest),                  //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                    // (terminated),                                       
		.av_beginbursttransfer  (),                                                    // (terminated),                                       
		.av_burstcount          (),                                                    // (terminated),                                       
		.av_writebyteenable     (),                                                    // (terminated),                                       
		.av_lock                (),                                                    // (terminated),                                       
		.av_chipselect          (),                                                    // (terminated),                                       
		.av_clken               (),                                                    // (terminated),                                       
		.uav_clken              (1'b0),                                                // (terminated),                                       
		.av_debugaccess         (),                                                    // (terminated),                                       
		.av_outputenable        (),                                                    // (terminated),                                       
		.uav_response           (),                                                    // (terminated),                                       
		.av_response            (2'b00),                                               // (terminated),                                       
		.uav_writeresponsevalid (),                                                    // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                 // (terminated),                                       
	);

	nios_system_altera_merlin_master_agent_1931_szfayly #(
		.PKT_WUNIQUE               (387),
		.PKT_DOMAIN_H              (386),
		.PKT_DOMAIN_L              (385),
		.PKT_SNOOP_H               (384),
		.PKT_SNOOP_L               (381),
		.PKT_BARRIER_H             (380),
		.PKT_BARRIER_L             (379),
		.PKT_ORI_BURST_SIZE_H      (378),
		.PKT_ORI_BURST_SIZE_L      (376),
		.PKT_RESPONSE_STATUS_H     (375),
		.PKT_RESPONSE_STATUS_L     (374),
		.PKT_QOS_H                 (359),
		.PKT_QOS_L                 (356),
		.PKT_DATA_SIDEBAND_H       (354),
		.PKT_DATA_SIDEBAND_L       (354),
		.PKT_ADDR_SIDEBAND_H       (353),
		.PKT_ADDR_SIDEBAND_L       (353),
		.PKT_BURST_TYPE_H          (352),
		.PKT_BURST_TYPE_L          (351),
		.PKT_CACHE_H               (373),
		.PKT_CACHE_L               (370),
		.PKT_THREAD_ID_H           (366),
		.PKT_THREAD_ID_L           (366),
		.PKT_BURST_SIZE_H          (350),
		.PKT_BURST_SIZE_L          (348),
		.PKT_TRANS_EXCLUSIVE       (325),
		.PKT_TRANS_LOCK            (324),
		.PKT_BEGIN_BURST           (355),
		.PKT_PROTECTION_H          (369),
		.PKT_PROTECTION_L          (367),
		.PKT_BURSTWRAP_H           (347),
		.PKT_BURSTWRAP_L           (340),
		.PKT_BYTE_CNT_H            (339),
		.PKT_BYTE_CNT_L            (326),
		.PKT_ADDR_H                (319),
		.PKT_ADDR_L                (288),
		.PKT_TRANS_COMPRESSED_READ (320),
		.PKT_TRANS_POSTED          (321),
		.PKT_TRANS_WRITE           (322),
		.PKT_TRANS_READ            (323),
		.PKT_DATA_H                (255),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (287),
		.PKT_BYTEEN_L              (256),
		.PKT_SRC_ID_H              (362),
		.PKT_SRC_ID_L              (360),
		.PKT_DEST_ID_H             (365),
		.PKT_DEST_ID_L             (363),
		.PKT_POISON_H              (388),
		.PKT_POISON_L              (388),
		.PKT_DATACHK_H             (389),
		.PKT_DATACHK_L             (389),
		.PKT_ADDRCHK_H             (392),
		.PKT_ADDRCHK_L             (391),
		.PKT_SAI_H                 (393),
		.PKT_SAI_L                 (393),
		.PKT_USER_DATA_H           (390),
		.PKT_USER_DATA_L           (390),
		.PKT_ATRACE                (403),
		.PKT_TRACE                 (404),
		.PKT_AWAKEUP               (405),
		.ST_DATA_W                 (406),
		.ST_CHANNEL_W              (6),
		.AV_BURSTCOUNT_W           (11),
		.SUPPRESS_0_BYTEEN_RSP     (0),
		.ID                        (0),
		.BURSTWRAP_VALUE           (255),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.OPTIMIZED_READS_WITH_BE   (0)
	) intel_vvp_vfr_av_mm_mem_read_host_agent (
		.clk                   (iopll_outclk0_clk),                                                                    //   input,    width = 1,       clk.clk
		.reset                 (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                  //   input,    width = 1, clk_reset.reset
		.av_address            (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_address),       //   input,   width = 32,        av.address
		.av_write              (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_writedata),     //   input,  width = 256,          .writedata
		.av_readdata           (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdata),      //  output,  width = 256,          .readdata
		.av_waitrequest        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_byteenable),    //   input,   width = 32,          .byteenable
		.av_burstcount         (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_burstcount),    //   input,   width = 11,          .burstcount
		.av_debugaccess        (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (intel_vvp_vfr_av_mm_mem_read_host_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_data),                                      //  output,  width = 406,          .data
		.cp_startofpacket      (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_data),                               //   input,  width = 406,          .data
		.rp_channel            (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_channel),                            //   input,    width = 6,          .channel
		.rp_startofpacket      (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                                     // (terminated),                         
		.av_writeresponsevalid ()                                                                                      // (terminated),                         
	);

	nios_system_altera_merlin_axi_master_ni_19100_y3ctica #(
		.ID_WIDTH                  (1),
		.ADDR_WIDTH                (32),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (1),
		.READ_ISSUING_CAPABILITY   (1),
		.PKT_BEGIN_BURST           (103),
		.PKT_CACHE_H               (121),
		.PKT_CACHE_L               (118),
		.PKT_ADDR_SIDEBAND_H       (101),
		.PKT_ADDR_SIDEBAND_L       (101),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_BURST_TYPE_H          (100),
		.PKT_BURST_TYPE_L          (99),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (110),
		.PKT_SRC_ID_L              (108),
		.PKT_DEST_ID_H             (113),
		.PKT_DEST_ID_L             (111),
		.PKT_THREAD_ID_H           (114),
		.PKT_THREAD_ID_L           (114),
		.PKT_QOS_L                 (104),
		.PKT_QOS_H                 (107),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_DATA_SIDEBAND_H       (102),
		.PKT_DATA_SIDEBAND_L       (102),
		.PKT_DOMAIN_H              (134),
		.PKT_DOMAIN_L              (133),
		.PKT_SNOOP_H               (132),
		.PKT_SNOOP_L               (129),
		.PKT_BARRIER_H             (128),
		.PKT_BARRIER_L             (127),
		.PKT_WUNIQUE               (135),
		.PKT_EOP_OOO               (142),
		.PKT_SOP_OOO               (143),
		.PKT_ATRACE                (151),
		.PKT_TRACE                 (152),
		.PKT_AWAKEUP               (153),
		.PKT_POISON_H              (136),
		.PKT_POISON_L              (136),
		.PKT_DATACHK_H             (137),
		.PKT_DATACHK_L             (137),
		.PKT_ADDRCHK_H             (140),
		.PKT_ADDRCHK_L             (139),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.PKT_USER_DATA_H           (138),
		.PKT_USER_DATA_L           (138),
		.ST_DATA_W                 (154),
		.ST_CHANNEL_W              (6),
		.ID                        (1),
		.SYNC_RESET                (1),
		.DATA_USER_WIDTH           (1)
	) niosv_g_data_manager_agent (
		.aclk                   (iopll_outclk0_clk),                                    //   input,    width = 1,              clk.clk
		.aresetn                (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (niosv_g_data_manager_agent_write_cp_valid),            //  output,    width = 1,         write_cp.valid
		.write_cp_data          (niosv_g_data_manager_agent_write_cp_data),             //  output,  width = 154,                 .data
		.write_cp_startofpacket (niosv_g_data_manager_agent_write_cp_startofpacket),    //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (niosv_g_data_manager_agent_write_cp_endofpacket),      //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (niosv_g_data_manager_agent_write_cp_ready),            //   input,    width = 1,                 .ready
		.write_rp_valid         (rsp_mux_001_src_valid),                                //   input,    width = 1,         write_rp.valid
		.write_rp_data          (rsp_mux_001_src_data),                                 //   input,  width = 154,                 .data
		.write_rp_channel       (rsp_mux_001_src_channel),                              //   input,    width = 6,                 .channel
		.write_rp_startofpacket (rsp_mux_001_src_startofpacket),                        //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_001_src_endofpacket),                          //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (rsp_mux_001_src_ready),                                //  output,    width = 1,                 .ready
		.read_cp_valid          (niosv_g_data_manager_agent_read_cp_valid),             //  output,    width = 1,          read_cp.valid
		.read_cp_data           (niosv_g_data_manager_agent_read_cp_data),              //  output,  width = 154,                 .data
		.read_cp_startofpacket  (niosv_g_data_manager_agent_read_cp_startofpacket),     //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (niosv_g_data_manager_agent_read_cp_endofpacket),       //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (niosv_g_data_manager_agent_read_cp_ready),             //   input,    width = 1,                 .ready
		.read_rp_valid          (rsp_mux_002_src_valid),                                //   input,    width = 1,          read_rp.valid
		.read_rp_data           (rsp_mux_002_src_data),                                 //   input,  width = 154,                 .data
		.read_rp_channel        (rsp_mux_002_src_channel),                              //   input,    width = 6,                 .channel
		.read_rp_startofpacket  (rsp_mux_002_src_startofpacket),                        //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_002_src_endofpacket),                          //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (rsp_mux_002_src_ready),                                //  output,    width = 1,                 .ready
		.awid                   (niosv_g_data_manager_translator_m0_awid),              //   input,    width = 1, altera_axi_slave.awid
		.awaddr                 (niosv_g_data_manager_translator_m0_awaddr),            //   input,   width = 32,                 .awaddr
		.awlen                  (niosv_g_data_manager_translator_m0_awlen),             //   input,    width = 8,                 .awlen
		.awsize                 (niosv_g_data_manager_translator_m0_awsize),            //   input,    width = 3,                 .awsize
		.awburst                (niosv_g_data_manager_translator_m0_awburst),           //   input,    width = 2,                 .awburst
		.awlock                 (niosv_g_data_manager_translator_m0_awlock),            //   input,    width = 1,                 .awlock
		.awcache                (niosv_g_data_manager_translator_m0_awcache),           //   input,    width = 4,                 .awcache
		.awprot                 (niosv_g_data_manager_translator_m0_awprot),            //   input,    width = 3,                 .awprot
		.awuser                 (niosv_g_data_manager_translator_m0_awuser),            //   input,    width = 1,                 .awuser
		.awqos                  (niosv_g_data_manager_translator_m0_awqos),             //   input,    width = 4,                 .awqos
		.awregion               (niosv_g_data_manager_translator_m0_awregion),          //   input,    width = 4,                 .awregion
		.awvalid                (niosv_g_data_manager_translator_m0_awvalid),           //   input,    width = 1,                 .awvalid
		.awready                (niosv_g_data_manager_translator_m0_awready),           //  output,    width = 1,                 .awready
		.wdata                  (niosv_g_data_manager_translator_m0_wdata),             //   input,   width = 32,                 .wdata
		.wstrb                  (niosv_g_data_manager_translator_m0_wstrb),             //   input,    width = 4,                 .wstrb
		.wlast                  (niosv_g_data_manager_translator_m0_wlast),             //   input,    width = 1,                 .wlast
		.wvalid                 (niosv_g_data_manager_translator_m0_wvalid),            //   input,    width = 1,                 .wvalid
		.wuser                  (niosv_g_data_manager_translator_m0_wuser),             //   input,    width = 1,                 .wuser
		.wready                 (niosv_g_data_manager_translator_m0_wready),            //  output,    width = 1,                 .wready
		.bid                    (niosv_g_data_manager_translator_m0_bid),               //  output,    width = 1,                 .bid
		.bresp                  (niosv_g_data_manager_translator_m0_bresp),             //  output,    width = 2,                 .bresp
		.buser                  (niosv_g_data_manager_translator_m0_buser),             //  output,    width = 1,                 .buser
		.bvalid                 (niosv_g_data_manager_translator_m0_bvalid),            //  output,    width = 1,                 .bvalid
		.bready                 (niosv_g_data_manager_translator_m0_bready),            //   input,    width = 1,                 .bready
		.arid                   (niosv_g_data_manager_translator_m0_arid),              //   input,    width = 1,                 .arid
		.araddr                 (niosv_g_data_manager_translator_m0_araddr),            //   input,   width = 32,                 .araddr
		.arlen                  (niosv_g_data_manager_translator_m0_arlen),             //   input,    width = 8,                 .arlen
		.arsize                 (niosv_g_data_manager_translator_m0_arsize),            //   input,    width = 3,                 .arsize
		.arburst                (niosv_g_data_manager_translator_m0_arburst),           //   input,    width = 2,                 .arburst
		.arlock                 (niosv_g_data_manager_translator_m0_arlock),            //   input,    width = 1,                 .arlock
		.arcache                (niosv_g_data_manager_translator_m0_arcache),           //   input,    width = 4,                 .arcache
		.arprot                 (niosv_g_data_manager_translator_m0_arprot),            //   input,    width = 3,                 .arprot
		.aruser                 (niosv_g_data_manager_translator_m0_aruser),            //   input,    width = 1,                 .aruser
		.arqos                  (niosv_g_data_manager_translator_m0_arqos),             //   input,    width = 4,                 .arqos
		.arregion               (niosv_g_data_manager_translator_m0_arregion),          //   input,    width = 4,                 .arregion
		.arvalid                (niosv_g_data_manager_translator_m0_arvalid),           //   input,    width = 1,                 .arvalid
		.arready                (niosv_g_data_manager_translator_m0_arready),           //  output,    width = 1,                 .arready
		.rid                    (niosv_g_data_manager_translator_m0_rid),               //  output,    width = 1,                 .rid
		.rdata                  (niosv_g_data_manager_translator_m0_rdata),             //  output,   width = 32,                 .rdata
		.rresp                  (niosv_g_data_manager_translator_m0_rresp),             //  output,    width = 2,                 .rresp
		.rlast                  (niosv_g_data_manager_translator_m0_rlast),             //  output,    width = 1,                 .rlast
		.rvalid                 (niosv_g_data_manager_translator_m0_rvalid),            //  output,    width = 1,                 .rvalid
		.rready                 (niosv_g_data_manager_translator_m0_rready),            //   input,    width = 1,                 .rready
		.ruser                  (niosv_g_data_manager_translator_m0_ruser),             //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                                 // (terminated),                                
		.awuser_sai             (1'b0),                                                 // (terminated),                                
		.wuser_datachk          (4'b0000),                                              // (terminated),                                
		.wuser_data             (1'b0),                                                 // (terminated),                                
		.wuser_poison           (1'b0),                                                 // (terminated),                                
		.aruser_addrchk         (1'b0),                                                 // (terminated),                                
		.aruser_sai             (1'b0),                                                 // (terminated),                                
		.ruser_datachk          (),                                                     // (terminated),                                
		.ruser_data             (),                                                     // (terminated),                                
		.ruser_poison           (),                                                     // (terminated),                                
		.awakeup                (1'b0),                                                 // (terminated),                                
		.awtrace                (1'b0),                                                 // (terminated),                                
		.artrace                (1'b0),                                                 // (terminated),                                
		.wpoison                (1'b0),                                                 // (terminated),                                
		.wdatachk               (4'b0000),                                              // (terminated),                                
		.wtrace                 (1'b0),                                                 // (terminated),                                
		.btrace                 (),                                                     // (terminated),                                
		.rpoison                (),                                                     // (terminated),                                
		.rdatachk               (),                                                     // (terminated),                                
		.rtrace                 (),                                                     // (terminated),                                
		.wid                    (1'b0),                                                 // (terminated),                                
		.arsnoop                (4'b0000),                                              // (terminated),                                
		.ardomain               (2'b00),                                                // (terminated),                                
		.arbar                  (2'b00),                                                // (terminated),                                
		.awsnoop                (3'b000),                                               // (terminated),                                
		.awdomain               (2'b00),                                                // (terminated),                                
		.awbar                  (2'b00),                                                // (terminated),                                
		.awunique               (1'b0)                                                  // (terminated),                                
	);

	nios_system_altera_merlin_axi_master_ni_19100_y3ctica #(
		.ID_WIDTH                  (1),
		.ADDR_WIDTH                (32),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (1),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (103),
		.PKT_CACHE_H               (121),
		.PKT_CACHE_L               (118),
		.PKT_ADDR_SIDEBAND_H       (101),
		.PKT_ADDR_SIDEBAND_L       (101),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_BURST_TYPE_H          (100),
		.PKT_BURST_TYPE_L          (99),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (110),
		.PKT_SRC_ID_L              (108),
		.PKT_DEST_ID_H             (113),
		.PKT_DEST_ID_L             (111),
		.PKT_THREAD_ID_H           (114),
		.PKT_THREAD_ID_L           (114),
		.PKT_QOS_L                 (104),
		.PKT_QOS_H                 (107),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_DATA_SIDEBAND_H       (102),
		.PKT_DATA_SIDEBAND_L       (102),
		.PKT_DOMAIN_H              (134),
		.PKT_DOMAIN_L              (133),
		.PKT_SNOOP_H               (132),
		.PKT_SNOOP_L               (129),
		.PKT_BARRIER_H             (128),
		.PKT_BARRIER_L             (127),
		.PKT_WUNIQUE               (135),
		.PKT_EOP_OOO               (142),
		.PKT_SOP_OOO               (143),
		.PKT_ATRACE                (151),
		.PKT_TRACE                 (152),
		.PKT_AWAKEUP               (153),
		.PKT_POISON_H              (136),
		.PKT_POISON_L              (136),
		.PKT_DATACHK_H             (137),
		.PKT_DATACHK_L             (137),
		.PKT_ADDRCHK_H             (140),
		.PKT_ADDRCHK_L             (139),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.PKT_USER_DATA_H           (138),
		.PKT_USER_DATA_L           (138),
		.ST_DATA_W                 (154),
		.ST_CHANNEL_W              (6),
		.ID                        (2),
		.SYNC_RESET                (1),
		.DATA_USER_WIDTH           (1)
	) niosv_g_instruction_manager_agent (
		.aclk                   (iopll_outclk0_clk),                                            //   input,    width = 1,              clk.clk
		.aresetn                (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),         //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (niosv_g_instruction_manager_agent_write_cp_valid),             //  output,    width = 1,         write_cp.valid
		.write_cp_data          (niosv_g_instruction_manager_agent_write_cp_data),              //  output,  width = 154,                 .data
		.write_cp_startofpacket (niosv_g_instruction_manager_agent_write_cp_startofpacket),     //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (niosv_g_instruction_manager_agent_write_cp_endofpacket),       //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (niosv_g_instruction_manager_agent_write_cp_ready),             //   input,    width = 1,                 .ready
		.write_rp_valid         (niosv_g_instruction_manager_wr_limiter_rsp_src_valid),         //   input,    width = 1,         write_rp.valid
		.write_rp_data          (niosv_g_instruction_manager_wr_limiter_rsp_src_data),          //   input,  width = 154,                 .data
		.write_rp_channel       (niosv_g_instruction_manager_wr_limiter_rsp_src_channel),       //   input,    width = 6,                 .channel
		.write_rp_startofpacket (niosv_g_instruction_manager_wr_limiter_rsp_src_startofpacket), //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (niosv_g_instruction_manager_wr_limiter_rsp_src_endofpacket),   //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (niosv_g_instruction_manager_wr_limiter_rsp_src_ready),         //  output,    width = 1,                 .ready
		.read_cp_valid          (niosv_g_instruction_manager_agent_read_cp_valid),              //  output,    width = 1,          read_cp.valid
		.read_cp_data           (niosv_g_instruction_manager_agent_read_cp_data),               //  output,  width = 154,                 .data
		.read_cp_startofpacket  (niosv_g_instruction_manager_agent_read_cp_startofpacket),      //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (niosv_g_instruction_manager_agent_read_cp_endofpacket),        //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (niosv_g_instruction_manager_agent_read_cp_ready),              //   input,    width = 1,                 .ready
		.read_rp_valid          (niosv_g_instruction_manager_rd_limiter_rsp_src_valid),         //   input,    width = 1,          read_rp.valid
		.read_rp_data           (niosv_g_instruction_manager_rd_limiter_rsp_src_data),          //   input,  width = 154,                 .data
		.read_rp_channel        (niosv_g_instruction_manager_rd_limiter_rsp_src_channel),       //   input,    width = 6,                 .channel
		.read_rp_startofpacket  (niosv_g_instruction_manager_rd_limiter_rsp_src_startofpacket), //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (niosv_g_instruction_manager_rd_limiter_rsp_src_endofpacket),   //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (niosv_g_instruction_manager_rd_limiter_rsp_src_ready),         //  output,    width = 1,                 .ready
		.awid                   (niosv_g_instruction_manager_translator_m0_awid),               //   input,    width = 1, altera_axi_slave.awid
		.awaddr                 (niosv_g_instruction_manager_translator_m0_awaddr),             //   input,   width = 32,                 .awaddr
		.awlen                  (niosv_g_instruction_manager_translator_m0_awlen),              //   input,    width = 8,                 .awlen
		.awsize                 (niosv_g_instruction_manager_translator_m0_awsize),             //   input,    width = 3,                 .awsize
		.awburst                (niosv_g_instruction_manager_translator_m0_awburst),            //   input,    width = 2,                 .awburst
		.awlock                 (niosv_g_instruction_manager_translator_m0_awlock),             //   input,    width = 1,                 .awlock
		.awcache                (niosv_g_instruction_manager_translator_m0_awcache),            //   input,    width = 4,                 .awcache
		.awprot                 (niosv_g_instruction_manager_translator_m0_awprot),             //   input,    width = 3,                 .awprot
		.awuser                 (niosv_g_instruction_manager_translator_m0_awuser),             //   input,    width = 1,                 .awuser
		.awqos                  (niosv_g_instruction_manager_translator_m0_awqos),              //   input,    width = 4,                 .awqos
		.awregion               (niosv_g_instruction_manager_translator_m0_awregion),           //   input,    width = 4,                 .awregion
		.awvalid                (niosv_g_instruction_manager_translator_m0_awvalid),            //   input,    width = 1,                 .awvalid
		.awready                (niosv_g_instruction_manager_translator_m0_awready),            //  output,    width = 1,                 .awready
		.wdata                  (niosv_g_instruction_manager_translator_m0_wdata),              //   input,   width = 32,                 .wdata
		.wstrb                  (niosv_g_instruction_manager_translator_m0_wstrb),              //   input,    width = 4,                 .wstrb
		.wlast                  (niosv_g_instruction_manager_translator_m0_wlast),              //   input,    width = 1,                 .wlast
		.wvalid                 (niosv_g_instruction_manager_translator_m0_wvalid),             //   input,    width = 1,                 .wvalid
		.wuser                  (niosv_g_instruction_manager_translator_m0_wuser),              //   input,    width = 1,                 .wuser
		.wready                 (niosv_g_instruction_manager_translator_m0_wready),             //  output,    width = 1,                 .wready
		.bid                    (niosv_g_instruction_manager_translator_m0_bid),                //  output,    width = 1,                 .bid
		.bresp                  (niosv_g_instruction_manager_translator_m0_bresp),              //  output,    width = 2,                 .bresp
		.buser                  (niosv_g_instruction_manager_translator_m0_buser),              //  output,    width = 1,                 .buser
		.bvalid                 (niosv_g_instruction_manager_translator_m0_bvalid),             //  output,    width = 1,                 .bvalid
		.bready                 (niosv_g_instruction_manager_translator_m0_bready),             //   input,    width = 1,                 .bready
		.arid                   (niosv_g_instruction_manager_translator_m0_arid),               //   input,    width = 1,                 .arid
		.araddr                 (niosv_g_instruction_manager_translator_m0_araddr),             //   input,   width = 32,                 .araddr
		.arlen                  (niosv_g_instruction_manager_translator_m0_arlen),              //   input,    width = 8,                 .arlen
		.arsize                 (niosv_g_instruction_manager_translator_m0_arsize),             //   input,    width = 3,                 .arsize
		.arburst                (niosv_g_instruction_manager_translator_m0_arburst),            //   input,    width = 2,                 .arburst
		.arlock                 (niosv_g_instruction_manager_translator_m0_arlock),             //   input,    width = 1,                 .arlock
		.arcache                (niosv_g_instruction_manager_translator_m0_arcache),            //   input,    width = 4,                 .arcache
		.arprot                 (niosv_g_instruction_manager_translator_m0_arprot),             //   input,    width = 3,                 .arprot
		.aruser                 (niosv_g_instruction_manager_translator_m0_aruser),             //   input,    width = 1,                 .aruser
		.arqos                  (niosv_g_instruction_manager_translator_m0_arqos),              //   input,    width = 4,                 .arqos
		.arregion               (niosv_g_instruction_manager_translator_m0_arregion),           //   input,    width = 4,                 .arregion
		.arvalid                (niosv_g_instruction_manager_translator_m0_arvalid),            //   input,    width = 1,                 .arvalid
		.arready                (niosv_g_instruction_manager_translator_m0_arready),            //  output,    width = 1,                 .arready
		.rid                    (niosv_g_instruction_manager_translator_m0_rid),                //  output,    width = 1,                 .rid
		.rdata                  (niosv_g_instruction_manager_translator_m0_rdata),              //  output,   width = 32,                 .rdata
		.rresp                  (niosv_g_instruction_manager_translator_m0_rresp),              //  output,    width = 2,                 .rresp
		.rlast                  (niosv_g_instruction_manager_translator_m0_rlast),              //  output,    width = 1,                 .rlast
		.rvalid                 (niosv_g_instruction_manager_translator_m0_rvalid),             //  output,    width = 1,                 .rvalid
		.rready                 (niosv_g_instruction_manager_translator_m0_rready),             //   input,    width = 1,                 .rready
		.ruser                  (niosv_g_instruction_manager_translator_m0_ruser),              //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                                         // (terminated),                                
		.awuser_sai             (1'b0),                                                         // (terminated),                                
		.wuser_datachk          (4'b0000),                                                      // (terminated),                                
		.wuser_data             (1'b0),                                                         // (terminated),                                
		.wuser_poison           (1'b0),                                                         // (terminated),                                
		.aruser_addrchk         (1'b0),                                                         // (terminated),                                
		.aruser_sai             (1'b0),                                                         // (terminated),                                
		.ruser_datachk          (),                                                             // (terminated),                                
		.ruser_data             (),                                                             // (terminated),                                
		.ruser_poison           (),                                                             // (terminated),                                
		.awakeup                (1'b0),                                                         // (terminated),                                
		.awtrace                (1'b0),                                                         // (terminated),                                
		.artrace                (1'b0),                                                         // (terminated),                                
		.wpoison                (1'b0),                                                         // (terminated),                                
		.wdatachk               (4'b0000),                                                      // (terminated),                                
		.wtrace                 (1'b0),                                                         // (terminated),                                
		.btrace                 (),                                                             // (terminated),                                
		.rpoison                (),                                                             // (terminated),                                
		.rdatachk               (),                                                             // (terminated),                                
		.rtrace                 (),                                                             // (terminated),                                
		.wid                    (1'b0),                                                         // (terminated),                                
		.arsnoop                (4'b0000),                                                      // (terminated),                                
		.ardomain               (2'b00),                                                        // (terminated),                                
		.arbar                  (2'b00),                                                        // (terminated),                                
		.awsnoop                (3'b000),                                                       // (terminated),                                
		.awdomain               (2'b00),                                                        // (terminated),                                
		.awbar                  (2'b00),                                                        // (terminated),                                
		.awunique               (1'b0)                                                          // (terminated),                                
	);

	nios_system_altera_merlin_axi_slave_ni_19112_be2djva #(
		.PKT_QOS_H                   (143),
		.PKT_QOS_L                   (140),
		.PKT_THREAD_ID_H             (150),
		.PKT_THREAD_ID_L             (150),
		.PKT_RESPONSE_STATUS_H       (159),
		.PKT_RESPONSE_STATUS_L       (158),
		.PKT_BEGIN_BURST             (139),
		.PKT_CACHE_H                 (157),
		.PKT_CACHE_L                 (154),
		.PKT_DATA_SIDEBAND_H         (138),
		.PKT_DATA_SIDEBAND_L         (138),
		.PKT_ADDR_SIDEBAND_H         (137),
		.PKT_ADDR_SIDEBAND_L         (137),
		.PKT_BURST_TYPE_H            (136),
		.PKT_BURST_TYPE_L            (135),
		.PKT_PROTECTION_H            (153),
		.PKT_PROTECTION_L            (151),
		.PKT_BURST_SIZE_H            (134),
		.PKT_BURST_SIZE_L            (132),
		.PKT_BURSTWRAP_H             (131),
		.PKT_BURSTWRAP_L             (124),
		.PKT_BYTE_CNT_H              (123),
		.PKT_BYTE_CNT_L              (110),
		.PKT_ADDR_H                  (103),
		.PKT_ADDR_L                  (72),
		.PKT_TRANS_EXCLUSIVE         (109),
		.PKT_TRANS_LOCK              (108),
		.PKT_TRANS_COMPRESSED_READ   (104),
		.PKT_TRANS_POSTED            (105),
		.PKT_TRANS_WRITE             (106),
		.PKT_TRANS_READ              (107),
		.PKT_DATA_H                  (63),
		.PKT_DATA_L                  (0),
		.PKT_BYTEEN_H                (71),
		.PKT_BYTEEN_L                (64),
		.PKT_SRC_ID_H                (146),
		.PKT_SRC_ID_L                (144),
		.PKT_DEST_ID_H               (149),
		.PKT_DEST_ID_L               (147),
		.PKT_ORI_BURST_SIZE_L        (160),
		.PKT_ORI_BURST_SIZE_H        (162),
		.PKT_DOMAIN_L                (169),
		.PKT_DOMAIN_H                (170),
		.PKT_SNOOP_L                 (165),
		.PKT_SNOOP_H                 (168),
		.PKT_BARRIER_L               (163),
		.PKT_BARRIER_H               (164),
		.PKT_WUNIQUE                 (171),
		.PKT_EOP_OOO                 (178),
		.PKT_SOP_OOO                 (179),
		.PKT_AWAKEUP                 (189),
		.PKT_ATRACE                  (187),
		.PKT_TRACE                   (188),
		.PKT_POISON_H                (172),
		.PKT_POISON_L                (172),
		.PKT_DATACHK_H               (173),
		.PKT_DATACHK_L               (173),
		.PKT_ADDRCHK_H               (176),
		.PKT_ADDRCHK_L               (175),
		.PKT_SAI_H                   (177),
		.PKT_SAI_L                   (177),
		.PKT_USER_DATA_H             (174),
		.PKT_USER_DATA_L             (174),
		.SAI_WIDTH                   (1),
		.ADDRCHK_WIDTH               (1),
		.USER_DATA_WIDTH             (1),
		.ADDR_USER_WIDTH             (1),
		.DATA_USER_WIDTH             (1),
		.ST_DATA_W                   (190),
		.ADDR_WIDTH                  (26),
		.RDATA_WIDTH                 (64),
		.WDATA_WIDTH                 (64),
		.ST_CHANNEL_W                (6),
		.AXI_SLAVE_ID_W              (4),
		.ACE_LITE_SUPPORT            (0),
		.PASS_ID_TO_SLAVE            (1),
		.AXI_VERSION                 ("AXI4"),
		.WRITE_ACCEPTANCE_CAPABILITY (1),
		.READ_ACCEPTANCE_CAPABILITY  (1),
		.USE_PKT_DATACHK             (0),
		.USE_PKT_ADDRCHK             (0),
		.SYNC_RESET                  (1),
		.USE_MEMORY_BLOCKS           (0),
		.ROLE_BASED_USER             (0),
		.ENABLE_OOO                  (0),
		.REORDER_BUFFER              (0)
	) sdram_axi4_slave_agent (
		.aclk                   (iopll_outclk0_clk),                                    //   input,    width = 1,        clock_sink.clk
		.aresetn                (~intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        reset_sink.reset_n
		.read_cp_valid          (cmd_mux_001_src_valid),                                //   input,    width = 1,           read_cp.valid
		.read_cp_ready          (cmd_mux_001_src_ready),                                //  output,    width = 1,                  .ready
		.read_cp_data           (cmd_mux_001_src_data),                                 //   input,  width = 190,                  .data
		.read_cp_channel        (cmd_mux_001_src_channel),                              //   input,    width = 6,                  .channel
		.read_cp_startofpacket  (cmd_mux_001_src_startofpacket),                        //   input,    width = 1,                  .startofpacket
		.read_cp_endofpacket    (cmd_mux_001_src_endofpacket),                          //   input,    width = 1,                  .endofpacket
		.write_cp_ready         (cmd_mux_src_ready),                                    //  output,    width = 1,          write_cp.ready
		.write_cp_valid         (cmd_mux_src_valid),                                    //   input,    width = 1,                  .valid
		.write_cp_data          (cmd_mux_src_data),                                     //   input,  width = 190,                  .data
		.write_cp_channel       (cmd_mux_src_channel),                                  //   input,    width = 6,                  .channel
		.write_cp_startofpacket (cmd_mux_src_startofpacket),                            //   input,    width = 1,                  .startofpacket
		.write_cp_endofpacket   (cmd_mux_src_endofpacket),                              //   input,    width = 1,                  .endofpacket
		.read_rp_ready          (sdram_axi4_slave_agent_read_rp_ready),                 //   input,    width = 1,           read_rp.ready
		.read_rp_valid          (sdram_axi4_slave_agent_read_rp_valid),                 //  output,    width = 1,                  .valid
		.read_rp_data           (sdram_axi4_slave_agent_read_rp_data),                  //  output,  width = 190,                  .data
		.read_rp_startofpacket  (sdram_axi4_slave_agent_read_rp_startofpacket),         //  output,    width = 1,                  .startofpacket
		.read_rp_endofpacket    (sdram_axi4_slave_agent_read_rp_endofpacket),           //  output,    width = 1,                  .endofpacket
		.write_rp_ready         (sdram_axi4_slave_agent_write_rp_ready),                //   input,    width = 1,          write_rp.ready
		.write_rp_valid         (sdram_axi4_slave_agent_write_rp_valid),                //  output,    width = 1,                  .valid
		.write_rp_data          (sdram_axi4_slave_agent_write_rp_data),                 //  output,  width = 190,                  .data
		.write_rp_startofpacket (sdram_axi4_slave_agent_write_rp_startofpacket),        //  output,    width = 1,                  .startofpacket
		.write_rp_endofpacket   (sdram_axi4_slave_agent_write_rp_endofpacket),          //  output,    width = 1,                  .endofpacket
		.awid                   (sdram_axi4_slave_agent_altera_axi_master_awid),        //  output,    width = 4, altera_axi_master.awid
		.awaddr                 (sdram_axi4_slave_agent_altera_axi_master_awaddr),      //  output,   width = 26,                  .awaddr
		.awlen                  (sdram_axi4_slave_agent_altera_axi_master_awlen),       //  output,    width = 8,                  .awlen
		.awsize                 (sdram_axi4_slave_agent_altera_axi_master_awsize),      //  output,    width = 3,                  .awsize
		.awburst                (sdram_axi4_slave_agent_altera_axi_master_awburst),     //  output,    width = 2,                  .awburst
		.awlock                 (sdram_axi4_slave_agent_altera_axi_master_awlock),      //  output,    width = 1,                  .awlock
		.awcache                (sdram_axi4_slave_agent_altera_axi_master_awcache),     //  output,    width = 4,                  .awcache
		.awprot                 (sdram_axi4_slave_agent_altera_axi_master_awprot),      //  output,    width = 3,                  .awprot
		.awuser                 (sdram_axi4_slave_agent_altera_axi_master_awuser),      //  output,    width = 1,                  .awuser
		.awvalid                (sdram_axi4_slave_agent_altera_axi_master_awvalid),     //  output,    width = 1,                  .awvalid
		.awready                (sdram_axi4_slave_agent_altera_axi_master_awready),     //   input,    width = 1,                  .awready
		.wdata                  (sdram_axi4_slave_agent_altera_axi_master_wdata),       //  output,   width = 64,                  .wdata
		.wstrb                  (sdram_axi4_slave_agent_altera_axi_master_wstrb),       //  output,    width = 8,                  .wstrb
		.wlast                  (sdram_axi4_slave_agent_altera_axi_master_wlast),       //  output,    width = 1,                  .wlast
		.wvalid                 (sdram_axi4_slave_agent_altera_axi_master_wvalid),      //  output,    width = 1,                  .wvalid
		.wready                 (sdram_axi4_slave_agent_altera_axi_master_wready),      //   input,    width = 1,                  .wready
		.bid                    (sdram_axi4_slave_agent_altera_axi_master_bid),         //   input,    width = 4,                  .bid
		.bresp                  (sdram_axi4_slave_agent_altera_axi_master_bresp),       //   input,    width = 2,                  .bresp
		.bvalid                 (sdram_axi4_slave_agent_altera_axi_master_bvalid),      //   input,    width = 1,                  .bvalid
		.bready                 (sdram_axi4_slave_agent_altera_axi_master_bready),      //  output,    width = 1,                  .bready
		.arid                   (sdram_axi4_slave_agent_altera_axi_master_arid),        //  output,    width = 4,                  .arid
		.araddr                 (sdram_axi4_slave_agent_altera_axi_master_araddr),      //  output,   width = 26,                  .araddr
		.arlen                  (sdram_axi4_slave_agent_altera_axi_master_arlen),       //  output,    width = 8,                  .arlen
		.arsize                 (sdram_axi4_slave_agent_altera_axi_master_arsize),      //  output,    width = 3,                  .arsize
		.arburst                (sdram_axi4_slave_agent_altera_axi_master_arburst),     //  output,    width = 2,                  .arburst
		.arlock                 (sdram_axi4_slave_agent_altera_axi_master_arlock),      //  output,    width = 1,                  .arlock
		.arcache                (sdram_axi4_slave_agent_altera_axi_master_arcache),     //  output,    width = 4,                  .arcache
		.arprot                 (sdram_axi4_slave_agent_altera_axi_master_arprot),      //  output,    width = 3,                  .arprot
		.aruser                 (sdram_axi4_slave_agent_altera_axi_master_aruser),      //  output,    width = 1,                  .aruser
		.arvalid                (sdram_axi4_slave_agent_altera_axi_master_arvalid),     //  output,    width = 1,                  .arvalid
		.arready                (sdram_axi4_slave_agent_altera_axi_master_arready),     //   input,    width = 1,                  .arready
		.rid                    (sdram_axi4_slave_agent_altera_axi_master_rid),         //   input,    width = 4,                  .rid
		.rdata                  (sdram_axi4_slave_agent_altera_axi_master_rdata),       //   input,   width = 64,                  .rdata
		.rresp                  (sdram_axi4_slave_agent_altera_axi_master_rresp),       //   input,    width = 2,                  .rresp
		.rlast                  (sdram_axi4_slave_agent_altera_axi_master_rlast),       //   input,    width = 1,                  .rlast
		.rvalid                 (sdram_axi4_slave_agent_altera_axi_master_rvalid),      //   input,    width = 1,                  .rvalid
		.rready                 (sdram_axi4_slave_agent_altera_axi_master_rready),      //  output,    width = 1,                  .rready
		.wuser                  (sdram_axi4_slave_agent_altera_axi_master_wuser),       //  output,    width = 1,                  .wuser
		.awqos                  (sdram_axi4_slave_agent_altera_axi_master_awqos),       //  output,    width = 4,                  .awqos
		.awregion               (sdram_axi4_slave_agent_altera_axi_master_awregion),    //  output,    width = 4,                  .awregion
		.ruser                  (sdram_axi4_slave_agent_altera_axi_master_ruser),       //   input,    width = 1,                  .ruser
		.buser                  (sdram_axi4_slave_agent_altera_axi_master_buser),       //   input,    width = 1,                  .buser
		.arqos                  (sdram_axi4_slave_agent_altera_axi_master_arqos),       //  output,    width = 4,                  .arqos
		.arregion               (sdram_axi4_slave_agent_altera_axi_master_arregion),    //  output,    width = 4,                  .arregion
		.awuser_addrchk         (),                                                     // (terminated),                                 
		.awuser_sai             (),                                                     // (terminated),                                 
		.wuser_datachk          (),                                                     // (terminated),                                 
		.wuser_data             (),                                                     // (terminated),                                 
		.wuser_poison           (),                                                     // (terminated),                                 
		.aruser_addrchk         (),                                                     // (terminated),                                 
		.aruser_sai             (),                                                     // (terminated),                                 
		.ruser_datachk          (8'b00000000),                                          // (terminated),                                 
		.ruser_data             (1'b0),                                                 // (terminated),                                 
		.ruser_poison           (1'b0),                                                 // (terminated),                                 
		.awakeup                (),                                                     // (terminated),                                 
		.awtrace                (),                                                     // (terminated),                                 
		.artrace                (),                                                     // (terminated),                                 
		.wpoison                (),                                                     // (terminated),                                 
		.wdatachk               (),                                                     // (terminated),                                 
		.wtrace                 (),                                                     // (terminated),                                 
		.btrace                 (1'b0),                                                 // (terminated),                                 
		.rpoison                (1'b0),                                                 // (terminated),                                 
		.rdatachk               (8'b00000000),                                          // (terminated),                                 
		.rtrace                 (1'b0),                                                 // (terminated),                                 
		.wid                    (),                                                     // (terminated),                                 
		.arsnoop                (),                                                     // (terminated),                                 
		.ardomain               (),                                                     // (terminated),                                 
		.arbar                  (),                                                     // (terminated),                                 
		.awsnoop                (),                                                     // (terminated),                                 
		.awdomain               (),                                                     // (terminated),                                 
		.awbar                  (),                                                     // (terminated),                                 
		.awunique               ()                                                      // (terminated),                                 
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (103),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (110),
		.PKT_SRC_ID_L              (108),
		.PKT_DEST_ID_H             (113),
		.PKT_DEST_ID_L             (111),
		.PKT_POISON_H              (136),
		.PKT_POISON_L              (136),
		.PKT_DATACHK_H             (137),
		.PKT_DATACHK_L             (137),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.PKT_ADDRCHK_H             (140),
		.PKT_ADDRCHK_L             (139),
		.PKT_USER_DATA_H           (138),
		.PKT_USER_DATA_L           (138),
		.PKT_ATRACE                (151),
		.PKT_TRACE                 (152),
		.PKT_AWAKEUP               (153),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (154),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) niosv_g_dm_agent_agent (
		.clk                     (iopll_outclk0_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),  //   input,    width = 1,       clk_reset.reset
		.m0_address              (niosv_g_dm_agent_agent_m0_address),                    //  output,   width = 32,              m0.address
		.m0_burstcount           (niosv_g_dm_agent_agent_m0_burstcount),                 //  output,    width = 3,                .burstcount
		.m0_byteenable           (niosv_g_dm_agent_agent_m0_byteenable),                 //  output,    width = 4,                .byteenable
		.m0_debugaccess          (niosv_g_dm_agent_agent_m0_debugaccess),                //  output,    width = 1,                .debugaccess
		.m0_lock                 (niosv_g_dm_agent_agent_m0_lock),                       //  output,    width = 1,                .lock
		.m0_readdata             (niosv_g_dm_agent_agent_m0_readdata),                   //   input,   width = 32,                .readdata
		.m0_readdatavalid        (niosv_g_dm_agent_agent_m0_readdatavalid),              //   input,    width = 1,                .readdatavalid
		.m0_read                 (niosv_g_dm_agent_agent_m0_read),                       //  output,    width = 1,                .read
		.m0_waitrequest          (niosv_g_dm_agent_agent_m0_waitrequest),                //   input,    width = 1,                .waitrequest
		.m0_writedata            (niosv_g_dm_agent_agent_m0_writedata),                  //  output,   width = 32,                .writedata
		.m0_write                (niosv_g_dm_agent_agent_m0_write),                      //  output,    width = 1,                .write
		.rp_endofpacket          (niosv_g_dm_agent_agent_rp_endofpacket),                //  output,    width = 1,              rp.endofpacket
		.rp_ready                (niosv_g_dm_agent_agent_rp_ready),                      //   input,    width = 1,                .ready
		.rp_valid                (niosv_g_dm_agent_agent_rp_valid),                      //  output,    width = 1,                .valid
		.rp_data                 (niosv_g_dm_agent_agent_rp_data),                       //  output,  width = 154,                .data
		.rp_startofpacket        (niosv_g_dm_agent_agent_rp_startofpacket),              //  output,    width = 1,                .startofpacket
		.cp_ready                (niosv_g_dm_agent_burst_adapter_source0_ready),         //  output,    width = 1,              cp.ready
		.cp_valid                (niosv_g_dm_agent_burst_adapter_source0_valid),         //   input,    width = 1,                .valid
		.cp_data                 (niosv_g_dm_agent_burst_adapter_source0_data),          //   input,  width = 154,                .data
		.cp_startofpacket        (niosv_g_dm_agent_burst_adapter_source0_startofpacket), //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (niosv_g_dm_agent_burst_adapter_source0_endofpacket),   //   input,    width = 1,                .endofpacket
		.cp_channel              (niosv_g_dm_agent_burst_adapter_source0_channel),       //   input,    width = 6,                .channel
		.rf_sink_ready           (niosv_g_dm_agent_agent_rsp_fifo_out_ready),            //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (niosv_g_dm_agent_agent_rsp_fifo_out_valid),            //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (niosv_g_dm_agent_agent_rsp_fifo_out_startofpacket),    //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (niosv_g_dm_agent_agent_rsp_fifo_out_endofpacket),      //   input,    width = 1,                .endofpacket
		.rf_sink_data            (niosv_g_dm_agent_agent_rsp_fifo_out_data),             //   input,  width = 155,                .data
		.rf_source_ready         (niosv_g_dm_agent_agent_rf_source_ready),               //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (niosv_g_dm_agent_agent_rf_source_valid),               //  output,    width = 1,                .valid
		.rf_source_startofpacket (niosv_g_dm_agent_agent_rf_source_startofpacket),       //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (niosv_g_dm_agent_agent_rf_source_endofpacket),         //  output,    width = 1,                .endofpacket
		.rf_source_data          (niosv_g_dm_agent_agent_rf_source_data),                //  output,  width = 155,                .data
		.rdata_fifo_sink_ready   (niosv_g_dm_agent_agent_rdata_fifo_out_ready),          //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (niosv_g_dm_agent_agent_rdata_fifo_out_valid),          //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (niosv_g_dm_agent_agent_rdata_fifo_out_data),           //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (niosv_g_dm_agent_agent_rdata_fifo_src_ready),          //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (niosv_g_dm_agent_agent_rdata_fifo_src_valid),          //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (niosv_g_dm_agent_agent_rdata_fifo_src_data),           //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (155),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) niosv_g_dm_agent_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                 //   input,    width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, clk_reset.reset
		.in_data           (niosv_g_dm_agent_agent_rf_source_data),             //   input,  width = 155,        in.data
		.in_valid          (niosv_g_dm_agent_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (niosv_g_dm_agent_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (niosv_g_dm_agent_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (niosv_g_dm_agent_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (niosv_g_dm_agent_agent_rsp_fifo_out_data),          //  output,  width = 155,       out.data
		.out_valid         (niosv_g_dm_agent_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (niosv_g_dm_agent_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (niosv_g_dm_agent_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (niosv_g_dm_agent_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                             // (terminated),                         
		.csr_read          (1'b0),                                              // (terminated),                         
		.csr_write         (1'b0),                                              // (terminated),                         
		.csr_readdata      (),                                                  // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated),                         
		.almost_full_data  (),                                                  // (terminated),                         
		.almost_empty_data (),                                                  // (terminated),                         
		.in_empty          (1'b0),                                              // (terminated),                         
		.out_empty         (),                                                  // (terminated),                         
		.in_error          (1'b0),                                              // (terminated),                         
		.out_error         (),                                                  // (terminated),                         
		.in_channel        (1'b0),                                              // (terminated),                         
		.out_channel       ()                                                   // (terminated),                         
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) niosv_g_dm_agent_agent_rdata_fifo (
		.clk               (iopll_outclk0_clk),                           //   input,   width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),   //   input,   width = 1, clk_reset.reset
		.in_data           (niosv_g_dm_agent_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (niosv_g_dm_agent_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (niosv_g_dm_agent_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (niosv_g_dm_agent_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (niosv_g_dm_agent_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (niosv_g_dm_agent_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                       // (terminated),                        
		.csr_read          (1'b0),                                        // (terminated),                        
		.csr_write         (1'b0),                                        // (terminated),                        
		.csr_readdata      (),                                            // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),        // (terminated),                        
		.almost_full_data  (),                                            // (terminated),                        
		.almost_empty_data (),                                            // (terminated),                        
		.in_startofpacket  (1'b0),                                        // (terminated),                        
		.in_endofpacket    (1'b0),                                        // (terminated),                        
		.out_startofpacket (),                                            // (terminated),                        
		.out_endofpacket   (),                                            // (terminated),                        
		.in_empty          (1'b0),                                        // (terminated),                        
		.out_empty         (),                                            // (terminated),                        
		.in_error          (1'b0),                                        // (terminated),                        
		.out_error         (),                                            // (terminated),                        
		.in_channel        (1'b0),                                        // (terminated),                        
		.out_channel       ()                                             // (terminated),                        
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (103),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (110),
		.PKT_SRC_ID_L              (108),
		.PKT_DEST_ID_H             (113),
		.PKT_DEST_ID_L             (111),
		.PKT_POISON_H              (136),
		.PKT_POISON_L              (136),
		.PKT_DATACHK_H             (137),
		.PKT_DATACHK_L             (137),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.PKT_ADDRCHK_H             (140),
		.PKT_ADDRCHK_L             (139),
		.PKT_USER_DATA_H           (138),
		.PKT_USER_DATA_L           (138),
		.PKT_ATRACE                (151),
		.PKT_TRACE                 (152),
		.PKT_AWAKEUP               (153),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (154),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) mm_bridge_peripheral_s0_agent (
		.clk                     (iopll_outclk0_clk),                                           //   input,    width = 1,             clk.clk
		.reset                   (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),         //   input,    width = 1,       clk_reset.reset
		.m0_address              (mm_bridge_peripheral_s0_agent_m0_address),                    //  output,   width = 32,              m0.address
		.m0_burstcount           (mm_bridge_peripheral_s0_agent_m0_burstcount),                 //  output,    width = 3,                .burstcount
		.m0_byteenable           (mm_bridge_peripheral_s0_agent_m0_byteenable),                 //  output,    width = 4,                .byteenable
		.m0_debugaccess          (mm_bridge_peripheral_s0_agent_m0_debugaccess),                //  output,    width = 1,                .debugaccess
		.m0_lock                 (mm_bridge_peripheral_s0_agent_m0_lock),                       //  output,    width = 1,                .lock
		.m0_readdata             (mm_bridge_peripheral_s0_agent_m0_readdata),                   //   input,   width = 32,                .readdata
		.m0_readdatavalid        (mm_bridge_peripheral_s0_agent_m0_readdatavalid),              //   input,    width = 1,                .readdatavalid
		.m0_read                 (mm_bridge_peripheral_s0_agent_m0_read),                       //  output,    width = 1,                .read
		.m0_waitrequest          (mm_bridge_peripheral_s0_agent_m0_waitrequest),                //   input,    width = 1,                .waitrequest
		.m0_writedata            (mm_bridge_peripheral_s0_agent_m0_writedata),                  //  output,   width = 32,                .writedata
		.m0_write                (mm_bridge_peripheral_s0_agent_m0_write),                      //  output,    width = 1,                .write
		.rp_endofpacket          (mm_bridge_peripheral_s0_agent_rp_endofpacket),                //  output,    width = 1,              rp.endofpacket
		.rp_ready                (mm_bridge_peripheral_s0_agent_rp_ready),                      //   input,    width = 1,                .ready
		.rp_valid                (mm_bridge_peripheral_s0_agent_rp_valid),                      //  output,    width = 1,                .valid
		.rp_data                 (mm_bridge_peripheral_s0_agent_rp_data),                       //  output,  width = 154,                .data
		.rp_startofpacket        (mm_bridge_peripheral_s0_agent_rp_startofpacket),              //  output,    width = 1,                .startofpacket
		.cp_ready                (mm_bridge_peripheral_s0_burst_adapter_source0_ready),         //  output,    width = 1,              cp.ready
		.cp_valid                (mm_bridge_peripheral_s0_burst_adapter_source0_valid),         //   input,    width = 1,                .valid
		.cp_data                 (mm_bridge_peripheral_s0_burst_adapter_source0_data),          //   input,  width = 154,                .data
		.cp_startofpacket        (mm_bridge_peripheral_s0_burst_adapter_source0_startofpacket), //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (mm_bridge_peripheral_s0_burst_adapter_source0_endofpacket),   //   input,    width = 1,                .endofpacket
		.cp_channel              (mm_bridge_peripheral_s0_burst_adapter_source0_channel),       //   input,    width = 6,                .channel
		.rf_sink_ready           (mm_bridge_peripheral_s0_agent_rsp_fifo_out_ready),            //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (mm_bridge_peripheral_s0_agent_rsp_fifo_out_valid),            //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (mm_bridge_peripheral_s0_agent_rsp_fifo_out_startofpacket),    //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (mm_bridge_peripheral_s0_agent_rsp_fifo_out_endofpacket),      //   input,    width = 1,                .endofpacket
		.rf_sink_data            (mm_bridge_peripheral_s0_agent_rsp_fifo_out_data),             //   input,  width = 155,                .data
		.rf_source_ready         (mm_bridge_peripheral_s0_agent_rf_source_ready),               //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (mm_bridge_peripheral_s0_agent_rf_source_valid),               //  output,    width = 1,                .valid
		.rf_source_startofpacket (mm_bridge_peripheral_s0_agent_rf_source_startofpacket),       //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (mm_bridge_peripheral_s0_agent_rf_source_endofpacket),         //  output,    width = 1,                .endofpacket
		.rf_source_data          (mm_bridge_peripheral_s0_agent_rf_source_data),                //  output,  width = 155,                .data
		.rdata_fifo_sink_ready   (mm_bridge_peripheral_s0_agent_rdata_fifo_out_ready),          //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (mm_bridge_peripheral_s0_agent_rdata_fifo_out_valid),          //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (mm_bridge_peripheral_s0_agent_rdata_fifo_out_data),           //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (mm_bridge_peripheral_s0_agent_rdata_fifo_src_ready),          //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (mm_bridge_peripheral_s0_agent_rdata_fifo_src_valid),          //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (mm_bridge_peripheral_s0_agent_rdata_fifo_src_data),           //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                         // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (155),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) mm_bridge_peripheral_s0_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                        //   input,    width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),                //   input,    width = 1, clk_reset.reset
		.in_data           (mm_bridge_peripheral_s0_agent_rf_source_data),             //   input,  width = 155,        in.data
		.in_valid          (mm_bridge_peripheral_s0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (mm_bridge_peripheral_s0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (mm_bridge_peripheral_s0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (mm_bridge_peripheral_s0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (mm_bridge_peripheral_s0_agent_rsp_fifo_out_data),          //  output,  width = 155,       out.data
		.out_valid         (mm_bridge_peripheral_s0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (mm_bridge_peripheral_s0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (mm_bridge_peripheral_s0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mm_bridge_peripheral_s0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                    // (terminated),                         
		.csr_read          (1'b0),                                                     // (terminated),                         
		.csr_write         (1'b0),                                                     // (terminated),                         
		.csr_readdata      (),                                                         // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                     // (terminated),                         
		.almost_full_data  (),                                                         // (terminated),                         
		.almost_empty_data (),                                                         // (terminated),                         
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.in_error          (1'b0),                                                     // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_channel        (1'b0),                                                     // (terminated),                         
		.out_channel       ()                                                          // (terminated),                         
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) mm_bridge_peripheral_s0_agent_rdata_fifo (
		.clk               (iopll_outclk0_clk),                                  //   input,   width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),          //   input,   width = 1, clk_reset.reset
		.in_data           (mm_bridge_peripheral_s0_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (mm_bridge_peripheral_s0_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (mm_bridge_peripheral_s0_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (mm_bridge_peripheral_s0_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (mm_bridge_peripheral_s0_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (mm_bridge_peripheral_s0_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                              // (terminated),                        
		.csr_read          (1'b0),                                               // (terminated),                        
		.csr_write         (1'b0),                                               // (terminated),                        
		.csr_readdata      (),                                                   // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated),                        
		.almost_full_data  (),                                                   // (terminated),                        
		.almost_empty_data (),                                                   // (terminated),                        
		.in_startofpacket  (1'b0),                                               // (terminated),                        
		.in_endofpacket    (1'b0),                                               // (terminated),                        
		.out_startofpacket (),                                                   // (terminated),                        
		.out_endofpacket   (),                                                   // (terminated),                        
		.in_empty          (1'b0),                                               // (terminated),                        
		.out_empty         (),                                                   // (terminated),                        
		.in_error          (1'b0),                                               // (terminated),                        
		.out_error         (),                                                   // (terminated),                        
		.in_channel        (1'b0),                                               // (terminated),                        
		.out_channel       ()                                                    // (terminated),                        
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (103),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (110),
		.PKT_SRC_ID_L              (108),
		.PKT_DEST_ID_H             (113),
		.PKT_DEST_ID_L             (111),
		.PKT_POISON_H              (136),
		.PKT_POISON_L              (136),
		.PKT_DATACHK_H             (137),
		.PKT_DATACHK_L             (137),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.PKT_ADDRCHK_H             (140),
		.PKT_ADDRCHK_L             (139),
		.PKT_USER_DATA_H           (138),
		.PKT_USER_DATA_L           (138),
		.PKT_ATRACE                (151),
		.PKT_TRACE                 (152),
		.PKT_AWAKEUP               (153),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (154),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) onchip_memory_s1_agent (
		.clk                     (iopll_outclk0_clk),                                    //   input,    width = 1,             clk.clk
		.reset                   (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),  //   input,    width = 1,       clk_reset.reset
		.m0_address              (onchip_memory_s1_agent_m0_address),                    //  output,   width = 32,              m0.address
		.m0_burstcount           (onchip_memory_s1_agent_m0_burstcount),                 //  output,    width = 3,                .burstcount
		.m0_byteenable           (onchip_memory_s1_agent_m0_byteenable),                 //  output,    width = 4,                .byteenable
		.m0_debugaccess          (onchip_memory_s1_agent_m0_debugaccess),                //  output,    width = 1,                .debugaccess
		.m0_lock                 (onchip_memory_s1_agent_m0_lock),                       //  output,    width = 1,                .lock
		.m0_readdata             (onchip_memory_s1_agent_m0_readdata),                   //   input,   width = 32,                .readdata
		.m0_readdatavalid        (onchip_memory_s1_agent_m0_readdatavalid),              //   input,    width = 1,                .readdatavalid
		.m0_read                 (onchip_memory_s1_agent_m0_read),                       //  output,    width = 1,                .read
		.m0_waitrequest          (onchip_memory_s1_agent_m0_waitrequest),                //   input,    width = 1,                .waitrequest
		.m0_writedata            (onchip_memory_s1_agent_m0_writedata),                  //  output,   width = 32,                .writedata
		.m0_write                (onchip_memory_s1_agent_m0_write),                      //  output,    width = 1,                .write
		.rp_endofpacket          (onchip_memory_s1_agent_rp_endofpacket),                //  output,    width = 1,              rp.endofpacket
		.rp_ready                (onchip_memory_s1_agent_rp_ready),                      //   input,    width = 1,                .ready
		.rp_valid                (onchip_memory_s1_agent_rp_valid),                      //  output,    width = 1,                .valid
		.rp_data                 (onchip_memory_s1_agent_rp_data),                       //  output,  width = 154,                .data
		.rp_startofpacket        (onchip_memory_s1_agent_rp_startofpacket),              //  output,    width = 1,                .startofpacket
		.cp_ready                (onchip_memory_s1_burst_adapter_source0_ready),         //  output,    width = 1,              cp.ready
		.cp_valid                (onchip_memory_s1_burst_adapter_source0_valid),         //   input,    width = 1,                .valid
		.cp_data                 (onchip_memory_s1_burst_adapter_source0_data),          //   input,  width = 154,                .data
		.cp_startofpacket        (onchip_memory_s1_burst_adapter_source0_startofpacket), //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (onchip_memory_s1_burst_adapter_source0_endofpacket),   //   input,    width = 1,                .endofpacket
		.cp_channel              (onchip_memory_s1_burst_adapter_source0_channel),       //   input,    width = 6,                .channel
		.rf_sink_ready           (onchip_memory_s1_agent_rsp_fifo_out_ready),            //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (onchip_memory_s1_agent_rsp_fifo_out_valid),            //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (onchip_memory_s1_agent_rsp_fifo_out_startofpacket),    //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (onchip_memory_s1_agent_rsp_fifo_out_endofpacket),      //   input,    width = 1,                .endofpacket
		.rf_sink_data            (onchip_memory_s1_agent_rsp_fifo_out_data),             //   input,  width = 155,                .data
		.rf_source_ready         (onchip_memory_s1_agent_rf_source_ready),               //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (onchip_memory_s1_agent_rf_source_valid),               //  output,    width = 1,                .valid
		.rf_source_startofpacket (onchip_memory_s1_agent_rf_source_startofpacket),       //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (onchip_memory_s1_agent_rf_source_endofpacket),         //  output,    width = 1,                .endofpacket
		.rf_source_data          (onchip_memory_s1_agent_rf_source_data),                //  output,  width = 155,                .data
		.rdata_fifo_sink_ready   (onchip_memory_s1_agent_rdata_fifo_out_ready),          //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (onchip_memory_s1_agent_rdata_fifo_out_valid),          //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (onchip_memory_s1_agent_rdata_fifo_out_data),           //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (onchip_memory_s1_agent_rdata_fifo_src_ready),          //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (onchip_memory_s1_agent_rdata_fifo_src_valid),          //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (onchip_memory_s1_agent_rdata_fifo_src_data),           //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                  // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (155),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) onchip_memory_s1_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                 //   input,    width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, clk_reset.reset
		.in_data           (onchip_memory_s1_agent_rf_source_data),             //   input,  width = 155,        in.data
		.in_valid          (onchip_memory_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (onchip_memory_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (onchip_memory_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (onchip_memory_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (onchip_memory_s1_agent_rsp_fifo_out_data),          //  output,  width = 155,       out.data
		.out_valid         (onchip_memory_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (onchip_memory_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (onchip_memory_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (onchip_memory_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                             // (terminated),                         
		.csr_read          (1'b0),                                              // (terminated),                         
		.csr_write         (1'b0),                                              // (terminated),                         
		.csr_readdata      (),                                                  // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated),                         
		.almost_full_data  (),                                                  // (terminated),                         
		.almost_empty_data (),                                                  // (terminated),                         
		.in_empty          (1'b0),                                              // (terminated),                         
		.out_empty         (),                                                  // (terminated),                         
		.in_error          (1'b0),                                              // (terminated),                         
		.out_error         (),                                                  // (terminated),                         
		.in_channel        (1'b0),                                              // (terminated),                         
		.out_channel       ()                                                   // (terminated),                         
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) onchip_memory_s1_agent_rdata_fifo (
		.clk               (iopll_outclk0_clk),                           //   input,   width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),   //   input,   width = 1, clk_reset.reset
		.in_data           (onchip_memory_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (onchip_memory_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (onchip_memory_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (onchip_memory_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (onchip_memory_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (onchip_memory_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                       // (terminated),                        
		.csr_read          (1'b0),                                        // (terminated),                        
		.csr_write         (1'b0),                                        // (terminated),                        
		.csr_readdata      (),                                            // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),        // (terminated),                        
		.almost_full_data  (),                                            // (terminated),                        
		.almost_empty_data (),                                            // (terminated),                        
		.in_startofpacket  (1'b0),                                        // (terminated),                        
		.in_endofpacket    (1'b0),                                        // (terminated),                        
		.out_startofpacket (),                                            // (terminated),                        
		.out_endofpacket   (),                                            // (terminated),                        
		.in_empty          (1'b0),                                        // (terminated),                        
		.out_empty         (),                                            // (terminated),                        
		.in_error          (1'b0),                                        // (terminated),                        
		.out_error         (),                                            // (terminated),                        
		.in_channel        (1'b0),                                        // (terminated),                        
		.out_channel       ()                                             // (terminated),                        
	);

	nios_system_altera_merlin_slave_agent_1930_jxauz3i #(
		.PKT_ORI_BURST_SIZE_H      (126),
		.PKT_ORI_BURST_SIZE_L      (124),
		.PKT_RESPONSE_STATUS_H     (123),
		.PKT_RESPONSE_STATUS_L     (122),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (103),
		.PKT_PROTECTION_H          (117),
		.PKT_PROTECTION_L          (115),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (110),
		.PKT_SRC_ID_L              (108),
		.PKT_DEST_ID_H             (113),
		.PKT_DEST_ID_L             (111),
		.PKT_POISON_H              (136),
		.PKT_POISON_L              (136),
		.PKT_DATACHK_H             (137),
		.PKT_DATACHK_L             (137),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.PKT_ADDRCHK_H             (140),
		.PKT_ADDRCHK_L             (139),
		.PKT_USER_DATA_H           (138),
		.PKT_USER_DATA_L           (138),
		.PKT_ATRACE                (151),
		.PKT_TRACE                 (152),
		.PKT_AWAKEUP               (153),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (6),
		.ST_DATA_W                 (154),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0)
	) niosv_g_timer_sw_agent_agent (
		.clk                     (iopll_outclk0_clk),                                          //   input,    width = 1,             clk.clk
		.reset                   (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),        //   input,    width = 1,       clk_reset.reset
		.m0_address              (niosv_g_timer_sw_agent_agent_m0_address),                    //  output,   width = 32,              m0.address
		.m0_burstcount           (niosv_g_timer_sw_agent_agent_m0_burstcount),                 //  output,    width = 3,                .burstcount
		.m0_byteenable           (niosv_g_timer_sw_agent_agent_m0_byteenable),                 //  output,    width = 4,                .byteenable
		.m0_debugaccess          (niosv_g_timer_sw_agent_agent_m0_debugaccess),                //  output,    width = 1,                .debugaccess
		.m0_lock                 (niosv_g_timer_sw_agent_agent_m0_lock),                       //  output,    width = 1,                .lock
		.m0_readdata             (niosv_g_timer_sw_agent_agent_m0_readdata),                   //   input,   width = 32,                .readdata
		.m0_readdatavalid        (niosv_g_timer_sw_agent_agent_m0_readdatavalid),              //   input,    width = 1,                .readdatavalid
		.m0_read                 (niosv_g_timer_sw_agent_agent_m0_read),                       //  output,    width = 1,                .read
		.m0_waitrequest          (niosv_g_timer_sw_agent_agent_m0_waitrequest),                //   input,    width = 1,                .waitrequest
		.m0_writedata            (niosv_g_timer_sw_agent_agent_m0_writedata),                  //  output,   width = 32,                .writedata
		.m0_write                (niosv_g_timer_sw_agent_agent_m0_write),                      //  output,    width = 1,                .write
		.rp_endofpacket          (niosv_g_timer_sw_agent_agent_rp_endofpacket),                //  output,    width = 1,              rp.endofpacket
		.rp_ready                (niosv_g_timer_sw_agent_agent_rp_ready),                      //   input,    width = 1,                .ready
		.rp_valid                (niosv_g_timer_sw_agent_agent_rp_valid),                      //  output,    width = 1,                .valid
		.rp_data                 (niosv_g_timer_sw_agent_agent_rp_data),                       //  output,  width = 154,                .data
		.rp_startofpacket        (niosv_g_timer_sw_agent_agent_rp_startofpacket),              //  output,    width = 1,                .startofpacket
		.cp_ready                (niosv_g_timer_sw_agent_burst_adapter_source0_ready),         //  output,    width = 1,              cp.ready
		.cp_valid                (niosv_g_timer_sw_agent_burst_adapter_source0_valid),         //   input,    width = 1,                .valid
		.cp_data                 (niosv_g_timer_sw_agent_burst_adapter_source0_data),          //   input,  width = 154,                .data
		.cp_startofpacket        (niosv_g_timer_sw_agent_burst_adapter_source0_startofpacket), //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (niosv_g_timer_sw_agent_burst_adapter_source0_endofpacket),   //   input,    width = 1,                .endofpacket
		.cp_channel              (niosv_g_timer_sw_agent_burst_adapter_source0_channel),       //   input,    width = 6,                .channel
		.rf_sink_ready           (niosv_g_timer_sw_agent_agent_rsp_fifo_out_ready),            //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (niosv_g_timer_sw_agent_agent_rsp_fifo_out_valid),            //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (niosv_g_timer_sw_agent_agent_rsp_fifo_out_startofpacket),    //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (niosv_g_timer_sw_agent_agent_rsp_fifo_out_endofpacket),      //   input,    width = 1,                .endofpacket
		.rf_sink_data            (niosv_g_timer_sw_agent_agent_rsp_fifo_out_data),             //   input,  width = 155,                .data
		.rf_source_ready         (niosv_g_timer_sw_agent_agent_rf_source_ready),               //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (niosv_g_timer_sw_agent_agent_rf_source_valid),               //  output,    width = 1,                .valid
		.rf_source_startofpacket (niosv_g_timer_sw_agent_agent_rf_source_startofpacket),       //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (niosv_g_timer_sw_agent_agent_rf_source_endofpacket),         //  output,    width = 1,                .endofpacket
		.rf_source_data          (niosv_g_timer_sw_agent_agent_rf_source_data),                //  output,  width = 155,                .data
		.rdata_fifo_sink_ready   (niosv_g_timer_sw_agent_agent_rdata_fifo_out_ready),          //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (niosv_g_timer_sw_agent_agent_rdata_fifo_out_valid),          //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (niosv_g_timer_sw_agent_agent_rdata_fifo_out_data),           //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (niosv_g_timer_sw_agent_agent_rdata_fifo_src_ready),          //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (niosv_g_timer_sw_agent_agent_rdata_fifo_src_valid),          //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (niosv_g_timer_sw_agent_agent_rdata_fifo_src_data),           //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                      // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                       // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                        // (terminated),                               
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (155),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) niosv_g_timer_sw_agent_agent_rsp_fifo (
		.clk               (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),               //   input,    width = 1, clk_reset.reset
		.in_data           (niosv_g_timer_sw_agent_agent_rf_source_data),             //   input,  width = 155,        in.data
		.in_valid          (niosv_g_timer_sw_agent_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (niosv_g_timer_sw_agent_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (niosv_g_timer_sw_agent_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (niosv_g_timer_sw_agent_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (niosv_g_timer_sw_agent_agent_rsp_fifo_out_data),          //  output,  width = 155,       out.data
		.out_valid         (niosv_g_timer_sw_agent_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (niosv_g_timer_sw_agent_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (niosv_g_timer_sw_agent_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (niosv_g_timer_sw_agent_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                   // (terminated),                         
		.csr_read          (1'b0),                                                    // (terminated),                         
		.csr_write         (1'b0),                                                    // (terminated),                         
		.csr_readdata      (),                                                        // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated),                         
		.almost_full_data  (),                                                        // (terminated),                         
		.almost_empty_data (),                                                        // (terminated),                         
		.in_empty          (1'b0),                                                    // (terminated),                         
		.out_empty         (),                                                        // (terminated),                         
		.in_error          (1'b0),                                                    // (terminated),                         
		.out_error         (),                                                        // (terminated),                         
		.in_channel        (1'b0),                                                    // (terminated),                         
		.out_channel       ()                                                         // (terminated),                         
	);

	nios_system_altera_avalon_sc_fifo_1932_22gxxgi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) niosv_g_timer_sw_agent_agent_rdata_fifo (
		.clk               (iopll_outclk0_clk),                                 //   input,   width = 1,       clk.clk
		.reset             (niosv_g_reset_reset_bridge_in_reset_reset),         //   input,   width = 1, clk_reset.reset
		.in_data           (niosv_g_timer_sw_agent_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (niosv_g_timer_sw_agent_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (niosv_g_timer_sw_agent_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (niosv_g_timer_sw_agent_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (niosv_g_timer_sw_agent_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (niosv_g_timer_sw_agent_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                             // (terminated),                        
		.csr_read          (1'b0),                                              // (terminated),                        
		.csr_write         (1'b0),                                              // (terminated),                        
		.csr_readdata      (),                                                  // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated),                        
		.almost_full_data  (),                                                  // (terminated),                        
		.almost_empty_data (),                                                  // (terminated),                        
		.in_startofpacket  (1'b0),                                              // (terminated),                        
		.in_endofpacket    (1'b0),                                              // (terminated),                        
		.out_startofpacket (),                                                  // (terminated),                        
		.out_endofpacket   (),                                                  // (terminated),                        
		.in_empty          (1'b0),                                              // (terminated),                        
		.out_empty         (),                                                  // (terminated),                        
		.in_error          (1'b0),                                              // (terminated),                        
		.out_error         (),                                                  // (terminated),                        
		.in_channel        (1'b0),                                              // (terminated),                        
		.out_channel       ()                                                   // (terminated),                        
	);

	nios_system_altera_merlin_router_1921_tskfxay router (
		.sink_ready         (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_data),          //   input,  width = 406,          .data
		.sink_startofpacket (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_vvp_vfr_av_mm_mem_read_host_agent_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                        //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),      //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                         //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                         //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                          //  output,  width = 406,          .data
		.src_channel        (router_src_channel),                                       //  output,    width = 6,          .channel
		.src_startofpacket  (router_src_startofpacket),                                 //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                    //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_qcihwxy router_001 (
		.sink_ready         (niosv_g_data_manager_agent_write_cp_ready),           //  output,    width = 1,      sink.ready
		.sink_valid         (niosv_g_data_manager_agent_write_cp_valid),           //   input,    width = 1,          .valid
		.sink_data          (niosv_g_data_manager_agent_write_cp_data),            //   input,  width = 154,          .data
		.sink_startofpacket (niosv_g_data_manager_agent_write_cp_startofpacket),   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (niosv_g_data_manager_agent_write_cp_endofpacket),     //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                 //  output,  width = 154,          .data
		.src_channel        (router_001_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_drs4cuy router_002 (
		.sink_ready         (niosv_g_data_manager_agent_read_cp_ready),            //  output,    width = 1,      sink.ready
		.sink_valid         (niosv_g_data_manager_agent_read_cp_valid),            //   input,    width = 1,          .valid
		.sink_data          (niosv_g_data_manager_agent_read_cp_data),             //   input,  width = 154,          .data
		.sink_startofpacket (niosv_g_data_manager_agent_read_cp_startofpacket),    //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (niosv_g_data_manager_agent_read_cp_endofpacket),      //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                 //  output,  width = 154,          .data
		.src_channel        (router_002_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_ui7ivra router_003 (
		.sink_ready         (niosv_g_instruction_manager_agent_write_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (niosv_g_instruction_manager_agent_write_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (niosv_g_instruction_manager_agent_write_cp_data),          //   input,  width = 154,          .data
		.sink_startofpacket (niosv_g_instruction_manager_agent_write_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (niosv_g_instruction_manager_agent_write_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                        //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),      //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                                     //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                                     //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                                      //  output,  width = 154,          .data
		.src_channel        (router_003_src_channel),                                   //  output,    width = 6,          .channel
		.src_startofpacket  (router_003_src_startofpacket),                             //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                                //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_ui7ivra router_004 (
		.sink_ready         (niosv_g_instruction_manager_agent_read_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (niosv_g_instruction_manager_agent_read_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (niosv_g_instruction_manager_agent_read_cp_data),          //   input,  width = 154,          .data
		.sink_startofpacket (niosv_g_instruction_manager_agent_read_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (niosv_g_instruction_manager_agent_read_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                       //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                                    //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                                    //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                                     //  output,  width = 154,          .data
		.src_channel        (router_004_src_channel),                                  //  output,    width = 6,          .channel
		.src_startofpacket  (router_004_src_startofpacket),                            //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                               //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_sqaahmy router_005 (
		.sink_ready         (sdram_axi4_slave_agent_write_rp_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (sdram_axi4_slave_agent_write_rp_valid),               //   input,    width = 1,          .valid
		.sink_data          (sdram_axi4_slave_agent_write_rp_data),                //   input,  width = 190,          .data
		.sink_startofpacket (sdram_axi4_slave_agent_write_rp_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sdram_axi4_slave_agent_write_rp_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_005_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_005_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_005_src_data),                                 //  output,  width = 190,          .data
		.src_channel        (router_005_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_005_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_g2m2shi router_006 (
		.sink_ready         (sdram_axi4_slave_agent_read_rp_ready),                //  output,    width = 1,      sink.ready
		.sink_valid         (sdram_axi4_slave_agent_read_rp_valid),                //   input,    width = 1,          .valid
		.sink_data          (sdram_axi4_slave_agent_read_rp_data),                 //   input,  width = 190,          .data
		.sink_startofpacket (sdram_axi4_slave_agent_read_rp_startofpacket),        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sdram_axi4_slave_agent_read_rp_endofpacket),          //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_006_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_006_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_006_src_data),                                 //  output,  width = 190,          .data
		.src_channel        (router_006_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_006_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_ux3f3gi router_007 (
		.sink_ready         (niosv_g_dm_agent_agent_rp_ready),                     //  output,    width = 1,      sink.ready
		.sink_valid         (niosv_g_dm_agent_agent_rp_valid),                     //   input,    width = 1,          .valid
		.sink_data          (niosv_g_dm_agent_agent_rp_data),                      //   input,  width = 154,          .data
		.sink_startofpacket (niosv_g_dm_agent_agent_rp_startofpacket),             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (niosv_g_dm_agent_agent_rp_endofpacket),               //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_007_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_007_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_007_src_data),                                 //  output,  width = 154,          .data
		.src_channel        (router_007_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_007_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_eomz43y router_008 (
		.sink_ready         (mm_bridge_peripheral_s0_agent_rp_ready),              //  output,    width = 1,      sink.ready
		.sink_valid         (mm_bridge_peripheral_s0_agent_rp_valid),              //   input,    width = 1,          .valid
		.sink_data          (mm_bridge_peripheral_s0_agent_rp_data),               //   input,  width = 154,          .data
		.sink_startofpacket (mm_bridge_peripheral_s0_agent_rp_startofpacket),      //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (mm_bridge_peripheral_s0_agent_rp_endofpacket),        //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_008_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_008_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_008_src_data),                                 //  output,  width = 154,          .data
		.src_channel        (router_008_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_008_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_ux3f3gi router_009 (
		.sink_ready         (onchip_memory_s1_agent_rp_ready),                     //  output,    width = 1,      sink.ready
		.sink_valid         (onchip_memory_s1_agent_rp_valid),                     //   input,    width = 1,          .valid
		.sink_data          (onchip_memory_s1_agent_rp_data),                      //   input,  width = 154,          .data
		.sink_startofpacket (onchip_memory_s1_agent_rp_startofpacket),             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (onchip_memory_s1_agent_rp_endofpacket),               //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_009_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_009_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_009_src_data),                                 //  output,  width = 154,          .data
		.src_channel        (router_009_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_009_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_009_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_router_1921_eomz43y router_010 (
		.sink_ready         (niosv_g_timer_sw_agent_agent_rp_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (niosv_g_timer_sw_agent_agent_rp_valid),               //   input,    width = 1,          .valid
		.sink_data          (niosv_g_timer_sw_agent_agent_rp_data),                //   input,  width = 154,          .data
		.sink_startofpacket (niosv_g_timer_sw_agent_agent_rp_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (niosv_g_timer_sw_agent_agent_rp_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_010_src_ready),                                //   input,    width = 1,       src.ready
		.src_valid          (router_010_src_valid),                                //  output,    width = 1,          .valid
		.src_data           (router_010_src_data),                                 //  output,  width = 154,          .data
		.src_channel        (router_010_src_channel),                              //  output,    width = 6,          .channel
		.src_startofpacket  (router_010_src_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_010_src_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_traffic_limiter_1921_p3fvlba #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (365),
		.PKT_DEST_ID_L                        (363),
		.PKT_SRC_ID_H                         (362),
		.PKT_SRC_ID_L                         (360),
		.PKT_BYTE_CNT_H                       (339),
		.PKT_BYTE_CNT_L                       (326),
		.PKT_BYTEEN_H                         (287),
		.PKT_BYTEEN_L                         (256),
		.PKT_TRANS_POSTED                     (321),
		.PKT_TRANS_WRITE                      (322),
		.PKT_TRANS_SEQ_H                      (402),
		.PKT_TRANS_SEQ_L                      (396),
		.MAX_OUTSTANDING_RESPONSES            (2),
		.PIPELINED                            (0),
		.ST_DATA_W                            (406),
		.ST_CHANNEL_W                         (6),
		.VALID_WIDTH                          (6),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (1),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) intel_vvp_vfr_av_mm_mem_read_host_limiter (
		.clk                    (iopll_outclk0_clk),                                               //   input,    width = 1,       clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                                //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                                //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                                 //   input,  width = 406,          .data
		.cmd_sink_channel       (router_src_channel),                                              //   input,    width = 6,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                        //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                          //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_data),          //  output,  width = 406,          .data
		.cmd_src_channel        (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_channel),       //  output,    width = 6,          .channel
		.cmd_src_startofpacket  (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_src_ready),                                               //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_src_valid),                                               //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_src_channel),                                             //   input,    width = 6,          .channel
		.rsp_sink_data          (rsp_mux_src_data),                                                //   input,  width = 406,          .data
		.rsp_sink_startofpacket (rsp_mux_src_startofpacket),                                       //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_src_endofpacket),                                         //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_data),          //  output,  width = 406,          .data
		.rsp_src_channel        (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_channel),       //  output,    width = 6,          .channel
		.rsp_src_startofpacket  (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (intel_vvp_vfr_av_mm_mem_read_host_limiter_rsp_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_valid_data)         //  output,    width = 6, cmd_valid.data
	);

	nios_system_altera_merlin_traffic_limiter_1921_5pm4apa #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (113),
		.PKT_DEST_ID_L                        (111),
		.PKT_SRC_ID_H                         (110),
		.PKT_SRC_ID_L                         (108),
		.PKT_BYTE_CNT_H                       (87),
		.PKT_BYTE_CNT_L                       (74),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (69),
		.PKT_TRANS_WRITE                      (70),
		.PKT_TRANS_SEQ_H                      (150),
		.PKT_TRANS_SEQ_L                      (144),
		.MAX_OUTSTANDING_RESPONSES            (5),
		.PIPELINED                            (0),
		.ST_DATA_W                            (154),
		.ST_CHANNEL_W                         (6),
		.VALID_WIDTH                          (6),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) niosv_g_instruction_manager_wr_limiter (
		.clk                    (iopll_outclk0_clk),                                            //   input,    width = 1,       clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),          //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_003_src_ready),                                         //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_003_src_valid),                                         //   input,    width = 1,          .valid
		.cmd_sink_data          (router_003_src_data),                                          //   input,  width = 154,          .data
		.cmd_sink_channel       (router_003_src_channel),                                       //   input,    width = 6,          .channel
		.cmd_sink_startofpacket (router_003_src_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_003_src_endofpacket),                                   //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (niosv_g_instruction_manager_wr_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (niosv_g_instruction_manager_wr_limiter_cmd_src_data),          //  output,  width = 154,          .data
		.cmd_src_channel        (niosv_g_instruction_manager_wr_limiter_cmd_src_channel),       //  output,    width = 6,          .channel
		.cmd_src_startofpacket  (niosv_g_instruction_manager_wr_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (niosv_g_instruction_manager_wr_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_003_src_ready),                                        //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_003_src_valid),                                        //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_003_src_channel),                                      //   input,    width = 6,          .channel
		.rsp_sink_data          (rsp_mux_003_src_data),                                         //   input,  width = 154,          .data
		.rsp_sink_startofpacket (rsp_mux_003_src_startofpacket),                                //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_003_src_endofpacket),                                  //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (niosv_g_instruction_manager_wr_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (niosv_g_instruction_manager_wr_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (niosv_g_instruction_manager_wr_limiter_rsp_src_data),          //  output,  width = 154,          .data
		.rsp_src_channel        (niosv_g_instruction_manager_wr_limiter_rsp_src_channel),       //  output,    width = 6,          .channel
		.rsp_src_startofpacket  (niosv_g_instruction_manager_wr_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (niosv_g_instruction_manager_wr_limiter_rsp_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (niosv_g_instruction_manager_wr_limiter_cmd_valid_data)         //  output,    width = 6, cmd_valid.data
	);

	nios_system_altera_merlin_traffic_limiter_1921_5pm4apa #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (113),
		.PKT_DEST_ID_L                        (111),
		.PKT_SRC_ID_H                         (110),
		.PKT_SRC_ID_L                         (108),
		.PKT_BYTE_CNT_H                       (87),
		.PKT_BYTE_CNT_L                       (74),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (69),
		.PKT_TRANS_WRITE                      (70),
		.PKT_TRANS_SEQ_H                      (150),
		.PKT_TRANS_SEQ_L                      (144),
		.MAX_OUTSTANDING_RESPONSES            (5),
		.PIPELINED                            (0),
		.ST_DATA_W                            (154),
		.ST_CHANNEL_W                         (6),
		.VALID_WIDTH                          (6),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) niosv_g_instruction_manager_rd_limiter (
		.clk                    (iopll_outclk0_clk),                                            //   input,    width = 1,       clk.clk
		.reset                  (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),          //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_004_src_ready),                                         //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_004_src_valid),                                         //   input,    width = 1,          .valid
		.cmd_sink_data          (router_004_src_data),                                          //   input,  width = 154,          .data
		.cmd_sink_channel       (router_004_src_channel),                                       //   input,    width = 6,          .channel
		.cmd_sink_startofpacket (router_004_src_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_004_src_endofpacket),                                   //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (niosv_g_instruction_manager_rd_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (niosv_g_instruction_manager_rd_limiter_cmd_src_data),          //  output,  width = 154,          .data
		.cmd_src_channel        (niosv_g_instruction_manager_rd_limiter_cmd_src_channel),       //  output,    width = 6,          .channel
		.cmd_src_startofpacket  (niosv_g_instruction_manager_rd_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (niosv_g_instruction_manager_rd_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_004_src_ready),                                        //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_004_src_valid),                                        //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_004_src_channel),                                      //   input,    width = 6,          .channel
		.rsp_sink_data          (rsp_mux_004_src_data),                                         //   input,  width = 154,          .data
		.rsp_sink_startofpacket (rsp_mux_004_src_startofpacket),                                //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_004_src_endofpacket),                                  //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (niosv_g_instruction_manager_rd_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (niosv_g_instruction_manager_rd_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (niosv_g_instruction_manager_rd_limiter_rsp_src_data),          //  output,  width = 154,          .data
		.rsp_src_channel        (niosv_g_instruction_manager_rd_limiter_rsp_src_channel),       //  output,    width = 6,          .channel
		.rsp_src_startofpacket  (niosv_g_instruction_manager_rd_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (niosv_g_instruction_manager_rd_limiter_rsp_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (niosv_g_instruction_manager_rd_limiter_cmd_valid_data)         //  output,    width = 6, cmd_valid.data
	);

	nios_system_altera_merlin_burst_adapter_1940_46k3ybi #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (103),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_BURST_TYPE_H          (100),
		.PKT_BURST_TYPE_L          (99),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (154),
		.ST_CHANNEL_W              (6),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (95),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) niosv_g_dm_agent_burst_adapter (
		.clk                   (iopll_outclk0_clk),                                    //   input,    width = 1,       cr0.clk
		.reset                 (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),  //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_002_src_valid),                                //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_002_src_data),                                 //   input,  width = 154,          .data
		.sink0_channel         (cmd_mux_002_src_channel),                              //   input,    width = 6,          .channel
		.sink0_startofpacket   (cmd_mux_002_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_002_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_002_src_ready),                                //  output,    width = 1,          .ready
		.source0_valid         (niosv_g_dm_agent_burst_adapter_source0_valid),         //  output,    width = 1,   source0.valid
		.source0_data          (niosv_g_dm_agent_burst_adapter_source0_data),          //  output,  width = 154,          .data
		.source0_channel       (niosv_g_dm_agent_burst_adapter_source0_channel),       //  output,    width = 6,          .channel
		.source0_startofpacket (niosv_g_dm_agent_burst_adapter_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (niosv_g_dm_agent_burst_adapter_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.source0_ready         (niosv_g_dm_agent_burst_adapter_source0_ready)          //   input,    width = 1,          .ready
	);

	nios_system_altera_merlin_burst_adapter_1940_46k3ybi #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (103),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_BURST_TYPE_H          (100),
		.PKT_BURST_TYPE_L          (99),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (154),
		.ST_CHANNEL_W              (6),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (95),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) mm_bridge_peripheral_s0_burst_adapter (
		.clk                   (iopll_outclk0_clk),                                           //   input,    width = 1,       cr0.clk
		.reset                 (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_003_src_valid),                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_003_src_data),                                        //   input,  width = 154,          .data
		.sink0_channel         (cmd_mux_003_src_channel),                                     //   input,    width = 6,          .channel
		.sink0_startofpacket   (cmd_mux_003_src_startofpacket),                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_003_src_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_003_src_ready),                                       //  output,    width = 1,          .ready
		.source0_valid         (mm_bridge_peripheral_s0_burst_adapter_source0_valid),         //  output,    width = 1,   source0.valid
		.source0_data          (mm_bridge_peripheral_s0_burst_adapter_source0_data),          //  output,  width = 154,          .data
		.source0_channel       (mm_bridge_peripheral_s0_burst_adapter_source0_channel),       //  output,    width = 6,          .channel
		.source0_startofpacket (mm_bridge_peripheral_s0_burst_adapter_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (mm_bridge_peripheral_s0_burst_adapter_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.source0_ready         (mm_bridge_peripheral_s0_burst_adapter_source0_ready)          //   input,    width = 1,          .ready
	);

	nios_system_altera_merlin_burst_adapter_1940_46k3ybi #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (103),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_BURST_TYPE_H          (100),
		.PKT_BURST_TYPE_L          (99),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (154),
		.ST_CHANNEL_W              (6),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (95),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) onchip_memory_s1_burst_adapter (
		.clk                   (iopll_outclk0_clk),                                    //   input,    width = 1,       cr0.clk
		.reset                 (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),  //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_004_src_valid),                                //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_004_src_data),                                 //   input,  width = 154,          .data
		.sink0_channel         (cmd_mux_004_src_channel),                              //   input,    width = 6,          .channel
		.sink0_startofpacket   (cmd_mux_004_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_004_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_004_src_ready),                                //  output,    width = 1,          .ready
		.source0_valid         (onchip_memory_s1_burst_adapter_source0_valid),         //  output,    width = 1,   source0.valid
		.source0_data          (onchip_memory_s1_burst_adapter_source0_data),          //  output,  width = 154,          .data
		.source0_channel       (onchip_memory_s1_burst_adapter_source0_channel),       //  output,    width = 6,          .channel
		.source0_startofpacket (onchip_memory_s1_burst_adapter_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (onchip_memory_s1_burst_adapter_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.source0_ready         (onchip_memory_s1_burst_adapter_source0_ready)          //   input,    width = 1,          .ready
	);

	nios_system_altera_merlin_burst_adapter_1940_46k3ybi #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (103),
		.PKT_BYTE_CNT_H            (87),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (98),
		.PKT_BURST_SIZE_L          (96),
		.PKT_BURST_TYPE_H          (100),
		.PKT_BURST_TYPE_L          (99),
		.PKT_BURSTWRAP_H           (95),
		.PKT_BURSTWRAP_L           (88),
		.PKT_SAI_H                 (141),
		.PKT_SAI_L                 (141),
		.ROLE_BASED_USER           (0),
		.ENABLE_AXI5               (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (154),
		.ST_CHANNEL_W              (6),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (95),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) niosv_g_timer_sw_agent_burst_adapter (
		.clk                   (iopll_outclk0_clk),                                          //   input,    width = 1,       cr0.clk
		.reset                 (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),        //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_005_src_valid),                                      //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_005_src_data),                                       //   input,  width = 154,          .data
		.sink0_channel         (cmd_mux_005_src_channel),                                    //   input,    width = 6,          .channel
		.sink0_startofpacket   (cmd_mux_005_src_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_005_src_endofpacket),                                //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_005_src_ready),                                      //  output,    width = 1,          .ready
		.source0_valid         (niosv_g_timer_sw_agent_burst_adapter_source0_valid),         //  output,    width = 1,   source0.valid
		.source0_data          (niosv_g_timer_sw_agent_burst_adapter_source0_data),          //  output,  width = 154,          .data
		.source0_channel       (niosv_g_timer_sw_agent_burst_adapter_source0_channel),       //  output,    width = 6,          .channel
		.source0_startofpacket (niosv_g_timer_sw_agent_burst_adapter_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (niosv_g_timer_sw_agent_burst_adapter_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.source0_ready         (niosv_g_timer_sw_agent_burst_adapter_source0_ready)          //   input,    width = 1,          .ready
	);

	nios_system_altera_merlin_demultiplexer_1921_p47gxfy cmd_demux (
		.clk                (iopll_outclk0_clk),                                               //   input,    width = 1,        clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),             //   input,    width = 1,  clk_reset.reset
		.sink_ready         (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_ready),         //  output,    width = 1,       sink.ready
		.sink_channel       (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_channel),       //   input,    width = 6,           .channel
		.sink_data          (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_data),          //   input,  width = 406,           .data
		.sink_startofpacket (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_startofpacket), //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_src_endofpacket),   //   input,    width = 1,           .endofpacket
		.sink_valid         (intel_vvp_vfr_av_mm_mem_read_host_limiter_cmd_valid_data),        //   input,    width = 6, sink_valid.data
		.src0_ready         (cmd_demux_src0_ready),                                            //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                            //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_src0_data),                                             //  output,  width = 406,           .data
		.src0_channel       (cmd_demux_src0_channel),                                          //  output,    width = 6,           .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                    //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                      //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                            //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                            //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_src1_data),                                             //  output,  width = 406,           .data
		.src1_channel       (cmd_demux_src1_channel),                                          //  output,    width = 6,           .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                    //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                       //  output,    width = 1,           .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_s7etjsa cmd_demux_001 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_001_src_data),                                 //   input,  width = 154,          .data
		.sink_startofpacket (router_001_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_001_src0_data),                             //  output,  width = 154,          .data
		.src0_channel       (cmd_demux_001_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_001_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_001_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_001_src1_data),                             //  output,  width = 154,          .data
		.src1_channel       (cmd_demux_001_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (cmd_demux_001_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_001_src1_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src2_ready         (cmd_demux_001_src2_ready),                            //   input,    width = 1,      src2.ready
		.src2_valid         (cmd_demux_001_src2_valid),                            //  output,    width = 1,          .valid
		.src2_data          (cmd_demux_001_src2_data),                             //  output,  width = 154,          .data
		.src2_channel       (cmd_demux_001_src2_channel),                          //  output,    width = 6,          .channel
		.src2_startofpacket (cmd_demux_001_src2_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (cmd_demux_001_src2_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src3_ready         (cmd_demux_001_src3_ready),                            //   input,    width = 1,      src3.ready
		.src3_valid         (cmd_demux_001_src3_valid),                            //  output,    width = 1,          .valid
		.src3_data          (cmd_demux_001_src3_data),                             //  output,  width = 154,          .data
		.src3_channel       (cmd_demux_001_src3_channel),                          //  output,    width = 6,          .channel
		.src3_startofpacket (cmd_demux_001_src3_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (cmd_demux_001_src3_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src4_ready         (cmd_demux_001_src4_ready),                            //   input,    width = 1,      src4.ready
		.src4_valid         (cmd_demux_001_src4_valid),                            //  output,    width = 1,          .valid
		.src4_data          (cmd_demux_001_src4_data),                             //  output,  width = 154,          .data
		.src4_channel       (cmd_demux_001_src4_channel),                          //  output,    width = 6,          .channel
		.src4_startofpacket (cmd_demux_001_src4_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src4_endofpacket   (cmd_demux_001_src4_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_s7etjsa cmd_demux_002 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_002_src_data),                                 //   input,  width = 154,          .data
		.sink_startofpacket (router_002_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_002_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_002_src0_data),                             //  output,  width = 154,          .data
		.src0_channel       (cmd_demux_002_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_002_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_002_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_002_src1_data),                             //  output,  width = 154,          .data
		.src1_channel       (cmd_demux_002_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (cmd_demux_002_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_002_src1_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src2_ready         (cmd_demux_002_src2_ready),                            //   input,    width = 1,      src2.ready
		.src2_valid         (cmd_demux_002_src2_valid),                            //  output,    width = 1,          .valid
		.src2_data          (cmd_demux_002_src2_data),                             //  output,  width = 154,          .data
		.src2_channel       (cmd_demux_002_src2_channel),                          //  output,    width = 6,          .channel
		.src2_startofpacket (cmd_demux_002_src2_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (cmd_demux_002_src2_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src3_ready         (cmd_demux_002_src3_ready),                            //   input,    width = 1,      src3.ready
		.src3_valid         (cmd_demux_002_src3_valid),                            //  output,    width = 1,          .valid
		.src3_data          (cmd_demux_002_src3_data),                             //  output,  width = 154,          .data
		.src3_channel       (cmd_demux_002_src3_channel),                          //  output,    width = 6,          .channel
		.src3_startofpacket (cmd_demux_002_src3_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (cmd_demux_002_src3_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src4_ready         (cmd_demux_002_src4_ready),                            //   input,    width = 1,      src4.ready
		.src4_valid         (cmd_demux_002_src4_valid),                            //  output,    width = 1,          .valid
		.src4_data          (cmd_demux_002_src4_data),                             //  output,  width = 154,          .data
		.src4_channel       (cmd_demux_002_src4_channel),                          //  output,    width = 6,          .channel
		.src4_startofpacket (cmd_demux_002_src4_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src4_endofpacket   (cmd_demux_002_src4_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_xaihpji cmd_demux_003 (
		.clk                (iopll_outclk0_clk),                                            //   input,    width = 1,        clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),          //   input,    width = 1,  clk_reset.reset
		.sink_ready         (niosv_g_instruction_manager_wr_limiter_cmd_src_ready),         //  output,    width = 1,       sink.ready
		.sink_channel       (niosv_g_instruction_manager_wr_limiter_cmd_src_channel),       //   input,    width = 6,           .channel
		.sink_data          (niosv_g_instruction_manager_wr_limiter_cmd_src_data),          //   input,  width = 154,           .data
		.sink_startofpacket (niosv_g_instruction_manager_wr_limiter_cmd_src_startofpacket), //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (niosv_g_instruction_manager_wr_limiter_cmd_src_endofpacket),   //   input,    width = 1,           .endofpacket
		.sink_valid         (niosv_g_instruction_manager_wr_limiter_cmd_valid_data),        //   input,    width = 6, sink_valid.data
		.src0_ready         (cmd_demux_003_src0_ready),                                     //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_003_src0_valid),                                     //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_003_src0_data),                                      //  output,  width = 154,           .data
		.src0_channel       (cmd_demux_003_src0_channel),                                   //  output,    width = 6,           .channel
		.src0_startofpacket (cmd_demux_003_src0_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_003_src0_endofpacket),                               //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_003_src1_ready),                                     //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_003_src1_valid),                                     //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_003_src1_data),                                      //  output,  width = 154,           .data
		.src1_channel       (cmd_demux_003_src1_channel),                                   //  output,    width = 6,           .channel
		.src1_startofpacket (cmd_demux_003_src1_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_003_src1_endofpacket)                                //  output,    width = 1,           .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_xaihpji cmd_demux_004 (
		.clk                (iopll_outclk0_clk),                                            //   input,    width = 1,        clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),          //   input,    width = 1,  clk_reset.reset
		.sink_ready         (niosv_g_instruction_manager_rd_limiter_cmd_src_ready),         //  output,    width = 1,       sink.ready
		.sink_channel       (niosv_g_instruction_manager_rd_limiter_cmd_src_channel),       //   input,    width = 6,           .channel
		.sink_data          (niosv_g_instruction_manager_rd_limiter_cmd_src_data),          //   input,  width = 154,           .data
		.sink_startofpacket (niosv_g_instruction_manager_rd_limiter_cmd_src_startofpacket), //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (niosv_g_instruction_manager_rd_limiter_cmd_src_endofpacket),   //   input,    width = 1,           .endofpacket
		.sink_valid         (niosv_g_instruction_manager_rd_limiter_cmd_valid_data),        //   input,    width = 6, sink_valid.data
		.src0_ready         (cmd_demux_004_src0_ready),                                     //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_004_src0_valid),                                     //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_004_src0_data),                                      //  output,  width = 154,           .data
		.src0_channel       (cmd_demux_004_src0_channel),                                   //  output,    width = 6,           .channel
		.src0_startofpacket (cmd_demux_004_src0_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_004_src0_endofpacket),                               //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_004_src1_ready),                                     //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_004_src1_valid),                                     //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_004_src1_data),                                      //  output,  width = 154,           .data
		.src1_channel       (cmd_demux_004_src1_channel),                                   //  output,    width = 6,           .channel
		.src1_startofpacket (cmd_demux_004_src1_startofpacket),                             //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_004_src1_endofpacket)                                //  output,    width = 1,           .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_dm22zrq cmd_mux (
		.clk                 (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                                            //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                                                            //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                                                             //  output,  width = 190,          .data
		.src_channel         (cmd_mux_src_channel),                                                                          //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                                                    //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                                                      //  output,    width = 1,          .endofpacket
		.sink0_ready         (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.sink0_valid         (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.sink0_channel       (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_channel),       //   input,    width = 6,          .channel
		.sink0_data          (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_data),          //   input,  width = 190,          .data
		.sink0_startofpacket (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink1_ready         (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_ready),                   //  output,    width = 1,     sink1.ready
		.sink1_valid         (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_valid),                   //   input,    width = 1,          .valid
		.sink1_channel       (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_channel),                 //   input,    width = 6,          .channel
		.sink1_data          (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_data),                    //   input,  width = 190,          .data
		.sink1_startofpacket (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket),           //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket)              //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_dm22zrq cmd_mux_001 (
		.clk                 (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                                                        //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                                                        //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                                                         //  output,  width = 190,          .data
		.src_channel         (cmd_mux_001_src_channel),                                                                      //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                                                  //  output,    width = 1,          .endofpacket
		.sink0_ready         (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.sink0_valid         (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.sink0_channel       (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_channel),       //   input,    width = 6,          .channel
		.sink0_data          (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_data),          //   input,  width = 190,          .data
		.sink0_startofpacket (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink1_ready         (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_ready),                   //  output,    width = 1,     sink1.ready
		.sink1_valid         (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_valid),                   //   input,    width = 1,          .valid
		.sink1_channel       (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_channel),                 //   input,    width = 6,          .channel
		.sink1_data          (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_data),                    //   input,  width = 190,          .data
		.sink1_startofpacket (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket),           //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket)              //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_pjxnofq cmd_mux_002 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                                //  output,  width = 154,          .data
		.src_channel         (cmd_mux_002_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_001_src1_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_001_src1_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_001_src1_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_001_src1_data),                             //   input,  width = 154,          .data
		.sink0_startofpacket (cmd_demux_001_src1_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src1_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_002_src1_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_002_src1_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_002_src1_channel),                          //   input,    width = 6,          .channel
		.sink1_data          (cmd_demux_002_src1_data),                             //   input,  width = 154,          .data
		.sink1_startofpacket (cmd_demux_002_src1_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src1_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink2_ready         (cmd_demux_003_src0_ready),                            //  output,    width = 1,     sink2.ready
		.sink2_valid         (cmd_demux_003_src0_valid),                            //   input,    width = 1,          .valid
		.sink2_channel       (cmd_demux_003_src0_channel),                          //   input,    width = 6,          .channel
		.sink2_data          (cmd_demux_003_src0_data),                             //   input,  width = 154,          .data
		.sink2_startofpacket (cmd_demux_003_src0_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (cmd_demux_003_src0_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink3_ready         (cmd_demux_004_src0_ready),                            //  output,    width = 1,     sink3.ready
		.sink3_valid         (cmd_demux_004_src0_valid),                            //   input,    width = 1,          .valid
		.sink3_channel       (cmd_demux_004_src0_channel),                          //   input,    width = 6,          .channel
		.sink3_data          (cmd_demux_004_src0_data),                             //   input,  width = 154,          .data
		.sink3_startofpacket (cmd_demux_004_src0_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (cmd_demux_004_src0_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_wh2scqi cmd_mux_003 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                                //  output,  width = 154,          .data
		.src_channel         (cmd_mux_003_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_001_src2_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_001_src2_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_001_src2_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_001_src2_data),                             //   input,  width = 154,          .data
		.sink0_startofpacket (cmd_demux_001_src2_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src2_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_002_src2_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_002_src2_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_002_src2_channel),                          //   input,    width = 6,          .channel
		.sink1_data          (cmd_demux_002_src2_data),                             //   input,  width = 154,          .data
		.sink1_startofpacket (cmd_demux_002_src2_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src2_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_pjxnofq cmd_mux_004 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_004_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_004_src_data),                                //  output,  width = 154,          .data
		.src_channel         (cmd_mux_004_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_001_src3_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_001_src3_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_001_src3_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_001_src3_data),                             //   input,  width = 154,          .data
		.sink0_startofpacket (cmd_demux_001_src3_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src3_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_002_src3_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_002_src3_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_002_src3_channel),                          //   input,    width = 6,          .channel
		.sink1_data          (cmd_demux_002_src3_data),                             //   input,  width = 154,          .data
		.sink1_startofpacket (cmd_demux_002_src3_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src3_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink2_ready         (cmd_demux_003_src1_ready),                            //  output,    width = 1,     sink2.ready
		.sink2_valid         (cmd_demux_003_src1_valid),                            //   input,    width = 1,          .valid
		.sink2_channel       (cmd_demux_003_src1_channel),                          //   input,    width = 6,          .channel
		.sink2_data          (cmd_demux_003_src1_data),                             //   input,  width = 154,          .data
		.sink2_startofpacket (cmd_demux_003_src1_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (cmd_demux_003_src1_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink3_ready         (cmd_demux_004_src1_ready),                            //  output,    width = 1,     sink3.ready
		.sink3_valid         (cmd_demux_004_src1_valid),                            //   input,    width = 1,          .valid
		.sink3_channel       (cmd_demux_004_src1_channel),                          //   input,    width = 6,          .channel
		.sink3_data          (cmd_demux_004_src1_data),                             //   input,  width = 154,          .data
		.sink3_startofpacket (cmd_demux_004_src1_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (cmd_demux_004_src1_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_wh2scqi cmd_mux_005 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_005_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_005_src_data),                                //  output,  width = 154,          .data
		.src_channel         (cmd_mux_005_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_001_src4_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_001_src4_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_001_src4_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (cmd_demux_001_src4_data),                             //   input,  width = 154,          .data
		.sink0_startofpacket (cmd_demux_001_src4_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_001_src4_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_002_src4_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_002_src4_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_002_src4_channel),                          //   input,    width = 6,          .channel
		.sink1_data          (cmd_demux_002_src4_data),                             //   input,  width = 154,          .data
		.sink1_startofpacket (cmd_demux_002_src4_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_002_src4_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_mggywyq rsp_demux (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_005_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_005_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_005_src_data),                                 //   input,  width = 190,          .data
		.sink_startofpacket (router_005_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_005_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                 //  output,  width = 190,          .data
		.src0_channel       (rsp_demux_src0_channel),                              //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                          //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_src1_data),                                 //  output,  width = 190,          .data
		.src1_channel       (rsp_demux_src1_channel),                              //  output,    width = 6,          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                        //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                           //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_mggywyq rsp_demux_001 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_006_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_006_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_006_src_data),                                 //   input,  width = 190,          .data
		.sink_startofpacket (router_006_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_006_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                             //  output,  width = 190,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_001_src1_data),                             //  output,  width = 190,          .data
		.src1_channel       (rsp_demux_001_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_u3vc5wa rsp_demux_002 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_007_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_007_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_007_src_data),                                 //   input,  width = 154,          .data
		.sink_startofpacket (router_007_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_007_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                             //  output,  width = 154,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_002_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_002_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_002_src1_data),                             //  output,  width = 154,          .data
		.src1_channel       (rsp_demux_002_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (rsp_demux_002_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_002_src1_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src2_ready         (rsp_demux_002_src2_ready),                            //   input,    width = 1,      src2.ready
		.src2_valid         (rsp_demux_002_src2_valid),                            //  output,    width = 1,          .valid
		.src2_data          (rsp_demux_002_src2_data),                             //  output,  width = 154,          .data
		.src2_channel       (rsp_demux_002_src2_channel),                          //  output,    width = 6,          .channel
		.src2_startofpacket (rsp_demux_002_src2_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (rsp_demux_002_src2_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src3_ready         (rsp_demux_002_src3_ready),                            //   input,    width = 1,      src3.ready
		.src3_valid         (rsp_demux_002_src3_valid),                            //  output,    width = 1,          .valid
		.src3_data          (rsp_demux_002_src3_data),                             //  output,  width = 154,          .data
		.src3_channel       (rsp_demux_002_src3_channel),                          //  output,    width = 6,          .channel
		.src3_startofpacket (rsp_demux_002_src3_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (rsp_demux_002_src3_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_aaqhfoa rsp_demux_003 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_008_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_008_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_008_src_data),                                 //   input,  width = 154,          .data
		.sink_startofpacket (router_008_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_008_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                             //  output,  width = 154,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_003_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_003_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_003_src1_data),                             //  output,  width = 154,          .data
		.src1_channel       (rsp_demux_003_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (rsp_demux_003_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_003_src1_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_u3vc5wa rsp_demux_004 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_009_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_009_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_009_src_data),                                 //   input,  width = 154,          .data
		.sink_startofpacket (router_009_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_009_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_009_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_004_src0_data),                             //  output,  width = 154,          .data
		.src0_channel       (rsp_demux_004_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_004_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_004_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_004_src1_data),                             //  output,  width = 154,          .data
		.src1_channel       (rsp_demux_004_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (rsp_demux_004_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_004_src1_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src2_ready         (rsp_demux_004_src2_ready),                            //   input,    width = 1,      src2.ready
		.src2_valid         (rsp_demux_004_src2_valid),                            //  output,    width = 1,          .valid
		.src2_data          (rsp_demux_004_src2_data),                             //  output,  width = 154,          .data
		.src2_channel       (rsp_demux_004_src2_channel),                          //  output,    width = 6,          .channel
		.src2_startofpacket (rsp_demux_004_src2_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (rsp_demux_004_src2_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src3_ready         (rsp_demux_004_src3_ready),                            //   input,    width = 1,      src3.ready
		.src3_valid         (rsp_demux_004_src3_valid),                            //  output,    width = 1,          .valid
		.src3_data          (rsp_demux_004_src3_data),                             //  output,  width = 154,          .data
		.src3_channel       (rsp_demux_004_src3_channel),                          //  output,    width = 6,          .channel
		.src3_startofpacket (rsp_demux_004_src3_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (rsp_demux_004_src3_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_demultiplexer_1921_aaqhfoa rsp_demux_005 (
		.clk                (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset              (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_010_src_ready),                                //  output,    width = 1,      sink.ready
		.sink_channel       (router_010_src_channel),                              //   input,    width = 6,          .channel
		.sink_data          (router_010_src_data),                                 //   input,  width = 154,          .data
		.sink_startofpacket (router_010_src_startofpacket),                        //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_010_src_endofpacket),                          //   input,    width = 1,          .endofpacket
		.sink_valid         (router_010_src_valid),                                //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_005_src0_data),                             //  output,  width = 154,          .data
		.src0_channel       (rsp_demux_005_src0_channel),                          //  output,    width = 6,          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket),                      //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_005_src1_ready),                            //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_005_src1_valid),                            //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_005_src1_data),                             //  output,  width = 154,          .data
		.src1_channel       (rsp_demux_005_src1_channel),                          //  output,    width = 6,          .channel
		.src1_startofpacket (rsp_demux_005_src1_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_005_src1_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_w3oifoq rsp_mux (
		.clk                 (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                                            //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                                                            //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                                                             //  output,  width = 406,          .data
		.src_channel         (rsp_mux_src_channel),                                                                          //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                                                    //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                                                      //  output,    width = 1,          .endofpacket
		.sink0_ready         (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.sink0_valid         (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.sink0_channel       (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_channel),       //   input,    width = 6,          .channel
		.sink0_data          (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_data),          //   input,  width = 406,          .data
		.sink0_startofpacket (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink1_ready         (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_ready),         //  output,    width = 1,     sink1.ready
		.sink1_valid         (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.sink1_channel       (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_channel),       //   input,    width = 6,          .channel
		.sink1_data          (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_data),          //   input,  width = 406,          .data
		.sink1_startofpacket (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_endofpacket)    //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_kokbg6i rsp_mux_001 (
		.clk                 (iopll_outclk0_clk),                                                                  //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                                                              //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_001_src_valid),                                                              //  output,    width = 1,          .valid
		.src_data            (rsp_mux_001_src_data),                                                               //  output,  width = 154,          .data
		.src_channel         (rsp_mux_001_src_channel),                                                            //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                                                      //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                                                        //  output,    width = 1,          .endofpacket
		.sink0_ready         (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.sink0_valid         (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.sink0_channel       (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_channel),       //   input,    width = 6,          .channel
		.sink0_data          (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_data),          //   input,  width = 154,          .data
		.sink0_startofpacket (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_002_src0_ready),                                                           //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_002_src0_valid),                                                           //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_002_src0_channel),                                                         //   input,    width = 6,          .channel
		.sink1_data          (rsp_demux_002_src0_data),                                                            //   input,  width = 154,          .data
		.sink1_startofpacket (rsp_demux_002_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_002_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink2_ready         (rsp_demux_003_src0_ready),                                                           //  output,    width = 1,     sink2.ready
		.sink2_valid         (rsp_demux_003_src0_valid),                                                           //   input,    width = 1,          .valid
		.sink2_channel       (rsp_demux_003_src0_channel),                                                         //   input,    width = 6,          .channel
		.sink2_data          (rsp_demux_003_src0_data),                                                            //   input,  width = 154,          .data
		.sink2_startofpacket (rsp_demux_003_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (rsp_demux_003_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink3_ready         (rsp_demux_004_src0_ready),                                                           //  output,    width = 1,     sink3.ready
		.sink3_valid         (rsp_demux_004_src0_valid),                                                           //   input,    width = 1,          .valid
		.sink3_channel       (rsp_demux_004_src0_channel),                                                         //   input,    width = 6,          .channel
		.sink3_data          (rsp_demux_004_src0_data),                                                            //   input,  width = 154,          .data
		.sink3_startofpacket (rsp_demux_004_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (rsp_demux_004_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink4_ready         (rsp_demux_005_src0_ready),                                                           //  output,    width = 1,     sink4.ready
		.sink4_valid         (rsp_demux_005_src0_valid),                                                           //   input,    width = 1,          .valid
		.sink4_channel       (rsp_demux_005_src0_channel),                                                         //   input,    width = 6,          .channel
		.sink4_data          (rsp_demux_005_src0_data),                                                            //   input,  width = 154,          .data
		.sink4_startofpacket (rsp_demux_005_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink4_endofpacket   (rsp_demux_005_src0_endofpacket)                                                      //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_kokbg6i rsp_mux_002 (
		.clk                 (iopll_outclk0_clk),                                                                  //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                                                              //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_002_src_valid),                                                              //  output,    width = 1,          .valid
		.src_data            (rsp_mux_002_src_data),                                                               //  output,  width = 154,          .data
		.src_channel         (rsp_mux_002_src_channel),                                                            //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                                                      //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                                                        //  output,    width = 1,          .endofpacket
		.sink0_ready         (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.sink0_valid         (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.sink0_channel       (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_channel),       //   input,    width = 6,          .channel
		.sink0_data          (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_data),          //   input,  width = 154,          .data
		.sink0_startofpacket (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_002_src1_ready),                                                           //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_002_src1_valid),                                                           //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_002_src1_channel),                                                         //   input,    width = 6,          .channel
		.sink1_data          (rsp_demux_002_src1_data),                                                            //   input,  width = 154,          .data
		.sink1_startofpacket (rsp_demux_002_src1_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_002_src1_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink2_ready         (rsp_demux_003_src1_ready),                                                           //  output,    width = 1,     sink2.ready
		.sink2_valid         (rsp_demux_003_src1_valid),                                                           //   input,    width = 1,          .valid
		.sink2_channel       (rsp_demux_003_src1_channel),                                                         //   input,    width = 6,          .channel
		.sink2_data          (rsp_demux_003_src1_data),                                                            //   input,  width = 154,          .data
		.sink2_startofpacket (rsp_demux_003_src1_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (rsp_demux_003_src1_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink3_ready         (rsp_demux_004_src1_ready),                                                           //  output,    width = 1,     sink3.ready
		.sink3_valid         (rsp_demux_004_src1_valid),                                                           //   input,    width = 1,          .valid
		.sink3_channel       (rsp_demux_004_src1_channel),                                                         //   input,    width = 6,          .channel
		.sink3_data          (rsp_demux_004_src1_data),                                                            //   input,  width = 154,          .data
		.sink3_startofpacket (rsp_demux_004_src1_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (rsp_demux_004_src1_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink4_ready         (rsp_demux_005_src1_ready),                                                           //  output,    width = 1,     sink4.ready
		.sink4_valid         (rsp_demux_005_src1_valid),                                                           //   input,    width = 1,          .valid
		.sink4_channel       (rsp_demux_005_src1_channel),                                                         //   input,    width = 6,          .channel
		.sink4_data          (rsp_demux_005_src1_data),                                                            //   input,  width = 154,          .data
		.sink4_startofpacket (rsp_demux_005_src1_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink4_endofpacket   (rsp_demux_005_src1_endofpacket)                                                      //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_4c2zq4a rsp_mux_003 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_003_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_003_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (rsp_mux_003_src_data),                                //  output,  width = 154,          .data
		.src_channel         (rsp_mux_003_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_003_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_003_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_002_src2_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_002_src2_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_002_src2_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (rsp_demux_002_src2_data),                             //   input,  width = 154,          .data
		.sink0_startofpacket (rsp_demux_002_src2_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_002_src2_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_004_src2_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_004_src2_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_004_src2_channel),                          //   input,    width = 6,          .channel
		.sink1_data          (rsp_demux_004_src2_data),                             //   input,  width = 154,          .data
		.sink1_startofpacket (rsp_demux_004_src2_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_004_src2_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_multiplexer_1922_4c2zq4a rsp_mux_004 (
		.clk                 (iopll_outclk0_clk),                                   //   input,    width = 1,       clk.clk
		.reset               (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_004_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_004_src_valid),                               //  output,    width = 1,          .valid
		.src_data            (rsp_mux_004_src_data),                                //  output,  width = 154,          .data
		.src_channel         (rsp_mux_004_src_channel),                             //  output,    width = 6,          .channel
		.src_startofpacket   (rsp_mux_004_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_004_src_endofpacket),                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_002_src3_ready),                            //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_002_src3_valid),                            //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_002_src3_channel),                          //   input,    width = 6,          .channel
		.sink0_data          (rsp_demux_002_src3_data),                             //   input,  width = 154,          .data
		.sink0_startofpacket (rsp_demux_002_src3_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_002_src3_endofpacket),                      //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_004_src3_ready),                            //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_004_src3_valid),                            //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_004_src3_channel),                          //   input,    width = 6,          .channel
		.sink1_data          (rsp_demux_004_src3_data),                             //   input,  width = 154,          .data
		.sink1_startofpacket (rsp_demux_004_src3_startofpacket),                    //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_004_src3_endofpacket)                       //   input,    width = 1,          .endofpacket
	);

	nios_system_altera_merlin_width_adapter_1950_i55zexy #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (339),
		.IN_PKT_BYTE_CNT_L             (326),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_TRANS_WRITE            (322),
		.IN_PKT_BURSTWRAP_H            (347),
		.IN_PKT_BURSTWRAP_L            (340),
		.IN_PKT_BURST_SIZE_H           (350),
		.IN_PKT_BURST_SIZE_L           (348),
		.IN_PKT_RESPONSE_STATUS_H      (375),
		.IN_PKT_RESPONSE_STATUS_L      (374),
		.IN_PKT_TRANS_EXCLUSIVE        (325),
		.IN_PKT_BURST_TYPE_H           (352),
		.IN_PKT_BURST_TYPE_L           (351),
		.IN_PKT_ORI_BURST_SIZE_L       (376),
		.IN_PKT_ORI_BURST_SIZE_H       (378),
		.IN_PKT_POISON_H               (388),
		.IN_PKT_POISON_L               (388),
		.IN_PKT_DATACHK_H              (389),
		.IN_PKT_DATACHK_L              (389),
		.IN_PKT_ADDRCHK_H              (392),
		.IN_PKT_ADDRCHK_L              (391),
		.IN_PKT_SAI_H                  (393),
		.IN_PKT_SAI_L                  (393),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (390),
		.IN_PKT_USER_DATA_L            (390),
		.IN_ST_DATA_W                  (406),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (123),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (134),
		.OUT_PKT_BURST_SIZE_L          (132),
		.OUT_PKT_RESPONSE_STATUS_H     (159),
		.OUT_PKT_RESPONSE_STATUS_L     (158),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (136),
		.OUT_PKT_BURST_TYPE_L          (135),
		.OUT_PKT_ORI_BURST_SIZE_L      (160),
		.OUT_PKT_ORI_BURST_SIZE_H      (162),
		.OUT_PKT_POISON_H              (172),
		.OUT_PKT_POISON_L              (172),
		.OUT_PKT_DATACHK_H             (173),
		.OUT_PKT_DATACHK_L             (173),
		.OUT_PKT_ADDRCHK_H             (176),
		.OUT_PKT_ADDRCHK_L             (175),
		.OUT_PKT_SAI_H                 (177),
		.OUT_PKT_SAI_L                 (177),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (178),
		.OUT_PKT_SOP_OOO               (179),
		.OUT_PKT_USER_DATA_H           (174),
		.OUT_PKT_USER_DATA_L           (174),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (190),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_demux_src0_valid),                                                                         //   input,    width = 1,      sink.valid
		.in_channel           (cmd_demux_src0_channel),                                                                       //   input,    width = 6,          .channel
		.in_startofpacket     (cmd_demux_src0_startofpacket),                                                                 //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_demux_src0_endofpacket),                                                                   //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_demux_src0_ready),                                                                         //  output,    width = 1,          .ready
		.in_data              (cmd_demux_src0_data),                                                                          //   input,  width = 406,          .data
		.out_endofpacket      (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_data),          //  output,  width = 190,          .data
		.out_channel          (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                                        // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_i55zexy #(
		.IN_PKT_ADDR_H                 (319),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (339),
		.IN_PKT_BYTE_CNT_L             (326),
		.IN_PKT_TRANS_COMPRESSED_READ  (320),
		.IN_PKT_TRANS_WRITE            (322),
		.IN_PKT_BURSTWRAP_H            (347),
		.IN_PKT_BURSTWRAP_L            (340),
		.IN_PKT_BURST_SIZE_H           (350),
		.IN_PKT_BURST_SIZE_L           (348),
		.IN_PKT_RESPONSE_STATUS_H      (375),
		.IN_PKT_RESPONSE_STATUS_L      (374),
		.IN_PKT_TRANS_EXCLUSIVE        (325),
		.IN_PKT_BURST_TYPE_H           (352),
		.IN_PKT_BURST_TYPE_L           (351),
		.IN_PKT_ORI_BURST_SIZE_L       (376),
		.IN_PKT_ORI_BURST_SIZE_H       (378),
		.IN_PKT_POISON_H               (388),
		.IN_PKT_POISON_L               (388),
		.IN_PKT_DATACHK_H              (389),
		.IN_PKT_DATACHK_L              (389),
		.IN_PKT_ADDRCHK_H              (392),
		.IN_PKT_ADDRCHK_L              (391),
		.IN_PKT_SAI_H                  (393),
		.IN_PKT_SAI_L                  (393),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (390),
		.IN_PKT_USER_DATA_L            (390),
		.IN_ST_DATA_W                  (406),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (123),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (134),
		.OUT_PKT_BURST_SIZE_L          (132),
		.OUT_PKT_RESPONSE_STATUS_H     (159),
		.OUT_PKT_RESPONSE_STATUS_L     (158),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (136),
		.OUT_PKT_BURST_TYPE_L          (135),
		.OUT_PKT_ORI_BURST_SIZE_L      (160),
		.OUT_PKT_ORI_BURST_SIZE_H      (162),
		.OUT_PKT_POISON_H              (172),
		.OUT_PKT_POISON_L              (172),
		.OUT_PKT_DATACHK_H             (173),
		.OUT_PKT_DATACHK_L             (173),
		.OUT_PKT_ADDRCHK_H             (176),
		.OUT_PKT_ADDRCHK_L             (175),
		.OUT_PKT_SAI_H                 (177),
		.OUT_PKT_SAI_L                 (177),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (178),
		.OUT_PKT_SOP_OOO               (179),
		.OUT_PKT_USER_DATA_H           (174),
		.OUT_PKT_USER_DATA_L           (174),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (190),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_demux_src1_valid),                                                                         //   input,    width = 1,      sink.valid
		.in_channel           (cmd_demux_src1_channel),                                                                       //   input,    width = 6,          .channel
		.in_startofpacket     (cmd_demux_src1_startofpacket),                                                                 //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_demux_src1_endofpacket),                                                                   //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_demux_src1_ready),                                                                         //  output,    width = 1,          .ready
		.in_data              (cmd_demux_src1_data),                                                                          //   input,  width = 406,          .data
		.out_endofpacket      (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_data),          //  output,  width = 190,          .data
		.out_channel          (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (intel_vvp_vfr_av_mm_mem_read_host_to_sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                                        // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_y3w73oq #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (87),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (95),
		.IN_PKT_BURSTWRAP_L            (88),
		.IN_PKT_BURST_SIZE_H           (98),
		.IN_PKT_BURST_SIZE_L           (96),
		.IN_PKT_RESPONSE_STATUS_H      (123),
		.IN_PKT_RESPONSE_STATUS_L      (122),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (100),
		.IN_PKT_BURST_TYPE_L           (99),
		.IN_PKT_ORI_BURST_SIZE_L       (124),
		.IN_PKT_ORI_BURST_SIZE_H       (126),
		.IN_PKT_POISON_H               (136),
		.IN_PKT_POISON_L               (136),
		.IN_PKT_DATACHK_H              (137),
		.IN_PKT_DATACHK_L              (137),
		.IN_PKT_ADDRCHK_H              (140),
		.IN_PKT_ADDRCHK_L              (139),
		.IN_PKT_SAI_H                  (141),
		.IN_PKT_SAI_L                  (141),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (138),
		.IN_PKT_USER_DATA_L            (138),
		.IN_ST_DATA_W                  (154),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (123),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (134),
		.OUT_PKT_BURST_SIZE_L          (132),
		.OUT_PKT_RESPONSE_STATUS_H     (159),
		.OUT_PKT_RESPONSE_STATUS_L     (158),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (136),
		.OUT_PKT_BURST_TYPE_L          (135),
		.OUT_PKT_ORI_BURST_SIZE_L      (160),
		.OUT_PKT_ORI_BURST_SIZE_H      (162),
		.OUT_PKT_POISON_H              (172),
		.OUT_PKT_POISON_L              (172),
		.OUT_PKT_DATACHK_H             (173),
		.OUT_PKT_DATACHK_L             (173),
		.OUT_PKT_ADDRCHK_H             (176),
		.OUT_PKT_ADDRCHK_L             (175),
		.OUT_PKT_SAI_H                 (177),
		.OUT_PKT_SAI_L                 (177),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (178),
		.OUT_PKT_SOP_OOO               (179),
		.OUT_PKT_USER_DATA_H           (174),
		.OUT_PKT_USER_DATA_L           (174),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (190),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                  //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_demux_001_src0_valid),                                                           //   input,    width = 1,      sink.valid
		.in_channel           (cmd_demux_001_src0_channel),                                                         //   input,    width = 6,          .channel
		.in_startofpacket     (cmd_demux_001_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_demux_001_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_demux_001_src0_ready),                                                           //  output,    width = 1,          .ready
		.in_data              (cmd_demux_001_src0_data),                                                            //   input,  width = 154,          .data
		.out_endofpacket      (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_data),          //  output,  width = 190,          .data
		.out_channel          (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (niosv_g_data_manager_wr_to_sdram_axi4_slave_wr_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                              // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_y3w73oq #(
		.IN_PKT_ADDR_H                 (67),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (87),
		.IN_PKT_BYTE_CNT_L             (74),
		.IN_PKT_TRANS_COMPRESSED_READ  (68),
		.IN_PKT_TRANS_WRITE            (70),
		.IN_PKT_BURSTWRAP_H            (95),
		.IN_PKT_BURSTWRAP_L            (88),
		.IN_PKT_BURST_SIZE_H           (98),
		.IN_PKT_BURST_SIZE_L           (96),
		.IN_PKT_RESPONSE_STATUS_H      (123),
		.IN_PKT_RESPONSE_STATUS_L      (122),
		.IN_PKT_TRANS_EXCLUSIVE        (73),
		.IN_PKT_BURST_TYPE_H           (100),
		.IN_PKT_BURST_TYPE_L           (99),
		.IN_PKT_ORI_BURST_SIZE_L       (124),
		.IN_PKT_ORI_BURST_SIZE_H       (126),
		.IN_PKT_POISON_H               (136),
		.IN_PKT_POISON_L               (136),
		.IN_PKT_DATACHK_H              (137),
		.IN_PKT_DATACHK_L              (137),
		.IN_PKT_ADDRCHK_H              (140),
		.IN_PKT_ADDRCHK_L              (139),
		.IN_PKT_SAI_H                  (141),
		.IN_PKT_SAI_L                  (141),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (138),
		.IN_PKT_USER_DATA_L            (138),
		.IN_ST_DATA_W                  (154),
		.OUT_PKT_ADDR_H                (103),
		.OUT_PKT_ADDR_L                (72),
		.OUT_PKT_DATA_H                (63),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (71),
		.OUT_PKT_BYTEEN_L              (64),
		.OUT_PKT_BYTE_CNT_H            (123),
		.OUT_PKT_BYTE_CNT_L            (110),
		.OUT_PKT_TRANS_COMPRESSED_READ (104),
		.OUT_PKT_BURST_SIZE_H          (134),
		.OUT_PKT_BURST_SIZE_L          (132),
		.OUT_PKT_RESPONSE_STATUS_H     (159),
		.OUT_PKT_RESPONSE_STATUS_L     (158),
		.OUT_PKT_TRANS_EXCLUSIVE       (109),
		.OUT_PKT_BURST_TYPE_H          (136),
		.OUT_PKT_BURST_TYPE_L          (135),
		.OUT_PKT_ORI_BURST_SIZE_L      (160),
		.OUT_PKT_ORI_BURST_SIZE_H      (162),
		.OUT_PKT_POISON_H              (172),
		.OUT_PKT_POISON_L              (172),
		.OUT_PKT_DATACHK_H             (173),
		.OUT_PKT_DATACHK_L             (173),
		.OUT_PKT_ADDRCHK_H             (176),
		.OUT_PKT_ADDRCHK_L             (175),
		.OUT_PKT_SAI_H                 (177),
		.OUT_PKT_SAI_L                 (177),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (178),
		.OUT_PKT_SOP_OOO               (179),
		.OUT_PKT_USER_DATA_H           (174),
		.OUT_PKT_USER_DATA_L           (174),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (190),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                  //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_demux_002_src0_valid),                                                           //   input,    width = 1,      sink.valid
		.in_channel           (cmd_demux_002_src0_channel),                                                         //   input,    width = 6,          .channel
		.in_startofpacket     (cmd_demux_002_src0_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_demux_002_src0_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_demux_002_src0_ready),                                                           //  output,    width = 1,          .ready
		.in_data              (cmd_demux_002_src0_data),                                                            //   input,  width = 154,          .data
		.out_endofpacket      (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_data),          //  output,  width = 190,          .data
		.out_channel          (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (niosv_g_data_manager_rd_to_sdram_axi4_slave_rd_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                              // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_wiuwjva #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (123),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (131),
		.IN_PKT_BURSTWRAP_L            (124),
		.IN_PKT_BURST_SIZE_H           (134),
		.IN_PKT_BURST_SIZE_L           (132),
		.IN_PKT_RESPONSE_STATUS_H      (159),
		.IN_PKT_RESPONSE_STATUS_L      (158),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (136),
		.IN_PKT_BURST_TYPE_L           (135),
		.IN_PKT_ORI_BURST_SIZE_L       (160),
		.IN_PKT_ORI_BURST_SIZE_H       (162),
		.IN_PKT_POISON_H               (172),
		.IN_PKT_POISON_L               (172),
		.IN_PKT_DATACHK_H              (173),
		.IN_PKT_DATACHK_L              (173),
		.IN_PKT_ADDRCHK_H              (176),
		.IN_PKT_ADDRCHK_L              (175),
		.IN_PKT_SAI_H                  (177),
		.IN_PKT_SAI_L                  (177),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (174),
		.IN_PKT_USER_DATA_L            (174),
		.IN_ST_DATA_W                  (190),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (339),
		.OUT_PKT_BYTE_CNT_L            (326),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_PKT_BURST_SIZE_H          (350),
		.OUT_PKT_BURST_SIZE_L          (348),
		.OUT_PKT_RESPONSE_STATUS_H     (375),
		.OUT_PKT_RESPONSE_STATUS_L     (374),
		.OUT_PKT_TRANS_EXCLUSIVE       (325),
		.OUT_PKT_BURST_TYPE_H          (352),
		.OUT_PKT_BURST_TYPE_L          (351),
		.OUT_PKT_ORI_BURST_SIZE_L      (376),
		.OUT_PKT_ORI_BURST_SIZE_H      (378),
		.OUT_PKT_POISON_H              (388),
		.OUT_PKT_POISON_L              (388),
		.OUT_PKT_DATACHK_H             (389),
		.OUT_PKT_DATACHK_L             (389),
		.OUT_PKT_ADDRCHK_H             (392),
		.OUT_PKT_ADDRCHK_L             (391),
		.OUT_PKT_SAI_H                 (393),
		.OUT_PKT_SAI_L                 (393),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (394),
		.OUT_PKT_SOP_OOO               (395),
		.OUT_PKT_USER_DATA_H           (390),
		.OUT_PKT_USER_DATA_L           (390),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (406),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.in_valid             (rsp_demux_src0_valid),                                                                         //   input,    width = 1,      sink.valid
		.in_channel           (rsp_demux_src0_channel),                                                                       //   input,    width = 6,          .channel
		.in_startofpacket     (rsp_demux_src0_startofpacket),                                                                 //   input,    width = 1,          .startofpacket
		.in_endofpacket       (rsp_demux_src0_endofpacket),                                                                   //   input,    width = 1,          .endofpacket
		.in_ready             (rsp_demux_src0_ready),                                                                         //  output,    width = 1,          .ready
		.in_data              (rsp_demux_src0_data),                                                                          //   input,  width = 190,          .data
		.out_endofpacket      (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_data),          //  output,  width = 406,          .data
		.out_channel          (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_wr_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                                        // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_yuq5bny #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (123),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (131),
		.IN_PKT_BURSTWRAP_L            (124),
		.IN_PKT_BURST_SIZE_H           (134),
		.IN_PKT_BURST_SIZE_L           (132),
		.IN_PKT_RESPONSE_STATUS_H      (159),
		.IN_PKT_RESPONSE_STATUS_L      (158),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (136),
		.IN_PKT_BURST_TYPE_L           (135),
		.IN_PKT_ORI_BURST_SIZE_L       (160),
		.IN_PKT_ORI_BURST_SIZE_H       (162),
		.IN_PKT_POISON_H               (172),
		.IN_PKT_POISON_L               (172),
		.IN_PKT_DATACHK_H              (173),
		.IN_PKT_DATACHK_L              (173),
		.IN_PKT_ADDRCHK_H              (176),
		.IN_PKT_ADDRCHK_L              (175),
		.IN_PKT_SAI_H                  (177),
		.IN_PKT_SAI_L                  (177),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (174),
		.IN_PKT_USER_DATA_L            (174),
		.IN_ST_DATA_W                  (190),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (87),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (98),
		.OUT_PKT_BURST_SIZE_L          (96),
		.OUT_PKT_RESPONSE_STATUS_H     (123),
		.OUT_PKT_RESPONSE_STATUS_L     (122),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (100),
		.OUT_PKT_BURST_TYPE_L          (99),
		.OUT_PKT_ORI_BURST_SIZE_L      (124),
		.OUT_PKT_ORI_BURST_SIZE_H      (126),
		.OUT_PKT_POISON_H              (136),
		.OUT_PKT_POISON_L              (136),
		.OUT_PKT_DATACHK_H             (137),
		.OUT_PKT_DATACHK_L             (137),
		.OUT_PKT_ADDRCHK_H             (140),
		.OUT_PKT_ADDRCHK_L             (139),
		.OUT_PKT_SAI_H                 (141),
		.OUT_PKT_SAI_L                 (141),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (142),
		.OUT_PKT_SOP_OOO               (143),
		.OUT_PKT_USER_DATA_H           (138),
		.OUT_PKT_USER_DATA_L           (138),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (154),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                  //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.in_valid             (rsp_demux_src1_valid),                                                               //   input,    width = 1,      sink.valid
		.in_channel           (rsp_demux_src1_channel),                                                             //   input,    width = 6,          .channel
		.in_startofpacket     (rsp_demux_src1_startofpacket),                                                       //   input,    width = 1,          .startofpacket
		.in_endofpacket       (rsp_demux_src1_endofpacket),                                                         //   input,    width = 1,          .endofpacket
		.in_ready             (rsp_demux_src1_ready),                                                               //  output,    width = 1,          .ready
		.in_data              (rsp_demux_src1_data),                                                                //   input,  width = 190,          .data
		.out_endofpacket      (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_data),          //  output,  width = 154,          .data
		.out_channel          (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_wr_to_niosv_g_data_manager_wr_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                              // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_wiuwjva #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (123),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (131),
		.IN_PKT_BURSTWRAP_L            (124),
		.IN_PKT_BURST_SIZE_H           (134),
		.IN_PKT_BURST_SIZE_L           (132),
		.IN_PKT_RESPONSE_STATUS_H      (159),
		.IN_PKT_RESPONSE_STATUS_L      (158),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (136),
		.IN_PKT_BURST_TYPE_L           (135),
		.IN_PKT_ORI_BURST_SIZE_L       (160),
		.IN_PKT_ORI_BURST_SIZE_H       (162),
		.IN_PKT_POISON_H               (172),
		.IN_PKT_POISON_L               (172),
		.IN_PKT_DATACHK_H              (173),
		.IN_PKT_DATACHK_L              (173),
		.IN_PKT_ADDRCHK_H              (176),
		.IN_PKT_ADDRCHK_L              (175),
		.IN_PKT_SAI_H                  (177),
		.IN_PKT_SAI_L                  (177),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (174),
		.IN_PKT_USER_DATA_L            (174),
		.IN_ST_DATA_W                  (190),
		.OUT_PKT_ADDR_H                (319),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (339),
		.OUT_PKT_BYTE_CNT_L            (326),
		.OUT_PKT_TRANS_COMPRESSED_READ (320),
		.OUT_PKT_BURST_SIZE_H          (350),
		.OUT_PKT_BURST_SIZE_L          (348),
		.OUT_PKT_RESPONSE_STATUS_H     (375),
		.OUT_PKT_RESPONSE_STATUS_L     (374),
		.OUT_PKT_TRANS_EXCLUSIVE       (325),
		.OUT_PKT_BURST_TYPE_H          (352),
		.OUT_PKT_BURST_TYPE_L          (351),
		.OUT_PKT_ORI_BURST_SIZE_L      (376),
		.OUT_PKT_ORI_BURST_SIZE_H      (378),
		.OUT_PKT_POISON_H              (388),
		.OUT_PKT_POISON_L              (388),
		.OUT_PKT_DATACHK_H             (389),
		.OUT_PKT_DATACHK_L             (389),
		.OUT_PKT_ADDRCHK_H             (392),
		.OUT_PKT_ADDRCHK_L             (391),
		.OUT_PKT_SAI_H                 (393),
		.OUT_PKT_SAI_L                 (393),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (394),
		.OUT_PKT_SOP_OOO               (395),
		.OUT_PKT_USER_DATA_H           (390),
		.OUT_PKT_USER_DATA_L           (390),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (406),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                            //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                          //   input,    width = 1, clk_reset.reset
		.in_valid             (rsp_demux_001_src0_valid),                                                                     //   input,    width = 1,      sink.valid
		.in_channel           (rsp_demux_001_src0_channel),                                                                   //   input,    width = 6,          .channel
		.in_startofpacket     (rsp_demux_001_src0_startofpacket),                                                             //   input,    width = 1,          .startofpacket
		.in_endofpacket       (rsp_demux_001_src0_endofpacket),                                                               //   input,    width = 1,          .endofpacket
		.in_ready             (rsp_demux_001_src0_ready),                                                                     //  output,    width = 1,          .ready
		.in_data              (rsp_demux_001_src0_data),                                                                      //   input,  width = 190,          .data
		.out_endofpacket      (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_data),          //  output,  width = 406,          .data
		.out_channel          (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_rd_to_intel_vvp_vfr_av_mm_mem_read_host_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                                        // (terminated),                         
	);

	nios_system_altera_merlin_width_adapter_1950_yuq5bny #(
		.IN_PKT_ADDR_H                 (103),
		.IN_PKT_ADDR_L                 (72),
		.IN_PKT_DATA_H                 (63),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (71),
		.IN_PKT_BYTEEN_L               (64),
		.IN_PKT_BYTE_CNT_H             (123),
		.IN_PKT_BYTE_CNT_L             (110),
		.IN_PKT_TRANS_COMPRESSED_READ  (104),
		.IN_PKT_TRANS_WRITE            (106),
		.IN_PKT_BURSTWRAP_H            (131),
		.IN_PKT_BURSTWRAP_L            (124),
		.IN_PKT_BURST_SIZE_H           (134),
		.IN_PKT_BURST_SIZE_L           (132),
		.IN_PKT_RESPONSE_STATUS_H      (159),
		.IN_PKT_RESPONSE_STATUS_L      (158),
		.IN_PKT_TRANS_EXCLUSIVE        (109),
		.IN_PKT_BURST_TYPE_H           (136),
		.IN_PKT_BURST_TYPE_L           (135),
		.IN_PKT_ORI_BURST_SIZE_L       (160),
		.IN_PKT_ORI_BURST_SIZE_H       (162),
		.IN_PKT_POISON_H               (172),
		.IN_PKT_POISON_L               (172),
		.IN_PKT_DATACHK_H              (173),
		.IN_PKT_DATACHK_L              (173),
		.IN_PKT_ADDRCHK_H              (176),
		.IN_PKT_ADDRCHK_L              (175),
		.IN_PKT_SAI_H                  (177),
		.IN_PKT_SAI_L                  (177),
		.IN_PKT_AWAKEUP                (137),
		.IN_PKT_ATRACE                 (138),
		.IN_PKT_TRACE                  (139),
		.IN_PKT_USER_DATA_H            (174),
		.IN_PKT_USER_DATA_L            (174),
		.IN_ST_DATA_W                  (190),
		.OUT_PKT_ADDR_H                (67),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (87),
		.OUT_PKT_BYTE_CNT_L            (74),
		.OUT_PKT_TRANS_COMPRESSED_READ (68),
		.OUT_PKT_BURST_SIZE_H          (98),
		.OUT_PKT_BURST_SIZE_L          (96),
		.OUT_PKT_RESPONSE_STATUS_H     (123),
		.OUT_PKT_RESPONSE_STATUS_L     (122),
		.OUT_PKT_TRANS_EXCLUSIVE       (73),
		.OUT_PKT_BURST_TYPE_H          (100),
		.OUT_PKT_BURST_TYPE_L          (99),
		.OUT_PKT_ORI_BURST_SIZE_L      (124),
		.OUT_PKT_ORI_BURST_SIZE_H      (126),
		.OUT_PKT_POISON_H              (136),
		.OUT_PKT_POISON_L              (136),
		.OUT_PKT_DATACHK_H             (137),
		.OUT_PKT_DATACHK_L             (137),
		.OUT_PKT_ADDRCHK_H             (140),
		.OUT_PKT_ADDRCHK_L             (139),
		.OUT_PKT_SAI_H                 (141),
		.OUT_PKT_SAI_L                 (141),
		.OUT_PKT_AWAKEUP               (137),
		.OUT_PKT_ATRACE                (138),
		.OUT_PKT_TRACE                 (139),
		.OUT_PKT_EOP_OOO               (142),
		.OUT_PKT_SOP_OOO               (143),
		.OUT_PKT_USER_DATA_H           (138),
		.OUT_PKT_USER_DATA_L           (138),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (154),
		.ST_CHANNEL_W                  (6),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.ENABLE_AXI5                   (0),
		.SYNC_RESET                    (1)
	) sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter (
		.clk                  (iopll_outclk0_clk),                                                                  //   input,    width = 1,       clk.clk
		.reset                (intel_vvp_vfr_mem_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.in_valid             (rsp_demux_001_src1_valid),                                                           //   input,    width = 1,      sink.valid
		.in_channel           (rsp_demux_001_src1_channel),                                                         //   input,    width = 6,          .channel
		.in_startofpacket     (rsp_demux_001_src1_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.in_endofpacket       (rsp_demux_001_src1_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.in_ready             (rsp_demux_001_src1_ready),                                                           //  output,    width = 1,          .ready
		.in_data              (rsp_demux_001_src1_data),                                                            //   input,  width = 190,          .data
		.out_endofpacket      (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_data),          //  output,  width = 154,          .data
		.out_channel          (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_channel),       //  output,    width = 6,          .channel
		.out_valid            (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (sdram_axi4_slave_rd_to_niosv_g_data_manager_rd_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                              // (terminated),                         
	);

endmodule
