module nios_system_intel_vvp_fr2cv_0 (
		output wire        cv_clk_out_clk,           //      cv_clk_out.clk
		output wire [23:0] cv_vid_out_vid_data,      //      cv_vid_out.vid_data
		output wire        cv_vid_out_underflow,     //                .underflow
		output wire        cv_vid_out_vid_datavalid, //                .vid_datavalid
		output wire        cv_vid_out_vid_v_sync,    //                .vid_v_sync
		output wire        cv_vid_out_vid_h_sync,    //                .vid_h_sync
		output wire        cv_vid_out_vid_f,         //                .vid_f
		output wire        cv_vid_out_vid_h,         //                .vid_h
		output wire        cv_vid_out_vid_v,         //                .vid_v
		input  wire [31:0] axi4s_fr_vid_in_tdata,    // axi4s_fr_vid_in.tdata
		input  wire        axi4s_fr_vid_in_tvalid,   //                .tvalid
		output wire        axi4s_fr_vid_in_tready,   //                .tready
		input  wire        axi4s_fr_vid_in_tlast,    //                .tlast
		input  wire [3:0]  axi4s_fr_vid_in_tuser,    //                .tuser
		input  wire        vid_clock_clk,            //       vid_clock.clk,          Clock Input
		input  wire        vid_reset_reset           //       vid_reset.reset
	);
endmodule

