/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'niosv_g' in SOPC Builder design 'nios_system'
 *
 * Generated: Wed Jul 16 23:44:33 CST 2025
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "intel_niosv_g"
#define ALT_CPU_CLIC_EN 0
#define ALT_CPU_CPU_FREQ 80000000u
#define ALT_CPU_DATA_ADDR_WIDTH 0x20
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 4096
#define ALT_CPU_FREQ 80000000
#define ALT_CPU_HAS_CSR_SUPPORT 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INST_ADDR_WIDTH 0x20
#define ALT_CPU_INT_MODE 0
#define ALT_CPU_MTIME_OFFSET 0x00011000
#define ALT_CPU_NAME "niosv_g"
#define ALT_CPU_NIOSV_CORE_VARIANT 3
#define ALT_CPU_NUM_GPR 32
#define ALT_CPU_NUM_SRF_BANKS 1
#define ALT_CPU_RESET_ADDR 0x00100000
#define ALT_CPU_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND
#define ALT_CPU_TIMER_DEVICE_TYPE 2


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define BANTAMLAKE_CLIC_EN 0
#define BANTAMLAKE_CPU_FREQ 80000000u
#define BANTAMLAKE_DATA_ADDR_WIDTH 0x20
#define BANTAMLAKE_DCACHE_LINE_SIZE 32
#define BANTAMLAKE_DCACHE_LINE_SIZE_LOG2 5
#define BANTAMLAKE_DCACHE_SIZE 4096
#define BANTAMLAKE_HAS_CSR_SUPPORT 1
#define BANTAMLAKE_HAS_DEBUG_STUB
#define BANTAMLAKE_ICACHE_LINE_SIZE 32
#define BANTAMLAKE_ICACHE_LINE_SIZE_LOG2 5
#define BANTAMLAKE_ICACHE_SIZE 4096
#define BANTAMLAKE_INST_ADDR_WIDTH 0x20
#define BANTAMLAKE_INT_MODE 0
#define BANTAMLAKE_MTIME_OFFSET 0x00011000
#define BANTAMLAKE_NIOSV_CORE_VARIANT 3
#define BANTAMLAKE_NUM_GPR 32
#define BANTAMLAKE_NUM_SRF_BANKS 1
#define BANTAMLAKE_RESET_ADDR 0x00100000
#define BANTAMLAKE_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND
#define BANTAMLAKE_TIMER_DEVICE_TYPE 2


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS
#define __CORE_SDRAM_AXI4
#define __INTEL_NIOSV_G
#define __INTEL_ONCHIP_MEMORY
#define __INTEL_VVP_VFR
#define __TERASIC_SDIO


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "AGILEX3"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x80448
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x80448
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x80448
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSID_BASE SYSID_QSYS_BASE
#define ALT_SYSID_ID SYSID_QSYS_ID
#define ALT_SYSTEM_NAME "nios_system"
#define ALT_SYS_CLK_TICKS_PER_SEC ALT_CPU_TICKS_PER_SEC
#define ALT_TIMESTAMP_CLK_TIMER_DEVICE_TYPE ALT_CPU_TIMER_DEVICE_TYPE


/*
 * hal2 configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK NIOSV_G
#define ALT_TIMESTAMP_CLK NIOSV_G
#define INTEL_FPGA_DFL_START_ADDRESS 0xffffffffffffffff
#define INTEL_FPGA_USE_DFL_WALKER 0


/*
 * intel_niosv_g_hal_driver configuration
 *
 */

#define NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND 1000


/*
 * intel_vvp_vfr configuration
 *
 */

#define ALT_MODULE_CLASS_intel_vvp_vfr intel_vvp_vfr
#define INTEL_VVP_VFR_BASE 0x80000
#define INTEL_VVP_VFR_IRQ -1
#define INTEL_VVP_VFR_IRQ_INTERRUPT_CONTROLLER_ID -1
#define INTEL_VVP_VFR_NAME "/dev/intel_vvp_vfr"
#define INTEL_VVP_VFR_SPAN 1024
#define INTEL_VVP_VFR_TYPE "intel_vvp_vfr"


/*
 * jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x80448
#define JTAG_UART_IRQ 0
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_SPAN 8
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8


/*
 * niosv_g_dm_agent configuration
 *
 */

#define ALT_MODULE_CLASS_niosv_g_dm_agent intel_niosv_g
#define NIOSV_G_DM_AGENT_BASE 0x0
#define NIOSV_G_DM_AGENT_CLIC_EN 0
#define NIOSV_G_DM_AGENT_CPU_FREQ 80000000u
#define NIOSV_G_DM_AGENT_DATA_ADDR_WIDTH 0x20
#define NIOSV_G_DM_AGENT_DCACHE_LINE_SIZE 32
#define NIOSV_G_DM_AGENT_DCACHE_LINE_SIZE_LOG2 5
#define NIOSV_G_DM_AGENT_DCACHE_SIZE 4096
#define NIOSV_G_DM_AGENT_HAS_CSR_SUPPORT 1
#define NIOSV_G_DM_AGENT_HAS_DEBUG_STUB
#define NIOSV_G_DM_AGENT_ICACHE_LINE_SIZE 32
#define NIOSV_G_DM_AGENT_ICACHE_LINE_SIZE_LOG2 5
#define NIOSV_G_DM_AGENT_ICACHE_SIZE 4096
#define NIOSV_G_DM_AGENT_INST_ADDR_WIDTH 0x20
#define NIOSV_G_DM_AGENT_INT_MODE 0
#define NIOSV_G_DM_AGENT_IRQ -1
#define NIOSV_G_DM_AGENT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOSV_G_DM_AGENT_MTIME_OFFSET 0x00011000
#define NIOSV_G_DM_AGENT_NAME "/dev/niosv_g_dm_agent"
#define NIOSV_G_DM_AGENT_NIOSV_CORE_VARIANT 3
#define NIOSV_G_DM_AGENT_NUM_GPR 32
#define NIOSV_G_DM_AGENT_NUM_SRF_BANKS 1
#define NIOSV_G_DM_AGENT_RESET_ADDR 0x00100000
#define NIOSV_G_DM_AGENT_SPAN 65536
#define NIOSV_G_DM_AGENT_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND
#define NIOSV_G_DM_AGENT_TIMER_DEVICE_TYPE 2
#define NIOSV_G_DM_AGENT_TYPE "intel_niosv_g"


/*
 * niosv_g_timer_sw_agent configuration
 *
 */

#define ALT_MODULE_CLASS_niosv_g_timer_sw_agent intel_niosv_g
#define NIOSV_G_TIMER_SW_AGENT_BASE 0x11000
#define NIOSV_G_TIMER_SW_AGENT_CLIC_EN 0
#define NIOSV_G_TIMER_SW_AGENT_CPU_FREQ 80000000u
#define NIOSV_G_TIMER_SW_AGENT_DATA_ADDR_WIDTH 0x20
#define NIOSV_G_TIMER_SW_AGENT_DCACHE_LINE_SIZE 32
#define NIOSV_G_TIMER_SW_AGENT_DCACHE_LINE_SIZE_LOG2 5
#define NIOSV_G_TIMER_SW_AGENT_DCACHE_SIZE 4096
#define NIOSV_G_TIMER_SW_AGENT_HAS_CSR_SUPPORT 1
#define NIOSV_G_TIMER_SW_AGENT_HAS_DEBUG_STUB
#define NIOSV_G_TIMER_SW_AGENT_ICACHE_LINE_SIZE 32
#define NIOSV_G_TIMER_SW_AGENT_ICACHE_LINE_SIZE_LOG2 5
#define NIOSV_G_TIMER_SW_AGENT_ICACHE_SIZE 4096
#define NIOSV_G_TIMER_SW_AGENT_INST_ADDR_WIDTH 0x20
#define NIOSV_G_TIMER_SW_AGENT_INT_MODE 0
#define NIOSV_G_TIMER_SW_AGENT_IRQ -1
#define NIOSV_G_TIMER_SW_AGENT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define NIOSV_G_TIMER_SW_AGENT_MTIME_OFFSET 0x00011000
#define NIOSV_G_TIMER_SW_AGENT_NAME "/dev/niosv_g_timer_sw_agent"
#define NIOSV_G_TIMER_SW_AGENT_NIOSV_CORE_VARIANT 3
#define NIOSV_G_TIMER_SW_AGENT_NUM_GPR 32
#define NIOSV_G_TIMER_SW_AGENT_NUM_SRF_BANKS 1
#define NIOSV_G_TIMER_SW_AGENT_RESET_ADDR 0x00100000
#define NIOSV_G_TIMER_SW_AGENT_SPAN 64
#define NIOSV_G_TIMER_SW_AGENT_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND
#define NIOSV_G_TIMER_SW_AGENT_TIMER_DEVICE_TYPE 2
#define NIOSV_G_TIMER_SW_AGENT_TYPE "intel_niosv_g"


/*
 * onchip_memory configuration
 *
 */

#define ALT_MODULE_CLASS_onchip_memory intel_onchip_memory
#define ONCHIP_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY_BASE 0x100000
#define ONCHIP_MEMORY_CONTENTS_INFO ""
#define ONCHIP_MEMORY_DUAL_PORT 0
#define ONCHIP_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEMORY_INIT_CONTENTS_FILE "ram"
#define ONCHIP_MEMORY_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY_INSTANCE_ID "NONE"
#define ONCHIP_MEMORY_IRQ -1
#define ONCHIP_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1
#define ONCHIP_MEMORY_NAME "/dev/onchip_memory"
#define ONCHIP_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 1
#define ONCHIP_MEMORY_RAM_BLOCK_TYPE "AUTO"
#define ONCHIP_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
#define ONCHIP_MEMORY_SINGLE_CLOCK_OP 0
#define ONCHIP_MEMORY_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY_SIZE_VALUE 524280
#define ONCHIP_MEMORY_SPAN 524280
#define ONCHIP_MEMORY_TYPE "intel_onchip_memory"
#define ONCHIP_MEMORY_WRITABLE 1


/*
 * pio_fsync_out configuration
 *
 */

#define ALT_MODULE_CLASS_pio_fsync_out altera_avalon_pio
#define PIO_FSYNC_OUT_BASE 0x80400
#define PIO_FSYNC_OUT_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_FSYNC_OUT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_FSYNC_OUT_CAPTURE 0
#define PIO_FSYNC_OUT_DATA_WIDTH 1
#define PIO_FSYNC_OUT_DO_TEST_BENCH_WIRING 0
#define PIO_FSYNC_OUT_DRIVEN_SIM_VALUE 0
#define PIO_FSYNC_OUT_EDGE_TYPE "NONE"
#define PIO_FSYNC_OUT_FREQ 80000000
#define PIO_FSYNC_OUT_HAS_IN 0
#define PIO_FSYNC_OUT_HAS_OUT 1
#define PIO_FSYNC_OUT_HAS_TRI 0
#define PIO_FSYNC_OUT_IRQ -1
#define PIO_FSYNC_OUT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_FSYNC_OUT_IRQ_TYPE "NONE"
#define PIO_FSYNC_OUT_NAME "/dev/pio_fsync_out"
#define PIO_FSYNC_OUT_RESET_VALUE 0
#define PIO_FSYNC_OUT_SPAN 16
#define PIO_FSYNC_OUT_TYPE "altera_avalon_pio"


/*
 * pio_key configuration
 *
 */

#define ALT_MODULE_CLASS_pio_key altera_avalon_pio
#define PIO_KEY_BASE 0x80410
#define PIO_KEY_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_KEY_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_KEY_CAPTURE 1
#define PIO_KEY_DATA_WIDTH 2
#define PIO_KEY_DO_TEST_BENCH_WIRING 0
#define PIO_KEY_DRIVEN_SIM_VALUE 4
#define PIO_KEY_EDGE_TYPE "FALLING"
#define PIO_KEY_FREQ 80000000
#define PIO_KEY_HAS_IN 1
#define PIO_KEY_HAS_OUT 0
#define PIO_KEY_HAS_TRI 0
#define PIO_KEY_IRQ 1
#define PIO_KEY_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PIO_KEY_IRQ_TYPE "EDGE"
#define PIO_KEY_NAME "/dev/pio_key"
#define PIO_KEY_RESET_VALUE 0
#define PIO_KEY_SPAN 16
#define PIO_KEY_TYPE "altera_avalon_pio"


/*
 * pio_led configuration
 *
 */

#define ALT_MODULE_CLASS_pio_led altera_avalon_pio
#define PIO_LED_BASE 0x80420
#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_LED_CAPTURE 0
#define PIO_LED_DATA_WIDTH 4
#define PIO_LED_DO_TEST_BENCH_WIRING 0
#define PIO_LED_DRIVEN_SIM_VALUE 0
#define PIO_LED_EDGE_TYPE "NONE"
#define PIO_LED_FREQ 80000000
#define PIO_LED_HAS_IN 0
#define PIO_LED_HAS_OUT 1
#define PIO_LED_HAS_TRI 0
#define PIO_LED_IRQ -1
#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define PIO_LED_IRQ_TYPE "NONE"
#define PIO_LED_NAME "/dev/pio_led"
#define PIO_LED_RESET_VALUE 0
#define PIO_LED_SPAN 16
#define PIO_LED_TYPE "altera_avalon_pio"


/*
 * pio_sw configuration
 *
 */

#define ALT_MODULE_CLASS_pio_sw altera_avalon_pio
#define PIO_SW_BASE 0x80430
#define PIO_SW_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_SW_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_SW_CAPTURE 1
#define PIO_SW_DATA_WIDTH 2
#define PIO_SW_DO_TEST_BENCH_WIRING 1
#define PIO_SW_DRIVEN_SIM_VALUE 0
#define PIO_SW_EDGE_TYPE "ANY"
#define PIO_SW_FREQ 80000000
#define PIO_SW_HAS_IN 1
#define PIO_SW_HAS_OUT 0
#define PIO_SW_HAS_TRI 0
#define PIO_SW_IRQ 2
#define PIO_SW_IRQ_INTERRUPT_CONTROLLER_ID 0
#define PIO_SW_IRQ_TYPE "EDGE"
#define PIO_SW_NAME "/dev/pio_sw"
#define PIO_SW_RESET_VALUE 0
#define PIO_SW_SPAN 16
#define PIO_SW_TYPE "altera_avalon_pio"


/*
 * sdram configuration
 *
 */

#define ALT_MODULE_CLASS_sdram core_sdram_axi4
#define SDRAM_BASE 0x4000000
#define SDRAM_IRQ -1
#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_NAME "/dev/sdram"
#define SDRAM_SPAN 67108864
#define SDRAM_TYPE "core_sdram_axi4"


/*
 * sysid_qsys configuration
 *
 */

#define ALT_MODULE_CLASS_sysid_qsys altera_avalon_sysid_qsys
#define SYSID_QSYS_BASE 0x80440
#define SYSID_QSYS_ID 0
#define SYSID_QSYS_IRQ -1
#define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_QSYS_NAME "/dev/sysid_qsys"
#define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_TIMESTAMP 0
#define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys"


/*
 * terasic_sdcard configuration
 *
 */

#define ALT_MODULE_CLASS_terasic_sdcard terasic_sdio
#define TERASIC_SDCARD_BASE 0x90000
#define TERASIC_SDCARD_IRQ -1
#define TERASIC_SDCARD_IRQ_INTERRUPT_CONTROLLER_ID -1
#define TERASIC_SDCARD_NAME "/dev/terasic_sdcard"
#define TERASIC_SDCARD_SPAN 4096
#define TERASIC_SDCARD_TYPE "terasic_sdio"

#endif /* __SYSTEM_H_ */
