// nios_system_intel_vvp_fr2cv_0.v

// Generated using ACDS version 25.1 129

`timescale 1 ps / 1 ps
module nios_system_intel_vvp_fr2cv_0 (
		output wire        cv_clk_out_clk,           //      cv_clk_out.clk
		output wire [23:0] cv_vid_out_vid_data,      //      cv_vid_out.vid_data
		output wire        cv_vid_out_underflow,     //                .underflow
		output wire        cv_vid_out_vid_datavalid, //                .vid_datavalid
		output wire        cv_vid_out_vid_v_sync,    //                .vid_v_sync
		output wire        cv_vid_out_vid_h_sync,    //                .vid_h_sync
		output wire        cv_vid_out_vid_f,         //                .vid_f
		output wire        cv_vid_out_vid_h,         //                .vid_h
		output wire        cv_vid_out_vid_v,         //                .vid_v
		input  wire [31:0] axi4s_fr_vid_in_tdata,    // axi4s_fr_vid_in.tdata
		input  wire        axi4s_fr_vid_in_tvalid,   //                .tvalid
		output wire        axi4s_fr_vid_in_tready,   //                .tready
		input  wire        axi4s_fr_vid_in_tlast,    //                .tlast
		input  wire [3:0]  axi4s_fr_vid_in_tuser,    //                .tuser
		input  wire        vid_clock_clk,            //       vid_clock.clk,          Clock Input
		input  wire        vid_reset_reset           //       vid_reset.reset
	);

	nios_system_intel_vvp_fr2cv_0_intel_vvp_fr2cv_2430_a633opy #(
		.DEVICE_FAMILY          ("Agilex 3"),
		.RUNTIME_CONTROL        (0),
		.SEPARATE_SLAVE_CLOCK   (0),
		.BPS                    (8),
		.NUMBER_OF_COLOR_PLANES (3),
		.PIXELS_IN_PARALLEL     (1),
		.CV_STYLE               ("CVO")
	) intel_vvp_fr2cv_0 (
		.cv_clk_out_clk           (cv_clk_out_clk),           //  output,   width = 1,      cv_clk_out.clk
		.cv_vid_out_vid_data      (cv_vid_out_vid_data),      //  output,  width = 24,      cv_vid_out.vid_data
		.cv_vid_out_underflow     (cv_vid_out_underflow),     //  output,   width = 1,                .underflow
		.cv_vid_out_vid_datavalid (cv_vid_out_vid_datavalid), //  output,   width = 1,                .vid_datavalid
		.cv_vid_out_vid_v_sync    (cv_vid_out_vid_v_sync),    //  output,   width = 1,                .vid_v_sync
		.cv_vid_out_vid_h_sync    (cv_vid_out_vid_h_sync),    //  output,   width = 1,                .vid_h_sync
		.cv_vid_out_vid_f         (cv_vid_out_vid_f),         //  output,   width = 1,                .vid_f
		.cv_vid_out_vid_h         (cv_vid_out_vid_h),         //  output,   width = 1,                .vid_h
		.cv_vid_out_vid_v         (cv_vid_out_vid_v),         //  output,   width = 1,                .vid_v
		.axi4s_fr_vid_in_tdata    (axi4s_fr_vid_in_tdata),    //   input,  width = 32, axi4s_fr_vid_in.tdata
		.axi4s_fr_vid_in_tvalid   (axi4s_fr_vid_in_tvalid),   //   input,   width = 1,                .tvalid
		.axi4s_fr_vid_in_tready   (axi4s_fr_vid_in_tready),   //  output,   width = 1,                .tready
		.axi4s_fr_vid_in_tlast    (axi4s_fr_vid_in_tlast),    //   input,   width = 1,                .tlast
		.axi4s_fr_vid_in_tuser    (axi4s_fr_vid_in_tuser),    //   input,   width = 4,                .tuser
		.vid_clock_clk            (vid_clock_clk),            //   input,   width = 1,       vid_clock.clk
		.vid_reset_reset          (vid_reset_reset)           //   input,   width = 1,       vid_reset.reset
	);

endmodule
