ed_sim

2024.11.28.09:42:39 Datasheet
Overview

Memory Map
axil_driver_0 traffic_generator
 axil_driver_axi4_lite  driver0_axi4
  emif_io96b_ddr4comp_1
s0_axi4  0x0000_0000 - 0xffff_ffff
s0_axi4lite  0x0000_0000 - 0x07ff_ffff

async_clk_source

altera_avalon_clock_source v19.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

axil_driver_0

emif_ph2_axil_driver v1.0.0
user_pll outclk1   axil_driver_0
  axil_driver_clk
reset_handler reset_n_out  
  axil_driver_rst_n
axil_driver_axi4_lite   emif_io96b_ddr4comp_1
  s0_axi4lite
cal_done_rst_n   traffic_generator
  driver0_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_io96b_ddr4comp_1

emif_io96b_ddr4comp v1.0.0
axil_driver_0 axil_driver_axi4_lite   emif_io96b_ddr4comp_1
  s0_axi4lite
traffic_generator driver0_axi4  
  s0_axi4
ref_clk_source_0 clk  
  ref_clk
user_pll outclk0  
  s0_axi4_clock_in
outclk1  
  s0_axi4lite_clock
mem mem_0  
  mem_0
mem_ck_0  
  mem_ck_0
mem_reset_n  
  mem_reset_n
oct_0  
  oct_0
reset_handler reset_n_out  
  core_init_n
reset_n_out  
  s0_axi4lite_reset_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

mem

emif_io96b_mem_model_ddr4 v1.0.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

ref_clk_source_0

altera_avalon_clock_source v19.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_handler

mem_reset_handler v1.0.0
user_pll outclk0   reset_handler
  clk
locked  
  conduit_0
rrip ninit_done  
  reset_n_0
reset_n_out   axil_driver_0
  axil_driver_rst_n
reset_n_out   emif_io96b_ddr4comp_1
  core_init_n
reset_n_out  
  s0_axi4lite_reset_n
reset_n_out   traffic_generator
  remote_intf_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

rrip

altera_s10_user_rst_clkgate v19.4.7


Parameters

generateLegacySim false
  

Software Assignments

(none)

traffic_generator

hydra v1.2.0
user_pll outclk0   traffic_generator
  driver0_clk
outclk1  
  remote_intf_clk
axil_driver_0 cal_done_rst_n  
  driver0_reset
reset_handler reset_n_out  
  remote_intf_reset
driver0_axi4   emif_io96b_ddr4comp_1
  s0_axi4


Parameters

generateLegacySim false
  

Software Assignments

(none)

user_pll

altera_iopll v20.0.0
async_clk_source clk   user_pll
  refclk
rrip ninit_done  
  reset
outclk0   reset_handler
  clk
locked  
  conduit_0
outclk0   traffic_generator
  driver0_clk
outclk1  
  remote_intf_clk
outclk0   emif_io96b_ddr4comp_1
  s0_axi4_clock_in
outclk1  
  s0_axi4lite_clock
outclk1   axil_driver_0
  axil_driver_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)
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