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2024.11.28.13:51:23 | Datasheet |
altera_ace5lite_cache_coherency_translator_0 | ext_hps_f2sdram_master | subsys_debug | subsys_debug_fpga_m | subsys_debug_hps_f2sdram | subsys_debug_hps_m | subsys_hps | subsys_hps_agilex_hps | subsys_hps_f2sdram_adapter | subsys_periph_pb_cpu_0 | |||||
m0 | expanded_master | fpga_m_master | hps_f2sdram_master | hps_m_master | master | master | master | hps2fpga | lwhps2fpga | hps2fpga | lwhps2fpga | axi4_man | m0 | |
altera_ace5lite_cache_coherency_translator_0 | ||||||||||||||
s0 | 0x0000_0000 - 0xffff_ffff | 0x0000_0000 - 0xffff_ffff | ||||||||||||
ext_hps_f2sdram_master | ||||||||||||||
windowed_slave | 0x0000_0000 - 0xffff_ffff | 0x0000_0000 - 0xffff_ffff | ||||||||||||
ocm | ||||||||||||||
axi_s1 | 0x0004_0000 - 0x0007_ffff | 0x0004_0000 - 0x0007_ffff | 0x0000_0000_0000_0000 - 0x0000_0000_0003_ffff | 0x0000_0000_0000_0000 - 0x0000_0000_0003_ffff | ||||||||||
subsys_hps | ||||||||||||||
usb31_phy_reconfig_slave | ||||||||||||||
fpga2hps | ||||||||||||||
f2sdram_adapter_axi4_sub | ||||||||||||||
subsys_hps_agilex_hps | ||||||||||||||
usb31_phy_reconfig_slave | 0x0080_0000 - 0x00ff_ffff | 0x0080_0000 - 0x00ff_ffff | 0x0080_0000 - 0x00ff_ffff | 0x0080_0000 - 0x00ff_ffff | ||||||||||
f2sdram | 0x0000_0000 - 0xffff_ffff | |||||||||||||
fpga2hps | 0x0000_0000 - 0xffff_ffff | |||||||||||||
subsys_hps_f2sdram_adapter | ||||||||||||||
axi4_sub | 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff | 0x0000_0000 - 0xffff_ffff | 0x0000_0000 - 0xffff_ffff | |||||||||||
subsys_periph | ||||||||||||||
pb_cpu_0_s0 | ||||||||||||||
subsys_periph_button_pio | ||||||||||||||
s1 | 0x0001_0060 - 0x0001_006f | 0x0001_0060 - 0x0001_006f | 0x0001_0060 - 0x0001_006f | |||||||||||
subsys_periph_dipsw_pio | ||||||||||||||
s1 | 0x0001_0070 - 0x0001_007f | 0x0001_0070 - 0x0001_007f | 0x0001_0070 - 0x0001_007f | |||||||||||
subsys_periph_led_pio | ||||||||||||||
s1 | 0x0001_0080 - 0x0001_008f | 0x0001_0080 - 0x0001_008f | 0x0001_0080 - 0x0001_008f | |||||||||||
subsys_periph_pb_cpu_0 | ||||||||||||||
s0 | 0x0000_0000 - 0x0001_ffff | 0x0000_0000 - 0x0001_ffff | ||||||||||||
subsys_periph_sysid | ||||||||||||||
control_slave | 0x0001_0000 - 0x0001_0007 | 0x0001_0000 - 0x0001_0007 | 0x0001_0000 - 0x0001_0007 |
subsys_debug_hps_m | master | altera_ace5lite_cache_coherency_translator_0 | |
s0 | |||
clk_100 | out_clk | ||
clock | |||
rst_in | out_reset | ||
reset | |||
m0 | subsys_hps_agilex_hps | ||
fpga2hps |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
subsys_debug_hps_f2sdram | master | ext_hps_f2sdram_master | |
windowed_slave | |||
clk_100 | out_clk | ||
clock | |||
rst_in | out_reset | ||
reset | |||
expanded_master | subsys_hps_f2sdram_adapter | ||
axi4_sub |
Parameters
|
Software Assignments
|
Parameters
|
Software Assignments(none) |
subsys_debug_fpga_m | master | ocm |
axi_s1 | ||
subsys_hps_agilex_hps | hps2fpga | |
axi_s1 | ||
clk_100 | out_clk | |
clk1 | ||
rst_in | out_reset | |
reset1 |
Parameters
|
Software Assignments
|
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
subsys_debug_jtag_clk | out_clk | subsys_debug_fpga_m | |
clk | |||
subsys_debug_jtag_rst_in | out_reset | ||
clk_reset | |||
master | ocm | ||
axi_s1 | |||
master | subsys_hps_agilex_hps | ||
usb31_phy_reconfig_slave |
Parameters
|
Software Assignments(none) |
subsys_debug_jtag_clk | out_clk | subsys_debug_hps_f2sdram | |
clk | |||
subsys_debug_jtag_rst_in | out_reset | ||
clk_reset | |||
master | ext_hps_f2sdram_master | ||
windowed_slave |
Parameters
|
Software Assignments(none) |
subsys_debug_jtag_clk | out_clk | subsys_debug_hps_m | |
clk | |||
subsys_debug_jtag_rst_in | out_reset | ||
clk_reset | |||
master | altera_ace5lite_cache_coherency_translator_0 | ||
s0 |
Parameters
|
Software Assignments(none) |
clk_100 | out_clk | subsys_debug_jtag_clk | |
in_clk | |||
out_clk | subsys_debug_fpga_m | ||
clk | |||
out_clk | subsys_debug_hps_f2sdram | ||
clk | |||
out_clk | subsys_debug_hps_m | ||
clk |
Parameters
|
Software Assignments(none) |
rst_in | out_reset | subsys_debug_jtag_rst_in | |
in_reset | |||
out_reset | subsys_debug_fpga_m | ||
clk_reset | |||
out_reset | subsys_debug_hps_f2sdram | ||
clk_reset | |||
out_reset | subsys_debug_hps_m | ||
clk_reset |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
subsys_hps_f2sdram_adapter | axi4_man | subsys_hps_agilex_hps | |
f2sdram | |||
subsys_debug_fpga_m | master | ||
usb31_phy_reconfig_slave | |||
altera_ace5lite_cache_coherency_translator_0 | m0 | ||
fpga2hps | |||
clk_100 | out_clk | ||
f2sdram_axi_clock | |||
out_clk | |||
fpga2hps_clock | |||
out_clk | |||
hps2fpga_axi_clock | |||
out_clk | |||
lwhps2fpga_axi_clock | |||
out_clk | |||
usb31_phy_reconfig_clk | |||
rst_in | out_reset | ||
f2sdram_axi_reset | |||
out_reset | |||
fpga2hps_reset | |||
out_reset | |||
hps2fpga_axi_reset | |||
out_reset | |||
lwhps2fpga_axi_reset | |||
out_reset | |||
usb31_phy_reconfig_rst | |||
io96b0_to_hps | subsys_hps_emif_hps | ||
io96b0_to_hps | |||
hps2fpga | ocm | ||
axi_s1 | |||
lwhps2fpga | subsys_periph_pb_cpu_0 | ||
s0 | |||
fpga2hps_interrupt_irq0 | subsys_periph_button_pio | ||
irq | |||
fpga2hps_interrupt_irq0 | subsys_periph_dipsw_pio | ||
irq |
Parameters
|
Software Assignments
|
subsys_hps_agilex_hps | io96b0_to_hps | subsys_hps_emif_hps |
io96b0_to_hps |
Parameters
|
Software Assignments(none) |
ext_hps_f2sdram_master | expanded_master | subsys_hps_f2sdram_adapter | |
axi4_sub | |||
clk_100 | out_clk | ||
clock | |||
rst_in | out_reset | ||
reset | |||
axi4_man | subsys_hps_agilex_hps | ||
f2sdram |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
subsys_periph_pb_cpu_0 | m0 | subsys_periph_button_pio |
s1 | ||
subsys_periph_periph_clk | out_clk | |
clk | ||
subsys_periph_periph_rst_in | out_reset | |
reset | ||
subsys_hps_agilex_hps | fpga2hps_interrupt_irq0 | |
irq |
Parameters
|
Software Assignments
|
subsys_periph_pb_cpu_0 | m0 | subsys_periph_dipsw_pio |
s1 | ||
subsys_periph_periph_clk | out_clk | |
clk | ||
subsys_periph_periph_rst_in | out_reset | |
reset | ||
subsys_hps_agilex_hps | fpga2hps_interrupt_irq0 | |
irq |
Parameters
|
Software Assignments
|
subsys_periph_pb_cpu_0 | m0 | subsys_periph_led_pio |
s1 | ||
subsys_periph_periph_clk | out_clk | |
clk | ||
subsys_periph_periph_rst_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
subsys_periph_periph_clk | out_clk | subsys_periph_pb_cpu_0 | |
clk | |||
subsys_periph_periph_rst_in | out_reset | ||
reset | |||
subsys_hps_agilex_hps | lwhps2fpga | ||
s0 | |||
m0 | subsys_periph_sysid | ||
control_slave | |||
m0 | subsys_periph_led_pio | ||
s1 | |||
m0 | subsys_periph_dipsw_pio | ||
s1 | |||
m0 | subsys_periph_button_pio | ||
s1 |
Parameters
|
Software Assignments(none) |
clk_100 | out_clk | subsys_periph_periph_clk | |
in_clk | |||
out_clk | subsys_periph_sysid | ||
clk | |||
out_clk | subsys_periph_pb_cpu_0 | ||
clk | |||
out_clk | subsys_periph_led_pio | ||
clk | |||
out_clk | subsys_periph_dipsw_pio | ||
clk | |||
out_clk | subsys_periph_button_pio | ||
clk |
Parameters
|
Software Assignments(none) |
rst_in | out_reset | subsys_periph_periph_rst_in | |
in_reset | |||
out_reset | subsys_periph_sysid | ||
reset | |||
out_reset | subsys_periph_led_pio | ||
reset | |||
out_reset | subsys_periph_dipsw_pio | ||
reset | |||
out_reset | subsys_periph_button_pio | ||
reset | |||
out_reset | subsys_periph_pb_cpu_0 | ||
reset |
Parameters
|
Software Assignments(none) |
subsys_periph_pb_cpu_0 | m0 | subsys_periph_sysid |
control_slave | ||
subsys_periph_periph_clk | out_clk | |
clk | ||
subsys_periph_periph_rst_in | out_reset | |
reset |
Parameters
|
Software Assignments
|
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