Qsys_XCVR_CLK

2024.11.29.15:41:48 Datasheet
Overview

All Components
   xcvr_fmcp_x4_refclk0 xcvr_fmcp_x4_refclk0 1.0
   xcvr_fmcp_x4_refclk0_intel_directphy_gts_x4 intel_directphy_gts 6.0.0
   xcvr_fmcp_x4_refclk1 xcvr_fmcp_x4_refclk1 1.0
   xcvr_fmcp_x4_refclk1_intel_directphy_gts_x4 intel_directphy_gts 6.0.0
   xcvr_fmcp_x4_refclk2 xcvr_fmcp_x4_refclk2 1.0
   xcvr_fmcp_x4_refclk2_intel_directphy_gts_x4 intel_directphy_gts 6.0.0
   xcvr_pcie_x4 xcvr_pcie_x4 1.0
   xcvr_pcie_x4_intel_directphy_gts_x4 intel_directphy_gts 6.0.0
   xcvr_qsfp xcvr_x4 1.0
   xcvr_qsfp_intel_directphy_gts_x4 intel_directphy_gts 6.0.0
   xcvr_usb3_x2_refclk xcvr_usb3_x2_refclk 1.0
   xcvr_usb3_x2_refclk_intel_directphy_gts_x4 intel_directphy_gts 6.0.0
Memory Map
  xcvr_fmcp_x4_refclk0
intel_directphy_gts_x4_reconfig 
  xcvr_fmcp_x4_refclk0_intel_directphy_gts_x4
reconfig 
  xcvr_fmcp_x4_refclk1
intel_directphy_gts_x4_reconfig 
  xcvr_fmcp_x4_refclk1_intel_directphy_gts_x4
reconfig 
  xcvr_fmcp_x4_refclk2
intel_directphy_gts_x4_reconfig 
  xcvr_fmcp_x4_refclk2_intel_directphy_gts_x4
reconfig 
  xcvr_pcie_x4
intel_directphy_gts_x4_reconfig 
  xcvr_pcie_x4_intel_directphy_gts_x4
reconfig 
  xcvr_qsfp
intel_directphy_gts_x4_reconfig 
  xcvr_qsfp_intel_directphy_gts_x4
reconfig 
  xcvr_usb3_x2_refclk
intel_directphy_gts_x4_reconfig 
  xcvr_usb3_x2_refclk_intel_directphy_gts_x4
reconfig 

clock_in

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_srcss_gts_bank1

intel_srcss_gts v3.1.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

intel_srcss_gts_bank4

intel_srcss_gts v3.1.1


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_in

altera_reset_bridge v19.2.0
clock_in out_clk   reset_in
  clk
out_reset   xcvr_qsfp_intel_directphy_gts_x4
  i_reconfig_reset
out_reset   xcvr_pcie_x4_intel_directphy_gts_x4
  i_reconfig_reset
out_reset   xcvr_fmcp_x4_refclk0_intel_directphy_gts_x4
  i_reconfig_reset
out_reset   xcvr_fmcp_x4_refclk1_intel_directphy_gts_x4
  i_reconfig_reset
out_reset   xcvr_fmcp_x4_refclk2_intel_directphy_gts_x4
  i_reconfig_reset
out_reset   xcvr_usb3_x2_refclk_intel_directphy_gts_x4
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk0

xcvr_fmcp_x4_refclk0 v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk0_clock_bridge_xcvr_pma_rx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk0_clock_bridge_xcvr_pma_tx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk0_intel_directphy_gts_x4

intel_directphy_gts v6.0.0
xcvr_fmcp_x4_refclk0_intel_systemclk_gts o_syspll_c0   xcvr_fmcp_x4_refclk0_intel_directphy_gts_x4
  i_system_pll_clk
xcvr_fmcp_x4_refclk0_clock_bridge_xcvr_pma_rx_refclk out_clk  
  i_rx_cdr_refclk_p
xcvr_fmcp_x4_refclk0_clock_bridge_xcvr_pma_tx_refclk out_clk  
  i_tx_pll_refclk_p
clock_in out_clk  
  i_reconfig_clk
reset_in out_reset  
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk0_intel_systemclk_gts

intel_systemclk_gts v4.1.1
xcvr_fmcp_x4_refclk0_clock_bridge_xcvr_pma_tx_refclk out_clk   xcvr_fmcp_x4_refclk0_intel_systemclk_gts
  refclk_xcvr
o_syspll_c0   xcvr_fmcp_x4_refclk0_intel_directphy_gts_x4
  i_system_pll_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk1

xcvr_fmcp_x4_refclk1 v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk1_clock_bridge_xcvr_pma_rx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk1_clock_bridge_xcvr_pma_tx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk1_intel_directphy_gts_x4

intel_directphy_gts v6.0.0
xcvr_fmcp_x4_refclk1_intel_systemclk_gts o_syspll_c0   xcvr_fmcp_x4_refclk1_intel_directphy_gts_x4
  i_system_pll_clk
xcvr_fmcp_x4_refclk1_clock_bridge_xcvr_pma_rx_refclk out_clk  
  i_rx_cdr_refclk_p
xcvr_fmcp_x4_refclk1_clock_bridge_xcvr_pma_tx_refclk out_clk  
  i_tx_pll_refclk_p
clock_in out_clk  
  i_reconfig_clk
reset_in out_reset  
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk1_intel_systemclk_gts

intel_systemclk_gts v4.1.1
xcvr_fmcp_x4_refclk1_clock_bridge_xcvr_pma_tx_refclk out_clk   xcvr_fmcp_x4_refclk1_intel_systemclk_gts
  refclk_xcvr
o_syspll_c0   xcvr_fmcp_x4_refclk1_intel_directphy_gts_x4
  i_system_pll_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk2

xcvr_fmcp_x4_refclk2 v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk2_clock_bridge_xcvr_pma_rx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk2_clock_bridge_xcvr_pma_tx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk2_intel_directphy_gts_x4

intel_directphy_gts v6.0.0
xcvr_fmcp_x4_refclk2_intel_systemclk_gts o_syspll_c0   xcvr_fmcp_x4_refclk2_intel_directphy_gts_x4
  i_system_pll_clk
xcvr_fmcp_x4_refclk2_clock_bridge_xcvr_pma_rx_refclk out_clk  
  i_rx_cdr_refclk_p
xcvr_fmcp_x4_refclk2_clock_bridge_xcvr_pma_tx_refclk out_clk  
  i_tx_pll_refclk_p
clock_in out_clk  
  i_reconfig_clk
reset_in out_reset  
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_fmcp_x4_refclk2_intel_systemclk_gts

intel_systemclk_gts v4.1.1
xcvr_fmcp_x4_refclk2_clock_bridge_xcvr_pma_tx_refclk out_clk   xcvr_fmcp_x4_refclk2_intel_systemclk_gts
  refclk_xcvr
o_syspll_c0   xcvr_fmcp_x4_refclk2_intel_directphy_gts_x4
  i_system_pll_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_pcie_x4

xcvr_pcie_x4 v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_pcie_x4_clock_bridge_xcvr_pma_rx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_pcie_x4_clock_bridge_xcvr_pma_tx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_pcie_x4_intel_directphy_gts_x4

intel_directphy_gts v6.0.0
xcvr_pcie_x4_intel_systemclk_gts o_syspll_c0   xcvr_pcie_x4_intel_directphy_gts_x4
  i_system_pll_clk
xcvr_pcie_x4_clock_bridge_xcvr_pma_rx_refclk out_clk  
  i_rx_cdr_refclk_p
xcvr_pcie_x4_clock_bridge_xcvr_pma_tx_refclk out_clk  
  i_tx_pll_refclk_p
clock_in out_clk  
  i_reconfig_clk
reset_in out_reset  
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_pcie_x4_intel_systemclk_gts

intel_systemclk_gts v4.1.1
xcvr_pcie_x4_clock_bridge_xcvr_pma_tx_refclk out_clk   xcvr_pcie_x4_intel_systemclk_gts
  refclk_xcvr
o_syspll_c0   xcvr_pcie_x4_intel_directphy_gts_x4
  i_system_pll_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_qsfp

xcvr_x4 v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_qsfp_clock_bridge_xcvr_syspll_ref

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_qsfp_intel_directphy_gts_x4

intel_directphy_gts v6.0.0
xcvr_qsfp_intel_systemclk_gts o_syspll_c0   xcvr_qsfp_intel_directphy_gts_x4
  i_system_pll_clk
xcvr_qsfp_clock_bridge_xcvr_syspll_ref out_clk  
  i_rx_cdr_refclk_p
out_clk  
  i_tx_pll_refclk_p
clock_in out_clk  
  i_reconfig_clk
reset_in out_reset  
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_qsfp_intel_systemclk_gts

intel_systemclk_gts v4.1.1
xcvr_qsfp_clock_bridge_xcvr_syspll_ref out_clk   xcvr_qsfp_intel_systemclk_gts
  refclk_xcvr
o_syspll_c0   xcvr_qsfp_intel_directphy_gts_x4
  i_system_pll_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_usb3_x2_refclk

xcvr_usb3_x2_refclk v1.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_usb3_x2_refclk_clock_bridge_xcvr_pma_rx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_usb3_x2_refclk_clock_bridge_xcvr_pma_tx_refclk

altera_clock_bridge v19.2.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_usb3_x2_refclk_intel_directphy_gts_x4

intel_directphy_gts v6.0.0
xcvr_usb3_x2_refclk_intel_systemclk_gts o_syspll_c0   xcvr_usb3_x2_refclk_intel_directphy_gts_x4
  i_system_pll_clk
xcvr_usb3_x2_refclk_clock_bridge_xcvr_pma_rx_refclk out_clk  
  i_rx_cdr_refclk_p
xcvr_usb3_x2_refclk_clock_bridge_xcvr_pma_tx_refclk out_clk  
  i_tx_pll_refclk_p
clock_in out_clk  
  i_reconfig_clk
reset_in out_reset  
  i_reconfig_reset


Parameters

generateLegacySim false
  

Software Assignments

(none)

xcvr_usb3_x2_refclk_intel_systemclk_gts

intel_systemclk_gts v4.1.1
xcvr_usb3_x2_refclk_clock_bridge_xcvr_pma_tx_refclk out_clk   xcvr_usb3_x2_refclk_intel_systemclk_gts
  refclk_xcvr
o_syspll_c0   xcvr_usb3_x2_refclk_intel_directphy_gts_x4
  i_system_pll_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)
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