xcvr_x4_intel_directphy_gts_0

2024.11.29.15:36:07 Datasheet
Overview

All Components
   intel_directphy_gts_x4 intel_directphy_gts 6.0.0
   intel_directphy_gts_x4_dphy_adme intel_directphy_gts_intel_adme_gts 6.0.0
   intel_directphy_gts_x4_dphy_adme_dphy_adme intel_adme_gts 1.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper intel_directphy_gts_n_channel_superset 6.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper n_channel_superset 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip n_channel_superset_hal_top 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip hal_top 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0 hal_top_one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0 one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pcs_hal_top one_lane_hal_pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pcs_hal_top_pcs_hal_top pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top one_lane_hal_fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top_fec_hal_top fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top one_lane_hal_pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top_pldif_hal_top pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top one_lane_hal_phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top_phy_hal_top phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1 hal_top_one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1 one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pcs_hal_top one_lane_hal_pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pcs_hal_top_pcs_hal_top pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top one_lane_hal_fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top_fec_hal_top fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top one_lane_hal_pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top_pldif_hal_top pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top one_lane_hal_phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top_phy_hal_top phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2 hal_top_one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2 one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pcs_hal_top one_lane_hal_pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pcs_hal_top_pcs_hal_top pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top one_lane_hal_fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top_fec_hal_top fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top one_lane_hal_pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top_pldif_hal_top pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top one_lane_hal_phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top_phy_hal_top phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3 hal_top_one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3 one_lane_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pcs_hal_top one_lane_hal_pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pcs_hal_top_pcs_hal_top pcs_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top one_lane_hal_fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top_fec_hal_top fec_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top one_lane_hal_pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top_pldif_hal_top pldif_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top one_lane_hal_phy_hal 21.0.0
   intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top_phy_hal_top phy_hal 21.0.0
Memory Map
intel_directphy_gts_x4_dphy_adme intel_directphy_gts_x4_dphy_adme_dphy_adme intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3 intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top_fec_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top_pldif_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top_phy_hal_top
 avmm2_address_tile  avmm2_byte_enable_tile  avmm2_write_tile  avmm2_read_tile  avmm2_write_data_tile  avmm2_read_data_user  avmm2_waitrequest_user  avmm2_read_data_valid_user  avmm1_address_tile  avmm1_byte_enable_tile  avmm1_write_tile  avmm1_read_tile  avmm1_write_data_tile  avmm1_read_data_user  avmm1_waitrequest_user  avmm1_read_data_valid_user  avmm2_address_tile  avmm2_byte_enable_tile  avmm2_write_tile  avmm2_read_tile  avmm2_write_data_tile  avmm2_read_data_user  avmm2_waitrequest_user  avmm2_read_data_valid_user  avmm1_address_tile  avmm1_byte_enable_tile  avmm1_write_tile  avmm1_read_tile  avmm1_write_data_tile  avmm1_read_data_user  avmm1_waitrequest_user  avmm1_read_data_valid_user  reconfig_phy_shared  reconfig_fecwrap  reconfig_phy_shared  reconfig_fecwrap  reconfig_fecwrap  reconfig_fecwrap  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_phy_shared  reconfig_phy_shared  reconfig_phy_shared  reconfig_fecwrap  reconfig_phy_shared  reconfig_fecwrap  reconfig_fecwrap  reconfig_fecwrap  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_phy_shared  reconfig_phy_shared  reconfig_phy_shared  reconfig_fecwrap  reconfig_phy_shared  reconfig_fecwrap  reconfig_fecwrap  reconfig_fecwrap  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_phy_shared  reconfig_phy_shared  reconfig_phy_shared  reconfig_fecwrap  reconfig_phy_shared  reconfig_fecwrap  reconfig_fecwrap  reconfig_fecwrap  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_pcie  reconfig_xcvrif  reconfig_emac  reconfig_epcs  reconfig_fec  reconfig_ux  reconfig_phy_shared  reconfig_phy_shared
  intel_directphy_gts_x4
reconfig 
  intel_directphy_gts_x4_dphy_adme
avmm2_address_user 
avmm2_byte_enable_user 
avmm2_write_user 
avmm2_read_user 
avmm2_write_data_user 
avmm2_read_data_tile 
avmm2_waitrequest_tile 
avmm2_read_data_valid_tile 
avmm1_address_user 
avmm1_byte_enable_user 
avmm1_write_user 
avmm1_read_user 
avmm1_write_data_user 
avmm1_read_data_tile 
avmm1_waitrequest_tile 
avmm1_read_data_valid_tile 
  intel_directphy_gts_x4_dphy_adme_dphy_adme
avmm2_address_user 
avmm2_byte_enable_user 
avmm2_write_user 
avmm2_read_user 
avmm2_write_data_user 
avmm2_read_data_tile 
avmm2_waitrequest_tile 
avmm2_read_data_valid_tile 
avmm1_address_user 
avmm1_byte_enable_user 
avmm1_write_user 
avmm1_read_user 
avmm1_write_data_user 
avmm1_read_data_tile 
avmm1_waitrequest_tile 
avmm1_read_data_valid_tile 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper
hio_ch0_lavmm 
hio_ch1_lavmm 
hio_ch2_lavmm 
hio_ch3_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper
hio_ch0_lavmm 
hio_ch1_lavmm 
hio_ch2_lavmm 
hio_ch3_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip
hio_ch0_lavmm 
hio_ch1_lavmm 
hio_ch2_lavmm 
hio_ch3_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip
hio_ch0_lavmm 
hio_ch1_lavmm 
hio_ch2_lavmm 
hio_ch3_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pcs_hal_top_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pcs_hal_top_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pcs_hal_top_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pcs_hal_top_pcs_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top_fec_hal_top
reconfig 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top_pldif_hal_top
reconfig_lavmm 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top
reconfig 
reconfig_xcvr 
  intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top_phy_hal_top
reconfig 
reconfig_xcvr 

intel_directphy_gts_x4

intel_directphy_gts v6.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 156.250000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_mhz 184.320000
duplex_mode_rphy duplex
fec_en_rphy 0
syspll_outclk_freq_mhz_rphy 322.265625
protocol_mode DISABLED
num_xcvr_per_sys 4
clocking_mode syspll
syspll_outclk_freq_mhz 322.265625
duplex_mode duplex
ed_sel None
ed_ack 0
ed_hdl_sel Verilog
ed_board None
pma_data_rate 1105.92
pma_outclk_freq_mhz 34.56
pma_width 32
enable_split_interface 0
custom_pcs_en 1
custom_pcs_mode IEEE MII Interface
enable_refclock_to_core 1
serdes_lpbk_mode LOOPBACK_MODE_DISABLED
tx_pll_txuserclk_div 100
tx_pll_txuserclk_freq_mhz 88.4736
enable_port_rx_cdr_divclk_link0 0
rx_cdr_lock_mode auto
enable_port_rx_set_locktoref 0
rx_cdr_rxuserclk_div 100
rx_cdr_rxuserclk_freq_mhz 88.4736
pmaif_tx_fifo_mode_s elastic
enable_port_tx_pmaif_fifo_empty 0
enable_port_tx_pmaif_fifo_pempty 0
enable_port_tx_pmaif_fifo_pfull 0
pmaif_rx_fifo_mode_s elastic
enable_port_rx_pmaif_fifo_empty 0
enable_port_rx_pmaif_fifo_pempty 0
enable_port_rx_pmaif_fifo_pfull 0
fec_en 0
l_fec_mode IEEE 802.3 BASE-R Firecode (CL 74)
fec_lpbk_en 0
l_av1_enable 1
avmm1_soft_csr_enable 1
avmm1_readdv_enable 1
avmm1_split 0
avmm1_jtag_enable 1
enable_port_latency_measurement 0
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
tx_custom_cadence_enable 0
enable_port_tx_cadence_slow_clk_locked 1
pldif_tx_fifo_mode phase_comp
pldif_tx_double_width_transfer_enable 1
enable_port_tx_fifo_full 0
enable_port_tx_fifo_empty 0
enable_port_tx_fifo_pfull 0
enable_port_tx_fifo_pempty 0
pldif_tx_clkout_sel PLL_DIV1
pldif_tx_clkout_div 2
pldif_tx_clkout_freq_mhz 161.132812
enable_port_tx_clkout2 0
pldif_rx_fifo_mode phase_comp
pldif_rx_double_width_transfer_enable 1
enable_port_rx_fifo_full 0
enable_port_rx_fifo_empty 0
enable_port_rx_fifo_pfull 0
enable_port_rx_fifo_pempty 0
enable_port_rx_fifo_rd_en 0
pldif_rx_clkout_sel PLL_DIV1
pldif_rx_clkout_div 2
pldif_rx_clkout_freq_mhz 161.132812
enable_port_rx_clkout2 0
tx_spread_spectrum_en DISABLE
tx_invert_pin DISABLE
ux_txeq_post_tap_1 5
ux_txeq_main_tap 52
ux_txeq_pre_tap_1 0
ux_txeq_pre_tap_2 0
rx_adaptation_mode auto
rx_invert_pin DISABLE
rx_external_couple_type AC
rx_termination_mode GROUNDED
rx_onchip_termination R_2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_dphy_adme

intel_directphy_gts_intel_adme_gts v6.0.0


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_dphy_adme_dphy_adme

intel_adme_gts v1.0.0


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper

intel_directphy_gts_n_channel_superset v6.0.0


Parameters

num_of_lanes 4
dr_enable DR_ENABLED
SRC_SIM_SCALE_DOWN 0
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch0_lane_id 0
ch0_tx_channel_mode PCSD
ch0_rx_channel_mode PCSD
ch0_duplex_mode DUPLEX
ch0_rate_mode RATE_25G
ch0_ptp_mode DISABLED
ch0_fec_mode 0
ch0_tx_dl_enable DISABLE
ch0_rx_dl_enable DISABLE
ch0_sup_mode USER_MODE
ch0_sim_mode ENABLE
ch0_syspll_rx_clk_hz 322265625
ch0_syspll_tx_clk_hz 322265625
ch0_tx_user1_clk_dynamic_mux PLL_C0
ch0_tx_user2_clk_dynamic_mux DISABLED
ch0_rx_user1_clk_dynamic_mux PLL_C0
ch0_rx_user2_clk_dynamic_mux DISABLED
ch0_tx_bond_size 4
ch0_rx_bond_size 1
ch0_xcvr_tx_protocol_hint DISABLED
ch0_xcvr_tx_datarate_bps 1105.92
ch0_xcvr_tx_prbs_pattern DISABLE
ch0_xcvr_tx_user_clk_only_mode DISABLE
ch0_xcvr_tx_width 32
ch0_xcvr_rx_protocol_hint DISABLED
ch0_xcvr_rx_datarate_bps 1105.92
ch0_xcvr_rx_prbs_pattern DISABLE
ch0_xcvr_rx_width 32
ch0_xcvr_rx_force_cdr_ltr FALSE
ch0_xcvr_rx_adaptation_mode DISABLED
ch0_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch0_xcvr_cdr_f_ref_hz 184320000
ch0_xcvr_cdr_f_vco_hz 552960000
ch0_rx_postdiv_clk_en ENABLE
ch0_rx_postdiv_clk_divider 100
ch0_tx_postdiv_clk_divider 100
ch0_tx_pll_f_ref_hz 184320000
ch0_tx_pll_f_out_hz 552960000
ch0_tx_pll_refclk_select GLOBAL_REFCLK0
ch0_cdr_refclk_select GLOBAL_REFCLK1
ch0_phy_loopback_mode DISABLED
ch0_flux_mode FLUX_MODE_BYPASS
ch0_flux_mode_hw FLUX_MODE_SNIFFER
ch0_xcvrif_tx_fifo_mode ELASTIC
ch0_xcvrif_rx_fifo_mode ELASTIC
ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch0_xcvr_tx_spread_spectrum_en DISABLE
ch0_xcvr_tx_cascade_en DISABLE
ch0_tx_pcs_mode IEEE
ch0_rx_pcs_mode IEEE
ch0_mac_link_fault_mode OFF
ch0_mac_remove_pads DISABLE
ch0_mac_keep_rx_crc DISABLE
ch0_mac_forward_rx_pause_requests DISABLE
ch0_mac_source_address_insertion DISABLE
ch0_mac_tx_vlan_detection DISABLE
ch0_mac_rx_vlan_detection DISABLE
ch0_mac_flow_control DISABLE FLOW CONTROL
ch0_mac_tx_max_frame_size 65
ch0_mac_rx_max_frame_size 65
ch0_mac_enforce_max_frame_size DISABLE
ch0_mac_tx_preamble_passthrough DISABLE
ch0_mac_rx_preamble_passthrough DISABLE
ch0_mac_strict_preamble_checking DISABLE
ch0_mac_strict_sfd_checking DISABLE
ch0_mac_tx_ipg_size 12
ch0_mac_ipg_removed_per_am_period 0
ch0_mac_custom_cadence DISABLE
ch0_ptp0_en DISABLED
ch0_ptp1_en DISABLED
ch0_mac_sim_mode ENABLE
ch0_ptp0_sim_mode ENABLE
ch0_ptp1_sim_mode ENABLE
ch0_mac_tx_mac_data_flow DISABLE
ch0_mac_sf_en DISABLED
ch0_ehip_loopback_mode NO_LOOPBACK
ch0_mac_txmac_saddr 001122334455
ch0_pldif_tx_fifo_mode PHASE_COMP
ch0_pldif_tx_fifo_width DOUBLE_WIDTH
ch0_pldif_rx_fifo_mode PHASE_COMP
ch0_pldif_rx_fifo_width DOUBLE_WIDTH
ch0_pldif_tx_clkout1_divider DIV2
ch0_pldif_tx_clkout2_divider DIV2
ch0_pldif_rx_clkout1_divider DIV2
ch0_pldif_rx_clkout2_divider DIV2
ch0_pldif_channel_identifier GENERIC
ch0_pldif_sf_en ENABLED
ch0_pldif_loopback_mode NO_LOOPBACK
ch0_pcs_loopback_mode NO_LOOPBACK
ch0_pcs_sf_en ENABLED
ch0_fec_spec DISABLED
ch0_fec_fracture UNUSED
ch0_fec_tx_en FALSE
ch0_fec_rx_en FALSE
ch0_fec_loopback_mode DISABLE
ch0_tx_pll_frac_mode_en DISABLE
ch0_rx_invert_pin DISABLE
ch0_tx_invert_pin DISABLE
ch0_xcvr_rx_cdrdivout_en DISABLE
ch0_xcvr_tx_eq_main_tap 52
ch0_xcvr_tx_eq_post_tap_1 5
ch0_xcvr_tx_eq_pre_tap_1 0
ch0_xcvr_tx_eq_pre_tap_2 0
ch0_tx_pll_feed_forward_gain 197
ch0_xcvr_rx_termination_mode GROUNDED
ch0_xcvr_rx_onchip_termination_setting R_2
ch0_xcvr_rx_eq_vga_gain 0
ch0_xcvr_x_eq_hf_boost 0
ch0_xcvr_rx_eq_dfe_tap_1 0
ch0_xcvr_rx_external_couple_type AC
ch0_sequencer_reg_en DISABLE
ch0_rx_dl_rx_lat_bit_for_async 0
ch0_rx_dl_rxbit_rollover 0
ch0_rx_dl_rxbit_cntr_pma DISABLE
ch0_hw_fec 0
CH0_SRC_TX_ENABLE 1
CH0_SRC_RX_ENABLE 1
CH0_SRC_TX_INITIATOR 1
CH0_SRC_RX_INITIATOR 1
CH0_SRC_TX_INITIATOR_INDEX 0
CH0_SRC_RX_INITIATOR_INDEX 0
CH0_SRC_TX_TARGET_ENABLE 14
CH0_SRC_RX_TARGET_ENABLE 14
CH0_SRC_TX_LANE_FUCTIONAL_MODE 3
CH0_SRC_RX_LANE_FUCTIONAL_MODE 3
CH0_SRC_NON_PTP_CHANNEL 1
CH0_SRC_TX_PCS_EN 1
CH0_SRC_RX_PCS_EN 1
CH0_SRC_UX_EN 1
CH0_SRC_TX_DL_EN 0
CH0_SRC_RX_DL_EN 0
CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH0_SRC_PTP_EN 0
CH0_SRC_TX_FEC_EN 0
CH0_SRC_RX_FEC_EN 0
CH0_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH0_SRC_UX_USING_SYSPLL_CLK 0
CH0_SRC_FLUX_USING_SYSPLL_CLK 0
CH0_SRC_FLUX_EN 0
CH0_SRC_FLUX_EN_HW 1
CH0_SRC_SRC_LANE_INDEX 0
CH0_SRC_LEADER_LANE 1
ch1_lane_id 1
ch1_tx_channel_mode PCSD
ch1_rx_channel_mode PCSD
ch1_duplex_mode DUPLEX
ch1_rate_mode RATE_25G
ch1_ptp_mode DISABLED
ch1_fec_mode 0
ch1_tx_dl_enable DISABLE
ch1_rx_dl_enable DISABLE
ch1_sup_mode USER_MODE
ch1_sim_mode ENABLE
ch1_syspll_rx_clk_hz 322265625
ch1_syspll_tx_clk_hz 322265625
ch1_tx_user1_clk_dynamic_mux PLL_C0
ch1_tx_user2_clk_dynamic_mux DISABLED
ch1_rx_user1_clk_dynamic_mux PLL_C0
ch1_rx_user2_clk_dynamic_mux DISABLED
ch1_tx_bond_size 4
ch1_rx_bond_size 1
ch1_xcvr_tx_protocol_hint DISABLED
ch1_xcvr_tx_datarate_bps 1105.92
ch1_xcvr_tx_prbs_pattern DISABLE
ch1_xcvr_tx_user_clk_only_mode DISABLE
ch1_xcvr_tx_width 32
ch1_xcvr_rx_protocol_hint DISABLED
ch1_xcvr_rx_datarate_bps 1105.92
ch1_xcvr_rx_prbs_pattern DISABLE
ch1_xcvr_rx_width 32
ch1_xcvr_rx_force_cdr_ltr FALSE
ch1_xcvr_rx_adaptation_mode DISABLED
ch1_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch1_xcvr_cdr_f_ref_hz 184320000
ch1_xcvr_cdr_f_vco_hz 552960000
ch1_rx_postdiv_clk_en ENABLE
ch1_rx_postdiv_clk_divider 100
ch1_tx_postdiv_clk_divider 100
ch1_tx_pll_f_ref_hz 184320000
ch1_tx_pll_f_out_hz 552960000
ch1_tx_pll_refclk_select GLOBAL_REFCLK0
ch1_cdr_refclk_select GLOBAL_REFCLK1
ch1_phy_loopback_mode DISABLED
ch1_flux_mode FLUX_MODE_BYPASS
ch1_flux_mode_hw FLUX_MODE_SNIFFER
ch1_xcvrif_tx_fifo_mode ELASTIC
ch1_xcvrif_rx_fifo_mode ELASTIC
ch1_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch1_xcvr_tx_spread_spectrum_en DISABLE
ch1_xcvr_tx_cascade_en DISABLE
ch1_tx_pcs_mode IEEE
ch1_rx_pcs_mode IEEE
ch1_mac_link_fault_mode OFF
ch1_mac_remove_pads DISABLE
ch1_mac_keep_rx_crc DISABLE
ch1_mac_forward_rx_pause_requests DISABLE
ch1_mac_source_address_insertion DISABLE
ch1_mac_tx_vlan_detection DISABLE
ch1_mac_rx_vlan_detection DISABLE
ch1_mac_flow_control DISABLE FLOW CONTROL
ch1_mac_tx_max_frame_size 65
ch1_mac_rx_max_frame_size 65
ch1_mac_enforce_max_frame_size DISABLE
ch1_mac_tx_preamble_passthrough DISABLE
ch1_mac_rx_preamble_passthrough DISABLE
ch1_mac_strict_preamble_checking DISABLE
ch1_mac_strict_sfd_checking DISABLE
ch1_mac_tx_ipg_size 12
ch1_mac_ipg_removed_per_am_period 0
ch1_mac_custom_cadence DISABLE
ch1_ptp0_en DISABLED
ch1_ptp1_en DISABLED
ch1_mac_sim_mode ENABLE
ch1_ptp0_sim_mode ENABLE
ch1_ptp1_sim_mode ENABLE
ch1_mac_tx_mac_data_flow DISABLE
ch1_mac_sf_en DISABLED
ch1_ehip_loopback_mode NO_LOOPBACK
ch1_mac_txmac_saddr 001122334455
ch1_pldif_tx_fifo_mode PHASE_COMP
ch1_pldif_tx_fifo_width DOUBLE_WIDTH
ch1_pldif_rx_fifo_mode PHASE_COMP
ch1_pldif_rx_fifo_width DOUBLE_WIDTH
ch1_pldif_tx_clkout1_divider DIV2
ch1_pldif_tx_clkout2_divider DIV2
ch1_pldif_rx_clkout1_divider DIV2
ch1_pldif_rx_clkout2_divider DIV2
ch1_pldif_channel_identifier GENERIC
ch1_pldif_sf_en ENABLED
ch1_pldif_loopback_mode NO_LOOPBACK
ch1_pcs_loopback_mode NO_LOOPBACK
ch1_pcs_sf_en ENABLED
ch1_fec_spec DISABLED
ch1_fec_fracture UNUSED
ch1_fec_tx_en FALSE
ch1_fec_rx_en FALSE
ch1_fec_loopback_mode DISABLE
ch1_tx_pll_frac_mode_en DISABLE
ch1_rx_invert_pin DISABLE
ch1_tx_invert_pin DISABLE
ch1_xcvr_rx_cdrdivout_en DISABLE
ch1_xcvr_tx_eq_main_tap 52
ch1_xcvr_tx_eq_post_tap_1 5
ch1_xcvr_tx_eq_pre_tap_1 0
ch1_xcvr_tx_eq_pre_tap_2 0
ch1_tx_pll_feed_forward_gain 197
ch1_xcvr_rx_termination_mode GROUNDED
ch1_xcvr_rx_onchip_termination_setting R_2
ch1_xcvr_rx_eq_vga_gain 0
ch1_xcvr_x_eq_hf_boost 0
ch1_xcvr_rx_eq_dfe_tap_1 0
ch1_xcvr_rx_external_couple_type AC
ch1_sequencer_reg_en DISABLE
ch1_rx_dl_rx_lat_bit_for_async 0
ch1_rx_dl_rxbit_rollover 0
ch1_rx_dl_rxbit_cntr_pma DISABLE
ch1_hw_fec 0
CH1_SRC_TX_ENABLE 1
CH1_SRC_RX_ENABLE 1
CH1_SRC_TX_INITIATOR 0
CH1_SRC_RX_INITIATOR 0
CH1_SRC_TX_INITIATOR_INDEX 0
CH1_SRC_RX_INITIATOR_INDEX 0
CH1_SRC_TX_TARGET_ENABLE 0
CH1_SRC_RX_TARGET_ENABLE 0
CH1_SRC_TX_LANE_FUCTIONAL_MODE 3
CH1_SRC_RX_LANE_FUCTIONAL_MODE 3
CH1_SRC_NON_PTP_CHANNEL 1
CH1_SRC_TX_PCS_EN 1
CH1_SRC_RX_PCS_EN 1
CH1_SRC_UX_EN 1
CH1_SRC_TX_DL_EN 0
CH1_SRC_RX_DL_EN 0
CH1_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH1_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH1_SRC_PTP_EN 0
CH1_SRC_TX_FEC_EN 0
CH1_SRC_RX_FEC_EN 0
CH1_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH1_SRC_UX_USING_SYSPLL_CLK 0
CH1_SRC_FLUX_USING_SYSPLL_CLK 0
CH1_SRC_FLUX_EN 0
CH1_SRC_FLUX_EN_HW 1
CH1_SRC_SRC_LANE_INDEX 1
CH1_SRC_LEADER_LANE 0
ch2_lane_id 2
ch2_tx_channel_mode PCSD
ch2_rx_channel_mode PCSD
ch2_duplex_mode DUPLEX
ch2_rate_mode RATE_25G
ch2_ptp_mode DISABLED
ch2_fec_mode 0
ch2_tx_dl_enable DISABLE
ch2_rx_dl_enable DISABLE
ch2_sup_mode USER_MODE
ch2_sim_mode ENABLE
ch2_syspll_rx_clk_hz 322265625
ch2_syspll_tx_clk_hz 322265625
ch2_tx_user1_clk_dynamic_mux PLL_C0
ch2_tx_user2_clk_dynamic_mux DISABLED
ch2_rx_user1_clk_dynamic_mux PLL_C0
ch2_rx_user2_clk_dynamic_mux DISABLED
ch2_tx_bond_size 4
ch2_rx_bond_size 1
ch2_xcvr_tx_protocol_hint DISABLED
ch2_xcvr_tx_datarate_bps 1105.92
ch2_xcvr_tx_prbs_pattern DISABLE
ch2_xcvr_tx_user_clk_only_mode DISABLE
ch2_xcvr_tx_width 32
ch2_xcvr_rx_protocol_hint DISABLED
ch2_xcvr_rx_datarate_bps 1105.92
ch2_xcvr_rx_prbs_pattern DISABLE
ch2_xcvr_rx_width 32
ch2_xcvr_rx_force_cdr_ltr FALSE
ch2_xcvr_rx_adaptation_mode DISABLED
ch2_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch2_xcvr_cdr_f_ref_hz 184320000
ch2_xcvr_cdr_f_vco_hz 552960000
ch2_rx_postdiv_clk_en ENABLE
ch2_rx_postdiv_clk_divider 100
ch2_tx_postdiv_clk_divider 100
ch2_tx_pll_f_ref_hz 184320000
ch2_tx_pll_f_out_hz 552960000
ch2_tx_pll_refclk_select GLOBAL_REFCLK0
ch2_cdr_refclk_select GLOBAL_REFCLK1
ch2_phy_loopback_mode DISABLED
ch2_flux_mode FLUX_MODE_BYPASS
ch2_flux_mode_hw FLUX_MODE_SNIFFER
ch2_xcvrif_tx_fifo_mode ELASTIC
ch2_xcvrif_rx_fifo_mode ELASTIC
ch2_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch2_xcvr_tx_spread_spectrum_en DISABLE
ch2_xcvr_tx_cascade_en DISABLE
ch2_tx_pcs_mode IEEE
ch2_rx_pcs_mode IEEE
ch2_mac_link_fault_mode OFF
ch2_mac_remove_pads DISABLE
ch2_mac_keep_rx_crc DISABLE
ch2_mac_forward_rx_pause_requests DISABLE
ch2_mac_source_address_insertion DISABLE
ch2_mac_tx_vlan_detection DISABLE
ch2_mac_rx_vlan_detection DISABLE
ch2_mac_flow_control DISABLE FLOW CONTROL
ch2_mac_tx_max_frame_size 65
ch2_mac_rx_max_frame_size 65
ch2_mac_enforce_max_frame_size DISABLE
ch2_mac_tx_preamble_passthrough DISABLE
ch2_mac_rx_preamble_passthrough DISABLE
ch2_mac_strict_preamble_checking DISABLE
ch2_mac_strict_sfd_checking DISABLE
ch2_mac_tx_ipg_size 12
ch2_mac_ipg_removed_per_am_period 0
ch2_mac_custom_cadence DISABLE
ch2_ptp0_en DISABLED
ch2_ptp1_en DISABLED
ch2_mac_sim_mode ENABLE
ch2_ptp0_sim_mode ENABLE
ch2_ptp1_sim_mode ENABLE
ch2_mac_tx_mac_data_flow DISABLE
ch2_mac_sf_en DISABLED
ch2_ehip_loopback_mode NO_LOOPBACK
ch2_mac_txmac_saddr 001122334455
ch2_pldif_tx_fifo_mode PHASE_COMP
ch2_pldif_tx_fifo_width DOUBLE_WIDTH
ch2_pldif_rx_fifo_mode PHASE_COMP
ch2_pldif_rx_fifo_width DOUBLE_WIDTH
ch2_pldif_tx_clkout1_divider DIV2
ch2_pldif_tx_clkout2_divider DIV2
ch2_pldif_rx_clkout1_divider DIV2
ch2_pldif_rx_clkout2_divider DIV2
ch2_pldif_channel_identifier GENERIC
ch2_pldif_sf_en ENABLED
ch2_pldif_loopback_mode NO_LOOPBACK
ch2_pcs_loopback_mode NO_LOOPBACK
ch2_pcs_sf_en ENABLED
ch2_fec_spec DISABLED
ch2_fec_fracture UNUSED
ch2_fec_tx_en FALSE
ch2_fec_rx_en FALSE
ch2_fec_loopback_mode DISABLE
ch2_tx_pll_frac_mode_en DISABLE
ch2_rx_invert_pin DISABLE
ch2_tx_invert_pin DISABLE
ch2_xcvr_rx_cdrdivout_en DISABLE
ch2_xcvr_tx_eq_main_tap 52
ch2_xcvr_tx_eq_post_tap_1 5
ch2_xcvr_tx_eq_pre_tap_1 0
ch2_xcvr_tx_eq_pre_tap_2 0
ch2_tx_pll_feed_forward_gain 197
ch2_xcvr_rx_termination_mode GROUNDED
ch2_xcvr_rx_onchip_termination_setting R_2
ch2_xcvr_rx_eq_vga_gain 0
ch2_xcvr_x_eq_hf_boost 0
ch2_xcvr_rx_eq_dfe_tap_1 0
ch2_xcvr_rx_external_couple_type AC
ch2_sequencer_reg_en DISABLE
ch2_rx_dl_rx_lat_bit_for_async 0
ch2_rx_dl_rxbit_rollover 0
ch2_rx_dl_rxbit_cntr_pma DISABLE
ch2_hw_fec 0
CH2_SRC_TX_ENABLE 1
CH2_SRC_RX_ENABLE 1
CH2_SRC_TX_INITIATOR 0
CH2_SRC_RX_INITIATOR 0
CH2_SRC_TX_INITIATOR_INDEX 0
CH2_SRC_RX_INITIATOR_INDEX 0
CH2_SRC_TX_TARGET_ENABLE 0
CH2_SRC_RX_TARGET_ENABLE 0
CH2_SRC_TX_LANE_FUCTIONAL_MODE 3
CH2_SRC_RX_LANE_FUCTIONAL_MODE 3
CH2_SRC_NON_PTP_CHANNEL 1
CH2_SRC_TX_PCS_EN 1
CH2_SRC_RX_PCS_EN 1
CH2_SRC_UX_EN 1
CH2_SRC_TX_DL_EN 0
CH2_SRC_RX_DL_EN 0
CH2_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH2_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH2_SRC_PTP_EN 0
CH2_SRC_TX_FEC_EN 0
CH2_SRC_RX_FEC_EN 0
CH2_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH2_SRC_UX_USING_SYSPLL_CLK 0
CH2_SRC_FLUX_USING_SYSPLL_CLK 0
CH2_SRC_FLUX_EN 0
CH2_SRC_FLUX_EN_HW 1
CH2_SRC_SRC_LANE_INDEX 2
CH2_SRC_LEADER_LANE 0
ch3_lane_id 3
ch3_tx_channel_mode PCSD
ch3_rx_channel_mode PCSD
ch3_duplex_mode DUPLEX
ch3_rate_mode RATE_25G
ch3_ptp_mode DISABLED
ch3_fec_mode 0
ch3_tx_dl_enable DISABLE
ch3_rx_dl_enable DISABLE
ch3_sup_mode USER_MODE
ch3_sim_mode ENABLE
ch3_syspll_rx_clk_hz 322265625
ch3_syspll_tx_clk_hz 322265625
ch3_tx_user1_clk_dynamic_mux PLL_C0
ch3_tx_user2_clk_dynamic_mux DISABLED
ch3_rx_user1_clk_dynamic_mux PLL_C0
ch3_rx_user2_clk_dynamic_mux DISABLED
ch3_tx_bond_size 4
ch3_rx_bond_size 1
ch3_xcvr_tx_protocol_hint DISABLED
ch3_xcvr_tx_datarate_bps 1105.92
ch3_xcvr_tx_prbs_pattern DISABLE
ch3_xcvr_tx_user_clk_only_mode DISABLE
ch3_xcvr_tx_width 32
ch3_xcvr_rx_protocol_hint DISABLED
ch3_xcvr_rx_datarate_bps 1105.92
ch3_xcvr_rx_prbs_pattern DISABLE
ch3_xcvr_rx_width 32
ch3_xcvr_rx_force_cdr_ltr FALSE
ch3_xcvr_rx_adaptation_mode DISABLED
ch3_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch3_xcvr_cdr_f_ref_hz 184320000
ch3_xcvr_cdr_f_vco_hz 552960000
ch3_rx_postdiv_clk_en ENABLE
ch3_rx_postdiv_clk_divider 100
ch3_tx_postdiv_clk_divider 100
ch3_tx_pll_f_ref_hz 184320000
ch3_tx_pll_f_out_hz 552960000
ch3_tx_pll_refclk_select GLOBAL_REFCLK0
ch3_cdr_refclk_select GLOBAL_REFCLK1
ch3_phy_loopback_mode DISABLED
ch3_flux_mode FLUX_MODE_BYPASS
ch3_flux_mode_hw FLUX_MODE_SNIFFER
ch3_xcvrif_tx_fifo_mode ELASTIC
ch3_xcvrif_rx_fifo_mode ELASTIC
ch3_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch3_xcvr_tx_spread_spectrum_en DISABLE
ch3_xcvr_tx_cascade_en DISABLE
ch3_tx_pcs_mode IEEE
ch3_rx_pcs_mode IEEE
ch3_mac_link_fault_mode OFF
ch3_mac_remove_pads DISABLE
ch3_mac_keep_rx_crc DISABLE
ch3_mac_forward_rx_pause_requests DISABLE
ch3_mac_source_address_insertion DISABLE
ch3_mac_tx_vlan_detection DISABLE
ch3_mac_rx_vlan_detection DISABLE
ch3_mac_flow_control DISABLE FLOW CONTROL
ch3_mac_tx_max_frame_size 65
ch3_mac_rx_max_frame_size 65
ch3_mac_enforce_max_frame_size DISABLE
ch3_mac_tx_preamble_passthrough DISABLE
ch3_mac_rx_preamble_passthrough DISABLE
ch3_mac_strict_preamble_checking DISABLE
ch3_mac_strict_sfd_checking DISABLE
ch3_mac_tx_ipg_size 12
ch3_mac_ipg_removed_per_am_period 0
ch3_mac_custom_cadence DISABLE
ch3_ptp0_en DISABLED
ch3_ptp1_en DISABLED
ch3_mac_sim_mode ENABLE
ch3_ptp0_sim_mode ENABLE
ch3_ptp1_sim_mode ENABLE
ch3_mac_tx_mac_data_flow DISABLE
ch3_mac_sf_en DISABLED
ch3_ehip_loopback_mode NO_LOOPBACK
ch3_mac_txmac_saddr 001122334455
ch3_pldif_tx_fifo_mode PHASE_COMP
ch3_pldif_tx_fifo_width DOUBLE_WIDTH
ch3_pldif_rx_fifo_mode PHASE_COMP
ch3_pldif_rx_fifo_width DOUBLE_WIDTH
ch3_pldif_tx_clkout1_divider DIV2
ch3_pldif_tx_clkout2_divider DIV2
ch3_pldif_rx_clkout1_divider DIV2
ch3_pldif_rx_clkout2_divider DIV2
ch3_pldif_channel_identifier GENERIC
ch3_pldif_sf_en ENABLED
ch3_pldif_loopback_mode NO_LOOPBACK
ch3_pcs_loopback_mode NO_LOOPBACK
ch3_pcs_sf_en ENABLED
ch3_fec_spec DISABLED
ch3_fec_fracture UNUSED
ch3_fec_tx_en FALSE
ch3_fec_rx_en FALSE
ch3_fec_loopback_mode DISABLE
ch3_tx_pll_frac_mode_en DISABLE
ch3_rx_invert_pin DISABLE
ch3_tx_invert_pin DISABLE
ch3_xcvr_rx_cdrdivout_en DISABLE
ch3_xcvr_tx_eq_main_tap 52
ch3_xcvr_tx_eq_post_tap_1 5
ch3_xcvr_tx_eq_pre_tap_1 0
ch3_xcvr_tx_eq_pre_tap_2 0
ch3_tx_pll_feed_forward_gain 197
ch3_xcvr_rx_termination_mode GROUNDED
ch3_xcvr_rx_onchip_termination_setting R_2
ch3_xcvr_rx_eq_vga_gain 0
ch3_xcvr_x_eq_hf_boost 0
ch3_xcvr_rx_eq_dfe_tap_1 0
ch3_xcvr_rx_external_couple_type AC
ch3_sequencer_reg_en DISABLE
ch3_rx_dl_rx_lat_bit_for_async 0
ch3_rx_dl_rxbit_rollover 0
ch3_rx_dl_rxbit_cntr_pma DISABLE
ch3_hw_fec 0
CH3_SRC_TX_ENABLE 1
CH3_SRC_RX_ENABLE 1
CH3_SRC_TX_INITIATOR 0
CH3_SRC_RX_INITIATOR 0
CH3_SRC_TX_INITIATOR_INDEX 0
CH3_SRC_RX_INITIATOR_INDEX 0
CH3_SRC_TX_TARGET_ENABLE 0
CH3_SRC_RX_TARGET_ENABLE 0
CH3_SRC_TX_LANE_FUCTIONAL_MODE 3
CH3_SRC_RX_LANE_FUCTIONAL_MODE 3
CH3_SRC_NON_PTP_CHANNEL 1
CH3_SRC_TX_PCS_EN 1
CH3_SRC_RX_PCS_EN 1
CH3_SRC_UX_EN 1
CH3_SRC_TX_DL_EN 0
CH3_SRC_RX_DL_EN 0
CH3_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH3_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH3_SRC_PTP_EN 0
CH3_SRC_TX_FEC_EN 0
CH3_SRC_RX_FEC_EN 0
CH3_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH3_SRC_UX_USING_SYSPLL_CLK 0
CH3_SRC_FLUX_USING_SYSPLL_CLK 0
CH3_SRC_FLUX_EN 0
CH3_SRC_FLUX_EN_HW 1
CH3_SRC_SRC_LANE_INDEX 3
CH3_SRC_LEADER_LANE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper

n_channel_superset v21.0.0


Parameters

num_of_lanes 4
dr_enable DR_ENABLED
SRC_SIM_SCALE_DOWN 0
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch0_lane_id 0
ch0_tx_channel_mode PCSD
ch0_rx_channel_mode PCSD
ch0_duplex_mode DUPLEX
ch0_rate_mode RATE_25G
ch0_ptp_mode DISABLED
ch0_fec_mode 0
ch0_tx_dl_enable DISABLE
ch0_rx_dl_enable DISABLE
ch0_sup_mode USER_MODE
ch0_sim_mode ENABLE
ch0_syspll_rx_clk_hz 322265625
ch0_syspll_tx_clk_hz 322265625
ch0_tx_user1_clk_dynamic_mux PLL_C0
ch0_tx_user2_clk_dynamic_mux DISABLED
ch0_rx_user1_clk_dynamic_mux PLL_C0
ch0_rx_user2_clk_dynamic_mux DISABLED
ch0_tx_bond_size 4
ch0_rx_bond_size 1
ch0_xcvr_tx_protocol_hint DISABLED
ch0_xcvr_tx_datarate_bps 1105.92
ch0_xcvr_tx_prbs_pattern DISABLE
ch0_xcvr_tx_user_clk_only_mode DISABLE
ch0_xcvr_tx_width 32
ch0_xcvr_rx_protocol_hint DISABLED
ch0_xcvr_rx_datarate_bps 1105.92
ch0_xcvr_rx_prbs_pattern DISABLE
ch0_xcvr_rx_width 32
ch0_xcvr_rx_force_cdr_ltr FALSE
ch0_xcvr_rx_adaptation_mode DISABLED
ch0_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch0_xcvr_cdr_f_ref_hz 184320000
ch0_xcvr_cdr_f_vco_hz 552960000
ch0_rx_postdiv_clk_en ENABLE
ch0_rx_postdiv_clk_divider 100
ch0_tx_postdiv_clk_divider 100
ch0_tx_pll_f_ref_hz 184320000
ch0_tx_pll_f_out_hz 552960000
ch0_tx_pll_refclk_select GLOBAL_REFCLK0
ch0_cdr_refclk_select GLOBAL_REFCLK1
ch0_phy_loopback_mode DISABLED
ch0_flux_mode FLUX_MODE_BYPASS
ch0_flux_mode_hw FLUX_MODE_SNIFFER
ch0_xcvrif_tx_fifo_mode ELASTIC
ch0_xcvrif_rx_fifo_mode ELASTIC
ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch0_xcvr_tx_spread_spectrum_en DISABLE
ch0_xcvr_tx_cascade_en DISABLE
ch0_tx_pcs_mode IEEE
ch0_rx_pcs_mode IEEE
ch0_mac_link_fault_mode OFF
ch0_mac_remove_pads DISABLE
ch0_mac_keep_rx_crc DISABLE
ch0_mac_forward_rx_pause_requests DISABLE
ch0_mac_source_address_insertion DISABLE
ch0_mac_tx_vlan_detection DISABLE
ch0_mac_rx_vlan_detection DISABLE
ch0_mac_flow_control DISABLE FLOW CONTROL
ch0_mac_tx_max_frame_size 65
ch0_mac_rx_max_frame_size 65
ch0_mac_enforce_max_frame_size DISABLE
ch0_mac_tx_preamble_passthrough DISABLE
ch0_mac_rx_preamble_passthrough DISABLE
ch0_mac_strict_preamble_checking DISABLE
ch0_mac_strict_sfd_checking DISABLE
ch0_mac_tx_ipg_size 12
ch0_mac_ipg_removed_per_am_period 0
ch0_mac_custom_cadence DISABLE
ch0_ptp0_en DISABLED
ch0_ptp1_en DISABLED
ch0_mac_sim_mode ENABLE
ch0_ptp0_sim_mode ENABLE
ch0_ptp1_sim_mode ENABLE
ch0_mac_tx_mac_data_flow DISABLE
ch0_mac_sf_en DISABLED
ch0_ehip_loopback_mode NO_LOOPBACK
ch0_mac_txmac_saddr 001122334455
ch0_pldif_tx_fifo_mode PHASE_COMP
ch0_pldif_tx_fifo_width DOUBLE_WIDTH
ch0_pldif_rx_fifo_mode PHASE_COMP
ch0_pldif_rx_fifo_width DOUBLE_WIDTH
ch0_pldif_tx_clkout1_divider DIV2
ch0_pldif_tx_clkout2_divider DIV2
ch0_pldif_rx_clkout1_divider DIV2
ch0_pldif_rx_clkout2_divider DIV2
ch0_pldif_channel_identifier GENERIC
ch0_pldif_sf_en ENABLED
ch0_pldif_loopback_mode NO_LOOPBACK
ch0_pcs_loopback_mode NO_LOOPBACK
ch0_pcs_sf_en ENABLED
ch0_fec_spec DISABLED
ch0_fec_fracture UNUSED
ch0_fec_tx_en FALSE
ch0_fec_rx_en FALSE
ch0_fec_loopback_mode DISABLE
ch0_tx_pll_frac_mode_en DISABLE
ch0_rx_invert_pin DISABLE
ch0_tx_invert_pin DISABLE
ch0_xcvr_rx_cdrdivout_en DISABLE
ch0_xcvr_tx_eq_main_tap 52
ch0_xcvr_tx_eq_post_tap_1 5
ch0_xcvr_tx_eq_pre_tap_1 0
ch0_xcvr_tx_eq_pre_tap_2 0
ch0_tx_pll_feed_forward_gain 197
ch0_xcvr_rx_termination_mode GROUNDED
ch0_xcvr_rx_onchip_termination_setting R_2
ch0_xcvr_rx_eq_vga_gain 0
ch0_xcvr_x_eq_hf_boost 0
ch0_xcvr_rx_eq_dfe_tap_1 0
ch0_xcvr_rx_external_couple_type AC
ch0_sequencer_reg_en DISABLE
ch0_rx_dl_rx_lat_bit_for_async 0
ch0_rx_dl_rxbit_rollover 0
ch0_rx_dl_rxbit_cntr_pma DISABLE
ch0_hw_fec 0
CH0_SRC_TX_ENABLE 1
CH0_SRC_RX_ENABLE 1
CH0_SRC_TX_INITIATOR 1
CH0_SRC_RX_INITIATOR 1
CH0_SRC_TX_INITIATOR_INDEX 0
CH0_SRC_RX_INITIATOR_INDEX 0
CH0_SRC_TX_TARGET_ENABLE 14
CH0_SRC_RX_TARGET_ENABLE 14
CH0_SRC_TX_LANE_FUCTIONAL_MODE 3
CH0_SRC_RX_LANE_FUCTIONAL_MODE 3
CH0_SRC_NON_PTP_CHANNEL 1
CH0_SRC_TX_PCS_EN 1
CH0_SRC_RX_PCS_EN 1
CH0_SRC_UX_EN 1
CH0_SRC_TX_DL_EN 0
CH0_SRC_RX_DL_EN 0
CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH0_SRC_PTP_EN 0
CH0_SRC_TX_FEC_EN 0
CH0_SRC_RX_FEC_EN 0
CH0_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH0_SRC_UX_USING_SYSPLL_CLK 0
CH0_SRC_FLUX_USING_SYSPLL_CLK 0
CH0_SRC_FLUX_EN 0
CH0_SRC_FLUX_EN_HW 1
CH0_SRC_SRC_LANE_INDEX 0
CH0_SRC_LEADER_LANE 1
ch1_lane_id 1
ch1_tx_channel_mode PCSD
ch1_rx_channel_mode PCSD
ch1_duplex_mode DUPLEX
ch1_rate_mode RATE_25G
ch1_ptp_mode DISABLED
ch1_fec_mode 0
ch1_tx_dl_enable DISABLE
ch1_rx_dl_enable DISABLE
ch1_sup_mode USER_MODE
ch1_sim_mode ENABLE
ch1_syspll_rx_clk_hz 322265625
ch1_syspll_tx_clk_hz 322265625
ch1_tx_user1_clk_dynamic_mux PLL_C0
ch1_tx_user2_clk_dynamic_mux DISABLED
ch1_rx_user1_clk_dynamic_mux PLL_C0
ch1_rx_user2_clk_dynamic_mux DISABLED
ch1_tx_bond_size 4
ch1_rx_bond_size 1
ch1_xcvr_tx_protocol_hint DISABLED
ch1_xcvr_tx_datarate_bps 1105.92
ch1_xcvr_tx_prbs_pattern DISABLE
ch1_xcvr_tx_user_clk_only_mode DISABLE
ch1_xcvr_tx_width 32
ch1_xcvr_rx_protocol_hint DISABLED
ch1_xcvr_rx_datarate_bps 1105.92
ch1_xcvr_rx_prbs_pattern DISABLE
ch1_xcvr_rx_width 32
ch1_xcvr_rx_force_cdr_ltr FALSE
ch1_xcvr_rx_adaptation_mode DISABLED
ch1_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch1_xcvr_cdr_f_ref_hz 184320000
ch1_xcvr_cdr_f_vco_hz 552960000
ch1_rx_postdiv_clk_en ENABLE
ch1_rx_postdiv_clk_divider 100
ch1_tx_postdiv_clk_divider 100
ch1_tx_pll_f_ref_hz 184320000
ch1_tx_pll_f_out_hz 552960000
ch1_tx_pll_refclk_select GLOBAL_REFCLK0
ch1_cdr_refclk_select GLOBAL_REFCLK1
ch1_phy_loopback_mode DISABLED
ch1_flux_mode FLUX_MODE_BYPASS
ch1_flux_mode_hw FLUX_MODE_SNIFFER
ch1_xcvrif_tx_fifo_mode ELASTIC
ch1_xcvrif_rx_fifo_mode ELASTIC
ch1_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch1_xcvr_tx_spread_spectrum_en DISABLE
ch1_xcvr_tx_cascade_en DISABLE
ch1_tx_pcs_mode IEEE
ch1_rx_pcs_mode IEEE
ch1_mac_link_fault_mode OFF
ch1_mac_remove_pads DISABLE
ch1_mac_keep_rx_crc DISABLE
ch1_mac_forward_rx_pause_requests DISABLE
ch1_mac_source_address_insertion DISABLE
ch1_mac_tx_vlan_detection DISABLE
ch1_mac_rx_vlan_detection DISABLE
ch1_mac_flow_control DISABLE FLOW CONTROL
ch1_mac_tx_max_frame_size 65
ch1_mac_rx_max_frame_size 65
ch1_mac_enforce_max_frame_size DISABLE
ch1_mac_tx_preamble_passthrough DISABLE
ch1_mac_rx_preamble_passthrough DISABLE
ch1_mac_strict_preamble_checking DISABLE
ch1_mac_strict_sfd_checking DISABLE
ch1_mac_tx_ipg_size 12
ch1_mac_ipg_removed_per_am_period 0
ch1_mac_custom_cadence DISABLE
ch1_ptp0_en DISABLED
ch1_ptp1_en DISABLED
ch1_mac_sim_mode ENABLE
ch1_ptp0_sim_mode ENABLE
ch1_ptp1_sim_mode ENABLE
ch1_mac_tx_mac_data_flow DISABLE
ch1_mac_sf_en DISABLED
ch1_ehip_loopback_mode NO_LOOPBACK
ch1_mac_txmac_saddr 001122334455
ch1_pldif_tx_fifo_mode PHASE_COMP
ch1_pldif_tx_fifo_width DOUBLE_WIDTH
ch1_pldif_rx_fifo_mode PHASE_COMP
ch1_pldif_rx_fifo_width DOUBLE_WIDTH
ch1_pldif_tx_clkout1_divider DIV2
ch1_pldif_tx_clkout2_divider DIV2
ch1_pldif_rx_clkout1_divider DIV2
ch1_pldif_rx_clkout2_divider DIV2
ch1_pldif_channel_identifier GENERIC
ch1_pldif_sf_en ENABLED
ch1_pldif_loopback_mode NO_LOOPBACK
ch1_pcs_loopback_mode NO_LOOPBACK
ch1_pcs_sf_en ENABLED
ch1_fec_spec DISABLED
ch1_fec_fracture UNUSED
ch1_fec_tx_en FALSE
ch1_fec_rx_en FALSE
ch1_fec_loopback_mode DISABLE
ch1_tx_pll_frac_mode_en DISABLE
ch1_rx_invert_pin DISABLE
ch1_tx_invert_pin DISABLE
ch1_xcvr_rx_cdrdivout_en DISABLE
ch1_xcvr_tx_eq_main_tap 52
ch1_xcvr_tx_eq_post_tap_1 5
ch1_xcvr_tx_eq_pre_tap_1 0
ch1_xcvr_tx_eq_pre_tap_2 0
ch1_tx_pll_feed_forward_gain 197
ch1_xcvr_rx_termination_mode GROUNDED
ch1_xcvr_rx_onchip_termination_setting R_2
ch1_xcvr_rx_eq_vga_gain 0
ch1_xcvr_x_eq_hf_boost 0
ch1_xcvr_rx_eq_dfe_tap_1 0
ch1_xcvr_rx_external_couple_type AC
ch1_sequencer_reg_en DISABLE
ch1_rx_dl_rx_lat_bit_for_async 0
ch1_rx_dl_rxbit_rollover 0
ch1_rx_dl_rxbit_cntr_pma DISABLE
ch1_hw_fec 0
CH1_SRC_TX_ENABLE 1
CH1_SRC_RX_ENABLE 1
CH1_SRC_TX_INITIATOR 0
CH1_SRC_RX_INITIATOR 0
CH1_SRC_TX_INITIATOR_INDEX 0
CH1_SRC_RX_INITIATOR_INDEX 0
CH1_SRC_TX_TARGET_ENABLE 0
CH1_SRC_RX_TARGET_ENABLE 0
CH1_SRC_TX_LANE_FUCTIONAL_MODE 3
CH1_SRC_RX_LANE_FUCTIONAL_MODE 3
CH1_SRC_NON_PTP_CHANNEL 1
CH1_SRC_TX_PCS_EN 1
CH1_SRC_RX_PCS_EN 1
CH1_SRC_UX_EN 1
CH1_SRC_TX_DL_EN 0
CH1_SRC_RX_DL_EN 0
CH1_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH1_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH1_SRC_PTP_EN 0
CH1_SRC_TX_FEC_EN 0
CH1_SRC_RX_FEC_EN 0
CH1_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH1_SRC_UX_USING_SYSPLL_CLK 0
CH1_SRC_FLUX_USING_SYSPLL_CLK 0
CH1_SRC_FLUX_EN 0
CH1_SRC_FLUX_EN_HW 1
CH1_SRC_SRC_LANE_INDEX 1
CH1_SRC_LEADER_LANE 0
ch2_lane_id 2
ch2_tx_channel_mode PCSD
ch2_rx_channel_mode PCSD
ch2_duplex_mode DUPLEX
ch2_rate_mode RATE_25G
ch2_ptp_mode DISABLED
ch2_fec_mode 0
ch2_tx_dl_enable DISABLE
ch2_rx_dl_enable DISABLE
ch2_sup_mode USER_MODE
ch2_sim_mode ENABLE
ch2_syspll_rx_clk_hz 322265625
ch2_syspll_tx_clk_hz 322265625
ch2_tx_user1_clk_dynamic_mux PLL_C0
ch2_tx_user2_clk_dynamic_mux DISABLED
ch2_rx_user1_clk_dynamic_mux PLL_C0
ch2_rx_user2_clk_dynamic_mux DISABLED
ch2_tx_bond_size 4
ch2_rx_bond_size 1
ch2_xcvr_tx_protocol_hint DISABLED
ch2_xcvr_tx_datarate_bps 1105.92
ch2_xcvr_tx_prbs_pattern DISABLE
ch2_xcvr_tx_user_clk_only_mode DISABLE
ch2_xcvr_tx_width 32
ch2_xcvr_rx_protocol_hint DISABLED
ch2_xcvr_rx_datarate_bps 1105.92
ch2_xcvr_rx_prbs_pattern DISABLE
ch2_xcvr_rx_width 32
ch2_xcvr_rx_force_cdr_ltr FALSE
ch2_xcvr_rx_adaptation_mode DISABLED
ch2_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch2_xcvr_cdr_f_ref_hz 184320000
ch2_xcvr_cdr_f_vco_hz 552960000
ch2_rx_postdiv_clk_en ENABLE
ch2_rx_postdiv_clk_divider 100
ch2_tx_postdiv_clk_divider 100
ch2_tx_pll_f_ref_hz 184320000
ch2_tx_pll_f_out_hz 552960000
ch2_tx_pll_refclk_select GLOBAL_REFCLK0
ch2_cdr_refclk_select GLOBAL_REFCLK1
ch2_phy_loopback_mode DISABLED
ch2_flux_mode FLUX_MODE_BYPASS
ch2_flux_mode_hw FLUX_MODE_SNIFFER
ch2_xcvrif_tx_fifo_mode ELASTIC
ch2_xcvrif_rx_fifo_mode ELASTIC
ch2_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch2_xcvr_tx_spread_spectrum_en DISABLE
ch2_xcvr_tx_cascade_en DISABLE
ch2_tx_pcs_mode IEEE
ch2_rx_pcs_mode IEEE
ch2_mac_link_fault_mode OFF
ch2_mac_remove_pads DISABLE
ch2_mac_keep_rx_crc DISABLE
ch2_mac_forward_rx_pause_requests DISABLE
ch2_mac_source_address_insertion DISABLE
ch2_mac_tx_vlan_detection DISABLE
ch2_mac_rx_vlan_detection DISABLE
ch2_mac_flow_control DISABLE FLOW CONTROL
ch2_mac_tx_max_frame_size 65
ch2_mac_rx_max_frame_size 65
ch2_mac_enforce_max_frame_size DISABLE
ch2_mac_tx_preamble_passthrough DISABLE
ch2_mac_rx_preamble_passthrough DISABLE
ch2_mac_strict_preamble_checking DISABLE
ch2_mac_strict_sfd_checking DISABLE
ch2_mac_tx_ipg_size 12
ch2_mac_ipg_removed_per_am_period 0
ch2_mac_custom_cadence DISABLE
ch2_ptp0_en DISABLED
ch2_ptp1_en DISABLED
ch2_mac_sim_mode ENABLE
ch2_ptp0_sim_mode ENABLE
ch2_ptp1_sim_mode ENABLE
ch2_mac_tx_mac_data_flow DISABLE
ch2_mac_sf_en DISABLED
ch2_ehip_loopback_mode NO_LOOPBACK
ch2_mac_txmac_saddr 001122334455
ch2_pldif_tx_fifo_mode PHASE_COMP
ch2_pldif_tx_fifo_width DOUBLE_WIDTH
ch2_pldif_rx_fifo_mode PHASE_COMP
ch2_pldif_rx_fifo_width DOUBLE_WIDTH
ch2_pldif_tx_clkout1_divider DIV2
ch2_pldif_tx_clkout2_divider DIV2
ch2_pldif_rx_clkout1_divider DIV2
ch2_pldif_rx_clkout2_divider DIV2
ch2_pldif_channel_identifier GENERIC
ch2_pldif_sf_en ENABLED
ch2_pldif_loopback_mode NO_LOOPBACK
ch2_pcs_loopback_mode NO_LOOPBACK
ch2_pcs_sf_en ENABLED
ch2_fec_spec DISABLED
ch2_fec_fracture UNUSED
ch2_fec_tx_en FALSE
ch2_fec_rx_en FALSE
ch2_fec_loopback_mode DISABLE
ch2_tx_pll_frac_mode_en DISABLE
ch2_rx_invert_pin DISABLE
ch2_tx_invert_pin DISABLE
ch2_xcvr_rx_cdrdivout_en DISABLE
ch2_xcvr_tx_eq_main_tap 52
ch2_xcvr_tx_eq_post_tap_1 5
ch2_xcvr_tx_eq_pre_tap_1 0
ch2_xcvr_tx_eq_pre_tap_2 0
ch2_tx_pll_feed_forward_gain 197
ch2_xcvr_rx_termination_mode GROUNDED
ch2_xcvr_rx_onchip_termination_setting R_2
ch2_xcvr_rx_eq_vga_gain 0
ch2_xcvr_x_eq_hf_boost 0
ch2_xcvr_rx_eq_dfe_tap_1 0
ch2_xcvr_rx_external_couple_type AC
ch2_sequencer_reg_en DISABLE
ch2_rx_dl_rx_lat_bit_for_async 0
ch2_rx_dl_rxbit_rollover 0
ch2_rx_dl_rxbit_cntr_pma DISABLE
ch2_hw_fec 0
CH2_SRC_TX_ENABLE 1
CH2_SRC_RX_ENABLE 1
CH2_SRC_TX_INITIATOR 0
CH2_SRC_RX_INITIATOR 0
CH2_SRC_TX_INITIATOR_INDEX 0
CH2_SRC_RX_INITIATOR_INDEX 0
CH2_SRC_TX_TARGET_ENABLE 0
CH2_SRC_RX_TARGET_ENABLE 0
CH2_SRC_TX_LANE_FUCTIONAL_MODE 3
CH2_SRC_RX_LANE_FUCTIONAL_MODE 3
CH2_SRC_NON_PTP_CHANNEL 1
CH2_SRC_TX_PCS_EN 1
CH2_SRC_RX_PCS_EN 1
CH2_SRC_UX_EN 1
CH2_SRC_TX_DL_EN 0
CH2_SRC_RX_DL_EN 0
CH2_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH2_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH2_SRC_PTP_EN 0
CH2_SRC_TX_FEC_EN 0
CH2_SRC_RX_FEC_EN 0
CH2_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH2_SRC_UX_USING_SYSPLL_CLK 0
CH2_SRC_FLUX_USING_SYSPLL_CLK 0
CH2_SRC_FLUX_EN 0
CH2_SRC_FLUX_EN_HW 1
CH2_SRC_SRC_LANE_INDEX 2
CH2_SRC_LEADER_LANE 0
ch3_lane_id 3
ch3_tx_channel_mode PCSD
ch3_rx_channel_mode PCSD
ch3_duplex_mode DUPLEX
ch3_rate_mode RATE_25G
ch3_ptp_mode DISABLED
ch3_fec_mode 0
ch3_tx_dl_enable DISABLE
ch3_rx_dl_enable DISABLE
ch3_sup_mode USER_MODE
ch3_sim_mode ENABLE
ch3_syspll_rx_clk_hz 322265625
ch3_syspll_tx_clk_hz 322265625
ch3_tx_user1_clk_dynamic_mux PLL_C0
ch3_tx_user2_clk_dynamic_mux DISABLED
ch3_rx_user1_clk_dynamic_mux PLL_C0
ch3_rx_user2_clk_dynamic_mux DISABLED
ch3_tx_bond_size 4
ch3_rx_bond_size 1
ch3_xcvr_tx_protocol_hint DISABLED
ch3_xcvr_tx_datarate_bps 1105.92
ch3_xcvr_tx_prbs_pattern DISABLE
ch3_xcvr_tx_user_clk_only_mode DISABLE
ch3_xcvr_tx_width 32
ch3_xcvr_rx_protocol_hint DISABLED
ch3_xcvr_rx_datarate_bps 1105.92
ch3_xcvr_rx_prbs_pattern DISABLE
ch3_xcvr_rx_width 32
ch3_xcvr_rx_force_cdr_ltr FALSE
ch3_xcvr_rx_adaptation_mode DISABLED
ch3_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch3_xcvr_cdr_f_ref_hz 184320000
ch3_xcvr_cdr_f_vco_hz 552960000
ch3_rx_postdiv_clk_en ENABLE
ch3_rx_postdiv_clk_divider 100
ch3_tx_postdiv_clk_divider 100
ch3_tx_pll_f_ref_hz 184320000
ch3_tx_pll_f_out_hz 552960000
ch3_tx_pll_refclk_select GLOBAL_REFCLK0
ch3_cdr_refclk_select GLOBAL_REFCLK1
ch3_phy_loopback_mode DISABLED
ch3_flux_mode FLUX_MODE_BYPASS
ch3_flux_mode_hw FLUX_MODE_SNIFFER
ch3_xcvrif_tx_fifo_mode ELASTIC
ch3_xcvrif_rx_fifo_mode ELASTIC
ch3_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch3_xcvr_tx_spread_spectrum_en DISABLE
ch3_xcvr_tx_cascade_en DISABLE
ch3_tx_pcs_mode IEEE
ch3_rx_pcs_mode IEEE
ch3_mac_link_fault_mode OFF
ch3_mac_remove_pads DISABLE
ch3_mac_keep_rx_crc DISABLE
ch3_mac_forward_rx_pause_requests DISABLE
ch3_mac_source_address_insertion DISABLE
ch3_mac_tx_vlan_detection DISABLE
ch3_mac_rx_vlan_detection DISABLE
ch3_mac_flow_control DISABLE FLOW CONTROL
ch3_mac_tx_max_frame_size 65
ch3_mac_rx_max_frame_size 65
ch3_mac_enforce_max_frame_size DISABLE
ch3_mac_tx_preamble_passthrough DISABLE
ch3_mac_rx_preamble_passthrough DISABLE
ch3_mac_strict_preamble_checking DISABLE
ch3_mac_strict_sfd_checking DISABLE
ch3_mac_tx_ipg_size 12
ch3_mac_ipg_removed_per_am_period 0
ch3_mac_custom_cadence DISABLE
ch3_ptp0_en DISABLED
ch3_ptp1_en DISABLED
ch3_mac_sim_mode ENABLE
ch3_ptp0_sim_mode ENABLE
ch3_ptp1_sim_mode ENABLE
ch3_mac_tx_mac_data_flow DISABLE
ch3_mac_sf_en DISABLED
ch3_ehip_loopback_mode NO_LOOPBACK
ch3_mac_txmac_saddr 001122334455
ch3_pldif_tx_fifo_mode PHASE_COMP
ch3_pldif_tx_fifo_width DOUBLE_WIDTH
ch3_pldif_rx_fifo_mode PHASE_COMP
ch3_pldif_rx_fifo_width DOUBLE_WIDTH
ch3_pldif_tx_clkout1_divider DIV2
ch3_pldif_tx_clkout2_divider DIV2
ch3_pldif_rx_clkout1_divider DIV2
ch3_pldif_rx_clkout2_divider DIV2
ch3_pldif_channel_identifier GENERIC
ch3_pldif_sf_en ENABLED
ch3_pldif_loopback_mode NO_LOOPBACK
ch3_pcs_loopback_mode NO_LOOPBACK
ch3_pcs_sf_en ENABLED
ch3_fec_spec DISABLED
ch3_fec_fracture UNUSED
ch3_fec_tx_en FALSE
ch3_fec_rx_en FALSE
ch3_fec_loopback_mode DISABLE
ch3_tx_pll_frac_mode_en DISABLE
ch3_rx_invert_pin DISABLE
ch3_tx_invert_pin DISABLE
ch3_xcvr_rx_cdrdivout_en DISABLE
ch3_xcvr_tx_eq_main_tap 52
ch3_xcvr_tx_eq_post_tap_1 5
ch3_xcvr_tx_eq_pre_tap_1 0
ch3_xcvr_tx_eq_pre_tap_2 0
ch3_tx_pll_feed_forward_gain 197
ch3_xcvr_rx_termination_mode GROUNDED
ch3_xcvr_rx_onchip_termination_setting R_2
ch3_xcvr_rx_eq_vga_gain 0
ch3_xcvr_x_eq_hf_boost 0
ch3_xcvr_rx_eq_dfe_tap_1 0
ch3_xcvr_rx_external_couple_type AC
ch3_sequencer_reg_en DISABLE
ch3_rx_dl_rx_lat_bit_for_async 0
ch3_rx_dl_rxbit_rollover 0
ch3_rx_dl_rxbit_cntr_pma DISABLE
ch3_hw_fec 0
CH3_SRC_TX_ENABLE 1
CH3_SRC_RX_ENABLE 1
CH3_SRC_TX_INITIATOR 0
CH3_SRC_RX_INITIATOR 0
CH3_SRC_TX_INITIATOR_INDEX 0
CH3_SRC_RX_INITIATOR_INDEX 0
CH3_SRC_TX_TARGET_ENABLE 0
CH3_SRC_RX_TARGET_ENABLE 0
CH3_SRC_TX_LANE_FUCTIONAL_MODE 3
CH3_SRC_RX_LANE_FUCTIONAL_MODE 3
CH3_SRC_NON_PTP_CHANNEL 1
CH3_SRC_TX_PCS_EN 1
CH3_SRC_RX_PCS_EN 1
CH3_SRC_UX_EN 1
CH3_SRC_TX_DL_EN 0
CH3_SRC_RX_DL_EN 0
CH3_SRC_FLUX_USED_FOR_RX_ADAPTATION 0
CH3_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW 1
CH3_SRC_PTP_EN 0
CH3_SRC_TX_FEC_EN 0
CH3_SRC_RX_FEC_EN 0
CH3_SRC_ETHERNET_SYSPLL_CLK_MODE 1
CH3_SRC_UX_USING_SYSPLL_CLK 0
CH3_SRC_FLUX_USING_SYSPLL_CLK 0
CH3_SRC_FLUX_EN 0
CH3_SRC_FLUX_EN_HW 1
CH3_SRC_SRC_LANE_INDEX 3
CH3_SRC_LEADER_LANE 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip

n_channel_superset_hal_top v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 156.250000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz
rx_pll_refclk_freq_mhz 184.320000
dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch0_tx_channel_mode PCSD
ch0_rx_channel_mode PCSD
ch0_duplex_mode DUPLEX
ch0_rate_mode RATE_25G
ch0_ptp_mode DISABLED
ch0_fec_mode 0
ch0_tx_dl_enable DISABLE
ch0_rx_dl_enable DISABLE
ch0_sup_mode USER_MODE
ch0_sim_mode ENABLE
ch0_tx_user1_clk_dynamic_mux PLL_C0
ch0_tx_user2_clk_dynamic_mux DISABLED
ch0_rx_user1_clk_dynamic_mux PLL_C0
ch0_rx_user2_clk_dynamic_mux DISABLED
ch0_tx_bond_size 4
ch0_rx_bond_size 1
ch0_tx_pcs_mode IEEE
ch0_rx_pcs_mode IEEE
ch0_syspll_rx_clk_hz 322265625
ch0_syspll_tx_clk_hz 322265625
ch0_mac_link_fault_mode OFF
ch0_mac_remove_pads DISABLE
ch0_mac_keep_rx_crc DISABLE
ch0_mac_forward_rx_pause_requests DISABLE
ch0_mac_source_address_insertion DISABLE
ch0_mac_tx_vlan_detection DISABLE
ch0_mac_rx_vlan_detection DISABLE
ch0_mac_flow_control DISABLE FLOW CONTROL
ch0_mac_tx_max_frame_size 65
ch0_mac_rx_max_frame_size 65
ch0_mac_enforce_max_frame_size DISABLE
ch0_mac_tx_preamble_passthrough DISABLE
ch0_mac_rx_preamble_passthrough DISABLE
ch0_mac_strict_preamble_checking DISABLE
ch0_mac_strict_sfd_checking DISABLE
ch0_mac_tx_ipg_size 12
ch0_mac_ipg_removed_per_am_period 0
ch0_mac_custom_cadence DISABLE
ch0_ptp0_en DISABLED
ch0_ptp1_en DISABLED
ch0_mac_sim_mode ENABLE
ch0_ptp0_sim_mode ENABLE
ch0_ptp1_sim_mode ENABLE
ch0_mac_tx_mac_data_flow DISABLE
ch0_mac_sf_en DISABLED
ch0_ehip_loopback_mode NO_LOOPBACK
ch0_mac_txmac_saddr 001122334455
ch0_pldif_tx_fifo_mode PHASE_COMP
ch0_pldif_tx_fifo_width DOUBLE_WIDTH
ch0_pldif_rx_fifo_mode PHASE_COMP
ch0_pldif_rx_fifo_width DOUBLE_WIDTH
ch0_pldif_tx_clkout1_divider DIV2
ch0_pldif_tx_clkout2_divider DIV2
ch0_pldif_rx_clkout1_divider DIV2
ch0_pldif_rx_clkout2_divider DIV2
ch0_pldif_channel_identifier GENERIC
ch0_pldif_sf_en ENABLED
ch0_pldif_loopback_mode NO_LOOPBACK
ch0_pcs_loopback_mode NO_LOOPBACK
ch0_pcs_sf_en ENABLED
ch0_fec_spec DISABLED
ch0_fec_fracture UNUSED
ch0_fec_tx_en FALSE
ch0_fec_rx_en FALSE
ch0_fec_loopback_mode DISABLE
ch0_xcvr_tx_protocol_hint DISABLED
ch0_xcvr_tx_datarate_bps 1105.92
ch0_xcvr_tx_prbs_pattern DISABLE
ch0_xcvr_tx_user_clk_only_mode DISABLE
ch0_xcvr_tx_width 32
ch0_xcvr_rx_protocol_hint DISABLED
ch0_xcvr_rx_datarate_bps 1105.92
ch0_xcvr_rx_prbs_pattern DISABLE
ch0_xcvr_rx_width 32
ch0_xcvr_rx_force_cdr_ltr FALSE
ch0_xcvr_rx_adaptation_mode DISABLED
ch0_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch0_xcvr_cdr_f_ref_hz 184320000
ch0_xcvr_cdr_f_vco_hz 552960000
ch0_rx_postdiv_clk_en ENABLE
ch0_rx_postdiv_clk_divider 100
ch0_tx_postdiv_clk_divider 100
ch0_tx_pll_f_ref_hz 184320000
ch0_tx_pll_f_out_hz 552960000
ch0_tx_pll_refclk_select GLOBAL_REFCLK0
ch0_cdr_refclk_select GLOBAL_REFCLK1
ch0_phy_loopback_mode DISABLED
ch0_flux_mode FLUX_MODE_BYPASS
ch0_flux_mode_hw FLUX_MODE_SNIFFER
ch0_xcvrif_tx_fifo_mode ELASTIC
ch0_xcvrif_rx_fifo_mode ELASTIC
ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch0_tx_pll_frac_mode_en DISABLE
ch0_xcvr_tx_spread_spectrum_en DISABLE
ch0_xcvr_tx_cascade_en DISABLE
ch0_rx_invert_pin DISABLE
ch0_tx_invert_pin DISABLE
ch0_xcvr_rx_cdrdivout_en DISABLE
ch0_xcvr_tx_eq_main_tap 52
ch0_xcvr_tx_eq_post_tap_1 5
ch0_xcvr_tx_eq_pre_tap_1 0
ch0_xcvr_tx_eq_pre_tap_2 0
ch0_tx_pll_feed_forward_gain 197
ch0_xcvr_rx_termination_mode GROUNDED
ch0_xcvr_rx_onchip_termination_setting R_2
ch0_xcvr_rx_eq_vga_gain 0
ch0_xcvr_x_eq_hf_boost 0
ch0_xcvr_rx_eq_dfe_tap_1 0
ch0_xcvr_rx_external_couple_type AC
ch0_sequencer_reg_en DISABLE
ch0_rx_dl_rx_lat_bit_for_async 0
ch0_rx_dl_rxbit_rollover 0
ch0_rx_dl_rxbit_cntr_pma DISABLE
ch0_hw_fec 0
ch1_tx_channel_mode PCSD
ch1_rx_channel_mode PCSD
ch1_duplex_mode DUPLEX
ch1_rate_mode RATE_25G
ch1_ptp_mode DISABLED
ch1_fec_mode 0
ch1_tx_dl_enable DISABLE
ch1_rx_dl_enable DISABLE
ch1_sup_mode USER_MODE
ch1_sim_mode ENABLE
ch1_tx_user1_clk_dynamic_mux PLL_C0
ch1_tx_user2_clk_dynamic_mux DISABLED
ch1_rx_user1_clk_dynamic_mux PLL_C0
ch1_rx_user2_clk_dynamic_mux DISABLED
ch1_tx_bond_size 4
ch1_rx_bond_size 1
ch1_tx_pcs_mode IEEE
ch1_rx_pcs_mode IEEE
ch1_syspll_rx_clk_hz 322265625
ch1_syspll_tx_clk_hz 322265625
ch1_mac_link_fault_mode OFF
ch1_mac_remove_pads DISABLE
ch1_mac_keep_rx_crc DISABLE
ch1_mac_forward_rx_pause_requests DISABLE
ch1_mac_source_address_insertion DISABLE
ch1_mac_tx_vlan_detection DISABLE
ch1_mac_rx_vlan_detection DISABLE
ch1_mac_flow_control DISABLE FLOW CONTROL
ch1_mac_tx_max_frame_size 65
ch1_mac_rx_max_frame_size 65
ch1_mac_enforce_max_frame_size DISABLE
ch1_mac_tx_preamble_passthrough DISABLE
ch1_mac_rx_preamble_passthrough DISABLE
ch1_mac_strict_preamble_checking DISABLE
ch1_mac_strict_sfd_checking DISABLE
ch1_mac_tx_ipg_size 12
ch1_mac_ipg_removed_per_am_period 0
ch1_mac_custom_cadence DISABLE
ch1_ptp0_en DISABLED
ch1_ptp1_en DISABLED
ch1_mac_sim_mode ENABLE
ch1_ptp0_sim_mode ENABLE
ch1_ptp1_sim_mode ENABLE
ch1_mac_tx_mac_data_flow DISABLE
ch1_mac_sf_en DISABLED
ch1_ehip_loopback_mode NO_LOOPBACK
ch1_mac_txmac_saddr 001122334455
ch1_pldif_tx_fifo_mode PHASE_COMP
ch1_pldif_tx_fifo_width DOUBLE_WIDTH
ch1_pldif_rx_fifo_mode PHASE_COMP
ch1_pldif_rx_fifo_width DOUBLE_WIDTH
ch1_pldif_tx_clkout1_divider DIV2
ch1_pldif_tx_clkout2_divider DIV2
ch1_pldif_rx_clkout1_divider DIV2
ch1_pldif_rx_clkout2_divider DIV2
ch1_pldif_channel_identifier GENERIC
ch1_pldif_sf_en ENABLED
ch1_pldif_loopback_mode NO_LOOPBACK
ch1_pcs_loopback_mode NO_LOOPBACK
ch1_pcs_sf_en ENABLED
ch1_fec_spec DISABLED
ch1_fec_fracture UNUSED
ch1_fec_tx_en FALSE
ch1_fec_rx_en FALSE
ch1_fec_loopback_mode DISABLE
ch1_xcvr_tx_protocol_hint DISABLED
ch1_xcvr_tx_datarate_bps 1105.92
ch1_xcvr_tx_prbs_pattern DISABLE
ch1_xcvr_tx_user_clk_only_mode DISABLE
ch1_xcvr_tx_width 32
ch1_xcvr_rx_protocol_hint DISABLED
ch1_xcvr_rx_datarate_bps 1105.92
ch1_xcvr_rx_prbs_pattern DISABLE
ch1_xcvr_rx_width 32
ch1_xcvr_rx_force_cdr_ltr FALSE
ch1_xcvr_rx_adaptation_mode DISABLED
ch1_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch1_xcvr_cdr_f_ref_hz 184320000
ch1_xcvr_cdr_f_vco_hz 552960000
ch1_rx_postdiv_clk_en ENABLE
ch1_rx_postdiv_clk_divider 100
ch1_tx_postdiv_clk_divider 100
ch1_tx_pll_f_ref_hz 184320000
ch1_tx_pll_f_out_hz 552960000
ch1_tx_pll_refclk_select GLOBAL_REFCLK0
ch1_cdr_refclk_select GLOBAL_REFCLK1
ch1_phy_loopback_mode DISABLED
ch1_flux_mode FLUX_MODE_BYPASS
ch1_flux_mode_hw FLUX_MODE_SNIFFER
ch1_xcvrif_tx_fifo_mode ELASTIC
ch1_xcvrif_rx_fifo_mode ELASTIC
ch1_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch1_tx_pll_frac_mode_en DISABLE
ch1_xcvr_tx_spread_spectrum_en DISABLE
ch1_xcvr_tx_cascade_en DISABLE
ch1_rx_invert_pin DISABLE
ch1_tx_invert_pin DISABLE
ch1_xcvr_rx_cdrdivout_en DISABLE
ch1_xcvr_tx_eq_main_tap 52
ch1_xcvr_tx_eq_post_tap_1 5
ch1_xcvr_tx_eq_pre_tap_1 0
ch1_xcvr_tx_eq_pre_tap_2 0
ch1_tx_pll_feed_forward_gain 197
ch1_xcvr_rx_termination_mode GROUNDED
ch1_xcvr_rx_onchip_termination_setting R_2
ch1_xcvr_rx_eq_vga_gain 0
ch1_xcvr_x_eq_hf_boost 0
ch1_xcvr_rx_eq_dfe_tap_1 0
ch1_xcvr_rx_external_couple_type AC
ch1_sequencer_reg_en DISABLE
ch1_rx_dl_rx_lat_bit_for_async 0
ch1_rx_dl_rxbit_rollover 0
ch1_rx_dl_rxbit_cntr_pma DISABLE
ch1_hw_fec 0
ch2_tx_channel_mode PCSD
ch2_rx_channel_mode PCSD
ch2_duplex_mode DUPLEX
ch2_rate_mode RATE_25G
ch2_ptp_mode DISABLED
ch2_fec_mode 0
ch2_tx_dl_enable DISABLE
ch2_rx_dl_enable DISABLE
ch2_sup_mode USER_MODE
ch2_sim_mode ENABLE
ch2_tx_user1_clk_dynamic_mux PLL_C0
ch2_tx_user2_clk_dynamic_mux DISABLED
ch2_rx_user1_clk_dynamic_mux PLL_C0
ch2_rx_user2_clk_dynamic_mux DISABLED
ch2_tx_bond_size 4
ch2_rx_bond_size 1
ch2_tx_pcs_mode IEEE
ch2_rx_pcs_mode IEEE
ch2_syspll_rx_clk_hz 322265625
ch2_syspll_tx_clk_hz 322265625
ch2_mac_link_fault_mode OFF
ch2_mac_remove_pads DISABLE
ch2_mac_keep_rx_crc DISABLE
ch2_mac_forward_rx_pause_requests DISABLE
ch2_mac_source_address_insertion DISABLE
ch2_mac_tx_vlan_detection DISABLE
ch2_mac_rx_vlan_detection DISABLE
ch2_mac_flow_control DISABLE FLOW CONTROL
ch2_mac_tx_max_frame_size 65
ch2_mac_rx_max_frame_size 65
ch2_mac_enforce_max_frame_size DISABLE
ch2_mac_tx_preamble_passthrough DISABLE
ch2_mac_rx_preamble_passthrough DISABLE
ch2_mac_strict_preamble_checking DISABLE
ch2_mac_strict_sfd_checking DISABLE
ch2_mac_tx_ipg_size 12
ch2_mac_ipg_removed_per_am_period 0
ch2_mac_custom_cadence DISABLE
ch2_ptp0_en DISABLED
ch2_ptp1_en DISABLED
ch2_mac_sim_mode ENABLE
ch2_ptp0_sim_mode ENABLE
ch2_ptp1_sim_mode ENABLE
ch2_mac_tx_mac_data_flow DISABLE
ch2_mac_sf_en DISABLED
ch2_ehip_loopback_mode NO_LOOPBACK
ch2_mac_txmac_saddr 001122334455
ch2_pldif_tx_fifo_mode PHASE_COMP
ch2_pldif_tx_fifo_width DOUBLE_WIDTH
ch2_pldif_rx_fifo_mode PHASE_COMP
ch2_pldif_rx_fifo_width DOUBLE_WIDTH
ch2_pldif_tx_clkout1_divider DIV2
ch2_pldif_tx_clkout2_divider DIV2
ch2_pldif_rx_clkout1_divider DIV2
ch2_pldif_rx_clkout2_divider DIV2
ch2_pldif_channel_identifier GENERIC
ch2_pldif_sf_en ENABLED
ch2_pldif_loopback_mode NO_LOOPBACK
ch2_pcs_loopback_mode NO_LOOPBACK
ch2_pcs_sf_en ENABLED
ch2_fec_spec DISABLED
ch2_fec_fracture UNUSED
ch2_fec_tx_en FALSE
ch2_fec_rx_en FALSE
ch2_fec_loopback_mode DISABLE
ch2_xcvr_tx_protocol_hint DISABLED
ch2_xcvr_tx_datarate_bps 1105.92
ch2_xcvr_tx_prbs_pattern DISABLE
ch2_xcvr_tx_user_clk_only_mode DISABLE
ch2_xcvr_tx_width 32
ch2_xcvr_rx_protocol_hint DISABLED
ch2_xcvr_rx_datarate_bps 1105.92
ch2_xcvr_rx_prbs_pattern DISABLE
ch2_xcvr_rx_width 32
ch2_xcvr_rx_force_cdr_ltr FALSE
ch2_xcvr_rx_adaptation_mode DISABLED
ch2_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch2_xcvr_cdr_f_ref_hz 184320000
ch2_xcvr_cdr_f_vco_hz 552960000
ch2_rx_postdiv_clk_en ENABLE
ch2_rx_postdiv_clk_divider 100
ch2_tx_postdiv_clk_divider 100
ch2_tx_pll_f_ref_hz 184320000
ch2_tx_pll_f_out_hz 552960000
ch2_tx_pll_refclk_select GLOBAL_REFCLK0
ch2_cdr_refclk_select GLOBAL_REFCLK1
ch2_phy_loopback_mode DISABLED
ch2_flux_mode FLUX_MODE_BYPASS
ch2_flux_mode_hw FLUX_MODE_SNIFFER
ch2_xcvrif_tx_fifo_mode ELASTIC
ch2_xcvrif_rx_fifo_mode ELASTIC
ch2_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch2_tx_pll_frac_mode_en DISABLE
ch2_xcvr_tx_spread_spectrum_en DISABLE
ch2_xcvr_tx_cascade_en DISABLE
ch2_rx_invert_pin DISABLE
ch2_tx_invert_pin DISABLE
ch2_xcvr_rx_cdrdivout_en DISABLE
ch2_xcvr_tx_eq_main_tap 52
ch2_xcvr_tx_eq_post_tap_1 5
ch2_xcvr_tx_eq_pre_tap_1 0
ch2_xcvr_tx_eq_pre_tap_2 0
ch2_tx_pll_feed_forward_gain 197
ch2_xcvr_rx_termination_mode GROUNDED
ch2_xcvr_rx_onchip_termination_setting R_2
ch2_xcvr_rx_eq_vga_gain 0
ch2_xcvr_x_eq_hf_boost 0
ch2_xcvr_rx_eq_dfe_tap_1 0
ch2_xcvr_rx_external_couple_type AC
ch2_sequencer_reg_en DISABLE
ch2_rx_dl_rx_lat_bit_for_async 0
ch2_rx_dl_rxbit_rollover 0
ch2_rx_dl_rxbit_cntr_pma DISABLE
ch2_hw_fec 0
ch3_tx_channel_mode PCSD
ch3_rx_channel_mode PCSD
ch3_duplex_mode DUPLEX
ch3_rate_mode RATE_25G
ch3_ptp_mode DISABLED
ch3_fec_mode 0
ch3_tx_dl_enable DISABLE
ch3_rx_dl_enable DISABLE
ch3_sup_mode USER_MODE
ch3_sim_mode ENABLE
ch3_tx_user1_clk_dynamic_mux PLL_C0
ch3_tx_user2_clk_dynamic_mux DISABLED
ch3_rx_user1_clk_dynamic_mux PLL_C0
ch3_rx_user2_clk_dynamic_mux DISABLED
ch3_tx_bond_size 4
ch3_rx_bond_size 1
ch3_tx_pcs_mode IEEE
ch3_rx_pcs_mode IEEE
ch3_syspll_rx_clk_hz 322265625
ch3_syspll_tx_clk_hz 322265625
ch3_mac_link_fault_mode OFF
ch3_mac_remove_pads DISABLE
ch3_mac_keep_rx_crc DISABLE
ch3_mac_forward_rx_pause_requests DISABLE
ch3_mac_source_address_insertion DISABLE
ch3_mac_tx_vlan_detection DISABLE
ch3_mac_rx_vlan_detection DISABLE
ch3_mac_flow_control DISABLE FLOW CONTROL
ch3_mac_tx_max_frame_size 65
ch3_mac_rx_max_frame_size 65
ch3_mac_enforce_max_frame_size DISABLE
ch3_mac_tx_preamble_passthrough DISABLE
ch3_mac_rx_preamble_passthrough DISABLE
ch3_mac_strict_preamble_checking DISABLE
ch3_mac_strict_sfd_checking DISABLE
ch3_mac_tx_ipg_size 12
ch3_mac_ipg_removed_per_am_period 0
ch3_mac_custom_cadence DISABLE
ch3_ptp0_en DISABLED
ch3_ptp1_en DISABLED
ch3_mac_sim_mode ENABLE
ch3_ptp0_sim_mode ENABLE
ch3_ptp1_sim_mode ENABLE
ch3_mac_tx_mac_data_flow DISABLE
ch3_mac_sf_en DISABLED
ch3_ehip_loopback_mode NO_LOOPBACK
ch3_mac_txmac_saddr 001122334455
ch3_pldif_tx_fifo_mode PHASE_COMP
ch3_pldif_tx_fifo_width DOUBLE_WIDTH
ch3_pldif_rx_fifo_mode PHASE_COMP
ch3_pldif_rx_fifo_width DOUBLE_WIDTH
ch3_pldif_tx_clkout1_divider DIV2
ch3_pldif_tx_clkout2_divider DIV2
ch3_pldif_rx_clkout1_divider DIV2
ch3_pldif_rx_clkout2_divider DIV2
ch3_pldif_channel_identifier GENERIC
ch3_pldif_sf_en ENABLED
ch3_pldif_loopback_mode NO_LOOPBACK
ch3_pcs_loopback_mode NO_LOOPBACK
ch3_pcs_sf_en ENABLED
ch3_fec_spec DISABLED
ch3_fec_fracture UNUSED
ch3_fec_tx_en FALSE
ch3_fec_rx_en FALSE
ch3_fec_loopback_mode DISABLE
ch3_xcvr_tx_protocol_hint DISABLED
ch3_xcvr_tx_datarate_bps 1105.92
ch3_xcvr_tx_prbs_pattern DISABLE
ch3_xcvr_tx_user_clk_only_mode DISABLE
ch3_xcvr_tx_width 32
ch3_xcvr_rx_protocol_hint DISABLED
ch3_xcvr_rx_datarate_bps 1105.92
ch3_xcvr_rx_prbs_pattern DISABLE
ch3_xcvr_rx_width 32
ch3_xcvr_rx_force_cdr_ltr FALSE
ch3_xcvr_rx_adaptation_mode DISABLED
ch3_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch3_xcvr_cdr_f_ref_hz 184320000
ch3_xcvr_cdr_f_vco_hz 552960000
ch3_rx_postdiv_clk_en ENABLE
ch3_rx_postdiv_clk_divider 100
ch3_tx_postdiv_clk_divider 100
ch3_tx_pll_f_ref_hz 184320000
ch3_tx_pll_f_out_hz 552960000
ch3_tx_pll_refclk_select GLOBAL_REFCLK0
ch3_cdr_refclk_select GLOBAL_REFCLK1
ch3_phy_loopback_mode DISABLED
ch3_flux_mode FLUX_MODE_BYPASS
ch3_flux_mode_hw FLUX_MODE_SNIFFER
ch3_xcvrif_tx_fifo_mode ELASTIC
ch3_xcvrif_rx_fifo_mode ELASTIC
ch3_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch3_tx_pll_frac_mode_en DISABLE
ch3_xcvr_tx_spread_spectrum_en DISABLE
ch3_xcvr_tx_cascade_en DISABLE
ch3_rx_invert_pin DISABLE
ch3_tx_invert_pin DISABLE
ch3_xcvr_rx_cdrdivout_en DISABLE
ch3_xcvr_tx_eq_main_tap 52
ch3_xcvr_tx_eq_post_tap_1 5
ch3_xcvr_tx_eq_pre_tap_1 0
ch3_xcvr_tx_eq_pre_tap_2 0
ch3_tx_pll_feed_forward_gain 197
ch3_xcvr_rx_termination_mode GROUNDED
ch3_xcvr_rx_onchip_termination_setting R_2
ch3_xcvr_rx_eq_vga_gain 0
ch3_xcvr_x_eq_hf_boost 0
ch3_xcvr_rx_eq_dfe_tap_1 0
ch3_xcvr_rx_external_couple_type AC
ch3_sequencer_reg_en DISABLE
ch3_rx_dl_rx_lat_bit_for_async 0
ch3_rx_dl_rxbit_rollover 0
ch3_rx_dl_rxbit_cntr_pma DISABLE
ch3_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip

hal_top v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 156.250000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz
rx_pll_refclk_freq_mhz 184.320000
dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch0_tx_channel_mode PCSD
ch0_rx_channel_mode PCSD
ch0_duplex_mode DUPLEX
ch0_rate_mode RATE_25G
ch0_ptp_mode DISABLED
ch0_fec_mode 0
ch0_tx_dl_enable DISABLE
ch0_rx_dl_enable DISABLE
ch0_sup_mode USER_MODE
ch0_sim_mode ENABLE
ch0_tx_user1_clk_dynamic_mux PLL_C0
ch0_tx_user2_clk_dynamic_mux DISABLED
ch0_rx_user1_clk_dynamic_mux PLL_C0
ch0_rx_user2_clk_dynamic_mux DISABLED
ch0_tx_bond_size 4
ch0_rx_bond_size 1
ch0_tx_pcs_mode IEEE
ch0_rx_pcs_mode IEEE
ch0_syspll_rx_clk_hz 322265625
ch0_syspll_tx_clk_hz 322265625
ch0_mac_link_fault_mode OFF
ch0_mac_remove_pads DISABLE
ch0_mac_keep_rx_crc DISABLE
ch0_mac_forward_rx_pause_requests DISABLE
ch0_mac_source_address_insertion DISABLE
ch0_mac_tx_vlan_detection DISABLE
ch0_mac_rx_vlan_detection DISABLE
ch0_mac_flow_control DISABLE FLOW CONTROL
ch0_mac_tx_max_frame_size 65
ch0_mac_rx_max_frame_size 65
ch0_mac_enforce_max_frame_size DISABLE
ch0_mac_tx_preamble_passthrough DISABLE
ch0_mac_rx_preamble_passthrough DISABLE
ch0_mac_strict_preamble_checking DISABLE
ch0_mac_strict_sfd_checking DISABLE
ch0_mac_tx_ipg_size 12
ch0_mac_ipg_removed_per_am_period 0
ch0_mac_custom_cadence DISABLE
ch0_ptp0_en DISABLED
ch0_ptp1_en DISABLED
ch0_mac_sim_mode ENABLE
ch0_ptp0_sim_mode ENABLE
ch0_ptp1_sim_mode ENABLE
ch0_mac_tx_mac_data_flow DISABLE
ch0_mac_sf_en DISABLED
ch0_ehip_loopback_mode NO_LOOPBACK
ch0_mac_txmac_saddr 001122334455
ch0_pldif_tx_fifo_mode PHASE_COMP
ch0_pldif_tx_fifo_width DOUBLE_WIDTH
ch0_pldif_rx_fifo_mode PHASE_COMP
ch0_pldif_rx_fifo_width DOUBLE_WIDTH
ch0_pldif_tx_clkout1_divider DIV2
ch0_pldif_tx_clkout2_divider DIV2
ch0_pldif_rx_clkout1_divider DIV2
ch0_pldif_rx_clkout2_divider DIV2
ch0_pldif_channel_identifier GENERIC
ch0_pldif_sf_en ENABLED
ch0_pldif_loopback_mode NO_LOOPBACK
ch0_pcs_loopback_mode NO_LOOPBACK
ch0_pcs_sf_en ENABLED
ch0_fec_spec DISABLED
ch0_fec_fracture UNUSED
ch0_fec_tx_en FALSE
ch0_fec_rx_en FALSE
ch0_fec_loopback_mode DISABLE
ch0_xcvr_tx_protocol_hint DISABLED
ch0_xcvr_tx_datarate_bps 1105.92
ch0_xcvr_tx_prbs_pattern DISABLE
ch0_xcvr_tx_user_clk_only_mode DISABLE
ch0_xcvr_tx_width 32
ch0_xcvr_rx_protocol_hint DISABLED
ch0_xcvr_rx_datarate_bps 1105.92
ch0_xcvr_rx_prbs_pattern DISABLE
ch0_xcvr_rx_width 32
ch0_xcvr_rx_force_cdr_ltr FALSE
ch0_xcvr_rx_adaptation_mode DISABLED
ch0_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch0_xcvr_cdr_f_ref_hz 184320000
ch0_xcvr_cdr_f_vco_hz 552960000
ch0_rx_postdiv_clk_en ENABLE
ch0_rx_postdiv_clk_divider 100
ch0_tx_postdiv_clk_divider 100
ch0_tx_pll_f_ref_hz 184320000
ch0_tx_pll_f_out_hz 552960000
ch0_tx_pll_refclk_select GLOBAL_REFCLK0
ch0_cdr_refclk_select GLOBAL_REFCLK1
ch0_phy_loopback_mode DISABLED
ch0_flux_mode FLUX_MODE_BYPASS
ch0_flux_mode_hw FLUX_MODE_SNIFFER
ch0_xcvrif_tx_fifo_mode ELASTIC
ch0_xcvrif_rx_fifo_mode ELASTIC
ch0_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch0_tx_pll_frac_mode_en DISABLE
ch0_xcvr_tx_spread_spectrum_en DISABLE
ch0_xcvr_tx_cascade_en DISABLE
ch0_rx_invert_pin DISABLE
ch0_tx_invert_pin DISABLE
ch0_xcvr_rx_cdrdivout_en DISABLE
ch0_xcvr_tx_eq_main_tap 52
ch0_xcvr_tx_eq_post_tap_1 5
ch0_xcvr_tx_eq_pre_tap_1 0
ch0_xcvr_tx_eq_pre_tap_2 0
ch0_tx_pll_feed_forward_gain 197
ch0_xcvr_rx_termination_mode GROUNDED
ch0_xcvr_rx_onchip_termination_setting R_2
ch0_xcvr_rx_eq_vga_gain 0
ch0_xcvr_x_eq_hf_boost 0
ch0_xcvr_rx_eq_dfe_tap_1 0
ch0_xcvr_rx_external_couple_type AC
ch0_sequencer_reg_en DISABLE
ch0_rx_dl_rx_lat_bit_for_async 0
ch0_rx_dl_rxbit_rollover 0
ch0_rx_dl_rxbit_cntr_pma DISABLE
ch0_hw_fec 0
ch1_tx_channel_mode PCSD
ch1_rx_channel_mode PCSD
ch1_duplex_mode DUPLEX
ch1_rate_mode RATE_25G
ch1_ptp_mode DISABLED
ch1_fec_mode 0
ch1_tx_dl_enable DISABLE
ch1_rx_dl_enable DISABLE
ch1_sup_mode USER_MODE
ch1_sim_mode ENABLE
ch1_tx_user1_clk_dynamic_mux PLL_C0
ch1_tx_user2_clk_dynamic_mux DISABLED
ch1_rx_user1_clk_dynamic_mux PLL_C0
ch1_rx_user2_clk_dynamic_mux DISABLED
ch1_tx_bond_size 4
ch1_rx_bond_size 1
ch1_tx_pcs_mode IEEE
ch1_rx_pcs_mode IEEE
ch1_syspll_rx_clk_hz 322265625
ch1_syspll_tx_clk_hz 322265625
ch1_mac_link_fault_mode OFF
ch1_mac_remove_pads DISABLE
ch1_mac_keep_rx_crc DISABLE
ch1_mac_forward_rx_pause_requests DISABLE
ch1_mac_source_address_insertion DISABLE
ch1_mac_tx_vlan_detection DISABLE
ch1_mac_rx_vlan_detection DISABLE
ch1_mac_flow_control DISABLE FLOW CONTROL
ch1_mac_tx_max_frame_size 65
ch1_mac_rx_max_frame_size 65
ch1_mac_enforce_max_frame_size DISABLE
ch1_mac_tx_preamble_passthrough DISABLE
ch1_mac_rx_preamble_passthrough DISABLE
ch1_mac_strict_preamble_checking DISABLE
ch1_mac_strict_sfd_checking DISABLE
ch1_mac_tx_ipg_size 12
ch1_mac_ipg_removed_per_am_period 0
ch1_mac_custom_cadence DISABLE
ch1_ptp0_en DISABLED
ch1_ptp1_en DISABLED
ch1_mac_sim_mode ENABLE
ch1_ptp0_sim_mode ENABLE
ch1_ptp1_sim_mode ENABLE
ch1_mac_tx_mac_data_flow DISABLE
ch1_mac_sf_en DISABLED
ch1_ehip_loopback_mode NO_LOOPBACK
ch1_mac_txmac_saddr 001122334455
ch1_pldif_tx_fifo_mode PHASE_COMP
ch1_pldif_tx_fifo_width DOUBLE_WIDTH
ch1_pldif_rx_fifo_mode PHASE_COMP
ch1_pldif_rx_fifo_width DOUBLE_WIDTH
ch1_pldif_tx_clkout1_divider DIV2
ch1_pldif_tx_clkout2_divider DIV2
ch1_pldif_rx_clkout1_divider DIV2
ch1_pldif_rx_clkout2_divider DIV2
ch1_pldif_channel_identifier GENERIC
ch1_pldif_sf_en ENABLED
ch1_pldif_loopback_mode NO_LOOPBACK
ch1_pcs_loopback_mode NO_LOOPBACK
ch1_pcs_sf_en ENABLED
ch1_fec_spec DISABLED
ch1_fec_fracture UNUSED
ch1_fec_tx_en FALSE
ch1_fec_rx_en FALSE
ch1_fec_loopback_mode DISABLE
ch1_xcvr_tx_protocol_hint DISABLED
ch1_xcvr_tx_datarate_bps 1105.92
ch1_xcvr_tx_prbs_pattern DISABLE
ch1_xcvr_tx_user_clk_only_mode DISABLE
ch1_xcvr_tx_width 32
ch1_xcvr_rx_protocol_hint DISABLED
ch1_xcvr_rx_datarate_bps 1105.92
ch1_xcvr_rx_prbs_pattern DISABLE
ch1_xcvr_rx_width 32
ch1_xcvr_rx_force_cdr_ltr FALSE
ch1_xcvr_rx_adaptation_mode DISABLED
ch1_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch1_xcvr_cdr_f_ref_hz 184320000
ch1_xcvr_cdr_f_vco_hz 552960000
ch1_rx_postdiv_clk_en ENABLE
ch1_rx_postdiv_clk_divider 100
ch1_tx_postdiv_clk_divider 100
ch1_tx_pll_f_ref_hz 184320000
ch1_tx_pll_f_out_hz 552960000
ch1_tx_pll_refclk_select GLOBAL_REFCLK0
ch1_cdr_refclk_select GLOBAL_REFCLK1
ch1_phy_loopback_mode DISABLED
ch1_flux_mode FLUX_MODE_BYPASS
ch1_flux_mode_hw FLUX_MODE_SNIFFER
ch1_xcvrif_tx_fifo_mode ELASTIC
ch1_xcvrif_rx_fifo_mode ELASTIC
ch1_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch1_tx_pll_frac_mode_en DISABLE
ch1_xcvr_tx_spread_spectrum_en DISABLE
ch1_xcvr_tx_cascade_en DISABLE
ch1_rx_invert_pin DISABLE
ch1_tx_invert_pin DISABLE
ch1_xcvr_rx_cdrdivout_en DISABLE
ch1_xcvr_tx_eq_main_tap 52
ch1_xcvr_tx_eq_post_tap_1 5
ch1_xcvr_tx_eq_pre_tap_1 0
ch1_xcvr_tx_eq_pre_tap_2 0
ch1_tx_pll_feed_forward_gain 197
ch1_xcvr_rx_termination_mode GROUNDED
ch1_xcvr_rx_onchip_termination_setting R_2
ch1_xcvr_rx_eq_vga_gain 0
ch1_xcvr_x_eq_hf_boost 0
ch1_xcvr_rx_eq_dfe_tap_1 0
ch1_xcvr_rx_external_couple_type AC
ch1_sequencer_reg_en DISABLE
ch1_rx_dl_rx_lat_bit_for_async 0
ch1_rx_dl_rxbit_rollover 0
ch1_rx_dl_rxbit_cntr_pma DISABLE
ch1_hw_fec 0
ch2_tx_channel_mode PCSD
ch2_rx_channel_mode PCSD
ch2_duplex_mode DUPLEX
ch2_rate_mode RATE_25G
ch2_ptp_mode DISABLED
ch2_fec_mode 0
ch2_tx_dl_enable DISABLE
ch2_rx_dl_enable DISABLE
ch2_sup_mode USER_MODE
ch2_sim_mode ENABLE
ch2_tx_user1_clk_dynamic_mux PLL_C0
ch2_tx_user2_clk_dynamic_mux DISABLED
ch2_rx_user1_clk_dynamic_mux PLL_C0
ch2_rx_user2_clk_dynamic_mux DISABLED
ch2_tx_bond_size 4
ch2_rx_bond_size 1
ch2_tx_pcs_mode IEEE
ch2_rx_pcs_mode IEEE
ch2_syspll_rx_clk_hz 322265625
ch2_syspll_tx_clk_hz 322265625
ch2_mac_link_fault_mode OFF
ch2_mac_remove_pads DISABLE
ch2_mac_keep_rx_crc DISABLE
ch2_mac_forward_rx_pause_requests DISABLE
ch2_mac_source_address_insertion DISABLE
ch2_mac_tx_vlan_detection DISABLE
ch2_mac_rx_vlan_detection DISABLE
ch2_mac_flow_control DISABLE FLOW CONTROL
ch2_mac_tx_max_frame_size 65
ch2_mac_rx_max_frame_size 65
ch2_mac_enforce_max_frame_size DISABLE
ch2_mac_tx_preamble_passthrough DISABLE
ch2_mac_rx_preamble_passthrough DISABLE
ch2_mac_strict_preamble_checking DISABLE
ch2_mac_strict_sfd_checking DISABLE
ch2_mac_tx_ipg_size 12
ch2_mac_ipg_removed_per_am_period 0
ch2_mac_custom_cadence DISABLE
ch2_ptp0_en DISABLED
ch2_ptp1_en DISABLED
ch2_mac_sim_mode ENABLE
ch2_ptp0_sim_mode ENABLE
ch2_ptp1_sim_mode ENABLE
ch2_mac_tx_mac_data_flow DISABLE
ch2_mac_sf_en DISABLED
ch2_ehip_loopback_mode NO_LOOPBACK
ch2_mac_txmac_saddr 001122334455
ch2_pldif_tx_fifo_mode PHASE_COMP
ch2_pldif_tx_fifo_width DOUBLE_WIDTH
ch2_pldif_rx_fifo_mode PHASE_COMP
ch2_pldif_rx_fifo_width DOUBLE_WIDTH
ch2_pldif_tx_clkout1_divider DIV2
ch2_pldif_tx_clkout2_divider DIV2
ch2_pldif_rx_clkout1_divider DIV2
ch2_pldif_rx_clkout2_divider DIV2
ch2_pldif_channel_identifier GENERIC
ch2_pldif_sf_en ENABLED
ch2_pldif_loopback_mode NO_LOOPBACK
ch2_pcs_loopback_mode NO_LOOPBACK
ch2_pcs_sf_en ENABLED
ch2_fec_spec DISABLED
ch2_fec_fracture UNUSED
ch2_fec_tx_en FALSE
ch2_fec_rx_en FALSE
ch2_fec_loopback_mode DISABLE
ch2_xcvr_tx_protocol_hint DISABLED
ch2_xcvr_tx_datarate_bps 1105.92
ch2_xcvr_tx_prbs_pattern DISABLE
ch2_xcvr_tx_user_clk_only_mode DISABLE
ch2_xcvr_tx_width 32
ch2_xcvr_rx_protocol_hint DISABLED
ch2_xcvr_rx_datarate_bps 1105.92
ch2_xcvr_rx_prbs_pattern DISABLE
ch2_xcvr_rx_width 32
ch2_xcvr_rx_force_cdr_ltr FALSE
ch2_xcvr_rx_adaptation_mode DISABLED
ch2_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch2_xcvr_cdr_f_ref_hz 184320000
ch2_xcvr_cdr_f_vco_hz 552960000
ch2_rx_postdiv_clk_en ENABLE
ch2_rx_postdiv_clk_divider 100
ch2_tx_postdiv_clk_divider 100
ch2_tx_pll_f_ref_hz 184320000
ch2_tx_pll_f_out_hz 552960000
ch2_tx_pll_refclk_select GLOBAL_REFCLK0
ch2_cdr_refclk_select GLOBAL_REFCLK1
ch2_phy_loopback_mode DISABLED
ch2_flux_mode FLUX_MODE_BYPASS
ch2_flux_mode_hw FLUX_MODE_SNIFFER
ch2_xcvrif_tx_fifo_mode ELASTIC
ch2_xcvrif_rx_fifo_mode ELASTIC
ch2_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch2_tx_pll_frac_mode_en DISABLE
ch2_xcvr_tx_spread_spectrum_en DISABLE
ch2_xcvr_tx_cascade_en DISABLE
ch2_rx_invert_pin DISABLE
ch2_tx_invert_pin DISABLE
ch2_xcvr_rx_cdrdivout_en DISABLE
ch2_xcvr_tx_eq_main_tap 52
ch2_xcvr_tx_eq_post_tap_1 5
ch2_xcvr_tx_eq_pre_tap_1 0
ch2_xcvr_tx_eq_pre_tap_2 0
ch2_tx_pll_feed_forward_gain 197
ch2_xcvr_rx_termination_mode GROUNDED
ch2_xcvr_rx_onchip_termination_setting R_2
ch2_xcvr_rx_eq_vga_gain 0
ch2_xcvr_x_eq_hf_boost 0
ch2_xcvr_rx_eq_dfe_tap_1 0
ch2_xcvr_rx_external_couple_type AC
ch2_sequencer_reg_en DISABLE
ch2_rx_dl_rx_lat_bit_for_async 0
ch2_rx_dl_rxbit_rollover 0
ch2_rx_dl_rxbit_cntr_pma DISABLE
ch2_hw_fec 0
ch3_tx_channel_mode PCSD
ch3_rx_channel_mode PCSD
ch3_duplex_mode DUPLEX
ch3_rate_mode RATE_25G
ch3_ptp_mode DISABLED
ch3_fec_mode 0
ch3_tx_dl_enable DISABLE
ch3_rx_dl_enable DISABLE
ch3_sup_mode USER_MODE
ch3_sim_mode ENABLE
ch3_tx_user1_clk_dynamic_mux PLL_C0
ch3_tx_user2_clk_dynamic_mux DISABLED
ch3_rx_user1_clk_dynamic_mux PLL_C0
ch3_rx_user2_clk_dynamic_mux DISABLED
ch3_tx_bond_size 4
ch3_rx_bond_size 1
ch3_tx_pcs_mode IEEE
ch3_rx_pcs_mode IEEE
ch3_syspll_rx_clk_hz 322265625
ch3_syspll_tx_clk_hz 322265625
ch3_mac_link_fault_mode OFF
ch3_mac_remove_pads DISABLE
ch3_mac_keep_rx_crc DISABLE
ch3_mac_forward_rx_pause_requests DISABLE
ch3_mac_source_address_insertion DISABLE
ch3_mac_tx_vlan_detection DISABLE
ch3_mac_rx_vlan_detection DISABLE
ch3_mac_flow_control DISABLE FLOW CONTROL
ch3_mac_tx_max_frame_size 65
ch3_mac_rx_max_frame_size 65
ch3_mac_enforce_max_frame_size DISABLE
ch3_mac_tx_preamble_passthrough DISABLE
ch3_mac_rx_preamble_passthrough DISABLE
ch3_mac_strict_preamble_checking DISABLE
ch3_mac_strict_sfd_checking DISABLE
ch3_mac_tx_ipg_size 12
ch3_mac_ipg_removed_per_am_period 0
ch3_mac_custom_cadence DISABLE
ch3_ptp0_en DISABLED
ch3_ptp1_en DISABLED
ch3_mac_sim_mode ENABLE
ch3_ptp0_sim_mode ENABLE
ch3_ptp1_sim_mode ENABLE
ch3_mac_tx_mac_data_flow DISABLE
ch3_mac_sf_en DISABLED
ch3_ehip_loopback_mode NO_LOOPBACK
ch3_mac_txmac_saddr 001122334455
ch3_pldif_tx_fifo_mode PHASE_COMP
ch3_pldif_tx_fifo_width DOUBLE_WIDTH
ch3_pldif_rx_fifo_mode PHASE_COMP
ch3_pldif_rx_fifo_width DOUBLE_WIDTH
ch3_pldif_tx_clkout1_divider DIV2
ch3_pldif_tx_clkout2_divider DIV2
ch3_pldif_rx_clkout1_divider DIV2
ch3_pldif_rx_clkout2_divider DIV2
ch3_pldif_channel_identifier GENERIC
ch3_pldif_sf_en ENABLED
ch3_pldif_loopback_mode NO_LOOPBACK
ch3_pcs_loopback_mode NO_LOOPBACK
ch3_pcs_sf_en ENABLED
ch3_fec_spec DISABLED
ch3_fec_fracture UNUSED
ch3_fec_tx_en FALSE
ch3_fec_rx_en FALSE
ch3_fec_loopback_mode DISABLE
ch3_xcvr_tx_protocol_hint DISABLED
ch3_xcvr_tx_datarate_bps 1105.92
ch3_xcvr_tx_prbs_pattern DISABLE
ch3_xcvr_tx_user_clk_only_mode DISABLE
ch3_xcvr_tx_width 32
ch3_xcvr_rx_protocol_hint DISABLED
ch3_xcvr_rx_datarate_bps 1105.92
ch3_xcvr_rx_prbs_pattern DISABLE
ch3_xcvr_rx_width 32
ch3_xcvr_rx_force_cdr_ltr FALSE
ch3_xcvr_rx_adaptation_mode DISABLED
ch3_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch3_xcvr_cdr_f_ref_hz 184320000
ch3_xcvr_cdr_f_vco_hz 552960000
ch3_rx_postdiv_clk_en ENABLE
ch3_rx_postdiv_clk_divider 100
ch3_tx_postdiv_clk_divider 100
ch3_tx_pll_f_ref_hz 184320000
ch3_tx_pll_f_out_hz 552960000
ch3_tx_pll_refclk_select GLOBAL_REFCLK0
ch3_cdr_refclk_select GLOBAL_REFCLK1
ch3_phy_loopback_mode DISABLED
ch3_flux_mode FLUX_MODE_BYPASS
ch3_flux_mode_hw FLUX_MODE_SNIFFER
ch3_xcvrif_tx_fifo_mode ELASTIC
ch3_xcvrif_rx_fifo_mode ELASTIC
ch3_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch3_tx_pll_frac_mode_en DISABLE
ch3_xcvr_tx_spread_spectrum_en DISABLE
ch3_xcvr_tx_cascade_en DISABLE
ch3_rx_invert_pin DISABLE
ch3_tx_invert_pin DISABLE
ch3_xcvr_rx_cdrdivout_en DISABLE
ch3_xcvr_tx_eq_main_tap 52
ch3_xcvr_tx_eq_post_tap_1 5
ch3_xcvr_tx_eq_pre_tap_1 0
ch3_xcvr_tx_eq_pre_tap_2 0
ch3_tx_pll_feed_forward_gain 197
ch3_xcvr_rx_termination_mode GROUNDED
ch3_xcvr_rx_onchip_termination_setting R_2
ch3_xcvr_rx_eq_vga_gain 0
ch3_xcvr_x_eq_hf_boost 0
ch3_xcvr_rx_eq_dfe_tap_1 0
ch3_xcvr_rx_external_couple_type AC
ch3_sequencer_reg_en DISABLE
ch3_rx_dl_rx_lat_bit_for_async 0
ch3_rx_dl_rxbit_rollover 0
ch3_rx_dl_rxbit_cntr_pma DISABLE
ch3_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0

hal_top_one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0

one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pcs_hal_top

one_lane_hal_pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pcs_hal_top_pcs_hal_top

pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top

one_lane_hal_fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_fec_hal_top_fec_hal_top

fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top

one_lane_hal_pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 0
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_pldif_hal_top_pldif_hal_top

pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 0
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top

one_lane_hal_phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 0
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p0_one_lane_hal_top_p0_phy_hal_top_phy_hal_top

phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 0
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1

hal_top_one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 1
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1

one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 1
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pcs_hal_top

one_lane_hal_pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pcs_hal_top_pcs_hal_top

pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top

one_lane_hal_fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_fec_hal_top_fec_hal_top

fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top

one_lane_hal_pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 1
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_pldif_hal_top_pldif_hal_top

pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 1
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top

one_lane_hal_phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 1
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p1_one_lane_hal_top_p1_phy_hal_top_phy_hal_top

phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 1
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2

hal_top_one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 2
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2

one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 2
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pcs_hal_top

one_lane_hal_pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pcs_hal_top_pcs_hal_top

pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top

one_lane_hal_fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_fec_hal_top_fec_hal_top

fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top

one_lane_hal_pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 2
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_pldif_hal_top_pldif_hal_top

pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 2
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top

one_lane_hal_phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 2
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p2_one_lane_hal_top_p2_phy_hal_top_phy_hal_top

phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 2
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3

hal_top_one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 3
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3

one_lane_hal v21.0.0


Parameters

dr_enable DR_ENABLED
num_of_lanes 4
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
ch_lane_id 3
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_duplex_mode DUPLEX
ch_rate_mode RATE_25G
ch_ptp_mode DISABLED
ch_fec_mode 0
ch_tx_dl_enable DISABLE
ch_rx_dl_enable DISABLE
ch_sup_mode USER_MODE
ch_sim_mode ENABLE
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_bond_size 4
ch_rx_bond_size 1
ch_tx_pcs_mode IEEE
ch_rx_pcs_mode IEEE
ch_syspll_rx_clk_hz 322265625
ch_syspll_tx_clk_hz 322265625
ch_mac_link_fault_mode OFF
ch_mac_remove_pads DISABLE
ch_mac_keep_rx_crc DISABLE
ch_mac_forward_rx_pause_requests DISABLE
ch_mac_source_address_insertion DISABLE
ch_mac_tx_vlan_detection DISABLE
ch_mac_rx_vlan_detection DISABLE
ch_mac_flow_control DISABLE FLOW CONTROL
ch_mac_tx_max_frame_size 65
ch_mac_rx_max_frame_size 65
ch_mac_enforce_max_frame_size DISABLE
ch_mac_tx_preamble_passthrough DISABLE
ch_mac_rx_preamble_passthrough DISABLE
ch_mac_strict_preamble_checking DISABLE
ch_mac_strict_sfd_checking DISABLE
ch_mac_tx_ipg_size 12
ch_mac_ipg_removed_per_am_period 0
ch_mac_custom_cadence DISABLE
ch_ptp0_en DISABLED
ch_ptp1_en DISABLED
ch_mac_sim_mode ENABLE
ch_ptp0_sim_mode ENABLE
ch_ptp1_sim_mode ENABLE
ch_mac_tx_mac_data_flow DISABLE
ch_mac_sf_en DISABLED
ch_ehip_loopback_mode NO_LOOPBACK
ch_mac_txmac_saddr 001122334455
ch_pldif_tx_fifo_mode PHASE_COMP
ch_pldif_tx_fifo_width DOUBLE_WIDTH
ch_pldif_rx_fifo_mode PHASE_COMP
ch_pldif_rx_fifo_width DOUBLE_WIDTH
ch_pldif_tx_clkout1_divider DIV2
ch_pldif_tx_clkout2_divider DIV2
ch_pldif_rx_clkout1_divider DIV2
ch_pldif_rx_clkout2_divider DIV2
ch_pldif_channel_identifier GENERIC
ch_pldif_sf_en ENABLED
ch_pldif_loopback_mode NO_LOOPBACK
ch_pcs_loopback_mode NO_LOOPBACK
ch_pcs_sf_en ENABLED
ch_fec_spec DISABLED
ch_fec_fracture UNUSED
ch_fec_sf_en DISABLED
ch_fec_tx_en FALSE
ch_fec_rx_en FALSE
ch_fec_loopback_mode DISABLE
ch_xcvr_tx_protocol_hint DISABLED
ch_xcvr_tx_datarate_bps 1105.92
ch_xcvr_tx_prbs_pattern DISABLE
ch_xcvr_tx_user_clk_only_mode DISABLE
ch_xcvr_tx_width 32
ch_xcvr_rx_protocol_hint DISABLED
ch_xcvr_rx_datarate_bps 1105.92
ch_xcvr_rx_prbs_pattern DISABLE
ch_xcvr_rx_width 32
ch_xcvr_rx_force_cdr_ltr FALSE
ch_xcvr_rx_adaptation_mode DISABLED
ch_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_xcvr_cdr_f_ref_hz 184320000
ch_xcvr_cdr_f_vco_hz 552960000
ch_rx_postdiv_clk_en ENABLE
ch_rx_postdiv_clk_divider 100
ch_tx_postdiv_clk_divider 100
ch_tx_pll_f_ref_hz 184320000
ch_tx_pll_f_out_hz 552960000
ch_tx_pll_refclk_select GLOBAL_REFCLK0
ch_cdr_refclk_select GLOBAL_REFCLK1
ch_phy_loopback_mode DISABLED
ch_flux_mode FLUX_MODE_BYPASS
ch_flux_mode_hw FLUX_MODE_SNIFFER
ch_xcvrif_tx_fifo_mode ELASTIC
ch_xcvrif_rx_fifo_mode ELASTIC
ch_xcvrif_rx_word_clk_dynamic_mux SEL_RXWORD_CLK
ch_xcvr_tx_spread_spectrum_en DISABLE
ch_tx_pll_frac_mode_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_xcvr_rx_cdrdivout_en DISABLE
ch_xcvr_tx_eq_main_tap 52
ch_xcvr_tx_eq_post_tap_1 5
ch_xcvr_tx_eq_pre_tap_1 0
ch_xcvr_tx_eq_pre_tap_2 0
ch_tx_pll_feed_forward_gain 197
ch_xcvr_rx_termination_mode GROUNDED
ch_xcvr_rx_onchip_termination_setting R_2
ch_xcvr_rx_eq_vga_gain 0
ch_xcvr_x_eq_hf_boost 0
ch_xcvr_rx_eq_dfe_tap_1 0
ch_xcvr_rx_external_couple_type AC
ch_flux_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
ch_SF_PCS_TXMUX_EN ENABLED
ch_SF_PCS_RXMUX_EN ENABLED
ch_SF_FEC_TXMUX_EN ENABLED
ch_SF_FEC_INGRESS_EN ENABLED
ch_SF_FEC_EGRESS_EN ENABLED
ch_SF_PLDCH_TX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_TX_USER2_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER1_MUX_EN ENABLED
ch_SF_PLDCH_RX_USER2_MUX_EN ENABLED
ch_SF_DESKEW_EN ENABLED
ch_SF_DESKEW_RXMUX_EN ENABLED
ch_SF_PTP_INGRESS_EN ENABLED
ch_SF_PTP_EGRESS_EN ENABLED
ch_SF_PTP_S_EN ENABLED
ch_SF_PTP_EN ENABLED
ch_SF_UX_EN ENABLED
ch_SF_FLUX_GLOBAL_MEM_EN ENABLED
ch_SF_FLUX_S_EN ENABLED
ch_SF_FLUX_TXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_TXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK1_MUX_EN ENABLED
ch_SF_FLUX_RXUSER_CLK2_MUX_EN ENABLED
ch_SF_FLUX_I_EN ENABLED
ch_SF_UX_TOOLBOX_EN ENABLED
ch_SF_FLUX_CORE_EN ENABLED
ch_SF_XCVRIF_1CH_EN ENABLED
ch_SF_XCVRIF_TXMUX_EN ENABLED
ch_SF_XCRIF_TX_RST_MUX_EN ENABLED
ch_SF_XCRIF_TX_WREN_MUX_EN ENABLED
ch_SF_XCRIF_TX_RDEN_MUX_EN ENABLED
ch_SF_XCRIF_TXWORD_CLK_MUX_EN ENABLED
ch_SF_XCRIF_RXWORD_CLK_MUX_EN ENABLED
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pcs_hal_top

one_lane_hal_pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pcs_hal_top_pcs_hal_top

pcs_hal v21.0.0


Parameters

ch_pcs_l_duplex_mode DUPLEX
ch_pcs_l_loopback_mode NO_LOOPBACK
ch_pcs_l_fec_tx_en FALSE
ch_pcs_l_fec_rx_en FALSE
ch_pcs_dr_enabled DR_ENABLED
ch_pcs_l_tx_pcs_mode IEEE
ch_pcs_l_rx_pcs_mode IEEE
ch_pcs_l_rate_mode RATE_25G
ch_pcs_l_sup_mode USER_MODE
ch_pcs_l_sim_mode ENABLE
ch_pcs_l_tx_en TRUE
ch_pcs_l_rx_en TRUE
ch_pcs_l_fec_mode 0
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top

one_lane_hal_fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_fec_hal_top_fec_hal_top

fec_hal v21.0.0


Parameters

ch_fec_l_duplex_mode DUPLEX
ch_fec_l_fec_spec DISABLED
ch_fec_l_fracture UNUSED
ch_fec_l_fec_mode 0
ch_fec_l_tx_en FALSE
ch_fec_l_rx_en FALSE
ch_fec_dr_enabled DR_ENABLED
ch_fec_l_sup_mode USER_MODE
ch_fec_l_sim_mode ENABLE
ch_fec_l_loopback_mode DISABLE
ch_fec_l_pcs_tx_en FALSE
ch_fec_l_pcs_rx_en TRUE
ch_tx_Channel_mode PCSD
ch_rx_Channel_mode PCSD
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top

one_lane_hal_pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 3
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_pldif_hal_top_pldif_hal_top

pldif_hal v21.0.0


Parameters

device_die_type MAIN_SM7
ch_pldif_l_tx_en TRUE
ch_pldif_l_rx_en TRUE
ch_pldif_l_duplex_mode DUPLEX
ch_pldif_l_tx_fifo_mode PHASE_COMP
ch_pldif_l_tx_fifo_width DOUBLE_WIDTH
ch_pldif_l_rx_fifo_mode PHASE_COMP
ch_pldif_l_rx_fifo_width DOUBLE_WIDTH
ch_pldif_l_tx_clkout1_divider DIV2
ch_pldif_l_tx_clkout2_divider DIV2
ch_pldif_l_rx_clkout1_divider DIV2
ch_pldif_l_rx_clkout2_divider DIV2
ch_pldif_l_dr_enabled DR_ENABLED
ch_pcs_l_tx_bond_size 4
ch_pcs_l_rx_bond_size 1
ch_pldif_l_ptp_enable DISABLE
ch_pldif_l_tx_user1_clk_dynamic_mux C0
ch_pldif_l_tx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_rx_user1_clk_dynamic_mux C0
ch_pldif_l_rx_user2_clk_dynamic_mux UNUSED
ch_pldif_l_sup_mode USER_MODE
ch_pldif_l_tx_mac_en FALSE
ch_pldif_loopback_mode NO_LOOPBACK
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_lane_id 3
num_of_lanes 4
ch_pldif_channel_identifier GENERIC
ch_pldif_rx_fifo_wr_clk_hz 322265625
ch_pldif_tx_fifo_rd_clk_hz 322265625
ch_mac_mode IEEE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top

one_lane_hal_phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 3
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

intel_directphy_gts_x4_n_channel_superset_top_wrapper_n_channel_superset_top_wrapper_hal_top_ip_hal_top_ip_one_lane_hal_top_p3_one_lane_hal_top_p3_phy_hal_top_phy_hal_top

phy_hal v21.0.0


Parameters

tx_pll_fout_hz 552.960000
tx_pll_vco_MHz 8847.360000
tx_pll_cascade_enable 0
tx_pll_frac_mode_enable 0
tx_pll_refclk_freq_mhz 184.320000
tx_pll_refclk_freq_itxt 82.500000
rx_pll_fout_hz 552.960000
rx_pll_vco_MHz 8847.360000
rx_pll_refclk_freq_otxt 327.680000
dr_enable DR_ENABLED
device_die_type MAIN_SM7
device_die_revisions MAIN_SM7_REVA
num_of_lanes 4
ch_lane_id 3
ch_tx_user1_clk_dynamic_mux PLL_C0
ch_tx_user2_clk_dynamic_mux DISABLED
ch_rx_user1_clk_dynamic_mux PLL_C0
ch_rx_user2_clk_dynamic_mux DISABLED
ch_tx_channel_mode PCSD
ch_rx_channel_mode PCSD
ch_l_xcvr_tx_preloaded_hardware_configs NONE
ch_l_xcvr_tx_protocol_hint DISABLED
ch_l_xcvr_tx_datarate_bps 1105.92
ch_l_xcvr_tx_prbs_gen_en DISABLE
ch_l_xcvr_tx_prbs_pattern DISABLE
ch_l_xcvr_tx_bond_size X4
ch_l_xcvr_tx_user_clk_only_mode DISABLE
ch_l_xcvr_tx_width X32
ch_l_xcvr_tx_dl_enable DISABLE
ch_l_xcvr_rx_preloaded_hardware_configs NONE
ch_l_xcvr_rx_protocol_hint DISABLED
ch_l_xcvr_rx_datarate_bps 1105.92
ch_l_xcvr_rx_prbs_monitor_en DISABLE
ch_l_xcvr_rx_prbs_pattern DISABLE
ch_l_xcvr_rx_width X32
ch_l_xcvr_rx_force_cdr_ltr FALSE
ch_l_xcvr_rx_adaptation_mode DISABLED
ch_l_xcvr_rx_adaptation_mode_hw FLUX_ADAPTATION
ch_l_xcvr_rx_dl_enable DISABLE
ch_l_xcvr_cdr_f_ref_hz_false 184320000
ch_l_xcvr_cdr_f_vco_hz_false 552960000
ch_l_rx_postdiv_clk_en ENABLE
ch_l_rx_postdiv_clk_divider 100
ch_l_tx_pll_f_ref_hz_false 184320000
ch_l_tx_pll_f_out_hz_false 552960000
ch_l_tx_postdiv_clk_divider 100
ch_l_tx_pll_refclk_select GLOBAL_REFCLK0
ch_l_cdr_refclk_select GLOBAL_REFCLK1
ch_l_loopback_mode DISABLED
ch_flux_l_flux_mode FLUX_MODE_BYPASS
ch_flux_l_flux_mode_hw FLUX_MODE_SNIFFER
ch_flux_l_rx_protocol_hint DISABLED
ch_flux_l_tx_dl_enable DISABLE
ch_flux_l_rx_dl_enable DISABLE
ch_xcvrif_l_tx_dl_enable DISABLE
ch_xcvrif_l_rx_dl_enable DISABLE
ch_xcvrif_l_loopback_mode DISABLED
ch_xcvrif_l_tx_fifo_mode ELASTIC
ch_xcvrif_l_rx_fifo_mode ELASTIC
ch_xcvrif_l_tx_bond_size X4
ch_xcvrif_l_rx_bond_size X1
ch_l_xcvr_tx_en TRUE
ch_l_xcvr_rx_en TRUE
ch_l_duplex_mode DUPLEX
ch_xcvrif_l_tx_en TRUE
ch_xcvrif_l_rx_en TRUE
ch_xcvrif_l_duplex_mode DUPLEX
ch_flux_l_rx_fec_type_used DISABLED
ch_l_sim_mode ENABLE
ch_flux_l_rx_sim_mode ENABLE
ch_flux_l_tx_sim_mode ENABLE
ch_flux_l_dr_enabled DR_ENABLED
ch_xcvrif_l_sup_mode USER_MODE
ch_xcvrif_l_sim_mode ENABLE
ch_xcvrif_l_dr_enabled DR_ENABLED
ch_tx_pll_frac_mode_en DISABLE
ch_l_xcvr_tx_spread_spectrum_en DISABLE
ch_xcvr_tx_cascade_en DISABLE
ch_rx_invert_pin DISABLE
ch_tx_invert_pin DISABLE
ch_eth_rx_clk_hz 322265625
ch_eth_tx_clk_hz 322265625
ch_l_xcvr_rx_cdrdivout_en DISABLE
ch_l_xcvr_tx_eq_main_tap 52
ch_l_xcvr_tx_eq_post_tap_1 5
ch_l_xcvr_tx_eq_pre_tap_1 0
ch_l_xcvr_tx_eq_pre_tap_2 0
ch_l_tx_pll_feed_forward_gain 197
ch_l_xcvr_rx_termination_mode GROUNDED
ch_l_xcvr_rx_onchip_termination_setting R_2
ch_l_xcvr_rx_eq_vga_gain 0
ch_l_xcvr_x_eq_hf_boost 0
ch_l_xcvr_rx_eq_dfe_tap_1 0
ch_l_xcvr_rx_external_couple_type AC
ch_flux_l_sequencer_reg_en DISABLE
ch_rx_dl_rx_lat_bit_for_async 0
ch_rx_dl_rxbit_rollover 0
ch_rx_dl_rxbit_cntr_pma DISABLE
ch_hw_fec 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
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