EMIF_Qsys |
|
2025.02.03.09:32:59 | Datasheet |
emif_ddr4a |
s0_axi4 |
s0_axi4lite |
emif_ddr4b |
s0_axi4 |
s0_axi4lite |
iopll | outclk0 | clock_310m |
in_clk |
Parameters
|
Software Assignments(none) |
iopll | outclk0 | emif_ddr4a |
s0_axi4_clock_in | ||
reset_bridge | out_reset | |
core_init_n |
Parameters
|
Software Assignments(none) |
iopll | outclk0 | emif_ddr4b |
s0_axi4_clock_in | ||
reset_bridge | out_reset | |
core_init_n |
Parameters
|
Software Assignments(none) |
Parameters
|
Software Assignments(none) |
iopll | outclk0 | reset_bridge | |
clk | |||
out_reset | emif_ddr4a | ||
core_init_n | |||
out_reset | emif_ddr4b | ||
core_init_n |
Parameters
|
Software Assignments(none) |
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