num_of_lanes |
4 |
dr_enable |
DR_ENABLED |
SRC_SIM_SCALE_DOWN |
0 |
device_die_type |
MAIN_SM7 |
device_die_revisions |
MAIN_SM7_REVA |
ch0_lane_id |
0 |
ch0_tx_channel_mode |
PCSD |
ch0_rx_channel_mode |
PCSD |
ch0_duplex_mode |
DUPLEX |
ch0_rate_mode |
RATE_25G |
ch0_ptp_mode |
DISABLED |
ch0_fec_mode |
0 |
ch0_tx_dl_enable |
DISABLE |
ch0_rx_dl_enable |
DISABLE |
ch0_sup_mode |
USER_MODE |
ch0_sim_mode |
ENABLE |
ch0_syspll_rx_clk_hz |
322265625 |
ch0_syspll_tx_clk_hz |
322265625 |
ch0_tx_user1_clk_dynamic_mux |
PLL_C0 |
ch0_tx_user2_clk_dynamic_mux |
DISABLED |
ch0_rx_user1_clk_dynamic_mux |
PLL_C0 |
ch0_rx_user2_clk_dynamic_mux |
DISABLED |
ch0_tx_bond_size |
4 |
ch0_rx_bond_size |
1 |
ch0_xcvr_tx_protocol_hint |
DISABLED |
ch0_xcvr_tx_datarate_bps |
1105.92 |
ch0_xcvr_tx_prbs_pattern |
DISABLE |
ch0_xcvr_tx_user_clk_only_mode |
DISABLE |
ch0_xcvr_tx_width |
32 |
ch0_xcvr_rx_protocol_hint |
DISABLED |
ch0_xcvr_rx_datarate_bps |
1105.92 |
ch0_xcvr_rx_prbs_pattern |
DISABLE |
ch0_xcvr_rx_width |
32 |
ch0_xcvr_rx_force_cdr_ltr |
FALSE |
ch0_xcvr_rx_adaptation_mode |
DISABLED |
ch0_xcvr_rx_adaptation_mode_hw |
FLUX_ADAPTATION |
ch0_xcvr_cdr_f_ref_hz |
184320000 |
ch0_xcvr_cdr_f_vco_hz |
552960000 |
ch0_rx_postdiv_clk_en |
ENABLE |
ch0_rx_postdiv_clk_divider |
100 |
ch0_tx_postdiv_clk_divider |
100 |
ch0_tx_pll_f_ref_hz |
184320000 |
ch0_tx_pll_f_out_hz |
552960000 |
ch0_tx_pll_refclk_select |
GLOBAL_REFCLK0 |
ch0_cdr_refclk_select |
GLOBAL_REFCLK1 |
ch0_phy_loopback_mode |
DISABLED |
ch0_flux_mode |
FLUX_MODE_BYPASS |
ch0_flux_mode_hw |
FLUX_MODE_SNIFFER |
ch0_xcvrif_tx_fifo_mode |
ELASTIC |
ch0_xcvrif_rx_fifo_mode |
ELASTIC |
ch0_xcvrif_rx_word_clk_dynamic_mux |
SEL_RXWORD_CLK |
ch0_xcvr_tx_spread_spectrum_en |
DISABLE |
ch0_xcvr_tx_cascade_en |
DISABLE |
ch0_tx_pcs_mode |
IEEE |
ch0_rx_pcs_mode |
IEEE |
ch0_mac_link_fault_mode |
OFF |
ch0_mac_remove_pads |
DISABLE |
ch0_mac_keep_rx_crc |
DISABLE |
ch0_mac_forward_rx_pause_requests |
DISABLE |
ch0_mac_source_address_insertion |
DISABLE |
ch0_mac_tx_vlan_detection |
DISABLE |
ch0_mac_rx_vlan_detection |
DISABLE |
ch0_mac_flow_control |
DISABLE FLOW CONTROL |
ch0_mac_tx_max_frame_size |
65 |
ch0_mac_rx_max_frame_size |
65 |
ch0_mac_enforce_max_frame_size |
DISABLE |
ch0_mac_tx_preamble_passthrough |
DISABLE |
ch0_mac_rx_preamble_passthrough |
DISABLE |
ch0_mac_strict_preamble_checking |
DISABLE |
ch0_mac_strict_sfd_checking |
DISABLE |
ch0_mac_tx_ipg_size |
12 |
ch0_mac_ipg_removed_per_am_period |
0 |
ch0_mac_custom_cadence |
DISABLE |
ch0_ptp0_en |
DISABLED |
ch0_ptp1_en |
DISABLED |
ch0_mac_sim_mode |
ENABLE |
ch0_ptp0_sim_mode |
ENABLE |
ch0_ptp1_sim_mode |
ENABLE |
ch0_mac_tx_mac_data_flow |
DISABLE |
ch0_mac_sf_en |
DISABLED |
ch0_ehip_loopback_mode |
NO_LOOPBACK |
ch0_mac_txmac_saddr |
001122334455 |
ch0_pldif_tx_fifo_mode |
PHASE_COMP |
ch0_pldif_tx_fifo_width |
DOUBLE_WIDTH |
ch0_pldif_rx_fifo_mode |
PHASE_COMP |
ch0_pldif_rx_fifo_width |
DOUBLE_WIDTH |
ch0_pldif_tx_clkout1_divider |
DIV2 |
ch0_pldif_tx_clkout2_divider |
DIV2 |
ch0_pldif_rx_clkout1_divider |
DIV2 |
ch0_pldif_rx_clkout2_divider |
DIV2 |
ch0_pldif_channel_identifier |
GENERIC |
ch0_pldif_sf_en |
ENABLED |
ch0_pldif_loopback_mode |
NO_LOOPBACK |
ch0_pcs_loopback_mode |
NO_LOOPBACK |
ch0_pcs_sf_en |
ENABLED |
ch0_fec_spec |
DISABLED |
ch0_fec_fracture |
UNUSED |
ch0_fec_tx_en |
FALSE |
ch0_fec_rx_en |
FALSE |
ch0_fec_loopback_mode |
DISABLE |
ch0_tx_pll_frac_mode_en |
DISABLE |
ch0_rx_invert_pin |
DISABLE |
ch0_tx_invert_pin |
DISABLE |
ch0_xcvr_rx_cdrdivout_en |
DISABLE |
ch0_xcvr_tx_eq_main_tap |
52 |
ch0_xcvr_tx_eq_post_tap_1 |
5 |
ch0_xcvr_tx_eq_pre_tap_1 |
0 |
ch0_xcvr_tx_eq_pre_tap_2 |
0 |
ch0_tx_pll_feed_forward_gain |
197 |
ch0_xcvr_rx_termination_mode |
GROUNDED |
ch0_xcvr_rx_onchip_termination_setting |
R_2 |
ch0_xcvr_rx_eq_vga_gain |
0 |
ch0_xcvr_x_eq_hf_boost |
0 |
ch0_xcvr_rx_eq_dfe_tap_1 |
0 |
ch0_xcvr_rx_external_couple_type |
AC |
ch0_sequencer_reg_en |
DISABLE |
ch0_rx_dl_rx_lat_bit_for_async |
0 |
ch0_rx_dl_rxbit_rollover |
0 |
ch0_rx_dl_rxbit_cntr_pma |
DISABLE |
ch0_hw_fec |
0 |
CH0_SRC_TX_ENABLE |
1 |
CH0_SRC_RX_ENABLE |
1 |
CH0_SRC_TX_INITIATOR |
1 |
CH0_SRC_RX_INITIATOR |
1 |
CH0_SRC_TX_INITIATOR_INDEX |
0 |
CH0_SRC_RX_INITIATOR_INDEX |
0 |
CH0_SRC_TX_TARGET_ENABLE |
14 |
CH0_SRC_RX_TARGET_ENABLE |
14 |
CH0_SRC_TX_LANE_FUCTIONAL_MODE |
3 |
CH0_SRC_RX_LANE_FUCTIONAL_MODE |
3 |
CH0_SRC_NON_PTP_CHANNEL |
1 |
CH0_SRC_TX_PCS_EN |
1 |
CH0_SRC_RX_PCS_EN |
1 |
CH0_SRC_UX_EN |
1 |
CH0_SRC_TX_DL_EN |
0 |
CH0_SRC_RX_DL_EN |
0 |
CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION |
0 |
CH0_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW |
1 |
CH0_SRC_PTP_EN |
0 |
CH0_SRC_TX_FEC_EN |
0 |
CH0_SRC_RX_FEC_EN |
0 |
CH0_SRC_ETHERNET_SYSPLL_CLK_MODE |
1 |
CH0_SRC_UX_USING_SYSPLL_CLK |
0 |
CH0_SRC_FLUX_USING_SYSPLL_CLK |
0 |
CH0_SRC_FLUX_EN |
0 |
CH0_SRC_FLUX_EN_HW |
1 |
CH0_SRC_SRC_LANE_INDEX |
0 |
CH0_SRC_LEADER_LANE |
1 |
ch1_lane_id |
1 |
ch1_tx_channel_mode |
PCSD |
ch1_rx_channel_mode |
PCSD |
ch1_duplex_mode |
DUPLEX |
ch1_rate_mode |
RATE_25G |
ch1_ptp_mode |
DISABLED |
ch1_fec_mode |
0 |
ch1_tx_dl_enable |
DISABLE |
ch1_rx_dl_enable |
DISABLE |
ch1_sup_mode |
USER_MODE |
ch1_sim_mode |
ENABLE |
ch1_syspll_rx_clk_hz |
322265625 |
ch1_syspll_tx_clk_hz |
322265625 |
ch1_tx_user1_clk_dynamic_mux |
PLL_C0 |
ch1_tx_user2_clk_dynamic_mux |
DISABLED |
ch1_rx_user1_clk_dynamic_mux |
PLL_C0 |
ch1_rx_user2_clk_dynamic_mux |
DISABLED |
ch1_tx_bond_size |
4 |
ch1_rx_bond_size |
1 |
ch1_xcvr_tx_protocol_hint |
DISABLED |
ch1_xcvr_tx_datarate_bps |
1105.92 |
ch1_xcvr_tx_prbs_pattern |
DISABLE |
ch1_xcvr_tx_user_clk_only_mode |
DISABLE |
ch1_xcvr_tx_width |
32 |
ch1_xcvr_rx_protocol_hint |
DISABLED |
ch1_xcvr_rx_datarate_bps |
1105.92 |
ch1_xcvr_rx_prbs_pattern |
DISABLE |
ch1_xcvr_rx_width |
32 |
ch1_xcvr_rx_force_cdr_ltr |
FALSE |
ch1_xcvr_rx_adaptation_mode |
DISABLED |
ch1_xcvr_rx_adaptation_mode_hw |
FLUX_ADAPTATION |
ch1_xcvr_cdr_f_ref_hz |
184320000 |
ch1_xcvr_cdr_f_vco_hz |
552960000 |
ch1_rx_postdiv_clk_en |
ENABLE |
ch1_rx_postdiv_clk_divider |
100 |
ch1_tx_postdiv_clk_divider |
100 |
ch1_tx_pll_f_ref_hz |
184320000 |
ch1_tx_pll_f_out_hz |
552960000 |
ch1_tx_pll_refclk_select |
GLOBAL_REFCLK0 |
ch1_cdr_refclk_select |
GLOBAL_REFCLK1 |
ch1_phy_loopback_mode |
DISABLED |
ch1_flux_mode |
FLUX_MODE_BYPASS |
ch1_flux_mode_hw |
FLUX_MODE_SNIFFER |
ch1_xcvrif_tx_fifo_mode |
ELASTIC |
ch1_xcvrif_rx_fifo_mode |
ELASTIC |
ch1_xcvrif_rx_word_clk_dynamic_mux |
SEL_RXWORD_CLK |
ch1_xcvr_tx_spread_spectrum_en |
DISABLE |
ch1_xcvr_tx_cascade_en |
DISABLE |
ch1_tx_pcs_mode |
IEEE |
ch1_rx_pcs_mode |
IEEE |
ch1_mac_link_fault_mode |
OFF |
ch1_mac_remove_pads |
DISABLE |
ch1_mac_keep_rx_crc |
DISABLE |
ch1_mac_forward_rx_pause_requests |
DISABLE |
ch1_mac_source_address_insertion |
DISABLE |
ch1_mac_tx_vlan_detection |
DISABLE |
ch1_mac_rx_vlan_detection |
DISABLE |
ch1_mac_flow_control |
DISABLE FLOW CONTROL |
ch1_mac_tx_max_frame_size |
65 |
ch1_mac_rx_max_frame_size |
65 |
ch1_mac_enforce_max_frame_size |
DISABLE |
ch1_mac_tx_preamble_passthrough |
DISABLE |
ch1_mac_rx_preamble_passthrough |
DISABLE |
ch1_mac_strict_preamble_checking |
DISABLE |
ch1_mac_strict_sfd_checking |
DISABLE |
ch1_mac_tx_ipg_size |
12 |
ch1_mac_ipg_removed_per_am_period |
0 |
ch1_mac_custom_cadence |
DISABLE |
ch1_ptp0_en |
DISABLED |
ch1_ptp1_en |
DISABLED |
ch1_mac_sim_mode |
ENABLE |
ch1_ptp0_sim_mode |
ENABLE |
ch1_ptp1_sim_mode |
ENABLE |
ch1_mac_tx_mac_data_flow |
DISABLE |
ch1_mac_sf_en |
DISABLED |
ch1_ehip_loopback_mode |
NO_LOOPBACK |
ch1_mac_txmac_saddr |
001122334455 |
ch1_pldif_tx_fifo_mode |
PHASE_COMP |
ch1_pldif_tx_fifo_width |
DOUBLE_WIDTH |
ch1_pldif_rx_fifo_mode |
PHASE_COMP |
ch1_pldif_rx_fifo_width |
DOUBLE_WIDTH |
ch1_pldif_tx_clkout1_divider |
DIV2 |
ch1_pldif_tx_clkout2_divider |
DIV2 |
ch1_pldif_rx_clkout1_divider |
DIV2 |
ch1_pldif_rx_clkout2_divider |
DIV2 |
ch1_pldif_channel_identifier |
GENERIC |
ch1_pldif_sf_en |
ENABLED |
ch1_pldif_loopback_mode |
NO_LOOPBACK |
ch1_pcs_loopback_mode |
NO_LOOPBACK |
ch1_pcs_sf_en |
ENABLED |
ch1_fec_spec |
DISABLED |
ch1_fec_fracture |
UNUSED |
ch1_fec_tx_en |
FALSE |
ch1_fec_rx_en |
FALSE |
ch1_fec_loopback_mode |
DISABLE |
ch1_tx_pll_frac_mode_en |
DISABLE |
ch1_rx_invert_pin |
DISABLE |
ch1_tx_invert_pin |
DISABLE |
ch1_xcvr_rx_cdrdivout_en |
DISABLE |
ch1_xcvr_tx_eq_main_tap |
52 |
ch1_xcvr_tx_eq_post_tap_1 |
5 |
ch1_xcvr_tx_eq_pre_tap_1 |
0 |
ch1_xcvr_tx_eq_pre_tap_2 |
0 |
ch1_tx_pll_feed_forward_gain |
197 |
ch1_xcvr_rx_termination_mode |
GROUNDED |
ch1_xcvr_rx_onchip_termination_setting |
R_2 |
ch1_xcvr_rx_eq_vga_gain |
0 |
ch1_xcvr_x_eq_hf_boost |
0 |
ch1_xcvr_rx_eq_dfe_tap_1 |
0 |
ch1_xcvr_rx_external_couple_type |
AC |
ch1_sequencer_reg_en |
DISABLE |
ch1_rx_dl_rx_lat_bit_for_async |
0 |
ch1_rx_dl_rxbit_rollover |
0 |
ch1_rx_dl_rxbit_cntr_pma |
DISABLE |
ch1_hw_fec |
0 |
CH1_SRC_TX_ENABLE |
1 |
CH1_SRC_RX_ENABLE |
1 |
CH1_SRC_TX_INITIATOR |
0 |
CH1_SRC_RX_INITIATOR |
0 |
CH1_SRC_TX_INITIATOR_INDEX |
0 |
CH1_SRC_RX_INITIATOR_INDEX |
0 |
CH1_SRC_TX_TARGET_ENABLE |
0 |
CH1_SRC_RX_TARGET_ENABLE |
0 |
CH1_SRC_TX_LANE_FUCTIONAL_MODE |
3 |
CH1_SRC_RX_LANE_FUCTIONAL_MODE |
3 |
CH1_SRC_NON_PTP_CHANNEL |
1 |
CH1_SRC_TX_PCS_EN |
1 |
CH1_SRC_RX_PCS_EN |
1 |
CH1_SRC_UX_EN |
1 |
CH1_SRC_TX_DL_EN |
0 |
CH1_SRC_RX_DL_EN |
0 |
CH1_SRC_FLUX_USED_FOR_RX_ADAPTATION |
0 |
CH1_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW |
1 |
CH1_SRC_PTP_EN |
0 |
CH1_SRC_TX_FEC_EN |
0 |
CH1_SRC_RX_FEC_EN |
0 |
CH1_SRC_ETHERNET_SYSPLL_CLK_MODE |
1 |
CH1_SRC_UX_USING_SYSPLL_CLK |
0 |
CH1_SRC_FLUX_USING_SYSPLL_CLK |
0 |
CH1_SRC_FLUX_EN |
0 |
CH1_SRC_FLUX_EN_HW |
1 |
CH1_SRC_SRC_LANE_INDEX |
1 |
CH1_SRC_LEADER_LANE |
0 |
ch2_lane_id |
2 |
ch2_tx_channel_mode |
PCSD |
ch2_rx_channel_mode |
PCSD |
ch2_duplex_mode |
DUPLEX |
ch2_rate_mode |
RATE_25G |
ch2_ptp_mode |
DISABLED |
ch2_fec_mode |
0 |
ch2_tx_dl_enable |
DISABLE |
ch2_rx_dl_enable |
DISABLE |
ch2_sup_mode |
USER_MODE |
ch2_sim_mode |
ENABLE |
ch2_syspll_rx_clk_hz |
322265625 |
ch2_syspll_tx_clk_hz |
322265625 |
ch2_tx_user1_clk_dynamic_mux |
PLL_C0 |
ch2_tx_user2_clk_dynamic_mux |
DISABLED |
ch2_rx_user1_clk_dynamic_mux |
PLL_C0 |
ch2_rx_user2_clk_dynamic_mux |
DISABLED |
ch2_tx_bond_size |
4 |
ch2_rx_bond_size |
1 |
ch2_xcvr_tx_protocol_hint |
DISABLED |
ch2_xcvr_tx_datarate_bps |
1105.92 |
ch2_xcvr_tx_prbs_pattern |
DISABLE |
ch2_xcvr_tx_user_clk_only_mode |
DISABLE |
ch2_xcvr_tx_width |
32 |
ch2_xcvr_rx_protocol_hint |
DISABLED |
ch2_xcvr_rx_datarate_bps |
1105.92 |
ch2_xcvr_rx_prbs_pattern |
DISABLE |
ch2_xcvr_rx_width |
32 |
ch2_xcvr_rx_force_cdr_ltr |
FALSE |
ch2_xcvr_rx_adaptation_mode |
DISABLED |
ch2_xcvr_rx_adaptation_mode_hw |
FLUX_ADAPTATION |
ch2_xcvr_cdr_f_ref_hz |
184320000 |
ch2_xcvr_cdr_f_vco_hz |
552960000 |
ch2_rx_postdiv_clk_en |
ENABLE |
ch2_rx_postdiv_clk_divider |
100 |
ch2_tx_postdiv_clk_divider |
100 |
ch2_tx_pll_f_ref_hz |
184320000 |
ch2_tx_pll_f_out_hz |
552960000 |
ch2_tx_pll_refclk_select |
GLOBAL_REFCLK0 |
ch2_cdr_refclk_select |
GLOBAL_REFCLK1 |
ch2_phy_loopback_mode |
DISABLED |
ch2_flux_mode |
FLUX_MODE_BYPASS |
ch2_flux_mode_hw |
FLUX_MODE_SNIFFER |
ch2_xcvrif_tx_fifo_mode |
ELASTIC |
ch2_xcvrif_rx_fifo_mode |
ELASTIC |
ch2_xcvrif_rx_word_clk_dynamic_mux |
SEL_RXWORD_CLK |
ch2_xcvr_tx_spread_spectrum_en |
DISABLE |
ch2_xcvr_tx_cascade_en |
DISABLE |
ch2_tx_pcs_mode |
IEEE |
ch2_rx_pcs_mode |
IEEE |
ch2_mac_link_fault_mode |
OFF |
ch2_mac_remove_pads |
DISABLE |
ch2_mac_keep_rx_crc |
DISABLE |
ch2_mac_forward_rx_pause_requests |
DISABLE |
ch2_mac_source_address_insertion |
DISABLE |
ch2_mac_tx_vlan_detection |
DISABLE |
ch2_mac_rx_vlan_detection |
DISABLE |
ch2_mac_flow_control |
DISABLE FLOW CONTROL |
ch2_mac_tx_max_frame_size |
65 |
ch2_mac_rx_max_frame_size |
65 |
ch2_mac_enforce_max_frame_size |
DISABLE |
ch2_mac_tx_preamble_passthrough |
DISABLE |
ch2_mac_rx_preamble_passthrough |
DISABLE |
ch2_mac_strict_preamble_checking |
DISABLE |
ch2_mac_strict_sfd_checking |
DISABLE |
ch2_mac_tx_ipg_size |
12 |
ch2_mac_ipg_removed_per_am_period |
0 |
ch2_mac_custom_cadence |
DISABLE |
ch2_ptp0_en |
DISABLED |
ch2_ptp1_en |
DISABLED |
ch2_mac_sim_mode |
ENABLE |
ch2_ptp0_sim_mode |
ENABLE |
ch2_ptp1_sim_mode |
ENABLE |
ch2_mac_tx_mac_data_flow |
DISABLE |
ch2_mac_sf_en |
DISABLED |
ch2_ehip_loopback_mode |
NO_LOOPBACK |
ch2_mac_txmac_saddr |
001122334455 |
ch2_pldif_tx_fifo_mode |
PHASE_COMP |
ch2_pldif_tx_fifo_width |
DOUBLE_WIDTH |
ch2_pldif_rx_fifo_mode |
PHASE_COMP |
ch2_pldif_rx_fifo_width |
DOUBLE_WIDTH |
ch2_pldif_tx_clkout1_divider |
DIV2 |
ch2_pldif_tx_clkout2_divider |
DIV2 |
ch2_pldif_rx_clkout1_divider |
DIV2 |
ch2_pldif_rx_clkout2_divider |
DIV2 |
ch2_pldif_channel_identifier |
GENERIC |
ch2_pldif_sf_en |
ENABLED |
ch2_pldif_loopback_mode |
NO_LOOPBACK |
ch2_pcs_loopback_mode |
NO_LOOPBACK |
ch2_pcs_sf_en |
ENABLED |
ch2_fec_spec |
DISABLED |
ch2_fec_fracture |
UNUSED |
ch2_fec_tx_en |
FALSE |
ch2_fec_rx_en |
FALSE |
ch2_fec_loopback_mode |
DISABLE |
ch2_tx_pll_frac_mode_en |
DISABLE |
ch2_rx_invert_pin |
DISABLE |
ch2_tx_invert_pin |
DISABLE |
ch2_xcvr_rx_cdrdivout_en |
DISABLE |
ch2_xcvr_tx_eq_main_tap |
52 |
ch2_xcvr_tx_eq_post_tap_1 |
5 |
ch2_xcvr_tx_eq_pre_tap_1 |
0 |
ch2_xcvr_tx_eq_pre_tap_2 |
0 |
ch2_tx_pll_feed_forward_gain |
197 |
ch2_xcvr_rx_termination_mode |
GROUNDED |
ch2_xcvr_rx_onchip_termination_setting |
R_2 |
ch2_xcvr_rx_eq_vga_gain |
0 |
ch2_xcvr_x_eq_hf_boost |
0 |
ch2_xcvr_rx_eq_dfe_tap_1 |
0 |
ch2_xcvr_rx_external_couple_type |
AC |
ch2_sequencer_reg_en |
DISABLE |
ch2_rx_dl_rx_lat_bit_for_async |
0 |
ch2_rx_dl_rxbit_rollover |
0 |
ch2_rx_dl_rxbit_cntr_pma |
DISABLE |
ch2_hw_fec |
0 |
CH2_SRC_TX_ENABLE |
1 |
CH2_SRC_RX_ENABLE |
1 |
CH2_SRC_TX_INITIATOR |
0 |
CH2_SRC_RX_INITIATOR |
0 |
CH2_SRC_TX_INITIATOR_INDEX |
0 |
CH2_SRC_RX_INITIATOR_INDEX |
0 |
CH2_SRC_TX_TARGET_ENABLE |
0 |
CH2_SRC_RX_TARGET_ENABLE |
0 |
CH2_SRC_TX_LANE_FUCTIONAL_MODE |
3 |
CH2_SRC_RX_LANE_FUCTIONAL_MODE |
3 |
CH2_SRC_NON_PTP_CHANNEL |
1 |
CH2_SRC_TX_PCS_EN |
1 |
CH2_SRC_RX_PCS_EN |
1 |
CH2_SRC_UX_EN |
1 |
CH2_SRC_TX_DL_EN |
0 |
CH2_SRC_RX_DL_EN |
0 |
CH2_SRC_FLUX_USED_FOR_RX_ADAPTATION |
0 |
CH2_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW |
1 |
CH2_SRC_PTP_EN |
0 |
CH2_SRC_TX_FEC_EN |
0 |
CH2_SRC_RX_FEC_EN |
0 |
CH2_SRC_ETHERNET_SYSPLL_CLK_MODE |
1 |
CH2_SRC_UX_USING_SYSPLL_CLK |
0 |
CH2_SRC_FLUX_USING_SYSPLL_CLK |
0 |
CH2_SRC_FLUX_EN |
0 |
CH2_SRC_FLUX_EN_HW |
1 |
CH2_SRC_SRC_LANE_INDEX |
2 |
CH2_SRC_LEADER_LANE |
0 |
ch3_lane_id |
3 |
ch3_tx_channel_mode |
PCSD |
ch3_rx_channel_mode |
PCSD |
ch3_duplex_mode |
DUPLEX |
ch3_rate_mode |
RATE_25G |
ch3_ptp_mode |
DISABLED |
ch3_fec_mode |
0 |
ch3_tx_dl_enable |
DISABLE |
ch3_rx_dl_enable |
DISABLE |
ch3_sup_mode |
USER_MODE |
ch3_sim_mode |
ENABLE |
ch3_syspll_rx_clk_hz |
322265625 |
ch3_syspll_tx_clk_hz |
322265625 |
ch3_tx_user1_clk_dynamic_mux |
PLL_C0 |
ch3_tx_user2_clk_dynamic_mux |
DISABLED |
ch3_rx_user1_clk_dynamic_mux |
PLL_C0 |
ch3_rx_user2_clk_dynamic_mux |
DISABLED |
ch3_tx_bond_size |
4 |
ch3_rx_bond_size |
1 |
ch3_xcvr_tx_protocol_hint |
DISABLED |
ch3_xcvr_tx_datarate_bps |
1105.92 |
ch3_xcvr_tx_prbs_pattern |
DISABLE |
ch3_xcvr_tx_user_clk_only_mode |
DISABLE |
ch3_xcvr_tx_width |
32 |
ch3_xcvr_rx_protocol_hint |
DISABLED |
ch3_xcvr_rx_datarate_bps |
1105.92 |
ch3_xcvr_rx_prbs_pattern |
DISABLE |
ch3_xcvr_rx_width |
32 |
ch3_xcvr_rx_force_cdr_ltr |
FALSE |
ch3_xcvr_rx_adaptation_mode |
DISABLED |
ch3_xcvr_rx_adaptation_mode_hw |
FLUX_ADAPTATION |
ch3_xcvr_cdr_f_ref_hz |
184320000 |
ch3_xcvr_cdr_f_vco_hz |
552960000 |
ch3_rx_postdiv_clk_en |
ENABLE |
ch3_rx_postdiv_clk_divider |
100 |
ch3_tx_postdiv_clk_divider |
100 |
ch3_tx_pll_f_ref_hz |
184320000 |
ch3_tx_pll_f_out_hz |
552960000 |
ch3_tx_pll_refclk_select |
GLOBAL_REFCLK0 |
ch3_cdr_refclk_select |
GLOBAL_REFCLK1 |
ch3_phy_loopback_mode |
DISABLED |
ch3_flux_mode |
FLUX_MODE_BYPASS |
ch3_flux_mode_hw |
FLUX_MODE_SNIFFER |
ch3_xcvrif_tx_fifo_mode |
ELASTIC |
ch3_xcvrif_rx_fifo_mode |
ELASTIC |
ch3_xcvrif_rx_word_clk_dynamic_mux |
SEL_RXWORD_CLK |
ch3_xcvr_tx_spread_spectrum_en |
DISABLE |
ch3_xcvr_tx_cascade_en |
DISABLE |
ch3_tx_pcs_mode |
IEEE |
ch3_rx_pcs_mode |
IEEE |
ch3_mac_link_fault_mode |
OFF |
ch3_mac_remove_pads |
DISABLE |
ch3_mac_keep_rx_crc |
DISABLE |
ch3_mac_forward_rx_pause_requests |
DISABLE |
ch3_mac_source_address_insertion |
DISABLE |
ch3_mac_tx_vlan_detection |
DISABLE |
ch3_mac_rx_vlan_detection |
DISABLE |
ch3_mac_flow_control |
DISABLE FLOW CONTROL |
ch3_mac_tx_max_frame_size |
65 |
ch3_mac_rx_max_frame_size |
65 |
ch3_mac_enforce_max_frame_size |
DISABLE |
ch3_mac_tx_preamble_passthrough |
DISABLE |
ch3_mac_rx_preamble_passthrough |
DISABLE |
ch3_mac_strict_preamble_checking |
DISABLE |
ch3_mac_strict_sfd_checking |
DISABLE |
ch3_mac_tx_ipg_size |
12 |
ch3_mac_ipg_removed_per_am_period |
0 |
ch3_mac_custom_cadence |
DISABLE |
ch3_ptp0_en |
DISABLED |
ch3_ptp1_en |
DISABLED |
ch3_mac_sim_mode |
ENABLE |
ch3_ptp0_sim_mode |
ENABLE |
ch3_ptp1_sim_mode |
ENABLE |
ch3_mac_tx_mac_data_flow |
DISABLE |
ch3_mac_sf_en |
DISABLED |
ch3_ehip_loopback_mode |
NO_LOOPBACK |
ch3_mac_txmac_saddr |
001122334455 |
ch3_pldif_tx_fifo_mode |
PHASE_COMP |
ch3_pldif_tx_fifo_width |
DOUBLE_WIDTH |
ch3_pldif_rx_fifo_mode |
PHASE_COMP |
ch3_pldif_rx_fifo_width |
DOUBLE_WIDTH |
ch3_pldif_tx_clkout1_divider |
DIV2 |
ch3_pldif_tx_clkout2_divider |
DIV2 |
ch3_pldif_rx_clkout1_divider |
DIV2 |
ch3_pldif_rx_clkout2_divider |
DIV2 |
ch3_pldif_channel_identifier |
GENERIC |
ch3_pldif_sf_en |
ENABLED |
ch3_pldif_loopback_mode |
NO_LOOPBACK |
ch3_pcs_loopback_mode |
NO_LOOPBACK |
ch3_pcs_sf_en |
ENABLED |
ch3_fec_spec |
DISABLED |
ch3_fec_fracture |
UNUSED |
ch3_fec_tx_en |
FALSE |
ch3_fec_rx_en |
FALSE |
ch3_fec_loopback_mode |
DISABLE |
ch3_tx_pll_frac_mode_en |
DISABLE |
ch3_rx_invert_pin |
DISABLE |
ch3_tx_invert_pin |
DISABLE |
ch3_xcvr_rx_cdrdivout_en |
DISABLE |
ch3_xcvr_tx_eq_main_tap |
52 |
ch3_xcvr_tx_eq_post_tap_1 |
5 |
ch3_xcvr_tx_eq_pre_tap_1 |
0 |
ch3_xcvr_tx_eq_pre_tap_2 |
0 |
ch3_tx_pll_feed_forward_gain |
197 |
ch3_xcvr_rx_termination_mode |
GROUNDED |
ch3_xcvr_rx_onchip_termination_setting |
R_2 |
ch3_xcvr_rx_eq_vga_gain |
0 |
ch3_xcvr_x_eq_hf_boost |
0 |
ch3_xcvr_rx_eq_dfe_tap_1 |
0 |
ch3_xcvr_rx_external_couple_type |
AC |
ch3_sequencer_reg_en |
DISABLE |
ch3_rx_dl_rx_lat_bit_for_async |
0 |
ch3_rx_dl_rxbit_rollover |
0 |
ch3_rx_dl_rxbit_cntr_pma |
DISABLE |
ch3_hw_fec |
0 |
CH3_SRC_TX_ENABLE |
1 |
CH3_SRC_RX_ENABLE |
1 |
CH3_SRC_TX_INITIATOR |
0 |
CH3_SRC_RX_INITIATOR |
0 |
CH3_SRC_TX_INITIATOR_INDEX |
0 |
CH3_SRC_RX_INITIATOR_INDEX |
0 |
CH3_SRC_TX_TARGET_ENABLE |
0 |
CH3_SRC_RX_TARGET_ENABLE |
0 |
CH3_SRC_TX_LANE_FUCTIONAL_MODE |
3 |
CH3_SRC_RX_LANE_FUCTIONAL_MODE |
3 |
CH3_SRC_NON_PTP_CHANNEL |
1 |
CH3_SRC_TX_PCS_EN |
1 |
CH3_SRC_RX_PCS_EN |
1 |
CH3_SRC_UX_EN |
1 |
CH3_SRC_TX_DL_EN |
0 |
CH3_SRC_RX_DL_EN |
0 |
CH3_SRC_FLUX_USED_FOR_RX_ADAPTATION |
0 |
CH3_SRC_FLUX_USED_FOR_RX_ADAPTATION_HW |
1 |
CH3_SRC_PTP_EN |
0 |
CH3_SRC_TX_FEC_EN |
0 |
CH3_SRC_RX_FEC_EN |
0 |
CH3_SRC_ETHERNET_SYSPLL_CLK_MODE |
1 |
CH3_SRC_UX_USING_SYSPLL_CLK |
0 |
CH3_SRC_FLUX_USING_SYSPLL_CLK |
0 |
CH3_SRC_FLUX_EN |
0 |
CH3_SRC_FLUX_EN_HW |
1 |
CH3_SRC_SRC_LANE_INDEX |
3 |
CH3_SRC_LEADER_LANE |
0 |
deviceFamily |
UNKNOWN |
generateLegacySim |
false |