EMIF_Qsys

2025.02.03.09:32:59 Datasheet
Overview
Memory Map
  emif_ddr4a
s0_axi4 
s0_axi4lite 
  emif_ddr4b
s0_axi4 
s0_axi4lite 

clock_310m

altera_clock_bridge v19.2.0
iopll outclk0   clock_310m
  in_clk


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_ddr4a

emif_io96b_ddr4comp v1.0.0
iopll outclk0   emif_ddr4a
  s0_axi4_clock_in
reset_bridge out_reset  
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

emif_ddr4b

emif_io96b_ddr4comp v1.0.0
iopll outclk0   emif_ddr4b
  s0_axi4_clock_in
reset_bridge out_reset  
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)

iopll

altera_iopll v20.0.0


Parameters

generateLegacySim false
  

Software Assignments

(none)

reset_bridge

altera_reset_bridge v19.2.0
iopll outclk0   reset_bridge
  clk
out_reset   emif_ddr4a
  core_init_n
out_reset   emif_ddr4b
  core_init_n


Parameters

generateLegacySim false
  

Software Assignments

(none)
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