{ "Info" "IDMS_INIT_MSG_DB" "" "Initialized Quartus Message Database" {  } {  } 0 21958 "Initialized Quartus Message Database" 0 0 "Design Software" 0 -1 0 ""}
{ "Info" "0" "" "Analyzing source files" {  } {  } 0 0 "Analyzing source files" 0 0 "0" 0 0 1732685475814 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "vpg_source/vpg.h vpg.v(33) " "Verilog HDL info at vpg.v(33): analyzing included file vpg_source/vpg.h" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/vpg_source/vpg.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/vpg_source/vpg.v" 33 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1732685487863 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "vpg_source/vpg.v vpg.v(33) " "Verilog HDL info at vpg.v(33): back to file 'vpg_source/vpg.v'" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/vpg_source/vpg.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/vpg_source/vpg.v" 33 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1732685487863 ""}
{ "Warning" "WVRFX2_VERI_POTENTIAL_ALWAYS_LOOP" "I2C_HDMI_Config.v(150) " "Verilog HDL warning at I2C_HDMI_Config.v(150): potential always loop found" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_HDMI_Config.v" 150 0 0 0 } }  } 0 16752 "Verilog HDL warning at %1!s!: potential always loop found" 0 0 "Design Software" 0 -1 1732685487867 ""}
{ "Critical Warning" "WQIS_RESET_IP_NOT_EXISTS_IN_FM_DESIGN" "Agilex 5 " "Use the Reset Release IP in Intel Agilex 5 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Configuration User Guide." {  } {  } 1 20759 "Use the Reset Release IP in Intel %1!s! FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Configuration User Guide." 0 0 "Design Software" 0 -1 1732685487891 ""}
{ "Info" "0" "" "Elaborating from top-level entity \"golden_top\"" {  } {  } 0 0 "Elaborating from top-level entity \"golden_top\"" 0 0 "0" 0 0 1732685488010 ""}
{ "Info" "IVRFX2_USER_LIBRARY_SEARCH_ORDER" "altera_iopll_2000; sys_pll; pll; pll_audio " "Library search order is as follows: \"altera_iopll_2000; sys_pll; pll; pll_audio\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." {  } {  } 0 18235 "Library search order is as follows: \"%1!s!\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." 0 0 "Design Software" 0 -1 1732685488263 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "17 16 I2C_HDMI_Config.v(45) " "Verilog HDL assignment warning at I2C_HDMI_Config.v(45): truncated value with size 17 to match size of target (16)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_HDMI_Config.v" 45 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489959 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(62) " "Verilog HDL assignment warning at I2C_Controller.v(62): truncated value with size 32 to match size of target (1)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_Controller.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_Controller.v" 62 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489960 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 I2C_Controller.v(90) " "Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_Controller.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_Controller.v" 90 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489960 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 I2C_HDMI_Config.v(93) " "Verilog HDL assignment warning at I2C_HDMI_Config.v(93): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/I2C_HDMI_Config.v" 93 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489964 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 AUDIO_IF.v(113) " "Verilog HDL assignment warning at AUDIO_IF.v(113): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/AUDIO_IF.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/AUDIO_IF.v" 113 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489979 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 7 AUDIO_IF.v(129) " "Verilog HDL assignment warning at AUDIO_IF.v(129): truncated value with size 8 to match size of target (7)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/AUDIO_IF.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/AUDIO_IF.v" 129 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489980 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 AUDIO_IF.v(155) " "Verilog HDL assignment warning at AUDIO_IF.v(155): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/AUDIO_IF.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/AUDIO_IF.v" 155 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1732685489980 ""}
{ "Warning" "WVRFX2_VERI_1330_UNCONVERTED" "1 4 i2s golden_top.v(338) " "Verilog HDL warning at golden_top.v(338): actual bit length 1 differs from formal bit length 4 for port \"i2s\"" {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/golden_top.v" 338 0 0 0 } }  } 0 24541 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!lu! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1732685490010 ""}
{ "Info" "0" "" "Found 13 design entities" {  } {  } 0 0 "Found 13 design entities" 0 0 "0" 0 0 1732685491888 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "LED\[0..3\] golden_top gnd top-level " "Output port \"LED\[0..3\]\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/golden_top.v" 61 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1732685492208 "LED[3]"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_SCLK golden_top gnd top-level " "Output port \"INFO_SPI_SCLK\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/golden_top.v" 274 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1732685492254 "INFO_SPI_SCLK"}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_MOSI golden_top gnd top-level " "Output port \"INFO_SPI_MOSI\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/ax5soc_cd_243/HDMI_TX/gol