{ "Info" "IDMS_INIT_MSG_DB" "" "Initialized Quartus Message Database" {  } {  } 0 21958 "Initialized Quartus Message Database" 0 0 "Design Software" 0 -1 0 ""}
{ "Info" "0" "" "Analyzing source files" {  } {  } 0 0 "Analyzing source files" 0 0 "0" 0 0 1713519314027 ""}
{ "Info" "IVRFX2_VERI_1328_UNCONVERTED" "vpg_source/vpg.h vpg.v(33) " "Verilog HDL info at vpg.v(33): analyzing included file vpg_source/vpg.h" {  } { { "E:/nick/AG5/nick/HDMI_TX/vpg_source/vpg.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/vpg_source/vpg.v" 33 0 0 0 } }  } 0 16884 "Verilog HDL info at %2!s!: analyzing included file %1!s!" 0 0 "Design Software" 0 -1 1713519332363 ""}
{ "Info" "IVRFX2_VERI_2320_UNCONVERTED" "vpg_source/vpg.v vpg.v(33) " "Verilog HDL info at vpg.v(33): back to file 'vpg_source/vpg.v'" {  } { { "E:/nick/AG5/nick/HDMI_TX/vpg_source/vpg.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/vpg_source/vpg.v" 33 0 0 0 } }  } 0 19624 "Verilog HDL info at %2!s!: back to file '%1!s!'" 0 0 "Design Software" 0 -1 1713519332364 ""}
{ "Warning" "WVRFX2_VERI_POTENTIAL_ALWAYS_LOOP" "I2C_HDMI_Config.v(150) " "Verilog HDL warning at I2C_HDMI_Config.v(150): potential always loop found" {  } { { "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" 150 0 0 0 } }  } 0 16752 "Verilog HDL warning at %1!s!: potential always loop found" 0 0 "Design Software" 0 -1 1713519332367 ""}
{ "Critical Warning" "WQIS_RESET_IP_NOT_EXISTS_IN_FM_DESIGN" "Agilex 5 " "Use the Reset Release IP in Intel Agilex 5 FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Configuration User Guide." {  } {  } 1 20759 "Use the Reset Release IP in Intel %1!s! FPGA designs to ensure a successful configuration. For more information about the Reset Release IP, refer to the Configuration User Guide." 0 0 "Design Software" 0 -1 1713519332383 ""}
{ "Info" "0" "" "Elaborating from top-level entity \"golden_top\"" {  } {  } 0 0 "Elaborating from top-level entity \"golden_top\"" 0 0 "0" 0 0 1713519332474 ""}
{ "Info" "IVRFX2_USER_LIBRARY_SEARCH_ORDER" "altera_iopll_1931; sys_pll; pll " "Library search order is as follows: \"altera_iopll_1931; sys_pll; pll\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." {  } {  } 0 18235 "Library search order is as follows: \"%1!s!\". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER." 0 0 "Design Software" 0 -1 1713519332500 ""}
{ "Warning" "WVRFX2_VERI_PORT_UNCONNECTED" "SD_COUNTER I2C_HDMI_Config.v(61) " "Verilog HDL warning at I2C_HDMI_Config.v(61): port \"SD_COUNTER\" remains unconnected for this instance" {  } { { "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" 61 0 0 0 } }  } 0 16751 "Verilog HDL warning at %2!s!: port \"%1!s!\" remains unconnected for this instance" 1 0 "Design Software" 0 -1 1713519334042 ""}
{ "Warning" "WVRFX2_VERI_PORT_UNCONNECTED" "locked vpg.v(75) " "Verilog HDL warning at vpg.v(75): port \"locked\" remains unconnected for this instance" {  } { { "E:/nick/AG5/nick/HDMI_TX/vpg_source/vpg.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/vpg_source/vpg.v" 75 0 0 0 } }  } 0 16751 "Verilog HDL warning at %2!s!: port \"%1!s!\" remains unconnected for this instance" 1 0 "Design Software" 0 -1 1713519334042 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "27 26 Pll_Audio.v(18) " "Verilog HDL assignment warning at Pll_Audio.v(18): truncated value with size 27 to match size of target (26)" {  } { { "E:/nick/AG5/nick/HDMI_TX/Pll_Audio.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/Pll_Audio.v" 18 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334043 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "17 16 I2C_HDMI_Config.v(45) " "Verilog HDL assignment warning at I2C_HDMI_Config.v(45): truncated value with size 17 to match size of target (16)" {  } { { "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" 45 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334044 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 I2C_Controller.v(62) " "Verilog HDL assignment warning at I2C_Controller.v(62): truncated value with size 32 to match size of target (1)" {  } { { "E:/nick/AG5/nick/HDMI_TX/I2C_Controller.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/I2C_Controller.v" 62 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334044 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 I2C_Controller.v(90) " "Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/nick/HDMI_TX/I2C_Controller.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/I2C_Controller.v" 90 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334045 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 I2C_HDMI_Config.v(93) " "Verilog HDL assignment warning at I2C_HDMI_Config.v(93): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/I2C_HDMI_Config.v" 93 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334046 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 AUDIO_IF.v(113) " "Verilog HDL assignment warning at AUDIO_IF.v(113): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/nick/HDMI_TX/AUDIO_IF.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/AUDIO_IF.v" 113 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334050 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 7 AUDIO_IF.v(129) " "Verilog HDL assignment warning at AUDIO_IF.v(129): truncated value with size 8 to match size of target (7)" {  } { { "E:/nick/AG5/nick/HDMI_TX/AUDIO_IF.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/AUDIO_IF.v" 129 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334050 ""}
{ "Warning" "WVRFX2_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "7 6 AUDIO_IF.v(155) " "Verilog HDL assignment warning at AUDIO_IF.v(155): truncated value with size 7 to match size of target (6)" {  } { { "E:/nick/AG5/nick/HDMI_TX/AUDIO_IF.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/AUDIO_IF.v" 155 0 0 0 } }  } 3 13469 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Design Software" 0 -1 1713519334051 ""}
{ "Warning" "WVRFX2_VERI_PORT_BIT_LENGTH_DIFFER" "1 4 i2s golden_top.v(337) " "Verilog HDL warning at golden_top.v(337): actual bit length 1 differs from formal bit length 4 for port \"i2s\"" {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 337 0 0 0 } }  } 0 16735 "Verilog HDL warning at %4!s!: actual bit length %1!d! differs from formal bit length %2!d! for port \"%3!s!\"" 0 0 "Design Software" 0 -1 1713519334053 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "CLK_50_5A golden_top.v(305) " "Net \"CLK_50_5A\" does not have a driver at golden_top.v(305)" {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 305 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 0 0 "Design Software" 0 -1 1713519334053 ""}
{ "Warning" "WVRFX2_VDB_NET_DOES_NOT_HAVE_DRIVER" "CLK_50_6A golden_top.v(321) " "Net \"CLK_50_6A\" does not have a driver at golden_top.v(321)" {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 321 0 0 0 } }  } 0 16788 "Net \"%1!s!\" does not have a driver at %2!s!" 0 0 "Design Software" 0 -1 1713519334054 ""}
{ "Info" "0" "" "Found 12 design entities" {  } {  } 0 0 "Found 12 design entities" 0 0 "0" 0 0 1713519335616 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "LED\[0..3\] golden_top gnd top-level " "Output port \"LED\[0..3\]\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 61 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1713519335945 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_SCLK golden_top gnd top-level " "Output port \"INFO_SPI_SCLK\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 274 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1713519335945 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_MOSI golden_top gnd top-level " "Output port \"INFO_SPI_MOSI\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 276 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1713519335945 ""}
{ "Warning" "WQIS_UNCONNECTED_OUTPUT_PORT_WARNING" "INFO_SPI_CS_n golden_top gnd top-level " "Output port \"INFO_SPI_CS_n\" in top-level entity \"golden_top\" does not have a driver. Connecting to the default value \"gnd\"." {  } { { "E:/nick/AG5/nick/HDMI_TX/golden_top.v" "" { Text "E:/nick/AG5/nick/HDMI_TX/golden_top.v" 277 0 0 0 } }  } 0 21610 "Output port \"%1!s!\" in %4!s! entity \"%2!s!\" does not have a driver. Connecting to the default value \"%3!s!\"." 0 0 "Design Software" 0 -1 1713519335945 ""}
{ "Info" "0" "" "There are 9 partitions after elaboration." {  } {  } 0 0 "There are 9 partitions after elaboration." 0 0 "0" 0 0 1713519335959 ""}
{ "Info" "" "Running rule checking for Agilex5 protocol IPs... " "Running rule checking for Agilex5 protocol IPs..." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1713519338235 ""}
{ "Info" "0" "" "DA report generation in native DNI mode" {  } {  } 0 0 "DA report generation in native DNI mode" 0 0 "0" 0 0 1713519342438 ""}
{ "Info" "IDRC_START_RUN_DA_DRC" "partitioned " "Running Design Assistant Rules for snapshot 'partitioned'" {  } {  } 0 21615 "Running Design Assistant Rules for snapshot '%1!s!'" 0 0 "Design Software" 0 -1 1713519342443 ""}
{ "Info" "" "" "No waiver waived any violations" {  } {  } 0 0 "No waiver waived any violations" 0 0 "Design Software" 0 -1 1713519342496 ""}
{ "Info" "IDRC_PASSED_RULES_RESULT" "28 29 partitioned  1 " "Design Assistant Results: 28 of 29 enabled rules passed, and 1 rules was disabled, in snapshot 'partitioned'" {  } {  } 0 22360 "Design Assistant Results: %1!d! of %2!d! enabled rules passed, and %5!d! rules was disabled, in snapshot '%3!s!'%4!s!" 0 0 "Design Software" 0 -1 1713519342496 ""}
{ "Info" "IDRC_NO_CRITICAL_WARN_SEVERITY_RESULT" "0 19 Critical partitioned  " "Design Assistant Results: 0 of 19 Critical severity rules issued violations in snapshot 'partitioned'" {  } {  } 0 21660 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1713519342496 ""}
{ "Warning" "WDRC_WARN_SEVERITY_RESULT" "1 1 High partitioned . Please refer to DRC report 'E:/nick/AG5/nick/HDMI_TX/output_files/golden_top.drc.partitioned.rpt' for more information " "Design Assistant Results: 1 of 1 High severity rules issued violations in snapshot 'partitioned'. Please refer to DRC report 'E:/nick/AG5/nick/HDMI_TX/output_files/golden_top.drc.partitioned.rpt' for more information" {  } {  } 0 21620 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1713519342496 ""}
{ "Info" "IDRC_MEDIUM_SEVERITY_RESULT" "0 1 Medium partitioned  " "Design Assistant Results: 0 of 1 Medium severity rules issued violations in snapshot 'partitioned'" {  } {  } 0 21621 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1713519342496 ""}
{ "Info" "IDRC_LOW_SEVERITY_RESULT" "0 8 Low partitioned  " "Design Assistant Results: 0 of 8 Low severity rules issued violations in snapshot 'partitioned'" {  } {  } 0 21622 "Design Assistant Results: %1!d! of %2!d! %3!s! severity rules issued violations in snapshot '%4!s!'%5!s!" 0 0 "Design Software" 0 -1 1713519342496 ""}
{ "Warning" "WQCU_SYNTHESIS_HIERARCHIES_OPTIMIZED_AWAY_REPORT_WARNING" "" "Hierarchies were optimized away during sweep. For details, refer to \" Hierarchies Optimized Away During Sweep \" report." {  } {  } 0 23762 "Hierarchies were optimized away during sweep. For details, refer to \" Hierarchies Optimized Away During Sweep \" report." 0 0 "Design Software" 0 -1 1713519342697 ""}
