module agilex_hps (
		output wire         h2f_reset_reset,                        //                h2f_reset.reset,         Active high reset from the HPS Reset Manager.
		input  wire         hps2fpga_axi_clock_clk,                 //       hps2fpga_axi_clock.clk,           Clock from a single source in the FPGA.
		input  wire         hps2fpga_axi_reset_reset,               //       hps2fpga_axi_reset.reset,         Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   hps2fpga_awid,                          //                 hps2fpga.awid,          Identification tag for a write transaction.
		output wire [37:0]  hps2fpga_awaddr,                        //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [7:0]   hps2fpga_awlen,                         //                         .awlen,         The exact number of data transfers in a write transaction.
		output wire [2:0]   hps2fpga_awsize,                        //                         .awsize,        The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   hps2fpga_awburst,                       //                         .awburst,       Indicates how address changes between each transfer in a write transaction.
		output wire         hps2fpga_awlock,                        //                         .awlock,        Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   hps2fpga_awcache,                       //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_awprot,                        //                         .awprot,        Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         hps2fpga_awvalid,                       //                         .awvalid,       Indicates that the write address channel signals are valid.
		input  wire         hps2fpga_awready,                       //                         .awready,       Indicates that a transfer on the write address channel can be accepted.
		output wire [127:0] hps2fpga_wdata,                         //                         .wdata,         Write data.
		output wire [15:0]  hps2fpga_wstrb,                         //                         .wstrb,         Write strobes, indicate which byte lanes hold valid data.
		output wire         hps2fpga_wlast,                         //                         .wlast,         User-defined extension for the write data channel.
		output wire         hps2fpga_wvalid,                        //                         .wvalid,        Indicates that the write data channel signals are valid.
		input  wire         hps2fpga_wready,                        //                         .wready,        Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   hps2fpga_bid,                           //                         .bid,           Transaction identifier for the write response.
		input  wire [1:0]   hps2fpga_bresp,                         //                         .bresp,         Write response, indicates the status of a write transaction.
		input  wire         hps2fpga_bvalid,                        //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire         hps2fpga_bready,                        //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   hps2fpga_arid,                          //                         .arid,          Transaction identifier for the read transaction.
		output wire [37:0]  hps2fpga_araddr,                        //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [7:0]   hps2fpga_arlen,                         //                         .arlen,         The exact number of data transfers in a read transaction.
		output wire [2:0]   hps2fpga_arsize,                        //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   hps2fpga_arburst,                       //                         .arburst,       Indicates how address changes between each transfer in a read transaction.
		output wire         hps2fpga_arlock,                        //                         .arlock,        Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   hps2fpga_arcache,                       //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_arprot,                        //                         .arprot,        Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         hps2fpga_arvalid,                       //                         .arvalid,       Indicates that the read address channel signals are valid.
		input  wire         hps2fpga_arready,                       //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   hps2fpga_rid,                           //                         .rid,           Identification tag for read data and response.
		input  wire [127:0] hps2fpga_rdata,                         //                         .rdata,         Read data.
		input  wire [1:0]   hps2fpga_rresp,                         //                         .rresp,         Read response, indicates the status of a read transfer.
		input  wire         hps2fpga_rlast,                         //                         .rlast,         Indicates whether this is the last data transfer in a read transaction.
		input  wire         hps2fpga_rvalid,                        //                         .rvalid,        Indicates that the read data channel signals are valid.
		output wire         hps2fpga_rready,                        //                         .rready,        Indicates that a transfer on the read data channel can be accepted.
		input  wire         lwhps2fpga_axi_clock_clk,               //     lwhps2fpga_axi_clock.clk,           clock from a single source in the FPGA.
		input  wire         lwhps2fpga_axi_reset_reset,             //     lwhps2fpga_axi_reset.reset,         Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   lwhps2fpga_awid,                        //               lwhps2fpga.awid,          Identification tag for a write transaction.
		output wire [28:0]  lwhps2fpga_awaddr,                      //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [7:0]   lwhps2fpga_awlen,                       //                         .awlen,         The exact number of data transfers in a write transaction.
		output wire [2:0]   lwhps2fpga_awsize,                      //                         .awsize,        The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   lwhps2fpga_awburst,                     //                         .awburst,       Indicates how address changes between each transfer in a write transaction.
		output wire         lwhps2fpga_awlock,                      //                         .awlock,        Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   lwhps2fpga_awcache,                     //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_awprot,                      //                         .awprot,        Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_awvalid,                     //                         .awvalid,       Indicates that the write address channel signals are valid.
		input  wire         lwhps2fpga_awready,                     //                         .awready,       Indicates that a transfer on the write address channel can be accepted.
		output wire [31:0]  lwhps2fpga_wdata,                       //                         .wdata,         Write data.
		output wire [3:0]   lwhps2fpga_wstrb,                       //                         .wstrb,         Write strobes, indicate which byte lanes hold valid data.
		output wire         lwhps2fpga_wlast,                       //                         .wlast,         User-defined extension for the write data channel.
		output wire         lwhps2fpga_wvalid,                      //                         .wvalid,        Indicates that the write data channel signals are valid.
		input  wire         lwhps2fpga_wready,                      //                         .wready,        Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   lwhps2fpga_bid,                         //                         .bid,           Transaction identifier for the write response.
		input  wire [1:0]   lwhps2fpga_bresp,                       //                         .bresp,         Write response, indicates the status of a write transaction.
		input  wire         lwhps2fpga_bvalid,                      //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire         lwhps2fpga_bready,                      //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   lwhps2fpga_arid,                        //                         .arid,          Transaction identifier for the read transaction.
		output wire [28:0]  lwhps2fpga_araddr,                      //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [7:0]   lwhps2fpga_arlen,                       //                         .arlen,         The exact number of data transfers in a read transaction.
		output wire [2:0]   lwhps2fpga_arsize,                      //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   lwhps2fpga_arburst,                     //                         .arburst,       Indicates how address changes between each transfer in a read transaction.
		output wire         lwhps2fpga_arlock,                      //                         .arlock,        Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   lwhps2fpga_arcache,                     //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_arprot,                      //                         .arprot,        Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_arvalid,                     //                         .arvalid,       Indicates that the read address channel signals are valid.
		input  wire         lwhps2fpga_arready,                     //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   lwhps2fpga_rid,                         //                         .rid,           Identification tag for read data and response.
		input  wire [31:0]  lwhps2fpga_rdata,                       //                         .rdata,         Read data.
		input  wire [1:0]   lwhps2fpga_rresp,                       //                         .rresp,         Read response, indicates the status of a read transfer.
		input  wire         lwhps2fpga_rlast,                       //                         .rlast,         Indicates whether this is the last data transfer in a read transaction.
		input  wire         lwhps2fpga_rvalid,                      //                         .rvalid,        Indicates that the read data channel signals are valid.
		output wire         lwhps2fpga_rready,                      //                         .rready,        Indicates that a transfer on the read data channel can be accepted.
		output wire         emac2_app_rst_reset_n,                  //            emac2_app_rst.reset_n,       EMAC2 application clock reset output.
		output wire         h2f_warm_reset_handshake_reset_req,     // h2f_warm_reset_handshake.reset_req,     HPS warm reset request. Identical to watchdog reset except this is asserted by SDM.
		input  wire         h2f_warm_reset_handshake_reset_ack,     //                         .reset_ack,     HPS warm reset acknowledge response to SDM. Should be asserted when all HPS soft logic is successfully in reset.
		input  wire         hps_io_hps_osc_clk,                     //                   hps_io.hps_osc_clk,   HPS input clock pin for EOSC reference clock.
		inout  wire         hps_io_sdmmc_data0,                     //                         .sdmmc_data0,   SDMMC data[0].
		inout  wire         hps_io_sdmmc_data1,                     //                         .sdmmc_data1,   SDMMC data[1].
		output wire         hps_io_sdmmc_cclk,                      //                         .sdmmc_cclk,    SDMMC output clock.
		inout  wire         hps_io_sdmmc_data2,                     //                         .sdmmc_data2,   SDMMC data[2].
		inout  wire         hps_io_sdmmc_data3,                     //                         .sdmmc_data3,   SDMMC data[3].
		inout  wire         hps_io_sdmmc_cmd,                       //                         .sdmmc_cmd,     SDMMC command.
		input  wire         hps_io_usb1_clk,                        //                         .usb1_clk,      ULPI PHY clock input.
		output wire         hps_io_usb1_stp,                        //                         .usb1_stp,      ULPI stop output control.
		input  wire         hps_io_usb1_dir,                        //                         .usb1_dir,      Data bus control.
		inout  wire         hps_io_usb1_data0,                      //                         .usb1_data0,    USB data[0].
		inout  wire         hps_io_usb1_data1,                      //                         .usb1_data1,    USB data[1].
		input  wire         hps_io_usb1_nxt,                        //                         .usb1_nxt,      ULPI next data control.
		inout  wire         hps_io_usb1_data2,                      //                         .usb1_data2,    USB data[2].
		inout  wire         hps_io_usb1_data3,                      //                         .usb1_data3,    USB data[3].
		inout  wire         hps_io_usb1_data4,                      //                         .usb1_data4,    USB data[4].
		inout  wire         hps_io_usb1_data5,                      //                         .usb1_data5,    USB data[5].
		inout  wire         hps_io_usb1_data6,                      //                         .usb1_data6,    USB data[6].
		inout  wire         hps_io_usb1_data7,                      //                         .usb1_data7,    USB data[7].
		output wire         hps_io_emac2_tx_clk,                    //                         .emac2_tx_clk,  EMAC2 transmit clock.
		output wire         hps_io_emac2_tx_ctl,                    //                         .emac2_tx_ctl,  EMAC2 transmit data enable.
		input  wire         hps_io_emac2_rx_clk,                    //                         .emac2_rx_clk,  EMAC2 receive clock.
		input  wire         hps_io_emac2_rx_ctl,                    //                         .emac2_rx_ctl,  EMAC2 receive data enable.
		output wire         hps_io_emac2_txd0,                      //                         .emac2_txd0,    EMAC2 transmit data[0].
		output wire         hps_io_emac2_txd1,                      //                         .emac2_txd1,    EMAC2 transmit data[1].
		input  wire         hps_io_emac2_rxd0,                      //                         .emac2_rxd0,    EMAC2 receive data[0].
		input  wire         hps_io_emac2_rxd1,                      //                         .emac2_rxd1,    EMAC2 receive data[1].
		output wire         hps_io_emac2_txd2,                      //                         .emac2_txd2,    EMAC2 transmit data[2].
		output wire         hps_io_emac2_txd3,                      //                         .emac2_txd3,    EMAC2 transmit data[3].
		input  wire         hps_io_emac2_rxd2,                      //                         .emac2_rxd2,    EMAC2 receive data[2].
		input  wire         hps_io_emac2_rxd3,                      //                         .emac2_rxd3,    EMAC2 receive data[3].
		inout  wire         hps_io_mdio2_mdio,                      //                         .mdio2_mdio,    EMAC2 MDIO data.
		output wire         hps_io_mdio2_mdc,                       //                         .mdio2_mdc,     EMAC2 MDIO clock.
		output wire         hps_io_uart0_tx,                        //                         .uart0_tx,      UART0 transmit data.
		input  wire         hps_io_uart0_rx,                        //                         .uart0_rx,      UART0 receive data.
		inout  wire         hps_io_i2c0_sda,                        //                         .i2c0_sda,      I2C0 serial data.
		inout  wire         hps_io_i2c0_scl,                        //                         .i2c0_scl,      I2C0 clock.
		inout  wire         hps_io_gpio0,                           //                         .gpio0,         GPIO0 IO0
		inout  wire         hps_io_gpio1,                           //                         .gpio1,         GPIO0 IO1
		inout  wire         hps_io_gpio8,                           //                         .gpio8,         GPIO0 IO8
		inout  wire         hps_io_gpio9,                           //                         .gpio9,         GPIO0 IO9
		inout  wire         hps_io_gpio10,                          //                         .gpio10,        GPIO0 IO10
		inout  wire         hps_io_gpio11,                          //                         .gpio11,        GPIO0 IO11
		inout  wire         hps_io_gpio28,                          //                         .gpio28,        GPIO1 IO4
		input  wire         usb31_io_vbus_det,                      //                 usb31_io.vbus_det,      VBUS detect.
		input  wire         usb31_io_flt_bar,                       //                         .flt_bar,       Connected to overcurrent input on USB3.1 controller.
		output wire [1:0]   usb31_io_usb_ctrl,                      //                         .usb_ctrl,      USB3.1 control output to connect to UMC.
		input  wire         usb31_io_usb31_id,                      //                         .usb31_id,      USB ID.
		input  wire [62:0]  fpga2hps_interrupt_irq,                 //       fpga2hps_interrupt.irq,           FPGA-to-HPS interrupts.
		input  wire         usb31_phy_pma_cpu_clk_clk,              //    usb31_phy_pma_cpu_clk.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_refclk_p_clk,                 //       usb31_phy_refclk_p.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_refclk_n_clk,                 //       usb31_phy_refclk_n.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_rx_serial_n_i_rx_serial_n,    //    usb31_phy_rx_serial_n.i_rx_serial_n, Differential pair for RX serial data port. Historically was hidden; however now used in pam4 signal simulation model, hence needs to be connected by user.
		input  wire         usb31_phy_rx_serial_p_i_rx_serial_p,    //    usb31_phy_rx_serial_p.i_rx_serial_p, TX serial data port.
		output wire         usb31_phy_tx_serial_n_o_tx_serial_n,    //    usb31_phy_tx_serial_n.o_tx_serial_n, Differential pair for TX serial data port. Historically was hidden; however now used in pam4 signal simulation model, hence needs to be connected by user.
		output wire         usb31_phy_tx_serial_p_o_tx_serial_p,    //    usb31_phy_tx_serial_p.o_tx_serial_p, TX serial data port.
		input  wire         usb31_phy_reconfig_rst_reset,           //   usb31_phy_reconfig_rst.reset,         reconfig_reset
		input  wire         usb31_phy_reconfig_clk_clk,             //   usb31_phy_reconfig_clk.clk,           reconfig_clk
		input  wire [20:0]  usb31_phy_reconfig_slave_address,       // usb31_phy_reconfig_slave.address,       Address for Ethernet CSRs
		input  wire [3:0]   usb31_phy_reconfig_slave_byteenable,    //                         .byteenable,    Byte enable for read/write to Ethernet CSRs
		output wire         usb31_phy_reconfig_slave_readdatavalid, //                         .readdatavalid, Read data from Ethernet CSRs is valid
		input  wire         usb31_phy_reconfig_slave_read,          //                         .read,          Read command for Ethernet CSRs
		input  wire         usb31_phy_reconfig_slave_write,         //                         .write,         Write command for Ethernet CSRs
		output wire [31:0]  usb31_phy_reconfig_slave_readdata,      //                         .readdata,      Read data from reads to Ethernet CSRs
		input  wire [31:0]  usb31_phy_reconfig_slave_writedata,     //                         .writedata,     Data for writes to Ethernet CSRs
		output wire         usb31_phy_reconfig_slave_waitrequest,   //                         .waitrequest,   AVMM stall signal for operation on Ethernet CSRs
		input  wire         f2sdram_axi_clock_clk,                  //        f2sdram_axi_clock.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         f2sdram_axi_reset_reset,                //        f2sdram_axi_reset.reset,         Active high reset for f2sdram soft logic on FPGA. The actual bridge reset is driven by internal HPS Reset Manager.
		input  wire [31:0]  f2sdram_araddr,                         //                  f2sdram.araddr,        Address of the first transfer in a read transaction.
		input  wire [1:0]   f2sdram_arburst,                        //                         .arburst,       Burst type indicating how address changes between each transfer in a read transaction.
		input  wire [3:0]   f2sdram_arcache,                        //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_arid,                           //                         .arid,          Identification tag for a read transaction.
		input  wire [7:0]   f2sdram_arlen,                          //                         .arlen,         The exact number of data transfers in a read transaction.
		input  wire         f2sdram_arlock,                         //                         .arlock,        Provides info on atomic characteristics of a read transaction.
		input  wire [2:0]   f2sdram_arprot,                         //                         .arprot,        Protection attributes of a read transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_arqos,                          //                         .arqos,         Quality service identifier for a read transaction.
		output wire         f2sdram_arready,                        //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [2:0]   f2sdram_arsize,                         //                         .arsize,        The number of bytes in each data transfer of a read transaction.
		input  wire         f2sdram_arvalid,                        //                         .arvalid,       Indicates the read address channel signals are valid.
		input  wire [31:0]  f2sdram_awaddr,                         //                         .awaddr,        The address of the first transfer in a write transaction.
		input  wire [1:0]   f2sdram_awburst,                        //                         .awburst,       Burst type indicating how address changes between each transfer in a write transaction.
		input  wire [3:0]   f2sdram_awcache,                        //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_awid,                           //                         .awid,          Identification tag for a write transaction.
		input  wire [7:0]   f2sdram_awlen,                          //                         .awlen,         The exact number of data transfers in a write transaction.
		input  wire         f2sdram_awlock,                         //                         .awlock,        Provides info on atomic characteristics of a write transaction.
		input  wire [2:0]   f2sdram_awprot,                         //                         .awprot,        Protection attributes of a write transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_awqos,                          //                         .awqos,         Quality of servide identifier for a write transaction.
		output wire         f2sdram_awready,                        //                         .awready,       Indicates that a transfer on the write channel address can be accepted.
		input  wire [2:0]   f2sdram_awsize,                         //                         .awsize,        The number of bytes in each data transfer of a write transaction.
		input  wire         f2sdram_awvalid,                        //                         .awvalid,       Indicates the write address channel signals are valid.
		output wire [4:0]   f2sdram_bid,                            //                         .bid,           Identification tag for a write response.
		input  wire         f2sdram_bready,                         //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [1:0]   f2sdram_bresp,                          //                         .bresp,         Write response indicating the status of a write transaction.
		output wire         f2sdram_bvalid,                         //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire [255:0] f2sdram_rdata,                          //                         .rdata,         Read data.
		output wire [4:0]   f2sdram_rid,                            //                         .rid,           Identification tag for read data and response.
		output wire         f2sdram_rlast,                          //                         .rlast,         Indicates the last data transfer in a read transaction.
		input  wire         f2sdram_rready,                         //                         .rready,        Indicates a transfer on the read data channel can be accepted.
		output wire [1:0]   f2sdram_rresp,                          //                         .rresp,         Read response indicating the status of a read transfer.
		output wire         f2sdram_rvalid,                         //                         .rvalid,        Indicates the read channel data channel signals are valid.
		input  wire [255:0] f2sdram_wdata,                          //                         .wdata,         Write data.
		input  wire         f2sdram_wlast,                          //                         .wlast,         Indicates the last data transfer in a write transaction.
		output wire         f2sdram_wready,                         //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		input  wire [31:0]  f2sdram_wstrb,                          //                         .wstrb,         Write strobes indicating which bye lanes hold valid data.
		input  wire         f2sdram_wvalid,                         //                         .wvalid,        Indicates the write channel data signals are valid.
		input  wire [7:0]   f2sdram_aruser,                         //                         .aruser,        Extension for the read address channel.
		input  wire [7:0]   f2sdram_awuser,                         //                         .awuser,        Extension for the write address channel.
		input  wire [7:0]   f2sdram_wuser,                          //                         .wuser,         Extension for the write data channel.
		output wire [7:0]   f2sdram_buser,                          //                         .buser,         Extension for the write response channel.
		input  wire [3:0]   f2sdram_arregion,                       //                         .arregion,      Region indicator for a read transaction.
		output wire [7:0]   f2sdram_ruser,                          //                         .ruser,         Extension for the read data channel.
		input  wire [3:0]   f2sdram_awregion,                       //                         .awregion,      Region indicator for a write transaction.
		input  wire         io96b0_csr_axi_clk_clk,                 //       io96b0_csr_axi_clk.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_csr_axi_rst_reset_n,             //       io96b0_csr_axi_rst.reset_n,       Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_csr_axi_arready,                 //           io96b0_csr_axi.arready,       Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_csr_axi_awready,                 //                         .awready,       Indicates a transfer on the write address channel can be accepted.
		input  wire [1:0]   io96b0_csr_axi_bresp,                   //                         .bresp,         Indicates status of write transaction.
		input  wire         io96b0_csr_axi_bvalid,                  //                         .bvalid,        Indicates write response channel signals are valid.
		input  wire [31:0]  io96b0_csr_axi_rdata,                   //                         .rdata,         Read data.
		input  wire [1:0]   io96b0_csr_axi_rresp,                   //                         .rresp,         Indicates status of read transaction.
		input  wire         io96b0_csr_axi_rvalid,                  //                         .rvalid,        Indicates read data channel signals are valid.
		input  wire         io96b0_csr_axi_wready,                  //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		output wire [31:0]  io96b0_csr_axi_araddr,                  //                         .araddr,        The address of the first transfer in a read transaction.
		output wire         io96b0_csr_axi_arvalid,                 //                         .arvalid,       Indicates read address channel signals are valid.
		output wire [31:0]  io96b0_csr_axi_awaddr,                  //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire         io96b0_csr_axi_awvalid,                 //                         .awvalid,       Indicates write address channel signals are valid.
		output wire         io96b0_csr_axi_bready,                  //                         .bready,        Indicates a transfer on the write response channel can be accepted.
		output wire         io96b0_csr_axi_rready,                  //                         .rready,        Indicates a transfer on the read data channel can be accepted.
		output wire [31:0]  io96b0_csr_axi_wdata,                   //                         .wdata,         Write data.
		output wire [3:0]   io96b0_csr_axi_wstrb,                   //                         .wstrb,         Write strobes indicating which bye lanes hold valid data.
		output wire         io96b0_csr_axi_wvalid,                  //                         .wvalid,        Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_csr_axi_arprot,                  //                         .arprot,        Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_csr_axi_awprot,                  //                         .awprot,        Placegolder AWPROT. Protection attributes not supported for this bridge.
		input  wire         io96b0_ch0_axi_clk_clk,                 //       io96b0_ch0_axi_clk.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_ch0_axi_rst_reset_n,             //       io96b0_ch0_axi_rst.reset_n,       Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_ch0_axi_arready,                 //           io96b0_ch0_axi.arready,       Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_ch0_axi_awready,                 //                         .awready,       Indicates a transfer on the write address channel can be accepted.
		input  wire [6:0]   io96b0_ch0_axi_bid,                     //                         .bid,           Identification tag for a write response.
		input  wire [1:0]   io96b0_ch0_axi_bresp,                   //                         .bresp,         Indicates the status of a write transaction.
		input  wire         io96b0_ch0_axi_bvalid,                  //                         .bvalid,        Indicates write response channel signals are valid.
		input  wire [255:0] io96b0_ch0_axi_rdata,                   //                         .rdata,         Read data.
		input  wire [6:0]   io96b0_ch0_axi_rid,                     //                         .rid,           Identification tag for read data and response.
		input  wire         io96b0_ch0_axi_rlast,                   //                         .rlast,         Indicates the last data transfer in a read transaction.
		input  wire [1:0]   io96b0_ch0_axi_rresp,                   //                         .rresp,         Indicates the status of a read transfer.
		input  wire [31:0]  io96b0_ch0_axi_ruser,                   //                         .ruser,         Extension of read data channel.
		input  wire         io96b0_ch0_axi_rvalid,                  //                         .rvalid,        Indicates read data channel signals are valid.
		input  wire         io96b0_ch0_axi_wready,                  //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		output wire [43:0]  io96b0_ch0_axi_araddr,                  //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [1:0]   io96b0_ch0_axi_arburst,                 //                         .arburst,       Burst type indicating how address changes between each transfer in a read transaction.
		output wire [6:0]   io96b0_ch0_axi_arid,                    //                         .arid,          Identification tag for a read transaction.
		output wire [7:0]   io96b0_ch0_axi_arlen,                   //                         .arlen,         Exact number of data transfers in a read transaction.
		output wire         io96b0_ch0_axi_arlock,                  //                         .arlock,        Provides info on atomic characteristics of a read transaction.
		output wire [3:0]   io96b0_ch0_axi_arqos,                   //                         .arqos,         Quality of service identifier for a read transaction.
		output wire [2:0]   io96b0_ch0_axi_arsize,                  //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [13:0]  io96b0_ch0_axi_aruser,                  //                         .aruser,        Extension of read address channel.
		output wire         io96b0_ch0_axi_arvalid,                 //                         .arvalid,       Indicates read address channel signals are valid.
		output wire [43:0]  io96b0_ch0_axi_awaddr,                  //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [1:0]   io96b0_ch0_axi_awburst,                 //                         .awburst,       Burst type indicating how address changes between each transfer in a write transaction.
		output wire [6:0]   io96b0_ch0_axi_awid,                    //                         .awid,          Identification tag for a write transaction.
		output wire [7:0]   io96b0_ch0_axi_awlen,                   //                         .awlen,         Exact number of data transfers in a write transaction.
		output wire         io96b0_ch0_axi_awlock,                  //                         .awlock,        Provides info on atomic characteristics of a write transaction.
		output wire [3:0]   io96b0_ch0_axi_awqos,                   //                         .awqos,         Quality of service identifier for a write transaction.
		output wire [2:0]   io96b0_ch0_axi_awsize,                  //                         .awsize,        Number of bytes in each data transfer in a write transaction.
		output wire [13:0]  io96b0_ch0_axi_awuser,                  //                         .awuser,        Extension of write address channel.
		output wire         io96b0_ch0_axi_awvalid,                 //                         .awvalid,       Indicates write address channel signals are valid.
		output wire         io96b0_ch0_axi_bready,                  //                         .bready,        Indicates a transfer on write response channel can be accepted.
		output wire         io96b0_ch0_axi_rready,                  //                         .rready,        Indicates a transfer on read data channel can be accepted.
		output wire [255:0] io96b0_ch0_axi_wdata,                   //                         .wdata,         Write data.
		output wire         io96b0_ch0_axi_wlast,                   //                         .wlast,         Indicates the last data transfer in a write transaction.
		output wire [31:0]  io96b0_ch0_axi_wstrb,                   //                         .wstrb,         Write strobes indicating which byte lanes hold valid data.
		output wire [31:0]  io96b0_ch0_axi_wuser,                   //                         .wuser,         Extension of the write data channel.
		output wire         io96b0_ch0_axi_wvalid,                  //                         .wvalid,        Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_ch0_axi_arprot,                  //                         .arprot,        Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_ch0_axi_awprot                   //                         .awprot,        Placeholder AWPROT. Protection attributes not supported for this bridge.
	);
endmodule

