// sysid_qsys.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module sysid_qsys (
		input  wire        clock,    //           clk.clk
		input  wire        reset_n,  //         reset.reset_n
		output wire [31:0] readdata, // control_slave.readdata
		input  wire        address   //              .address
	);

	altera_avalon_sysid_qsys #(
		.ID_VALUE  (0),
		.TIMESTAMP (0)
	) sysid_qsys (
		.clock    (clock),    //   input,   width = 1,           clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,         reset.reset_n
		.readdata (readdata), //  output,  width = 32, control_slave.readdata
		.address  (address)   //   input,   width = 1,              .address
	);

endmodule
