module emif_hps_emif_ph2_phy_arch_fp_610_y5glxty #(
   parameter PHY_NOC_EN                                         = 0,
   parameter AXI4_USER_DATA_ENABLE                              = 0,
   parameter MEM_NUM_CHANNELS_PER_IO96                          = 0,
   parameter AXI4_DATA_WIDTH                                    = 0,
   parameter AXI4_ADDR_WIDTH                                    = 0,
   parameter PHY_I3C_EN                                         = 0,
   parameter SLIM_BL_EN                                         = 0,
   parameter AXI4_AXUSER_WIDTH                                  = 0,
   parameter LS_MEM_DQ_WIDTH                                    = 0,
   parameter MEM_LBD_WIDTH                                      = 0,
   parameter MEM_LBS_WIDTH                                      = 0,
   parameter OCT_RZQIN_WIDTH                                    = 0,
   parameter MEM_ACT_N_WIDTH                                    = 0,
   parameter MEM_ALERT_N_WIDTH                                  = 0,
   parameter MEM_A_WIDTH                                        = 0,
   parameter MEM_BANK_ADDR_WIDTH                                = 0,
   parameter MEM_BANK_GROUP_ADDR_WIDTH                          = 0,
   parameter MEM_CA_WIDTH                                       = 0,
   parameter MEM_CHIP_ID_WIDTH                                  = 0,
   parameter MEM_CKE_WIDTH                                      = 0,
   parameter MEM_CK_C_WIDTH                                     = 0,
   parameter MEM_CK_T_WIDTH                                     = 0,
   parameter MEM_CS_N_WIDTH                                     = 0,
   parameter MEM_CS_WIDTH                                       = 0,
   parameter MEM_DBI_N_WIDTH                                    = 0,
   parameter MEM_DMI_WIDTH                                      = 0,
   parameter MEM_DM_N_WIDTH                                     = 0,
   parameter MEM_DQS_C_WIDTH                                    = 0,
   parameter MEM_DQS_T_WIDTH                                    = 0,
   parameter MEM_DQ_WIDTH                                       = 0,
   parameter MEM_ODT_WIDTH                                      = 0,
   parameter MEM_PAR_WIDTH                                      = 0,
   parameter MEM_RDQS_C_WIDTH                                   = 0,
   parameter MEM_RDQS_T_WIDTH                                   = 0,
   parameter MEM_RESET_N_WIDTH                                  = 0,
   parameter MEM_WCK_C_WIDTH                                    = 0,
   parameter MEM_WCK_T_WIDTH                                    = 0
) (
   input  logic            ref_clk_0,
   input  logic            core_init_n_0,
   output logic            noc_aclk_0,
   output logic            noc_rst_n_0,
   input  logic [39:0]     s0_axi4_araddr,
   input  logic [1:0]      s0_axi4_arburst,
   input  logic [6:0]      s0_axi4_arid,
   input  logic [7:0]      s0_axi4_arlen,
   input  logic            s0_axi4_arlock,
   input  logic [3:0]      s0_axi4_arqos,
   input  logic [2:0]      s0_axi4_arsize,
   input  logic            s0_axi4_arvalid,
   input  logic [13:0]     s0_axi4_aruser,
   input  logic [2:0]      s0_axi4_arprot,
   input  logic [39:0]     s0_axi4_awaddr,
   input  logic [1:0]      s0_axi4_awburst,
   input  logic [6:0]      s0_axi4_awid,
   input  logic [7:0]      s0_axi4_awlen,
   input  logic            s0_axi4_awlock,
   input  logic [3:0]      s0_axi4_awqos,
   input  logic [2:0]      s0_axi4_awsize,
   input  logic            s0_axi4_awvalid,
   input  logic [13:0]     s0_axi4_awuser,
   input  logic [2:0]      s0_axi4_awprot,
   input  logic            s0_axi4_bready,
   input  logic            s0_axi4_rready,
   input  logic [255:0]    s0_axi4_wdata,
   input  logic [31:0]     s0_axi4_wstrb,
   input  logic            s0_axi4_wlast,
   input  logic            s0_axi4_wvalid,
   input  logic [31:0]     s0_axi4_wuser,
   output logic [31:0]     s0_axi4_ruser,
   output logic            s0_axi4_arready,
   output logic            s0_axi4_awready,
   output logic [6:0]      s0_axi4_bid,
   output logic [1:0]      s0_axi4_bresp,
   output logic            s0_axi4_bvalid,
   output logic [255:0]    s0_axi4_rdata,
   output logic [6:0]      s0_axi4_rid,
   output logic            s0_axi4_rlast,
   output logic [1:0]      s0_axi4_rresp,
   output logic            s0_axi4_rvalid,
   output logic            s0_axi4_wready,
   output logic            mem_ck_t_0,
   output logic            mem_ck_c_0,
   output logic            mem_cke_0,
   output logic            mem_odt_0,
   output logic            mem_cs_n_0,
   output logic [16:0]     mem_a_0,
   output logic [1:0]      mem_ba_0,
   output logic            mem_bg_0,
   output logic            mem_act_n_0,
   output logic            mem_par_0,
   input  logic            mem_alert_n_0,
   output logic            mem_reset_n_0,
   inout  tri   [31:0]     mem_dq_0,
   inout  tri   [3:0]      mem_dqs_t_0,
   inout  tri   [3:0]      mem_dqs_c_0,
   inout  tri   [3:0]      mem_dbi_n_0,
   input  logic [1341:0]   calbus_0,
   output logic [1314:0]   calbus_readdata_0,
   output logic [32767:0]  calbus_param_table_0,
   output logic            i3c_scl_0,
   inout  tri              i3c_sda_0,
   input  logic            oct_rzqin_0
);
   timeunit 1ns;
   timeprecision 1ps;

   emif_hps_emif_ph2_phy_arch_fp_610_y5glxty_phy_arch_fp_top # (
      .PHY_NOC_EN (PHY_NOC_EN),
      .AXI4_USER_DATA_ENABLE (AXI4_USER_DATA_ENABLE),
      .MEM_NUM_CHANNELS_PER_IO96 (MEM_NUM_CHANNELS_PER_IO96),
      .AXI4_DATA_WIDTH (AXI4_DATA_WIDTH),
      .AXI4_ADDR_WIDTH (AXI4_ADDR_WIDTH),
      .PHY_I3C_EN (PHY_I3C_EN),
      .SLIM_BL_EN (SLIM_BL_EN),
      .AXI4_AXUSER_WIDTH (AXI4_AXUSER_WIDTH),
      .LS_MEM_DQ_WIDTH (LS_MEM_DQ_WIDTH),
      .MEM_LBD_WIDTH (MEM_LBD_WIDTH),
      .MEM_LBS_WIDTH (MEM_LBS_WIDTH),
      .OCT_RZQIN_WIDTH (OCT_RZQIN_WIDTH),
      .MEM_ACT_N_WIDTH (MEM_ACT_N_WIDTH),
      .MEM_ALERT_N_WIDTH (MEM_ALERT_N_WIDTH),
      .MEM_A_WIDTH (MEM_A_WIDTH),
      .MEM_BANK_ADDR_WIDTH (MEM_BANK_ADDR_WIDTH),
      .MEM_BANK_GROUP_ADDR_WIDTH (MEM_BANK_GROUP_ADDR_WIDTH),
      .MEM_CA_WIDTH (MEM_CA_WIDTH),
      .MEM_CHIP_ID_WIDTH (MEM_CHIP_ID_WIDTH),
      .MEM_CKE_WIDTH (MEM_CKE_WIDTH),
      .MEM_CK_C_WIDTH (MEM_CK_C_WIDTH),
      .MEM_CK_T_WIDTH (MEM_CK_T_WIDTH),
      .MEM_CS_N_WIDTH (MEM_CS_N_WIDTH),
      .MEM_CS_WIDTH (MEM_CS_WIDTH),
      .MEM_DBI_N_WIDTH (MEM_DBI_N_WIDTH),
      .MEM_DMI_WIDTH (MEM_DMI_WIDTH),
      .MEM_DM_N_WIDTH (MEM_DM_N_WIDTH),
      .MEM_DQS_C_WIDTH (MEM_DQS_C_WIDTH),
      .MEM_DQS_T_WIDTH (MEM_DQS_T_WIDTH),
      .MEM_DQ_WIDTH (MEM_DQ_WIDTH),
      .MEM_ODT_WIDTH (MEM_ODT_WIDTH),
      .MEM_PAR_WIDTH (MEM_PAR_WIDTH),
      .MEM_RDQS_C_WIDTH (MEM_RDQS_C_WIDTH),
      .MEM_RDQS_T_WIDTH (MEM_RDQS_T_WIDTH),
      .MEM_RESET_N_WIDTH (MEM_RESET_N_WIDTH),
      .MEM_WCK_C_WIDTH (MEM_WCK_C_WIDTH),
      .MEM_WCK_T_WIDTH (MEM_WCK_T_WIDTH)
   ) emif_hps_emif_ph2_phy_arch_fp_610_y5glxty_phy_arch_fp_inst (
      .ref_clk_0 (ref_clk_0),
      .core_init_n_0 (core_init_n_0),
      .noc_aclk_0 (noc_aclk_0),
      .noc_rst_n_0 (noc_rst_n_0),
      .s0_axi4_araddr (s0_axi4_araddr),
      .s0_axi4_arburst (s0_axi4_arburst),
      .s0_axi4_arid (s0_axi4_arid),
      .s0_axi4_arlen (s0_axi4_arlen),
      .s0_axi4_arlock (s0_axi4_arlock),
      .s0_axi4_arqos (s0_axi4_arqos),
      .s0_axi4_arsize (s0_axi4_arsize),
      .s0_axi4_arvalid (s0_axi4_arvalid),
      .s0_axi4_aruser (s0_axi4_aruser),
      .s0_axi4_arprot (s0_axi4_arprot),
      .s0_axi4_awaddr (s0_axi4_awaddr),
      .s0_axi4_awburst (s0_axi4_awburst),
      .s0_axi4_awid (s0_axi4_awid),
      .s0_axi4_awlen (s0_axi4_awlen),
      .s0_axi4_awlock (s0_axi4_awlock),
      .s0_axi4_awqos (s0_axi4_awqos),
      .s0_axi4_awsize (s0_axi4_awsize),
      .s0_axi4_awvalid (s0_axi4_awvalid),
      .s0_axi4_awuser (s0_axi4_awuser),
      .s0_axi4_awprot (s0_axi4_awprot),
      .s0_axi4_bready (s0_axi4_bready),
      .s0_axi4_rready (s0_axi4_rready),
      .s0_axi4_wdata (s0_axi4_wdata),
      .s0_axi4_wstrb (s0_axi4_wstrb),
      .s0_axi4_wlast (s0_axi4_wlast),
      .s0_axi4_wvalid (s0_axi4_wvalid),
      .s0_axi4_wuser (s0_axi4_wuser),
      .s0_axi4_ruser (s0_axi4_ruser),
      .s0_axi4_arready (s0_axi4_arready),
      .s0_axi4_awready (s0_axi4_awready),
      .s0_axi4_bid (s0_axi4_bid),
      .s0_axi4_bresp (s0_axi4_bresp),
      .s0_axi4_bvalid (s0_axi4_bvalid),
      .s0_axi4_rdata (s0_axi4_rdata),
      .s0_axi4_rid (s0_axi4_rid),
      .s0_axi4_rlast (s0_axi4_rlast),
      .s0_axi4_rresp (s0_axi4_rresp),
      .s0_axi4_rvalid (s0_axi4_rvalid),
      .s0_axi4_wready (s0_axi4_wready),
      .mem_ck_t_0 (mem_ck_t_0),
      .mem_ck_c_0 (mem_ck_c_0),
      .mem_cke_0 (mem_cke_0),
      .mem_odt_0 (mem_odt_0),
      .mem_cs_n_0 (mem_cs_n_0),
      .mem_a_0 (mem_a_0),
      .mem_ba_0 (mem_ba_0),
      .mem_bg_0 (mem_bg_0),
      .mem_act_n_0 (mem_act_n_0),
      .mem_par_0 (mem_par_0),
      .mem_alert_n_0 (mem_alert_n_0),
      .mem_reset_n_0 (mem_reset_n_0),
      .mem_dq_0 (mem_dq_0),
      .mem_dqs_t_0 (mem_dqs_t_0),
      .mem_dqs_c_0 (mem_dqs_c_0),
      .mem_dbi_n_0 (mem_dbi_n_0),
      .calbus_0 (calbus_0),
      .calbus_readdata_0 (calbus_readdata_0),
      .calbus_param_table_0 (calbus_param_table_0),
      .i3c_scl_0 (i3c_scl_0),
      .i3c_sda_0 (i3c_sda_0),
      .oct_rzqin_0 (oct_rzqin_0)
   );
endmodule
