// board_info_pio.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module board_info_pio (
		input  wire        clk,      //                 clk.clk
		input  wire        reset_n,  //               reset.reset_n
		input  wire [1:0]  address,  //                  s1.address
		output wire [31:0] readdata, //                    .readdata
		input  wire [15:0] in_port   // external_connection.export
	);

	board_info_pio_altera_avalon_pio_1923_2qhtowy board_info_pio (
		.clk      (clk),      //   input,   width = 1,                 clk.clk
		.reset_n  (reset_n),  //   input,   width = 1,               reset.reset_n
		.address  (address),  //   input,   width = 2,                  s1.address
		.readdata (readdata), //  output,  width = 32,                    .readdata
		.in_port  (in_port)   //   input,  width = 16, external_connection.export
	);

endmodule
