// user_rst_clkgate_0.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module user_rst_clkgate_0 (
		output wire  ninit_done  // ninit_done.ninit_done
	);

	intel_user_rst_clkgate intel_user_rst_clkgate_inst (
		.ninit_done (ninit_done)  //  output,  width = 1, ninit_done.ninit_done
	);

endmodule
