// system_altera_mm_interconnect_1920_fdcsucq.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module system_altera_mm_interconnect_1920_fdcsucq (
		input  wire [31:0] intel_niosv_g_data_manager_awaddr,                                           //                                            intel_niosv_g_data_manager.awaddr
		input  wire [7:0]  intel_niosv_g_data_manager_awlen,                                            //                                                                      .awlen
		input  wire [2:0]  intel_niosv_g_data_manager_awsize,                                           //                                                                      .awsize
		input  wire [2:0]  intel_niosv_g_data_manager_awprot,                                           //                                                                      .awprot
		input  wire        intel_niosv_g_data_manager_awvalid,                                          //                                                                      .awvalid
		output wire        intel_niosv_g_data_manager_awready,                                          //                                                                      .awready
		input  wire [31:0] intel_niosv_g_data_manager_wdata,                                            //                                                                      .wdata
		input  wire [3:0]  intel_niosv_g_data_manager_wstrb,                                            //                                                                      .wstrb
		input  wire        intel_niosv_g_data_manager_wlast,                                            //                                                                      .wlast
		input  wire        intel_niosv_g_data_manager_wvalid,                                           //                                                                      .wvalid
		output wire        intel_niosv_g_data_manager_wready,                                           //                                                                      .wready
		output wire [1:0]  intel_niosv_g_data_manager_bresp,                                            //                                                                      .bresp
		output wire        intel_niosv_g_data_manager_bvalid,                                           //                                                                      .bvalid
		input  wire        intel_niosv_g_data_manager_bready,                                           //                                                                      .bready
		input  wire [31:0] intel_niosv_g_data_manager_araddr,                                           //                                                                      .araddr
		input  wire [7:0]  intel_niosv_g_data_manager_arlen,                                            //                                                                      .arlen
		input  wire [2:0]  intel_niosv_g_data_manager_arsize,                                           //                                                                      .arsize
		input  wire [2:0]  intel_niosv_g_data_manager_arprot,                                           //                                                                      .arprot
		input  wire        intel_niosv_g_data_manager_arvalid,                                          //                                                                      .arvalid
		output wire        intel_niosv_g_data_manager_arready,                                          //                                                                      .arready
		output wire [31:0] intel_niosv_g_data_manager_rdata,                                            //                                                                      .rdata
		output wire [1:0]  intel_niosv_g_data_manager_rresp,                                            //                                                                      .rresp
		output wire        intel_niosv_g_data_manager_rlast,                                            //                                                                      .rlast
		output wire        intel_niosv_g_data_manager_rvalid,                                           //                                                                      .rvalid
		input  wire        intel_niosv_g_data_manager_rready,                                           //                                                                      .rready
		input  wire [31:0] intel_niosv_g_instruction_manager_awaddr,                                    //                                     intel_niosv_g_instruction_manager.awaddr
		input  wire [7:0]  intel_niosv_g_instruction_manager_awlen,                                     //                                                                      .awlen
		input  wire [2:0]  intel_niosv_g_instruction_manager_awsize,                                    //                                                                      .awsize
		input  wire [1:0]  intel_niosv_g_instruction_manager_awburst,                                   //                                                                      .awburst
		input  wire [2:0]  intel_niosv_g_instruction_manager_awprot,                                    //                                                                      .awprot
		input  wire        intel_niosv_g_instruction_manager_awvalid,                                   //                                                                      .awvalid
		output wire        intel_niosv_g_instruction_manager_awready,                                   //                                                                      .awready
		input  wire [31:0] intel_niosv_g_instruction_manager_wdata,                                     //                                                                      .wdata
		input  wire [3:0]  intel_niosv_g_instruction_manager_wstrb,                                     //                                                                      .wstrb
		input  wire        intel_niosv_g_instruction_manager_wlast,                                     //                                                                      .wlast
		input  wire        intel_niosv_g_instruction_manager_wvalid,                                    //                                                                      .wvalid
		output wire        intel_niosv_g_instruction_manager_wready,                                    //                                                                      .wready
		output wire [1:0]  intel_niosv_g_instruction_manager_bresp,                                     //                                                                      .bresp
		output wire        intel_niosv_g_instruction_manager_bvalid,                                    //                                                                      .bvalid
		input  wire        intel_niosv_g_instruction_manager_bready,                                    //                                                                      .bready
		input  wire [31:0] intel_niosv_g_instruction_manager_araddr,                                    //                                                                      .araddr
		input  wire [7:0]  intel_niosv_g_instruction_manager_arlen,                                     //                                                                      .arlen
		input  wire [2:0]  intel_niosv_g_instruction_manager_arsize,                                    //                                                                      .arsize
		input  wire [1:0]  intel_niosv_g_instruction_manager_arburst,                                   //                                                                      .arburst
		input  wire [2:0]  intel_niosv_g_instruction_manager_arprot,                                    //                                                                      .arprot
		input  wire        intel_niosv_g_instruction_manager_arvalid,                                   //                                                                      .arvalid
		output wire        intel_niosv_g_instruction_manager_arready,                                   //                                                                      .arready
		output wire [31:0] intel_niosv_g_instruction_manager_rdata,                                     //                                                                      .rdata
		output wire [1:0]  intel_niosv_g_instruction_manager_rresp,                                     //                                                                      .rresp
		output wire        intel_niosv_g_instruction_manager_rlast,                                     //                                                                      .rlast
		output wire        intel_niosv_g_instruction_manager_rvalid,                                    //                                                                      .rvalid
		input  wire        intel_niosv_g_instruction_manager_rready,                                    //                                                                      .rready
		output wire [0:0]  jtag_uart_avalon_jtag_slave_address,                                         //                                           jtag_uart_avalon_jtag_slave.address
		output wire        jtag_uart_avalon_jtag_slave_write,                                           //                                                                      .write
		output wire        jtag_uart_avalon_jtag_slave_read,                                            //                                                                      .read
		input  wire [31:0] jtag_uart_avalon_jtag_slave_readdata,                                        //                                                                      .readdata
		output wire [31:0] jtag_uart_avalon_jtag_slave_writedata,                                       //                                                                      .writedata
		input  wire        jtag_uart_avalon_jtag_slave_waitrequest,                                     //                                                                      .waitrequest
		output wire        jtag_uart_avalon_jtag_slave_chipselect,                                      //                                                                      .chipselect
		output wire [0:0]  sysid_qsys_control_slave_address,                                            //                                              sysid_qsys_control_slave.address
		input  wire [31:0] sysid_qsys_control_slave_readdata,                                           //                                                                      .readdata
		output wire [15:0] intel_niosv_g_dm_agent_address,                                              //                                                intel_niosv_g_dm_agent.address
		output wire        intel_niosv_g_dm_agent_write,                                                //                                                                      .write
		output wire        intel_niosv_g_dm_agent_read,                                                 //                                                                      .read
		input  wire [31:0] intel_niosv_g_dm_agent_readdata,                                             //                                                                      .readdata
		output wire [31:0] intel_niosv_g_dm_agent_writedata,                                            //                                                                      .writedata
		input  wire        intel_niosv_g_dm_agent_readdatavalid,                                        //                                                                      .readdatavalid
		input  wire        intel_niosv_g_dm_agent_waitrequest,                                          //                                                                      .waitrequest
		output wire [2:0]  timer_s1_address,                                                            //                                                              timer_s1.address
		output wire        timer_s1_write,                                                              //                                                                      .write
		input  wire [15:0] timer_s1_readdata,                                                           //                                                                      .readdata
		output wire [15:0] timer_s1_writedata,                                                          //                                                                      .writedata
		output wire        timer_s1_chipselect,                                                         //                                                                      .chipselect
		output wire [1:0]  board_info_power_in_voltage_s1_address,                                      //                                        board_info_power_in_voltage_s1.address
		input  wire [31:0] board_info_power_in_voltage_s1_readdata,                                     //                                                                      .readdata
		output wire [1:0]  board_info_vcc1p2_voltage_s1_address,                                        //                                          board_info_vcc1p2_voltage_s1.address
		input  wire [31:0] board_info_vcc1p2_voltage_s1_readdata,                                       //                                                                      .readdata
		output wire [1:0]  board_info_vcc1p2_current_s1_address,                                        //                                          board_info_vcc1p2_current_s1.address
		input  wire [31:0] board_info_vcc1p2_current_s1_readdata,                                       //                                                                      .readdata
		output wire [1:0]  board_info_fan_speed_s1_address,                                             //                                               board_info_fan_speed_s1.address
		input  wire [31:0] board_info_fan_speed_s1_readdata,                                            //                                                                      .readdata
		output wire [1:0]  board_info_temperature_fpga_s1_address,                                      //                                        board_info_temperature_fpga_s1.address
		input  wire [31:0] board_info_temperature_fpga_s1_readdata,                                     //                                                                      .readdata
		output wire [1:0]  board_info_temperature_board1_s1_address,                                    //                                      board_info_temperature_board1_s1.address
		input  wire [31:0] board_info_temperature_board1_s1_readdata,                                   //                                                                      .readdata
		output wire [1:0]  board_info_pin_status_s1_address,                                            //                                              board_info_pin_status_s1.address
		input  wire [31:0] board_info_pin_status_s1_readdata,                                           //                                                                      .readdata
		output wire [1:0]  board_info_temperature_board2_s1_address,                                    //                                      board_info_temperature_board2_s1.address
		input  wire [31:0] board_info_temperature_board2_s1_readdata,                                   //                                                                      .readdata
		output wire [16:0] intel_onchip_memory_s1_address,                                              //                                                intel_onchip_memory_s1.address
		output wire        intel_onchip_memory_s1_write,                                                //                                                                      .write
		output wire        intel_onchip_memory_s1_read,                                                 //                                                                      .read
		input  wire [31:0] intel_onchip_memory_s1_readdata,                                             //                                                                      .readdata
		output wire [31:0] intel_onchip_memory_s1_writedata,                                            //                                                                      .writedata
		output wire [3:0]  intel_onchip_memory_s1_byteenable,                                           //                                                                      .byteenable
		output wire [5:0]  intel_niosv_g_timer_sw_agent_address,                                        //                                          intel_niosv_g_timer_sw_agent.address
		output wire        intel_niosv_g_timer_sw_agent_write,                                          //                                                                      .write
		output wire        intel_niosv_g_timer_sw_agent_read,                                           //                                                                      .read
		input  wire [31:0] intel_niosv_g_timer_sw_agent_readdata,                                       //                                                                      .readdata
		output wire [31:0] intel_niosv_g_timer_sw_agent_writedata,                                      //                                                                      .writedata
		output wire [3:0]  intel_niosv_g_timer_sw_agent_byteenable,                                     //                                                                      .byteenable
		input  wire        intel_niosv_g_timer_sw_agent_readdatavalid,                                  //                                                                      .readdatavalid
		input  wire        intel_niosv_g_timer_sw_agent_waitrequest,                                    //                                                                      .waitrequest
		input  wire        intel_niosv_g_reset_reset_bridge_in_reset_reset,                             //                             intel_niosv_g_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset, // intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        clock_in_out_clk_clk                                                         //                                                      clock_in_out_clk.clk,          Clock Input
	);

	wire    [0:0] intel_niosv_g_data_manager_translator_m0_ruser;                       // intel_niosv_g_data_manager_agent:ruser -> intel_niosv_g_data_manager_translator:m0_ruser
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_wuser;                       // intel_niosv_g_data_manager_translator:m0_wuser -> intel_niosv_g_data_manager_agent:wuser
	wire    [1:0] intel_niosv_g_data_manager_translator_m0_awburst;                     // intel_niosv_g_data_manager_translator:m0_awburst -> intel_niosv_g_data_manager_agent:awburst
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_arregion;                    // intel_niosv_g_data_manager_translator:m0_arregion -> intel_niosv_g_data_manager_agent:arregion
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_awuser;                      // intel_niosv_g_data_manager_translator:m0_awuser -> intel_niosv_g_data_manager_agent:awuser
	wire    [7:0] intel_niosv_g_data_manager_translator_m0_arlen;                       // intel_niosv_g_data_manager_translator:m0_arlen -> intel_niosv_g_data_manager_agent:arlen
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_arqos;                       // intel_niosv_g_data_manager_translator:m0_arqos -> intel_niosv_g_data_manager_agent:arqos
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_wstrb;                       // intel_niosv_g_data_manager_translator:m0_wstrb -> intel_niosv_g_data_manager_agent:wstrb
	wire          intel_niosv_g_data_manager_translator_m0_wready;                      // intel_niosv_g_data_manager_agent:wready -> intel_niosv_g_data_manager_translator:m0_wready
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_rid;                         // intel_niosv_g_data_manager_agent:rid -> intel_niosv_g_data_manager_translator:m0_rid
	wire          intel_niosv_g_data_manager_translator_m0_rready;                      // intel_niosv_g_data_manager_translator:m0_rready -> intel_niosv_g_data_manager_agent:rready
	wire    [7:0] intel_niosv_g_data_manager_translator_m0_awlen;                       // intel_niosv_g_data_manager_translator:m0_awlen -> intel_niosv_g_data_manager_agent:awlen
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_awqos;                       // intel_niosv_g_data_manager_translator:m0_awqos -> intel_niosv_g_data_manager_agent:awqos
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_arcache;                     // intel_niosv_g_data_manager_translator:m0_arcache -> intel_niosv_g_data_manager_agent:arcache
	wire          intel_niosv_g_data_manager_translator_m0_wvalid;                      // intel_niosv_g_data_manager_translator:m0_wvalid -> intel_niosv_g_data_manager_agent:wvalid
	wire   [31:0] intel_niosv_g_data_manager_translator_m0_araddr;                      // intel_niosv_g_data_manager_translator:m0_araddr -> intel_niosv_g_data_manager_agent:araddr
	wire    [2:0] intel_niosv_g_data_manager_translator_m0_arprot;                      // intel_niosv_g_data_manager_translator:m0_arprot -> intel_niosv_g_data_manager_agent:arprot
	wire    [2:0] intel_niosv_g_data_manager_translator_m0_awprot;                      // intel_niosv_g_data_manager_translator:m0_awprot -> intel_niosv_g_data_manager_agent:awprot
	wire   [31:0] intel_niosv_g_data_manager_translator_m0_wdata;                       // intel_niosv_g_data_manager_translator:m0_wdata -> intel_niosv_g_data_manager_agent:wdata
	wire          intel_niosv_g_data_manager_translator_m0_arvalid;                     // intel_niosv_g_data_manager_translator:m0_arvalid -> intel_niosv_g_data_manager_agent:arvalid
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_awcache;                     // intel_niosv_g_data_manager_translator:m0_awcache -> intel_niosv_g_data_manager_agent:awcache
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_arid;                        // intel_niosv_g_data_manager_translator:m0_arid -> intel_niosv_g_data_manager_agent:arid
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_arlock;                      // intel_niosv_g_data_manager_translator:m0_arlock -> intel_niosv_g_data_manager_agent:arlock
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_awlock;                      // intel_niosv_g_data_manager_translator:m0_awlock -> intel_niosv_g_data_manager_agent:awlock
	wire   [31:0] intel_niosv_g_data_manager_translator_m0_awaddr;                      // intel_niosv_g_data_manager_translator:m0_awaddr -> intel_niosv_g_data_manager_agent:awaddr
	wire    [1:0] intel_niosv_g_data_manager_translator_m0_bresp;                       // intel_niosv_g_data_manager_agent:bresp -> intel_niosv_g_data_manager_translator:m0_bresp
	wire          intel_niosv_g_data_manager_translator_m0_arready;                     // intel_niosv_g_data_manager_agent:arready -> intel_niosv_g_data_manager_translator:m0_arready
	wire   [31:0] intel_niosv_g_data_manager_translator_m0_rdata;                       // intel_niosv_g_data_manager_agent:rdata -> intel_niosv_g_data_manager_translator:m0_rdata
	wire          intel_niosv_g_data_manager_translator_m0_awready;                     // intel_niosv_g_data_manager_agent:awready -> intel_niosv_g_data_manager_translator:m0_awready
	wire    [1:0] intel_niosv_g_data_manager_translator_m0_arburst;                     // intel_niosv_g_data_manager_translator:m0_arburst -> intel_niosv_g_data_manager_agent:arburst
	wire    [2:0] intel_niosv_g_data_manager_translator_m0_arsize;                      // intel_niosv_g_data_manager_translator:m0_arsize -> intel_niosv_g_data_manager_agent:arsize
	wire          intel_niosv_g_data_manager_translator_m0_bready;                      // intel_niosv_g_data_manager_translator:m0_bready -> intel_niosv_g_data_manager_agent:bready
	wire          intel_niosv_g_data_manager_translator_m0_rlast;                       // intel_niosv_g_data_manager_agent:rlast -> intel_niosv_g_data_manager_translator:m0_rlast
	wire          intel_niosv_g_data_manager_translator_m0_wlast;                       // intel_niosv_g_data_manager_translator:m0_wlast -> intel_niosv_g_data_manager_agent:wlast
	wire    [3:0] intel_niosv_g_data_manager_translator_m0_awregion;                    // intel_niosv_g_data_manager_translator:m0_awregion -> intel_niosv_g_data_manager_agent:awregion
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_buser;                       // intel_niosv_g_data_manager_agent:buser -> intel_niosv_g_data_manager_translator:m0_buser
	wire    [1:0] intel_niosv_g_data_manager_translator_m0_rresp;                       // intel_niosv_g_data_manager_agent:rresp -> intel_niosv_g_data_manager_translator:m0_rresp
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_awid;                        // intel_niosv_g_data_manager_translator:m0_awid -> intel_niosv_g_data_manager_agent:awid
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_bid;                         // intel_niosv_g_data_manager_agent:bid -> intel_niosv_g_data_manager_translator:m0_bid
	wire          intel_niosv_g_data_manager_translator_m0_bvalid;                      // intel_niosv_g_data_manager_agent:bvalid -> intel_niosv_g_data_manager_translator:m0_bvalid
	wire    [2:0] intel_niosv_g_data_manager_translator_m0_awsize;                      // intel_niosv_g_data_manager_translator:m0_awsize -> intel_niosv_g_data_manager_agent:awsize
	wire          intel_niosv_g_data_manager_translator_m0_awvalid;                     // intel_niosv_g_data_manager_translator:m0_awvalid -> intel_niosv_g_data_manager_agent:awvalid
	wire    [0:0] intel_niosv_g_data_manager_translator_m0_aruser;                      // intel_niosv_g_data_manager_translator:m0_aruser -> intel_niosv_g_data_manager_agent:aruser
	wire          intel_niosv_g_data_manager_translator_m0_rvalid;                      // intel_niosv_g_data_manager_agent:rvalid -> intel_niosv_g_data_manager_translator:m0_rvalid
	wire          rsp_mux_src_valid;                                                    // rsp_mux:src_valid -> intel_niosv_g_data_manager_agent:write_rp_valid
	wire  [145:0] rsp_mux_src_data;                                                     // rsp_mux:src_data -> intel_niosv_g_data_manager_agent:write_rp_data
	wire          rsp_mux_src_ready;                                                    // intel_niosv_g_data_manager_agent:write_rp_ready -> rsp_mux:src_ready
	wire   [13:0] rsp_mux_src_channel;                                                  // rsp_mux:src_channel -> intel_niosv_g_data_manager_agent:write_rp_channel
	wire          rsp_mux_src_startofpacket;                                            // rsp_mux:src_startofpacket -> intel_niosv_g_data_manager_agent:write_rp_startofpacket
	wire          rsp_mux_src_endofpacket;                                              // rsp_mux:src_endofpacket -> intel_niosv_g_data_manager_agent:write_rp_endofpacket
	wire          rsp_mux_001_src_valid;                                                // rsp_mux_001:src_valid -> intel_niosv_g_data_manager_agent:read_rp_valid
	wire  [145:0] rsp_mux_001_src_data;                                                 // rsp_mux_001:src_data -> intel_niosv_g_data_manager_agent:read_rp_data
	wire          rsp_mux_001_src_ready;                                                // intel_niosv_g_data_manager_agent:read_rp_ready -> rsp_mux_001:src_ready
	wire   [13:0] rsp_mux_001_src_channel;                                              // rsp_mux_001:src_channel -> intel_niosv_g_data_manager_agent:read_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                        // rsp_mux_001:src_startofpacket -> intel_niosv_g_data_manager_agent:read_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                          // rsp_mux_001:src_endofpacket -> intel_niosv_g_data_manager_agent:read_rp_endofpacket
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_ruser;                // intel_niosv_g_instruction_manager_agent:ruser -> intel_niosv_g_instruction_manager_translator:m0_ruser
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_wuser;                // intel_niosv_g_instruction_manager_translator:m0_wuser -> intel_niosv_g_instruction_manager_agent:wuser
	wire    [1:0] intel_niosv_g_instruction_manager_translator_m0_awburst;              // intel_niosv_g_instruction_manager_translator:m0_awburst -> intel_niosv_g_instruction_manager_agent:awburst
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_arregion;             // intel_niosv_g_instruction_manager_translator:m0_arregion -> intel_niosv_g_instruction_manager_agent:arregion
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_awuser;               // intel_niosv_g_instruction_manager_translator:m0_awuser -> intel_niosv_g_instruction_manager_agent:awuser
	wire    [7:0] intel_niosv_g_instruction_manager_translator_m0_arlen;                // intel_niosv_g_instruction_manager_translator:m0_arlen -> intel_niosv_g_instruction_manager_agent:arlen
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_arqos;                // intel_niosv_g_instruction_manager_translator:m0_arqos -> intel_niosv_g_instruction_manager_agent:arqos
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_wstrb;                // intel_niosv_g_instruction_manager_translator:m0_wstrb -> intel_niosv_g_instruction_manager_agent:wstrb
	wire          intel_niosv_g_instruction_manager_translator_m0_wready;               // intel_niosv_g_instruction_manager_agent:wready -> intel_niosv_g_instruction_manager_translator:m0_wready
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_rid;                  // intel_niosv_g_instruction_manager_agent:rid -> intel_niosv_g_instruction_manager_translator:m0_rid
	wire          intel_niosv_g_instruction_manager_translator_m0_rready;               // intel_niosv_g_instruction_manager_translator:m0_rready -> intel_niosv_g_instruction_manager_agent:rready
	wire    [7:0] intel_niosv_g_instruction_manager_translator_m0_awlen;                // intel_niosv_g_instruction_manager_translator:m0_awlen -> intel_niosv_g_instruction_manager_agent:awlen
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_awqos;                // intel_niosv_g_instruction_manager_translator:m0_awqos -> intel_niosv_g_instruction_manager_agent:awqos
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_arcache;              // intel_niosv_g_instruction_manager_translator:m0_arcache -> intel_niosv_g_instruction_manager_agent:arcache
	wire          intel_niosv_g_instruction_manager_translator_m0_wvalid;               // intel_niosv_g_instruction_manager_translator:m0_wvalid -> intel_niosv_g_instruction_manager_agent:wvalid
	wire   [31:0] intel_niosv_g_instruction_manager_translator_m0_araddr;               // intel_niosv_g_instruction_manager_translator:m0_araddr -> intel_niosv_g_instruction_manager_agent:araddr
	wire    [2:0] intel_niosv_g_instruction_manager_translator_m0_arprot;               // intel_niosv_g_instruction_manager_translator:m0_arprot -> intel_niosv_g_instruction_manager_agent:arprot
	wire    [2:0] intel_niosv_g_instruction_manager_translator_m0_awprot;               // intel_niosv_g_instruction_manager_translator:m0_awprot -> intel_niosv_g_instruction_manager_agent:awprot
	wire   [31:0] intel_niosv_g_instruction_manager_translator_m0_wdata;                // intel_niosv_g_instruction_manager_translator:m0_wdata -> intel_niosv_g_instruction_manager_agent:wdata
	wire          intel_niosv_g_instruction_manager_translator_m0_arvalid;              // intel_niosv_g_instruction_manager_translator:m0_arvalid -> intel_niosv_g_instruction_manager_agent:arvalid
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_awcache;              // intel_niosv_g_instruction_manager_translator:m0_awcache -> intel_niosv_g_instruction_manager_agent:awcache
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_arid;                 // intel_niosv_g_instruction_manager_translator:m0_arid -> intel_niosv_g_instruction_manager_agent:arid
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_arlock;               // intel_niosv_g_instruction_manager_translator:m0_arlock -> intel_niosv_g_instruction_manager_agent:arlock
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_awlock;               // intel_niosv_g_instruction_manager_translator:m0_awlock -> intel_niosv_g_instruction_manager_agent:awlock
	wire   [31:0] intel_niosv_g_instruction_manager_translator_m0_awaddr;               // intel_niosv_g_instruction_manager_translator:m0_awaddr -> intel_niosv_g_instruction_manager_agent:awaddr
	wire    [1:0] intel_niosv_g_instruction_manager_translator_m0_bresp;                // intel_niosv_g_instruction_manager_agent:bresp -> intel_niosv_g_instruction_manager_translator:m0_bresp
	wire          intel_niosv_g_instruction_manager_translator_m0_arready;              // intel_niosv_g_instruction_manager_agent:arready -> intel_niosv_g_instruction_manager_translator:m0_arready
	wire   [31:0] intel_niosv_g_instruction_manager_translator_m0_rdata;                // intel_niosv_g_instruction_manager_agent:rdata -> intel_niosv_g_instruction_manager_translator:m0_rdata
	wire          intel_niosv_g_instruction_manager_translator_m0_awready;              // intel_niosv_g_instruction_manager_agent:awready -> intel_niosv_g_instruction_manager_translator:m0_awready
	wire    [1:0] intel_niosv_g_instruction_manager_translator_m0_arburst;              // intel_niosv_g_instruction_manager_translator:m0_arburst -> intel_niosv_g_instruction_manager_agent:arburst
	wire    [2:0] intel_niosv_g_instruction_manager_translator_m0_arsize;               // intel_niosv_g_instruction_manager_translator:m0_arsize -> intel_niosv_g_instruction_manager_agent:arsize
	wire          intel_niosv_g_instruction_manager_translator_m0_bready;               // intel_niosv_g_instruction_manager_translator:m0_bready -> intel_niosv_g_instruction_manager_agent:bready
	wire          intel_niosv_g_instruction_manager_translator_m0_rlast;                // intel_niosv_g_instruction_manager_agent:rlast -> intel_niosv_g_instruction_manager_translator:m0_rlast
	wire          intel_niosv_g_instruction_manager_translator_m0_wlast;                // intel_niosv_g_instruction_manager_translator:m0_wlast -> intel_niosv_g_instruction_manager_agent:wlast
	wire    [3:0] intel_niosv_g_instruction_manager_translator_m0_awregion;             // intel_niosv_g_instruction_manager_translator:m0_awregion -> intel_niosv_g_instruction_manager_agent:awregion
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_buser;                // intel_niosv_g_instruction_manager_agent:buser -> intel_niosv_g_instruction_manager_translator:m0_buser
	wire    [1:0] intel_niosv_g_instruction_manager_translator_m0_rresp;                // intel_niosv_g_instruction_manager_agent:rresp -> intel_niosv_g_instruction_manager_translator:m0_rresp
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_awid;                 // intel_niosv_g_instruction_manager_translator:m0_awid -> intel_niosv_g_instruction_manager_agent:awid
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_bid;                  // intel_niosv_g_instruction_manager_agent:bid -> intel_niosv_g_instruction_manager_translator:m0_bid
	wire          intel_niosv_g_instruction_manager_translator_m0_bvalid;               // intel_niosv_g_instruction_manager_agent:bvalid -> intel_niosv_g_instruction_manager_translator:m0_bvalid
	wire    [2:0] intel_niosv_g_instruction_manager_translator_m0_awsize;               // intel_niosv_g_instruction_manager_translator:m0_awsize -> intel_niosv_g_instruction_manager_agent:awsize
	wire          intel_niosv_g_instruction_manager_translator_m0_awvalid;              // intel_niosv_g_instruction_manager_translator:m0_awvalid -> intel_niosv_g_instruction_manager_agent:awvalid
	wire    [0:0] intel_niosv_g_instruction_manager_translator_m0_aruser;               // intel_niosv_g_instruction_manager_translator:m0_aruser -> intel_niosv_g_instruction_manager_agent:aruser
	wire          intel_niosv_g_instruction_manager_translator_m0_rvalid;               // intel_niosv_g_instruction_manager_agent:rvalid -> intel_niosv_g_instruction_manager_translator:m0_rvalid
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata;                        // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_waitrequest;                     // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
	wire          jtag_uart_avalon_jtag_slave_agent_m0_debugaccess;                     // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_address;                         // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
	wire    [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable;                      // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
	wire          jtag_uart_avalon_jtag_slave_agent_m0_read;                            // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
	wire          jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid;                   // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
	wire          jtag_uart_avalon_jtag_slave_agent_m0_lock;                            // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
	wire   [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata;                       // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
	wire          jtag_uart_avalon_jtag_slave_agent_m0_write;                           // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
	wire    [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount;                      // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_valid;                    // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
	wire  [146:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data;                     // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_ready;                    // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket;            // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket;              // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid;                 // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
	wire  [146:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data;                  // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready;                 // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket;         // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket;           // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid;               // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_valid
	wire   [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data;                // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_data
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready;               // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid;               // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data;                // jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready;               // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rdata_fifo:out_ready
	wire   [31:0] sysid_qsys_control_slave_agent_m0_readdata;                           // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
	wire          sysid_qsys_control_slave_agent_m0_waitrequest;                        // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
	wire          sysid_qsys_control_slave_agent_m0_debugaccess;                        // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
	wire   [31:0] sysid_qsys_control_slave_agent_m0_address;                            // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
	wire    [3:0] sysid_qsys_control_slave_agent_m0_byteenable;                         // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
	wire          sysid_qsys_control_slave_agent_m0_read;                               // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
	wire          sysid_qsys_control_slave_agent_m0_readdatavalid;                      // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
	wire          sysid_qsys_control_slave_agent_m0_lock;                               // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
	wire   [31:0] sysid_qsys_control_slave_agent_m0_writedata;                          // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
	wire          sysid_qsys_control_slave_agent_m0_write;                              // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
	wire    [2:0] sysid_qsys_control_slave_agent_m0_burstcount;                         // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
	wire          sysid_qsys_control_slave_agent_rf_source_valid;                       // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
	wire  [146:0] sysid_qsys_control_slave_agent_rf_source_data;                        // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
	wire          sysid_qsys_control_slave_agent_rf_source_ready;                       // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
	wire          sysid_qsys_control_slave_agent_rf_source_startofpacket;               // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
	wire          sysid_qsys_control_slave_agent_rf_source_endofpacket;                 // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_valid;                    // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
	wire  [146:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data;                     // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_ready;                    // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket;            // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
	wire          sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket;              // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
	wire          sysid_qsys_control_slave_agent_rdata_fifo_src_valid;                  // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent_rdata_fifo:in_valid
	wire   [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data;                   // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent_rdata_fifo:in_data
	wire          sysid_qsys_control_slave_agent_rdata_fifo_src_ready;                  // sysid_qsys_control_slave_agent_rdata_fifo:in_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
	wire          sysid_qsys_control_slave_agent_rdata_fifo_out_valid;                  // sysid_qsys_control_slave_agent_rdata_fifo:out_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] sysid_qsys_control_slave_agent_rdata_fifo_out_data;                   // sysid_qsys_control_slave_agent_rdata_fifo:out_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
	wire          sysid_qsys_control_slave_agent_rdata_fifo_out_ready;                  // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> sysid_qsys_control_slave_agent_rdata_fifo:out_ready
	wire   [31:0] intel_niosv_g_dm_agent_agent_m0_readdata;                             // intel_niosv_g_dm_agent_translator:uav_readdata -> intel_niosv_g_dm_agent_agent:m0_readdata
	wire          intel_niosv_g_dm_agent_agent_m0_waitrequest;                          // intel_niosv_g_dm_agent_translator:uav_waitrequest -> intel_niosv_g_dm_agent_agent:m0_waitrequest
	wire          intel_niosv_g_dm_agent_agent_m0_debugaccess;                          // intel_niosv_g_dm_agent_agent:m0_debugaccess -> intel_niosv_g_dm_agent_translator:uav_debugaccess
	wire   [31:0] intel_niosv_g_dm_agent_agent_m0_address;                              // intel_niosv_g_dm_agent_agent:m0_address -> intel_niosv_g_dm_agent_translator:uav_address
	wire    [3:0] intel_niosv_g_dm_agent_agent_m0_byteenable;                           // intel_niosv_g_dm_agent_agent:m0_byteenable -> intel_niosv_g_dm_agent_translator:uav_byteenable
	wire          intel_niosv_g_dm_agent_agent_m0_read;                                 // intel_niosv_g_dm_agent_agent:m0_read -> intel_niosv_g_dm_agent_translator:uav_read
	wire          intel_niosv_g_dm_agent_agent_m0_readdatavalid;                        // intel_niosv_g_dm_agent_translator:uav_readdatavalid -> intel_niosv_g_dm_agent_agent:m0_readdatavalid
	wire          intel_niosv_g_dm_agent_agent_m0_lock;                                 // intel_niosv_g_dm_agent_agent:m0_lock -> intel_niosv_g_dm_agent_translator:uav_lock
	wire   [31:0] intel_niosv_g_dm_agent_agent_m0_writedata;                            // intel_niosv_g_dm_agent_agent:m0_writedata -> intel_niosv_g_dm_agent_translator:uav_writedata
	wire          intel_niosv_g_dm_agent_agent_m0_write;                                // intel_niosv_g_dm_agent_agent:m0_write -> intel_niosv_g_dm_agent_translator:uav_write
	wire    [2:0] intel_niosv_g_dm_agent_agent_m0_burstcount;                           // intel_niosv_g_dm_agent_agent:m0_burstcount -> intel_niosv_g_dm_agent_translator:uav_burstcount
	wire          intel_niosv_g_dm_agent_agent_rf_source_valid;                         // intel_niosv_g_dm_agent_agent:rf_source_valid -> intel_niosv_g_dm_agent_agent_rsp_fifo:in_valid
	wire  [146:0] intel_niosv_g_dm_agent_agent_rf_source_data;                          // intel_niosv_g_dm_agent_agent:rf_source_data -> intel_niosv_g_dm_agent_agent_rsp_fifo:in_data
	wire          intel_niosv_g_dm_agent_agent_rf_source_ready;                         // intel_niosv_g_dm_agent_agent_rsp_fifo:in_ready -> intel_niosv_g_dm_agent_agent:rf_source_ready
	wire          intel_niosv_g_dm_agent_agent_rf_source_startofpacket;                 // intel_niosv_g_dm_agent_agent:rf_source_startofpacket -> intel_niosv_g_dm_agent_agent_rsp_fifo:in_startofpacket
	wire          intel_niosv_g_dm_agent_agent_rf_source_endofpacket;                   // intel_niosv_g_dm_agent_agent:rf_source_endofpacket -> intel_niosv_g_dm_agent_agent_rsp_fifo:in_endofpacket
	wire          intel_niosv_g_dm_agent_agent_rsp_fifo_out_valid;                      // intel_niosv_g_dm_agent_agent_rsp_fifo:out_valid -> intel_niosv_g_dm_agent_agent:rf_sink_valid
	wire  [146:0] intel_niosv_g_dm_agent_agent_rsp_fifo_out_data;                       // intel_niosv_g_dm_agent_agent_rsp_fifo:out_data -> intel_niosv_g_dm_agent_agent:rf_sink_data
	wire          intel_niosv_g_dm_agent_agent_rsp_fifo_out_ready;                      // intel_niosv_g_dm_agent_agent:rf_sink_ready -> intel_niosv_g_dm_agent_agent_rsp_fifo:out_ready
	wire          intel_niosv_g_dm_agent_agent_rsp_fifo_out_startofpacket;              // intel_niosv_g_dm_agent_agent_rsp_fifo:out_startofpacket -> intel_niosv_g_dm_agent_agent:rf_sink_startofpacket
	wire          intel_niosv_g_dm_agent_agent_rsp_fifo_out_endofpacket;                // intel_niosv_g_dm_agent_agent_rsp_fifo:out_endofpacket -> intel_niosv_g_dm_agent_agent:rf_sink_endofpacket
	wire          intel_niosv_g_dm_agent_agent_rdata_fifo_src_valid;                    // intel_niosv_g_dm_agent_agent:rdata_fifo_src_valid -> intel_niosv_g_dm_agent_agent_rdata_fifo:in_valid
	wire   [33:0] intel_niosv_g_dm_agent_agent_rdata_fifo_src_data;                     // intel_niosv_g_dm_agent_agent:rdata_fifo_src_data -> intel_niosv_g_dm_agent_agent_rdata_fifo:in_data
	wire          intel_niosv_g_dm_agent_agent_rdata_fifo_src_ready;                    // intel_niosv_g_dm_agent_agent_rdata_fifo:in_ready -> intel_niosv_g_dm_agent_agent:rdata_fifo_src_ready
	wire          intel_niosv_g_dm_agent_agent_rdata_fifo_out_valid;                    // intel_niosv_g_dm_agent_agent_rdata_fifo:out_valid -> intel_niosv_g_dm_agent_agent:rdata_fifo_sink_valid
	wire   [33:0] intel_niosv_g_dm_agent_agent_rdata_fifo_out_data;                     // intel_niosv_g_dm_agent_agent_rdata_fifo:out_data -> intel_niosv_g_dm_agent_agent:rdata_fifo_sink_data
	wire          intel_niosv_g_dm_agent_agent_rdata_fifo_out_ready;                    // intel_niosv_g_dm_agent_agent:rdata_fifo_sink_ready -> intel_niosv_g_dm_agent_agent_rdata_fifo:out_ready
	wire   [31:0] timer_s1_agent_m0_readdata;                                           // timer_s1_translator:uav_readdata -> timer_s1_agent:m0_readdata
	wire          timer_s1_agent_m0_waitrequest;                                        // timer_s1_translator:uav_waitrequest -> timer_s1_agent:m0_waitrequest
	wire          timer_s1_agent_m0_debugaccess;                                        // timer_s1_agent:m0_debugaccess -> timer_s1_translator:uav_debugaccess
	wire   [31:0] timer_s1_agent_m0_address;                                            // timer_s1_agent:m0_address -> timer_s1_translator:uav_address
	wire    [3:0] timer_s1_agent_m0_byteenable;                                         // timer_s1_agent:m0_byteenable -> timer_s1_translator:uav_byteenable
	wire          timer_s1_agent_m0_read;                                               // timer_s1_agent:m0_read -> timer_s1_translator:uav_read
	wire          timer_s1_agent_m0_readdatavalid;                                      // timer_s1_translator:uav_readdatavalid -> timer_s1_agent:m0_readdatavalid
	wire          timer_s1_agent_m0_lock;                                               // timer_s1_agent:m0_lock -> timer_s1_translator:uav_lock
	wire   [31:0] timer_s1_agent_m0_writedata;                                          // timer_s1_agent:m0_writedata -> timer_s1_translator:uav_writedata
	wire          timer_s1_agent_m0_write;                                              // timer_s1_agent:m0_write -> timer_s1_translator:uav_write
	wire    [2:0] timer_s1_agent_m0_burstcount;                                         // timer_s1_agent:m0_burstcount -> timer_s1_translator:uav_burstcount
	wire          timer_s1_agent_rf_source_valid;                                       // timer_s1_agent:rf_source_valid -> timer_s1_agent_rsp_fifo:in_valid
	wire  [146:0] timer_s1_agent_rf_source_data;                                        // timer_s1_agent:rf_source_data -> timer_s1_agent_rsp_fifo:in_data
	wire          timer_s1_agent_rf_source_ready;                                       // timer_s1_agent_rsp_fifo:in_ready -> timer_s1_agent:rf_source_ready
	wire          timer_s1_agent_rf_source_startofpacket;                               // timer_s1_agent:rf_source_startofpacket -> timer_s1_agent_rsp_fifo:in_startofpacket
	wire          timer_s1_agent_rf_source_endofpacket;                                 // timer_s1_agent:rf_source_endofpacket -> timer_s1_agent_rsp_fifo:in_endofpacket
	wire          timer_s1_agent_rsp_fifo_out_valid;                                    // timer_s1_agent_rsp_fifo:out_valid -> timer_s1_agent:rf_sink_valid
	wire  [146:0] timer_s1_agent_rsp_fifo_out_data;                                     // timer_s1_agent_rsp_fifo:out_data -> timer_s1_agent:rf_sink_data
	wire          timer_s1_agent_rsp_fifo_out_ready;                                    // timer_s1_agent:rf_sink_ready -> timer_s1_agent_rsp_fifo:out_ready
	wire          timer_s1_agent_rsp_fifo_out_startofpacket;                            // timer_s1_agent_rsp_fifo:out_startofpacket -> timer_s1_agent:rf_sink_startofpacket
	wire          timer_s1_agent_rsp_fifo_out_endofpacket;                              // timer_s1_agent_rsp_fifo:out_endofpacket -> timer_s1_agent:rf_sink_endofpacket
	wire          timer_s1_agent_rdata_fifo_src_valid;                                  // timer_s1_agent:rdata_fifo_src_valid -> timer_s1_agent_rdata_fifo:in_valid
	wire   [33:0] timer_s1_agent_rdata_fifo_src_data;                                   // timer_s1_agent:rdata_fifo_src_data -> timer_s1_agent_rdata_fifo:in_data
	wire          timer_s1_agent_rdata_fifo_src_ready;                                  // timer_s1_agent_rdata_fifo:in_ready -> timer_s1_agent:rdata_fifo_src_ready
	wire          timer_s1_agent_rdata_fifo_out_valid;                                  // timer_s1_agent_rdata_fifo:out_valid -> timer_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] timer_s1_agent_rdata_fifo_out_data;                                   // timer_s1_agent_rdata_fifo:out_data -> timer_s1_agent:rdata_fifo_sink_data
	wire          timer_s1_agent_rdata_fifo_out_ready;                                  // timer_s1_agent:rdata_fifo_sink_ready -> timer_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_power_in_voltage_s1_agent_m0_readdata;                     // board_info_power_in_voltage_s1_translator:uav_readdata -> board_info_power_in_voltage_s1_agent:m0_readdata
	wire          board_info_power_in_voltage_s1_agent_m0_waitrequest;                  // board_info_power_in_voltage_s1_translator:uav_waitrequest -> board_info_power_in_voltage_s1_agent:m0_waitrequest
	wire          board_info_power_in_voltage_s1_agent_m0_debugaccess;                  // board_info_power_in_voltage_s1_agent:m0_debugaccess -> board_info_power_in_voltage_s1_translator:uav_debugaccess
	wire   [31:0] board_info_power_in_voltage_s1_agent_m0_address;                      // board_info_power_in_voltage_s1_agent:m0_address -> board_info_power_in_voltage_s1_translator:uav_address
	wire    [3:0] board_info_power_in_voltage_s1_agent_m0_byteenable;                   // board_info_power_in_voltage_s1_agent:m0_byteenable -> board_info_power_in_voltage_s1_translator:uav_byteenable
	wire          board_info_power_in_voltage_s1_agent_m0_read;                         // board_info_power_in_voltage_s1_agent:m0_read -> board_info_power_in_voltage_s1_translator:uav_read
	wire          board_info_power_in_voltage_s1_agent_m0_readdatavalid;                // board_info_power_in_voltage_s1_translator:uav_readdatavalid -> board_info_power_in_voltage_s1_agent:m0_readdatavalid
	wire          board_info_power_in_voltage_s1_agent_m0_lock;                         // board_info_power_in_voltage_s1_agent:m0_lock -> board_info_power_in_voltage_s1_translator:uav_lock
	wire   [31:0] board_info_power_in_voltage_s1_agent_m0_writedata;                    // board_info_power_in_voltage_s1_agent:m0_writedata -> board_info_power_in_voltage_s1_translator:uav_writedata
	wire          board_info_power_in_voltage_s1_agent_m0_write;                        // board_info_power_in_voltage_s1_agent:m0_write -> board_info_power_in_voltage_s1_translator:uav_write
	wire    [2:0] board_info_power_in_voltage_s1_agent_m0_burstcount;                   // board_info_power_in_voltage_s1_agent:m0_burstcount -> board_info_power_in_voltage_s1_translator:uav_burstcount
	wire          board_info_power_in_voltage_s1_agent_rf_source_valid;                 // board_info_power_in_voltage_s1_agent:rf_source_valid -> board_info_power_in_voltage_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_power_in_voltage_s1_agent_rf_source_data;                  // board_info_power_in_voltage_s1_agent:rf_source_data -> board_info_power_in_voltage_s1_agent_rsp_fifo:in_data
	wire          board_info_power_in_voltage_s1_agent_rf_source_ready;                 // board_info_power_in_voltage_s1_agent_rsp_fifo:in_ready -> board_info_power_in_voltage_s1_agent:rf_source_ready
	wire          board_info_power_in_voltage_s1_agent_rf_source_startofpacket;         // board_info_power_in_voltage_s1_agent:rf_source_startofpacket -> board_info_power_in_voltage_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_power_in_voltage_s1_agent_rf_source_endofpacket;           // board_info_power_in_voltage_s1_agent:rf_source_endofpacket -> board_info_power_in_voltage_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_power_in_voltage_s1_agent_rsp_fifo_out_valid;              // board_info_power_in_voltage_s1_agent_rsp_fifo:out_valid -> board_info_power_in_voltage_s1_agent:rf_sink_valid
	wire  [146:0] board_info_power_in_voltage_s1_agent_rsp_fifo_out_data;               // board_info_power_in_voltage_s1_agent_rsp_fifo:out_data -> board_info_power_in_voltage_s1_agent:rf_sink_data
	wire          board_info_power_in_voltage_s1_agent_rsp_fifo_out_ready;              // board_info_power_in_voltage_s1_agent:rf_sink_ready -> board_info_power_in_voltage_s1_agent_rsp_fifo:out_ready
	wire          board_info_power_in_voltage_s1_agent_rsp_fifo_out_startofpacket;      // board_info_power_in_voltage_s1_agent_rsp_fifo:out_startofpacket -> board_info_power_in_voltage_s1_agent:rf_sink_startofpacket
	wire          board_info_power_in_voltage_s1_agent_rsp_fifo_out_endofpacket;        // board_info_power_in_voltage_s1_agent_rsp_fifo:out_endofpacket -> board_info_power_in_voltage_s1_agent:rf_sink_endofpacket
	wire          board_info_power_in_voltage_s1_agent_rdata_fifo_src_valid;            // board_info_power_in_voltage_s1_agent:rdata_fifo_src_valid -> board_info_power_in_voltage_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_power_in_voltage_s1_agent_rdata_fifo_src_data;             // board_info_power_in_voltage_s1_agent:rdata_fifo_src_data -> board_info_power_in_voltage_s1_agent_rdata_fifo:in_data
	wire          board_info_power_in_voltage_s1_agent_rdata_fifo_src_ready;            // board_info_power_in_voltage_s1_agent_rdata_fifo:in_ready -> board_info_power_in_voltage_s1_agent:rdata_fifo_src_ready
	wire          board_info_power_in_voltage_s1_agent_rdata_fifo_out_valid;            // board_info_power_in_voltage_s1_agent_rdata_fifo:out_valid -> board_info_power_in_voltage_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_power_in_voltage_s1_agent_rdata_fifo_out_data;             // board_info_power_in_voltage_s1_agent_rdata_fifo:out_data -> board_info_power_in_voltage_s1_agent:rdata_fifo_sink_data
	wire          board_info_power_in_voltage_s1_agent_rdata_fifo_out_ready;            // board_info_power_in_voltage_s1_agent:rdata_fifo_sink_ready -> board_info_power_in_voltage_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_vcc1p2_voltage_s1_agent_m0_readdata;                       // board_info_vcc1p2_voltage_s1_translator:uav_readdata -> board_info_vcc1p2_voltage_s1_agent:m0_readdata
	wire          board_info_vcc1p2_voltage_s1_agent_m0_waitrequest;                    // board_info_vcc1p2_voltage_s1_translator:uav_waitrequest -> board_info_vcc1p2_voltage_s1_agent:m0_waitrequest
	wire          board_info_vcc1p2_voltage_s1_agent_m0_debugaccess;                    // board_info_vcc1p2_voltage_s1_agent:m0_debugaccess -> board_info_vcc1p2_voltage_s1_translator:uav_debugaccess
	wire   [31:0] board_info_vcc1p2_voltage_s1_agent_m0_address;                        // board_info_vcc1p2_voltage_s1_agent:m0_address -> board_info_vcc1p2_voltage_s1_translator:uav_address
	wire    [3:0] board_info_vcc1p2_voltage_s1_agent_m0_byteenable;                     // board_info_vcc1p2_voltage_s1_agent:m0_byteenable -> board_info_vcc1p2_voltage_s1_translator:uav_byteenable
	wire          board_info_vcc1p2_voltage_s1_agent_m0_read;                           // board_info_vcc1p2_voltage_s1_agent:m0_read -> board_info_vcc1p2_voltage_s1_translator:uav_read
	wire          board_info_vcc1p2_voltage_s1_agent_m0_readdatavalid;                  // board_info_vcc1p2_voltage_s1_translator:uav_readdatavalid -> board_info_vcc1p2_voltage_s1_agent:m0_readdatavalid
	wire          board_info_vcc1p2_voltage_s1_agent_m0_lock;                           // board_info_vcc1p2_voltage_s1_agent:m0_lock -> board_info_vcc1p2_voltage_s1_translator:uav_lock
	wire   [31:0] board_info_vcc1p2_voltage_s1_agent_m0_writedata;                      // board_info_vcc1p2_voltage_s1_agent:m0_writedata -> board_info_vcc1p2_voltage_s1_translator:uav_writedata
	wire          board_info_vcc1p2_voltage_s1_agent_m0_write;                          // board_info_vcc1p2_voltage_s1_agent:m0_write -> board_info_vcc1p2_voltage_s1_translator:uav_write
	wire    [2:0] board_info_vcc1p2_voltage_s1_agent_m0_burstcount;                     // board_info_vcc1p2_voltage_s1_agent:m0_burstcount -> board_info_vcc1p2_voltage_s1_translator:uav_burstcount
	wire          board_info_vcc1p2_voltage_s1_agent_rf_source_valid;                   // board_info_vcc1p2_voltage_s1_agent:rf_source_valid -> board_info_vcc1p2_voltage_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_vcc1p2_voltage_s1_agent_rf_source_data;                    // board_info_vcc1p2_voltage_s1_agent:rf_source_data -> board_info_vcc1p2_voltage_s1_agent_rsp_fifo:in_data
	wire          board_info_vcc1p2_voltage_s1_agent_rf_source_ready;                   // board_info_vcc1p2_voltage_s1_agent_rsp_fifo:in_ready -> board_info_vcc1p2_voltage_s1_agent:rf_source_ready
	wire          board_info_vcc1p2_voltage_s1_agent_rf_source_startofpacket;           // board_info_vcc1p2_voltage_s1_agent:rf_source_startofpacket -> board_info_vcc1p2_voltage_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_vcc1p2_voltage_s1_agent_rf_source_endofpacket;             // board_info_vcc1p2_voltage_s1_agent:rf_source_endofpacket -> board_info_vcc1p2_voltage_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_valid;                // board_info_vcc1p2_voltage_s1_agent_rsp_fifo:out_valid -> board_info_vcc1p2_voltage_s1_agent:rf_sink_valid
	wire  [146:0] board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_data;                 // board_info_vcc1p2_voltage_s1_agent_rsp_fifo:out_data -> board_info_vcc1p2_voltage_s1_agent:rf_sink_data
	wire          board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_ready;                // board_info_vcc1p2_voltage_s1_agent:rf_sink_ready -> board_info_vcc1p2_voltage_s1_agent_rsp_fifo:out_ready
	wire          board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_startofpacket;        // board_info_vcc1p2_voltage_s1_agent_rsp_fifo:out_startofpacket -> board_info_vcc1p2_voltage_s1_agent:rf_sink_startofpacket
	wire          board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_endofpacket;          // board_info_vcc1p2_voltage_s1_agent_rsp_fifo:out_endofpacket -> board_info_vcc1p2_voltage_s1_agent:rf_sink_endofpacket
	wire          board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_valid;              // board_info_vcc1p2_voltage_s1_agent:rdata_fifo_src_valid -> board_info_vcc1p2_voltage_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_data;               // board_info_vcc1p2_voltage_s1_agent:rdata_fifo_src_data -> board_info_vcc1p2_voltage_s1_agent_rdata_fifo:in_data
	wire          board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_ready;              // board_info_vcc1p2_voltage_s1_agent_rdata_fifo:in_ready -> board_info_vcc1p2_voltage_s1_agent:rdata_fifo_src_ready
	wire          board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_valid;              // board_info_vcc1p2_voltage_s1_agent_rdata_fifo:out_valid -> board_info_vcc1p2_voltage_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_data;               // board_info_vcc1p2_voltage_s1_agent_rdata_fifo:out_data -> board_info_vcc1p2_voltage_s1_agent:rdata_fifo_sink_data
	wire          board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_ready;              // board_info_vcc1p2_voltage_s1_agent:rdata_fifo_sink_ready -> board_info_vcc1p2_voltage_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_vcc1p2_current_s1_agent_m0_readdata;                       // board_info_vcc1p2_current_s1_translator:uav_readdata -> board_info_vcc1p2_current_s1_agent:m0_readdata
	wire          board_info_vcc1p2_current_s1_agent_m0_waitrequest;                    // board_info_vcc1p2_current_s1_translator:uav_waitrequest -> board_info_vcc1p2_current_s1_agent:m0_waitrequest
	wire          board_info_vcc1p2_current_s1_agent_m0_debugaccess;                    // board_info_vcc1p2_current_s1_agent:m0_debugaccess -> board_info_vcc1p2_current_s1_translator:uav_debugaccess
	wire   [31:0] board_info_vcc1p2_current_s1_agent_m0_address;                        // board_info_vcc1p2_current_s1_agent:m0_address -> board_info_vcc1p2_current_s1_translator:uav_address
	wire    [3:0] board_info_vcc1p2_current_s1_agent_m0_byteenable;                     // board_info_vcc1p2_current_s1_agent:m0_byteenable -> board_info_vcc1p2_current_s1_translator:uav_byteenable
	wire          board_info_vcc1p2_current_s1_agent_m0_read;                           // board_info_vcc1p2_current_s1_agent:m0_read -> board_info_vcc1p2_current_s1_translator:uav_read
	wire          board_info_vcc1p2_current_s1_agent_m0_readdatavalid;                  // board_info_vcc1p2_current_s1_translator:uav_readdatavalid -> board_info_vcc1p2_current_s1_agent:m0_readdatavalid
	wire          board_info_vcc1p2_current_s1_agent_m0_lock;                           // board_info_vcc1p2_current_s1_agent:m0_lock -> board_info_vcc1p2_current_s1_translator:uav_lock
	wire   [31:0] board_info_vcc1p2_current_s1_agent_m0_writedata;                      // board_info_vcc1p2_current_s1_agent:m0_writedata -> board_info_vcc1p2_current_s1_translator:uav_writedata
	wire          board_info_vcc1p2_current_s1_agent_m0_write;                          // board_info_vcc1p2_current_s1_agent:m0_write -> board_info_vcc1p2_current_s1_translator:uav_write
	wire    [2:0] board_info_vcc1p2_current_s1_agent_m0_burstcount;                     // board_info_vcc1p2_current_s1_agent:m0_burstcount -> board_info_vcc1p2_current_s1_translator:uav_burstcount
	wire          board_info_vcc1p2_current_s1_agent_rf_source_valid;                   // board_info_vcc1p2_current_s1_agent:rf_source_valid -> board_info_vcc1p2_current_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_vcc1p2_current_s1_agent_rf_source_data;                    // board_info_vcc1p2_current_s1_agent:rf_source_data -> board_info_vcc1p2_current_s1_agent_rsp_fifo:in_data
	wire          board_info_vcc1p2_current_s1_agent_rf_source_ready;                   // board_info_vcc1p2_current_s1_agent_rsp_fifo:in_ready -> board_info_vcc1p2_current_s1_agent:rf_source_ready
	wire          board_info_vcc1p2_current_s1_agent_rf_source_startofpacket;           // board_info_vcc1p2_current_s1_agent:rf_source_startofpacket -> board_info_vcc1p2_current_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_vcc1p2_current_s1_agent_rf_source_endofpacket;             // board_info_vcc1p2_current_s1_agent:rf_source_endofpacket -> board_info_vcc1p2_current_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_vcc1p2_current_s1_agent_rsp_fifo_out_valid;                // board_info_vcc1p2_current_s1_agent_rsp_fifo:out_valid -> board_info_vcc1p2_current_s1_agent:rf_sink_valid
	wire  [146:0] board_info_vcc1p2_current_s1_agent_rsp_fifo_out_data;                 // board_info_vcc1p2_current_s1_agent_rsp_fifo:out_data -> board_info_vcc1p2_current_s1_agent:rf_sink_data
	wire          board_info_vcc1p2_current_s1_agent_rsp_fifo_out_ready;                // board_info_vcc1p2_current_s1_agent:rf_sink_ready -> board_info_vcc1p2_current_s1_agent_rsp_fifo:out_ready
	wire          board_info_vcc1p2_current_s1_agent_rsp_fifo_out_startofpacket;        // board_info_vcc1p2_current_s1_agent_rsp_fifo:out_startofpacket -> board_info_vcc1p2_current_s1_agent:rf_sink_startofpacket
	wire          board_info_vcc1p2_current_s1_agent_rsp_fifo_out_endofpacket;          // board_info_vcc1p2_current_s1_agent_rsp_fifo:out_endofpacket -> board_info_vcc1p2_current_s1_agent:rf_sink_endofpacket
	wire          board_info_vcc1p2_current_s1_agent_rdata_fifo_src_valid;              // board_info_vcc1p2_current_s1_agent:rdata_fifo_src_valid -> board_info_vcc1p2_current_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_vcc1p2_current_s1_agent_rdata_fifo_src_data;               // board_info_vcc1p2_current_s1_agent:rdata_fifo_src_data -> board_info_vcc1p2_current_s1_agent_rdata_fifo:in_data
	wire          board_info_vcc1p2_current_s1_agent_rdata_fifo_src_ready;              // board_info_vcc1p2_current_s1_agent_rdata_fifo:in_ready -> board_info_vcc1p2_current_s1_agent:rdata_fifo_src_ready
	wire          board_info_vcc1p2_current_s1_agent_rdata_fifo_out_valid;              // board_info_vcc1p2_current_s1_agent_rdata_fifo:out_valid -> board_info_vcc1p2_current_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_vcc1p2_current_s1_agent_rdata_fifo_out_data;               // board_info_vcc1p2_current_s1_agent_rdata_fifo:out_data -> board_info_vcc1p2_current_s1_agent:rdata_fifo_sink_data
	wire          board_info_vcc1p2_current_s1_agent_rdata_fifo_out_ready;              // board_info_vcc1p2_current_s1_agent:rdata_fifo_sink_ready -> board_info_vcc1p2_current_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_fan_speed_s1_agent_m0_readdata;                            // board_info_fan_speed_s1_translator:uav_readdata -> board_info_fan_speed_s1_agent:m0_readdata
	wire          board_info_fan_speed_s1_agent_m0_waitrequest;                         // board_info_fan_speed_s1_translator:uav_waitrequest -> board_info_fan_speed_s1_agent:m0_waitrequest
	wire          board_info_fan_speed_s1_agent_m0_debugaccess;                         // board_info_fan_speed_s1_agent:m0_debugaccess -> board_info_fan_speed_s1_translator:uav_debugaccess
	wire   [31:0] board_info_fan_speed_s1_agent_m0_address;                             // board_info_fan_speed_s1_agent:m0_address -> board_info_fan_speed_s1_translator:uav_address
	wire    [3:0] board_info_fan_speed_s1_agent_m0_byteenable;                          // board_info_fan_speed_s1_agent:m0_byteenable -> board_info_fan_speed_s1_translator:uav_byteenable
	wire          board_info_fan_speed_s1_agent_m0_read;                                // board_info_fan_speed_s1_agent:m0_read -> board_info_fan_speed_s1_translator:uav_read
	wire          board_info_fan_speed_s1_agent_m0_readdatavalid;                       // board_info_fan_speed_s1_translator:uav_readdatavalid -> board_info_fan_speed_s1_agent:m0_readdatavalid
	wire          board_info_fan_speed_s1_agent_m0_lock;                                // board_info_fan_speed_s1_agent:m0_lock -> board_info_fan_speed_s1_translator:uav_lock
	wire   [31:0] board_info_fan_speed_s1_agent_m0_writedata;                           // board_info_fan_speed_s1_agent:m0_writedata -> board_info_fan_speed_s1_translator:uav_writedata
	wire          board_info_fan_speed_s1_agent_m0_write;                               // board_info_fan_speed_s1_agent:m0_write -> board_info_fan_speed_s1_translator:uav_write
	wire    [2:0] board_info_fan_speed_s1_agent_m0_burstcount;                          // board_info_fan_speed_s1_agent:m0_burstcount -> board_info_fan_speed_s1_translator:uav_burstcount
	wire          board_info_fan_speed_s1_agent_rf_source_valid;                        // board_info_fan_speed_s1_agent:rf_source_valid -> board_info_fan_speed_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_fan_speed_s1_agent_rf_source_data;                         // board_info_fan_speed_s1_agent:rf_source_data -> board_info_fan_speed_s1_agent_rsp_fifo:in_data
	wire          board_info_fan_speed_s1_agent_rf_source_ready;                        // board_info_fan_speed_s1_agent_rsp_fifo:in_ready -> board_info_fan_speed_s1_agent:rf_source_ready
	wire          board_info_fan_speed_s1_agent_rf_source_startofpacket;                // board_info_fan_speed_s1_agent:rf_source_startofpacket -> board_info_fan_speed_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_fan_speed_s1_agent_rf_source_endofpacket;                  // board_info_fan_speed_s1_agent:rf_source_endofpacket -> board_info_fan_speed_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_fan_speed_s1_agent_rsp_fifo_out_valid;                     // board_info_fan_speed_s1_agent_rsp_fifo:out_valid -> board_info_fan_speed_s1_agent:rf_sink_valid
	wire  [146:0] board_info_fan_speed_s1_agent_rsp_fifo_out_data;                      // board_info_fan_speed_s1_agent_rsp_fifo:out_data -> board_info_fan_speed_s1_agent:rf_sink_data
	wire          board_info_fan_speed_s1_agent_rsp_fifo_out_ready;                     // board_info_fan_speed_s1_agent:rf_sink_ready -> board_info_fan_speed_s1_agent_rsp_fifo:out_ready
	wire          board_info_fan_speed_s1_agent_rsp_fifo_out_startofpacket;             // board_info_fan_speed_s1_agent_rsp_fifo:out_startofpacket -> board_info_fan_speed_s1_agent:rf_sink_startofpacket
	wire          board_info_fan_speed_s1_agent_rsp_fifo_out_endofpacket;               // board_info_fan_speed_s1_agent_rsp_fifo:out_endofpacket -> board_info_fan_speed_s1_agent:rf_sink_endofpacket
	wire          board_info_fan_speed_s1_agent_rdata_fifo_src_valid;                   // board_info_fan_speed_s1_agent:rdata_fifo_src_valid -> board_info_fan_speed_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_fan_speed_s1_agent_rdata_fifo_src_data;                    // board_info_fan_speed_s1_agent:rdata_fifo_src_data -> board_info_fan_speed_s1_agent_rdata_fifo:in_data
	wire          board_info_fan_speed_s1_agent_rdata_fifo_src_ready;                   // board_info_fan_speed_s1_agent_rdata_fifo:in_ready -> board_info_fan_speed_s1_agent:rdata_fifo_src_ready
	wire          board_info_fan_speed_s1_agent_rdata_fifo_out_valid;                   // board_info_fan_speed_s1_agent_rdata_fifo:out_valid -> board_info_fan_speed_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_fan_speed_s1_agent_rdata_fifo_out_data;                    // board_info_fan_speed_s1_agent_rdata_fifo:out_data -> board_info_fan_speed_s1_agent:rdata_fifo_sink_data
	wire          board_info_fan_speed_s1_agent_rdata_fifo_out_ready;                   // board_info_fan_speed_s1_agent:rdata_fifo_sink_ready -> board_info_fan_speed_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_temperature_fpga_s1_agent_m0_readdata;                     // board_info_temperature_fpga_s1_translator:uav_readdata -> board_info_temperature_fpga_s1_agent:m0_readdata
	wire          board_info_temperature_fpga_s1_agent_m0_waitrequest;                  // board_info_temperature_fpga_s1_translator:uav_waitrequest -> board_info_temperature_fpga_s1_agent:m0_waitrequest
	wire          board_info_temperature_fpga_s1_agent_m0_debugaccess;                  // board_info_temperature_fpga_s1_agent:m0_debugaccess -> board_info_temperature_fpga_s1_translator:uav_debugaccess
	wire   [31:0] board_info_temperature_fpga_s1_agent_m0_address;                      // board_info_temperature_fpga_s1_agent:m0_address -> board_info_temperature_fpga_s1_translator:uav_address
	wire    [3:0] board_info_temperature_fpga_s1_agent_m0_byteenable;                   // board_info_temperature_fpga_s1_agent:m0_byteenable -> board_info_temperature_fpga_s1_translator:uav_byteenable
	wire          board_info_temperature_fpga_s1_agent_m0_read;                         // board_info_temperature_fpga_s1_agent:m0_read -> board_info_temperature_fpga_s1_translator:uav_read
	wire          board_info_temperature_fpga_s1_agent_m0_readdatavalid;                // board_info_temperature_fpga_s1_translator:uav_readdatavalid -> board_info_temperature_fpga_s1_agent:m0_readdatavalid
	wire          board_info_temperature_fpga_s1_agent_m0_lock;                         // board_info_temperature_fpga_s1_agent:m0_lock -> board_info_temperature_fpga_s1_translator:uav_lock
	wire   [31:0] board_info_temperature_fpga_s1_agent_m0_writedata;                    // board_info_temperature_fpga_s1_agent:m0_writedata -> board_info_temperature_fpga_s1_translator:uav_writedata
	wire          board_info_temperature_fpga_s1_agent_m0_write;                        // board_info_temperature_fpga_s1_agent:m0_write -> board_info_temperature_fpga_s1_translator:uav_write
	wire    [2:0] board_info_temperature_fpga_s1_agent_m0_burstcount;                   // board_info_temperature_fpga_s1_agent:m0_burstcount -> board_info_temperature_fpga_s1_translator:uav_burstcount
	wire          board_info_temperature_fpga_s1_agent_rf_source_valid;                 // board_info_temperature_fpga_s1_agent:rf_source_valid -> board_info_temperature_fpga_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_temperature_fpga_s1_agent_rf_source_data;                  // board_info_temperature_fpga_s1_agent:rf_source_data -> board_info_temperature_fpga_s1_agent_rsp_fifo:in_data
	wire          board_info_temperature_fpga_s1_agent_rf_source_ready;                 // board_info_temperature_fpga_s1_agent_rsp_fifo:in_ready -> board_info_temperature_fpga_s1_agent:rf_source_ready
	wire          board_info_temperature_fpga_s1_agent_rf_source_startofpacket;         // board_info_temperature_fpga_s1_agent:rf_source_startofpacket -> board_info_temperature_fpga_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_temperature_fpga_s1_agent_rf_source_endofpacket;           // board_info_temperature_fpga_s1_agent:rf_source_endofpacket -> board_info_temperature_fpga_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_temperature_fpga_s1_agent_rsp_fifo_out_valid;              // board_info_temperature_fpga_s1_agent_rsp_fifo:out_valid -> board_info_temperature_fpga_s1_agent:rf_sink_valid
	wire  [146:0] board_info_temperature_fpga_s1_agent_rsp_fifo_out_data;               // board_info_temperature_fpga_s1_agent_rsp_fifo:out_data -> board_info_temperature_fpga_s1_agent:rf_sink_data
	wire          board_info_temperature_fpga_s1_agent_rsp_fifo_out_ready;              // board_info_temperature_fpga_s1_agent:rf_sink_ready -> board_info_temperature_fpga_s1_agent_rsp_fifo:out_ready
	wire          board_info_temperature_fpga_s1_agent_rsp_fifo_out_startofpacket;      // board_info_temperature_fpga_s1_agent_rsp_fifo:out_startofpacket -> board_info_temperature_fpga_s1_agent:rf_sink_startofpacket
	wire          board_info_temperature_fpga_s1_agent_rsp_fifo_out_endofpacket;        // board_info_temperature_fpga_s1_agent_rsp_fifo:out_endofpacket -> board_info_temperature_fpga_s1_agent:rf_sink_endofpacket
	wire          board_info_temperature_fpga_s1_agent_rdata_fifo_src_valid;            // board_info_temperature_fpga_s1_agent:rdata_fifo_src_valid -> board_info_temperature_fpga_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_temperature_fpga_s1_agent_rdata_fifo_src_data;             // board_info_temperature_fpga_s1_agent:rdata_fifo_src_data -> board_info_temperature_fpga_s1_agent_rdata_fifo:in_data
	wire          board_info_temperature_fpga_s1_agent_rdata_fifo_src_ready;            // board_info_temperature_fpga_s1_agent_rdata_fifo:in_ready -> board_info_temperature_fpga_s1_agent:rdata_fifo_src_ready
	wire          board_info_temperature_fpga_s1_agent_rdata_fifo_out_valid;            // board_info_temperature_fpga_s1_agent_rdata_fifo:out_valid -> board_info_temperature_fpga_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_temperature_fpga_s1_agent_rdata_fifo_out_data;             // board_info_temperature_fpga_s1_agent_rdata_fifo:out_data -> board_info_temperature_fpga_s1_agent:rdata_fifo_sink_data
	wire          board_info_temperature_fpga_s1_agent_rdata_fifo_out_ready;            // board_info_temperature_fpga_s1_agent:rdata_fifo_sink_ready -> board_info_temperature_fpga_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_temperature_board1_s1_agent_m0_readdata;                   // board_info_temperature_board1_s1_translator:uav_readdata -> board_info_temperature_board1_s1_agent:m0_readdata
	wire          board_info_temperature_board1_s1_agent_m0_waitrequest;                // board_info_temperature_board1_s1_translator:uav_waitrequest -> board_info_temperature_board1_s1_agent:m0_waitrequest
	wire          board_info_temperature_board1_s1_agent_m0_debugaccess;                // board_info_temperature_board1_s1_agent:m0_debugaccess -> board_info_temperature_board1_s1_translator:uav_debugaccess
	wire   [31:0] board_info_temperature_board1_s1_agent_m0_address;                    // board_info_temperature_board1_s1_agent:m0_address -> board_info_temperature_board1_s1_translator:uav_address
	wire    [3:0] board_info_temperature_board1_s1_agent_m0_byteenable;                 // board_info_temperature_board1_s1_agent:m0_byteenable -> board_info_temperature_board1_s1_translator:uav_byteenable
	wire          board_info_temperature_board1_s1_agent_m0_read;                       // board_info_temperature_board1_s1_agent:m0_read -> board_info_temperature_board1_s1_translator:uav_read
	wire          board_info_temperature_board1_s1_agent_m0_readdatavalid;              // board_info_temperature_board1_s1_translator:uav_readdatavalid -> board_info_temperature_board1_s1_agent:m0_readdatavalid
	wire          board_info_temperature_board1_s1_agent_m0_lock;                       // board_info_temperature_board1_s1_agent:m0_lock -> board_info_temperature_board1_s1_translator:uav_lock
	wire   [31:0] board_info_temperature_board1_s1_agent_m0_writedata;                  // board_info_temperature_board1_s1_agent:m0_writedata -> board_info_temperature_board1_s1_translator:uav_writedata
	wire          board_info_temperature_board1_s1_agent_m0_write;                      // board_info_temperature_board1_s1_agent:m0_write -> board_info_temperature_board1_s1_translator:uav_write
	wire    [2:0] board_info_temperature_board1_s1_agent_m0_burstcount;                 // board_info_temperature_board1_s1_agent:m0_burstcount -> board_info_temperature_board1_s1_translator:uav_burstcount
	wire          board_info_temperature_board1_s1_agent_rf_source_valid;               // board_info_temperature_board1_s1_agent:rf_source_valid -> board_info_temperature_board1_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_temperature_board1_s1_agent_rf_source_data;                // board_info_temperature_board1_s1_agent:rf_source_data -> board_info_temperature_board1_s1_agent_rsp_fifo:in_data
	wire          board_info_temperature_board1_s1_agent_rf_source_ready;               // board_info_temperature_board1_s1_agent_rsp_fifo:in_ready -> board_info_temperature_board1_s1_agent:rf_source_ready
	wire          board_info_temperature_board1_s1_agent_rf_source_startofpacket;       // board_info_temperature_board1_s1_agent:rf_source_startofpacket -> board_info_temperature_board1_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_temperature_board1_s1_agent_rf_source_endofpacket;         // board_info_temperature_board1_s1_agent:rf_source_endofpacket -> board_info_temperature_board1_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_temperature_board1_s1_agent_rsp_fifo_out_valid;            // board_info_temperature_board1_s1_agent_rsp_fifo:out_valid -> board_info_temperature_board1_s1_agent:rf_sink_valid
	wire  [146:0] board_info_temperature_board1_s1_agent_rsp_fifo_out_data;             // board_info_temperature_board1_s1_agent_rsp_fifo:out_data -> board_info_temperature_board1_s1_agent:rf_sink_data
	wire          board_info_temperature_board1_s1_agent_rsp_fifo_out_ready;            // board_info_temperature_board1_s1_agent:rf_sink_ready -> board_info_temperature_board1_s1_agent_rsp_fifo:out_ready
	wire          board_info_temperature_board1_s1_agent_rsp_fifo_out_startofpacket;    // board_info_temperature_board1_s1_agent_rsp_fifo:out_startofpacket -> board_info_temperature_board1_s1_agent:rf_sink_startofpacket
	wire          board_info_temperature_board1_s1_agent_rsp_fifo_out_endofpacket;      // board_info_temperature_board1_s1_agent_rsp_fifo:out_endofpacket -> board_info_temperature_board1_s1_agent:rf_sink_endofpacket
	wire          board_info_temperature_board1_s1_agent_rdata_fifo_src_valid;          // board_info_temperature_board1_s1_agent:rdata_fifo_src_valid -> board_info_temperature_board1_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_temperature_board1_s1_agent_rdata_fifo_src_data;           // board_info_temperature_board1_s1_agent:rdata_fifo_src_data -> board_info_temperature_board1_s1_agent_rdata_fifo:in_data
	wire          board_info_temperature_board1_s1_agent_rdata_fifo_src_ready;          // board_info_temperature_board1_s1_agent_rdata_fifo:in_ready -> board_info_temperature_board1_s1_agent:rdata_fifo_src_ready
	wire          board_info_temperature_board1_s1_agent_rdata_fifo_out_valid;          // board_info_temperature_board1_s1_agent_rdata_fifo:out_valid -> board_info_temperature_board1_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_temperature_board1_s1_agent_rdata_fifo_out_data;           // board_info_temperature_board1_s1_agent_rdata_fifo:out_data -> board_info_temperature_board1_s1_agent:rdata_fifo_sink_data
	wire          board_info_temperature_board1_s1_agent_rdata_fifo_out_ready;          // board_info_temperature_board1_s1_agent:rdata_fifo_sink_ready -> board_info_temperature_board1_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_pin_status_s1_agent_m0_readdata;                           // board_info_pin_status_s1_translator:uav_readdata -> board_info_pin_status_s1_agent:m0_readdata
	wire          board_info_pin_status_s1_agent_m0_waitrequest;                        // board_info_pin_status_s1_translator:uav_waitrequest -> board_info_pin_status_s1_agent:m0_waitrequest
	wire          board_info_pin_status_s1_agent_m0_debugaccess;                        // board_info_pin_status_s1_agent:m0_debugaccess -> board_info_pin_status_s1_translator:uav_debugaccess
	wire   [31:0] board_info_pin_status_s1_agent_m0_address;                            // board_info_pin_status_s1_agent:m0_address -> board_info_pin_status_s1_translator:uav_address
	wire    [3:0] board_info_pin_status_s1_agent_m0_byteenable;                         // board_info_pin_status_s1_agent:m0_byteenable -> board_info_pin_status_s1_translator:uav_byteenable
	wire          board_info_pin_status_s1_agent_m0_read;                               // board_info_pin_status_s1_agent:m0_read -> board_info_pin_status_s1_translator:uav_read
	wire          board_info_pin_status_s1_agent_m0_readdatavalid;                      // board_info_pin_status_s1_translator:uav_readdatavalid -> board_info_pin_status_s1_agent:m0_readdatavalid
	wire          board_info_pin_status_s1_agent_m0_lock;                               // board_info_pin_status_s1_agent:m0_lock -> board_info_pin_status_s1_translator:uav_lock
	wire   [31:0] board_info_pin_status_s1_agent_m0_writedata;                          // board_info_pin_status_s1_agent:m0_writedata -> board_info_pin_status_s1_translator:uav_writedata
	wire          board_info_pin_status_s1_agent_m0_write;                              // board_info_pin_status_s1_agent:m0_write -> board_info_pin_status_s1_translator:uav_write
	wire    [2:0] board_info_pin_status_s1_agent_m0_burstcount;                         // board_info_pin_status_s1_agent:m0_burstcount -> board_info_pin_status_s1_translator:uav_burstcount
	wire          board_info_pin_status_s1_agent_rf_source_valid;                       // board_info_pin_status_s1_agent:rf_source_valid -> board_info_pin_status_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_pin_status_s1_agent_rf_source_data;                        // board_info_pin_status_s1_agent:rf_source_data -> board_info_pin_status_s1_agent_rsp_fifo:in_data
	wire          board_info_pin_status_s1_agent_rf_source_ready;                       // board_info_pin_status_s1_agent_rsp_fifo:in_ready -> board_info_pin_status_s1_agent:rf_source_ready
	wire          board_info_pin_status_s1_agent_rf_source_startofpacket;               // board_info_pin_status_s1_agent:rf_source_startofpacket -> board_info_pin_status_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_pin_status_s1_agent_rf_source_endofpacket;                 // board_info_pin_status_s1_agent:rf_source_endofpacket -> board_info_pin_status_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_pin_status_s1_agent_rsp_fifo_out_valid;                    // board_info_pin_status_s1_agent_rsp_fifo:out_valid -> board_info_pin_status_s1_agent:rf_sink_valid
	wire  [146:0] board_info_pin_status_s1_agent_rsp_fifo_out_data;                     // board_info_pin_status_s1_agent_rsp_fifo:out_data -> board_info_pin_status_s1_agent:rf_sink_data
	wire          board_info_pin_status_s1_agent_rsp_fifo_out_ready;                    // board_info_pin_status_s1_agent:rf_sink_ready -> board_info_pin_status_s1_agent_rsp_fifo:out_ready
	wire          board_info_pin_status_s1_agent_rsp_fifo_out_startofpacket;            // board_info_pin_status_s1_agent_rsp_fifo:out_startofpacket -> board_info_pin_status_s1_agent:rf_sink_startofpacket
	wire          board_info_pin_status_s1_agent_rsp_fifo_out_endofpacket;              // board_info_pin_status_s1_agent_rsp_fifo:out_endofpacket -> board_info_pin_status_s1_agent:rf_sink_endofpacket
	wire          board_info_pin_status_s1_agent_rdata_fifo_src_valid;                  // board_info_pin_status_s1_agent:rdata_fifo_src_valid -> board_info_pin_status_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_pin_status_s1_agent_rdata_fifo_src_data;                   // board_info_pin_status_s1_agent:rdata_fifo_src_data -> board_info_pin_status_s1_agent_rdata_fifo:in_data
	wire          board_info_pin_status_s1_agent_rdata_fifo_src_ready;                  // board_info_pin_status_s1_agent_rdata_fifo:in_ready -> board_info_pin_status_s1_agent:rdata_fifo_src_ready
	wire          board_info_pin_status_s1_agent_rdata_fifo_out_valid;                  // board_info_pin_status_s1_agent_rdata_fifo:out_valid -> board_info_pin_status_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_pin_status_s1_agent_rdata_fifo_out_data;                   // board_info_pin_status_s1_agent_rdata_fifo:out_data -> board_info_pin_status_s1_agent:rdata_fifo_sink_data
	wire          board_info_pin_status_s1_agent_rdata_fifo_out_ready;                  // board_info_pin_status_s1_agent:rdata_fifo_sink_ready -> board_info_pin_status_s1_agent_rdata_fifo:out_ready
	wire   [31:0] board_info_temperature_board2_s1_agent_m0_readdata;                   // board_info_temperature_board2_s1_translator:uav_readdata -> board_info_temperature_board2_s1_agent:m0_readdata
	wire          board_info_temperature_board2_s1_agent_m0_waitrequest;                // board_info_temperature_board2_s1_translator:uav_waitrequest -> board_info_temperature_board2_s1_agent:m0_waitrequest
	wire          board_info_temperature_board2_s1_agent_m0_debugaccess;                // board_info_temperature_board2_s1_agent:m0_debugaccess -> board_info_temperature_board2_s1_translator:uav_debugaccess
	wire   [31:0] board_info_temperature_board2_s1_agent_m0_address;                    // board_info_temperature_board2_s1_agent:m0_address -> board_info_temperature_board2_s1_translator:uav_address
	wire    [3:0] board_info_temperature_board2_s1_agent_m0_byteenable;                 // board_info_temperature_board2_s1_agent:m0_byteenable -> board_info_temperature_board2_s1_translator:uav_byteenable
	wire          board_info_temperature_board2_s1_agent_m0_read;                       // board_info_temperature_board2_s1_agent:m0_read -> board_info_temperature_board2_s1_translator:uav_read
	wire          board_info_temperature_board2_s1_agent_m0_readdatavalid;              // board_info_temperature_board2_s1_translator:uav_readdatavalid -> board_info_temperature_board2_s1_agent:m0_readdatavalid
	wire          board_info_temperature_board2_s1_agent_m0_lock;                       // board_info_temperature_board2_s1_agent:m0_lock -> board_info_temperature_board2_s1_translator:uav_lock
	wire   [31:0] board_info_temperature_board2_s1_agent_m0_writedata;                  // board_info_temperature_board2_s1_agent:m0_writedata -> board_info_temperature_board2_s1_translator:uav_writedata
	wire          board_info_temperature_board2_s1_agent_m0_write;                      // board_info_temperature_board2_s1_agent:m0_write -> board_info_temperature_board2_s1_translator:uav_write
	wire    [2:0] board_info_temperature_board2_s1_agent_m0_burstcount;                 // board_info_temperature_board2_s1_agent:m0_burstcount -> board_info_temperature_board2_s1_translator:uav_burstcount
	wire          board_info_temperature_board2_s1_agent_rf_source_valid;               // board_info_temperature_board2_s1_agent:rf_source_valid -> board_info_temperature_board2_s1_agent_rsp_fifo:in_valid
	wire  [146:0] board_info_temperature_board2_s1_agent_rf_source_data;                // board_info_temperature_board2_s1_agent:rf_source_data -> board_info_temperature_board2_s1_agent_rsp_fifo:in_data
	wire          board_info_temperature_board2_s1_agent_rf_source_ready;               // board_info_temperature_board2_s1_agent_rsp_fifo:in_ready -> board_info_temperature_board2_s1_agent:rf_source_ready
	wire          board_info_temperature_board2_s1_agent_rf_source_startofpacket;       // board_info_temperature_board2_s1_agent:rf_source_startofpacket -> board_info_temperature_board2_s1_agent_rsp_fifo:in_startofpacket
	wire          board_info_temperature_board2_s1_agent_rf_source_endofpacket;         // board_info_temperature_board2_s1_agent:rf_source_endofpacket -> board_info_temperature_board2_s1_agent_rsp_fifo:in_endofpacket
	wire          board_info_temperature_board2_s1_agent_rsp_fifo_out_valid;            // board_info_temperature_board2_s1_agent_rsp_fifo:out_valid -> board_info_temperature_board2_s1_agent:rf_sink_valid
	wire  [146:0] board_info_temperature_board2_s1_agent_rsp_fifo_out_data;             // board_info_temperature_board2_s1_agent_rsp_fifo:out_data -> board_info_temperature_board2_s1_agent:rf_sink_data
	wire          board_info_temperature_board2_s1_agent_rsp_fifo_out_ready;            // board_info_temperature_board2_s1_agent:rf_sink_ready -> board_info_temperature_board2_s1_agent_rsp_fifo:out_ready
	wire          board_info_temperature_board2_s1_agent_rsp_fifo_out_startofpacket;    // board_info_temperature_board2_s1_agent_rsp_fifo:out_startofpacket -> board_info_temperature_board2_s1_agent:rf_sink_startofpacket
	wire          board_info_temperature_board2_s1_agent_rsp_fifo_out_endofpacket;      // board_info_temperature_board2_s1_agent_rsp_fifo:out_endofpacket -> board_info_temperature_board2_s1_agent:rf_sink_endofpacket
	wire          board_info_temperature_board2_s1_agent_rdata_fifo_src_valid;          // board_info_temperature_board2_s1_agent:rdata_fifo_src_valid -> board_info_temperature_board2_s1_agent_rdata_fifo:in_valid
	wire   [33:0] board_info_temperature_board2_s1_agent_rdata_fifo_src_data;           // board_info_temperature_board2_s1_agent:rdata_fifo_src_data -> board_info_temperature_board2_s1_agent_rdata_fifo:in_data
	wire          board_info_temperature_board2_s1_agent_rdata_fifo_src_ready;          // board_info_temperature_board2_s1_agent_rdata_fifo:in_ready -> board_info_temperature_board2_s1_agent:rdata_fifo_src_ready
	wire          board_info_temperature_board2_s1_agent_rdata_fifo_out_valid;          // board_info_temperature_board2_s1_agent_rdata_fifo:out_valid -> board_info_temperature_board2_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] board_info_temperature_board2_s1_agent_rdata_fifo_out_data;           // board_info_temperature_board2_s1_agent_rdata_fifo:out_data -> board_info_temperature_board2_s1_agent:rdata_fifo_sink_data
	wire          board_info_temperature_board2_s1_agent_rdata_fifo_out_ready;          // board_info_temperature_board2_s1_agent:rdata_fifo_sink_ready -> board_info_temperature_board2_s1_agent_rdata_fifo:out_ready
	wire   [31:0] intel_onchip_memory_s1_agent_m0_readdata;                             // intel_onchip_memory_s1_translator:uav_readdata -> intel_onchip_memory_s1_agent:m0_readdata
	wire          intel_onchip_memory_s1_agent_m0_waitrequest;                          // intel_onchip_memory_s1_translator:uav_waitrequest -> intel_onchip_memory_s1_agent:m0_waitrequest
	wire          intel_onchip_memory_s1_agent_m0_debugaccess;                          // intel_onchip_memory_s1_agent:m0_debugaccess -> intel_onchip_memory_s1_translator:uav_debugaccess
	wire   [31:0] intel_onchip_memory_s1_agent_m0_address;                              // intel_onchip_memory_s1_agent:m0_address -> intel_onchip_memory_s1_translator:uav_address
	wire    [3:0] intel_onchip_memory_s1_agent_m0_byteenable;                           // intel_onchip_memory_s1_agent:m0_byteenable -> intel_onchip_memory_s1_translator:uav_byteenable
	wire          intel_onchip_memory_s1_agent_m0_read;                                 // intel_onchip_memory_s1_agent:m0_read -> intel_onchip_memory_s1_translator:uav_read
	wire          intel_onchip_memory_s1_agent_m0_readdatavalid;                        // intel_onchip_memory_s1_translator:uav_readdatavalid -> intel_onchip_memory_s1_agent:m0_readdatavalid
	wire          intel_onchip_memory_s1_agent_m0_lock;                                 // intel_onchip_memory_s1_agent:m0_lock -> intel_onchip_memory_s1_translator:uav_lock
	wire   [31:0] intel_onchip_memory_s1_agent_m0_writedata;                            // intel_onchip_memory_s1_agent:m0_writedata -> intel_onchip_memory_s1_translator:uav_writedata
	wire          intel_onchip_memory_s1_agent_m0_write;                                // intel_onchip_memory_s1_agent:m0_write -> intel_onchip_memory_s1_translator:uav_write
	wire    [2:0] intel_onchip_memory_s1_agent_m0_burstcount;                           // intel_onchip_memory_s1_agent:m0_burstcount -> intel_onchip_memory_s1_translator:uav_burstcount
	wire          intel_onchip_memory_s1_agent_rf_source_valid;                         // intel_onchip_memory_s1_agent:rf_source_valid -> intel_onchip_memory_s1_agent_rsp_fifo:in_valid
	wire  [146:0] intel_onchip_memory_s1_agent_rf_source_data;                          // intel_onchip_memory_s1_agent:rf_source_data -> intel_onchip_memory_s1_agent_rsp_fifo:in_data
	wire          intel_onchip_memory_s1_agent_rf_source_ready;                         // intel_onchip_memory_s1_agent_rsp_fifo:in_ready -> intel_onchip_memory_s1_agent:rf_source_ready
	wire          intel_onchip_memory_s1_agent_rf_source_startofpacket;                 // intel_onchip_memory_s1_agent:rf_source_startofpacket -> intel_onchip_memory_s1_agent_rsp_fifo:in_startofpacket
	wire          intel_onchip_memory_s1_agent_rf_source_endofpacket;                   // intel_onchip_memory_s1_agent:rf_source_endofpacket -> intel_onchip_memory_s1_agent_rsp_fifo:in_endofpacket
	wire          intel_onchip_memory_s1_agent_rsp_fifo_out_valid;                      // intel_onchip_memory_s1_agent_rsp_fifo:out_valid -> intel_onchip_memory_s1_agent:rf_sink_valid
	wire  [146:0] intel_onchip_memory_s1_agent_rsp_fifo_out_data;                       // intel_onchip_memory_s1_agent_rsp_fifo:out_data -> intel_onchip_memory_s1_agent:rf_sink_data
	wire          intel_onchip_memory_s1_agent_rsp_fifo_out_ready;                      // intel_onchip_memory_s1_agent:rf_sink_ready -> intel_onchip_memory_s1_agent_rsp_fifo:out_ready
	wire          intel_onchip_memory_s1_agent_rsp_fifo_out_startofpacket;              // intel_onchip_memory_s1_agent_rsp_fifo:out_startofpacket -> intel_onchip_memory_s1_agent:rf_sink_startofpacket
	wire          intel_onchip_memory_s1_agent_rsp_fifo_out_endofpacket;                // intel_onchip_memory_s1_agent_rsp_fifo:out_endofpacket -> intel_onchip_memory_s1_agent:rf_sink_endofpacket
	wire          intel_onchip_memory_s1_agent_rdata_fifo_src_valid;                    // intel_onchip_memory_s1_agent:rdata_fifo_src_valid -> intel_onchip_memory_s1_agent_rdata_fifo:in_valid
	wire   [33:0] intel_onchip_memory_s1_agent_rdata_fifo_src_data;                     // intel_onchip_memory_s1_agent:rdata_fifo_src_data -> intel_onchip_memory_s1_agent_rdata_fifo:in_data
	wire          intel_onchip_memory_s1_agent_rdata_fifo_src_ready;                    // intel_onchip_memory_s1_agent_rdata_fifo:in_ready -> intel_onchip_memory_s1_agent:rdata_fifo_src_ready
	wire          intel_onchip_memory_s1_agent_rdata_fifo_out_valid;                    // intel_onchip_memory_s1_agent_rdata_fifo:out_valid -> intel_onchip_memory_s1_agent:rdata_fifo_sink_valid
	wire   [33:0] intel_onchip_memory_s1_agent_rdata_fifo_out_data;                     // intel_onchip_memory_s1_agent_rdata_fifo:out_data -> intel_onchip_memory_s1_agent:rdata_fifo_sink_data
	wire          intel_onchip_memory_s1_agent_rdata_fifo_out_ready;                    // intel_onchip_memory_s1_agent:rdata_fifo_sink_ready -> intel_onchip_memory_s1_agent_rdata_fifo:out_ready
	wire   [31:0] intel_niosv_g_timer_sw_agent_agent_m0_readdata;                       // intel_niosv_g_timer_sw_agent_translator:uav_readdata -> intel_niosv_g_timer_sw_agent_agent:m0_readdata
	wire          intel_niosv_g_timer_sw_agent_agent_m0_waitrequest;                    // intel_niosv_g_timer_sw_agent_translator:uav_waitrequest -> intel_niosv_g_timer_sw_agent_agent:m0_waitrequest
	wire          intel_niosv_g_timer_sw_agent_agent_m0_debugaccess;                    // intel_niosv_g_timer_sw_agent_agent:m0_debugaccess -> intel_niosv_g_timer_sw_agent_translator:uav_debugaccess
	wire   [31:0] intel_niosv_g_timer_sw_agent_agent_m0_address;                        // intel_niosv_g_timer_sw_agent_agent:m0_address -> intel_niosv_g_timer_sw_agent_translator:uav_address
	wire    [3:0] intel_niosv_g_timer_sw_agent_agent_m0_byteenable;                     // intel_niosv_g_timer_sw_agent_agent:m0_byteenable -> intel_niosv_g_timer_sw_agent_translator:uav_byteenable
	wire          intel_niosv_g_timer_sw_agent_agent_m0_read;                           // intel_niosv_g_timer_sw_agent_agent:m0_read -> intel_niosv_g_timer_sw_agent_translator:uav_read
	wire          intel_niosv_g_timer_sw_agent_agent_m0_readdatavalid;                  // intel_niosv_g_timer_sw_agent_translator:uav_readdatavalid -> intel_niosv_g_timer_sw_agent_agent:m0_readdatavalid
	wire          intel_niosv_g_timer_sw_agent_agent_m0_lock;                           // intel_niosv_g_timer_sw_agent_agent:m0_lock -> intel_niosv_g_timer_sw_agent_translator:uav_lock
	wire   [31:0] intel_niosv_g_timer_sw_agent_agent_m0_writedata;                      // intel_niosv_g_timer_sw_agent_agent:m0_writedata -> intel_niosv_g_timer_sw_agent_translator:uav_writedata
	wire          intel_niosv_g_timer_sw_agent_agent_m0_write;                          // intel_niosv_g_timer_sw_agent_agent:m0_write -> intel_niosv_g_timer_sw_agent_translator:uav_write
	wire    [2:0] intel_niosv_g_timer_sw_agent_agent_m0_burstcount;                     // intel_niosv_g_timer_sw_agent_agent:m0_burstcount -> intel_niosv_g_timer_sw_agent_translator:uav_burstcount
	wire          intel_niosv_g_timer_sw_agent_agent_rf_source_valid;                   // intel_niosv_g_timer_sw_agent_agent:rf_source_valid -> intel_niosv_g_timer_sw_agent_agent_rsp_fifo:in_valid
	wire  [146:0] intel_niosv_g_timer_sw_agent_agent_rf_source_data;                    // intel_niosv_g_timer_sw_agent_agent:rf_source_data -> intel_niosv_g_timer_sw_agent_agent_rsp_fifo:in_data
	wire          intel_niosv_g_timer_sw_agent_agent_rf_source_ready;                   // intel_niosv_g_timer_sw_agent_agent_rsp_fifo:in_ready -> intel_niosv_g_timer_sw_agent_agent:rf_source_ready
	wire          intel_niosv_g_timer_sw_agent_agent_rf_source_startofpacket;           // intel_niosv_g_timer_sw_agent_agent:rf_source_startofpacket -> intel_niosv_g_timer_sw_agent_agent_rsp_fifo:in_startofpacket
	wire          intel_niosv_g_timer_sw_agent_agent_rf_source_endofpacket;             // intel_niosv_g_timer_sw_agent_agent:rf_source_endofpacket -> intel_niosv_g_timer_sw_agent_agent_rsp_fifo:in_endofpacket
	wire          intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_valid;                // intel_niosv_g_timer_sw_agent_agent_rsp_fifo:out_valid -> intel_niosv_g_timer_sw_agent_agent:rf_sink_valid
	wire  [146:0] intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_data;                 // intel_niosv_g_timer_sw_agent_agent_rsp_fifo:out_data -> intel_niosv_g_timer_sw_agent_agent:rf_sink_data
	wire          intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_ready;                // intel_niosv_g_timer_sw_agent_agent:rf_sink_ready -> intel_niosv_g_timer_sw_agent_agent_rsp_fifo:out_ready
	wire          intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_startofpacket;        // intel_niosv_g_timer_sw_agent_agent_rsp_fifo:out_startofpacket -> intel_niosv_g_timer_sw_agent_agent:rf_sink_startofpacket
	wire          intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_endofpacket;          // intel_niosv_g_timer_sw_agent_agent_rsp_fifo:out_endofpacket -> intel_niosv_g_timer_sw_agent_agent:rf_sink_endofpacket
	wire          intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_valid;              // intel_niosv_g_timer_sw_agent_agent:rdata_fifo_src_valid -> intel_niosv_g_timer_sw_agent_agent_rdata_fifo:in_valid
	wire   [33:0] intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_data;               // intel_niosv_g_timer_sw_agent_agent:rdata_fifo_src_data -> intel_niosv_g_timer_sw_agent_agent_rdata_fifo:in_data
	wire          intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_ready;              // intel_niosv_g_timer_sw_agent_agent_rdata_fifo:in_ready -> intel_niosv_g_timer_sw_agent_agent:rdata_fifo_src_ready
	wire          intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_valid;              // intel_niosv_g_timer_sw_agent_agent_rdata_fifo:out_valid -> intel_niosv_g_timer_sw_agent_agent:rdata_fifo_sink_valid
	wire   [33:0] intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_data;               // intel_niosv_g_timer_sw_agent_agent_rdata_fifo:out_data -> intel_niosv_g_timer_sw_agent_agent:rdata_fifo_sink_data
	wire          intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_ready;              // intel_niosv_g_timer_sw_agent_agent:rdata_fifo_sink_ready -> intel_niosv_g_timer_sw_agent_agent_rdata_fifo:out_ready
	wire          intel_niosv_g_data_manager_agent_write_cp_valid;                      // intel_niosv_g_data_manager_agent:write_cp_valid -> router:sink_valid
	wire  [145:0] intel_niosv_g_data_manager_agent_write_cp_data;                       // intel_niosv_g_data_manager_agent:write_cp_data -> router:sink_data
	wire          intel_niosv_g_data_manager_agent_write_cp_ready;                      // router:sink_ready -> intel_niosv_g_data_manager_agent:write_cp_ready
	wire          intel_niosv_g_data_manager_agent_write_cp_startofpacket;              // intel_niosv_g_data_manager_agent:write_cp_startofpacket -> router:sink_startofpacket
	wire          intel_niosv_g_data_manager_agent_write_cp_endofpacket;                // intel_niosv_g_data_manager_agent:write_cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                     // router:src_valid -> cmd_demux:sink_valid
	wire  [145:0] router_src_data;                                                      // router:src_data -> cmd_demux:sink_data
	wire          router_src_ready;                                                     // cmd_demux:sink_ready -> router:src_ready
	wire   [13:0] router_src_channel;                                                   // router:src_channel -> cmd_demux:sink_channel
	wire          router_src_startofpacket;                                             // router:src_startofpacket -> cmd_demux:sink_startofpacket
	wire          router_src_endofpacket;                                               // router:src_endofpacket -> cmd_demux:sink_endofpacket
	wire          intel_niosv_g_data_manager_agent_read_cp_valid;                       // intel_niosv_g_data_manager_agent:read_cp_valid -> router_001:sink_valid
	wire  [145:0] intel_niosv_g_data_manager_agent_read_cp_data;                        // intel_niosv_g_data_manager_agent:read_cp_data -> router_001:sink_data
	wire          intel_niosv_g_data_manager_agent_read_cp_ready;                       // router_001:sink_ready -> intel_niosv_g_data_manager_agent:read_cp_ready
	wire          intel_niosv_g_data_manager_agent_read_cp_startofpacket;               // intel_niosv_g_data_manager_agent:read_cp_startofpacket -> router_001:sink_startofpacket
	wire          intel_niosv_g_data_manager_agent_read_cp_endofpacket;                 // intel_niosv_g_data_manager_agent:read_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                 // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [145:0] router_001_src_data;                                                  // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                 // cmd_demux_001:sink_ready -> router_001:src_ready
	wire   [13:0] router_001_src_channel;                                               // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                         // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                           // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          intel_niosv_g_instruction_manager_agent_write_cp_valid;               // intel_niosv_g_instruction_manager_agent:write_cp_valid -> router_002:sink_valid
	wire  [145:0] intel_niosv_g_instruction_manager_agent_write_cp_data;                // intel_niosv_g_instruction_manager_agent:write_cp_data -> router_002:sink_data
	wire          intel_niosv_g_instruction_manager_agent_write_cp_ready;               // router_002:sink_ready -> intel_niosv_g_instruction_manager_agent:write_cp_ready
	wire          intel_niosv_g_instruction_manager_agent_write_cp_startofpacket;       // intel_niosv_g_instruction_manager_agent:write_cp_startofpacket -> router_002:sink_startofpacket
	wire          intel_niosv_g_instruction_manager_agent_write_cp_endofpacket;         // intel_niosv_g_instruction_manager_agent:write_cp_endofpacket -> router_002:sink_endofpacket
	wire          intel_niosv_g_instruction_manager_agent_read_cp_valid;                // intel_niosv_g_instruction_manager_agent:read_cp_valid -> router_003:sink_valid
	wire  [145:0] intel_niosv_g_instruction_manager_agent_read_cp_data;                 // intel_niosv_g_instruction_manager_agent:read_cp_data -> router_003:sink_data
	wire          intel_niosv_g_instruction_manager_agent_read_cp_ready;                // router_003:sink_ready -> intel_niosv_g_instruction_manager_agent:read_cp_ready
	wire          intel_niosv_g_instruction_manager_agent_read_cp_startofpacket;        // intel_niosv_g_instruction_manager_agent:read_cp_startofpacket -> router_003:sink_startofpacket
	wire          intel_niosv_g_instruction_manager_agent_read_cp_endofpacket;          // intel_niosv_g_instruction_manager_agent:read_cp_endofpacket -> router_003:sink_endofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_valid;                           // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_004:sink_valid
	wire  [145:0] jtag_uart_avalon_jtag_slave_agent_rp_data;                            // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_004:sink_data
	wire          jtag_uart_avalon_jtag_slave_agent_rp_ready;                           // router_004:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
	wire          jtag_uart_avalon_jtag_slave_agent_rp_startofpacket;                   // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
	wire          jtag_uart_avalon_jtag_slave_agent_rp_endofpacket;                     // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
	wire          router_004_src_valid;                                                 // router_004:src_valid -> rsp_demux:sink_valid
	wire  [145:0] router_004_src_data;                                                  // router_004:src_data -> rsp_demux:sink_data
	wire          router_004_src_ready;                                                 // rsp_demux:sink_ready -> router_004:src_ready
	wire   [13:0] router_004_src_channel;                                               // router_004:src_channel -> rsp_demux:sink_channel
	wire          router_004_src_startofpacket;                                         // router_004:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_004_src_endofpacket;                                           // router_004:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          sysid_qsys_control_slave_agent_rp_valid;                              // sysid_qsys_control_slave_agent:rp_valid -> router_005:sink_valid
	wire  [145:0] sysid_qsys_control_slave_agent_rp_data;                               // sysid_qsys_control_slave_agent:rp_data -> router_005:sink_data
	wire          sysid_qsys_control_slave_agent_rp_ready;                              // router_005:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
	wire          sysid_qsys_control_slave_agent_rp_startofpacket;                      // sysid_qsys_control_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
	wire          sysid_qsys_control_slave_agent_rp_endofpacket;                        // sysid_qsys_control_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
	wire          router_005_src_valid;                                                 // router_005:src_valid -> rsp_demux_001:sink_valid
	wire  [145:0] router_005_src_data;                                                  // router_005:src_data -> rsp_demux_001:sink_data
	wire          router_005_src_ready;                                                 // rsp_demux_001:sink_ready -> router_005:src_ready
	wire   [13:0] router_005_src_channel;                                               // router_005:src_channel -> rsp_demux_001:sink_channel
	wire          router_005_src_startofpacket;                                         // router_005:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_005_src_endofpacket;                                           // router_005:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          intel_niosv_g_dm_agent_agent_rp_valid;                                // intel_niosv_g_dm_agent_agent:rp_valid -> router_006:sink_valid
	wire  [145:0] intel_niosv_g_dm_agent_agent_rp_data;                                 // intel_niosv_g_dm_agent_agent:rp_data -> router_006:sink_data
	wire          intel_niosv_g_dm_agent_agent_rp_ready;                                // router_006:sink_ready -> intel_niosv_g_dm_agent_agent:rp_ready
	wire          intel_niosv_g_dm_agent_agent_rp_startofpacket;                        // intel_niosv_g_dm_agent_agent:rp_startofpacket -> router_006:sink_startofpacket
	wire          intel_niosv_g_dm_agent_agent_rp_endofpacket;                          // intel_niosv_g_dm_agent_agent:rp_endofpacket -> router_006:sink_endofpacket
	wire          router_006_src_valid;                                                 // router_006:src_valid -> rsp_demux_002:sink_valid
	wire  [145:0] router_006_src_data;                                                  // router_006:src_data -> rsp_demux_002:sink_data
	wire          router_006_src_ready;                                                 // rsp_demux_002:sink_ready -> router_006:src_ready
	wire   [13:0] router_006_src_channel;                                               // router_006:src_channel -> rsp_demux_002:sink_channel
	wire          router_006_src_startofpacket;                                         // router_006:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_006_src_endofpacket;                                           // router_006:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          timer_s1_agent_rp_valid;                                              // timer_s1_agent:rp_valid -> router_007:sink_valid
	wire  [145:0] timer_s1_agent_rp_data;                                               // timer_s1_agent:rp_data -> router_007:sink_data
	wire          timer_s1_agent_rp_ready;                                              // router_007:sink_ready -> timer_s1_agent:rp_ready
	wire          timer_s1_agent_rp_startofpacket;                                      // timer_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
	wire          timer_s1_agent_rp_endofpacket;                                        // timer_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
	wire          router_007_src_valid;                                                 // router_007:src_valid -> rsp_demux_003:sink_valid
	wire  [145:0] router_007_src_data;                                                  // router_007:src_data -> rsp_demux_003:sink_data
	wire          router_007_src_ready;                                                 // rsp_demux_003:sink_ready -> router_007:src_ready
	wire   [13:0] router_007_src_channel;                                               // router_007:src_channel -> rsp_demux_003:sink_channel
	wire          router_007_src_startofpacket;                                         // router_007:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_007_src_endofpacket;                                           // router_007:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          board_info_power_in_voltage_s1_agent_rp_valid;                        // board_info_power_in_voltage_s1_agent:rp_valid -> router_008:sink_valid
	wire  [145:0] board_info_power_in_voltage_s1_agent_rp_data;                         // board_info_power_in_voltage_s1_agent:rp_data -> router_008:sink_data
	wire          board_info_power_in_voltage_s1_agent_rp_ready;                        // router_008:sink_ready -> board_info_power_in_voltage_s1_agent:rp_ready
	wire          board_info_power_in_voltage_s1_agent_rp_startofpacket;                // board_info_power_in_voltage_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
	wire          board_info_power_in_voltage_s1_agent_rp_endofpacket;                  // board_info_power_in_voltage_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
	wire          router_008_src_valid;                                                 // router_008:src_valid -> rsp_demux_004:sink_valid
	wire  [145:0] router_008_src_data;                                                  // router_008:src_data -> rsp_demux_004:sink_data
	wire          router_008_src_ready;                                                 // rsp_demux_004:sink_ready -> router_008:src_ready
	wire   [13:0] router_008_src_channel;                                               // router_008:src_channel -> rsp_demux_004:sink_channel
	wire          router_008_src_startofpacket;                                         // router_008:src_startofpacket -> rsp_demux_004:sink_startofpacket
	wire          router_008_src_endofpacket;                                           // router_008:src_endofpacket -> rsp_demux_004:sink_endofpacket
	wire          board_info_vcc1p2_voltage_s1_agent_rp_valid;                          // board_info_vcc1p2_voltage_s1_agent:rp_valid -> router_009:sink_valid
	wire  [145:0] board_info_vcc1p2_voltage_s1_agent_rp_data;                           // board_info_vcc1p2_voltage_s1_agent:rp_data -> router_009:sink_data
	wire          board_info_vcc1p2_voltage_s1_agent_rp_ready;                          // router_009:sink_ready -> board_info_vcc1p2_voltage_s1_agent:rp_ready
	wire          board_info_vcc1p2_voltage_s1_agent_rp_startofpacket;                  // board_info_vcc1p2_voltage_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
	wire          board_info_vcc1p2_voltage_s1_agent_rp_endofpacket;                    // board_info_vcc1p2_voltage_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
	wire          router_009_src_valid;                                                 // router_009:src_valid -> rsp_demux_005:sink_valid
	wire  [145:0] router_009_src_data;                                                  // router_009:src_data -> rsp_demux_005:sink_data
	wire          router_009_src_ready;                                                 // rsp_demux_005:sink_ready -> router_009:src_ready
	wire   [13:0] router_009_src_channel;                                               // router_009:src_channel -> rsp_demux_005:sink_channel
	wire          router_009_src_startofpacket;                                         // router_009:src_startofpacket -> rsp_demux_005:sink_startofpacket
	wire          router_009_src_endofpacket;                                           // router_009:src_endofpacket -> rsp_demux_005:sink_endofpacket
	wire          board_info_vcc1p2_current_s1_agent_rp_valid;                          // board_info_vcc1p2_current_s1_agent:rp_valid -> router_010:sink_valid
	wire  [145:0] board_info_vcc1p2_current_s1_agent_rp_data;                           // board_info_vcc1p2_current_s1_agent:rp_data -> router_010:sink_data
	wire          board_info_vcc1p2_current_s1_agent_rp_ready;                          // router_010:sink_ready -> board_info_vcc1p2_current_s1_agent:rp_ready
	wire          board_info_vcc1p2_current_s1_agent_rp_startofpacket;                  // board_info_vcc1p2_current_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
	wire          board_info_vcc1p2_current_s1_agent_rp_endofpacket;                    // board_info_vcc1p2_current_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
	wire          router_010_src_valid;                                                 // router_010:src_valid -> rsp_demux_006:sink_valid
	wire  [145:0] router_010_src_data;                                                  // router_010:src_data -> rsp_demux_006:sink_data
	wire          router_010_src_ready;                                                 // rsp_demux_006:sink_ready -> router_010:src_ready
	wire   [13:0] router_010_src_channel;                                               // router_010:src_channel -> rsp_demux_006:sink_channel
	wire          router_010_src_startofpacket;                                         // router_010:src_startofpacket -> rsp_demux_006:sink_startofpacket
	wire          router_010_src_endofpacket;                                           // router_010:src_endofpacket -> rsp_demux_006:sink_endofpacket
	wire          board_info_fan_speed_s1_agent_rp_valid;                               // board_info_fan_speed_s1_agent:rp_valid -> router_011:sink_valid
	wire  [145:0] board_info_fan_speed_s1_agent_rp_data;                                // board_info_fan_speed_s1_agent:rp_data -> router_011:sink_data
	wire          board_info_fan_speed_s1_agent_rp_ready;                               // router_011:sink_ready -> board_info_fan_speed_s1_agent:rp_ready
	wire          board_info_fan_speed_s1_agent_rp_startofpacket;                       // board_info_fan_speed_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
	wire          board_info_fan_speed_s1_agent_rp_endofpacket;                         // board_info_fan_speed_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
	wire          router_011_src_valid;                                                 // router_011:src_valid -> rsp_demux_007:sink_valid
	wire  [145:0] router_011_src_data;                                                  // router_011:src_data -> rsp_demux_007:sink_data
	wire          router_011_src_ready;                                                 // rsp_demux_007:sink_ready -> router_011:src_ready
	wire   [13:0] router_011_src_channel;                                               // router_011:src_channel -> rsp_demux_007:sink_channel
	wire          router_011_src_startofpacket;                                         // router_011:src_startofpacket -> rsp_demux_007:sink_startofpacket
	wire          router_011_src_endofpacket;                                           // router_011:src_endofpacket -> rsp_demux_007:sink_endofpacket
	wire          board_info_temperature_fpga_s1_agent_rp_valid;                        // board_info_temperature_fpga_s1_agent:rp_valid -> router_012:sink_valid
	wire  [145:0] board_info_temperature_fpga_s1_agent_rp_data;                         // board_info_temperature_fpga_s1_agent:rp_data -> router_012:sink_data
	wire          board_info_temperature_fpga_s1_agent_rp_ready;                        // router_012:sink_ready -> board_info_temperature_fpga_s1_agent:rp_ready
	wire          board_info_temperature_fpga_s1_agent_rp_startofpacket;                // board_info_temperature_fpga_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
	wire          board_info_temperature_fpga_s1_agent_rp_endofpacket;                  // board_info_temperature_fpga_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
	wire          router_012_src_valid;                                                 // router_012:src_valid -> rsp_demux_008:sink_valid
	wire  [145:0] router_012_src_data;                                                  // router_012:src_data -> rsp_demux_008:sink_data
	wire          router_012_src_ready;                                                 // rsp_demux_008:sink_ready -> router_012:src_ready
	wire   [13:0] router_012_src_channel;                                               // router_012:src_channel -> rsp_demux_008:sink_channel
	wire          router_012_src_startofpacket;                                         // router_012:src_startofpacket -> rsp_demux_008:sink_startofpacket
	wire          router_012_src_endofpacket;                                           // router_012:src_endofpacket -> rsp_demux_008:sink_endofpacket
	wire          board_info_temperature_board1_s1_agent_rp_valid;                      // board_info_temperature_board1_s1_agent:rp_valid -> router_013:sink_valid
	wire  [145:0] board_info_temperature_board1_s1_agent_rp_data;                       // board_info_temperature_board1_s1_agent:rp_data -> router_013:sink_data
	wire          board_info_temperature_board1_s1_agent_rp_ready;                      // router_013:sink_ready -> board_info_temperature_board1_s1_agent:rp_ready
	wire          board_info_temperature_board1_s1_agent_rp_startofpacket;              // board_info_temperature_board1_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
	wire          board_info_temperature_board1_s1_agent_rp_endofpacket;                // board_info_temperature_board1_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
	wire          router_013_src_valid;                                                 // router_013:src_valid -> rsp_demux_009:sink_valid
	wire  [145:0] router_013_src_data;                                                  // router_013:src_data -> rsp_demux_009:sink_data
	wire          router_013_src_ready;                                                 // rsp_demux_009:sink_ready -> router_013:src_ready
	wire   [13:0] router_013_src_channel;                                               // router_013:src_channel -> rsp_demux_009:sink_channel
	wire          router_013_src_startofpacket;                                         // router_013:src_startofpacket -> rsp_demux_009:sink_startofpacket
	wire          router_013_src_endofpacket;                                           // router_013:src_endofpacket -> rsp_demux_009:sink_endofpacket
	wire          board_info_pin_status_s1_agent_rp_valid;                              // board_info_pin_status_s1_agent:rp_valid -> router_014:sink_valid
	wire  [145:0] board_info_pin_status_s1_agent_rp_data;                               // board_info_pin_status_s1_agent:rp_data -> router_014:sink_data
	wire          board_info_pin_status_s1_agent_rp_ready;                              // router_014:sink_ready -> board_info_pin_status_s1_agent:rp_ready
	wire          board_info_pin_status_s1_agent_rp_startofpacket;                      // board_info_pin_status_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
	wire          board_info_pin_status_s1_agent_rp_endofpacket;                        // board_info_pin_status_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
	wire          router_014_src_valid;                                                 // router_014:src_valid -> rsp_demux_010:sink_valid
	wire  [145:0] router_014_src_data;                                                  // router_014:src_data -> rsp_demux_010:sink_data
	wire          router_014_src_ready;                                                 // rsp_demux_010:sink_ready -> router_014:src_ready
	wire   [13:0] router_014_src_channel;                                               // router_014:src_channel -> rsp_demux_010:sink_channel
	wire          router_014_src_startofpacket;                                         // router_014:src_startofpacket -> rsp_demux_010:sink_startofpacket
	wire          router_014_src_endofpacket;                                           // router_014:src_endofpacket -> rsp_demux_010:sink_endofpacket
	wire          board_info_temperature_board2_s1_agent_rp_valid;                      // board_info_temperature_board2_s1_agent:rp_valid -> router_015:sink_valid
	wire  [145:0] board_info_temperature_board2_s1_agent_rp_data;                       // board_info_temperature_board2_s1_agent:rp_data -> router_015:sink_data
	wire          board_info_temperature_board2_s1_agent_rp_ready;                      // router_015:sink_ready -> board_info_temperature_board2_s1_agent:rp_ready
	wire          board_info_temperature_board2_s1_agent_rp_startofpacket;              // board_info_temperature_board2_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
	wire          board_info_temperature_board2_s1_agent_rp_endofpacket;                // board_info_temperature_board2_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
	wire          router_015_src_valid;                                                 // router_015:src_valid -> rsp_demux_011:sink_valid
	wire  [145:0] router_015_src_data;                                                  // router_015:src_data -> rsp_demux_011:sink_data
	wire          router_015_src_ready;                                                 // rsp_demux_011:sink_ready -> router_015:src_ready
	wire   [13:0] router_015_src_channel;                                               // router_015:src_channel -> rsp_demux_011:sink_channel
	wire          router_015_src_startofpacket;                                         // router_015:src_startofpacket -> rsp_demux_011:sink_startofpacket
	wire          router_015_src_endofpacket;                                           // router_015:src_endofpacket -> rsp_demux_011:sink_endofpacket
	wire          intel_onchip_memory_s1_agent_rp_valid;                                // intel_onchip_memory_s1_agent:rp_valid -> router_016:sink_valid
	wire  [145:0] intel_onchip_memory_s1_agent_rp_data;                                 // intel_onchip_memory_s1_agent:rp_data -> router_016:sink_data
	wire          intel_onchip_memory_s1_agent_rp_ready;                                // router_016:sink_ready -> intel_onchip_memory_s1_agent:rp_ready
	wire          intel_onchip_memory_s1_agent_rp_startofpacket;                        // intel_onchip_memory_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
	wire          intel_onchip_memory_s1_agent_rp_endofpacket;                          // intel_onchip_memory_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
	wire          router_016_src_valid;                                                 // router_016:src_valid -> rsp_demux_012:sink_valid
	wire  [145:0] router_016_src_data;                                                  // router_016:src_data -> rsp_demux_012:sink_data
	wire          router_016_src_ready;                                                 // rsp_demux_012:sink_ready -> router_016:src_ready
	wire   [13:0] router_016_src_channel;                                               // router_016:src_channel -> rsp_demux_012:sink_channel
	wire          router_016_src_startofpacket;                                         // router_016:src_startofpacket -> rsp_demux_012:sink_startofpacket
	wire          router_016_src_endofpacket;                                           // router_016:src_endofpacket -> rsp_demux_012:sink_endofpacket
	wire          intel_niosv_g_timer_sw_agent_agent_rp_valid;                          // intel_niosv_g_timer_sw_agent_agent:rp_valid -> router_017:sink_valid
	wire  [145:0] intel_niosv_g_timer_sw_agent_agent_rp_data;                           // intel_niosv_g_timer_sw_agent_agent:rp_data -> router_017:sink_data
	wire          intel_niosv_g_timer_sw_agent_agent_rp_ready;                          // router_017:sink_ready -> intel_niosv_g_timer_sw_agent_agent:rp_ready
	wire          intel_niosv_g_timer_sw_agent_agent_rp_startofpacket;                  // intel_niosv_g_timer_sw_agent_agent:rp_startofpacket -> router_017:sink_startofpacket
	wire          intel_niosv_g_timer_sw_agent_agent_rp_endofpacket;                    // intel_niosv_g_timer_sw_agent_agent:rp_endofpacket -> router_017:sink_endofpacket
	wire          router_017_src_valid;                                                 // router_017:src_valid -> rsp_demux_013:sink_valid
	wire  [145:0] router_017_src_data;                                                  // router_017:src_data -> rsp_demux_013:sink_data
	wire          router_017_src_ready;                                                 // rsp_demux_013:sink_ready -> router_017:src_ready
	wire   [13:0] router_017_src_channel;                                               // router_017:src_channel -> rsp_demux_013:sink_channel
	wire          router_017_src_startofpacket;                                         // router_017:src_startofpacket -> rsp_demux_013:sink_startofpacket
	wire          router_017_src_endofpacket;                                           // router_017:src_endofpacket -> rsp_demux_013:sink_endofpacket
	wire          router_002_src_valid;                                                 // router_002:src_valid -> intel_niosv_g_instruction_manager_wr_limiter:cmd_sink_valid
	wire  [145:0] router_002_src_data;                                                  // router_002:src_data -> intel_niosv_g_instruction_manager_wr_limiter:cmd_sink_data
	wire          router_002_src_ready;                                                 // intel_niosv_g_instruction_manager_wr_limiter:cmd_sink_ready -> router_002:src_ready
	wire   [13:0] router_002_src_channel;                                               // router_002:src_channel -> intel_niosv_g_instruction_manager_wr_limiter:cmd_sink_channel
	wire          router_002_src_startofpacket;                                         // router_002:src_startofpacket -> intel_niosv_g_instruction_manager_wr_limiter:cmd_sink_startofpacket
	wire          router_002_src_endofpacket;                                           // router_002:src_endofpacket -> intel_niosv_g_instruction_manager_wr_limiter:cmd_sink_endofpacket
	wire  [145:0] intel_niosv_g_instruction_manager_wr_limiter_cmd_src_data;            // intel_niosv_g_instruction_manager_wr_limiter:cmd_src_data -> cmd_demux_002:sink_data
	wire          intel_niosv_g_instruction_manager_wr_limiter_cmd_src_ready;           // cmd_demux_002:sink_ready -> intel_niosv_g_instruction_manager_wr_limiter:cmd_src_ready
	wire   [13:0] intel_niosv_g_instruction_manager_wr_limiter_cmd_src_channel;         // intel_niosv_g_instruction_manager_wr_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
	wire          intel_niosv_g_instruction_manager_wr_limiter_cmd_src_startofpacket;   // intel_niosv_g_instruction_manager_wr_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          intel_niosv_g_instruction_manager_wr_limiter_cmd_src_endofpacket;     // intel_niosv_g_instruction_manager_wr_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          rsp_mux_002_src_valid;                                                // rsp_mux_002:src_valid -> intel_niosv_g_instruction_manager_wr_limiter:rsp_sink_valid
	wire  [145:0] rsp_mux_002_src_data;                                                 // rsp_mux_002:src_data -> intel_niosv_g_instruction_manager_wr_limiter:rsp_sink_data
	wire          rsp_mux_002_src_ready;                                                // intel_niosv_g_instruction_manager_wr_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
	wire   [13:0] rsp_mux_002_src_channel;                                              // rsp_mux_002:src_channel -> intel_niosv_g_instruction_manager_wr_limiter:rsp_sink_channel
	wire          rsp_mux_002_src_startofpacket;                                        // rsp_mux_002:src_startofpacket -> intel_niosv_g_instruction_manager_wr_limiter:rsp_sink_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                          // rsp_mux_002:src_endofpacket -> intel_niosv_g_instruction_manager_wr_limiter:rsp_sink_endofpacket
	wire          intel_niosv_g_instruction_manager_wr_limiter_rsp_src_valid;           // intel_niosv_g_instruction_manager_wr_limiter:rsp_src_valid -> intel_niosv_g_instruction_manager_agent:write_rp_valid
	wire  [145:0] intel_niosv_g_instruction_manager_wr_limiter_rsp_src_data;            // intel_niosv_g_instruction_manager_wr_limiter:rsp_src_data -> intel_niosv_g_instruction_manager_agent:write_rp_data
	wire          intel_niosv_g_instruction_manager_wr_limiter_rsp_src_ready;           // intel_niosv_g_instruction_manager_agent:write_rp_ready -> intel_niosv_g_instruction_manager_wr_limiter:rsp_src_ready
	wire   [13:0] intel_niosv_g_instruction_manager_wr_limiter_rsp_src_channel;         // intel_niosv_g_instruction_manager_wr_limiter:rsp_src_channel -> intel_niosv_g_instruction_manager_agent:write_rp_channel
	wire          intel_niosv_g_instruction_manager_wr_limiter_rsp_src_startofpacket;   // intel_niosv_g_instruction_manager_wr_limiter:rsp_src_startofpacket -> intel_niosv_g_instruction_manager_agent:write_rp_startofpacket
	wire          intel_niosv_g_instruction_manager_wr_limiter_rsp_src_endofpacket;     // intel_niosv_g_instruction_manager_wr_limiter:rsp_src_endofpacket -> intel_niosv_g_instruction_manager_agent:write_rp_endofpacket
	wire          router_003_src_valid;                                                 // router_003:src_valid -> intel_niosv_g_instruction_manager_rd_limiter:cmd_sink_valid
	wire  [145:0] router_003_src_data;                                                  // router_003:src_data -> intel_niosv_g_instruction_manager_rd_limiter:cmd_sink_data
	wire          router_003_src_ready;                                                 // intel_niosv_g_instruction_manager_rd_limiter:cmd_sink_ready -> router_003:src_ready
	wire   [13:0] router_003_src_channel;                                               // router_003:src_channel -> intel_niosv_g_instruction_manager_rd_limiter:cmd_sink_channel
	wire          router_003_src_startofpacket;                                         // router_003:src_startofpacket -> intel_niosv_g_instruction_manager_rd_limiter:cmd_sink_startofpacket
	wire          router_003_src_endofpacket;                                           // router_003:src_endofpacket -> intel_niosv_g_instruction_manager_rd_limiter:cmd_sink_endofpacket
	wire  [145:0] intel_niosv_g_instruction_manager_rd_limiter_cmd_src_data;            // intel_niosv_g_instruction_manager_rd_limiter:cmd_src_data -> cmd_demux_003:sink_data
	wire          intel_niosv_g_instruction_manager_rd_limiter_cmd_src_ready;           // cmd_demux_003:sink_ready -> intel_niosv_g_instruction_manager_rd_limiter:cmd_src_ready
	wire   [13:0] intel_niosv_g_instruction_manager_rd_limiter_cmd_src_channel;         // intel_niosv_g_instruction_manager_rd_limiter:cmd_src_channel -> cmd_demux_003:sink_channel
	wire          intel_niosv_g_instruction_manager_rd_limiter_cmd_src_startofpacket;   // intel_niosv_g_instruction_manager_rd_limiter:cmd_src_startofpacket -> cmd_demux_003:sink_startofpacket
	wire          intel_niosv_g_instruction_manager_rd_limiter_cmd_src_endofpacket;     // intel_niosv_g_instruction_manager_rd_limiter:cmd_src_endofpacket -> cmd_demux_003:sink_endofpacket
	wire          rsp_mux_003_src_valid;                                                // rsp_mux_003:src_valid -> intel_niosv_g_instruction_manager_rd_limiter:rsp_sink_valid
	wire  [145:0] rsp_mux_003_src_data;                                                 // rsp_mux_003:src_data -> intel_niosv_g_instruction_manager_rd_limiter:rsp_sink_data
	wire          rsp_mux_003_src_ready;                                                // intel_niosv_g_instruction_manager_rd_limiter:rsp_sink_ready -> rsp_mux_003:src_ready
	wire   [13:0] rsp_mux_003_src_channel;                                              // rsp_mux_003:src_channel -> intel_niosv_g_instruction_manager_rd_limiter:rsp_sink_channel
	wire          rsp_mux_003_src_startofpacket;                                        // rsp_mux_003:src_startofpacket -> intel_niosv_g_instruction_manager_rd_limiter:rsp_sink_startofpacket
	wire          rsp_mux_003_src_endofpacket;                                          // rsp_mux_003:src_endofpacket -> intel_niosv_g_instruction_manager_rd_limiter:rsp_sink_endofpacket
	wire          intel_niosv_g_instruction_manager_rd_limiter_rsp_src_valid;           // intel_niosv_g_instruction_manager_rd_limiter:rsp_src_valid -> intel_niosv_g_instruction_manager_agent:read_rp_valid
	wire  [145:0] intel_niosv_g_instruction_manager_rd_limiter_rsp_src_data;            // intel_niosv_g_instruction_manager_rd_limiter:rsp_src_data -> intel_niosv_g_instruction_manager_agent:read_rp_data
	wire          intel_niosv_g_instruction_manager_rd_limiter_rsp_src_ready;           // intel_niosv_g_instruction_manager_agent:read_rp_ready -> intel_niosv_g_instruction_manager_rd_limiter:rsp_src_ready
	wire   [13:0] intel_niosv_g_instruction_manager_rd_limiter_rsp_src_channel;         // intel_niosv_g_instruction_manager_rd_limiter:rsp_src_channel -> intel_niosv_g_instruction_manager_agent:read_rp_channel
	wire          intel_niosv_g_instruction_manager_rd_limiter_rsp_src_startofpacket;   // intel_niosv_g_instruction_manager_rd_limiter:rsp_src_startofpacket -> intel_niosv_g_instruction_manager_agent:read_rp_startofpacket
	wire          intel_niosv_g_instruction_manager_rd_limiter_rsp_src_endofpacket;     // intel_niosv_g_instruction_manager_rd_limiter:rsp_src_endofpacket -> intel_niosv_g_instruction_manager_agent:read_rp_endofpacket
	wire          cmd_mux_src_valid;                                                    // cmd_mux:src_valid -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_src_data;                                                     // cmd_mux:src_data -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_data
	wire          cmd_mux_src_ready;                                                    // jtag_uart_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux:src_ready
	wire   [13:0] cmd_mux_src_channel;                                                  // cmd_mux:src_channel -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_channel
	wire          cmd_mux_src_startofpacket;                                            // cmd_mux:src_startofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_src_endofpacket;                                              // cmd_mux:src_endofpacket -> jtag_uart_avalon_jtag_slave_burst_adapter:sink0_endofpacket
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid;              // jtag_uart_avalon_jtag_slave_burst_adapter:source0_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
	wire  [145:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_data;               // jtag_uart_avalon_jtag_slave_burst_adapter:source0_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready;              // jtag_uart_avalon_jtag_slave_agent:cp_ready -> jtag_uart_avalon_jtag_slave_burst_adapter:source0_ready
	wire   [13:0] jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel;            // jtag_uart_avalon_jtag_slave_burst_adapter:source0_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket;      // jtag_uart_avalon_jtag_slave_burst_adapter:source0_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
	wire          jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket;        // jtag_uart_avalon_jtag_slave_burst_adapter:source0_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                // cmd_mux_001:src_valid -> sysid_qsys_control_slave_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_001_src_data;                                                 // cmd_mux_001:src_data -> sysid_qsys_control_slave_burst_adapter:sink0_data
	wire          cmd_mux_001_src_ready;                                                // sysid_qsys_control_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
	wire   [13:0] cmd_mux_001_src_channel;                                              // cmd_mux_001:src_channel -> sysid_qsys_control_slave_burst_adapter:sink0_channel
	wire          cmd_mux_001_src_startofpacket;                                        // cmd_mux_001:src_startofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                          // cmd_mux_001:src_endofpacket -> sysid_qsys_control_slave_burst_adapter:sink0_endofpacket
	wire          sysid_qsys_control_slave_burst_adapter_source0_valid;                 // sysid_qsys_control_slave_burst_adapter:source0_valid -> sysid_qsys_control_slave_agent:cp_valid
	wire  [145:0] sysid_qsys_control_slave_burst_adapter_source0_data;                  // sysid_qsys_control_slave_burst_adapter:source0_data -> sysid_qsys_control_slave_agent:cp_data
	wire          sysid_qsys_control_slave_burst_adapter_source0_ready;                 // sysid_qsys_control_slave_agent:cp_ready -> sysid_qsys_control_slave_burst_adapter:source0_ready
	wire   [13:0] sysid_qsys_control_slave_burst_adapter_source0_channel;               // sysid_qsys_control_slave_burst_adapter:source0_channel -> sysid_qsys_control_slave_agent:cp_channel
	wire          sysid_qsys_control_slave_burst_adapter_source0_startofpacket;         // sysid_qsys_control_slave_burst_adapter:source0_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
	wire          sysid_qsys_control_slave_burst_adapter_source0_endofpacket;           // sysid_qsys_control_slave_burst_adapter:source0_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
	wire          cmd_mux_002_src_valid;                                                // cmd_mux_002:src_valid -> intel_niosv_g_dm_agent_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_002_src_data;                                                 // cmd_mux_002:src_data -> intel_niosv_g_dm_agent_burst_adapter:sink0_data
	wire          cmd_mux_002_src_ready;                                                // intel_niosv_g_dm_agent_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
	wire   [13:0] cmd_mux_002_src_channel;                                              // cmd_mux_002:src_channel -> intel_niosv_g_dm_agent_burst_adapter:sink0_channel
	wire          cmd_mux_002_src_startofpacket;                                        // cmd_mux_002:src_startofpacket -> intel_niosv_g_dm_agent_burst_adapter:sink0_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                          // cmd_mux_002:src_endofpacket -> intel_niosv_g_dm_agent_burst_adapter:sink0_endofpacket
	wire          intel_niosv_g_dm_agent_burst_adapter_source0_valid;                   // intel_niosv_g_dm_agent_burst_adapter:source0_valid -> intel_niosv_g_dm_agent_agent:cp_valid
	wire  [145:0] intel_niosv_g_dm_agent_burst_adapter_source0_data;                    // intel_niosv_g_dm_agent_burst_adapter:source0_data -> intel_niosv_g_dm_agent_agent:cp_data
	wire          intel_niosv_g_dm_agent_burst_adapter_source0_ready;                   // intel_niosv_g_dm_agent_agent:cp_ready -> intel_niosv_g_dm_agent_burst_adapter:source0_ready
	wire   [13:0] intel_niosv_g_dm_agent_burst_adapter_source0_channel;                 // intel_niosv_g_dm_agent_burst_adapter:source0_channel -> intel_niosv_g_dm_agent_agent:cp_channel
	wire          intel_niosv_g_dm_agent_burst_adapter_source0_startofpacket;           // intel_niosv_g_dm_agent_burst_adapter:source0_startofpacket -> intel_niosv_g_dm_agent_agent:cp_startofpacket
	wire          intel_niosv_g_dm_agent_burst_adapter_source0_endofpacket;             // intel_niosv_g_dm_agent_burst_adapter:source0_endofpacket -> intel_niosv_g_dm_agent_agent:cp_endofpacket
	wire          cmd_mux_003_src_valid;                                                // cmd_mux_003:src_valid -> timer_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_003_src_data;                                                 // cmd_mux_003:src_data -> timer_s1_burst_adapter:sink0_data
	wire          cmd_mux_003_src_ready;                                                // timer_s1_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
	wire   [13:0] cmd_mux_003_src_channel;                                              // cmd_mux_003:src_channel -> timer_s1_burst_adapter:sink0_channel
	wire          cmd_mux_003_src_startofpacket;                                        // cmd_mux_003:src_startofpacket -> timer_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                          // cmd_mux_003:src_endofpacket -> timer_s1_burst_adapter:sink0_endofpacket
	wire          timer_s1_burst_adapter_source0_valid;                                 // timer_s1_burst_adapter:source0_valid -> timer_s1_agent:cp_valid
	wire  [145:0] timer_s1_burst_adapter_source0_data;                                  // timer_s1_burst_adapter:source0_data -> timer_s1_agent:cp_data
	wire          timer_s1_burst_adapter_source0_ready;                                 // timer_s1_agent:cp_ready -> timer_s1_burst_adapter:source0_ready
	wire   [13:0] timer_s1_burst_adapter_source0_channel;                               // timer_s1_burst_adapter:source0_channel -> timer_s1_agent:cp_channel
	wire          timer_s1_burst_adapter_source0_startofpacket;                         // timer_s1_burst_adapter:source0_startofpacket -> timer_s1_agent:cp_startofpacket
	wire          timer_s1_burst_adapter_source0_endofpacket;                           // timer_s1_burst_adapter:source0_endofpacket -> timer_s1_agent:cp_endofpacket
	wire          cmd_mux_004_src_valid;                                                // cmd_mux_004:src_valid -> board_info_power_in_voltage_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_004_src_data;                                                 // cmd_mux_004:src_data -> board_info_power_in_voltage_s1_burst_adapter:sink0_data
	wire          cmd_mux_004_src_ready;                                                // board_info_power_in_voltage_s1_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
	wire   [13:0] cmd_mux_004_src_channel;                                              // cmd_mux_004:src_channel -> board_info_power_in_voltage_s1_burst_adapter:sink0_channel
	wire          cmd_mux_004_src_startofpacket;                                        // cmd_mux_004:src_startofpacket -> board_info_power_in_voltage_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_004_src_endofpacket;                                          // cmd_mux_004:src_endofpacket -> board_info_power_in_voltage_s1_burst_adapter:sink0_endofpacket
	wire          board_info_power_in_voltage_s1_burst_adapter_source0_valid;           // board_info_power_in_voltage_s1_burst_adapter:source0_valid -> board_info_power_in_voltage_s1_agent:cp_valid
	wire  [145:0] board_info_power_in_voltage_s1_burst_adapter_source0_data;            // board_info_power_in_voltage_s1_burst_adapter:source0_data -> board_info_power_in_voltage_s1_agent:cp_data
	wire          board_info_power_in_voltage_s1_burst_adapter_source0_ready;           // board_info_power_in_voltage_s1_agent:cp_ready -> board_info_power_in_voltage_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_power_in_voltage_s1_burst_adapter_source0_channel;         // board_info_power_in_voltage_s1_burst_adapter:source0_channel -> board_info_power_in_voltage_s1_agent:cp_channel
	wire          board_info_power_in_voltage_s1_burst_adapter_source0_startofpacket;   // board_info_power_in_voltage_s1_burst_adapter:source0_startofpacket -> board_info_power_in_voltage_s1_agent:cp_startofpacket
	wire          board_info_power_in_voltage_s1_burst_adapter_source0_endofpacket;     // board_info_power_in_voltage_s1_burst_adapter:source0_endofpacket -> board_info_power_in_voltage_s1_agent:cp_endofpacket
	wire          cmd_mux_005_src_valid;                                                // cmd_mux_005:src_valid -> board_info_vcc1p2_voltage_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_005_src_data;                                                 // cmd_mux_005:src_data -> board_info_vcc1p2_voltage_s1_burst_adapter:sink0_data
	wire          cmd_mux_005_src_ready;                                                // board_info_vcc1p2_voltage_s1_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
	wire   [13:0] cmd_mux_005_src_channel;                                              // cmd_mux_005:src_channel -> board_info_vcc1p2_voltage_s1_burst_adapter:sink0_channel
	wire          cmd_mux_005_src_startofpacket;                                        // cmd_mux_005:src_startofpacket -> board_info_vcc1p2_voltage_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_005_src_endofpacket;                                          // cmd_mux_005:src_endofpacket -> board_info_vcc1p2_voltage_s1_burst_adapter:sink0_endofpacket
	wire          board_info_vcc1p2_voltage_s1_burst_adapter_source0_valid;             // board_info_vcc1p2_voltage_s1_burst_adapter:source0_valid -> board_info_vcc1p2_voltage_s1_agent:cp_valid
	wire  [145:0] board_info_vcc1p2_voltage_s1_burst_adapter_source0_data;              // board_info_vcc1p2_voltage_s1_burst_adapter:source0_data -> board_info_vcc1p2_voltage_s1_agent:cp_data
	wire          board_info_vcc1p2_voltage_s1_burst_adapter_source0_ready;             // board_info_vcc1p2_voltage_s1_agent:cp_ready -> board_info_vcc1p2_voltage_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_vcc1p2_voltage_s1_burst_adapter_source0_channel;           // board_info_vcc1p2_voltage_s1_burst_adapter:source0_channel -> board_info_vcc1p2_voltage_s1_agent:cp_channel
	wire          board_info_vcc1p2_voltage_s1_burst_adapter_source0_startofpacket;     // board_info_vcc1p2_voltage_s1_burst_adapter:source0_startofpacket -> board_info_vcc1p2_voltage_s1_agent:cp_startofpacket
	wire          board_info_vcc1p2_voltage_s1_burst_adapter_source0_endofpacket;       // board_info_vcc1p2_voltage_s1_burst_adapter:source0_endofpacket -> board_info_vcc1p2_voltage_s1_agent:cp_endofpacket
	wire          cmd_mux_006_src_valid;                                                // cmd_mux_006:src_valid -> board_info_vcc1p2_current_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_006_src_data;                                                 // cmd_mux_006:src_data -> board_info_vcc1p2_current_s1_burst_adapter:sink0_data
	wire          cmd_mux_006_src_ready;                                                // board_info_vcc1p2_current_s1_burst_adapter:sink0_ready -> cmd_mux_006:src_ready
	wire   [13:0] cmd_mux_006_src_channel;                                              // cmd_mux_006:src_channel -> board_info_vcc1p2_current_s1_burst_adapter:sink0_channel
	wire          cmd_mux_006_src_startofpacket;                                        // cmd_mux_006:src_startofpacket -> board_info_vcc1p2_current_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_006_src_endofpacket;                                          // cmd_mux_006:src_endofpacket -> board_info_vcc1p2_current_s1_burst_adapter:sink0_endofpacket
	wire          board_info_vcc1p2_current_s1_burst_adapter_source0_valid;             // board_info_vcc1p2_current_s1_burst_adapter:source0_valid -> board_info_vcc1p2_current_s1_agent:cp_valid
	wire  [145:0] board_info_vcc1p2_current_s1_burst_adapter_source0_data;              // board_info_vcc1p2_current_s1_burst_adapter:source0_data -> board_info_vcc1p2_current_s1_agent:cp_data
	wire          board_info_vcc1p2_current_s1_burst_adapter_source0_ready;             // board_info_vcc1p2_current_s1_agent:cp_ready -> board_info_vcc1p2_current_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_vcc1p2_current_s1_burst_adapter_source0_channel;           // board_info_vcc1p2_current_s1_burst_adapter:source0_channel -> board_info_vcc1p2_current_s1_agent:cp_channel
	wire          board_info_vcc1p2_current_s1_burst_adapter_source0_startofpacket;     // board_info_vcc1p2_current_s1_burst_adapter:source0_startofpacket -> board_info_vcc1p2_current_s1_agent:cp_startofpacket
	wire          board_info_vcc1p2_current_s1_burst_adapter_source0_endofpacket;       // board_info_vcc1p2_current_s1_burst_adapter:source0_endofpacket -> board_info_vcc1p2_current_s1_agent:cp_endofpacket
	wire          cmd_mux_007_src_valid;                                                // cmd_mux_007:src_valid -> board_info_fan_speed_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_007_src_data;                                                 // cmd_mux_007:src_data -> board_info_fan_speed_s1_burst_adapter:sink0_data
	wire          cmd_mux_007_src_ready;                                                // board_info_fan_speed_s1_burst_adapter:sink0_ready -> cmd_mux_007:src_ready
	wire   [13:0] cmd_mux_007_src_channel;                                              // cmd_mux_007:src_channel -> board_info_fan_speed_s1_burst_adapter:sink0_channel
	wire          cmd_mux_007_src_startofpacket;                                        // cmd_mux_007:src_startofpacket -> board_info_fan_speed_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_007_src_endofpacket;                                          // cmd_mux_007:src_endofpacket -> board_info_fan_speed_s1_burst_adapter:sink0_endofpacket
	wire          board_info_fan_speed_s1_burst_adapter_source0_valid;                  // board_info_fan_speed_s1_burst_adapter:source0_valid -> board_info_fan_speed_s1_agent:cp_valid
	wire  [145:0] board_info_fan_speed_s1_burst_adapter_source0_data;                   // board_info_fan_speed_s1_burst_adapter:source0_data -> board_info_fan_speed_s1_agent:cp_data
	wire          board_info_fan_speed_s1_burst_adapter_source0_ready;                  // board_info_fan_speed_s1_agent:cp_ready -> board_info_fan_speed_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_fan_speed_s1_burst_adapter_source0_channel;                // board_info_fan_speed_s1_burst_adapter:source0_channel -> board_info_fan_speed_s1_agent:cp_channel
	wire          board_info_fan_speed_s1_burst_adapter_source0_startofpacket;          // board_info_fan_speed_s1_burst_adapter:source0_startofpacket -> board_info_fan_speed_s1_agent:cp_startofpacket
	wire          board_info_fan_speed_s1_burst_adapter_source0_endofpacket;            // board_info_fan_speed_s1_burst_adapter:source0_endofpacket -> board_info_fan_speed_s1_agent:cp_endofpacket
	wire          cmd_mux_008_src_valid;                                                // cmd_mux_008:src_valid -> board_info_temperature_fpga_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_008_src_data;                                                 // cmd_mux_008:src_data -> board_info_temperature_fpga_s1_burst_adapter:sink0_data
	wire          cmd_mux_008_src_ready;                                                // board_info_temperature_fpga_s1_burst_adapter:sink0_ready -> cmd_mux_008:src_ready
	wire   [13:0] cmd_mux_008_src_channel;                                              // cmd_mux_008:src_channel -> board_info_temperature_fpga_s1_burst_adapter:sink0_channel
	wire          cmd_mux_008_src_startofpacket;                                        // cmd_mux_008:src_startofpacket -> board_info_temperature_fpga_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_008_src_endofpacket;                                          // cmd_mux_008:src_endofpacket -> board_info_temperature_fpga_s1_burst_adapter:sink0_endofpacket
	wire          board_info_temperature_fpga_s1_burst_adapter_source0_valid;           // board_info_temperature_fpga_s1_burst_adapter:source0_valid -> board_info_temperature_fpga_s1_agent:cp_valid
	wire  [145:0] board_info_temperature_fpga_s1_burst_adapter_source0_data;            // board_info_temperature_fpga_s1_burst_adapter:source0_data -> board_info_temperature_fpga_s1_agent:cp_data
	wire          board_info_temperature_fpga_s1_burst_adapter_source0_ready;           // board_info_temperature_fpga_s1_agent:cp_ready -> board_info_temperature_fpga_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_temperature_fpga_s1_burst_adapter_source0_channel;         // board_info_temperature_fpga_s1_burst_adapter:source0_channel -> board_info_temperature_fpga_s1_agent:cp_channel
	wire          board_info_temperature_fpga_s1_burst_adapter_source0_startofpacket;   // board_info_temperature_fpga_s1_burst_adapter:source0_startofpacket -> board_info_temperature_fpga_s1_agent:cp_startofpacket
	wire          board_info_temperature_fpga_s1_burst_adapter_source0_endofpacket;     // board_info_temperature_fpga_s1_burst_adapter:source0_endofpacket -> board_info_temperature_fpga_s1_agent:cp_endofpacket
	wire          cmd_mux_009_src_valid;                                                // cmd_mux_009:src_valid -> board_info_temperature_board1_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_009_src_data;                                                 // cmd_mux_009:src_data -> board_info_temperature_board1_s1_burst_adapter:sink0_data
	wire          cmd_mux_009_src_ready;                                                // board_info_temperature_board1_s1_burst_adapter:sink0_ready -> cmd_mux_009:src_ready
	wire   [13:0] cmd_mux_009_src_channel;                                              // cmd_mux_009:src_channel -> board_info_temperature_board1_s1_burst_adapter:sink0_channel
	wire          cmd_mux_009_src_startofpacket;                                        // cmd_mux_009:src_startofpacket -> board_info_temperature_board1_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_009_src_endofpacket;                                          // cmd_mux_009:src_endofpacket -> board_info_temperature_board1_s1_burst_adapter:sink0_endofpacket
	wire          board_info_temperature_board1_s1_burst_adapter_source0_valid;         // board_info_temperature_board1_s1_burst_adapter:source0_valid -> board_info_temperature_board1_s1_agent:cp_valid
	wire  [145:0] board_info_temperature_board1_s1_burst_adapter_source0_data;          // board_info_temperature_board1_s1_burst_adapter:source0_data -> board_info_temperature_board1_s1_agent:cp_data
	wire          board_info_temperature_board1_s1_burst_adapter_source0_ready;         // board_info_temperature_board1_s1_agent:cp_ready -> board_info_temperature_board1_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_temperature_board1_s1_burst_adapter_source0_channel;       // board_info_temperature_board1_s1_burst_adapter:source0_channel -> board_info_temperature_board1_s1_agent:cp_channel
	wire          board_info_temperature_board1_s1_burst_adapter_source0_startofpacket; // board_info_temperature_board1_s1_burst_adapter:source0_startofpacket -> board_info_temperature_board1_s1_agent:cp_startofpacket
	wire          board_info_temperature_board1_s1_burst_adapter_source0_endofpacket;   // board_info_temperature_board1_s1_burst_adapter:source0_endofpacket -> board_info_temperature_board1_s1_agent:cp_endofpacket
	wire          cmd_mux_010_src_valid;                                                // cmd_mux_010:src_valid -> board_info_pin_status_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_010_src_data;                                                 // cmd_mux_010:src_data -> board_info_pin_status_s1_burst_adapter:sink0_data
	wire          cmd_mux_010_src_ready;                                                // board_info_pin_status_s1_burst_adapter:sink0_ready -> cmd_mux_010:src_ready
	wire   [13:0] cmd_mux_010_src_channel;                                              // cmd_mux_010:src_channel -> board_info_pin_status_s1_burst_adapter:sink0_channel
	wire          cmd_mux_010_src_startofpacket;                                        // cmd_mux_010:src_startofpacket -> board_info_pin_status_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_010_src_endofpacket;                                          // cmd_mux_010:src_endofpacket -> board_info_pin_status_s1_burst_adapter:sink0_endofpacket
	wire          board_info_pin_status_s1_burst_adapter_source0_valid;                 // board_info_pin_status_s1_burst_adapter:source0_valid -> board_info_pin_status_s1_agent:cp_valid
	wire  [145:0] board_info_pin_status_s1_burst_adapter_source0_data;                  // board_info_pin_status_s1_burst_adapter:source0_data -> board_info_pin_status_s1_agent:cp_data
	wire          board_info_pin_status_s1_burst_adapter_source0_ready;                 // board_info_pin_status_s1_agent:cp_ready -> board_info_pin_status_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_pin_status_s1_burst_adapter_source0_channel;               // board_info_pin_status_s1_burst_adapter:source0_channel -> board_info_pin_status_s1_agent:cp_channel
	wire          board_info_pin_status_s1_burst_adapter_source0_startofpacket;         // board_info_pin_status_s1_burst_adapter:source0_startofpacket -> board_info_pin_status_s1_agent:cp_startofpacket
	wire          board_info_pin_status_s1_burst_adapter_source0_endofpacket;           // board_info_pin_status_s1_burst_adapter:source0_endofpacket -> board_info_pin_status_s1_agent:cp_endofpacket
	wire          cmd_mux_011_src_valid;                                                // cmd_mux_011:src_valid -> board_info_temperature_board2_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_011_src_data;                                                 // cmd_mux_011:src_data -> board_info_temperature_board2_s1_burst_adapter:sink0_data
	wire          cmd_mux_011_src_ready;                                                // board_info_temperature_board2_s1_burst_adapter:sink0_ready -> cmd_mux_011:src_ready
	wire   [13:0] cmd_mux_011_src_channel;                                              // cmd_mux_011:src_channel -> board_info_temperature_board2_s1_burst_adapter:sink0_channel
	wire          cmd_mux_011_src_startofpacket;                                        // cmd_mux_011:src_startofpacket -> board_info_temperature_board2_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_011_src_endofpacket;                                          // cmd_mux_011:src_endofpacket -> board_info_temperature_board2_s1_burst_adapter:sink0_endofpacket
	wire          board_info_temperature_board2_s1_burst_adapter_source0_valid;         // board_info_temperature_board2_s1_burst_adapter:source0_valid -> board_info_temperature_board2_s1_agent:cp_valid
	wire  [145:0] board_info_temperature_board2_s1_burst_adapter_source0_data;          // board_info_temperature_board2_s1_burst_adapter:source0_data -> board_info_temperature_board2_s1_agent:cp_data
	wire          board_info_temperature_board2_s1_burst_adapter_source0_ready;         // board_info_temperature_board2_s1_agent:cp_ready -> board_info_temperature_board2_s1_burst_adapter:source0_ready
	wire   [13:0] board_info_temperature_board2_s1_burst_adapter_source0_channel;       // board_info_temperature_board2_s1_burst_adapter:source0_channel -> board_info_temperature_board2_s1_agent:cp_channel
	wire          board_info_temperature_board2_s1_burst_adapter_source0_startofpacket; // board_info_temperature_board2_s1_burst_adapter:source0_startofpacket -> board_info_temperature_board2_s1_agent:cp_startofpacket
	wire          board_info_temperature_board2_s1_burst_adapter_source0_endofpacket;   // board_info_temperature_board2_s1_burst_adapter:source0_endofpacket -> board_info_temperature_board2_s1_agent:cp_endofpacket
	wire          cmd_mux_012_src_valid;                                                // cmd_mux_012:src_valid -> intel_onchip_memory_s1_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_012_src_data;                                                 // cmd_mux_012:src_data -> intel_onchip_memory_s1_burst_adapter:sink0_data
	wire          cmd_mux_012_src_ready;                                                // intel_onchip_memory_s1_burst_adapter:sink0_ready -> cmd_mux_012:src_ready
	wire   [13:0] cmd_mux_012_src_channel;                                              // cmd_mux_012:src_channel -> intel_onchip_memory_s1_burst_adapter:sink0_channel
	wire          cmd_mux_012_src_startofpacket;                                        // cmd_mux_012:src_startofpacket -> intel_onchip_memory_s1_burst_adapter:sink0_startofpacket
	wire          cmd_mux_012_src_endofpacket;                                          // cmd_mux_012:src_endofpacket -> intel_onchip_memory_s1_burst_adapter:sink0_endofpacket
	wire          intel_onchip_memory_s1_burst_adapter_source0_valid;                   // intel_onchip_memory_s1_burst_adapter:source0_valid -> intel_onchip_memory_s1_agent:cp_valid
	wire  [145:0] intel_onchip_memory_s1_burst_adapter_source0_data;                    // intel_onchip_memory_s1_burst_adapter:source0_data -> intel_onchip_memory_s1_agent:cp_data
	wire          intel_onchip_memory_s1_burst_adapter_source0_ready;                   // intel_onchip_memory_s1_agent:cp_ready -> intel_onchip_memory_s1_burst_adapter:source0_ready
	wire   [13:0] intel_onchip_memory_s1_burst_adapter_source0_channel;                 // intel_onchip_memory_s1_burst_adapter:source0_channel -> intel_onchip_memory_s1_agent:cp_channel
	wire          intel_onchip_memory_s1_burst_adapter_source0_startofpacket;           // intel_onchip_memory_s1_burst_adapter:source0_startofpacket -> intel_onchip_memory_s1_agent:cp_startofpacket
	wire          intel_onchip_memory_s1_burst_adapter_source0_endofpacket;             // intel_onchip_memory_s1_burst_adapter:source0_endofpacket -> intel_onchip_memory_s1_agent:cp_endofpacket
	wire          cmd_mux_013_src_valid;                                                // cmd_mux_013:src_valid -> intel_niosv_g_timer_sw_agent_burst_adapter:sink0_valid
	wire  [145:0] cmd_mux_013_src_data;                                                 // cmd_mux_013:src_data -> intel_niosv_g_timer_sw_agent_burst_adapter:sink0_data
	wire          cmd_mux_013_src_ready;                                                // intel_niosv_g_timer_sw_agent_burst_adapter:sink0_ready -> cmd_mux_013:src_ready
	wire   [13:0] cmd_mux_013_src_channel;                                              // cmd_mux_013:src_channel -> intel_niosv_g_timer_sw_agent_burst_adapter:sink0_channel
	wire          cmd_mux_013_src_startofpacket;                                        // cmd_mux_013:src_startofpacket -> intel_niosv_g_timer_sw_agent_burst_adapter:sink0_startofpacket
	wire          cmd_mux_013_src_endofpacket;                                          // cmd_mux_013:src_endofpacket -> intel_niosv_g_timer_sw_agent_burst_adapter:sink0_endofpacket
	wire          intel_niosv_g_timer_sw_agent_burst_adapter_source0_valid;             // intel_niosv_g_timer_sw_agent_burst_adapter:source0_valid -> intel_niosv_g_timer_sw_agent_agent:cp_valid
	wire  [145:0] intel_niosv_g_timer_sw_agent_burst_adapter_source0_data;              // intel_niosv_g_timer_sw_agent_burst_adapter:source0_data -> intel_niosv_g_timer_sw_agent_agent:cp_data
	wire          intel_niosv_g_timer_sw_agent_burst_adapter_source0_ready;             // intel_niosv_g_timer_sw_agent_agent:cp_ready -> intel_niosv_g_timer_sw_agent_burst_adapter:source0_ready
	wire   [13:0] intel_niosv_g_timer_sw_agent_burst_adapter_source0_channel;           // intel_niosv_g_timer_sw_agent_burst_adapter:source0_channel -> intel_niosv_g_timer_sw_agent_agent:cp_channel
	wire          intel_niosv_g_timer_sw_agent_burst_adapter_source0_startofpacket;     // intel_niosv_g_timer_sw_agent_burst_adapter:source0_startofpacket -> intel_niosv_g_timer_sw_agent_agent:cp_startofpacket
	wire          intel_niosv_g_timer_sw_agent_burst_adapter_source0_endofpacket;       // intel_niosv_g_timer_sw_agent_burst_adapter:source0_endofpacket -> intel_niosv_g_timer_sw_agent_agent:cp_endofpacket
	wire          cmd_demux_src0_valid;                                                 // cmd_demux:src0_valid -> cmd_mux:sink0_valid
	wire  [145:0] cmd_demux_src0_data;                                                  // cmd_demux:src0_data -> cmd_mux:sink0_data
	wire          cmd_demux_src0_ready;                                                 // cmd_mux:sink0_ready -> cmd_demux:src0_ready
	wire   [13:0] cmd_demux_src0_channel;                                               // cmd_demux:src0_channel -> cmd_mux:sink0_channel
	wire          cmd_demux_src0_startofpacket;                                         // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	wire          cmd_demux_src0_endofpacket;                                           // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                 // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	wire  [145:0] cmd_demux_src1_data;                                                  // cmd_demux:src1_data -> cmd_mux_001:sink0_data
	wire          cmd_demux_src1_ready;                                                 // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	wire   [13:0] cmd_demux_src1_channel;                                               // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	wire          cmd_demux_src1_startofpacket;                                         // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          cmd_demux_src1_endofpacket;                                           // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_src2_valid;                                                 // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	wire  [145:0] cmd_demux_src2_data;                                                  // cmd_demux:src2_data -> cmd_mux_002:sink0_data
	wire          cmd_demux_src2_ready;                                                 // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	wire   [13:0] cmd_demux_src2_channel;                                               // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	wire          cmd_demux_src2_startofpacket;                                         // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          cmd_demux_src2_endofpacket;                                           // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_src3_valid;                                                 // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
	wire  [145:0] cmd_demux_src3_data;                                                  // cmd_demux:src3_data -> cmd_mux_003:sink0_data
	wire          cmd_demux_src3_ready;                                                 // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
	wire   [13:0] cmd_demux_src3_channel;                                               // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
	wire          cmd_demux_src3_startofpacket;                                         // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          cmd_demux_src3_endofpacket;                                           // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_src4_valid;                                                 // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
	wire  [145:0] cmd_demux_src4_data;                                                  // cmd_demux:src4_data -> cmd_mux_004:sink0_data
	wire          cmd_demux_src4_ready;                                                 // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
	wire   [13:0] cmd_demux_src4_channel;                                               // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
	wire          cmd_demux_src4_startofpacket;                                         // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
	wire          cmd_demux_src4_endofpacket;                                           // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
	wire          cmd_demux_src5_valid;                                                 // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
	wire  [145:0] cmd_demux_src5_data;                                                  // cmd_demux:src5_data -> cmd_mux_005:sink0_data
	wire          cmd_demux_src5_ready;                                                 // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
	wire   [13:0] cmd_demux_src5_channel;                                               // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
	wire          cmd_demux_src5_startofpacket;                                         // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
	wire          cmd_demux_src5_endofpacket;                                           // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
	wire          cmd_demux_src6_valid;                                                 // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
	wire  [145:0] cmd_demux_src6_data;                                                  // cmd_demux:src6_data -> cmd_mux_006:sink0_data
	wire          cmd_demux_src6_ready;                                                 // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
	wire   [13:0] cmd_demux_src6_channel;                                               // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
	wire          cmd_demux_src6_startofpacket;                                         // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
	wire          cmd_demux_src6_endofpacket;                                           // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
	wire          cmd_demux_src7_valid;                                                 // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
	wire  [145:0] cmd_demux_src7_data;                                                  // cmd_demux:src7_data -> cmd_mux_007:sink0_data
	wire          cmd_demux_src7_ready;                                                 // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
	wire   [13:0] cmd_demux_src7_channel;                                               // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
	wire          cmd_demux_src7_startofpacket;                                         // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
	wire          cmd_demux_src7_endofpacket;                                           // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
	wire          cmd_demux_src8_valid;                                                 // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
	wire  [145:0] cmd_demux_src8_data;                                                  // cmd_demux:src8_data -> cmd_mux_008:sink0_data
	wire          cmd_demux_src8_ready;                                                 // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
	wire   [13:0] cmd_demux_src8_channel;                                               // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
	wire          cmd_demux_src8_startofpacket;                                         // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
	wire          cmd_demux_src8_endofpacket;                                           // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
	wire          cmd_demux_src9_valid;                                                 // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
	wire  [145:0] cmd_demux_src9_data;                                                  // cmd_demux:src9_data -> cmd_mux_009:sink0_data
	wire          cmd_demux_src9_ready;                                                 // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
	wire   [13:0] cmd_demux_src9_channel;                                               // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
	wire          cmd_demux_src9_startofpacket;                                         // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
	wire          cmd_demux_src9_endofpacket;                                           // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
	wire          cmd_demux_src10_valid;                                                // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
	wire  [145:0] cmd_demux_src10_data;                                                 // cmd_demux:src10_data -> cmd_mux_010:sink0_data
	wire          cmd_demux_src10_ready;                                                // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
	wire   [13:0] cmd_demux_src10_channel;                                              // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
	wire          cmd_demux_src10_startofpacket;                                        // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
	wire          cmd_demux_src10_endofpacket;                                          // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
	wire          cmd_demux_src11_valid;                                                // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
	wire  [145:0] cmd_demux_src11_data;                                                 // cmd_demux:src11_data -> cmd_mux_011:sink0_data
	wire          cmd_demux_src11_ready;                                                // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
	wire   [13:0] cmd_demux_src11_channel;                                              // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
	wire          cmd_demux_src11_startofpacket;                                        // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
	wire          cmd_demux_src11_endofpacket;                                          // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
	wire          cmd_demux_src12_valid;                                                // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
	wire  [145:0] cmd_demux_src12_data;                                                 // cmd_demux:src12_data -> cmd_mux_012:sink0_data
	wire          cmd_demux_src12_ready;                                                // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
	wire   [13:0] cmd_demux_src12_channel;                                              // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
	wire          cmd_demux_src12_startofpacket;                                        // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
	wire          cmd_demux_src12_endofpacket;                                          // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
	wire          cmd_demux_src13_valid;                                                // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
	wire  [145:0] cmd_demux_src13_data;                                                 // cmd_demux:src13_data -> cmd_mux_013:sink0_data
	wire          cmd_demux_src13_ready;                                                // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
	wire   [13:0] cmd_demux_src13_channel;                                              // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
	wire          cmd_demux_src13_startofpacket;                                        // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
	wire          cmd_demux_src13_endofpacket;                                          // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                             // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
	wire  [145:0] cmd_demux_001_src0_data;                                              // cmd_demux_001:src0_data -> cmd_mux:sink1_data
	wire          cmd_demux_001_src0_ready;                                             // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
	wire   [13:0] cmd_demux_001_src0_channel;                                           // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
	wire          cmd_demux_001_src0_startofpacket;                                     // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                       // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
	wire          cmd_demux_001_src1_valid;                                             // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
	wire  [145:0] cmd_demux_001_src1_data;                                              // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
	wire          cmd_demux_001_src1_ready;                                             // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
	wire   [13:0] cmd_demux_001_src1_channel;                                           // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
	wire          cmd_demux_001_src1_startofpacket;                                     // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          cmd_demux_001_src1_endofpacket;                                       // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_001_src2_valid;                                             // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
	wire  [145:0] cmd_demux_001_src2_data;                                              // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
	wire          cmd_demux_001_src2_ready;                                             // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
	wire   [13:0] cmd_demux_001_src2_channel;                                           // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
	wire          cmd_demux_001_src2_startofpacket;                                     // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          cmd_demux_001_src2_endofpacket;                                       // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          cmd_demux_001_src3_valid;                                             // cmd_demux_001:src3_valid -> cmd_mux_003:sink1_valid
	wire  [145:0] cmd_demux_001_src3_data;                                              // cmd_demux_001:src3_data -> cmd_mux_003:sink1_data
	wire          cmd_demux_001_src3_ready;                                             // cmd_mux_003:sink1_ready -> cmd_demux_001:src3_ready
	wire   [13:0] cmd_demux_001_src3_channel;                                           // cmd_demux_001:src3_channel -> cmd_mux_003:sink1_channel
	wire          cmd_demux_001_src3_startofpacket;                                     // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire          cmd_demux_001_src3_endofpacket;                                       // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire          cmd_demux_001_src4_valid;                                             // cmd_demux_001:src4_valid -> cmd_mux_004:sink1_valid
	wire  [145:0] cmd_demux_001_src4_data;                                              // cmd_demux_001:src4_data -> cmd_mux_004:sink1_data
	wire          cmd_demux_001_src4_ready;                                             // cmd_mux_004:sink1_ready -> cmd_demux_001:src4_ready
	wire   [13:0] cmd_demux_001_src4_channel;                                           // cmd_demux_001:src4_channel -> cmd_mux_004:sink1_channel
	wire          cmd_demux_001_src4_startofpacket;                                     // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink1_startofpacket
	wire          cmd_demux_001_src4_endofpacket;                                       // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink1_endofpacket
	wire          cmd_demux_001_src5_valid;                                             // cmd_demux_001:src5_valid -> cmd_mux_005:sink1_valid
	wire  [145:0] cmd_demux_001_src5_data;                                              // cmd_demux_001:src5_data -> cmd_mux_005:sink1_data
	wire          cmd_demux_001_src5_ready;                                             // cmd_mux_005:sink1_ready -> cmd_demux_001:src5_ready
	wire   [13:0] cmd_demux_001_src5_channel;                                           // cmd_demux_001:src5_channel -> cmd_mux_005:sink1_channel
	wire          cmd_demux_001_src5_startofpacket;                                     // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink1_startofpacket
	wire          cmd_demux_001_src5_endofpacket;                                       // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink1_endofpacket
	wire          cmd_demux_001_src6_valid;                                             // cmd_demux_001:src6_valid -> cmd_mux_006:sink1_valid
	wire  [145:0] cmd_demux_001_src6_data;                                              // cmd_demux_001:src6_data -> cmd_mux_006:sink1_data
	wire          cmd_demux_001_src6_ready;                                             // cmd_mux_006:sink1_ready -> cmd_demux_001:src6_ready
	wire   [13:0] cmd_demux_001_src6_channel;                                           // cmd_demux_001:src6_channel -> cmd_mux_006:sink1_channel
	wire          cmd_demux_001_src6_startofpacket;                                     // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink1_startofpacket
	wire          cmd_demux_001_src6_endofpacket;                                       // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink1_endofpacket
	wire          cmd_demux_001_src7_valid;                                             // cmd_demux_001:src7_valid -> cmd_mux_007:sink1_valid
	wire  [145:0] cmd_demux_001_src7_data;                                              // cmd_demux_001:src7_data -> cmd_mux_007:sink1_data
	wire          cmd_demux_001_src7_ready;                                             // cmd_mux_007:sink1_ready -> cmd_demux_001:src7_ready
	wire   [13:0] cmd_demux_001_src7_channel;                                           // cmd_demux_001:src7_channel -> cmd_mux_007:sink1_channel
	wire          cmd_demux_001_src7_startofpacket;                                     // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink1_startofpacket
	wire          cmd_demux_001_src7_endofpacket;                                       // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink1_endofpacket
	wire          cmd_demux_001_src8_valid;                                             // cmd_demux_001:src8_valid -> cmd_mux_008:sink1_valid
	wire  [145:0] cmd_demux_001_src8_data;                                              // cmd_demux_001:src8_data -> cmd_mux_008:sink1_data
	wire          cmd_demux_001_src8_ready;                                             // cmd_mux_008:sink1_ready -> cmd_demux_001:src8_ready
	wire   [13:0] cmd_demux_001_src8_channel;                                           // cmd_demux_001:src8_channel -> cmd_mux_008:sink1_channel
	wire          cmd_demux_001_src8_startofpacket;                                     // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink1_startofpacket
	wire          cmd_demux_001_src8_endofpacket;                                       // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink1_endofpacket
	wire          cmd_demux_001_src9_valid;                                             // cmd_demux_001:src9_valid -> cmd_mux_009:sink1_valid
	wire  [145:0] cmd_demux_001_src9_data;                                              // cmd_demux_001:src9_data -> cmd_mux_009:sink1_data
	wire          cmd_demux_001_src9_ready;                                             // cmd_mux_009:sink1_ready -> cmd_demux_001:src9_ready
	wire   [13:0] cmd_demux_001_src9_channel;                                           // cmd_demux_001:src9_channel -> cmd_mux_009:sink1_channel
	wire          cmd_demux_001_src9_startofpacket;                                     // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink1_startofpacket
	wire          cmd_demux_001_src9_endofpacket;                                       // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink1_endofpacket
	wire          cmd_demux_001_src10_valid;                                            // cmd_demux_001:src10_valid -> cmd_mux_010:sink1_valid
	wire  [145:0] cmd_demux_001_src10_data;                                             // cmd_demux_001:src10_data -> cmd_mux_010:sink1_data
	wire          cmd_demux_001_src10_ready;                                            // cmd_mux_010:sink1_ready -> cmd_demux_001:src10_ready
	wire   [13:0] cmd_demux_001_src10_channel;                                          // cmd_demux_001:src10_channel -> cmd_mux_010:sink1_channel
	wire          cmd_demux_001_src10_startofpacket;                                    // cmd_demux_001:src10_startofpacket -> cmd_mux_010:sink1_startofpacket
	wire          cmd_demux_001_src10_endofpacket;                                      // cmd_demux_001:src10_endofpacket -> cmd_mux_010:sink1_endofpacket
	wire          cmd_demux_001_src11_valid;                                            // cmd_demux_001:src11_valid -> cmd_mux_011:sink1_valid
	wire  [145:0] cmd_demux_001_src11_data;                                             // cmd_demux_001:src11_data -> cmd_mux_011:sink1_data
	wire          cmd_demux_001_src11_ready;                                            // cmd_mux_011:sink1_ready -> cmd_demux_001:src11_ready
	wire   [13:0] cmd_demux_001_src11_channel;                                          // cmd_demux_001:src11_channel -> cmd_mux_011:sink1_channel
	wire          cmd_demux_001_src11_startofpacket;                                    // cmd_demux_001:src11_startofpacket -> cmd_mux_011:sink1_startofpacket
	wire          cmd_demux_001_src11_endofpacket;                                      // cmd_demux_001:src11_endofpacket -> cmd_mux_011:sink1_endofpacket
	wire          cmd_demux_001_src12_valid;                                            // cmd_demux_001:src12_valid -> cmd_mux_012:sink1_valid
	wire  [145:0] cmd_demux_001_src12_data;                                             // cmd_demux_001:src12_data -> cmd_mux_012:sink1_data
	wire          cmd_demux_001_src12_ready;                                            // cmd_mux_012:sink1_ready -> cmd_demux_001:src12_ready
	wire   [13:0] cmd_demux_001_src12_channel;                                          // cmd_demux_001:src12_channel -> cmd_mux_012:sink1_channel
	wire          cmd_demux_001_src12_startofpacket;                                    // cmd_demux_001:src12_startofpacket -> cmd_mux_012:sink1_startofpacket
	wire          cmd_demux_001_src12_endofpacket;                                      // cmd_demux_001:src12_endofpacket -> cmd_mux_012:sink1_endofpacket
	wire          cmd_demux_001_src13_valid;                                            // cmd_demux_001:src13_valid -> cmd_mux_013:sink1_valid
	wire  [145:0] cmd_demux_001_src13_data;                                             // cmd_demux_001:src13_data -> cmd_mux_013:sink1_data
	wire          cmd_demux_001_src13_ready;                                            // cmd_mux_013:sink1_ready -> cmd_demux_001:src13_ready
	wire   [13:0] cmd_demux_001_src13_channel;                                          // cmd_demux_001:src13_channel -> cmd_mux_013:sink1_channel
	wire          cmd_demux_001_src13_startofpacket;                                    // cmd_demux_001:src13_startofpacket -> cmd_mux_013:sink1_startofpacket
	wire          cmd_demux_001_src13_endofpacket;                                      // cmd_demux_001:src13_endofpacket -> cmd_mux_013:sink1_endofpacket
	wire          cmd_demux_002_src0_valid;                                             // cmd_demux_002:src0_valid -> cmd_mux_002:sink2_valid
	wire  [145:0] cmd_demux_002_src0_data;                                              // cmd_demux_002:src0_data -> cmd_mux_002:sink2_data
	wire          cmd_demux_002_src0_ready;                                             // cmd_mux_002:sink2_ready -> cmd_demux_002:src0_ready
	wire   [13:0] cmd_demux_002_src0_channel;                                           // cmd_demux_002:src0_channel -> cmd_mux_002:sink2_channel
	wire          cmd_demux_002_src0_startofpacket;                                     // cmd_demux_002:src0_startofpacket -> cmd_mux_002:sink2_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                       // cmd_demux_002:src0_endofpacket -> cmd_mux_002:sink2_endofpacket
	wire          cmd_demux_002_src1_valid;                                             // cmd_demux_002:src1_valid -> cmd_mux_012:sink2_valid
	wire  [145:0] cmd_demux_002_src1_data;                                              // cmd_demux_002:src1_data -> cmd_mux_012:sink2_data
	wire          cmd_demux_002_src1_ready;                                             // cmd_mux_012:sink2_ready -> cmd_demux_002:src1_ready
	wire   [13:0] cmd_demux_002_src1_channel;                                           // cmd_demux_002:src1_channel -> cmd_mux_012:sink2_channel
	wire          cmd_demux_002_src1_startofpacket;                                     // cmd_demux_002:src1_startofpacket -> cmd_mux_012:sink2_startofpacket
	wire          cmd_demux_002_src1_endofpacket;                                       // cmd_demux_002:src1_endofpacket -> cmd_mux_012:sink2_endofpacket
	wire          cmd_demux_003_src0_valid;                                             // cmd_demux_003:src0_valid -> cmd_mux_002:sink3_valid
	wire  [145:0] cmd_demux_003_src0_data;                                              // cmd_demux_003:src0_data -> cmd_mux_002:sink3_data
	wire          cmd_demux_003_src0_ready;                                             // cmd_mux_002:sink3_ready -> cmd_demux_003:src0_ready
	wire   [13:0] cmd_demux_003_src0_channel;                                           // cmd_demux_003:src0_channel -> cmd_mux_002:sink3_channel
	wire          cmd_demux_003_src0_startofpacket;                                     // cmd_demux_003:src0_startofpacket -> cmd_mux_002:sink3_startofpacket
	wire          cmd_demux_003_src0_endofpacket;                                       // cmd_demux_003:src0_endofpacket -> cmd_mux_002:sink3_endofpacket
	wire          cmd_demux_003_src1_valid;                                             // cmd_demux_003:src1_valid -> cmd_mux_012:sink3_valid
	wire  [145:0] cmd_demux_003_src1_data;                                              // cmd_demux_003:src1_data -> cmd_mux_012:sink3_data
	wire          cmd_demux_003_src1_ready;                                             // cmd_mux_012:sink3_ready -> cmd_demux_003:src1_ready
	wire   [13:0] cmd_demux_003_src1_channel;                                           // cmd_demux_003:src1_channel -> cmd_mux_012:sink3_channel
	wire          cmd_demux_003_src1_startofpacket;                                     // cmd_demux_003:src1_startofpacket -> cmd_mux_012:sink3_startofpacket
	wire          cmd_demux_003_src1_endofpacket;                                       // cmd_demux_003:src1_endofpacket -> cmd_mux_012:sink3_endofpacket
	wire          rsp_demux_src0_valid;                                                 // rsp_demux:src0_valid -> rsp_mux:sink0_valid
	wire  [145:0] rsp_demux_src0_data;                                                  // rsp_demux:src0_data -> rsp_mux:sink0_data
	wire          rsp_demux_src0_ready;                                                 // rsp_mux:sink0_ready -> rsp_demux:src0_ready
	wire   [13:0] rsp_demux_src0_channel;                                               // rsp_demux:src0_channel -> rsp_mux:sink0_channel
	wire          rsp_demux_src0_startofpacket;                                         // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	wire          rsp_demux_src0_endofpacket;                                           // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_src1_valid;                                                 // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
	wire  [145:0] rsp_demux_src1_data;                                                  // rsp_demux:src1_data -> rsp_mux_001:sink0_data
	wire          rsp_demux_src1_ready;                                                 // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
	wire   [13:0] rsp_demux_src1_channel;                                               // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
	wire          rsp_demux_src1_startofpacket;                                         // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          rsp_demux_src1_endofpacket;                                           // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                             // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	wire  [145:0] rsp_demux_001_src0_data;                                              // rsp_demux_001:src0_data -> rsp_mux:sink1_data
	wire          rsp_demux_001_src0_ready;                                             // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	wire   [13:0] rsp_demux_001_src0_channel;                                           // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	wire          rsp_demux_001_src0_startofpacket;                                     // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                       // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_001_src1_valid;                                             // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
	wire  [145:0] rsp_demux_001_src1_data;                                              // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
	wire          rsp_demux_001_src1_ready;                                             // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
	wire   [13:0] rsp_demux_001_src1_channel;                                           // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
	wire          rsp_demux_001_src1_startofpacket;                                     // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                       // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                             // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	wire  [145:0] rsp_demux_002_src0_data;                                              // rsp_demux_002:src0_data -> rsp_mux:sink2_data
	wire          rsp_demux_002_src0_ready;                                             // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	wire   [13:0] rsp_demux_002_src0_channel;                                           // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	wire          rsp_demux_002_src0_startofpacket;                                     // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                       // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_002_src1_valid;                                             // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
	wire  [145:0] rsp_demux_002_src1_data;                                              // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
	wire          rsp_demux_002_src1_ready;                                             // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
	wire   [13:0] rsp_demux_002_src1_channel;                                           // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
	wire          rsp_demux_002_src1_startofpacket;                                     // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                                       // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
	wire          rsp_demux_002_src2_valid;                                             // rsp_demux_002:src2_valid -> rsp_mux_002:sink0_valid
	wire  [145:0] rsp_demux_002_src2_data;                                              // rsp_demux_002:src2_data -> rsp_mux_002:sink0_data
	wire          rsp_demux_002_src2_ready;                                             // rsp_mux_002:sink0_ready -> rsp_demux_002:src2_ready
	wire   [13:0] rsp_demux_002_src2_channel;                                           // rsp_demux_002:src2_channel -> rsp_mux_002:sink0_channel
	wire          rsp_demux_002_src2_startofpacket;                                     // rsp_demux_002:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          rsp_demux_002_src2_endofpacket;                                       // rsp_demux_002:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire          rsp_demux_002_src3_valid;                                             // rsp_demux_002:src3_valid -> rsp_mux_003:sink0_valid
	wire  [145:0] rsp_demux_002_src3_data;                                              // rsp_demux_002:src3_data -> rsp_mux_003:sink0_data
	wire          rsp_demux_002_src3_ready;                                             // rsp_mux_003:sink0_ready -> rsp_demux_002:src3_ready
	wire   [13:0] rsp_demux_002_src3_channel;                                           // rsp_demux_002:src3_channel -> rsp_mux_003:sink0_channel
	wire          rsp_demux_002_src3_startofpacket;                                     // rsp_demux_002:src3_startofpacket -> rsp_mux_003:sink0_startofpacket
	wire          rsp_demux_002_src3_endofpacket;                                       // rsp_demux_002:src3_endofpacket -> rsp_mux_003:sink0_endofpacket
	wire          rsp_demux_003_src0_valid;                                             // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
	wire  [145:0] rsp_demux_003_src0_data;                                              // rsp_demux_003:src0_data -> rsp_mux:sink3_data
	wire          rsp_demux_003_src0_ready;                                             // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
	wire   [13:0] rsp_demux_003_src0_channel;                                           // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
	wire          rsp_demux_003_src0_startofpacket;                                     // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                       // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
	wire          rsp_demux_003_src1_valid;                                             // rsp_demux_003:src1_valid -> rsp_mux_001:sink3_valid
	wire  [145:0] rsp_demux_003_src1_data;                                              // rsp_demux_003:src1_data -> rsp_mux_001:sink3_data
	wire          rsp_demux_003_src1_ready;                                             // rsp_mux_001:sink3_ready -> rsp_demux_003:src1_ready
	wire   [13:0] rsp_demux_003_src1_channel;                                           // rsp_demux_003:src1_channel -> rsp_mux_001:sink3_channel
	wire          rsp_demux_003_src1_startofpacket;                                     // rsp_demux_003:src1_startofpacket -> rsp_mux_001:sink3_startofpacket
	wire          rsp_demux_003_src1_endofpacket;                                       // rsp_demux_003:src1_endofpacket -> rsp_mux_001:sink3_endofpacket
	wire          rsp_demux_004_src0_valid;                                             // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
	wire  [145:0] rsp_demux_004_src0_data;                                              // rsp_demux_004:src0_data -> rsp_mux:sink4_data
	wire          rsp_demux_004_src0_ready;                                             // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
	wire   [13:0] rsp_demux_004_src0_channel;                                           // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
	wire          rsp_demux_004_src0_startofpacket;                                     // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
	wire          rsp_demux_004_src0_endofpacket;                                       // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
	wire          rsp_demux_004_src1_valid;                                             // rsp_demux_004:src1_valid -> rsp_mux_001:sink4_valid
	wire  [145:0] rsp_demux_004_src1_data;                                              // rsp_demux_004:src1_data -> rsp_mux_001:sink4_data
	wire          rsp_demux_004_src1_ready;                                             // rsp_mux_001:sink4_ready -> rsp_demux_004:src1_ready
	wire   [13:0] rsp_demux_004_src1_channel;                                           // rsp_demux_004:src1_channel -> rsp_mux_001:sink4_channel
	wire          rsp_demux_004_src1_startofpacket;                                     // rsp_demux_004:src1_startofpacket -> rsp_mux_001:sink4_startofpacket
	wire          rsp_demux_004_src1_endofpacket;                                       // rsp_demux_004:src1_endofpacket -> rsp_mux_001:sink4_endofpacket
	wire          rsp_demux_005_src0_valid;                                             // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
	wire  [145:0] rsp_demux_005_src0_data;                                              // rsp_demux_005:src0_data -> rsp_mux:sink5_data
	wire          rsp_demux_005_src0_ready;                                             // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
	wire   [13:0] rsp_demux_005_src0_channel;                                           // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
	wire          rsp_demux_005_src0_startofpacket;                                     // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
	wire          rsp_demux_005_src0_endofpacket;                                       // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
	wire          rsp_demux_005_src1_valid;                                             // rsp_demux_005:src1_valid -> rsp_mux_001:sink5_valid
	wire  [145:0] rsp_demux_005_src1_data;                                              // rsp_demux_005:src1_data -> rsp_mux_001:sink5_data
	wire          rsp_demux_005_src1_ready;                                             // rsp_mux_001:sink5_ready -> rsp_demux_005:src1_ready
	wire   [13:0] rsp_demux_005_src1_channel;                                           // rsp_demux_005:src1_channel -> rsp_mux_001:sink5_channel
	wire          rsp_demux_005_src1_startofpacket;                                     // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink5_startofpacket
	wire          rsp_demux_005_src1_endofpacket;                                       // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink5_endofpacket
	wire          rsp_demux_006_src0_valid;                                             // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
	wire  [145:0] rsp_demux_006_src0_data;                                              // rsp_demux_006:src0_data -> rsp_mux:sink6_data
	wire          rsp_demux_006_src0_ready;                                             // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
	wire   [13:0] rsp_demux_006_src0_channel;                                           // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
	wire          rsp_demux_006_src0_startofpacket;                                     // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
	wire          rsp_demux_006_src0_endofpacket;                                       // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
	wire          rsp_demux_006_src1_valid;                                             // rsp_demux_006:src1_valid -> rsp_mux_001:sink6_valid
	wire  [145:0] rsp_demux_006_src1_data;                                              // rsp_demux_006:src1_data -> rsp_mux_001:sink6_data
	wire          rsp_demux_006_src1_ready;                                             // rsp_mux_001:sink6_ready -> rsp_demux_006:src1_ready
	wire   [13:0] rsp_demux_006_src1_channel;                                           // rsp_demux_006:src1_channel -> rsp_mux_001:sink6_channel
	wire          rsp_demux_006_src1_startofpacket;                                     // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink6_startofpacket
	wire          rsp_demux_006_src1_endofpacket;                                       // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink6_endofpacket
	wire          rsp_demux_007_src0_valid;                                             // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
	wire  [145:0] rsp_demux_007_src0_data;                                              // rsp_demux_007:src0_data -> rsp_mux:sink7_data
	wire          rsp_demux_007_src0_ready;                                             // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
	wire   [13:0] rsp_demux_007_src0_channel;                                           // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
	wire          rsp_demux_007_src0_startofpacket;                                     // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
	wire          rsp_demux_007_src0_endofpacket;                                       // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
	wire          rsp_demux_007_src1_valid;                                             // rsp_demux_007:src1_valid -> rsp_mux_001:sink7_valid
	wire  [145:0] rsp_demux_007_src1_data;                                              // rsp_demux_007:src1_data -> rsp_mux_001:sink7_data
	wire          rsp_demux_007_src1_ready;                                             // rsp_mux_001:sink7_ready -> rsp_demux_007:src1_ready
	wire   [13:0] rsp_demux_007_src1_channel;                                           // rsp_demux_007:src1_channel -> rsp_mux_001:sink7_channel
	wire          rsp_demux_007_src1_startofpacket;                                     // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink7_startofpacket
	wire          rsp_demux_007_src1_endofpacket;                                       // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink7_endofpacket
	wire          rsp_demux_008_src0_valid;                                             // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
	wire  [145:0] rsp_demux_008_src0_data;                                              // rsp_demux_008:src0_data -> rsp_mux:sink8_data
	wire          rsp_demux_008_src0_ready;                                             // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
	wire   [13:0] rsp_demux_008_src0_channel;                                           // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
	wire          rsp_demux_008_src0_startofpacket;                                     // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
	wire          rsp_demux_008_src0_endofpacket;                                       // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
	wire          rsp_demux_008_src1_valid;                                             // rsp_demux_008:src1_valid -> rsp_mux_001:sink8_valid
	wire  [145:0] rsp_demux_008_src1_data;                                              // rsp_demux_008:src1_data -> rsp_mux_001:sink8_data
	wire          rsp_demux_008_src1_ready;                                             // rsp_mux_001:sink8_ready -> rsp_demux_008:src1_ready
	wire   [13:0] rsp_demux_008_src1_channel;                                           // rsp_demux_008:src1_channel -> rsp_mux_001:sink8_channel
	wire          rsp_demux_008_src1_startofpacket;                                     // rsp_demux_008:src1_startofpacket -> rsp_mux_001:sink8_startofpacket
	wire          rsp_demux_008_src1_endofpacket;                                       // rsp_demux_008:src1_endofpacket -> rsp_mux_001:sink8_endofpacket
	wire          rsp_demux_009_src0_valid;                                             // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
	wire  [145:0] rsp_demux_009_src0_data;                                              // rsp_demux_009:src0_data -> rsp_mux:sink9_data
	wire          rsp_demux_009_src0_ready;                                             // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
	wire   [13:0] rsp_demux_009_src0_channel;                                           // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
	wire          rsp_demux_009_src0_startofpacket;                                     // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
	wire          rsp_demux_009_src0_endofpacket;                                       // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
	wire          rsp_demux_009_src1_valid;                                             // rsp_demux_009:src1_valid -> rsp_mux_001:sink9_valid
	wire  [145:0] rsp_demux_009_src1_data;                                              // rsp_demux_009:src1_data -> rsp_mux_001:sink9_data
	wire          rsp_demux_009_src1_ready;                                             // rsp_mux_001:sink9_ready -> rsp_demux_009:src1_ready
	wire   [13:0] rsp_demux_009_src1_channel;                                           // rsp_demux_009:src1_channel -> rsp_mux_001:sink9_channel
	wire          rsp_demux_009_src1_startofpacket;                                     // rsp_demux_009:src1_startofpacket -> rsp_mux_001:sink9_startofpacket
	wire          rsp_demux_009_src1_endofpacket;                                       // rsp_demux_009:src1_endofpacket -> rsp_mux_001:sink9_endofpacket
	wire          rsp_demux_010_src0_valid;                                             // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
	wire  [145:0] rsp_demux_010_src0_data;                                              // rsp_demux_010:src0_data -> rsp_mux:sink10_data
	wire          rsp_demux_010_src0_ready;                                             // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
	wire   [13:0] rsp_demux_010_src0_channel;                                           // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
	wire          rsp_demux_010_src0_startofpacket;                                     // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
	wire          rsp_demux_010_src0_endofpacket;                                       // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
	wire          rsp_demux_010_src1_valid;                                             // rsp_demux_010:src1_valid -> rsp_mux_001:sink10_valid
	wire  [145:0] rsp_demux_010_src1_data;                                              // rsp_demux_010:src1_data -> rsp_mux_001:sink10_data
	wire          rsp_demux_010_src1_ready;                                             // rsp_mux_001:sink10_ready -> rsp_demux_010:src1_ready
	wire   [13:0] rsp_demux_010_src1_channel;                                           // rsp_demux_010:src1_channel -> rsp_mux_001:sink10_channel
	wire          rsp_demux_010_src1_startofpacket;                                     // rsp_demux_010:src1_startofpacket -> rsp_mux_001:sink10_startofpacket
	wire          rsp_demux_010_src1_endofpacket;                                       // rsp_demux_010:src1_endofpacket -> rsp_mux_001:sink10_endofpacket
	wire          rsp_demux_011_src0_valid;                                             // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
	wire  [145:0] rsp_demux_011_src0_data;                                              // rsp_demux_011:src0_data -> rsp_mux:sink11_data
	wire          rsp_demux_011_src0_ready;                                             // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
	wire   [13:0] rsp_demux_011_src0_channel;                                           // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
	wire          rsp_demux_011_src0_startofpacket;                                     // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
	wire          rsp_demux_011_src0_endofpacket;                                       // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
	wire          rsp_demux_011_src1_valid;                                             // rsp_demux_011:src1_valid -> rsp_mux_001:sink11_valid
	wire  [145:0] rsp_demux_011_src1_data;                                              // rsp_demux_011:src1_data -> rsp_mux_001:sink11_data
	wire          rsp_demux_011_src1_ready;                                             // rsp_mux_001:sink11_ready -> rsp_demux_011:src1_ready
	wire   [13:0] rsp_demux_011_src1_channel;                                           // rsp_demux_011:src1_channel -> rsp_mux_001:sink11_channel
	wire          rsp_demux_011_src1_startofpacket;                                     // rsp_demux_011:src1_startofpacket -> rsp_mux_001:sink11_startofpacket
	wire          rsp_demux_011_src1_endofpacket;                                       // rsp_demux_011:src1_endofpacket -> rsp_mux_001:sink11_endofpacket
	wire          rsp_demux_012_src0_valid;                                             // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
	wire  [145:0] rsp_demux_012_src0_data;                                              // rsp_demux_012:src0_data -> rsp_mux:sink12_data
	wire          rsp_demux_012_src0_ready;                                             // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
	wire   [13:0] rsp_demux_012_src0_channel;                                           // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
	wire          rsp_demux_012_src0_startofpacket;                                     // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
	wire          rsp_demux_012_src0_endofpacket;                                       // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
	wire          rsp_demux_012_src1_valid;                                             // rsp_demux_012:src1_valid -> rsp_mux_001:sink12_valid
	wire  [145:0] rsp_demux_012_src1_data;                                              // rsp_demux_012:src1_data -> rsp_mux_001:sink12_data
	wire          rsp_demux_012_src1_ready;                                             // rsp_mux_001:sink12_ready -> rsp_demux_012:src1_ready
	wire   [13:0] rsp_demux_012_src1_channel;                                           // rsp_demux_012:src1_channel -> rsp_mux_001:sink12_channel
	wire          rsp_demux_012_src1_startofpacket;                                     // rsp_demux_012:src1_startofpacket -> rsp_mux_001:sink12_startofpacket
	wire          rsp_demux_012_src1_endofpacket;                                       // rsp_demux_012:src1_endofpacket -> rsp_mux_001:sink12_endofpacket
	wire          rsp_demux_012_src2_valid;                                             // rsp_demux_012:src2_valid -> rsp_mux_002:sink1_valid
	wire  [145:0] rsp_demux_012_src2_data;                                              // rsp_demux_012:src2_data -> rsp_mux_002:sink1_data
	wire          rsp_demux_012_src2_ready;                                             // rsp_mux_002:sink1_ready -> rsp_demux_012:src2_ready
	wire   [13:0] rsp_demux_012_src2_channel;                                           // rsp_demux_012:src2_channel -> rsp_mux_002:sink1_channel
	wire          rsp_demux_012_src2_startofpacket;                                     // rsp_demux_012:src2_startofpacket -> rsp_mux_002:sink1_startofpacket
	wire          rsp_demux_012_src2_endofpacket;                                       // rsp_demux_012:src2_endofpacket -> rsp_mux_002:sink1_endofpacket
	wire          rsp_demux_012_src3_valid;                                             // rsp_demux_012:src3_valid -> rsp_mux_003:sink1_valid
	wire  [145:0] rsp_demux_012_src3_data;                                              // rsp_demux_012:src3_data -> rsp_mux_003:sink1_data
	wire          rsp_demux_012_src3_ready;                                             // rsp_mux_003:sink1_ready -> rsp_demux_012:src3_ready
	wire   [13:0] rsp_demux_012_src3_channel;                                           // rsp_demux_012:src3_channel -> rsp_mux_003:sink1_channel
	wire          rsp_demux_012_src3_startofpacket;                                     // rsp_demux_012:src3_startofpacket -> rsp_mux_003:sink1_startofpacket
	wire          rsp_demux_012_src3_endofpacket;                                       // rsp_demux_012:src3_endofpacket -> rsp_mux_003:sink1_endofpacket
	wire          rsp_demux_013_src0_valid;                                             // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
	wire  [145:0] rsp_demux_013_src0_data;                                              // rsp_demux_013:src0_data -> rsp_mux:sink13_data
	wire          rsp_demux_013_src0_ready;                                             // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
	wire   [13:0] rsp_demux_013_src0_channel;                                           // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
	wire          rsp_demux_013_src0_startofpacket;                                     // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
	wire          rsp_demux_013_src0_endofpacket;                                       // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
	wire          rsp_demux_013_src1_valid;                                             // rsp_demux_013:src1_valid -> rsp_mux_001:sink13_valid
	wire  [145:0] rsp_demux_013_src1_data;                                              // rsp_demux_013:src1_data -> rsp_mux_001:sink13_data
	wire          rsp_demux_013_src1_ready;                                             // rsp_mux_001:sink13_ready -> rsp_demux_013:src1_ready
	wire   [13:0] rsp_demux_013_src1_channel;                                           // rsp_demux_013:src1_channel -> rsp_mux_001:sink13_channel
	wire          rsp_demux_013_src1_startofpacket;                                     // rsp_demux_013:src1_startofpacket -> rsp_mux_001:sink13_startofpacket
	wire          rsp_demux_013_src1_endofpacket;                                       // rsp_demux_013:src1_endofpacket -> rsp_mux_001:sink13_endofpacket
	wire   [13:0] intel_niosv_g_instruction_manager_wr_limiter_cmd_valid_data;          // intel_niosv_g_instruction_manager_wr_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
	wire   [13:0] intel_niosv_g_instruction_manager_rd_limiter_cmd_valid_data;          // intel_niosv_g_instruction_manager_rd_limiter:cmd_src_valid -> cmd_demux_003:sink_valid

	system_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (0),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (0),
		.USE_S0_AWLOCK                     (0),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (0),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (0),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (0),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (0),
		.USE_S0_ARLOCK                     (0),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (0),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (0),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (1),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (32),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (32),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) intel_niosv_g_data_manager_translator (
		.aclk              (clock_in_out_clk_clk),                                                         //   input,   width = 1,       clk.clk
		.aresetn           (~intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (intel_niosv_g_data_manager_translator_m0_awid),                                //  output,   width = 1,        m0.awid
		.m0_awaddr         (intel_niosv_g_data_manager_translator_m0_awaddr),                              //  output,  width = 32,          .awaddr
		.m0_awlen          (intel_niosv_g_data_manager_translator_m0_awlen),                               //  output,   width = 8,          .awlen
		.m0_awsize         (intel_niosv_g_data_manager_translator_m0_awsize),                              //  output,   width = 3,          .awsize
		.m0_awburst        (intel_niosv_g_data_manager_translator_m0_awburst),                             //  output,   width = 2,          .awburst
		.m0_awlock         (intel_niosv_g_data_manager_translator_m0_awlock),                              //  output,   width = 1,          .awlock
		.m0_awcache        (intel_niosv_g_data_manager_translator_m0_awcache),                             //  output,   width = 4,          .awcache
		.m0_awprot         (intel_niosv_g_data_manager_translator_m0_awprot),                              //  output,   width = 3,          .awprot
		.m0_awuser         (intel_niosv_g_data_manager_translator_m0_awuser),                              //  output,   width = 1,          .awuser
		.m0_awqos          (intel_niosv_g_data_manager_translator_m0_awqos),                               //  output,   width = 4,          .awqos
		.m0_awregion       (intel_niosv_g_data_manager_translator_m0_awregion),                            //  output,   width = 4,          .awregion
		.m0_awvalid        (intel_niosv_g_data_manager_translator_m0_awvalid),                             //  output,   width = 1,          .awvalid
		.m0_awready        (intel_niosv_g_data_manager_translator_m0_awready),                             //   input,   width = 1,          .awready
		.m0_wdata          (intel_niosv_g_data_manager_translator_m0_wdata),                               //  output,  width = 32,          .wdata
		.m0_wstrb          (intel_niosv_g_data_manager_translator_m0_wstrb),                               //  output,   width = 4,          .wstrb
		.m0_wlast          (intel_niosv_g_data_manager_translator_m0_wlast),                               //  output,   width = 1,          .wlast
		.m0_wvalid         (intel_niosv_g_data_manager_translator_m0_wvalid),                              //  output,   width = 1,          .wvalid
		.m0_wuser          (intel_niosv_g_data_manager_translator_m0_wuser),                               //  output,   width = 1,          .wuser
		.m0_wready         (intel_niosv_g_data_manager_translator_m0_wready),                              //   input,   width = 1,          .wready
		.m0_bid            (intel_niosv_g_data_manager_translator_m0_bid),                                 //   input,   width = 1,          .bid
		.m0_bresp          (intel_niosv_g_data_manager_translator_m0_bresp),                               //   input,   width = 2,          .bresp
		.m0_buser          (intel_niosv_g_data_manager_translator_m0_buser),                               //   input,   width = 1,          .buser
		.m0_bvalid         (intel_niosv_g_data_manager_translator_m0_bvalid),                              //   input,   width = 1,          .bvalid
		.m0_bready         (intel_niosv_g_data_manager_translator_m0_bready),                              //  output,   width = 1,          .bready
		.m0_arid           (intel_niosv_g_data_manager_translator_m0_arid),                                //  output,   width = 1,          .arid
		.m0_araddr         (intel_niosv_g_data_manager_translator_m0_araddr),                              //  output,  width = 32,          .araddr
		.m0_arlen          (intel_niosv_g_data_manager_translator_m0_arlen),                               //  output,   width = 8,          .arlen
		.m0_arsize         (intel_niosv_g_data_manager_translator_m0_arsize),                              //  output,   width = 3,          .arsize
		.m0_arburst        (intel_niosv_g_data_manager_translator_m0_arburst),                             //  output,   width = 2,          .arburst
		.m0_arlock         (intel_niosv_g_data_manager_translator_m0_arlock),                              //  output,   width = 1,          .arlock
		.m0_arcache        (intel_niosv_g_data_manager_translator_m0_arcache),                             //  output,   width = 4,          .arcache
		.m0_arprot         (intel_niosv_g_data_manager_translator_m0_arprot),                              //  output,   width = 3,          .arprot
		.m0_aruser         (intel_niosv_g_data_manager_translator_m0_aruser),                              //  output,   width = 1,          .aruser
		.m0_arqos          (intel_niosv_g_data_manager_translator_m0_arqos),                               //  output,   width = 4,          .arqos
		.m0_arregion       (intel_niosv_g_data_manager_translator_m0_arregion),                            //  output,   width = 4,          .arregion
		.m0_arvalid        (intel_niosv_g_data_manager_translator_m0_arvalid),                             //  output,   width = 1,          .arvalid
		.m0_arready        (intel_niosv_g_data_manager_translator_m0_arready),                             //   input,   width = 1,          .arready
		.m0_rid            (intel_niosv_g_data_manager_translator_m0_rid),                                 //   input,   width = 1,          .rid
		.m0_rdata          (intel_niosv_g_data_manager_translator_m0_rdata),                               //   input,  width = 32,          .rdata
		.m0_rresp          (intel_niosv_g_data_manager_translator_m0_rresp),                               //   input,   width = 2,          .rresp
		.m0_rlast          (intel_niosv_g_data_manager_translator_m0_rlast),                               //   input,   width = 1,          .rlast
		.m0_rvalid         (intel_niosv_g_data_manager_translator_m0_rvalid),                              //   input,   width = 1,          .rvalid
		.m0_rready         (intel_niosv_g_data_manager_translator_m0_rready),                              //  output,   width = 1,          .rready
		.m0_ruser          (intel_niosv_g_data_manager_translator_m0_ruser),                               //   input,   width = 1,          .ruser
		.s0_awaddr         (intel_niosv_g_data_manager_awaddr),                                            //   input,  width = 32,        s0.awaddr
		.s0_awlen          (intel_niosv_g_data_manager_awlen),                                             //   input,   width = 8,          .awlen
		.s0_awsize         (intel_niosv_g_data_manager_awsize),                                            //   input,   width = 3,          .awsize
		.s0_awprot         (intel_niosv_g_data_manager_awprot),                                            //   input,   width = 3,          .awprot
		.s0_awvalid        (intel_niosv_g_data_manager_awvalid),                                           //   input,   width = 1,          .awvalid
		.s0_awready        (intel_niosv_g_data_manager_awready),                                           //  output,   width = 1,          .awready
		.s0_wdata          (intel_niosv_g_data_manager_wdata),                                             //   input,  width = 32,          .wdata
		.s0_wstrb          (intel_niosv_g_data_manager_wstrb),                                             //   input,   width = 4,          .wstrb
		.s0_wlast          (intel_niosv_g_data_manager_wlast),                                             //   input,   width = 1,          .wlast
		.s0_wvalid         (intel_niosv_g_data_manager_wvalid),                                            //   input,   width = 1,          .wvalid
		.s0_wready         (intel_niosv_g_data_manager_wready),                                            //  output,   width = 1,          .wready
		.s0_bresp          (intel_niosv_g_data_manager_bresp),                                             //  output,   width = 2,          .bresp
		.s0_bvalid         (intel_niosv_g_data_manager_bvalid),                                            //  output,   width = 1,          .bvalid
		.s0_bready         (intel_niosv_g_data_manager_bready),                                            //   input,   width = 1,          .bready
		.s0_araddr         (intel_niosv_g_data_manager_araddr),                                            //   input,  width = 32,          .araddr
		.s0_arlen          (intel_niosv_g_data_manager_arlen),                                             //   input,   width = 8,          .arlen
		.s0_arsize         (intel_niosv_g_data_manager_arsize),                                            //   input,   width = 3,          .arsize
		.s0_arprot         (intel_niosv_g_data_manager_arprot),                                            //   input,   width = 3,          .arprot
		.s0_arvalid        (intel_niosv_g_data_manager_arvalid),                                           //   input,   width = 1,          .arvalid
		.s0_arready        (intel_niosv_g_data_manager_arready),                                           //  output,   width = 1,          .arready
		.s0_rdata          (intel_niosv_g_data_manager_rdata),                                             //  output,  width = 32,          .rdata
		.s0_rresp          (intel_niosv_g_data_manager_rresp),                                             //  output,   width = 2,          .rresp
		.s0_rlast          (intel_niosv_g_data_manager_rlast),                                             //  output,   width = 1,          .rlast
		.s0_rvalid         (intel_niosv_g_data_manager_rvalid),                                            //  output,   width = 1,          .rvalid
		.s0_rready         (intel_niosv_g_data_manager_rready),                                            //   input,   width = 1,          .rready
		.m0_awuser_addrchk (),                                                                             // (terminated),                        
		.m0_awuser_sai     (),                                                                             // (terminated),                        
		.m0_wuser_datachk  (),                                                                             // (terminated),                        
		.m0_wuser_data     (),                                                                             // (terminated),                        
		.m0_wuser_poison   (),                                                                             // (terminated),                        
		.m0_aruser_addrchk (),                                                                             // (terminated),                        
		.m0_aruser_sai     (),                                                                             // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                                                      // (terminated),                        
		.m0_ruser_data     (4'b0000),                                                                      // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                                         // (terminated),                        
		.s0_awid           (1'b0),                                                                         // (terminated),                        
		.s0_awburst        (2'b00),                                                                        // (terminated),                        
		.s0_awlock         (1'b0),                                                                         // (terminated),                        
		.s0_awcache        (4'b0000),                                                                      // (terminated),                        
		.s0_awuser         (1'b0),                                                                         // (terminated),                        
		.s0_awuser_addrchk (4'b0000),                                                                      // (terminated),                        
		.s0_awuser_sai     (4'b0000),                                                                      // (terminated),                        
		.s0_awqos          (4'b0000),                                                                      // (terminated),                        
		.s0_awregion       (4'b0000),                                                                      // (terminated),                        
		.s0_wuser          (1'b0),                                                                         // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                                                      // (terminated),                        
		.s0_wuser_data     (4'b0000),                                                                      // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                                         // (terminated),                        
		.s0_bid            (),                                                                             // (terminated),                        
		.s0_buser          (),                                                                             // (terminated),                        
		.s0_arid           (1'b0),                                                                         // (terminated),                        
		.s0_arburst        (2'b00),                                                                        // (terminated),                        
		.s0_arlock         (1'b0),                                                                         // (terminated),                        
		.s0_arcache        (4'b0000),                                                                      // (terminated),                        
		.s0_aruser         (1'b0),                                                                         // (terminated),                        
		.s0_aruser_addrchk (4'b0000),                                                                      // (terminated),                        
		.s0_aruser_sai     (4'b0000),                                                                      // (terminated),                        
		.s0_arqos          (4'b0000),                                                                      // (terminated),                        
		.s0_arregion       (4'b0000),                                                                      // (terminated),                        
		.s0_rid            (),                                                                             // (terminated),                        
		.s0_ruser          (),                                                                             // (terminated),                        
		.s0_ruser_datachk  (),                                                                             // (terminated),                        
		.s0_ruser_data     (),                                                                             // (terminated),                        
		.s0_ruser_poison   (),                                                                             // (terminated),                        
		.s0_wid            (1'b0),                                                                         // (terminated),                        
		.s0_ardomain       (2'b00),                                                                        // (terminated),                        
		.s0_arsnoop        (4'b0000),                                                                      // (terminated),                        
		.s0_arbar          (2'b00),                                                                        // (terminated),                        
		.s0_awdomain       (2'b00),                                                                        // (terminated),                        
		.s0_awsnoop        (3'b000),                                                                       // (terminated),                        
		.s0_awbar          (2'b00),                                                                        // (terminated),                        
		.s0_awunique       (1'b0),                                                                         // (terminated),                        
		.m0_wid            (),                                                                             // (terminated),                        
		.m0_ardomain       (),                                                                             // (terminated),                        
		.m0_arsnoop        (),                                                                             // (terminated),                        
		.m0_arbar          (),                                                                             // (terminated),                        
		.m0_awdomain       (),                                                                             // (terminated),                        
		.m0_awsnoop        (),                                                                             // (terminated),                        
		.m0_awbar          (),                                                                             // (terminated),                        
		.m0_awunique       ()                                                                              // (terminated),                        
	);

	system_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (0),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (0),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (0),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (0),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (0),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (0),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (0),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (0),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (1),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (32),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (32),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) intel_niosv_g_instruction_manager_translator (
		.aclk              (clock_in_out_clk_clk),                                                         //   input,   width = 1,       clk.clk
		.aresetn           (~intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (intel_niosv_g_instruction_manager_translator_m0_awid),                         //  output,   width = 1,        m0.awid
		.m0_awaddr         (intel_niosv_g_instruction_manager_translator_m0_awaddr),                       //  output,  width = 32,          .awaddr
		.m0_awlen          (intel_niosv_g_instruction_manager_translator_m0_awlen),                        //  output,   width = 8,          .awlen
		.m0_awsize         (intel_niosv_g_instruction_manager_translator_m0_awsize),                       //  output,   width = 3,          .awsize
		.m0_awburst        (intel_niosv_g_instruction_manager_translator_m0_awburst),                      //  output,   width = 2,          .awburst
		.m0_awlock         (intel_niosv_g_instruction_manager_translator_m0_awlock),                       //  output,   width = 1,          .awlock
		.m0_awcache        (intel_niosv_g_instruction_manager_translator_m0_awcache),                      //  output,   width = 4,          .awcache
		.m0_awprot         (intel_niosv_g_instruction_manager_translator_m0_awprot),                       //  output,   width = 3,          .awprot
		.m0_awuser         (intel_niosv_g_instruction_manager_translator_m0_awuser),                       //  output,   width = 1,          .awuser
		.m0_awqos          (intel_niosv_g_instruction_manager_translator_m0_awqos),                        //  output,   width = 4,          .awqos
		.m0_awregion       (intel_niosv_g_instruction_manager_translator_m0_awregion),                     //  output,   width = 4,          .awregion
		.m0_awvalid        (intel_niosv_g_instruction_manager_translator_m0_awvalid),                      //  output,   width = 1,          .awvalid
		.m0_awready        (intel_niosv_g_instruction_manager_translator_m0_awready),                      //   input,   width = 1,          .awready
		.m0_wdata          (intel_niosv_g_instruction_manager_translator_m0_wdata),                        //  output,  width = 32,          .wdata
		.m0_wstrb          (intel_niosv_g_instruction_manager_translator_m0_wstrb),                        //  output,   width = 4,          .wstrb
		.m0_wlast          (intel_niosv_g_instruction_manager_translator_m0_wlast),                        //  output,   width = 1,          .wlast
		.m0_wvalid         (intel_niosv_g_instruction_manager_translator_m0_wvalid),                       //  output,   width = 1,          .wvalid
		.m0_wuser          (intel_niosv_g_instruction_manager_translator_m0_wuser),                        //  output,   width = 1,          .wuser
		.m0_wready         (intel_niosv_g_instruction_manager_translator_m0_wready),                       //   input,   width = 1,          .wready
		.m0_bid            (intel_niosv_g_instruction_manager_translator_m0_bid),                          //   input,   width = 1,          .bid
		.m0_bresp          (intel_niosv_g_instruction_manager_translator_m0_bresp),                        //   input,   width = 2,          .bresp
		.m0_buser          (intel_niosv_g_instruction_manager_translator_m0_buser),                        //   input,   width = 1,          .buser
		.m0_bvalid         (intel_niosv_g_instruction_manager_translator_m0_bvalid),                       //   input,   width = 1,          .bvalid
		.m0_bready         (intel_niosv_g_instruction_manager_translator_m0_bready),                       //  output,   width = 1,          .bready
		.m0_arid           (intel_niosv_g_instruction_manager_translator_m0_arid),                         //  output,   width = 1,          .arid
		.m0_araddr         (intel_niosv_g_instruction_manager_translator_m0_araddr),                       //  output,  width = 32,          .araddr
		.m0_arlen          (intel_niosv_g_instruction_manager_translator_m0_arlen),                        //  output,   width = 8,          .arlen
		.m0_arsize         (intel_niosv_g_instruction_manager_translator_m0_arsize),                       //  output,   width = 3,          .arsize
		.m0_arburst        (intel_niosv_g_instruction_manager_translator_m0_arburst),                      //  output,   width = 2,          .arburst
		.m0_arlock         (intel_niosv_g_instruction_manager_translator_m0_arlock),                       //  output,   width = 1,          .arlock
		.m0_arcache        (intel_niosv_g_instruction_manager_translator_m0_arcache),                      //  output,   width = 4,          .arcache
		.m0_arprot         (intel_niosv_g_instruction_manager_translator_m0_arprot),                       //  output,   width = 3,          .arprot
		.m0_aruser         (intel_niosv_g_instruction_manager_translator_m0_aruser),                       //  output,   width = 1,          .aruser
		.m0_arqos          (intel_niosv_g_instruction_manager_translator_m0_arqos),                        //  output,   width = 4,          .arqos
		.m0_arregion       (intel_niosv_g_instruction_manager_translator_m0_arregion),                     //  output,   width = 4,          .arregion
		.m0_arvalid        (intel_niosv_g_instruction_manager_translator_m0_arvalid),                      //  output,   width = 1,          .arvalid
		.m0_arready        (intel_niosv_g_instruction_manager_translator_m0_arready),                      //   input,   width = 1,          .arready
		.m0_rid            (intel_niosv_g_instruction_manager_translator_m0_rid),                          //   input,   width = 1,          .rid
		.m0_rdata          (intel_niosv_g_instruction_manager_translator_m0_rdata),                        //   input,  width = 32,          .rdata
		.m0_rresp          (intel_niosv_g_instruction_manager_translator_m0_rresp),                        //   input,   width = 2,          .rresp
		.m0_rlast          (intel_niosv_g_instruction_manager_translator_m0_rlast),                        //   input,   width = 1,          .rlast
		.m0_rvalid         (intel_niosv_g_instruction_manager_translator_m0_rvalid),                       //   input,   width = 1,          .rvalid
		.m0_rready         (intel_niosv_g_instruction_manager_translator_m0_rready),                       //  output,   width = 1,          .rready
		.m0_ruser          (intel_niosv_g_instruction_manager_translator_m0_ruser),                        //   input,   width = 1,          .ruser
		.s0_awaddr         (intel_niosv_g_instruction_manager_awaddr),                                     //   input,  width = 32,        s0.awaddr
		.s0_awlen          (intel_niosv_g_instruction_manager_awlen),                                      //   input,   width = 8,          .awlen
		.s0_awsize         (intel_niosv_g_instruction_manager_awsize),                                     //   input,   width = 3,          .awsize
		.s0_awburst        (intel_niosv_g_instruction_manager_awburst),                                    //   input,   width = 2,          .awburst
		.s0_awprot         (intel_niosv_g_instruction_manager_awprot),                                     //   input,   width = 3,          .awprot
		.s0_awvalid        (intel_niosv_g_instruction_manager_awvalid),                                    //   input,   width = 1,          .awvalid
		.s0_awready        (intel_niosv_g_instruction_manager_awready),                                    //  output,   width = 1,          .awready
		.s0_wdata          (intel_niosv_g_instruction_manager_wdata),                                      //   input,  width = 32,          .wdata
		.s0_wstrb          (intel_niosv_g_instruction_manager_wstrb),                                      //   input,   width = 4,          .wstrb
		.s0_wlast          (intel_niosv_g_instruction_manager_wlast),                                      //   input,   width = 1,          .wlast
		.s0_wvalid         (intel_niosv_g_instruction_manager_wvalid),                                     //   input,   width = 1,          .wvalid
		.s0_wready         (intel_niosv_g_instruction_manager_wready),                                     //  output,   width = 1,          .wready
		.s0_bresp          (intel_niosv_g_instruction_manager_bresp),                                      //  output,   width = 2,          .bresp
		.s0_bvalid         (intel_niosv_g_instruction_manager_bvalid),                                     //  output,   width = 1,          .bvalid
		.s0_bready         (intel_niosv_g_instruction_manager_bready),                                     //   input,   width = 1,          .bready
		.s0_araddr         (intel_niosv_g_instruction_manager_araddr),                                     //   input,  width = 32,          .araddr
		.s0_arlen          (intel_niosv_g_instruction_manager_arlen),                                      //   input,   width = 8,          .arlen
		.s0_arsize         (intel_niosv_g_instruction_manager_arsize),                                     //   input,   width = 3,          .arsize
		.s0_arburst        (intel_niosv_g_instruction_manager_arburst),                                    //   input,   width = 2,          .arburst
		.s0_arprot         (intel_niosv_g_instruction_manager_arprot),                                     //   input,   width = 3,          .arprot
		.s0_arvalid        (intel_niosv_g_instruction_manager_arvalid),                                    //   input,   width = 1,          .arvalid
		.s0_arready        (intel_niosv_g_instruction_manager_arready),                                    //  output,   width = 1,          .arready
		.s0_rdata          (intel_niosv_g_instruction_manager_rdata),                                      //  output,  width = 32,          .rdata
		.s0_rresp          (intel_niosv_g_instruction_manager_rresp),                                      //  output,   width = 2,          .rresp
		.s0_rlast          (intel_niosv_g_instruction_manager_rlast),                                      //  output,   width = 1,          .rlast
		.s0_rvalid         (intel_niosv_g_instruction_manager_rvalid),                                     //  output,   width = 1,          .rvalid
		.s0_rready         (intel_niosv_g_instruction_manager_rready),                                     //   input,   width = 1,          .rready
		.m0_awuser_addrchk (),                                                                             // (terminated),                        
		.m0_awuser_sai     (),                                                                             // (terminated),                        
		.m0_wuser_datachk  (),                                                                             // (terminated),                        
		.m0_wuser_data     (),                                                                             // (terminated),                        
		.m0_wuser_poison   (),                                                                             // (terminated),                        
		.m0_aruser_addrchk (),                                                                             // (terminated),                        
		.m0_aruser_sai     (),                                                                             // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                                                      // (terminated),                        
		.m0_ruser_data     (4'b0000),                                                                      // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                                         // (terminated),                        
		.s0_awid           (1'b0),                                                                         // (terminated),                        
		.s0_awlock         (1'b0),                                                                         // (terminated),                        
		.s0_awcache        (4'b0000),                                                                      // (terminated),                        
		.s0_awuser         (1'b0),                                                                         // (terminated),                        
		.s0_awuser_addrchk (4'b0000),                                                                      // (terminated),                        
		.s0_awuser_sai     (4'b0000),                                                                      // (terminated),                        
		.s0_awqos          (4'b0000),                                                                      // (terminated),                        
		.s0_awregion       (4'b0000),                                                                      // (terminated),                        
		.s0_wuser          (1'b0),                                                                         // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                                                      // (terminated),                        
		.s0_wuser_data     (4'b0000),                                                                      // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                                         // (terminated),                        
		.s0_bid            (),                                                                             // (terminated),                        
		.s0_buser          (),                                                                             // (terminated),                        
		.s0_arid           (1'b0),                                                                         // (terminated),                        
		.s0_arlock         (1'b0),                                                                         // (terminated),                        
		.s0_arcache        (4'b0000),                                                                      // (terminated),                        
		.s0_aruser         (1'b0),                                                                         // (terminated),                        
		.s0_aruser_addrchk (4'b0000),                                                                      // (terminated),                        
		.s0_aruser_sai     (4'b0000),                                                                      // (terminated),                        
		.s0_arqos          (4'b0000),                                                                      // (terminated),                        
		.s0_arregion       (4'b0000),                                                                      // (terminated),                        
		.s0_rid            (),                                                                             // (terminated),                        
		.s0_ruser          (),                                                                             // (terminated),                        
		.s0_ruser_datachk  (),                                                                             // (terminated),                        
		.s0_ruser_data     (),                                                                             // (terminated),                        
		.s0_ruser_poison   (),                                                                             // (terminated),                        
		.s0_wid            (1'b0),                                                                         // (terminated),                        
		.s0_ardomain       (2'b00),                                                                        // (terminated),                        
		.s0_arsnoop        (4'b0000),                                                                      // (terminated),                        
		.s0_arbar          (2'b00),                                                                        // (terminated),                        
		.s0_awdomain       (2'b00),                                                                        // (terminated),                        
		.s0_awsnoop        (3'b000),                                                                       // (terminated),                        
		.s0_awbar          (2'b00),                                                                        // (terminated),                        
		.s0_awunique       (1'b0),                                                                         // (terminated),                        
		.m0_wid            (),                                                                             // (terminated),                        
		.m0_ardomain       (),                                                                             // (terminated),                        
		.m0_arsnoop        (),                                                                             // (terminated),                        
		.m0_arbar          (),                                                                             // (terminated),                        
		.m0_awdomain       (),                                                                             // (terminated),                        
		.m0_awsnoop        (),                                                                             // (terminated),                        
		.m0_awbar          (),                                                                             // (terminated),                        
		.m0_awunique       ()                                                                              // (terminated),                        
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) jtag_uart_avalon_jtag_slave_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (jtag_uart_avalon_jtag_slave_agent_m0_address),                                //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),                             //   input,   width = 3,                         .burstcount
		.uav_read               (jtag_uart_avalon_jtag_slave_agent_m0_read),                                   //   input,   width = 1,                         .read
		.uav_write              (jtag_uart_avalon_jtag_slave_agent_m0_write),                                  //   input,   width = 1,                         .write
		.uav_waitrequest        (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),                            //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),                          //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),                             //   input,   width = 4,                         .byteenable
		.uav_readdata           (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                               //  output,  width = 32,                         .readdata
		.uav_writedata          (jtag_uart_avalon_jtag_slave_agent_m0_writedata),                              //   input,  width = 32,                         .writedata
		.uav_lock               (jtag_uart_avalon_jtag_slave_agent_m0_lock),                                   //   input,   width = 1,                         .lock
		.uav_debugaccess        (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),                            //   input,   width = 1,                         .debugaccess
		.av_address             (jtag_uart_avalon_jtag_slave_address),                                         //  output,   width = 1,      avalon_anti_slave_0.address
		.av_write               (jtag_uart_avalon_jtag_slave_write),                                           //  output,   width = 1,                         .write
		.av_read                (jtag_uart_avalon_jtag_slave_read),                                            //  output,   width = 1,                         .read
		.av_readdata            (jtag_uart_avalon_jtag_slave_readdata),                                        //   input,  width = 32,                         .readdata
		.av_writedata           (jtag_uart_avalon_jtag_slave_writedata),                                       //  output,  width = 32,                         .writedata
		.av_waitrequest         (jtag_uart_avalon_jtag_slave_waitrequest),                                     //   input,   width = 1,                         .waitrequest
		.av_chipselect          (jtag_uart_avalon_jtag_slave_chipselect),                                      //  output,   width = 1,                         .chipselect
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (1),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) sysid_qsys_control_slave_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (sysid_qsys_control_slave_agent_m0_address),                                   //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (sysid_qsys_control_slave_agent_m0_burstcount),                                //   input,   width = 3,                         .burstcount
		.uav_read               (sysid_qsys_control_slave_agent_m0_read),                                      //   input,   width = 1,                         .read
		.uav_write              (sysid_qsys_control_slave_agent_m0_write),                                     //   input,   width = 1,                         .write
		.uav_waitrequest        (sysid_qsys_control_slave_agent_m0_waitrequest),                               //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (sysid_qsys_control_slave_agent_m0_readdatavalid),                             //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (sysid_qsys_control_slave_agent_m0_byteenable),                                //   input,   width = 4,                         .byteenable
		.uav_readdata           (sysid_qsys_control_slave_agent_m0_readdata),                                  //  output,  width = 32,                         .readdata
		.uav_writedata          (sysid_qsys_control_slave_agent_m0_writedata),                                 //   input,  width = 32,                         .writedata
		.uav_lock               (sysid_qsys_control_slave_agent_m0_lock),                                      //   input,   width = 1,                         .lock
		.uav_debugaccess        (sysid_qsys_control_slave_agent_m0_debugaccess),                               //   input,   width = 1,                         .debugaccess
		.av_address             (sysid_qsys_control_slave_address),                                            //  output,   width = 1,      avalon_anti_slave_0.address
		.av_readdata            (sysid_qsys_control_slave_readdata),                                           //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (16),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) intel_niosv_g_dm_agent_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (intel_niosv_g_dm_agent_agent_m0_address),                                     //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (intel_niosv_g_dm_agent_agent_m0_burstcount),                                  //   input,   width = 3,                         .burstcount
		.uav_read               (intel_niosv_g_dm_agent_agent_m0_read),                                        //   input,   width = 1,                         .read
		.uav_write              (intel_niosv_g_dm_agent_agent_m0_write),                                       //   input,   width = 1,                         .write
		.uav_waitrequest        (intel_niosv_g_dm_agent_agent_m0_waitrequest),                                 //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (intel_niosv_g_dm_agent_agent_m0_readdatavalid),                               //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (intel_niosv_g_dm_agent_agent_m0_byteenable),                                  //   input,   width = 4,                         .byteenable
		.uav_readdata           (intel_niosv_g_dm_agent_agent_m0_readdata),                                    //  output,  width = 32,                         .readdata
		.uav_writedata          (intel_niosv_g_dm_agent_agent_m0_writedata),                                   //   input,  width = 32,                         .writedata
		.uav_lock               (intel_niosv_g_dm_agent_agent_m0_lock),                                        //   input,   width = 1,                         .lock
		.uav_debugaccess        (intel_niosv_g_dm_agent_agent_m0_debugaccess),                                 //   input,   width = 1,                         .debugaccess
		.av_address             (intel_niosv_g_dm_agent_address),                                              //  output,  width = 16,      avalon_anti_slave_0.address
		.av_write               (intel_niosv_g_dm_agent_write),                                                //  output,   width = 1,                         .write
		.av_read                (intel_niosv_g_dm_agent_read),                                                 //  output,   width = 1,                         .read
		.av_readdata            (intel_niosv_g_dm_agent_readdata),                                             //   input,  width = 32,                         .readdata
		.av_writedata           (intel_niosv_g_dm_agent_writedata),                                            //  output,  width = 32,                         .writedata
		.av_readdatavalid       (intel_niosv_g_dm_agent_readdatavalid),                                        //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (intel_niosv_g_dm_agent_waitrequest),                                          //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (3),
		.AV_DATA_W                      (16),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) timer_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (timer_s1_agent_m0_address),                                                   //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (timer_s1_agent_m0_burstcount),                                                //   input,   width = 3,                         .burstcount
		.uav_read               (timer_s1_agent_m0_read),                                                      //   input,   width = 1,                         .read
		.uav_write              (timer_s1_agent_m0_write),                                                     //   input,   width = 1,                         .write
		.uav_waitrequest        (timer_s1_agent_m0_waitrequest),                                               //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (timer_s1_agent_m0_readdatavalid),                                             //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (timer_s1_agent_m0_byteenable),                                                //   input,   width = 4,                         .byteenable
		.uav_readdata           (timer_s1_agent_m0_readdata),                                                  //  output,  width = 32,                         .readdata
		.uav_writedata          (timer_s1_agent_m0_writedata),                                                 //   input,  width = 32,                         .writedata
		.uav_lock               (timer_s1_agent_m0_lock),                                                      //   input,   width = 1,                         .lock
		.uav_debugaccess        (timer_s1_agent_m0_debugaccess),                                               //   input,   width = 1,                         .debugaccess
		.av_address             (timer_s1_address),                                                            //  output,   width = 3,      avalon_anti_slave_0.address
		.av_write               (timer_s1_write),                                                              //  output,   width = 1,                         .write
		.av_readdata            (timer_s1_readdata),                                                           //   input,  width = 16,                         .readdata
		.av_writedata           (timer_s1_writedata),                                                          //  output,  width = 16,                         .writedata
		.av_chipselect          (timer_s1_chipselect),                                                         //  output,   width = 1,                         .chipselect
		.av_read                (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_power_in_voltage_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_power_in_voltage_s1_agent_m0_address),                             //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_power_in_voltage_s1_agent_m0_burstcount),                          //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_power_in_voltage_s1_agent_m0_read),                                //   input,   width = 1,                         .read
		.uav_write              (board_info_power_in_voltage_s1_agent_m0_write),                               //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_power_in_voltage_s1_agent_m0_waitrequest),                         //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_power_in_voltage_s1_agent_m0_readdatavalid),                       //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_power_in_voltage_s1_agent_m0_byteenable),                          //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_power_in_voltage_s1_agent_m0_readdata),                            //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_power_in_voltage_s1_agent_m0_writedata),                           //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_power_in_voltage_s1_agent_m0_lock),                                //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_power_in_voltage_s1_agent_m0_debugaccess),                         //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_power_in_voltage_s1_address),                                      //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_power_in_voltage_s1_readdata),                                     //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_vcc1p2_voltage_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_vcc1p2_voltage_s1_agent_m0_address),                               //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_vcc1p2_voltage_s1_agent_m0_burstcount),                            //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_vcc1p2_voltage_s1_agent_m0_read),                                  //   input,   width = 1,                         .read
		.uav_write              (board_info_vcc1p2_voltage_s1_agent_m0_write),                                 //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_vcc1p2_voltage_s1_agent_m0_waitrequest),                           //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_vcc1p2_voltage_s1_agent_m0_readdatavalid),                         //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_vcc1p2_voltage_s1_agent_m0_byteenable),                            //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_vcc1p2_voltage_s1_agent_m0_readdata),                              //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_vcc1p2_voltage_s1_agent_m0_writedata),                             //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_vcc1p2_voltage_s1_agent_m0_lock),                                  //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_vcc1p2_voltage_s1_agent_m0_debugaccess),                           //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_vcc1p2_voltage_s1_address),                                        //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_vcc1p2_voltage_s1_readdata),                                       //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_vcc1p2_current_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_vcc1p2_current_s1_agent_m0_address),                               //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_vcc1p2_current_s1_agent_m0_burstcount),                            //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_vcc1p2_current_s1_agent_m0_read),                                  //   input,   width = 1,                         .read
		.uav_write              (board_info_vcc1p2_current_s1_agent_m0_write),                                 //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_vcc1p2_current_s1_agent_m0_waitrequest),                           //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_vcc1p2_current_s1_agent_m0_readdatavalid),                         //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_vcc1p2_current_s1_agent_m0_byteenable),                            //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_vcc1p2_current_s1_agent_m0_readdata),                              //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_vcc1p2_current_s1_agent_m0_writedata),                             //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_vcc1p2_current_s1_agent_m0_lock),                                  //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_vcc1p2_current_s1_agent_m0_debugaccess),                           //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_vcc1p2_current_s1_address),                                        //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_vcc1p2_current_s1_readdata),                                       //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_fan_speed_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_fan_speed_s1_agent_m0_address),                                    //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_fan_speed_s1_agent_m0_burstcount),                                 //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_fan_speed_s1_agent_m0_read),                                       //   input,   width = 1,                         .read
		.uav_write              (board_info_fan_speed_s1_agent_m0_write),                                      //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_fan_speed_s1_agent_m0_waitrequest),                                //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_fan_speed_s1_agent_m0_readdatavalid),                              //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_fan_speed_s1_agent_m0_byteenable),                                 //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_fan_speed_s1_agent_m0_readdata),                                   //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_fan_speed_s1_agent_m0_writedata),                                  //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_fan_speed_s1_agent_m0_lock),                                       //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_fan_speed_s1_agent_m0_debugaccess),                                //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_fan_speed_s1_address),                                             //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_fan_speed_s1_readdata),                                            //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_temperature_fpga_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_temperature_fpga_s1_agent_m0_address),                             //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_temperature_fpga_s1_agent_m0_burstcount),                          //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_temperature_fpga_s1_agent_m0_read),                                //   input,   width = 1,                         .read
		.uav_write              (board_info_temperature_fpga_s1_agent_m0_write),                               //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_temperature_fpga_s1_agent_m0_waitrequest),                         //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_temperature_fpga_s1_agent_m0_readdatavalid),                       //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_temperature_fpga_s1_agent_m0_byteenable),                          //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_temperature_fpga_s1_agent_m0_readdata),                            //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_temperature_fpga_s1_agent_m0_writedata),                           //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_temperature_fpga_s1_agent_m0_lock),                                //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_temperature_fpga_s1_agent_m0_debugaccess),                         //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_temperature_fpga_s1_address),                                      //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_temperature_fpga_s1_readdata),                                     //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_temperature_board1_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_temperature_board1_s1_agent_m0_address),                           //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_temperature_board1_s1_agent_m0_burstcount),                        //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_temperature_board1_s1_agent_m0_read),                              //   input,   width = 1,                         .read
		.uav_write              (board_info_temperature_board1_s1_agent_m0_write),                             //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_temperature_board1_s1_agent_m0_waitrequest),                       //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_temperature_board1_s1_agent_m0_readdatavalid),                     //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_temperature_board1_s1_agent_m0_byteenable),                        //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_temperature_board1_s1_agent_m0_readdata),                          //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_temperature_board1_s1_agent_m0_writedata),                         //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_temperature_board1_s1_agent_m0_lock),                              //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_temperature_board1_s1_agent_m0_debugaccess),                       //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_temperature_board1_s1_address),                                    //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_temperature_board1_s1_readdata),                                   //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_pin_status_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_pin_status_s1_agent_m0_address),                                   //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_pin_status_s1_agent_m0_burstcount),                                //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_pin_status_s1_agent_m0_read),                                      //   input,   width = 1,                         .read
		.uav_write              (board_info_pin_status_s1_agent_m0_write),                                     //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_pin_status_s1_agent_m0_waitrequest),                               //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_pin_status_s1_agent_m0_readdatavalid),                             //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_pin_status_s1_agent_m0_byteenable),                                //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_pin_status_s1_agent_m0_readdata),                                  //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_pin_status_s1_agent_m0_writedata),                                 //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_pin_status_s1_agent_m0_lock),                                      //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_pin_status_s1_agent_m0_debugaccess),                               //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_pin_status_s1_address),                                            //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_pin_status_s1_readdata),                                           //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (2),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (1),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) board_info_temperature_board2_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (board_info_temperature_board2_s1_agent_m0_address),                           //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (board_info_temperature_board2_s1_agent_m0_burstcount),                        //   input,   width = 3,                         .burstcount
		.uav_read               (board_info_temperature_board2_s1_agent_m0_read),                              //   input,   width = 1,                         .read
		.uav_write              (board_info_temperature_board2_s1_agent_m0_write),                             //   input,   width = 1,                         .write
		.uav_waitrequest        (board_info_temperature_board2_s1_agent_m0_waitrequest),                       //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (board_info_temperature_board2_s1_agent_m0_readdatavalid),                     //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (board_info_temperature_board2_s1_agent_m0_byteenable),                        //   input,   width = 4,                         .byteenable
		.uav_readdata           (board_info_temperature_board2_s1_agent_m0_readdata),                          //  output,  width = 32,                         .readdata
		.uav_writedata          (board_info_temperature_board2_s1_agent_m0_writedata),                         //   input,  width = 32,                         .writedata
		.uav_lock               (board_info_temperature_board2_s1_agent_m0_lock),                              //   input,   width = 1,                         .lock
		.uav_debugaccess        (board_info_temperature_board2_s1_agent_m0_debugaccess),                       //   input,   width = 1,                         .debugaccess
		.av_address             (board_info_temperature_board2_s1_address),                                    //  output,   width = 2,      avalon_anti_slave_0.address
		.av_readdata            (board_info_temperature_board2_s1_readdata),                                   //   input,  width = 32,                         .readdata
		.av_write               (),                                                                            // (terminated),                                       
		.av_read                (),                                                                            // (terminated),                                       
		.av_writedata           (),                                                                            // (terminated),                                       
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_byteenable          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (17),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (1),
		.USE_READDATAVALID              (0),
		.USE_WAITREQUEST                (0),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) intel_onchip_memory_s1_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (intel_onchip_memory_s1_agent_m0_address),                                     //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (intel_onchip_memory_s1_agent_m0_burstcount),                                  //   input,   width = 3,                         .burstcount
		.uav_read               (intel_onchip_memory_s1_agent_m0_read),                                        //   input,   width = 1,                         .read
		.uav_write              (intel_onchip_memory_s1_agent_m0_write),                                       //   input,   width = 1,                         .write
		.uav_waitrequest        (intel_onchip_memory_s1_agent_m0_waitrequest),                                 //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (intel_onchip_memory_s1_agent_m0_readdatavalid),                               //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (intel_onchip_memory_s1_agent_m0_byteenable),                                  //   input,   width = 4,                         .byteenable
		.uav_readdata           (intel_onchip_memory_s1_agent_m0_readdata),                                    //  output,  width = 32,                         .readdata
		.uav_writedata          (intel_onchip_memory_s1_agent_m0_writedata),                                   //   input,  width = 32,                         .writedata
		.uav_lock               (intel_onchip_memory_s1_agent_m0_lock),                                        //   input,   width = 1,                         .lock
		.uav_debugaccess        (intel_onchip_memory_s1_agent_m0_debugaccess),                                 //   input,   width = 1,                         .debugaccess
		.av_address             (intel_onchip_memory_s1_address),                                              //  output,  width = 17,      avalon_anti_slave_0.address
		.av_write               (intel_onchip_memory_s1_write),                                                //  output,   width = 1,                         .write
		.av_read                (intel_onchip_memory_s1_read),                                                 //  output,   width = 1,                         .read
		.av_readdata            (intel_onchip_memory_s1_readdata),                                             //   input,  width = 32,                         .readdata
		.av_writedata           (intel_onchip_memory_s1_writedata),                                            //  output,  width = 32,                         .writedata
		.av_byteenable          (intel_onchip_memory_s1_byteenable),                                           //  output,   width = 4,                         .byteenable
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_readdatavalid       (1'b0),                                                                        // (terminated),                                       
		.av_waitrequest         (1'b0),                                                                        // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (6),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) intel_niosv_g_timer_sw_agent_translator (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,   width = 1,                      clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1,                    reset.reset
		.uav_address            (intel_niosv_g_timer_sw_agent_agent_m0_address),                               //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (intel_niosv_g_timer_sw_agent_agent_m0_burstcount),                            //   input,   width = 3,                         .burstcount
		.uav_read               (intel_niosv_g_timer_sw_agent_agent_m0_read),                                  //   input,   width = 1,                         .read
		.uav_write              (intel_niosv_g_timer_sw_agent_agent_m0_write),                                 //   input,   width = 1,                         .write
		.uav_waitrequest        (intel_niosv_g_timer_sw_agent_agent_m0_waitrequest),                           //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (intel_niosv_g_timer_sw_agent_agent_m0_readdatavalid),                         //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (intel_niosv_g_timer_sw_agent_agent_m0_byteenable),                            //   input,   width = 4,                         .byteenable
		.uav_readdata           (intel_niosv_g_timer_sw_agent_agent_m0_readdata),                              //  output,  width = 32,                         .readdata
		.uav_writedata          (intel_niosv_g_timer_sw_agent_agent_m0_writedata),                             //   input,  width = 32,                         .writedata
		.uav_lock               (intel_niosv_g_timer_sw_agent_agent_m0_lock),                                  //   input,   width = 1,                         .lock
		.uav_debugaccess        (intel_niosv_g_timer_sw_agent_agent_m0_debugaccess),                           //   input,   width = 1,                         .debugaccess
		.av_address             (intel_niosv_g_timer_sw_agent_address),                                        //  output,   width = 6,      avalon_anti_slave_0.address
		.av_write               (intel_niosv_g_timer_sw_agent_write),                                          //  output,   width = 1,                         .write
		.av_read                (intel_niosv_g_timer_sw_agent_read),                                           //  output,   width = 1,                         .read
		.av_readdata            (intel_niosv_g_timer_sw_agent_readdata),                                       //   input,  width = 32,                         .readdata
		.av_writedata           (intel_niosv_g_timer_sw_agent_writedata),                                      //  output,  width = 32,                         .writedata
		.av_byteenable          (intel_niosv_g_timer_sw_agent_byteenable),                                     //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (intel_niosv_g_timer_sw_agent_readdatavalid),                                  //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (intel_niosv_g_timer_sw_agent_waitrequest),                                    //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                                            // (terminated),                                       
		.av_beginbursttransfer  (),                                                                            // (terminated),                                       
		.av_burstcount          (),                                                                            // (terminated),                                       
		.av_writebyteenable     (),                                                                            // (terminated),                                       
		.av_lock                (),                                                                            // (terminated),                                       
		.av_chipselect          (),                                                                            // (terminated),                                       
		.av_clken               (),                                                                            // (terminated),                                       
		.uav_clken              (1'b0),                                                                        // (terminated),                                       
		.av_debugaccess         (),                                                                            // (terminated),                                       
		.av_outputenable        (),                                                                            // (terminated),                                       
		.uav_response           (),                                                                            // (terminated),                                       
		.av_response            (2'b00),                                                                       // (terminated),                                       
		.uav_writeresponsevalid (),                                                                            // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                         // (terminated),                                       
	);

	system_altera_merlin_axi_master_ni_1980_4qd7sla #(
		.ID_WIDTH                  (1),
		.ADDR_WIDTH                (32),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (1),
		.READ_ISSUING_CAPABILITY   (1),
		.PKT_BEGIN_BURST           (99),
		.PKT_CACHE_H               (119),
		.PKT_CACHE_L               (116),
		.PKT_ADDR_SIDEBAND_H       (97),
		.PKT_ADDR_SIDEBAND_L       (97),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_THREAD_ID_H           (112),
		.PKT_THREAD_ID_L           (112),
		.PKT_QOS_L                 (100),
		.PKT_QOS_H                 (103),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_DATA_SIDEBAND_H       (98),
		.PKT_DATA_SIDEBAND_L       (98),
		.PKT_DOMAIN_H              (132),
		.PKT_DOMAIN_L              (131),
		.PKT_SNOOP_H               (130),
		.PKT_SNOOP_L               (127),
		.PKT_BARRIER_H             (126),
		.PKT_BARRIER_L             (125),
		.PKT_WUNIQUE               (133),
		.PKT_EOP_OOO               (140),
		.PKT_SOP_OOO               (141),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.ID                        (0),
		.SYNC_RESET                (1)
	) intel_niosv_g_data_manager_agent (
		.aclk                   (clock_in_out_clk_clk),                                                         //   input,    width = 1,              clk.clk
		.aresetn                (~intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (intel_niosv_g_data_manager_agent_write_cp_valid),                              //  output,    width = 1,         write_cp.valid
		.write_cp_data          (intel_niosv_g_data_manager_agent_write_cp_data),                               //  output,  width = 146,                 .data
		.write_cp_startofpacket (intel_niosv_g_data_manager_agent_write_cp_startofpacket),                      //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (intel_niosv_g_data_manager_agent_write_cp_endofpacket),                        //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (intel_niosv_g_data_manager_agent_write_cp_ready),                              //   input,    width = 1,                 .ready
		.write_rp_valid         (rsp_mux_src_valid),                                                            //   input,    width = 1,         write_rp.valid
		.write_rp_data          (rsp_mux_src_data),                                                             //   input,  width = 146,                 .data
		.write_rp_channel       (rsp_mux_src_channel),                                                          //   input,   width = 14,                 .channel
		.write_rp_startofpacket (rsp_mux_src_startofpacket),                                                    //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_src_endofpacket),                                                      //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (rsp_mux_src_ready),                                                            //  output,    width = 1,                 .ready
		.read_cp_valid          (intel_niosv_g_data_manager_agent_read_cp_valid),                               //  output,    width = 1,          read_cp.valid
		.read_cp_data           (intel_niosv_g_data_manager_agent_read_cp_data),                                //  output,  width = 146,                 .data
		.read_cp_startofpacket  (intel_niosv_g_data_manager_agent_read_cp_startofpacket),                       //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (intel_niosv_g_data_manager_agent_read_cp_endofpacket),                         //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (intel_niosv_g_data_manager_agent_read_cp_ready),                               //   input,    width = 1,                 .ready
		.read_rp_valid          (rsp_mux_001_src_valid),                                                        //   input,    width = 1,          read_rp.valid
		.read_rp_data           (rsp_mux_001_src_data),                                                         //   input,  width = 146,                 .data
		.read_rp_channel        (rsp_mux_001_src_channel),                                                      //   input,   width = 14,                 .channel
		.read_rp_startofpacket  (rsp_mux_001_src_startofpacket),                                                //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_001_src_endofpacket),                                                  //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (rsp_mux_001_src_ready),                                                        //  output,    width = 1,                 .ready
		.awid                   (intel_niosv_g_data_manager_translator_m0_awid),                                //   input,    width = 1, altera_axi_slave.awid
		.awaddr                 (intel_niosv_g_data_manager_translator_m0_awaddr),                              //   input,   width = 32,                 .awaddr
		.awlen                  (intel_niosv_g_data_manager_translator_m0_awlen),                               //   input,    width = 8,                 .awlen
		.awsize                 (intel_niosv_g_data_manager_translator_m0_awsize),                              //   input,    width = 3,                 .awsize
		.awburst                (intel_niosv_g_data_manager_translator_m0_awburst),                             //   input,    width = 2,                 .awburst
		.awlock                 (intel_niosv_g_data_manager_translator_m0_awlock),                              //   input,    width = 1,                 .awlock
		.awcache                (intel_niosv_g_data_manager_translator_m0_awcache),                             //   input,    width = 4,                 .awcache
		.awprot                 (intel_niosv_g_data_manager_translator_m0_awprot),                              //   input,    width = 3,                 .awprot
		.awuser                 (intel_niosv_g_data_manager_translator_m0_awuser),                              //   input,    width = 1,                 .awuser
		.awqos                  (intel_niosv_g_data_manager_translator_m0_awqos),                               //   input,    width = 4,                 .awqos
		.awregion               (intel_niosv_g_data_manager_translator_m0_awregion),                            //   input,    width = 4,                 .awregion
		.awvalid                (intel_niosv_g_data_manager_translator_m0_awvalid),                             //   input,    width = 1,                 .awvalid
		.awready                (intel_niosv_g_data_manager_translator_m0_awready),                             //  output,    width = 1,                 .awready
		.wdata                  (intel_niosv_g_data_manager_translator_m0_wdata),                               //   input,   width = 32,                 .wdata
		.wstrb                  (intel_niosv_g_data_manager_translator_m0_wstrb),                               //   input,    width = 4,                 .wstrb
		.wlast                  (intel_niosv_g_data_manager_translator_m0_wlast),                               //   input,    width = 1,                 .wlast
		.wvalid                 (intel_niosv_g_data_manager_translator_m0_wvalid),                              //   input,    width = 1,                 .wvalid
		.wuser                  (intel_niosv_g_data_manager_translator_m0_wuser),                               //   input,    width = 1,                 .wuser
		.wready                 (intel_niosv_g_data_manager_translator_m0_wready),                              //  output,    width = 1,                 .wready
		.bid                    (intel_niosv_g_data_manager_translator_m0_bid),                                 //  output,    width = 1,                 .bid
		.bresp                  (intel_niosv_g_data_manager_translator_m0_bresp),                               //  output,    width = 2,                 .bresp
		.buser                  (intel_niosv_g_data_manager_translator_m0_buser),                               //  output,    width = 1,                 .buser
		.bvalid                 (intel_niosv_g_data_manager_translator_m0_bvalid),                              //  output,    width = 1,                 .bvalid
		.bready                 (intel_niosv_g_data_manager_translator_m0_bready),                              //   input,    width = 1,                 .bready
		.arid                   (intel_niosv_g_data_manager_translator_m0_arid),                                //   input,    width = 1,                 .arid
		.araddr                 (intel_niosv_g_data_manager_translator_m0_araddr),                              //   input,   width = 32,                 .araddr
		.arlen                  (intel_niosv_g_data_manager_translator_m0_arlen),                               //   input,    width = 8,                 .arlen
		.arsize                 (intel_niosv_g_data_manager_translator_m0_arsize),                              //   input,    width = 3,                 .arsize
		.arburst                (intel_niosv_g_data_manager_translator_m0_arburst),                             //   input,    width = 2,                 .arburst
		.arlock                 (intel_niosv_g_data_manager_translator_m0_arlock),                              //   input,    width = 1,                 .arlock
		.arcache                (intel_niosv_g_data_manager_translator_m0_arcache),                             //   input,    width = 4,                 .arcache
		.arprot                 (intel_niosv_g_data_manager_translator_m0_arprot),                              //   input,    width = 3,                 .arprot
		.aruser                 (intel_niosv_g_data_manager_translator_m0_aruser),                              //   input,    width = 1,                 .aruser
		.arqos                  (intel_niosv_g_data_manager_translator_m0_arqos),                               //   input,    width = 4,                 .arqos
		.arregion               (intel_niosv_g_data_manager_translator_m0_arregion),                            //   input,    width = 4,                 .arregion
		.arvalid                (intel_niosv_g_data_manager_translator_m0_arvalid),                             //   input,    width = 1,                 .arvalid
		.arready                (intel_niosv_g_data_manager_translator_m0_arready),                             //  output,    width = 1,                 .arready
		.rid                    (intel_niosv_g_data_manager_translator_m0_rid),                                 //  output,    width = 1,                 .rid
		.rdata                  (intel_niosv_g_data_manager_translator_m0_rdata),                               //  output,   width = 32,                 .rdata
		.rresp                  (intel_niosv_g_data_manager_translator_m0_rresp),                               //  output,    width = 2,                 .rresp
		.rlast                  (intel_niosv_g_data_manager_translator_m0_rlast),                               //  output,    width = 1,                 .rlast
		.rvalid                 (intel_niosv_g_data_manager_translator_m0_rvalid),                              //  output,    width = 1,                 .rvalid
		.rready                 (intel_niosv_g_data_manager_translator_m0_rready),                              //   input,    width = 1,                 .rready
		.ruser                  (intel_niosv_g_data_manager_translator_m0_ruser),                               //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                                                         // (terminated),                                
		.awuser_sai             (1'b0),                                                                         // (terminated),                                
		.wuser_datachk          (4'b0000),                                                                      // (terminated),                                
		.wuser_data             (1'b0),                                                                         // (terminated),                                
		.wuser_poison           (1'b0),                                                                         // (terminated),                                
		.aruser_addrchk         (1'b0),                                                                         // (terminated),                                
		.aruser_sai             (1'b0),                                                                         // (terminated),                                
		.ruser_datachk          (),                                                                             // (terminated),                                
		.ruser_data             (),                                                                             // (terminated),                                
		.ruser_poison           (),                                                                             // (terminated),                                
		.wid                    (1'b0),                                                                         // (terminated),                                
		.arsnoop                (4'b0000),                                                                      // (terminated),                                
		.ardomain               (2'b00),                                                                        // (terminated),                                
		.arbar                  (2'b00),                                                                        // (terminated),                                
		.awsnoop                (3'b000),                                                                       // (terminated),                                
		.awdomain               (2'b00),                                                                        // (terminated),                                
		.awbar                  (2'b00),                                                                        // (terminated),                                
		.awunique               (1'b0)                                                                          // (terminated),                                
	);

	system_altera_merlin_axi_master_ni_1980_4qd7sla #(
		.ID_WIDTH                  (1),
		.ADDR_WIDTH                (32),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (1),
		.READ_ISSUING_CAPABILITY   (8),
		.PKT_BEGIN_BURST           (99),
		.PKT_CACHE_H               (119),
		.PKT_CACHE_L               (116),
		.PKT_ADDR_SIDEBAND_H       (97),
		.PKT_ADDR_SIDEBAND_L       (97),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (73),
		.PKT_TRANS_LOCK            (72),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_THREAD_ID_H           (112),
		.PKT_THREAD_ID_L           (112),
		.PKT_QOS_L                 (100),
		.PKT_QOS_H                 (103),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_DATA_SIDEBAND_H       (98),
		.PKT_DATA_SIDEBAND_L       (98),
		.PKT_DOMAIN_H              (132),
		.PKT_DOMAIN_L              (131),
		.PKT_SNOOP_H               (130),
		.PKT_SNOOP_L               (127),
		.PKT_BARRIER_H             (126),
		.PKT_BARRIER_L             (125),
		.PKT_WUNIQUE               (133),
		.PKT_EOP_OOO               (140),
		.PKT_SOP_OOO               (141),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.ID                        (1),
		.SYNC_RESET                (1)
	) intel_niosv_g_instruction_manager_agent (
		.aclk                   (clock_in_out_clk_clk),                                                         //   input,    width = 1,              clk.clk
		.aresetn                (~intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (intel_niosv_g_instruction_manager_agent_write_cp_valid),                       //  output,    width = 1,         write_cp.valid
		.write_cp_data          (intel_niosv_g_instruction_manager_agent_write_cp_data),                        //  output,  width = 146,                 .data
		.write_cp_startofpacket (intel_niosv_g_instruction_manager_agent_write_cp_startofpacket),               //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (intel_niosv_g_instruction_manager_agent_write_cp_endofpacket),                 //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (intel_niosv_g_instruction_manager_agent_write_cp_ready),                       //   input,    width = 1,                 .ready
		.write_rp_valid         (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_valid),                   //   input,    width = 1,         write_rp.valid
		.write_rp_data          (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_data),                    //   input,  width = 146,                 .data
		.write_rp_channel       (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_channel),                 //   input,   width = 14,                 .channel
		.write_rp_startofpacket (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_startofpacket),           //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_endofpacket),             //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_ready),                   //  output,    width = 1,                 .ready
		.read_cp_valid          (intel_niosv_g_instruction_manager_agent_read_cp_valid),                        //  output,    width = 1,          read_cp.valid
		.read_cp_data           (intel_niosv_g_instruction_manager_agent_read_cp_data),                         //  output,  width = 146,                 .data
		.read_cp_startofpacket  (intel_niosv_g_instruction_manager_agent_read_cp_startofpacket),                //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (intel_niosv_g_instruction_manager_agent_read_cp_endofpacket),                  //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (intel_niosv_g_instruction_manager_agent_read_cp_ready),                        //   input,    width = 1,                 .ready
		.read_rp_valid          (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_valid),                   //   input,    width = 1,          read_rp.valid
		.read_rp_data           (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_data),                    //   input,  width = 146,                 .data
		.read_rp_channel        (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_channel),                 //   input,   width = 14,                 .channel
		.read_rp_startofpacket  (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_startofpacket),           //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_endofpacket),             //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_ready),                   //  output,    width = 1,                 .ready
		.awid                   (intel_niosv_g_instruction_manager_translator_m0_awid),                         //   input,    width = 1, altera_axi_slave.awid
		.awaddr                 (intel_niosv_g_instruction_manager_translator_m0_awaddr),                       //   input,   width = 32,                 .awaddr
		.awlen                  (intel_niosv_g_instruction_manager_translator_m0_awlen),                        //   input,    width = 8,                 .awlen
		.awsize                 (intel_niosv_g_instruction_manager_translator_m0_awsize),                       //   input,    width = 3,                 .awsize
		.awburst                (intel_niosv_g_instruction_manager_translator_m0_awburst),                      //   input,    width = 2,                 .awburst
		.awlock                 (intel_niosv_g_instruction_manager_translator_m0_awlock),                       //   input,    width = 1,                 .awlock
		.awcache                (intel_niosv_g_instruction_manager_translator_m0_awcache),                      //   input,    width = 4,                 .awcache
		.awprot                 (intel_niosv_g_instruction_manager_translator_m0_awprot),                       //   input,    width = 3,                 .awprot
		.awuser                 (intel_niosv_g_instruction_manager_translator_m0_awuser),                       //   input,    width = 1,                 .awuser
		.awqos                  (intel_niosv_g_instruction_manager_translator_m0_awqos),                        //   input,    width = 4,                 .awqos
		.awregion               (intel_niosv_g_instruction_manager_translator_m0_awregion),                     //   input,    width = 4,                 .awregion
		.awvalid                (intel_niosv_g_instruction_manager_translator_m0_awvalid),                      //   input,    width = 1,                 .awvalid
		.awready                (intel_niosv_g_instruction_manager_translator_m0_awready),                      //  output,    width = 1,                 .awready
		.wdata                  (intel_niosv_g_instruction_manager_translator_m0_wdata),                        //   input,   width = 32,                 .wdata
		.wstrb                  (intel_niosv_g_instruction_manager_translator_m0_wstrb),                        //   input,    width = 4,                 .wstrb
		.wlast                  (intel_niosv_g_instruction_manager_translator_m0_wlast),                        //   input,    width = 1,                 .wlast
		.wvalid                 (intel_niosv_g_instruction_manager_translator_m0_wvalid),                       //   input,    width = 1,                 .wvalid
		.wuser                  (intel_niosv_g_instruction_manager_translator_m0_wuser),                        //   input,    width = 1,                 .wuser
		.wready                 (intel_niosv_g_instruction_manager_translator_m0_wready),                       //  output,    width = 1,                 .wready
		.bid                    (intel_niosv_g_instruction_manager_translator_m0_bid),                          //  output,    width = 1,                 .bid
		.bresp                  (intel_niosv_g_instruction_manager_translator_m0_bresp),                        //  output,    width = 2,                 .bresp
		.buser                  (intel_niosv_g_instruction_manager_translator_m0_buser),                        //  output,    width = 1,                 .buser
		.bvalid                 (intel_niosv_g_instruction_manager_translator_m0_bvalid),                       //  output,    width = 1,                 .bvalid
		.bready                 (intel_niosv_g_instruction_manager_translator_m0_bready),                       //   input,    width = 1,                 .bready
		.arid                   (intel_niosv_g_instruction_manager_translator_m0_arid),                         //   input,    width = 1,                 .arid
		.araddr                 (intel_niosv_g_instruction_manager_translator_m0_araddr),                       //   input,   width = 32,                 .araddr
		.arlen                  (intel_niosv_g_instruction_manager_translator_m0_arlen),                        //   input,    width = 8,                 .arlen
		.arsize                 (intel_niosv_g_instruction_manager_translator_m0_arsize),                       //   input,    width = 3,                 .arsize
		.arburst                (intel_niosv_g_instruction_manager_translator_m0_arburst),                      //   input,    width = 2,                 .arburst
		.arlock                 (intel_niosv_g_instruction_manager_translator_m0_arlock),                       //   input,    width = 1,                 .arlock
		.arcache                (intel_niosv_g_instruction_manager_translator_m0_arcache),                      //   input,    width = 4,                 .arcache
		.arprot                 (intel_niosv_g_instruction_manager_translator_m0_arprot),                       //   input,    width = 3,                 .arprot
		.aruser                 (intel_niosv_g_instruction_manager_translator_m0_aruser),                       //   input,    width = 1,                 .aruser
		.arqos                  (intel_niosv_g_instruction_manager_translator_m0_arqos),                        //   input,    width = 4,                 .arqos
		.arregion               (intel_niosv_g_instruction_manager_translator_m0_arregion),                     //   input,    width = 4,                 .arregion
		.arvalid                (intel_niosv_g_instruction_manager_translator_m0_arvalid),                      //   input,    width = 1,                 .arvalid
		.arready                (intel_niosv_g_instruction_manager_translator_m0_arready),                      //  output,    width = 1,                 .arready
		.rid                    (intel_niosv_g_instruction_manager_translator_m0_rid),                          //  output,    width = 1,                 .rid
		.rdata                  (intel_niosv_g_instruction_manager_translator_m0_rdata),                        //  output,   width = 32,                 .rdata
		.rresp                  (intel_niosv_g_instruction_manager_translator_m0_rresp),                        //  output,    width = 2,                 .rresp
		.rlast                  (intel_niosv_g_instruction_manager_translator_m0_rlast),                        //  output,    width = 1,                 .rlast
		.rvalid                 (intel_niosv_g_instruction_manager_translator_m0_rvalid),                       //  output,    width = 1,                 .rvalid
		.rready                 (intel_niosv_g_instruction_manager_translator_m0_rready),                       //   input,    width = 1,                 .rready
		.ruser                  (intel_niosv_g_instruction_manager_translator_m0_ruser),                        //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                                                         // (terminated),                                
		.awuser_sai             (1'b0),                                                                         // (terminated),                                
		.wuser_datachk          (4'b0000),                                                                      // (terminated),                                
		.wuser_data             (1'b0),                                                                         // (terminated),                                
		.wuser_poison           (1'b0),                                                                         // (terminated),                                
		.aruser_addrchk         (1'b0),                                                                         // (terminated),                                
		.aruser_sai             (1'b0),                                                                         // (terminated),                                
		.ruser_datachk          (),                                                                             // (terminated),                                
		.ruser_data             (),                                                                             // (terminated),                                
		.ruser_poison           (),                                                                             // (terminated),                                
		.wid                    (1'b0),                                                                         // (terminated),                                
		.arsnoop                (4'b0000),                                                                      // (terminated),                                
		.ardomain               (2'b00),                                                                        // (terminated),                                
		.arbar                  (2'b00),                                                                        // (terminated),                                
		.awsnoop                (3'b000),                                                                       // (terminated),                                
		.awdomain               (2'b00),                                                                        // (terminated),                                
		.awbar                  (2'b00),                                                                        // (terminated),                                
		.awunique               (1'b0)                                                                          // (terminated),                                
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) jtag_uart_avalon_jtag_slave_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (jtag_uart_avalon_jtag_slave_agent_m0_address),                                //  output,   width = 32,              m0.address
		.m0_burstcount           (jtag_uart_avalon_jtag_slave_agent_m0_burstcount),                             //  output,    width = 3,                .burstcount
		.m0_byteenable           (jtag_uart_avalon_jtag_slave_agent_m0_byteenable),                             //  output,    width = 4,                .byteenable
		.m0_debugaccess          (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess),                            //  output,    width = 1,                .debugaccess
		.m0_lock                 (jtag_uart_avalon_jtag_slave_agent_m0_lock),                                   //  output,    width = 1,                .lock
		.m0_readdata             (jtag_uart_avalon_jtag_slave_agent_m0_readdata),                               //   input,   width = 32,                .readdata
		.m0_readdatavalid        (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid),                          //   input,    width = 1,                .readdatavalid
		.m0_read                 (jtag_uart_avalon_jtag_slave_agent_m0_read),                                   //  output,    width = 1,                .read
		.m0_waitrequest          (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest),                            //   input,    width = 1,                .waitrequest
		.m0_writedata            (jtag_uart_avalon_jtag_slave_agent_m0_writedata),                              //  output,   width = 32,                .writedata
		.m0_write                (jtag_uart_avalon_jtag_slave_agent_m0_write),                                  //  output,    width = 1,                .write
		.rp_endofpacket          (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),                            //  output,    width = 1,              rp.endofpacket
		.rp_ready                (jtag_uart_avalon_jtag_slave_agent_rp_ready),                                  //   input,    width = 1,                .ready
		.rp_valid                (jtag_uart_avalon_jtag_slave_agent_rp_valid),                                  //  output,    width = 1,                .valid
		.rp_data                 (jtag_uart_avalon_jtag_slave_agent_rp_data),                                   //  output,  width = 146,                .data
		.rp_startofpacket        (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),                          //  output,    width = 1,                .startofpacket
		.cp_ready                (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready),                     //  output,    width = 1,              cp.ready
		.cp_valid                (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid),                     //   input,    width = 1,                .valid
		.cp_data                 (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data),                      //   input,  width = 146,                .data
		.cp_startofpacket        (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket),             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket),               //   input,    width = 1,                .endofpacket
		.cp_channel              (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel),                   //   input,   width = 14,                .channel
		.rf_sink_ready           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),                        //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),                        //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket),                //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),                  //   input,    width = 1,                .endofpacket
		.rf_sink_data            (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),                         //   input,  width = 147,                .data
		.rf_source_ready         (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),                           //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),                           //  output,    width = 1,                .valid
		.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),                   //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),                     //  output,    width = 1,                .endofpacket
		.rf_source_data          (jtag_uart_avalon_jtag_slave_agent_rf_source_data),                            //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready),                      //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid),                      //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data),                       //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready),                      //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid),                      //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),                       //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                         //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),              //   input,    width = 1, clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                        // (terminated),                         
		.csr_read          (1'b0),                                                         // (terminated),                         
		.csr_write         (1'b0),                                                         // (terminated),                         
		.csr_readdata      (),                                                             // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                         // (terminated),                         
		.almost_full_data  (),                                                             // (terminated),                         
		.almost_empty_data (),                                                             // (terminated),                         
		.in_empty          (1'b0),                                                         // (terminated),                         
		.out_empty         (),                                                             // (terminated),                         
		.in_error          (1'b0),                                                         // (terminated),                         
		.out_error         (),                                                             // (terminated),                         
		.in_channel        (1'b0),                                                         // (terminated),                         
		.out_channel       ()                                                              // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) jtag_uart_avalon_jtag_slave_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                   //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),        //   input,   width = 1, clk_reset.reset
		.in_data           (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                  // (terminated),                        
		.csr_read          (1'b0),                                                   // (terminated),                        
		.csr_write         (1'b0),                                                   // (terminated),                        
		.csr_readdata      (),                                                       // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                   // (terminated),                        
		.almost_full_data  (),                                                       // (terminated),                        
		.almost_empty_data (),                                                       // (terminated),                        
		.in_startofpacket  (1'b0),                                                   // (terminated),                        
		.in_endofpacket    (1'b0),                                                   // (terminated),                        
		.out_startofpacket (),                                                       // (terminated),                        
		.out_endofpacket   (),                                                       // (terminated),                        
		.in_empty          (1'b0),                                                   // (terminated),                        
		.out_empty         (),                                                       // (terminated),                        
		.in_error          (1'b0),                                                   // (terminated),                        
		.out_error         (),                                                       // (terminated),                        
		.in_channel        (1'b0),                                                   // (terminated),                        
		.out_channel       ()                                                        // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) sysid_qsys_control_slave_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (sysid_qsys_control_slave_agent_m0_address),                                   //  output,   width = 32,              m0.address
		.m0_burstcount           (sysid_qsys_control_slave_agent_m0_burstcount),                                //  output,    width = 3,                .burstcount
		.m0_byteenable           (sysid_qsys_control_slave_agent_m0_byteenable),                                //  output,    width = 4,                .byteenable
		.m0_debugaccess          (sysid_qsys_control_slave_agent_m0_debugaccess),                               //  output,    width = 1,                .debugaccess
		.m0_lock                 (sysid_qsys_control_slave_agent_m0_lock),                                      //  output,    width = 1,                .lock
		.m0_readdata             (sysid_qsys_control_slave_agent_m0_readdata),                                  //   input,   width = 32,                .readdata
		.m0_readdatavalid        (sysid_qsys_control_slave_agent_m0_readdatavalid),                             //   input,    width = 1,                .readdatavalid
		.m0_read                 (sysid_qsys_control_slave_agent_m0_read),                                      //  output,    width = 1,                .read
		.m0_waitrequest          (sysid_qsys_control_slave_agent_m0_waitrequest),                               //   input,    width = 1,                .waitrequest
		.m0_writedata            (sysid_qsys_control_slave_agent_m0_writedata),                                 //  output,   width = 32,                .writedata
		.m0_write                (sysid_qsys_control_slave_agent_m0_write),                                     //  output,    width = 1,                .write
		.rp_endofpacket          (sysid_qsys_control_slave_agent_rp_endofpacket),                               //  output,    width = 1,              rp.endofpacket
		.rp_ready                (sysid_qsys_control_slave_agent_rp_ready),                                     //   input,    width = 1,                .ready
		.rp_valid                (sysid_qsys_control_slave_agent_rp_valid),                                     //  output,    width = 1,                .valid
		.rp_data                 (sysid_qsys_control_slave_agent_rp_data),                                      //  output,  width = 146,                .data
		.rp_startofpacket        (sysid_qsys_control_slave_agent_rp_startofpacket),                             //  output,    width = 1,                .startofpacket
		.cp_ready                (sysid_qsys_control_slave_burst_adapter_source0_ready),                        //  output,    width = 1,              cp.ready
		.cp_valid                (sysid_qsys_control_slave_burst_adapter_source0_valid),                        //   input,    width = 1,                .valid
		.cp_data                 (sysid_qsys_control_slave_burst_adapter_source0_data),                         //   input,  width = 146,                .data
		.cp_startofpacket        (sysid_qsys_control_slave_burst_adapter_source0_startofpacket),                //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (sysid_qsys_control_slave_burst_adapter_source0_endofpacket),                  //   input,    width = 1,                .endofpacket
		.cp_channel              (sysid_qsys_control_slave_burst_adapter_source0_channel),                      //   input,   width = 14,                .channel
		.rf_sink_ready           (sysid_qsys_control_slave_agent_rsp_fifo_out_ready),                           //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (sysid_qsys_control_slave_agent_rsp_fifo_out_valid),                           //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket),                   //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket),                     //   input,    width = 1,                .endofpacket
		.rf_sink_data            (sysid_qsys_control_slave_agent_rsp_fifo_out_data),                            //   input,  width = 147,                .data
		.rf_source_ready         (sysid_qsys_control_slave_agent_rf_source_ready),                              //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (sysid_qsys_control_slave_agent_rf_source_valid),                              //  output,    width = 1,                .valid
		.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket),                      //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (sysid_qsys_control_slave_agent_rf_source_endofpacket),                        //  output,    width = 1,                .endofpacket
		.rf_source_data          (sysid_qsys_control_slave_agent_rf_source_data),                               //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (sysid_qsys_control_slave_agent_rdata_fifo_out_ready),                         //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (sysid_qsys_control_slave_agent_rdata_fifo_out_valid),                         //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (sysid_qsys_control_slave_agent_rdata_fifo_out_data),                          //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (sysid_qsys_control_slave_agent_rdata_fifo_src_ready),                         //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (sysid_qsys_control_slave_agent_rdata_fifo_src_valid),                         //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (sysid_qsys_control_slave_agent_rdata_fifo_src_data),                          //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) sysid_qsys_control_slave_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (sysid_qsys_control_slave_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (sysid_qsys_control_slave_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (sysid_qsys_control_slave_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (sysid_qsys_control_slave_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (sysid_qsys_control_slave_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (sysid_qsys_control_slave_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (sysid_qsys_control_slave_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (sysid_qsys_control_slave_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated),                         
		.csr_read          (1'b0),                                                      // (terminated),                         
		.csr_write         (1'b0),                                                      // (terminated),                         
		.csr_readdata      (),                                                          // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated),                         
		.almost_full_data  (),                                                          // (terminated),                         
		.almost_empty_data (),                                                          // (terminated),                         
		.in_empty          (1'b0),                                                      // (terminated),                         
		.out_empty         (),                                                          // (terminated),                         
		.in_error          (1'b0),                                                      // (terminated),                         
		.out_error         (),                                                          // (terminated),                         
		.in_channel        (1'b0),                                                      // (terminated),                         
		.out_channel       ()                                                           // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) sysid_qsys_control_slave_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),     //   input,   width = 1, clk_reset.reset
		.in_data           (sysid_qsys_control_slave_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (sysid_qsys_control_slave_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (sysid_qsys_control_slave_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (sysid_qsys_control_slave_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                               // (terminated),                        
		.csr_read          (1'b0),                                                // (terminated),                        
		.csr_write         (1'b0),                                                // (terminated),                        
		.csr_readdata      (),                                                    // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated),                        
		.almost_full_data  (),                                                    // (terminated),                        
		.almost_empty_data (),                                                    // (terminated),                        
		.in_startofpacket  (1'b0),                                                // (terminated),                        
		.in_endofpacket    (1'b0),                                                // (terminated),                        
		.out_startofpacket (),                                                    // (terminated),                        
		.out_endofpacket   (),                                                    // (terminated),                        
		.in_empty          (1'b0),                                                // (terminated),                        
		.out_empty         (),                                                    // (terminated),                        
		.in_error          (1'b0),                                                // (terminated),                        
		.out_error         (),                                                    // (terminated),                        
		.in_channel        (1'b0),                                                // (terminated),                        
		.out_channel       ()                                                     // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) intel_niosv_g_dm_agent_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (intel_niosv_g_dm_agent_agent_m0_address),                                     //  output,   width = 32,              m0.address
		.m0_burstcount           (intel_niosv_g_dm_agent_agent_m0_burstcount),                                  //  output,    width = 3,                .burstcount
		.m0_byteenable           (intel_niosv_g_dm_agent_agent_m0_byteenable),                                  //  output,    width = 4,                .byteenable
		.m0_debugaccess          (intel_niosv_g_dm_agent_agent_m0_debugaccess),                                 //  output,    width = 1,                .debugaccess
		.m0_lock                 (intel_niosv_g_dm_agent_agent_m0_lock),                                        //  output,    width = 1,                .lock
		.m0_readdata             (intel_niosv_g_dm_agent_agent_m0_readdata),                                    //   input,   width = 32,                .readdata
		.m0_readdatavalid        (intel_niosv_g_dm_agent_agent_m0_readdatavalid),                               //   input,    width = 1,                .readdatavalid
		.m0_read                 (intel_niosv_g_dm_agent_agent_m0_read),                                        //  output,    width = 1,                .read
		.m0_waitrequest          (intel_niosv_g_dm_agent_agent_m0_waitrequest),                                 //   input,    width = 1,                .waitrequest
		.m0_writedata            (intel_niosv_g_dm_agent_agent_m0_writedata),                                   //  output,   width = 32,                .writedata
		.m0_write                (intel_niosv_g_dm_agent_agent_m0_write),                                       //  output,    width = 1,                .write
		.rp_endofpacket          (intel_niosv_g_dm_agent_agent_rp_endofpacket),                                 //  output,    width = 1,              rp.endofpacket
		.rp_ready                (intel_niosv_g_dm_agent_agent_rp_ready),                                       //   input,    width = 1,                .ready
		.rp_valid                (intel_niosv_g_dm_agent_agent_rp_valid),                                       //  output,    width = 1,                .valid
		.rp_data                 (intel_niosv_g_dm_agent_agent_rp_data),                                        //  output,  width = 146,                .data
		.rp_startofpacket        (intel_niosv_g_dm_agent_agent_rp_startofpacket),                               //  output,    width = 1,                .startofpacket
		.cp_ready                (intel_niosv_g_dm_agent_burst_adapter_source0_ready),                          //  output,    width = 1,              cp.ready
		.cp_valid                (intel_niosv_g_dm_agent_burst_adapter_source0_valid),                          //   input,    width = 1,                .valid
		.cp_data                 (intel_niosv_g_dm_agent_burst_adapter_source0_data),                           //   input,  width = 146,                .data
		.cp_startofpacket        (intel_niosv_g_dm_agent_burst_adapter_source0_startofpacket),                  //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (intel_niosv_g_dm_agent_burst_adapter_source0_endofpacket),                    //   input,    width = 1,                .endofpacket
		.cp_channel              (intel_niosv_g_dm_agent_burst_adapter_source0_channel),                        //   input,   width = 14,                .channel
		.rf_sink_ready           (intel_niosv_g_dm_agent_agent_rsp_fifo_out_ready),                             //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (intel_niosv_g_dm_agent_agent_rsp_fifo_out_valid),                             //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (intel_niosv_g_dm_agent_agent_rsp_fifo_out_startofpacket),                     //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (intel_niosv_g_dm_agent_agent_rsp_fifo_out_endofpacket),                       //   input,    width = 1,                .endofpacket
		.rf_sink_data            (intel_niosv_g_dm_agent_agent_rsp_fifo_out_data),                              //   input,  width = 147,                .data
		.rf_source_ready         (intel_niosv_g_dm_agent_agent_rf_source_ready),                                //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (intel_niosv_g_dm_agent_agent_rf_source_valid),                                //  output,    width = 1,                .valid
		.rf_source_startofpacket (intel_niosv_g_dm_agent_agent_rf_source_startofpacket),                        //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (intel_niosv_g_dm_agent_agent_rf_source_endofpacket),                          //  output,    width = 1,                .endofpacket
		.rf_source_data          (intel_niosv_g_dm_agent_agent_rf_source_data),                                 //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (intel_niosv_g_dm_agent_agent_rdata_fifo_out_ready),                           //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (intel_niosv_g_dm_agent_agent_rdata_fifo_out_valid),                           //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (intel_niosv_g_dm_agent_agent_rdata_fifo_out_data),                            //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (intel_niosv_g_dm_agent_agent_rdata_fifo_src_ready),                           //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (intel_niosv_g_dm_agent_agent_rdata_fifo_src_valid),                           //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (intel_niosv_g_dm_agent_agent_rdata_fifo_src_data),                            //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) intel_niosv_g_dm_agent_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, clk_reset.reset
		.in_data           (intel_niosv_g_dm_agent_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (intel_niosv_g_dm_agent_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (intel_niosv_g_dm_agent_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (intel_niosv_g_dm_agent_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (intel_niosv_g_dm_agent_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (intel_niosv_g_dm_agent_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (intel_niosv_g_dm_agent_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (intel_niosv_g_dm_agent_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (intel_niosv_g_dm_agent_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (intel_niosv_g_dm_agent_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                   // (terminated),                         
		.csr_read          (1'b0),                                                    // (terminated),                         
		.csr_write         (1'b0),                                                    // (terminated),                         
		.csr_readdata      (),                                                        // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated),                         
		.almost_full_data  (),                                                        // (terminated),                         
		.almost_empty_data (),                                                        // (terminated),                         
		.in_empty          (1'b0),                                                    // (terminated),                         
		.out_empty         (),                                                        // (terminated),                         
		.in_error          (1'b0),                                                    // (terminated),                         
		.out_error         (),                                                        // (terminated),                         
		.in_channel        (1'b0),                                                    // (terminated),                         
		.out_channel       ()                                                         // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (3),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) intel_niosv_g_dm_agent_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                              //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),   //   input,   width = 1, clk_reset.reset
		.in_data           (intel_niosv_g_dm_agent_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (intel_niosv_g_dm_agent_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (intel_niosv_g_dm_agent_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (intel_niosv_g_dm_agent_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (intel_niosv_g_dm_agent_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (intel_niosv_g_dm_agent_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                             // (terminated),                        
		.csr_read          (1'b0),                                              // (terminated),                        
		.csr_write         (1'b0),                                              // (terminated),                        
		.csr_readdata      (),                                                  // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated),                        
		.almost_full_data  (),                                                  // (terminated),                        
		.almost_empty_data (),                                                  // (terminated),                        
		.in_startofpacket  (1'b0),                                              // (terminated),                        
		.in_endofpacket    (1'b0),                                              // (terminated),                        
		.out_startofpacket (),                                                  // (terminated),                        
		.out_endofpacket   (),                                                  // (terminated),                        
		.in_empty          (1'b0),                                              // (terminated),                        
		.out_empty         (),                                                  // (terminated),                        
		.in_error          (1'b0),                                              // (terminated),                        
		.out_error         (),                                                  // (terminated),                        
		.in_channel        (1'b0),                                              // (terminated),                        
		.out_channel       ()                                                   // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) timer_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (timer_s1_agent_m0_address),                                                   //  output,   width = 32,              m0.address
		.m0_burstcount           (timer_s1_agent_m0_burstcount),                                                //  output,    width = 3,                .burstcount
		.m0_byteenable           (timer_s1_agent_m0_byteenable),                                                //  output,    width = 4,                .byteenable
		.m0_debugaccess          (timer_s1_agent_m0_debugaccess),                                               //  output,    width = 1,                .debugaccess
		.m0_lock                 (timer_s1_agent_m0_lock),                                                      //  output,    width = 1,                .lock
		.m0_readdata             (timer_s1_agent_m0_readdata),                                                  //   input,   width = 32,                .readdata
		.m0_readdatavalid        (timer_s1_agent_m0_readdatavalid),                                             //   input,    width = 1,                .readdatavalid
		.m0_read                 (timer_s1_agent_m0_read),                                                      //  output,    width = 1,                .read
		.m0_waitrequest          (timer_s1_agent_m0_waitrequest),                                               //   input,    width = 1,                .waitrequest
		.m0_writedata            (timer_s1_agent_m0_writedata),                                                 //  output,   width = 32,                .writedata
		.m0_write                (timer_s1_agent_m0_write),                                                     //  output,    width = 1,                .write
		.rp_endofpacket          (timer_s1_agent_rp_endofpacket),                                               //  output,    width = 1,              rp.endofpacket
		.rp_ready                (timer_s1_agent_rp_ready),                                                     //   input,    width = 1,                .ready
		.rp_valid                (timer_s1_agent_rp_valid),                                                     //  output,    width = 1,                .valid
		.rp_data                 (timer_s1_agent_rp_data),                                                      //  output,  width = 146,                .data
		.rp_startofpacket        (timer_s1_agent_rp_startofpacket),                                             //  output,    width = 1,                .startofpacket
		.cp_ready                (timer_s1_burst_adapter_source0_ready),                                        //  output,    width = 1,              cp.ready
		.cp_valid                (timer_s1_burst_adapter_source0_valid),                                        //   input,    width = 1,                .valid
		.cp_data                 (timer_s1_burst_adapter_source0_data),                                         //   input,  width = 146,                .data
		.cp_startofpacket        (timer_s1_burst_adapter_source0_startofpacket),                                //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (timer_s1_burst_adapter_source0_endofpacket),                                  //   input,    width = 1,                .endofpacket
		.cp_channel              (timer_s1_burst_adapter_source0_channel),                                      //   input,   width = 14,                .channel
		.rf_sink_ready           (timer_s1_agent_rsp_fifo_out_ready),                                           //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (timer_s1_agent_rsp_fifo_out_valid),                                           //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (timer_s1_agent_rsp_fifo_out_startofpacket),                                   //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (timer_s1_agent_rsp_fifo_out_endofpacket),                                     //   input,    width = 1,                .endofpacket
		.rf_sink_data            (timer_s1_agent_rsp_fifo_out_data),                                            //   input,  width = 147,                .data
		.rf_source_ready         (timer_s1_agent_rf_source_ready),                                              //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (timer_s1_agent_rf_source_valid),                                              //  output,    width = 1,                .valid
		.rf_source_startofpacket (timer_s1_agent_rf_source_startofpacket),                                      //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (timer_s1_agent_rf_source_endofpacket),                                        //  output,    width = 1,                .endofpacket
		.rf_source_data          (timer_s1_agent_rf_source_data),                                               //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (timer_s1_agent_rdata_fifo_out_ready),                                         //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (timer_s1_agent_rdata_fifo_out_valid),                                         //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (timer_s1_agent_rdata_fifo_out_data),                                          //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (timer_s1_agent_rdata_fifo_src_ready),                                         //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (timer_s1_agent_rdata_fifo_src_valid),                                         //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (timer_s1_agent_rdata_fifo_src_data),                                          //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) timer_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_data           (timer_s1_agent_rf_source_data),                   //   input,  width = 147,        in.data
		.in_valid          (timer_s1_agent_rf_source_valid),                  //   input,    width = 1,          .valid
		.in_ready          (timer_s1_agent_rf_source_ready),                  //  output,    width = 1,          .ready
		.in_startofpacket  (timer_s1_agent_rf_source_startofpacket),          //   input,    width = 1,          .startofpacket
		.in_endofpacket    (timer_s1_agent_rf_source_endofpacket),            //   input,    width = 1,          .endofpacket
		.out_data          (timer_s1_agent_rsp_fifo_out_data),                //  output,  width = 147,       out.data
		.out_valid         (timer_s1_agent_rsp_fifo_out_valid),               //  output,    width = 1,          .valid
		.out_ready         (timer_s1_agent_rsp_fifo_out_ready),               //   input,    width = 1,          .ready
		.out_startofpacket (timer_s1_agent_rsp_fifo_out_startofpacket),       //  output,    width = 1,          .startofpacket
		.out_endofpacket   (timer_s1_agent_rsp_fifo_out_endofpacket),         //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                           // (terminated),                         
		.csr_read          (1'b0),                                            // (terminated),                         
		.csr_write         (1'b0),                                            // (terminated),                         
		.csr_readdata      (),                                                // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated),                         
		.almost_full_data  (),                                                // (terminated),                         
		.almost_empty_data (),                                                // (terminated),                         
		.in_empty          (1'b0),                                            // (terminated),                         
		.out_empty         (),                                                // (terminated),                         
		.in_error          (1'b0),                                            // (terminated),                         
		.out_error         (),                                                // (terminated),                         
		.in_channel        (1'b0),                                            // (terminated),                         
		.out_channel       ()                                                 // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) timer_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                            //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset
		.in_data           (timer_s1_agent_rdata_fifo_src_data),              //   input,  width = 34,        in.data
		.in_valid          (timer_s1_agent_rdata_fifo_src_valid),             //   input,   width = 1,          .valid
		.in_ready          (timer_s1_agent_rdata_fifo_src_ready),             //  output,   width = 1,          .ready
		.out_data          (timer_s1_agent_rdata_fifo_out_data),              //  output,  width = 34,       out.data
		.out_valid         (timer_s1_agent_rdata_fifo_out_valid),             //  output,   width = 1,          .valid
		.out_ready         (timer_s1_agent_rdata_fifo_out_ready),             //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                           // (terminated),                        
		.csr_read          (1'b0),                                            // (terminated),                        
		.csr_write         (1'b0),                                            // (terminated),                        
		.csr_readdata      (),                                                // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),            // (terminated),                        
		.almost_full_data  (),                                                // (terminated),                        
		.almost_empty_data (),                                                // (terminated),                        
		.in_startofpacket  (1'b0),                                            // (terminated),                        
		.in_endofpacket    (1'b0),                                            // (terminated),                        
		.out_startofpacket (),                                                // (terminated),                        
		.out_endofpacket   (),                                                // (terminated),                        
		.in_empty          (1'b0),                                            // (terminated),                        
		.out_empty         (),                                                // (terminated),                        
		.in_error          (1'b0),                                            // (terminated),                        
		.out_error         (),                                                // (terminated),                        
		.in_channel        (1'b0),                                            // (terminated),                        
		.out_channel       ()                                                 // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_power_in_voltage_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_power_in_voltage_s1_agent_m0_address),                             //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_power_in_voltage_s1_agent_m0_burstcount),                          //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_power_in_voltage_s1_agent_m0_byteenable),                          //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_power_in_voltage_s1_agent_m0_debugaccess),                         //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_power_in_voltage_s1_agent_m0_lock),                                //  output,    width = 1,                .lock
		.m0_readdata             (board_info_power_in_voltage_s1_agent_m0_readdata),                            //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_power_in_voltage_s1_agent_m0_readdatavalid),                       //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_power_in_voltage_s1_agent_m0_read),                                //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_power_in_voltage_s1_agent_m0_waitrequest),                         //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_power_in_voltage_s1_agent_m0_writedata),                           //  output,   width = 32,                .writedata
		.m0_write                (board_info_power_in_voltage_s1_agent_m0_write),                               //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_power_in_voltage_s1_agent_rp_endofpacket),                         //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_power_in_voltage_s1_agent_rp_ready),                               //   input,    width = 1,                .ready
		.rp_valid                (board_info_power_in_voltage_s1_agent_rp_valid),                               //  output,    width = 1,                .valid
		.rp_data                 (board_info_power_in_voltage_s1_agent_rp_data),                                //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_power_in_voltage_s1_agent_rp_startofpacket),                       //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_power_in_voltage_s1_burst_adapter_source0_ready),                  //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_power_in_voltage_s1_burst_adapter_source0_valid),                  //   input,    width = 1,                .valid
		.cp_data                 (board_info_power_in_voltage_s1_burst_adapter_source0_data),                   //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_power_in_voltage_s1_burst_adapter_source0_startofpacket),          //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_power_in_voltage_s1_burst_adapter_source0_endofpacket),            //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_power_in_voltage_s1_burst_adapter_source0_channel),                //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_power_in_voltage_s1_agent_rsp_fifo_out_ready),                     //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_power_in_voltage_s1_agent_rsp_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_power_in_voltage_s1_agent_rsp_fifo_out_startofpacket),             //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_power_in_voltage_s1_agent_rsp_fifo_out_endofpacket),               //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_power_in_voltage_s1_agent_rsp_fifo_out_data),                      //   input,  width = 147,                .data
		.rf_source_ready         (board_info_power_in_voltage_s1_agent_rf_source_ready),                        //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_power_in_voltage_s1_agent_rf_source_valid),                        //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_power_in_voltage_s1_agent_rf_source_startofpacket),                //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_power_in_voltage_s1_agent_rf_source_endofpacket),                  //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_power_in_voltage_s1_agent_rf_source_data),                         //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_power_in_voltage_s1_agent_rdata_fifo_out_ready),                   //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_power_in_voltage_s1_agent_rdata_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_power_in_voltage_s1_agent_rdata_fifo_out_data),                    //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_power_in_voltage_s1_agent_rdata_fifo_src_ready),                   //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_power_in_voltage_s1_agent_rdata_fifo_src_valid),                   //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_power_in_voltage_s1_agent_rdata_fifo_src_data),                    //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_power_in_voltage_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                            //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),                 //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_power_in_voltage_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_power_in_voltage_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_power_in_voltage_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_power_in_voltage_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_power_in_voltage_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_power_in_voltage_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_power_in_voltage_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_power_in_voltage_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_power_in_voltage_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_power_in_voltage_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                           // (terminated),                         
		.csr_read          (1'b0),                                                            // (terminated),                         
		.csr_write         (1'b0),                                                            // (terminated),                         
		.csr_readdata      (),                                                                // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                            // (terminated),                         
		.almost_full_data  (),                                                                // (terminated),                         
		.almost_empty_data (),                                                                // (terminated),                         
		.in_empty          (1'b0),                                                            // (terminated),                         
		.out_empty         (),                                                                // (terminated),                         
		.in_error          (1'b0),                                                            // (terminated),                         
		.out_error         (),                                                                // (terminated),                         
		.in_channel        (1'b0),                                                            // (terminated),                         
		.out_channel       ()                                                                 // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_power_in_voltage_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                      //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),           //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_power_in_voltage_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_power_in_voltage_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_power_in_voltage_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_power_in_voltage_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_power_in_voltage_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_power_in_voltage_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                     // (terminated),                        
		.csr_read          (1'b0),                                                      // (terminated),                        
		.csr_write         (1'b0),                                                      // (terminated),                        
		.csr_readdata      (),                                                          // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated),                        
		.almost_full_data  (),                                                          // (terminated),                        
		.almost_empty_data (),                                                          // (terminated),                        
		.in_startofpacket  (1'b0),                                                      // (terminated),                        
		.in_endofpacket    (1'b0),                                                      // (terminated),                        
		.out_startofpacket (),                                                          // (terminated),                        
		.out_endofpacket   (),                                                          // (terminated),                        
		.in_empty          (1'b0),                                                      // (terminated),                        
		.out_empty         (),                                                          // (terminated),                        
		.in_error          (1'b0),                                                      // (terminated),                        
		.out_error         (),                                                          // (terminated),                        
		.in_channel        (1'b0),                                                      // (terminated),                        
		.out_channel       ()                                                           // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_vcc1p2_voltage_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_vcc1p2_voltage_s1_agent_m0_address),                               //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_vcc1p2_voltage_s1_agent_m0_burstcount),                            //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_vcc1p2_voltage_s1_agent_m0_byteenable),                            //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_vcc1p2_voltage_s1_agent_m0_debugaccess),                           //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_vcc1p2_voltage_s1_agent_m0_lock),                                  //  output,    width = 1,                .lock
		.m0_readdata             (board_info_vcc1p2_voltage_s1_agent_m0_readdata),                              //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_vcc1p2_voltage_s1_agent_m0_readdatavalid),                         //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_vcc1p2_voltage_s1_agent_m0_read),                                  //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_vcc1p2_voltage_s1_agent_m0_waitrequest),                           //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_vcc1p2_voltage_s1_agent_m0_writedata),                             //  output,   width = 32,                .writedata
		.m0_write                (board_info_vcc1p2_voltage_s1_agent_m0_write),                                 //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_vcc1p2_voltage_s1_agent_rp_endofpacket),                           //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_vcc1p2_voltage_s1_agent_rp_ready),                                 //   input,    width = 1,                .ready
		.rp_valid                (board_info_vcc1p2_voltage_s1_agent_rp_valid),                                 //  output,    width = 1,                .valid
		.rp_data                 (board_info_vcc1p2_voltage_s1_agent_rp_data),                                  //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_vcc1p2_voltage_s1_agent_rp_startofpacket),                         //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_vcc1p2_voltage_s1_burst_adapter_source0_ready),                    //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_vcc1p2_voltage_s1_burst_adapter_source0_valid),                    //   input,    width = 1,                .valid
		.cp_data                 (board_info_vcc1p2_voltage_s1_burst_adapter_source0_data),                     //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_vcc1p2_voltage_s1_burst_adapter_source0_startofpacket),            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_vcc1p2_voltage_s1_burst_adapter_source0_endofpacket),              //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_vcc1p2_voltage_s1_burst_adapter_source0_channel),                  //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_ready),                       //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_valid),                       //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_startofpacket),               //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_endofpacket),                 //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_data),                        //   input,  width = 147,                .data
		.rf_source_ready         (board_info_vcc1p2_voltage_s1_agent_rf_source_ready),                          //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_vcc1p2_voltage_s1_agent_rf_source_valid),                          //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_vcc1p2_voltage_s1_agent_rf_source_startofpacket),                  //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_vcc1p2_voltage_s1_agent_rf_source_endofpacket),                    //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_vcc1p2_voltage_s1_agent_rf_source_data),                           //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_ready),                     //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_data),                      //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_ready),                     //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_valid),                     //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_data),                      //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_vcc1p2_voltage_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                          //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),               //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_vcc1p2_voltage_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_vcc1p2_voltage_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_vcc1p2_voltage_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_vcc1p2_voltage_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_vcc1p2_voltage_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_vcc1p2_voltage_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                         // (terminated),                         
		.csr_read          (1'b0),                                                          // (terminated),                         
		.csr_write         (1'b0),                                                          // (terminated),                         
		.csr_readdata      (),                                                              // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                          // (terminated),                         
		.almost_full_data  (),                                                              // (terminated),                         
		.almost_empty_data (),                                                              // (terminated),                         
		.in_empty          (1'b0),                                                          // (terminated),                         
		.out_empty         (),                                                              // (terminated),                         
		.in_error          (1'b0),                                                          // (terminated),                         
		.out_error         (),                                                              // (terminated),                         
		.in_channel        (1'b0),                                                          // (terminated),                         
		.out_channel       ()                                                               // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_vcc1p2_voltage_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                    //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),         //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_vcc1p2_voltage_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                   // (terminated),                        
		.csr_read          (1'b0),                                                    // (terminated),                        
		.csr_write         (1'b0),                                                    // (terminated),                        
		.csr_readdata      (),                                                        // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated),                        
		.almost_full_data  (),                                                        // (terminated),                        
		.almost_empty_data (),                                                        // (terminated),                        
		.in_startofpacket  (1'b0),                                                    // (terminated),                        
		.in_endofpacket    (1'b0),                                                    // (terminated),                        
		.out_startofpacket (),                                                        // (terminated),                        
		.out_endofpacket   (),                                                        // (terminated),                        
		.in_empty          (1'b0),                                                    // (terminated),                        
		.out_empty         (),                                                        // (terminated),                        
		.in_error          (1'b0),                                                    // (terminated),                        
		.out_error         (),                                                        // (terminated),                        
		.in_channel        (1'b0),                                                    // (terminated),                        
		.out_channel       ()                                                         // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_vcc1p2_current_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_vcc1p2_current_s1_agent_m0_address),                               //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_vcc1p2_current_s1_agent_m0_burstcount),                            //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_vcc1p2_current_s1_agent_m0_byteenable),                            //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_vcc1p2_current_s1_agent_m0_debugaccess),                           //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_vcc1p2_current_s1_agent_m0_lock),                                  //  output,    width = 1,                .lock
		.m0_readdata             (board_info_vcc1p2_current_s1_agent_m0_readdata),                              //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_vcc1p2_current_s1_agent_m0_readdatavalid),                         //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_vcc1p2_current_s1_agent_m0_read),                                  //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_vcc1p2_current_s1_agent_m0_waitrequest),                           //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_vcc1p2_current_s1_agent_m0_writedata),                             //  output,   width = 32,                .writedata
		.m0_write                (board_info_vcc1p2_current_s1_agent_m0_write),                                 //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_vcc1p2_current_s1_agent_rp_endofpacket),                           //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_vcc1p2_current_s1_agent_rp_ready),                                 //   input,    width = 1,                .ready
		.rp_valid                (board_info_vcc1p2_current_s1_agent_rp_valid),                                 //  output,    width = 1,                .valid
		.rp_data                 (board_info_vcc1p2_current_s1_agent_rp_data),                                  //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_vcc1p2_current_s1_agent_rp_startofpacket),                         //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_vcc1p2_current_s1_burst_adapter_source0_ready),                    //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_vcc1p2_current_s1_burst_adapter_source0_valid),                    //   input,    width = 1,                .valid
		.cp_data                 (board_info_vcc1p2_current_s1_burst_adapter_source0_data),                     //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_vcc1p2_current_s1_burst_adapter_source0_startofpacket),            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_vcc1p2_current_s1_burst_adapter_source0_endofpacket),              //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_vcc1p2_current_s1_burst_adapter_source0_channel),                  //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_ready),                       //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_valid),                       //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_startofpacket),               //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_endofpacket),                 //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_data),                        //   input,  width = 147,                .data
		.rf_source_ready         (board_info_vcc1p2_current_s1_agent_rf_source_ready),                          //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_vcc1p2_current_s1_agent_rf_source_valid),                          //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_vcc1p2_current_s1_agent_rf_source_startofpacket),                  //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_vcc1p2_current_s1_agent_rf_source_endofpacket),                    //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_vcc1p2_current_s1_agent_rf_source_data),                           //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_vcc1p2_current_s1_agent_rdata_fifo_out_ready),                     //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_vcc1p2_current_s1_agent_rdata_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_vcc1p2_current_s1_agent_rdata_fifo_out_data),                      //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_vcc1p2_current_s1_agent_rdata_fifo_src_ready),                     //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_vcc1p2_current_s1_agent_rdata_fifo_src_valid),                     //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_vcc1p2_current_s1_agent_rdata_fifo_src_data),                      //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_vcc1p2_current_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                          //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),               //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_vcc1p2_current_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_vcc1p2_current_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_vcc1p2_current_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_vcc1p2_current_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_vcc1p2_current_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_vcc1p2_current_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                         // (terminated),                         
		.csr_read          (1'b0),                                                          // (terminated),                         
		.csr_write         (1'b0),                                                          // (terminated),                         
		.csr_readdata      (),                                                              // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                          // (terminated),                         
		.almost_full_data  (),                                                              // (terminated),                         
		.almost_empty_data (),                                                              // (terminated),                         
		.in_empty          (1'b0),                                                          // (terminated),                         
		.out_empty         (),                                                              // (terminated),                         
		.in_error          (1'b0),                                                          // (terminated),                         
		.out_error         (),                                                              // (terminated),                         
		.in_channel        (1'b0),                                                          // (terminated),                         
		.out_channel       ()                                                               // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_vcc1p2_current_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                    //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),         //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_vcc1p2_current_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_vcc1p2_current_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_vcc1p2_current_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_vcc1p2_current_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_vcc1p2_current_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_vcc1p2_current_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                   // (terminated),                        
		.csr_read          (1'b0),                                                    // (terminated),                        
		.csr_write         (1'b0),                                                    // (terminated),                        
		.csr_readdata      (),                                                        // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated),                        
		.almost_full_data  (),                                                        // (terminated),                        
		.almost_empty_data (),                                                        // (terminated),                        
		.in_startofpacket  (1'b0),                                                    // (terminated),                        
		.in_endofpacket    (1'b0),                                                    // (terminated),                        
		.out_startofpacket (),                                                        // (terminated),                        
		.out_endofpacket   (),                                                        // (terminated),                        
		.in_empty          (1'b0),                                                    // (terminated),                        
		.out_empty         (),                                                        // (terminated),                        
		.in_error          (1'b0),                                                    // (terminated),                        
		.out_error         (),                                                        // (terminated),                        
		.in_channel        (1'b0),                                                    // (terminated),                        
		.out_channel       ()                                                         // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_fan_speed_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_fan_speed_s1_agent_m0_address),                                    //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_fan_speed_s1_agent_m0_burstcount),                                 //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_fan_speed_s1_agent_m0_byteenable),                                 //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_fan_speed_s1_agent_m0_debugaccess),                                //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_fan_speed_s1_agent_m0_lock),                                       //  output,    width = 1,                .lock
		.m0_readdata             (board_info_fan_speed_s1_agent_m0_readdata),                                   //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_fan_speed_s1_agent_m0_readdatavalid),                              //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_fan_speed_s1_agent_m0_read),                                       //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_fan_speed_s1_agent_m0_waitrequest),                                //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_fan_speed_s1_agent_m0_writedata),                                  //  output,   width = 32,                .writedata
		.m0_write                (board_info_fan_speed_s1_agent_m0_write),                                      //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_fan_speed_s1_agent_rp_endofpacket),                                //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_fan_speed_s1_agent_rp_ready),                                      //   input,    width = 1,                .ready
		.rp_valid                (board_info_fan_speed_s1_agent_rp_valid),                                      //  output,    width = 1,                .valid
		.rp_data                 (board_info_fan_speed_s1_agent_rp_data),                                       //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_fan_speed_s1_agent_rp_startofpacket),                              //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_fan_speed_s1_burst_adapter_source0_ready),                         //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_fan_speed_s1_burst_adapter_source0_valid),                         //   input,    width = 1,                .valid
		.cp_data                 (board_info_fan_speed_s1_burst_adapter_source0_data),                          //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_fan_speed_s1_burst_adapter_source0_startofpacket),                 //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_fan_speed_s1_burst_adapter_source0_endofpacket),                   //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_fan_speed_s1_burst_adapter_source0_channel),                       //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_fan_speed_s1_agent_rsp_fifo_out_ready),                            //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_fan_speed_s1_agent_rsp_fifo_out_valid),                            //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_fan_speed_s1_agent_rsp_fifo_out_startofpacket),                    //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_fan_speed_s1_agent_rsp_fifo_out_endofpacket),                      //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_fan_speed_s1_agent_rsp_fifo_out_data),                             //   input,  width = 147,                .data
		.rf_source_ready         (board_info_fan_speed_s1_agent_rf_source_ready),                               //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_fan_speed_s1_agent_rf_source_valid),                               //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_fan_speed_s1_agent_rf_source_startofpacket),                       //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_fan_speed_s1_agent_rf_source_endofpacket),                         //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_fan_speed_s1_agent_rf_source_data),                                //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_fan_speed_s1_agent_rdata_fifo_out_ready),                          //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_fan_speed_s1_agent_rdata_fifo_out_valid),                          //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_fan_speed_s1_agent_rdata_fifo_out_data),                           //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_fan_speed_s1_agent_rdata_fifo_src_ready),                          //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_fan_speed_s1_agent_rdata_fifo_src_valid),                          //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_fan_speed_s1_agent_rdata_fifo_src_data),                           //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_fan_speed_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                     //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),          //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_fan_speed_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_fan_speed_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_fan_speed_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_fan_speed_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_fan_speed_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_fan_speed_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_fan_speed_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_fan_speed_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_fan_speed_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_fan_speed_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                    // (terminated),                         
		.csr_read          (1'b0),                                                     // (terminated),                         
		.csr_write         (1'b0),                                                     // (terminated),                         
		.csr_readdata      (),                                                         // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                     // (terminated),                         
		.almost_full_data  (),                                                         // (terminated),                         
		.almost_empty_data (),                                                         // (terminated),                         
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.in_error          (1'b0),                                                     // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_channel        (1'b0),                                                     // (terminated),                         
		.out_channel       ()                                                          // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_fan_speed_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                               //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),    //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_fan_speed_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_fan_speed_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_fan_speed_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_fan_speed_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_fan_speed_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_fan_speed_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                              // (terminated),                        
		.csr_read          (1'b0),                                               // (terminated),                        
		.csr_write         (1'b0),                                               // (terminated),                        
		.csr_readdata      (),                                                   // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),               // (terminated),                        
		.almost_full_data  (),                                                   // (terminated),                        
		.almost_empty_data (),                                                   // (terminated),                        
		.in_startofpacket  (1'b0),                                               // (terminated),                        
		.in_endofpacket    (1'b0),                                               // (terminated),                        
		.out_startofpacket (),                                                   // (terminated),                        
		.out_endofpacket   (),                                                   // (terminated),                        
		.in_empty          (1'b0),                                               // (terminated),                        
		.out_empty         (),                                                   // (terminated),                        
		.in_error          (1'b0),                                               // (terminated),                        
		.out_error         (),                                                   // (terminated),                        
		.in_channel        (1'b0),                                               // (terminated),                        
		.out_channel       ()                                                    // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_temperature_fpga_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_temperature_fpga_s1_agent_m0_address),                             //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_temperature_fpga_s1_agent_m0_burstcount),                          //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_temperature_fpga_s1_agent_m0_byteenable),                          //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_temperature_fpga_s1_agent_m0_debugaccess),                         //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_temperature_fpga_s1_agent_m0_lock),                                //  output,    width = 1,                .lock
		.m0_readdata             (board_info_temperature_fpga_s1_agent_m0_readdata),                            //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_temperature_fpga_s1_agent_m0_readdatavalid),                       //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_temperature_fpga_s1_agent_m0_read),                                //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_temperature_fpga_s1_agent_m0_waitrequest),                         //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_temperature_fpga_s1_agent_m0_writedata),                           //  output,   width = 32,                .writedata
		.m0_write                (board_info_temperature_fpga_s1_agent_m0_write),                               //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_temperature_fpga_s1_agent_rp_endofpacket),                         //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_temperature_fpga_s1_agent_rp_ready),                               //   input,    width = 1,                .ready
		.rp_valid                (board_info_temperature_fpga_s1_agent_rp_valid),                               //  output,    width = 1,                .valid
		.rp_data                 (board_info_temperature_fpga_s1_agent_rp_data),                                //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_temperature_fpga_s1_agent_rp_startofpacket),                       //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_temperature_fpga_s1_burst_adapter_source0_ready),                  //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_temperature_fpga_s1_burst_adapter_source0_valid),                  //   input,    width = 1,                .valid
		.cp_data                 (board_info_temperature_fpga_s1_burst_adapter_source0_data),                   //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_temperature_fpga_s1_burst_adapter_source0_startofpacket),          //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_temperature_fpga_s1_burst_adapter_source0_endofpacket),            //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_temperature_fpga_s1_burst_adapter_source0_channel),                //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_temperature_fpga_s1_agent_rsp_fifo_out_ready),                     //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_temperature_fpga_s1_agent_rsp_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_temperature_fpga_s1_agent_rsp_fifo_out_startofpacket),             //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_temperature_fpga_s1_agent_rsp_fifo_out_endofpacket),               //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_temperature_fpga_s1_agent_rsp_fifo_out_data),                      //   input,  width = 147,                .data
		.rf_source_ready         (board_info_temperature_fpga_s1_agent_rf_source_ready),                        //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_temperature_fpga_s1_agent_rf_source_valid),                        //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_temperature_fpga_s1_agent_rf_source_startofpacket),                //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_temperature_fpga_s1_agent_rf_source_endofpacket),                  //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_temperature_fpga_s1_agent_rf_source_data),                         //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_temperature_fpga_s1_agent_rdata_fifo_out_ready),                   //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_temperature_fpga_s1_agent_rdata_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_temperature_fpga_s1_agent_rdata_fifo_out_data),                    //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_temperature_fpga_s1_agent_rdata_fifo_src_ready),                   //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_temperature_fpga_s1_agent_rdata_fifo_src_valid),                   //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_temperature_fpga_s1_agent_rdata_fifo_src_data),                    //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_temperature_fpga_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                            //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),                 //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_temperature_fpga_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_temperature_fpga_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_temperature_fpga_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_temperature_fpga_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_temperature_fpga_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_temperature_fpga_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_temperature_fpga_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_temperature_fpga_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_temperature_fpga_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_temperature_fpga_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                           // (terminated),                         
		.csr_read          (1'b0),                                                            // (terminated),                         
		.csr_write         (1'b0),                                                            // (terminated),                         
		.csr_readdata      (),                                                                // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                            // (terminated),                         
		.almost_full_data  (),                                                                // (terminated),                         
		.almost_empty_data (),                                                                // (terminated),                         
		.in_empty          (1'b0),                                                            // (terminated),                         
		.out_empty         (),                                                                // (terminated),                         
		.in_error          (1'b0),                                                            // (terminated),                         
		.out_error         (),                                                                // (terminated),                         
		.in_channel        (1'b0),                                                            // (terminated),                         
		.out_channel       ()                                                                 // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_temperature_fpga_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                      //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),           //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_temperature_fpga_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_temperature_fpga_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_temperature_fpga_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_temperature_fpga_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_temperature_fpga_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_temperature_fpga_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                     // (terminated),                        
		.csr_read          (1'b0),                                                      // (terminated),                        
		.csr_write         (1'b0),                                                      // (terminated),                        
		.csr_readdata      (),                                                          // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated),                        
		.almost_full_data  (),                                                          // (terminated),                        
		.almost_empty_data (),                                                          // (terminated),                        
		.in_startofpacket  (1'b0),                                                      // (terminated),                        
		.in_endofpacket    (1'b0),                                                      // (terminated),                        
		.out_startofpacket (),                                                          // (terminated),                        
		.out_endofpacket   (),                                                          // (terminated),                        
		.in_empty          (1'b0),                                                      // (terminated),                        
		.out_empty         (),                                                          // (terminated),                        
		.in_error          (1'b0),                                                      // (terminated),                        
		.out_error         (),                                                          // (terminated),                        
		.in_channel        (1'b0),                                                      // (terminated),                        
		.out_channel       ()                                                           // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_temperature_board1_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_temperature_board1_s1_agent_m0_address),                           //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_temperature_board1_s1_agent_m0_burstcount),                        //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_temperature_board1_s1_agent_m0_byteenable),                        //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_temperature_board1_s1_agent_m0_debugaccess),                       //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_temperature_board1_s1_agent_m0_lock),                              //  output,    width = 1,                .lock
		.m0_readdata             (board_info_temperature_board1_s1_agent_m0_readdata),                          //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_temperature_board1_s1_agent_m0_readdatavalid),                     //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_temperature_board1_s1_agent_m0_read),                              //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_temperature_board1_s1_agent_m0_waitrequest),                       //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_temperature_board1_s1_agent_m0_writedata),                         //  output,   width = 32,                .writedata
		.m0_write                (board_info_temperature_board1_s1_agent_m0_write),                             //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_temperature_board1_s1_agent_rp_endofpacket),                       //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_temperature_board1_s1_agent_rp_ready),                             //   input,    width = 1,                .ready
		.rp_valid                (board_info_temperature_board1_s1_agent_rp_valid),                             //  output,    width = 1,                .valid
		.rp_data                 (board_info_temperature_board1_s1_agent_rp_data),                              //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_temperature_board1_s1_agent_rp_startofpacket),                     //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_temperature_board1_s1_burst_adapter_source0_ready),                //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_temperature_board1_s1_burst_adapter_source0_valid),                //   input,    width = 1,                .valid
		.cp_data                 (board_info_temperature_board1_s1_burst_adapter_source0_data),                 //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_temperature_board1_s1_burst_adapter_source0_startofpacket),        //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_temperature_board1_s1_burst_adapter_source0_endofpacket),          //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_temperature_board1_s1_burst_adapter_source0_channel),              //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_temperature_board1_s1_agent_rsp_fifo_out_ready),                   //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_temperature_board1_s1_agent_rsp_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_temperature_board1_s1_agent_rsp_fifo_out_startofpacket),           //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_temperature_board1_s1_agent_rsp_fifo_out_endofpacket),             //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_temperature_board1_s1_agent_rsp_fifo_out_data),                    //   input,  width = 147,                .data
		.rf_source_ready         (board_info_temperature_board1_s1_agent_rf_source_ready),                      //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_temperature_board1_s1_agent_rf_source_valid),                      //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_temperature_board1_s1_agent_rf_source_startofpacket),              //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_temperature_board1_s1_agent_rf_source_endofpacket),                //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_temperature_board1_s1_agent_rf_source_data),                       //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_temperature_board1_s1_agent_rdata_fifo_out_ready),                 //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_temperature_board1_s1_agent_rdata_fifo_out_valid),                 //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_temperature_board1_s1_agent_rdata_fifo_out_data),                  //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_temperature_board1_s1_agent_rdata_fifo_src_ready),                 //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_temperature_board1_s1_agent_rdata_fifo_src_valid),                 //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_temperature_board1_s1_agent_rdata_fifo_src_data),                  //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_temperature_board1_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                              //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),                   //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_temperature_board1_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_temperature_board1_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_temperature_board1_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_temperature_board1_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_temperature_board1_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_temperature_board1_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_temperature_board1_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_temperature_board1_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_temperature_board1_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_temperature_board1_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                             // (terminated),                         
		.csr_read          (1'b0),                                                              // (terminated),                         
		.csr_write         (1'b0),                                                              // (terminated),                         
		.csr_readdata      (),                                                                  // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                              // (terminated),                         
		.almost_full_data  (),                                                                  // (terminated),                         
		.almost_empty_data (),                                                                  // (terminated),                         
		.in_empty          (1'b0),                                                              // (terminated),                         
		.out_empty         (),                                                                  // (terminated),                         
		.in_error          (1'b0),                                                              // (terminated),                         
		.out_error         (),                                                                  // (terminated),                         
		.in_channel        (1'b0),                                                              // (terminated),                         
		.out_channel       ()                                                                   // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_temperature_board1_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                        //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),             //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_temperature_board1_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_temperature_board1_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_temperature_board1_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_temperature_board1_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_temperature_board1_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_temperature_board1_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                       // (terminated),                        
		.csr_read          (1'b0),                                                        // (terminated),                        
		.csr_write         (1'b0),                                                        // (terminated),                        
		.csr_readdata      (),                                                            // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                        // (terminated),                        
		.almost_full_data  (),                                                            // (terminated),                        
		.almost_empty_data (),                                                            // (terminated),                        
		.in_startofpacket  (1'b0),                                                        // (terminated),                        
		.in_endofpacket    (1'b0),                                                        // (terminated),                        
		.out_startofpacket (),                                                            // (terminated),                        
		.out_endofpacket   (),                                                            // (terminated),                        
		.in_empty          (1'b0),                                                        // (terminated),                        
		.out_empty         (),                                                            // (terminated),                        
		.in_error          (1'b0),                                                        // (terminated),                        
		.out_error         (),                                                            // (terminated),                        
		.in_channel        (1'b0),                                                        // (terminated),                        
		.out_channel       ()                                                             // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_pin_status_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_pin_status_s1_agent_m0_address),                                   //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_pin_status_s1_agent_m0_burstcount),                                //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_pin_status_s1_agent_m0_byteenable),                                //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_pin_status_s1_agent_m0_debugaccess),                               //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_pin_status_s1_agent_m0_lock),                                      //  output,    width = 1,                .lock
		.m0_readdata             (board_info_pin_status_s1_agent_m0_readdata),                                  //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_pin_status_s1_agent_m0_readdatavalid),                             //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_pin_status_s1_agent_m0_read),                                      //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_pin_status_s1_agent_m0_waitrequest),                               //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_pin_status_s1_agent_m0_writedata),                                 //  output,   width = 32,                .writedata
		.m0_write                (board_info_pin_status_s1_agent_m0_write),                                     //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_pin_status_s1_agent_rp_endofpacket),                               //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_pin_status_s1_agent_rp_ready),                                     //   input,    width = 1,                .ready
		.rp_valid                (board_info_pin_status_s1_agent_rp_valid),                                     //  output,    width = 1,                .valid
		.rp_data                 (board_info_pin_status_s1_agent_rp_data),                                      //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_pin_status_s1_agent_rp_startofpacket),                             //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_pin_status_s1_burst_adapter_source0_ready),                        //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_pin_status_s1_burst_adapter_source0_valid),                        //   input,    width = 1,                .valid
		.cp_data                 (board_info_pin_status_s1_burst_adapter_source0_data),                         //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_pin_status_s1_burst_adapter_source0_startofpacket),                //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_pin_status_s1_burst_adapter_source0_endofpacket),                  //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_pin_status_s1_burst_adapter_source0_channel),                      //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_pin_status_s1_agent_rsp_fifo_out_ready),                           //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_pin_status_s1_agent_rsp_fifo_out_valid),                           //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_pin_status_s1_agent_rsp_fifo_out_startofpacket),                   //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_pin_status_s1_agent_rsp_fifo_out_endofpacket),                     //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_pin_status_s1_agent_rsp_fifo_out_data),                            //   input,  width = 147,                .data
		.rf_source_ready         (board_info_pin_status_s1_agent_rf_source_ready),                              //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_pin_status_s1_agent_rf_source_valid),                              //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_pin_status_s1_agent_rf_source_startofpacket),                      //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_pin_status_s1_agent_rf_source_endofpacket),                        //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_pin_status_s1_agent_rf_source_data),                               //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_pin_status_s1_agent_rdata_fifo_out_ready),                         //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_pin_status_s1_agent_rdata_fifo_out_valid),                         //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_pin_status_s1_agent_rdata_fifo_out_data),                          //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_pin_status_s1_agent_rdata_fifo_src_ready),                         //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_pin_status_s1_agent_rdata_fifo_src_valid),                         //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_pin_status_s1_agent_rdata_fifo_src_data),                          //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_pin_status_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_pin_status_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_pin_status_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_pin_status_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_pin_status_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_pin_status_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_pin_status_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_pin_status_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_pin_status_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_pin_status_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_pin_status_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                     // (terminated),                         
		.csr_read          (1'b0),                                                      // (terminated),                         
		.csr_write         (1'b0),                                                      // (terminated),                         
		.csr_readdata      (),                                                          // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                      // (terminated),                         
		.almost_full_data  (),                                                          // (terminated),                         
		.almost_empty_data (),                                                          // (terminated),                         
		.in_empty          (1'b0),                                                      // (terminated),                         
		.out_empty         (),                                                          // (terminated),                         
		.in_error          (1'b0),                                                      // (terminated),                         
		.out_error         (),                                                          // (terminated),                         
		.in_channel        (1'b0),                                                      // (terminated),                         
		.out_channel       ()                                                           // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_pin_status_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),     //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_pin_status_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_pin_status_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_pin_status_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_pin_status_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_pin_status_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_pin_status_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                               // (terminated),                        
		.csr_read          (1'b0),                                                // (terminated),                        
		.csr_write         (1'b0),                                                // (terminated),                        
		.csr_readdata      (),                                                    // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                // (terminated),                        
		.almost_full_data  (),                                                    // (terminated),                        
		.almost_empty_data (),                                                    // (terminated),                        
		.in_startofpacket  (1'b0),                                                // (terminated),                        
		.in_endofpacket    (1'b0),                                                // (terminated),                        
		.out_startofpacket (),                                                    // (terminated),                        
		.out_endofpacket   (),                                                    // (terminated),                        
		.in_empty          (1'b0),                                                // (terminated),                        
		.out_empty         (),                                                    // (terminated),                        
		.in_error          (1'b0),                                                // (terminated),                        
		.out_error         (),                                                    // (terminated),                        
		.in_channel        (1'b0),                                                // (terminated),                        
		.out_channel       ()                                                     // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) board_info_temperature_board2_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (board_info_temperature_board2_s1_agent_m0_address),                           //  output,   width = 32,              m0.address
		.m0_burstcount           (board_info_temperature_board2_s1_agent_m0_burstcount),                        //  output,    width = 3,                .burstcount
		.m0_byteenable           (board_info_temperature_board2_s1_agent_m0_byteenable),                        //  output,    width = 4,                .byteenable
		.m0_debugaccess          (board_info_temperature_board2_s1_agent_m0_debugaccess),                       //  output,    width = 1,                .debugaccess
		.m0_lock                 (board_info_temperature_board2_s1_agent_m0_lock),                              //  output,    width = 1,                .lock
		.m0_readdata             (board_info_temperature_board2_s1_agent_m0_readdata),                          //   input,   width = 32,                .readdata
		.m0_readdatavalid        (board_info_temperature_board2_s1_agent_m0_readdatavalid),                     //   input,    width = 1,                .readdatavalid
		.m0_read                 (board_info_temperature_board2_s1_agent_m0_read),                              //  output,    width = 1,                .read
		.m0_waitrequest          (board_info_temperature_board2_s1_agent_m0_waitrequest),                       //   input,    width = 1,                .waitrequest
		.m0_writedata            (board_info_temperature_board2_s1_agent_m0_writedata),                         //  output,   width = 32,                .writedata
		.m0_write                (board_info_temperature_board2_s1_agent_m0_write),                             //  output,    width = 1,                .write
		.rp_endofpacket          (board_info_temperature_board2_s1_agent_rp_endofpacket),                       //  output,    width = 1,              rp.endofpacket
		.rp_ready                (board_info_temperature_board2_s1_agent_rp_ready),                             //   input,    width = 1,                .ready
		.rp_valid                (board_info_temperature_board2_s1_agent_rp_valid),                             //  output,    width = 1,                .valid
		.rp_data                 (board_info_temperature_board2_s1_agent_rp_data),                              //  output,  width = 146,                .data
		.rp_startofpacket        (board_info_temperature_board2_s1_agent_rp_startofpacket),                     //  output,    width = 1,                .startofpacket
		.cp_ready                (board_info_temperature_board2_s1_burst_adapter_source0_ready),                //  output,    width = 1,              cp.ready
		.cp_valid                (board_info_temperature_board2_s1_burst_adapter_source0_valid),                //   input,    width = 1,                .valid
		.cp_data                 (board_info_temperature_board2_s1_burst_adapter_source0_data),                 //   input,  width = 146,                .data
		.cp_startofpacket        (board_info_temperature_board2_s1_burst_adapter_source0_startofpacket),        //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (board_info_temperature_board2_s1_burst_adapter_source0_endofpacket),          //   input,    width = 1,                .endofpacket
		.cp_channel              (board_info_temperature_board2_s1_burst_adapter_source0_channel),              //   input,   width = 14,                .channel
		.rf_sink_ready           (board_info_temperature_board2_s1_agent_rsp_fifo_out_ready),                   //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (board_info_temperature_board2_s1_agent_rsp_fifo_out_valid),                   //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (board_info_temperature_board2_s1_agent_rsp_fifo_out_startofpacket),           //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (board_info_temperature_board2_s1_agent_rsp_fifo_out_endofpacket),             //   input,    width = 1,                .endofpacket
		.rf_sink_data            (board_info_temperature_board2_s1_agent_rsp_fifo_out_data),                    //   input,  width = 147,                .data
		.rf_source_ready         (board_info_temperature_board2_s1_agent_rf_source_ready),                      //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (board_info_temperature_board2_s1_agent_rf_source_valid),                      //  output,    width = 1,                .valid
		.rf_source_startofpacket (board_info_temperature_board2_s1_agent_rf_source_startofpacket),              //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (board_info_temperature_board2_s1_agent_rf_source_endofpacket),                //  output,    width = 1,                .endofpacket
		.rf_source_data          (board_info_temperature_board2_s1_agent_rf_source_data),                       //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (board_info_temperature_board2_s1_agent_rdata_fifo_out_ready),                 //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (board_info_temperature_board2_s1_agent_rdata_fifo_out_valid),                 //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (board_info_temperature_board2_s1_agent_rdata_fifo_out_data),                  //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (board_info_temperature_board2_s1_agent_rdata_fifo_src_ready),                 //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (board_info_temperature_board2_s1_agent_rdata_fifo_src_valid),                 //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (board_info_temperature_board2_s1_agent_rdata_fifo_src_data),                  //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_temperature_board2_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                              //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),                   //   input,    width = 1, clk_reset.reset
		.in_data           (board_info_temperature_board2_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (board_info_temperature_board2_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (board_info_temperature_board2_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (board_info_temperature_board2_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (board_info_temperature_board2_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (board_info_temperature_board2_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (board_info_temperature_board2_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (board_info_temperature_board2_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (board_info_temperature_board2_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (board_info_temperature_board2_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                             // (terminated),                         
		.csr_read          (1'b0),                                                              // (terminated),                         
		.csr_write         (1'b0),                                                              // (terminated),                         
		.csr_readdata      (),                                                                  // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                              // (terminated),                         
		.almost_full_data  (),                                                                  // (terminated),                         
		.almost_empty_data (),                                                                  // (terminated),                         
		.in_empty          (1'b0),                                                              // (terminated),                         
		.out_empty         (),                                                                  // (terminated),                         
		.in_error          (1'b0),                                                              // (terminated),                         
		.out_error         (),                                                                  // (terminated),                         
		.in_channel        (1'b0),                                                              // (terminated),                         
		.out_channel       ()                                                                   // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) board_info_temperature_board2_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                        //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),             //   input,   width = 1, clk_reset.reset
		.in_data           (board_info_temperature_board2_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (board_info_temperature_board2_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (board_info_temperature_board2_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (board_info_temperature_board2_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (board_info_temperature_board2_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (board_info_temperature_board2_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                       // (terminated),                        
		.csr_read          (1'b0),                                                        // (terminated),                        
		.csr_write         (1'b0),                                                        // (terminated),                        
		.csr_readdata      (),                                                            // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                        // (terminated),                        
		.almost_full_data  (),                                                            // (terminated),                        
		.almost_empty_data (),                                                            // (terminated),                        
		.in_startofpacket  (1'b0),                                                        // (terminated),                        
		.in_endofpacket    (1'b0),                                                        // (terminated),                        
		.out_startofpacket (),                                                            // (terminated),                        
		.out_endofpacket   (),                                                            // (terminated),                        
		.in_empty          (1'b0),                                                        // (terminated),                        
		.out_empty         (),                                                            // (terminated),                        
		.in_error          (1'b0),                                                        // (terminated),                        
		.out_error         (),                                                            // (terminated),                        
		.in_channel        (1'b0),                                                        // (terminated),                        
		.out_channel       ()                                                             // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) intel_onchip_memory_s1_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (intel_onchip_memory_s1_agent_m0_address),                                     //  output,   width = 32,              m0.address
		.m0_burstcount           (intel_onchip_memory_s1_agent_m0_burstcount),                                  //  output,    width = 3,                .burstcount
		.m0_byteenable           (intel_onchip_memory_s1_agent_m0_byteenable),                                  //  output,    width = 4,                .byteenable
		.m0_debugaccess          (intel_onchip_memory_s1_agent_m0_debugaccess),                                 //  output,    width = 1,                .debugaccess
		.m0_lock                 (intel_onchip_memory_s1_agent_m0_lock),                                        //  output,    width = 1,                .lock
		.m0_readdata             (intel_onchip_memory_s1_agent_m0_readdata),                                    //   input,   width = 32,                .readdata
		.m0_readdatavalid        (intel_onchip_memory_s1_agent_m0_readdatavalid),                               //   input,    width = 1,                .readdatavalid
		.m0_read                 (intel_onchip_memory_s1_agent_m0_read),                                        //  output,    width = 1,                .read
		.m0_waitrequest          (intel_onchip_memory_s1_agent_m0_waitrequest),                                 //   input,    width = 1,                .waitrequest
		.m0_writedata            (intel_onchip_memory_s1_agent_m0_writedata),                                   //  output,   width = 32,                .writedata
		.m0_write                (intel_onchip_memory_s1_agent_m0_write),                                       //  output,    width = 1,                .write
		.rp_endofpacket          (intel_onchip_memory_s1_agent_rp_endofpacket),                                 //  output,    width = 1,              rp.endofpacket
		.rp_ready                (intel_onchip_memory_s1_agent_rp_ready),                                       //   input,    width = 1,                .ready
		.rp_valid                (intel_onchip_memory_s1_agent_rp_valid),                                       //  output,    width = 1,                .valid
		.rp_data                 (intel_onchip_memory_s1_agent_rp_data),                                        //  output,  width = 146,                .data
		.rp_startofpacket        (intel_onchip_memory_s1_agent_rp_startofpacket),                               //  output,    width = 1,                .startofpacket
		.cp_ready                (intel_onchip_memory_s1_burst_adapter_source0_ready),                          //  output,    width = 1,              cp.ready
		.cp_valid                (intel_onchip_memory_s1_burst_adapter_source0_valid),                          //   input,    width = 1,                .valid
		.cp_data                 (intel_onchip_memory_s1_burst_adapter_source0_data),                           //   input,  width = 146,                .data
		.cp_startofpacket        (intel_onchip_memory_s1_burst_adapter_source0_startofpacket),                  //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (intel_onchip_memory_s1_burst_adapter_source0_endofpacket),                    //   input,    width = 1,                .endofpacket
		.cp_channel              (intel_onchip_memory_s1_burst_adapter_source0_channel),                        //   input,   width = 14,                .channel
		.rf_sink_ready           (intel_onchip_memory_s1_agent_rsp_fifo_out_ready),                             //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (intel_onchip_memory_s1_agent_rsp_fifo_out_valid),                             //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (intel_onchip_memory_s1_agent_rsp_fifo_out_startofpacket),                     //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (intel_onchip_memory_s1_agent_rsp_fifo_out_endofpacket),                       //   input,    width = 1,                .endofpacket
		.rf_sink_data            (intel_onchip_memory_s1_agent_rsp_fifo_out_data),                              //   input,  width = 147,                .data
		.rf_source_ready         (intel_onchip_memory_s1_agent_rf_source_ready),                                //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (intel_onchip_memory_s1_agent_rf_source_valid),                                //  output,    width = 1,                .valid
		.rf_source_startofpacket (intel_onchip_memory_s1_agent_rf_source_startofpacket),                        //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (intel_onchip_memory_s1_agent_rf_source_endofpacket),                          //  output,    width = 1,                .endofpacket
		.rf_source_data          (intel_onchip_memory_s1_agent_rf_source_data),                                 //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (intel_onchip_memory_s1_agent_rdata_fifo_out_ready),                           //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (intel_onchip_memory_s1_agent_rdata_fifo_out_valid),                           //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (intel_onchip_memory_s1_agent_rdata_fifo_out_data),                            //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (intel_onchip_memory_s1_agent_rdata_fifo_src_ready),                           //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (intel_onchip_memory_s1_agent_rdata_fifo_src_valid),                           //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (intel_onchip_memory_s1_agent_rdata_fifo_src_data),                            //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) intel_onchip_memory_s1_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, clk_reset.reset
		.in_data           (intel_onchip_memory_s1_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (intel_onchip_memory_s1_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (intel_onchip_memory_s1_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (intel_onchip_memory_s1_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (intel_onchip_memory_s1_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (intel_onchip_memory_s1_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (intel_onchip_memory_s1_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (intel_onchip_memory_s1_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (intel_onchip_memory_s1_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (intel_onchip_memory_s1_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                   // (terminated),                         
		.csr_read          (1'b0),                                                    // (terminated),                         
		.csr_write         (1'b0),                                                    // (terminated),                         
		.csr_readdata      (),                                                        // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated),                         
		.almost_full_data  (),                                                        // (terminated),                         
		.almost_empty_data (),                                                        // (terminated),                         
		.in_empty          (1'b0),                                                    // (terminated),                         
		.out_empty         (),                                                        // (terminated),                         
		.in_error          (1'b0),                                                    // (terminated),                         
		.out_error         (),                                                        // (terminated),                         
		.in_channel        (1'b0),                                                    // (terminated),                         
		.out_channel       ()                                                         // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) intel_onchip_memory_s1_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                              //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),   //   input,   width = 1, clk_reset.reset
		.in_data           (intel_onchip_memory_s1_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (intel_onchip_memory_s1_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (intel_onchip_memory_s1_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (intel_onchip_memory_s1_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (intel_onchip_memory_s1_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (intel_onchip_memory_s1_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                             // (terminated),                        
		.csr_read          (1'b0),                                              // (terminated),                        
		.csr_write         (1'b0),                                              // (terminated),                        
		.csr_readdata      (),                                                  // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),              // (terminated),                        
		.almost_full_data  (),                                                  // (terminated),                        
		.almost_empty_data (),                                                  // (terminated),                        
		.in_startofpacket  (1'b0),                                              // (terminated),                        
		.in_endofpacket    (1'b0),                                              // (terminated),                        
		.out_startofpacket (),                                                  // (terminated),                        
		.out_endofpacket   (),                                                  // (terminated),                        
		.in_empty          (1'b0),                                              // (terminated),                        
		.out_empty         (),                                                  // (terminated),                        
		.in_error          (1'b0),                                              // (terminated),                        
		.out_error         (),                                                  // (terminated),                        
		.in_channel        (1'b0),                                              // (terminated),                        
		.out_channel       ()                                                   // (terminated),                        
	);

	system_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (124),
		.PKT_ORI_BURST_SIZE_L      (122),
		.PKT_RESPONSE_STATUS_H     (121),
		.PKT_RESPONSE_STATUS_L     (120),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_TRANS_LOCK            (72),
		.PKT_BEGIN_BURST           (99),
		.PKT_PROTECTION_H          (115),
		.PKT_PROTECTION_L          (113),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_POSTED          (69),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (107),
		.PKT_SRC_ID_L              (104),
		.PKT_DEST_ID_H             (111),
		.PKT_DEST_ID_L             (108),
		.PKT_POISON_H              (134),
		.PKT_POISON_L              (134),
		.PKT_DATACHK_H             (135),
		.PKT_DATACHK_L             (135),
		.PKT_SAI_H                 (139),
		.PKT_SAI_L                 (139),
		.PKT_ADDRCHK_H             (138),
		.PKT_ADDRCHK_L             (137),
		.PKT_USER_DATA_H           (136),
		.PKT_USER_DATA_L           (136),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (14),
		.ST_DATA_W                 (146),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) intel_niosv_g_timer_sw_agent_agent (
		.clk                     (clock_in_out_clk_clk),                                                        //   input,    width = 1,             clk.clk
		.reset                   (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,       clk_reset.reset
		.m0_address              (intel_niosv_g_timer_sw_agent_agent_m0_address),                               //  output,   width = 32,              m0.address
		.m0_burstcount           (intel_niosv_g_timer_sw_agent_agent_m0_burstcount),                            //  output,    width = 3,                .burstcount
		.m0_byteenable           (intel_niosv_g_timer_sw_agent_agent_m0_byteenable),                            //  output,    width = 4,                .byteenable
		.m0_debugaccess          (intel_niosv_g_timer_sw_agent_agent_m0_debugaccess),                           //  output,    width = 1,                .debugaccess
		.m0_lock                 (intel_niosv_g_timer_sw_agent_agent_m0_lock),                                  //  output,    width = 1,                .lock
		.m0_readdata             (intel_niosv_g_timer_sw_agent_agent_m0_readdata),                              //   input,   width = 32,                .readdata
		.m0_readdatavalid        (intel_niosv_g_timer_sw_agent_agent_m0_readdatavalid),                         //   input,    width = 1,                .readdatavalid
		.m0_read                 (intel_niosv_g_timer_sw_agent_agent_m0_read),                                  //  output,    width = 1,                .read
		.m0_waitrequest          (intel_niosv_g_timer_sw_agent_agent_m0_waitrequest),                           //   input,    width = 1,                .waitrequest
		.m0_writedata            (intel_niosv_g_timer_sw_agent_agent_m0_writedata),                             //  output,   width = 32,                .writedata
		.m0_write                (intel_niosv_g_timer_sw_agent_agent_m0_write),                                 //  output,    width = 1,                .write
		.rp_endofpacket          (intel_niosv_g_timer_sw_agent_agent_rp_endofpacket),                           //  output,    width = 1,              rp.endofpacket
		.rp_ready                (intel_niosv_g_timer_sw_agent_agent_rp_ready),                                 //   input,    width = 1,                .ready
		.rp_valid                (intel_niosv_g_timer_sw_agent_agent_rp_valid),                                 //  output,    width = 1,                .valid
		.rp_data                 (intel_niosv_g_timer_sw_agent_agent_rp_data),                                  //  output,  width = 146,                .data
		.rp_startofpacket        (intel_niosv_g_timer_sw_agent_agent_rp_startofpacket),                         //  output,    width = 1,                .startofpacket
		.cp_ready                (intel_niosv_g_timer_sw_agent_burst_adapter_source0_ready),                    //  output,    width = 1,              cp.ready
		.cp_valid                (intel_niosv_g_timer_sw_agent_burst_adapter_source0_valid),                    //   input,    width = 1,                .valid
		.cp_data                 (intel_niosv_g_timer_sw_agent_burst_adapter_source0_data),                     //   input,  width = 146,                .data
		.cp_startofpacket        (intel_niosv_g_timer_sw_agent_burst_adapter_source0_startofpacket),            //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (intel_niosv_g_timer_sw_agent_burst_adapter_source0_endofpacket),              //   input,    width = 1,                .endofpacket
		.cp_channel              (intel_niosv_g_timer_sw_agent_burst_adapter_source0_channel),                  //   input,   width = 14,                .channel
		.rf_sink_ready           (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_ready),                       //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_valid),                       //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_startofpacket),               //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_endofpacket),                 //   input,    width = 1,                .endofpacket
		.rf_sink_data            (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_data),                        //   input,  width = 147,                .data
		.rf_source_ready         (intel_niosv_g_timer_sw_agent_agent_rf_source_ready),                          //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (intel_niosv_g_timer_sw_agent_agent_rf_source_valid),                          //  output,    width = 1,                .valid
		.rf_source_startofpacket (intel_niosv_g_timer_sw_agent_agent_rf_source_startofpacket),                  //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (intel_niosv_g_timer_sw_agent_agent_rf_source_endofpacket),                    //  output,    width = 1,                .endofpacket
		.rf_source_data          (intel_niosv_g_timer_sw_agent_agent_rf_source_data),                           //  output,  width = 147,                .data
		.rdata_fifo_sink_ready   (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_ready),                     //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_valid),                     //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_data),                      //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_ready),                     //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_valid),                     //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_data),                      //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                       // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                        // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                         // (terminated),                               
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (147),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) intel_niosv_g_timer_sw_agent_agent_rsp_fifo (
		.clk               (clock_in_out_clk_clk),                                          //   input,    width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),               //   input,    width = 1, clk_reset.reset
		.in_data           (intel_niosv_g_timer_sw_agent_agent_rf_source_data),             //   input,  width = 147,        in.data
		.in_valid          (intel_niosv_g_timer_sw_agent_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (intel_niosv_g_timer_sw_agent_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (intel_niosv_g_timer_sw_agent_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (intel_niosv_g_timer_sw_agent_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_data),          //  output,  width = 147,       out.data
		.out_valid         (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (intel_niosv_g_timer_sw_agent_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                         // (terminated),                         
		.csr_read          (1'b0),                                                          // (terminated),                         
		.csr_write         (1'b0),                                                          // (terminated),                         
		.csr_readdata      (),                                                              // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                          // (terminated),                         
		.almost_full_data  (),                                                              // (terminated),                         
		.almost_empty_data (),                                                              // (terminated),                         
		.in_empty          (1'b0),                                                          // (terminated),                         
		.out_empty         (),                                                              // (terminated),                         
		.in_error          (1'b0),                                                          // (terminated),                         
		.out_error         (),                                                              // (terminated),                         
		.in_channel        (1'b0),                                                          // (terminated),                         
		.out_channel       ()                                                               // (terminated),                         
	);

	system_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) intel_niosv_g_timer_sw_agent_agent_rdata_fifo (
		.clk               (clock_in_out_clk_clk),                                    //   input,   width = 1,       clk.clk
		.reset             (intel_niosv_g_reset_reset_bridge_in_reset_reset),         //   input,   width = 1, clk_reset.reset
		.in_data           (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (intel_niosv_g_timer_sw_agent_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                   // (terminated),                        
		.csr_read          (1'b0),                                                    // (terminated),                        
		.csr_write         (1'b0),                                                    // (terminated),                        
		.csr_readdata      (),                                                        // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                    // (terminated),                        
		.almost_full_data  (),                                                        // (terminated),                        
		.almost_empty_data (),                                                        // (terminated),                        
		.in_startofpacket  (1'b0),                                                    // (terminated),                        
		.in_endofpacket    (1'b0),                                                    // (terminated),                        
		.out_startofpacket (),                                                        // (terminated),                        
		.out_endofpacket   (),                                                        // (terminated),                        
		.in_empty          (1'b0),                                                    // (terminated),                        
		.out_empty         (),                                                        // (terminated),                        
		.in_error          (1'b0),                                                    // (terminated),                        
		.out_error         (),                                                        // (terminated),                        
		.in_channel        (1'b0),                                                    // (terminated),                        
		.out_channel       ()                                                         // (terminated),                        
	);

	system_altera_merlin_router_1921_pghskdi router (
		.sink_ready         (intel_niosv_g_data_manager_agent_write_cp_ready),                             //  output,    width = 1,      sink.ready
		.sink_valid         (intel_niosv_g_data_manager_agent_write_cp_valid),                             //   input,    width = 1,          .valid
		.sink_data          (intel_niosv_g_data_manager_agent_write_cp_data),                              //   input,  width = 146,          .data
		.sink_startofpacket (intel_niosv_g_data_manager_agent_write_cp_startofpacket),                     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_niosv_g_data_manager_agent_write_cp_endofpacket),                       //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                                            //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                                            //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                                             //  output,  width = 146,          .data
		.src_channel        (router_src_channel),                                                          //  output,   width = 14,          .channel
		.src_startofpacket  (router_src_startofpacket),                                                    //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                                       //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_pghskdi router_001 (
		.sink_ready         (intel_niosv_g_data_manager_agent_read_cp_ready),                              //  output,    width = 1,      sink.ready
		.sink_valid         (intel_niosv_g_data_manager_agent_read_cp_valid),                              //   input,    width = 1,          .valid
		.sink_data          (intel_niosv_g_data_manager_agent_read_cp_data),                               //   input,  width = 146,          .data
		.sink_startofpacket (intel_niosv_g_data_manager_agent_read_cp_startofpacket),                      //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_niosv_g_data_manager_agent_read_cp_endofpacket),                        //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_001_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_tdlqbkq router_002 (
		.sink_ready         (intel_niosv_g_instruction_manager_agent_write_cp_ready),                      //  output,    width = 1,      sink.ready
		.sink_valid         (intel_niosv_g_instruction_manager_agent_write_cp_valid),                      //   input,    width = 1,          .valid
		.sink_data          (intel_niosv_g_instruction_manager_agent_write_cp_data),                       //   input,  width = 146,          .data
		.sink_startofpacket (intel_niosv_g_instruction_manager_agent_write_cp_startofpacket),              //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_niosv_g_instruction_manager_agent_write_cp_endofpacket),                //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_002_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_tdlqbkq router_003 (
		.sink_ready         (intel_niosv_g_instruction_manager_agent_read_cp_ready),                       //  output,    width = 1,      sink.ready
		.sink_valid         (intel_niosv_g_instruction_manager_agent_read_cp_valid),                       //   input,    width = 1,          .valid
		.sink_data          (intel_niosv_g_instruction_manager_agent_read_cp_data),                        //   input,  width = 146,          .data
		.sink_startofpacket (intel_niosv_g_instruction_manager_agent_read_cp_startofpacket),               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_niosv_g_instruction_manager_agent_read_cp_endofpacket),                 //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_003_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_003_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_004 (
		.sink_ready         (jtag_uart_avalon_jtag_slave_agent_rp_ready),                                  //  output,    width = 1,      sink.ready
		.sink_valid         (jtag_uart_avalon_jtag_slave_agent_rp_valid),                                  //   input,    width = 1,          .valid
		.sink_data          (jtag_uart_avalon_jtag_slave_agent_rp_data),                                   //   input,  width = 146,          .data
		.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket),                          //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket),                            //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_004_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_004_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_005 (
		.sink_ready         (sysid_qsys_control_slave_agent_rp_ready),                                     //  output,    width = 1,      sink.ready
		.sink_valid         (sysid_qsys_control_slave_agent_rp_valid),                                     //   input,    width = 1,          .valid
		.sink_data          (sysid_qsys_control_slave_agent_rp_data),                                      //   input,  width = 146,          .data
		.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (sysid_qsys_control_slave_agent_rp_endofpacket),                               //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_005_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_005_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_005_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_005_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_005_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_fqk5enq router_006 (
		.sink_ready         (intel_niosv_g_dm_agent_agent_rp_ready),                                       //  output,    width = 1,      sink.ready
		.sink_valid         (intel_niosv_g_dm_agent_agent_rp_valid),                                       //   input,    width = 1,          .valid
		.sink_data          (intel_niosv_g_dm_agent_agent_rp_data),                                        //   input,  width = 146,          .data
		.sink_startofpacket (intel_niosv_g_dm_agent_agent_rp_startofpacket),                               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_niosv_g_dm_agent_agent_rp_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_006_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_006_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_006_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_006_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_006_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_007 (
		.sink_ready         (timer_s1_agent_rp_ready),                                                     //  output,    width = 1,      sink.ready
		.sink_valid         (timer_s1_agent_rp_valid),                                                     //   input,    width = 1,          .valid
		.sink_data          (timer_s1_agent_rp_data),                                                      //   input,  width = 146,          .data
		.sink_startofpacket (timer_s1_agent_rp_startofpacket),                                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (timer_s1_agent_rp_endofpacket),                                               //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_007_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_007_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_007_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_007_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_007_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_008 (
		.sink_ready         (board_info_power_in_voltage_s1_agent_rp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_power_in_voltage_s1_agent_rp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (board_info_power_in_voltage_s1_agent_rp_data),                                //   input,  width = 146,          .data
		.sink_startofpacket (board_info_power_in_voltage_s1_agent_rp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_power_in_voltage_s1_agent_rp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_008_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_008_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_008_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_008_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_008_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_009 (
		.sink_ready         (board_info_vcc1p2_voltage_s1_agent_rp_ready),                                 //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_vcc1p2_voltage_s1_agent_rp_valid),                                 //   input,    width = 1,          .valid
		.sink_data          (board_info_vcc1p2_voltage_s1_agent_rp_data),                                  //   input,  width = 146,          .data
		.sink_startofpacket (board_info_vcc1p2_voltage_s1_agent_rp_startofpacket),                         //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_vcc1p2_voltage_s1_agent_rp_endofpacket),                           //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_009_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_009_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_009_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_009_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_009_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_009_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_010 (
		.sink_ready         (board_info_vcc1p2_current_s1_agent_rp_ready),                                 //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_vcc1p2_current_s1_agent_rp_valid),                                 //   input,    width = 1,          .valid
		.sink_data          (board_info_vcc1p2_current_s1_agent_rp_data),                                  //   input,  width = 146,          .data
		.sink_startofpacket (board_info_vcc1p2_current_s1_agent_rp_startofpacket),                         //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_vcc1p2_current_s1_agent_rp_endofpacket),                           //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_010_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_010_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_010_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_010_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_010_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_010_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_011 (
		.sink_ready         (board_info_fan_speed_s1_agent_rp_ready),                                      //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_fan_speed_s1_agent_rp_valid),                                      //   input,    width = 1,          .valid
		.sink_data          (board_info_fan_speed_s1_agent_rp_data),                                       //   input,  width = 146,          .data
		.sink_startofpacket (board_info_fan_speed_s1_agent_rp_startofpacket),                              //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_fan_speed_s1_agent_rp_endofpacket),                                //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_011_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_011_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_011_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_011_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_011_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_011_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_012 (
		.sink_ready         (board_info_temperature_fpga_s1_agent_rp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_temperature_fpga_s1_agent_rp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (board_info_temperature_fpga_s1_agent_rp_data),                                //   input,  width = 146,          .data
		.sink_startofpacket (board_info_temperature_fpga_s1_agent_rp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_temperature_fpga_s1_agent_rp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_012_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_012_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_012_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_012_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_012_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_012_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_013 (
		.sink_ready         (board_info_temperature_board1_s1_agent_rp_ready),                             //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_temperature_board1_s1_agent_rp_valid),                             //   input,    width = 1,          .valid
		.sink_data          (board_info_temperature_board1_s1_agent_rp_data),                              //   input,  width = 146,          .data
		.sink_startofpacket (board_info_temperature_board1_s1_agent_rp_startofpacket),                     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_temperature_board1_s1_agent_rp_endofpacket),                       //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_013_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_013_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_013_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_013_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_013_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_013_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_014 (
		.sink_ready         (board_info_pin_status_s1_agent_rp_ready),                                     //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_pin_status_s1_agent_rp_valid),                                     //   input,    width = 1,          .valid
		.sink_data          (board_info_pin_status_s1_agent_rp_data),                                      //   input,  width = 146,          .data
		.sink_startofpacket (board_info_pin_status_s1_agent_rp_startofpacket),                             //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_pin_status_s1_agent_rp_endofpacket),                               //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_014_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_014_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_014_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_014_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_014_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_014_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_015 (
		.sink_ready         (board_info_temperature_board2_s1_agent_rp_ready),                             //  output,    width = 1,      sink.ready
		.sink_valid         (board_info_temperature_board2_s1_agent_rp_valid),                             //   input,    width = 1,          .valid
		.sink_data          (board_info_temperature_board2_s1_agent_rp_data),                              //   input,  width = 146,          .data
		.sink_startofpacket (board_info_temperature_board2_s1_agent_rp_startofpacket),                     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (board_info_temperature_board2_s1_agent_rp_endofpacket),                       //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_015_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_015_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_015_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_015_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_015_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_015_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_fqk5enq router_016 (
		.sink_ready         (intel_onchip_memory_s1_agent_rp_ready),                                       //  output,    width = 1,      sink.ready
		.sink_valid         (intel_onchip_memory_s1_agent_rp_valid),                                       //   input,    width = 1,          .valid
		.sink_data          (intel_onchip_memory_s1_agent_rp_data),                                        //   input,  width = 146,          .data
		.sink_startofpacket (intel_onchip_memory_s1_agent_rp_startofpacket),                               //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_onchip_memory_s1_agent_rp_endofpacket),                                 //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_016_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_016_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_016_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_016_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_016_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_016_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_router_1921_kqdqoaq router_017 (
		.sink_ready         (intel_niosv_g_timer_sw_agent_agent_rp_ready),                                 //  output,    width = 1,      sink.ready
		.sink_valid         (intel_niosv_g_timer_sw_agent_agent_rp_valid),                                 //   input,    width = 1,          .valid
		.sink_data          (intel_niosv_g_timer_sw_agent_agent_rp_data),                                  //   input,  width = 146,          .data
		.sink_startofpacket (intel_niosv_g_timer_sw_agent_agent_rp_startofpacket),                         //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (intel_niosv_g_timer_sw_agent_agent_rp_endofpacket),                           //   input,    width = 1,          .endofpacket
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_017_src_ready),                                                        //   input,    width = 1,       src.ready
		.src_valid          (router_017_src_valid),                                                        //  output,    width = 1,          .valid
		.src_data           (router_017_src_data),                                                         //  output,  width = 146,          .data
		.src_channel        (router_017_src_channel),                                                      //  output,   width = 14,          .channel
		.src_startofpacket  (router_017_src_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_017_src_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_traffic_limiter_1921_74hvqpa #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (111),
		.PKT_DEST_ID_L                        (108),
		.PKT_SRC_ID_H                         (107),
		.PKT_SRC_ID_L                         (104),
		.PKT_BYTE_CNT_H                       (84),
		.PKT_BYTE_CNT_L                       (74),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (69),
		.PKT_TRANS_WRITE                      (70),
		.PKT_TRANS_SEQ_H                      (145),
		.PKT_TRANS_SEQ_L                      (142),
		.MAX_OUTSTANDING_RESPONSES            (5),
		.PIPELINED                            (0),
		.ST_DATA_W                            (146),
		.ST_CHANNEL_W                         (14),
		.VALID_WIDTH                          (14),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) intel_niosv_g_instruction_manager_wr_limiter (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_002_src_ready),                                                        //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_002_src_valid),                                                        //   input,    width = 1,          .valid
		.cmd_sink_data          (router_002_src_data),                                                         //   input,  width = 146,          .data
		.cmd_sink_channel       (router_002_src_channel),                                                      //   input,   width = 14,          .channel
		.cmd_sink_startofpacket (router_002_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_002_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_ready),                  //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_data),                   //  output,  width = 146,          .data
		.cmd_src_channel        (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_channel),                //  output,   width = 14,          .channel
		.cmd_src_startofpacket  (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_endofpacket),            //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_002_src_ready),                                                       //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_002_src_valid),                                                       //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_002_src_channel),                                                     //   input,   width = 14,          .channel
		.rsp_sink_data          (rsp_mux_002_src_data),                                                        //   input,  width = 146,          .data
		.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_002_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_ready),                  //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_valid),                  //  output,    width = 1,          .valid
		.rsp_src_data           (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_data),                   //  output,  width = 146,          .data
		.rsp_src_channel        (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_channel),                //  output,   width = 14,          .channel
		.rsp_src_startofpacket  (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (intel_niosv_g_instruction_manager_wr_limiter_rsp_src_endofpacket),            //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (intel_niosv_g_instruction_manager_wr_limiter_cmd_valid_data)                  //  output,   width = 14, cmd_valid.data
	);

	system_altera_merlin_traffic_limiter_1921_74hvqpa #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (111),
		.PKT_DEST_ID_L                        (108),
		.PKT_SRC_ID_H                         (107),
		.PKT_SRC_ID_L                         (104),
		.PKT_BYTE_CNT_H                       (84),
		.PKT_BYTE_CNT_L                       (74),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (69),
		.PKT_TRANS_WRITE                      (70),
		.PKT_TRANS_SEQ_H                      (145),
		.PKT_TRANS_SEQ_L                      (142),
		.MAX_OUTSTANDING_RESPONSES            (5),
		.PIPELINED                            (0),
		.ST_DATA_W                            (146),
		.ST_CHANNEL_W                         (14),
		.VALID_WIDTH                          (14),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) intel_niosv_g_instruction_manager_rd_limiter (
		.clk                    (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset                  (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_003_src_ready),                                                        //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_003_src_valid),                                                        //   input,    width = 1,          .valid
		.cmd_sink_data          (router_003_src_data),                                                         //   input,  width = 146,          .data
		.cmd_sink_channel       (router_003_src_channel),                                                      //   input,   width = 14,          .channel
		.cmd_sink_startofpacket (router_003_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_003_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_ready),                  //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_data),                   //  output,  width = 146,          .data
		.cmd_src_channel        (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_channel),                //  output,   width = 14,          .channel
		.cmd_src_startofpacket  (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_endofpacket),            //  output,    width = 1,          .endofpacket
		.rsp_sink_ready         (rsp_mux_003_src_ready),                                                       //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (rsp_mux_003_src_valid),                                                       //   input,    width = 1,          .valid
		.rsp_sink_channel       (rsp_mux_003_src_channel),                                                     //   input,   width = 14,          .channel
		.rsp_sink_data          (rsp_mux_003_src_data),                                                        //   input,  width = 146,          .data
		.rsp_sink_startofpacket (rsp_mux_003_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (rsp_mux_003_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_ready),                  //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_valid),                  //  output,    width = 1,          .valid
		.rsp_src_data           (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_data),                   //  output,  width = 146,          .data
		.rsp_src_channel        (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_channel),                //  output,   width = 14,          .channel
		.rsp_src_startofpacket  (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (intel_niosv_g_instruction_manager_rd_limiter_rsp_src_endofpacket),            //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (intel_niosv_g_instruction_manager_rd_limiter_cmd_valid_data)                  //  output,   width = 14, cmd_valid.data
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) jtag_uart_avalon_jtag_slave_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_src_valid),                                                           //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_src_data),                                                            //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_src_channel),                                                         //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_src_startofpacket),                                                   //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_src_endofpacket),                                                     //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_src_ready),                                                           //  output,    width = 1,          .ready
		.source0_valid         (jtag_uart_avalon_jtag_slave_burst_adapter_source0_valid),                     //  output,    width = 1,   source0.valid
		.source0_data          (jtag_uart_avalon_jtag_slave_burst_adapter_source0_data),                      //  output,  width = 146,          .data
		.source0_channel       (jtag_uart_avalon_jtag_slave_burst_adapter_source0_channel),                   //  output,   width = 14,          .channel
		.source0_startofpacket (jtag_uart_avalon_jtag_slave_burst_adapter_source0_startofpacket),             //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (jtag_uart_avalon_jtag_slave_burst_adapter_source0_endofpacket),               //  output,    width = 1,          .endofpacket
		.source0_ready         (jtag_uart_avalon_jtag_slave_burst_adapter_source0_ready)                      //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) sysid_qsys_control_slave_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_001_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_001_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_001_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_001_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_001_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_001_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (sysid_qsys_control_slave_burst_adapter_source0_valid),                        //  output,    width = 1,   source0.valid
		.source0_data          (sysid_qsys_control_slave_burst_adapter_source0_data),                         //  output,  width = 146,          .data
		.source0_channel       (sysid_qsys_control_slave_burst_adapter_source0_channel),                      //  output,   width = 14,          .channel
		.source0_startofpacket (sysid_qsys_control_slave_burst_adapter_source0_startofpacket),                //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (sysid_qsys_control_slave_burst_adapter_source0_endofpacket),                  //  output,    width = 1,          .endofpacket
		.source0_ready         (sysid_qsys_control_slave_burst_adapter_source0_ready)                         //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) intel_niosv_g_dm_agent_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_002_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_002_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_002_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_002_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_002_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_002_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (intel_niosv_g_dm_agent_burst_adapter_source0_valid),                          //  output,    width = 1,   source0.valid
		.source0_data          (intel_niosv_g_dm_agent_burst_adapter_source0_data),                           //  output,  width = 146,          .data
		.source0_channel       (intel_niosv_g_dm_agent_burst_adapter_source0_channel),                        //  output,   width = 14,          .channel
		.source0_startofpacket (intel_niosv_g_dm_agent_burst_adapter_source0_startofpacket),                  //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (intel_niosv_g_dm_agent_burst_adapter_source0_endofpacket),                    //  output,    width = 1,          .endofpacket
		.source0_ready         (intel_niosv_g_dm_agent_burst_adapter_source0_ready)                           //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) timer_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_003_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_003_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_003_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_003_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_003_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_003_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (timer_s1_burst_adapter_source0_valid),                                        //  output,    width = 1,   source0.valid
		.source0_data          (timer_s1_burst_adapter_source0_data),                                         //  output,  width = 146,          .data
		.source0_channel       (timer_s1_burst_adapter_source0_channel),                                      //  output,   width = 14,          .channel
		.source0_startofpacket (timer_s1_burst_adapter_source0_startofpacket),                                //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (timer_s1_burst_adapter_source0_endofpacket),                                  //  output,    width = 1,          .endofpacket
		.source0_ready         (timer_s1_burst_adapter_source0_ready)                                         //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_power_in_voltage_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_004_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_004_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_004_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_004_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_004_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_004_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_power_in_voltage_s1_burst_adapter_source0_valid),                  //  output,    width = 1,   source0.valid
		.source0_data          (board_info_power_in_voltage_s1_burst_adapter_source0_data),                   //  output,  width = 146,          .data
		.source0_channel       (board_info_power_in_voltage_s1_burst_adapter_source0_channel),                //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_power_in_voltage_s1_burst_adapter_source0_startofpacket),          //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_power_in_voltage_s1_burst_adapter_source0_endofpacket),            //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_power_in_voltage_s1_burst_adapter_source0_ready)                   //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_vcc1p2_voltage_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_005_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_005_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_005_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_005_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_005_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_005_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_vcc1p2_voltage_s1_burst_adapter_source0_valid),                    //  output,    width = 1,   source0.valid
		.source0_data          (board_info_vcc1p2_voltage_s1_burst_adapter_source0_data),                     //  output,  width = 146,          .data
		.source0_channel       (board_info_vcc1p2_voltage_s1_burst_adapter_source0_channel),                  //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_vcc1p2_voltage_s1_burst_adapter_source0_startofpacket),            //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_vcc1p2_voltage_s1_burst_adapter_source0_endofpacket),              //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_vcc1p2_voltage_s1_burst_adapter_source0_ready)                     //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_vcc1p2_current_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_006_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_006_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_006_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_006_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_006_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_006_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_vcc1p2_current_s1_burst_adapter_source0_valid),                    //  output,    width = 1,   source0.valid
		.source0_data          (board_info_vcc1p2_current_s1_burst_adapter_source0_data),                     //  output,  width = 146,          .data
		.source0_channel       (board_info_vcc1p2_current_s1_burst_adapter_source0_channel),                  //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_vcc1p2_current_s1_burst_adapter_source0_startofpacket),            //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_vcc1p2_current_s1_burst_adapter_source0_endofpacket),              //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_vcc1p2_current_s1_burst_adapter_source0_ready)                     //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_fan_speed_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_007_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_007_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_007_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_007_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_007_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_007_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_fan_speed_s1_burst_adapter_source0_valid),                         //  output,    width = 1,   source0.valid
		.source0_data          (board_info_fan_speed_s1_burst_adapter_source0_data),                          //  output,  width = 146,          .data
		.source0_channel       (board_info_fan_speed_s1_burst_adapter_source0_channel),                       //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_fan_speed_s1_burst_adapter_source0_startofpacket),                 //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_fan_speed_s1_burst_adapter_source0_endofpacket),                   //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_fan_speed_s1_burst_adapter_source0_ready)                          //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_temperature_fpga_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_008_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_008_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_008_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_008_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_008_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_008_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_temperature_fpga_s1_burst_adapter_source0_valid),                  //  output,    width = 1,   source0.valid
		.source0_data          (board_info_temperature_fpga_s1_burst_adapter_source0_data),                   //  output,  width = 146,          .data
		.source0_channel       (board_info_temperature_fpga_s1_burst_adapter_source0_channel),                //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_temperature_fpga_s1_burst_adapter_source0_startofpacket),          //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_temperature_fpga_s1_burst_adapter_source0_endofpacket),            //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_temperature_fpga_s1_burst_adapter_source0_ready)                   //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_temperature_board1_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_009_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_009_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_009_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_009_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_009_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_009_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_temperature_board1_s1_burst_adapter_source0_valid),                //  output,    width = 1,   source0.valid
		.source0_data          (board_info_temperature_board1_s1_burst_adapter_source0_data),                 //  output,  width = 146,          .data
		.source0_channel       (board_info_temperature_board1_s1_burst_adapter_source0_channel),              //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_temperature_board1_s1_burst_adapter_source0_startofpacket),        //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_temperature_board1_s1_burst_adapter_source0_endofpacket),          //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_temperature_board1_s1_burst_adapter_source0_ready)                 //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_pin_status_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_010_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_010_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_010_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_010_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_010_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_010_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_pin_status_s1_burst_adapter_source0_valid),                        //  output,    width = 1,   source0.valid
		.source0_data          (board_info_pin_status_s1_burst_adapter_source0_data),                         //  output,  width = 146,          .data
		.source0_channel       (board_info_pin_status_s1_burst_adapter_source0_channel),                      //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_pin_status_s1_burst_adapter_source0_startofpacket),                //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_pin_status_s1_burst_adapter_source0_endofpacket),                  //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_pin_status_s1_burst_adapter_source0_ready)                         //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) board_info_temperature_board2_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_011_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_011_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_011_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_011_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_011_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_011_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (board_info_temperature_board2_s1_burst_adapter_source0_valid),                //  output,    width = 1,   source0.valid
		.source0_data          (board_info_temperature_board2_s1_burst_adapter_source0_data),                 //  output,  width = 146,          .data
		.source0_channel       (board_info_temperature_board2_s1_burst_adapter_source0_channel),              //  output,   width = 14,          .channel
		.source0_startofpacket (board_info_temperature_board2_s1_burst_adapter_source0_startofpacket),        //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (board_info_temperature_board2_s1_burst_adapter_source0_endofpacket),          //  output,    width = 1,          .endofpacket
		.source0_ready         (board_info_temperature_board2_s1_burst_adapter_source0_ready)                 //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) intel_onchip_memory_s1_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_012_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_012_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_012_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_012_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_012_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_012_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (intel_onchip_memory_s1_burst_adapter_source0_valid),                          //  output,    width = 1,   source0.valid
		.source0_data          (intel_onchip_memory_s1_burst_adapter_source0_data),                           //  output,  width = 146,          .data
		.source0_channel       (intel_onchip_memory_s1_burst_adapter_source0_channel),                        //  output,   width = 14,          .channel
		.source0_startofpacket (intel_onchip_memory_s1_burst_adapter_source0_startofpacket),                  //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (intel_onchip_memory_s1_burst_adapter_source0_endofpacket),                    //  output,    width = 1,          .endofpacket
		.source0_ready         (intel_onchip_memory_s1_burst_adapter_source0_ready)                           //   input,    width = 1,          .ready
	);

	system_altera_merlin_burst_adapter_1932_r6fbuaa #(
		.PKT_ADDR_H                (67),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (99),
		.PKT_BYTE_CNT_H            (84),
		.PKT_BYTE_CNT_L            (74),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (94),
		.PKT_BURST_SIZE_L          (92),
		.PKT_BURST_TYPE_H          (96),
		.PKT_BURST_TYPE_L          (95),
		.PKT_BURSTWRAP_H           (91),
		.PKT_BURSTWRAP_L           (85),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (68),
		.PKT_TRANS_WRITE           (70),
		.PKT_TRANS_READ            (71),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (146),
		.ST_CHANNEL_W              (14),
		.OUT_BYTE_CNT_H            (76),
		.OUT_BURSTWRAP_H           (91),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("13.1"),
		.SYNC_RESET                (1)
	) intel_niosv_g_timer_sw_agent_burst_adapter (
		.clk                   (clock_in_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset                 (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_013_src_valid),                                                       //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_013_src_data),                                                        //   input,  width = 146,          .data
		.sink0_channel         (cmd_mux_013_src_channel),                                                     //   input,   width = 14,          .channel
		.sink0_startofpacket   (cmd_mux_013_src_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_013_src_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_013_src_ready),                                                       //  output,    width = 1,          .ready
		.source0_valid         (intel_niosv_g_timer_sw_agent_burst_adapter_source0_valid),                    //  output,    width = 1,   source0.valid
		.source0_data          (intel_niosv_g_timer_sw_agent_burst_adapter_source0_data),                     //  output,  width = 146,          .data
		.source0_channel       (intel_niosv_g_timer_sw_agent_burst_adapter_source0_channel),                  //  output,   width = 14,          .channel
		.source0_startofpacket (intel_niosv_g_timer_sw_agent_burst_adapter_source0_startofpacket),            //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (intel_niosv_g_timer_sw_agent_burst_adapter_source0_endofpacket),              //  output,    width = 1,          .endofpacket
		.source0_ready         (intel_niosv_g_timer_sw_agent_burst_adapter_source0_ready)                     //   input,    width = 1,          .ready
	);

	system_altera_merlin_demultiplexer_1921_smo4omy cmd_demux (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready          (router_src_ready),                                                            //  output,    width = 1,      sink.ready
		.sink_channel        (router_src_channel),                                                          //   input,   width = 14,          .channel
		.sink_data           (router_src_data),                                                             //   input,  width = 146,          .data
		.sink_startofpacket  (router_src_startofpacket),                                                    //   input,    width = 1,          .startofpacket
		.sink_endofpacket    (router_src_endofpacket),                                                      //   input,    width = 1,          .endofpacket
		.sink_valid          (router_src_valid),                                                            //   input,    width = 1,          .valid
		.src0_ready          (cmd_demux_src0_ready),                                                        //   input,    width = 1,      src0.ready
		.src0_valid          (cmd_demux_src0_valid),                                                        //  output,    width = 1,          .valid
		.src0_data           (cmd_demux_src0_data),                                                         //  output,  width = 146,          .data
		.src0_channel        (cmd_demux_src0_channel),                                                      //  output,   width = 14,          .channel
		.src0_startofpacket  (cmd_demux_src0_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src0_endofpacket    (cmd_demux_src0_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src1_ready          (cmd_demux_src1_ready),                                                        //   input,    width = 1,      src1.ready
		.src1_valid          (cmd_demux_src1_valid),                                                        //  output,    width = 1,          .valid
		.src1_data           (cmd_demux_src1_data),                                                         //  output,  width = 146,          .data
		.src1_channel        (cmd_demux_src1_channel),                                                      //  output,   width = 14,          .channel
		.src1_startofpacket  (cmd_demux_src1_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src1_endofpacket    (cmd_demux_src1_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src2_ready          (cmd_demux_src2_ready),                                                        //   input,    width = 1,      src2.ready
		.src2_valid          (cmd_demux_src2_valid),                                                        //  output,    width = 1,          .valid
		.src2_data           (cmd_demux_src2_data),                                                         //  output,  width = 146,          .data
		.src2_channel        (cmd_demux_src2_channel),                                                      //  output,   width = 14,          .channel
		.src2_startofpacket  (cmd_demux_src2_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src2_endofpacket    (cmd_demux_src2_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src3_ready          (cmd_demux_src3_ready),                                                        //   input,    width = 1,      src3.ready
		.src3_valid          (cmd_demux_src3_valid),                                                        //  output,    width = 1,          .valid
		.src3_data           (cmd_demux_src3_data),                                                         //  output,  width = 146,          .data
		.src3_channel        (cmd_demux_src3_channel),                                                      //  output,   width = 14,          .channel
		.src3_startofpacket  (cmd_demux_src3_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src3_endofpacket    (cmd_demux_src3_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src4_ready          (cmd_demux_src4_ready),                                                        //   input,    width = 1,      src4.ready
		.src4_valid          (cmd_demux_src4_valid),                                                        //  output,    width = 1,          .valid
		.src4_data           (cmd_demux_src4_data),                                                         //  output,  width = 146,          .data
		.src4_channel        (cmd_demux_src4_channel),                                                      //  output,   width = 14,          .channel
		.src4_startofpacket  (cmd_demux_src4_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src4_endofpacket    (cmd_demux_src4_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src5_ready          (cmd_demux_src5_ready),                                                        //   input,    width = 1,      src5.ready
		.src5_valid          (cmd_demux_src5_valid),                                                        //  output,    width = 1,          .valid
		.src5_data           (cmd_demux_src5_data),                                                         //  output,  width = 146,          .data
		.src5_channel        (cmd_demux_src5_channel),                                                      //  output,   width = 14,          .channel
		.src5_startofpacket  (cmd_demux_src5_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src5_endofpacket    (cmd_demux_src5_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src6_ready          (cmd_demux_src6_ready),                                                        //   input,    width = 1,      src6.ready
		.src6_valid          (cmd_demux_src6_valid),                                                        //  output,    width = 1,          .valid
		.src6_data           (cmd_demux_src6_data),                                                         //  output,  width = 146,          .data
		.src6_channel        (cmd_demux_src6_channel),                                                      //  output,   width = 14,          .channel
		.src6_startofpacket  (cmd_demux_src6_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src6_endofpacket    (cmd_demux_src6_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src7_ready          (cmd_demux_src7_ready),                                                        //   input,    width = 1,      src7.ready
		.src7_valid          (cmd_demux_src7_valid),                                                        //  output,    width = 1,          .valid
		.src7_data           (cmd_demux_src7_data),                                                         //  output,  width = 146,          .data
		.src7_channel        (cmd_demux_src7_channel),                                                      //  output,   width = 14,          .channel
		.src7_startofpacket  (cmd_demux_src7_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src7_endofpacket    (cmd_demux_src7_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src8_ready          (cmd_demux_src8_ready),                                                        //   input,    width = 1,      src8.ready
		.src8_valid          (cmd_demux_src8_valid),                                                        //  output,    width = 1,          .valid
		.src8_data           (cmd_demux_src8_data),                                                         //  output,  width = 146,          .data
		.src8_channel        (cmd_demux_src8_channel),                                                      //  output,   width = 14,          .channel
		.src8_startofpacket  (cmd_demux_src8_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src8_endofpacket    (cmd_demux_src8_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src9_ready          (cmd_demux_src9_ready),                                                        //   input,    width = 1,      src9.ready
		.src9_valid          (cmd_demux_src9_valid),                                                        //  output,    width = 1,          .valid
		.src9_data           (cmd_demux_src9_data),                                                         //  output,  width = 146,          .data
		.src9_channel        (cmd_demux_src9_channel),                                                      //  output,   width = 14,          .channel
		.src9_startofpacket  (cmd_demux_src9_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src9_endofpacket    (cmd_demux_src9_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src10_ready         (cmd_demux_src10_ready),                                                       //   input,    width = 1,     src10.ready
		.src10_valid         (cmd_demux_src10_valid),                                                       //  output,    width = 1,          .valid
		.src10_data          (cmd_demux_src10_data),                                                        //  output,  width = 146,          .data
		.src10_channel       (cmd_demux_src10_channel),                                                     //  output,   width = 14,          .channel
		.src10_startofpacket (cmd_demux_src10_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src10_endofpacket   (cmd_demux_src10_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.src11_ready         (cmd_demux_src11_ready),                                                       //   input,    width = 1,     src11.ready
		.src11_valid         (cmd_demux_src11_valid),                                                       //  output,    width = 1,          .valid
		.src11_data          (cmd_demux_src11_data),                                                        //  output,  width = 146,          .data
		.src11_channel       (cmd_demux_src11_channel),                                                     //  output,   width = 14,          .channel
		.src11_startofpacket (cmd_demux_src11_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src11_endofpacket   (cmd_demux_src11_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.src12_ready         (cmd_demux_src12_ready),                                                       //   input,    width = 1,     src12.ready
		.src12_valid         (cmd_demux_src12_valid),                                                       //  output,    width = 1,          .valid
		.src12_data          (cmd_demux_src12_data),                                                        //  output,  width = 146,          .data
		.src12_channel       (cmd_demux_src12_channel),                                                     //  output,   width = 14,          .channel
		.src12_startofpacket (cmd_demux_src12_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src12_endofpacket   (cmd_demux_src12_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.src13_ready         (cmd_demux_src13_ready),                                                       //   input,    width = 1,     src13.ready
		.src13_valid         (cmd_demux_src13_valid),                                                       //  output,    width = 1,          .valid
		.src13_data          (cmd_demux_src13_data),                                                        //  output,  width = 146,          .data
		.src13_channel       (cmd_demux_src13_channel),                                                     //  output,   width = 14,          .channel
		.src13_startofpacket (cmd_demux_src13_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src13_endofpacket   (cmd_demux_src13_endofpacket)                                                  //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_smo4omy cmd_demux_001 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready          (router_001_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel        (router_001_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data           (router_001_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket  (router_001_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket    (router_001_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid          (router_001_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready          (cmd_demux_001_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid          (cmd_demux_001_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data           (cmd_demux_001_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel        (cmd_demux_001_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket  (cmd_demux_001_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket    (cmd_demux_001_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready          (cmd_demux_001_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid          (cmd_demux_001_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data           (cmd_demux_001_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel        (cmd_demux_001_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket  (cmd_demux_001_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket    (cmd_demux_001_src1_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src2_ready          (cmd_demux_001_src2_ready),                                                    //   input,    width = 1,      src2.ready
		.src2_valid          (cmd_demux_001_src2_valid),                                                    //  output,    width = 1,          .valid
		.src2_data           (cmd_demux_001_src2_data),                                                     //  output,  width = 146,          .data
		.src2_channel        (cmd_demux_001_src2_channel),                                                  //  output,   width = 14,          .channel
		.src2_startofpacket  (cmd_demux_001_src2_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src2_endofpacket    (cmd_demux_001_src2_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src3_ready          (cmd_demux_001_src3_ready),                                                    //   input,    width = 1,      src3.ready
		.src3_valid          (cmd_demux_001_src3_valid),                                                    //  output,    width = 1,          .valid
		.src3_data           (cmd_demux_001_src3_data),                                                     //  output,  width = 146,          .data
		.src3_channel        (cmd_demux_001_src3_channel),                                                  //  output,   width = 14,          .channel
		.src3_startofpacket  (cmd_demux_001_src3_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src3_endofpacket    (cmd_demux_001_src3_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src4_ready          (cmd_demux_001_src4_ready),                                                    //   input,    width = 1,      src4.ready
		.src4_valid          (cmd_demux_001_src4_valid),                                                    //  output,    width = 1,          .valid
		.src4_data           (cmd_demux_001_src4_data),                                                     //  output,  width = 146,          .data
		.src4_channel        (cmd_demux_001_src4_channel),                                                  //  output,   width = 14,          .channel
		.src4_startofpacket  (cmd_demux_001_src4_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src4_endofpacket    (cmd_demux_001_src4_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src5_ready          (cmd_demux_001_src5_ready),                                                    //   input,    width = 1,      src5.ready
		.src5_valid          (cmd_demux_001_src5_valid),                                                    //  output,    width = 1,          .valid
		.src5_data           (cmd_demux_001_src5_data),                                                     //  output,  width = 146,          .data
		.src5_channel        (cmd_demux_001_src5_channel),                                                  //  output,   width = 14,          .channel
		.src5_startofpacket  (cmd_demux_001_src5_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src5_endofpacket    (cmd_demux_001_src5_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src6_ready          (cmd_demux_001_src6_ready),                                                    //   input,    width = 1,      src6.ready
		.src6_valid          (cmd_demux_001_src6_valid),                                                    //  output,    width = 1,          .valid
		.src6_data           (cmd_demux_001_src6_data),                                                     //  output,  width = 146,          .data
		.src6_channel        (cmd_demux_001_src6_channel),                                                  //  output,   width = 14,          .channel
		.src6_startofpacket  (cmd_demux_001_src6_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src6_endofpacket    (cmd_demux_001_src6_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src7_ready          (cmd_demux_001_src7_ready),                                                    //   input,    width = 1,      src7.ready
		.src7_valid          (cmd_demux_001_src7_valid),                                                    //  output,    width = 1,          .valid
		.src7_data           (cmd_demux_001_src7_data),                                                     //  output,  width = 146,          .data
		.src7_channel        (cmd_demux_001_src7_channel),                                                  //  output,   width = 14,          .channel
		.src7_startofpacket  (cmd_demux_001_src7_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src7_endofpacket    (cmd_demux_001_src7_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src8_ready          (cmd_demux_001_src8_ready),                                                    //   input,    width = 1,      src8.ready
		.src8_valid          (cmd_demux_001_src8_valid),                                                    //  output,    width = 1,          .valid
		.src8_data           (cmd_demux_001_src8_data),                                                     //  output,  width = 146,          .data
		.src8_channel        (cmd_demux_001_src8_channel),                                                  //  output,   width = 14,          .channel
		.src8_startofpacket  (cmd_demux_001_src8_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src8_endofpacket    (cmd_demux_001_src8_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src9_ready          (cmd_demux_001_src9_ready),                                                    //   input,    width = 1,      src9.ready
		.src9_valid          (cmd_demux_001_src9_valid),                                                    //  output,    width = 1,          .valid
		.src9_data           (cmd_demux_001_src9_data),                                                     //  output,  width = 146,          .data
		.src9_channel        (cmd_demux_001_src9_channel),                                                  //  output,   width = 14,          .channel
		.src9_startofpacket  (cmd_demux_001_src9_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src9_endofpacket    (cmd_demux_001_src9_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src10_ready         (cmd_demux_001_src10_ready),                                                   //   input,    width = 1,     src10.ready
		.src10_valid         (cmd_demux_001_src10_valid),                                                   //  output,    width = 1,          .valid
		.src10_data          (cmd_demux_001_src10_data),                                                    //  output,  width = 146,          .data
		.src10_channel       (cmd_demux_001_src10_channel),                                                 //  output,   width = 14,          .channel
		.src10_startofpacket (cmd_demux_001_src10_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src10_endofpacket   (cmd_demux_001_src10_endofpacket),                                             //  output,    width = 1,          .endofpacket
		.src11_ready         (cmd_demux_001_src11_ready),                                                   //   input,    width = 1,     src11.ready
		.src11_valid         (cmd_demux_001_src11_valid),                                                   //  output,    width = 1,          .valid
		.src11_data          (cmd_demux_001_src11_data),                                                    //  output,  width = 146,          .data
		.src11_channel       (cmd_demux_001_src11_channel),                                                 //  output,   width = 14,          .channel
		.src11_startofpacket (cmd_demux_001_src11_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src11_endofpacket   (cmd_demux_001_src11_endofpacket),                                             //  output,    width = 1,          .endofpacket
		.src12_ready         (cmd_demux_001_src12_ready),                                                   //   input,    width = 1,     src12.ready
		.src12_valid         (cmd_demux_001_src12_valid),                                                   //  output,    width = 1,          .valid
		.src12_data          (cmd_demux_001_src12_data),                                                    //  output,  width = 146,          .data
		.src12_channel       (cmd_demux_001_src12_channel),                                                 //  output,   width = 14,          .channel
		.src12_startofpacket (cmd_demux_001_src12_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src12_endofpacket   (cmd_demux_001_src12_endofpacket),                                             //  output,    width = 1,          .endofpacket
		.src13_ready         (cmd_demux_001_src13_ready),                                                   //   input,    width = 1,     src13.ready
		.src13_valid         (cmd_demux_001_src13_valid),                                                   //  output,    width = 1,          .valid
		.src13_data          (cmd_demux_001_src13_data),                                                    //  output,  width = 146,          .data
		.src13_channel       (cmd_demux_001_src13_channel),                                                 //  output,   width = 14,          .channel
		.src13_startofpacket (cmd_demux_001_src13_startofpacket),                                           //  output,    width = 1,          .startofpacket
		.src13_endofpacket   (cmd_demux_001_src13_endofpacket)                                              //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_2m5mxly cmd_demux_002 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,        clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,  clk_reset.reset
		.sink_ready         (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_ready),                  //  output,    width = 1,       sink.ready
		.sink_channel       (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_channel),                //   input,   width = 14,           .channel
		.sink_data          (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_data),                   //   input,  width = 146,           .data
		.sink_startofpacket (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_startofpacket),          //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (intel_niosv_g_instruction_manager_wr_limiter_cmd_src_endofpacket),            //   input,    width = 1,           .endofpacket
		.sink_valid         (intel_niosv_g_instruction_manager_wr_limiter_cmd_valid_data),                 //   input,   width = 14, sink_valid.data
		.src0_ready         (cmd_demux_002_src0_ready),                                                    //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                                                    //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_002_src0_data),                                                     //  output,  width = 146,           .data
		.src0_channel       (cmd_demux_002_src0_channel),                                                  //  output,   width = 14,           .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),                                            //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket),                                              //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_002_src1_ready),                                                    //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_002_src1_valid),                                                    //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_002_src1_data),                                                     //  output,  width = 146,           .data
		.src1_channel       (cmd_demux_002_src1_channel),                                                  //  output,   width = 14,           .channel
		.src1_startofpacket (cmd_demux_002_src1_startofpacket),                                            //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_002_src1_endofpacket)                                               //  output,    width = 1,           .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_2m5mxly cmd_demux_003 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,        clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1,  clk_reset.reset
		.sink_ready         (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_ready),                  //  output,    width = 1,       sink.ready
		.sink_channel       (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_channel),                //   input,   width = 14,           .channel
		.sink_data          (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_data),                   //   input,  width = 146,           .data
		.sink_startofpacket (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_startofpacket),          //   input,    width = 1,           .startofpacket
		.sink_endofpacket   (intel_niosv_g_instruction_manager_rd_limiter_cmd_src_endofpacket),            //   input,    width = 1,           .endofpacket
		.sink_valid         (intel_niosv_g_instruction_manager_rd_limiter_cmd_valid_data),                 //   input,   width = 14, sink_valid.data
		.src0_ready         (cmd_demux_003_src0_ready),                                                    //   input,    width = 1,       src0.ready
		.src0_valid         (cmd_demux_003_src0_valid),                                                    //  output,    width = 1,           .valid
		.src0_data          (cmd_demux_003_src0_data),                                                     //  output,  width = 146,           .data
		.src0_channel       (cmd_demux_003_src0_channel),                                                  //  output,   width = 14,           .channel
		.src0_startofpacket (cmd_demux_003_src0_startofpacket),                                            //  output,    width = 1,           .startofpacket
		.src0_endofpacket   (cmd_demux_003_src0_endofpacket),                                              //  output,    width = 1,           .endofpacket
		.src1_ready         (cmd_demux_003_src1_ready),                                                    //   input,    width = 1,       src1.ready
		.src1_valid         (cmd_demux_003_src1_valid),                                                    //  output,    width = 1,           .valid
		.src1_data          (cmd_demux_003_src1_data),                                                     //  output,  width = 146,           .data
		.src1_channel       (cmd_demux_003_src1_channel),                                                  //  output,   width = 14,           .channel
		.src1_startofpacket (cmd_demux_003_src1_startofpacket),                                            //  output,    width = 1,           .startofpacket
		.src1_endofpacket   (cmd_demux_003_src1_endofpacket)                                               //  output,    width = 1,           .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                           //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                                           //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                                            //  output,  width = 146,          .data
		.src_channel         (cmd_mux_src_channel),                                                         //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                                   //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                                     //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src0_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src0_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src0_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src0_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src0_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src0_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src0_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src0_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src0_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_001 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_001_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src1_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src1_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src1_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src1_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src1_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src1_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src1_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src1_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src1_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_qysncvq cmd_mux_002 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_002_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src2_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src2_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src2_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src2_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src2_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src2_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src2_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src2_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src2_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src2_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src2_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src2_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink2_ready         (cmd_demux_002_src0_ready),                                                    //  output,    width = 1,     sink2.ready
		.sink2_valid         (cmd_demux_002_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink2_channel       (cmd_demux_002_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink2_data          (cmd_demux_002_src0_data),                                                     //   input,  width = 146,          .data
		.sink2_startofpacket (cmd_demux_002_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (cmd_demux_002_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink3_ready         (cmd_demux_003_src0_ready),                                                    //  output,    width = 1,     sink3.ready
		.sink3_valid         (cmd_demux_003_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink3_channel       (cmd_demux_003_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink3_data          (cmd_demux_003_src0_data),                                                     //   input,  width = 146,          .data
		.sink3_startofpacket (cmd_demux_003_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (cmd_demux_003_src0_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_003 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_003_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src3_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src3_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src3_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src3_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src3_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src3_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src3_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src3_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src3_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src3_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src3_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src3_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_004 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_004_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_004_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_004_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_004_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_004_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_004_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src4_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src4_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src4_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src4_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src4_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src4_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src4_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src4_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src4_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src4_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src4_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src4_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_005 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_005_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_005_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_005_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_005_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_005_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_005_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src5_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src5_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src5_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src5_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src5_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src5_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src5_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src5_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src5_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src5_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src5_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src5_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_006 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_006_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_006_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_006_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_006_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_006_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_006_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src6_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src6_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src6_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src6_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src6_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src6_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src6_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src6_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src6_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src6_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src6_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src6_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_007 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_007_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_007_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_007_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_007_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_007_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_007_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src7_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src7_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src7_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src7_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src7_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src7_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src7_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src7_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src7_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src7_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src7_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src7_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_008 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_008_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_008_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_008_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_008_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_008_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_008_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src8_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src8_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src8_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src8_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src8_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src8_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src8_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src8_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src8_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src8_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src8_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src8_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_009 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_009_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_009_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_009_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_009_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_009_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_009_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src9_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src9_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src9_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src9_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src9_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src9_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src9_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src9_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src9_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src9_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src9_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src9_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_010 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_010_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_010_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_010_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_010_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_010_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_010_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src10_ready),                                                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src10_valid),                                                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src10_channel),                                                     //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src10_data),                                                        //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src10_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src10_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src10_ready),                                                   //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src10_valid),                                                   //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src10_channel),                                                 //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src10_data),                                                    //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src10_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src10_endofpacket)                                              //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_011 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_011_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_011_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_011_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_011_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_011_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_011_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src11_ready),                                                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src11_valid),                                                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src11_channel),                                                     //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src11_data),                                                        //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src11_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src11_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src11_ready),                                                   //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src11_valid),                                                   //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src11_channel),                                                 //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src11_data),                                                    //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src11_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src11_endofpacket)                                              //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_qysncvq cmd_mux_012 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_012_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_012_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_012_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_012_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_012_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_012_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src12_ready),                                                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src12_valid),                                                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src12_channel),                                                     //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src12_data),                                                        //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src12_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src12_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src12_ready),                                                   //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src12_valid),                                                   //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src12_channel),                                                 //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src12_data),                                                    //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src12_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src12_endofpacket),                                             //   input,    width = 1,          .endofpacket
		.sink2_ready         (cmd_demux_002_src1_ready),                                                    //  output,    width = 1,     sink2.ready
		.sink2_valid         (cmd_demux_002_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink2_channel       (cmd_demux_002_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink2_data          (cmd_demux_002_src1_data),                                                     //   input,  width = 146,          .data
		.sink2_startofpacket (cmd_demux_002_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (cmd_demux_002_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink3_ready         (cmd_demux_003_src1_ready),                                                    //  output,    width = 1,     sink3.ready
		.sink3_valid         (cmd_demux_003_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink3_channel       (cmd_demux_003_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink3_data          (cmd_demux_003_src1_data),                                                     //   input,  width = 146,          .data
		.sink3_startofpacket (cmd_demux_003_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink3_endofpacket   (cmd_demux_003_src1_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_k76kzey cmd_mux_013 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_013_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_013_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (cmd_mux_013_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (cmd_mux_013_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (cmd_mux_013_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_013_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (cmd_demux_src13_ready),                                                       //  output,    width = 1,     sink0.ready
		.sink0_valid         (cmd_demux_src13_valid),                                                       //   input,    width = 1,          .valid
		.sink0_channel       (cmd_demux_src13_channel),                                                     //   input,   width = 14,          .channel
		.sink0_data          (cmd_demux_src13_data),                                                        //   input,  width = 146,          .data
		.sink0_startofpacket (cmd_demux_src13_startofpacket),                                               //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (cmd_demux_src13_endofpacket),                                                 //   input,    width = 1,          .endofpacket
		.sink1_ready         (cmd_demux_001_src13_ready),                                                   //  output,    width = 1,     sink1.ready
		.sink1_valid         (cmd_demux_001_src13_valid),                                                   //   input,    width = 1,          .valid
		.sink1_channel       (cmd_demux_001_src13_channel),                                                 //   input,   width = 14,          .channel
		.sink1_data          (cmd_demux_001_src13_data),                                                    //   input,  width = 146,          .data
		.sink1_startofpacket (cmd_demux_001_src13_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (cmd_demux_001_src13_endofpacket)                                              //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_004_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_004_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_004_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_004_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_004_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_004_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                                        //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                                        //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                                         //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_src0_channel),                                                      //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                                                  //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                                                        //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                                                        //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_src1_data),                                                         //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_src1_channel),                                                      //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                                                //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                                                   //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_001 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_005_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_005_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_005_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_005_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_005_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_001_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_001_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_3ne2ekq rsp_demux_002 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_006_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_006_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_006_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_006_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_006_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_002_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_002_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_002_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_002_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_002_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_002_src1_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src2_ready         (rsp_demux_002_src2_ready),                                                    //   input,    width = 1,      src2.ready
		.src2_valid         (rsp_demux_002_src2_valid),                                                    //  output,    width = 1,          .valid
		.src2_data          (rsp_demux_002_src2_data),                                                     //  output,  width = 146,          .data
		.src2_channel       (rsp_demux_002_src2_channel),                                                  //  output,   width = 14,          .channel
		.src2_startofpacket (rsp_demux_002_src2_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (rsp_demux_002_src2_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src3_ready         (rsp_demux_002_src3_ready),                                                    //   input,    width = 1,      src3.ready
		.src3_valid         (rsp_demux_002_src3_valid),                                                    //  output,    width = 1,          .valid
		.src3_data          (rsp_demux_002_src3_data),                                                     //  output,  width = 146,          .data
		.src3_channel       (rsp_demux_002_src3_channel),                                                  //  output,   width = 14,          .channel
		.src3_startofpacket (rsp_demux_002_src3_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (rsp_demux_002_src3_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_003 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_007_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_007_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_007_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_007_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_007_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_003_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_003_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_003_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_003_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_003_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_003_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_004 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_008_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_008_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_008_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_008_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_008_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_004_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_004_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_004_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_004_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_004_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_004_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_004_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_004_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_004_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_004_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_004_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_004_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_005 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_009_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_009_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_009_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_009_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_009_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_009_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_005_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_005_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_005_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_005_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_005_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_005_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_005_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_005_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_005_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_005_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_005_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_005_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_006 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_010_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_010_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_010_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_010_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_010_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_010_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_006_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_006_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_006_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_006_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_006_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_006_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_006_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_006_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_006_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_006_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_006_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_006_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_007 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_011_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_011_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_011_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_011_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_011_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_011_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_007_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_007_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_007_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_007_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_007_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_007_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_007_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_007_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_007_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_007_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_007_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_007_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_008 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_012_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_012_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_012_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_012_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_012_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_012_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_008_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_008_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_008_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_008_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_008_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_008_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_008_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_008_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_008_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_008_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_008_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_008_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_009 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_013_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_013_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_013_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_013_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_013_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_013_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_009_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_009_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_009_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_009_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_009_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_009_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_009_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_009_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_009_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_009_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_009_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_009_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_010 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_014_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_014_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_014_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_014_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_014_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_014_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_010_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_010_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_010_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_010_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_010_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_010_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_010_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_010_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_010_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_010_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_010_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_010_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_011 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_015_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_015_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_015_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_015_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_015_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_015_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_011_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_011_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_011_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_011_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_011_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_011_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_011_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_011_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_011_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_011_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_011_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_011_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_3ne2ekq rsp_demux_012 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_016_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_016_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_016_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_016_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_016_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_016_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_012_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_012_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_012_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_012_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_012_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_012_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_012_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_012_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_012_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_012_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_012_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_012_src1_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src2_ready         (rsp_demux_012_src2_ready),                                                    //   input,    width = 1,      src2.ready
		.src2_valid         (rsp_demux_012_src2_valid),                                                    //  output,    width = 1,          .valid
		.src2_data          (rsp_demux_012_src2_data),                                                     //  output,  width = 146,          .data
		.src2_channel       (rsp_demux_012_src2_channel),                                                  //  output,   width = 14,          .channel
		.src2_startofpacket (rsp_demux_012_src2_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (rsp_demux_012_src2_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src3_ready         (rsp_demux_012_src3_ready),                                                    //   input,    width = 1,      src3.ready
		.src3_valid         (rsp_demux_012_src3_valid),                                                    //  output,    width = 1,          .valid
		.src3_data          (rsp_demux_012_src3_data),                                                     //  output,  width = 146,          .data
		.src3_channel       (rsp_demux_012_src3_channel),                                                  //  output,   width = 14,          .channel
		.src3_startofpacket (rsp_demux_012_src3_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src3_endofpacket   (rsp_demux_012_src3_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_demultiplexer_1921_q63uh4y rsp_demux_013 (
		.clk                (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset              (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_017_src_ready),                                                        //  output,    width = 1,      sink.ready
		.sink_channel       (router_017_src_channel),                                                      //   input,   width = 14,          .channel
		.sink_data          (router_017_src_data),                                                         //   input,  width = 146,          .data
		.sink_startofpacket (router_017_src_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_017_src_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink_valid         (router_017_src_valid),                                                        //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_013_src0_ready),                                                    //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_013_src0_valid),                                                    //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_013_src0_data),                                                     //  output,  width = 146,          .data
		.src0_channel       (rsp_demux_013_src0_channel),                                                  //  output,   width = 14,          .channel
		.src0_startofpacket (rsp_demux_013_src0_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_013_src0_endofpacket),                                              //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_013_src1_ready),                                                    //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_013_src1_valid),                                                    //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_013_src1_data),                                                     //  output,  width = 146,          .data
		.src1_channel       (rsp_demux_013_src1_channel),                                                  //  output,   width = 14,          .channel
		.src1_startofpacket (rsp_demux_013_src1_startofpacket),                                            //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_013_src1_endofpacket)                                               //  output,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_56vobdi rsp_mux (
		.clk                  (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset                (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready            (rsp_mux_src_ready),                                                           //   input,    width = 1,       src.ready
		.src_valid            (rsp_mux_src_valid),                                                           //  output,    width = 1,          .valid
		.src_data             (rsp_mux_src_data),                                                            //  output,  width = 146,          .data
		.src_channel          (rsp_mux_src_channel),                                                         //  output,   width = 14,          .channel
		.src_startofpacket    (rsp_mux_src_startofpacket),                                                   //  output,    width = 1,          .startofpacket
		.src_endofpacket      (rsp_mux_src_endofpacket),                                                     //  output,    width = 1,          .endofpacket
		.sink0_ready          (rsp_demux_src0_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid          (rsp_demux_src0_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel        (rsp_demux_src0_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data           (rsp_demux_src0_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket  (rsp_demux_src0_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket    (rsp_demux_src0_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready          (rsp_demux_001_src0_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid          (rsp_demux_001_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel        (rsp_demux_001_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data           (rsp_demux_001_src0_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket  (rsp_demux_001_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket    (rsp_demux_001_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink2_ready          (rsp_demux_002_src0_ready),                                                    //  output,    width = 1,     sink2.ready
		.sink2_valid          (rsp_demux_002_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink2_channel        (rsp_demux_002_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink2_data           (rsp_demux_002_src0_data),                                                     //   input,  width = 146,          .data
		.sink2_startofpacket  (rsp_demux_002_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink2_endofpacket    (rsp_demux_002_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink3_ready          (rsp_demux_003_src0_ready),                                                    //  output,    width = 1,     sink3.ready
		.sink3_valid          (rsp_demux_003_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink3_channel        (rsp_demux_003_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink3_data           (rsp_demux_003_src0_data),                                                     //   input,  width = 146,          .data
		.sink3_startofpacket  (rsp_demux_003_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink3_endofpacket    (rsp_demux_003_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink4_ready          (rsp_demux_004_src0_ready),                                                    //  output,    width = 1,     sink4.ready
		.sink4_valid          (rsp_demux_004_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink4_channel        (rsp_demux_004_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink4_data           (rsp_demux_004_src0_data),                                                     //   input,  width = 146,          .data
		.sink4_startofpacket  (rsp_demux_004_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink4_endofpacket    (rsp_demux_004_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink5_ready          (rsp_demux_005_src0_ready),                                                    //  output,    width = 1,     sink5.ready
		.sink5_valid          (rsp_demux_005_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink5_channel        (rsp_demux_005_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink5_data           (rsp_demux_005_src0_data),                                                     //   input,  width = 146,          .data
		.sink5_startofpacket  (rsp_demux_005_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink5_endofpacket    (rsp_demux_005_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink6_ready          (rsp_demux_006_src0_ready),                                                    //  output,    width = 1,     sink6.ready
		.sink6_valid          (rsp_demux_006_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink6_channel        (rsp_demux_006_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink6_data           (rsp_demux_006_src0_data),                                                     //   input,  width = 146,          .data
		.sink6_startofpacket  (rsp_demux_006_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink6_endofpacket    (rsp_demux_006_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink7_ready          (rsp_demux_007_src0_ready),                                                    //  output,    width = 1,     sink7.ready
		.sink7_valid          (rsp_demux_007_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink7_channel        (rsp_demux_007_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink7_data           (rsp_demux_007_src0_data),                                                     //   input,  width = 146,          .data
		.sink7_startofpacket  (rsp_demux_007_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink7_endofpacket    (rsp_demux_007_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink8_ready          (rsp_demux_008_src0_ready),                                                    //  output,    width = 1,     sink8.ready
		.sink8_valid          (rsp_demux_008_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink8_channel        (rsp_demux_008_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink8_data           (rsp_demux_008_src0_data),                                                     //   input,  width = 146,          .data
		.sink8_startofpacket  (rsp_demux_008_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink8_endofpacket    (rsp_demux_008_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink9_ready          (rsp_demux_009_src0_ready),                                                    //  output,    width = 1,     sink9.ready
		.sink9_valid          (rsp_demux_009_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink9_channel        (rsp_demux_009_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink9_data           (rsp_demux_009_src0_data),                                                     //   input,  width = 146,          .data
		.sink9_startofpacket  (rsp_demux_009_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink9_endofpacket    (rsp_demux_009_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink10_ready         (rsp_demux_010_src0_ready),                                                    //  output,    width = 1,    sink10.ready
		.sink10_valid         (rsp_demux_010_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink10_channel       (rsp_demux_010_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink10_data          (rsp_demux_010_src0_data),                                                     //   input,  width = 146,          .data
		.sink10_startofpacket (rsp_demux_010_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink10_endofpacket   (rsp_demux_010_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink11_ready         (rsp_demux_011_src0_ready),                                                    //  output,    width = 1,    sink11.ready
		.sink11_valid         (rsp_demux_011_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink11_channel       (rsp_demux_011_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink11_data          (rsp_demux_011_src0_data),                                                     //   input,  width = 146,          .data
		.sink11_startofpacket (rsp_demux_011_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink11_endofpacket   (rsp_demux_011_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink12_ready         (rsp_demux_012_src0_ready),                                                    //  output,    width = 1,    sink12.ready
		.sink12_valid         (rsp_demux_012_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink12_channel       (rsp_demux_012_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink12_data          (rsp_demux_012_src0_data),                                                     //   input,  width = 146,          .data
		.sink12_startofpacket (rsp_demux_012_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink12_endofpacket   (rsp_demux_012_src0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink13_ready         (rsp_demux_013_src0_ready),                                                    //  output,    width = 1,    sink13.ready
		.sink13_valid         (rsp_demux_013_src0_valid),                                                    //   input,    width = 1,          .valid
		.sink13_channel       (rsp_demux_013_src0_channel),                                                  //   input,   width = 14,          .channel
		.sink13_data          (rsp_demux_013_src0_data),                                                     //   input,  width = 146,          .data
		.sink13_startofpacket (rsp_demux_013_src0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink13_endofpacket   (rsp_demux_013_src0_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_56vobdi rsp_mux_001 (
		.clk                  (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset                (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready            (rsp_mux_001_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid            (rsp_mux_001_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data             (rsp_mux_001_src_data),                                                        //  output,  width = 146,          .data
		.src_channel          (rsp_mux_001_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket    (rsp_mux_001_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket      (rsp_mux_001_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready          (rsp_demux_src1_ready),                                                        //  output,    width = 1,     sink0.ready
		.sink0_valid          (rsp_demux_src1_valid),                                                        //   input,    width = 1,          .valid
		.sink0_channel        (rsp_demux_src1_channel),                                                      //   input,   width = 14,          .channel
		.sink0_data           (rsp_demux_src1_data),                                                         //   input,  width = 146,          .data
		.sink0_startofpacket  (rsp_demux_src1_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.sink0_endofpacket    (rsp_demux_src1_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.sink1_ready          (rsp_demux_001_src1_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid          (rsp_demux_001_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel        (rsp_demux_001_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data           (rsp_demux_001_src1_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket  (rsp_demux_001_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket    (rsp_demux_001_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink2_ready          (rsp_demux_002_src1_ready),                                                    //  output,    width = 1,     sink2.ready
		.sink2_valid          (rsp_demux_002_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink2_channel        (rsp_demux_002_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink2_data           (rsp_demux_002_src1_data),                                                     //   input,  width = 146,          .data
		.sink2_startofpacket  (rsp_demux_002_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink2_endofpacket    (rsp_demux_002_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink3_ready          (rsp_demux_003_src1_ready),                                                    //  output,    width = 1,     sink3.ready
		.sink3_valid          (rsp_demux_003_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink3_channel        (rsp_demux_003_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink3_data           (rsp_demux_003_src1_data),                                                     //   input,  width = 146,          .data
		.sink3_startofpacket  (rsp_demux_003_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink3_endofpacket    (rsp_demux_003_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink4_ready          (rsp_demux_004_src1_ready),                                                    //  output,    width = 1,     sink4.ready
		.sink4_valid          (rsp_demux_004_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink4_channel        (rsp_demux_004_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink4_data           (rsp_demux_004_src1_data),                                                     //   input,  width = 146,          .data
		.sink4_startofpacket  (rsp_demux_004_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink4_endofpacket    (rsp_demux_004_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink5_ready          (rsp_demux_005_src1_ready),                                                    //  output,    width = 1,     sink5.ready
		.sink5_valid          (rsp_demux_005_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink5_channel        (rsp_demux_005_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink5_data           (rsp_demux_005_src1_data),                                                     //   input,  width = 146,          .data
		.sink5_startofpacket  (rsp_demux_005_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink5_endofpacket    (rsp_demux_005_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink6_ready          (rsp_demux_006_src1_ready),                                                    //  output,    width = 1,     sink6.ready
		.sink6_valid          (rsp_demux_006_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink6_channel        (rsp_demux_006_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink6_data           (rsp_demux_006_src1_data),                                                     //   input,  width = 146,          .data
		.sink6_startofpacket  (rsp_demux_006_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink6_endofpacket    (rsp_demux_006_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink7_ready          (rsp_demux_007_src1_ready),                                                    //  output,    width = 1,     sink7.ready
		.sink7_valid          (rsp_demux_007_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink7_channel        (rsp_demux_007_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink7_data           (rsp_demux_007_src1_data),                                                     //   input,  width = 146,          .data
		.sink7_startofpacket  (rsp_demux_007_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink7_endofpacket    (rsp_demux_007_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink8_ready          (rsp_demux_008_src1_ready),                                                    //  output,    width = 1,     sink8.ready
		.sink8_valid          (rsp_demux_008_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink8_channel        (rsp_demux_008_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink8_data           (rsp_demux_008_src1_data),                                                     //   input,  width = 146,          .data
		.sink8_startofpacket  (rsp_demux_008_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink8_endofpacket    (rsp_demux_008_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink9_ready          (rsp_demux_009_src1_ready),                                                    //  output,    width = 1,     sink9.ready
		.sink9_valid          (rsp_demux_009_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink9_channel        (rsp_demux_009_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink9_data           (rsp_demux_009_src1_data),                                                     //   input,  width = 146,          .data
		.sink9_startofpacket  (rsp_demux_009_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink9_endofpacket    (rsp_demux_009_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink10_ready         (rsp_demux_010_src1_ready),                                                    //  output,    width = 1,    sink10.ready
		.sink10_valid         (rsp_demux_010_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink10_channel       (rsp_demux_010_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink10_data          (rsp_demux_010_src1_data),                                                     //   input,  width = 146,          .data
		.sink10_startofpacket (rsp_demux_010_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink10_endofpacket   (rsp_demux_010_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink11_ready         (rsp_demux_011_src1_ready),                                                    //  output,    width = 1,    sink11.ready
		.sink11_valid         (rsp_demux_011_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink11_channel       (rsp_demux_011_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink11_data          (rsp_demux_011_src1_data),                                                     //   input,  width = 146,          .data
		.sink11_startofpacket (rsp_demux_011_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink11_endofpacket   (rsp_demux_011_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink12_ready         (rsp_demux_012_src1_ready),                                                    //  output,    width = 1,    sink12.ready
		.sink12_valid         (rsp_demux_012_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink12_channel       (rsp_demux_012_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink12_data          (rsp_demux_012_src1_data),                                                     //   input,  width = 146,          .data
		.sink12_startofpacket (rsp_demux_012_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink12_endofpacket   (rsp_demux_012_src1_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink13_ready         (rsp_demux_013_src1_ready),                                                    //  output,    width = 1,    sink13.ready
		.sink13_valid         (rsp_demux_013_src1_valid),                                                    //   input,    width = 1,          .valid
		.sink13_channel       (rsp_demux_013_src1_channel),                                                  //   input,   width = 14,          .channel
		.sink13_data          (rsp_demux_013_src1_data),                                                     //   input,  width = 146,          .data
		.sink13_startofpacket (rsp_demux_013_src1_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink13_endofpacket   (rsp_demux_013_src1_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_yih4mkq rsp_mux_002 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_002_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (rsp_mux_002_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (rsp_mux_002_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_002_src2_ready),                                                    //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_002_src2_valid),                                                    //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_002_src2_channel),                                                  //   input,   width = 14,          .channel
		.sink0_data          (rsp_demux_002_src2_data),                                                     //   input,  width = 146,          .data
		.sink0_startofpacket (rsp_demux_002_src2_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_002_src2_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_012_src2_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_012_src2_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_012_src2_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (rsp_demux_012_src2_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (rsp_demux_012_src2_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_012_src2_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

	system_altera_merlin_multiplexer_1922_yih4mkq rsp_mux_003 (
		.clk                 (clock_in_out_clk_clk),                                                        //   input,    width = 1,       clk.clk
		.reset               (intel_niosv_g_data_manager_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_003_src_ready),                                                       //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_003_src_valid),                                                       //  output,    width = 1,          .valid
		.src_data            (rsp_mux_003_src_data),                                                        //  output,  width = 146,          .data
		.src_channel         (rsp_mux_003_src_channel),                                                     //  output,   width = 14,          .channel
		.src_startofpacket   (rsp_mux_003_src_startofpacket),                                               //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_003_src_endofpacket),                                                 //  output,    width = 1,          .endofpacket
		.sink0_ready         (rsp_demux_002_src3_ready),                                                    //  output,    width = 1,     sink0.ready
		.sink0_valid         (rsp_demux_002_src3_valid),                                                    //   input,    width = 1,          .valid
		.sink0_channel       (rsp_demux_002_src3_channel),                                                  //   input,   width = 14,          .channel
		.sink0_data          (rsp_demux_002_src3_data),                                                     //   input,  width = 146,          .data
		.sink0_startofpacket (rsp_demux_002_src3_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (rsp_demux_002_src3_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.sink1_ready         (rsp_demux_012_src3_ready),                                                    //  output,    width = 1,     sink1.ready
		.sink1_valid         (rsp_demux_012_src3_valid),                                                    //   input,    width = 1,          .valid
		.sink1_channel       (rsp_demux_012_src3_channel),                                                  //   input,   width = 14,          .channel
		.sink1_data          (rsp_demux_012_src3_data),                                                     //   input,  width = 146,          .data
		.sink1_startofpacket (rsp_demux_012_src3_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (rsp_demux_012_src3_endofpacket)                                               //   input,    width = 1,          .endofpacket
	);

endmodule
