// hps_subsys_altera_mm_interconnect_1920_zvx2jfy.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module hps_subsys_altera_mm_interconnect_1920_zvx2jfy (
		output wire [26:0] emif_hps_s0_axil_awaddr,                                                //                                                 emif_hps_s0_axil.awaddr
		output wire [2:0]  emif_hps_s0_axil_awprot,                                                //                                                                 .awprot
		output wire        emif_hps_s0_axil_awvalid,                                               //                                                                 .awvalid
		input  wire        emif_hps_s0_axil_awready,                                               //                                                                 .awready
		output wire [31:0] emif_hps_s0_axil_wdata,                                                 //                                                                 .wdata
		output wire [3:0]  emif_hps_s0_axil_wstrb,                                                 //                                                                 .wstrb
		output wire        emif_hps_s0_axil_wvalid,                                                //                                                                 .wvalid
		input  wire        emif_hps_s0_axil_wready,                                                //                                                                 .wready
		input  wire [1:0]  emif_hps_s0_axil_bresp,                                                 //                                                                 .bresp
		input  wire        emif_hps_s0_axil_bvalid,                                                //                                                                 .bvalid
		output wire        emif_hps_s0_axil_bready,                                                //                                                                 .bready
		output wire [26:0] emif_hps_s0_axil_araddr,                                                //                                                                 .araddr
		output wire [2:0]  emif_hps_s0_axil_arprot,                                                //                                                                 .arprot
		output wire        emif_hps_s0_axil_arvalid,                                               //                                                                 .arvalid
		input  wire        emif_hps_s0_axil_arready,                                               //                                                                 .arready
		input  wire [31:0] emif_hps_s0_axil_rdata,                                                 //                                                                 .rdata
		input  wire [1:0]  emif_hps_s0_axil_rresp,                                                 //                                                                 .rresp
		input  wire        emif_hps_s0_axil_rvalid,                                                //                                                                 .rvalid
		output wire        emif_hps_s0_axil_rready,                                                //                                                                 .rready
		input  wire [31:0] agilex_hps_io96b0_csr_axi_awaddr,                                       //                                        agilex_hps_io96b0_csr_axi.awaddr
		input  wire [2:0]  agilex_hps_io96b0_csr_axi_awprot,                                       //                                                                 .awprot
		input  wire        agilex_hps_io96b0_csr_axi_awvalid,                                      //                                                                 .awvalid
		output wire        agilex_hps_io96b0_csr_axi_awready,                                      //                                                                 .awready
		input  wire [31:0] agilex_hps_io96b0_csr_axi_wdata,                                        //                                                                 .wdata
		input  wire [3:0]  agilex_hps_io96b0_csr_axi_wstrb,                                        //                                                                 .wstrb
		input  wire        agilex_hps_io96b0_csr_axi_wvalid,                                       //                                                                 .wvalid
		output wire        agilex_hps_io96b0_csr_axi_wready,                                       //                                                                 .wready
		output wire [1:0]  agilex_hps_io96b0_csr_axi_bresp,                                        //                                                                 .bresp
		output wire        agilex_hps_io96b0_csr_axi_bvalid,                                       //                                                                 .bvalid
		input  wire        agilex_hps_io96b0_csr_axi_bready,                                       //                                                                 .bready
		input  wire [31:0] agilex_hps_io96b0_csr_axi_araddr,                                       //                                                                 .araddr
		input  wire [2:0]  agilex_hps_io96b0_csr_axi_arprot,                                       //                                                                 .arprot
		input  wire        agilex_hps_io96b0_csr_axi_arvalid,                                      //                                                                 .arvalid
		output wire        agilex_hps_io96b0_csr_axi_arready,                                      //                                                                 .arready
		output wire [31:0] agilex_hps_io96b0_csr_axi_rdata,                                        //                                                                 .rdata
		output wire [1:0]  agilex_hps_io96b0_csr_axi_rresp,                                        //                                                                 .rresp
		output wire        agilex_hps_io96b0_csr_axi_rvalid,                                       //                                                                 .rvalid
		input  wire        agilex_hps_io96b0_csr_axi_rready,                                       //                                                                 .rready
		input  wire        agilex_hps_io96b0_csr_axi_id_pad_clk_reset_reset_bridge_in_reset_reset, // agilex_hps_io96b0_csr_axi_id_pad_clk_reset_reset_bridge_in_reset.reset,  Reset Input
		input  wire        emif_hps_s0_axil_clk_clk                                                //                                             emif_hps_s0_axil_clk.clk,    Clock Input
	);

	hps_subsys_altera_merlin_axi_translator_1950_yxywpoy #(
		.USE_S0_AWID                       (0),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (0),
		.USE_S0_AWLEN                      (0),
		.USE_S0_AWSIZE                     (0),
		.USE_S0_AWBURST                    (0),
		.USE_S0_AWLOCK                     (0),
		.USE_M0_AWLOCK                     (0),
		.USE_S0_AWCACHE                    (0),
		.USE_M0_AWCACHE                    (0),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (0),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (0),
		.USE_S0_BID                        (0),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (0),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (0),
		.USE_S0_ARLEN                      (0),
		.USE_S0_ARSIZE                     (0),
		.USE_S0_ARBURST                    (0),
		.USE_S0_ARLOCK                     (0),
		.USE_M0_ARLOCK                     (0),
		.USE_M0_ARCACHE                    (0),
		.USE_M0_ARQOS                      (0),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (0),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (0),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (0),
		.M0_ID_WIDTH                       (1),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (27),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (32),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (0),
		.USE_M0_ARUSER                     (0),
		.USE_M0_WUSER                      (0),
		.USE_M0_RUSER                      (0),
		.USE_M0_BUSER                      (0),
		.M0_AXI_VERSION                    ("AXI4Lite"),
		.M0_BURST_LENGTH_WIDTH             (4),
		.S0_BURST_LENGTH_WIDTH             (4),
		.M0_LOCK_WIDTH                     (2),
		.S0_LOCK_WIDTH                     (2),
		.S0_AXI_VERSION                    ("AXI4Lite"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) agilex_hps_io96b0_csr_axi_id_pad (
		.aclk              (emif_hps_s0_axil_clk_clk),                                                //   input,   width = 1,       clk.clk
		.aresetn           (~agilex_hps_io96b0_csr_axi_id_pad_clk_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awaddr         (emif_hps_s0_axil_awaddr),                                                 //  output,  width = 27,        m0.awaddr
		.m0_awprot         (emif_hps_s0_axil_awprot),                                                 //  output,   width = 3,          .awprot
		.m0_awvalid        (emif_hps_s0_axil_awvalid),                                                //  output,   width = 1,          .awvalid
		.m0_awready        (emif_hps_s0_axil_awready),                                                //   input,   width = 1,          .awready
		.m0_wdata          (emif_hps_s0_axil_wdata),                                                  //  output,  width = 32,          .wdata
		.m0_wstrb          (emif_hps_s0_axil_wstrb),                                                  //  output,   width = 4,          .wstrb
		.m0_wvalid         (emif_hps_s0_axil_wvalid),                                                 //  output,   width = 1,          .wvalid
		.m0_wready         (emif_hps_s0_axil_wready),                                                 //   input,   width = 1,          .wready
		.m0_bresp          (emif_hps_s0_axil_bresp),                                                  //   input,   width = 2,          .bresp
		.m0_bvalid         (emif_hps_s0_axil_bvalid),                                                 //   input,   width = 1,          .bvalid
		.m0_bready         (emif_hps_s0_axil_bready),                                                 //  output,   width = 1,          .bready
		.m0_araddr         (emif_hps_s0_axil_araddr),                                                 //  output,  width = 27,          .araddr
		.m0_arprot         (emif_hps_s0_axil_arprot),                                                 //  output,   width = 3,          .arprot
		.m0_arvalid        (emif_hps_s0_axil_arvalid),                                                //  output,   width = 1,          .arvalid
		.m0_arready        (emif_hps_s0_axil_arready),                                                //   input,   width = 1,          .arready
		.m0_rdata          (emif_hps_s0_axil_rdata),                                                  //   input,  width = 32,          .rdata
		.m0_rresp          (emif_hps_s0_axil_rresp),                                                  //   input,   width = 2,          .rresp
		.m0_rvalid         (emif_hps_s0_axil_rvalid),                                                 //   input,   width = 1,          .rvalid
		.m0_rready         (emif_hps_s0_axil_rready),                                                 //  output,   width = 1,          .rready
		.s0_awaddr         (agilex_hps_io96b0_csr_axi_awaddr),                                        //   input,  width = 32,        s0.awaddr
		.s0_awprot         (agilex_hps_io96b0_csr_axi_awprot),                                        //   input,   width = 3,          .awprot
		.s0_awvalid        (agilex_hps_io96b0_csr_axi_awvalid),                                       //   input,   width = 1,          .awvalid
		.s0_awready        (agilex_hps_io96b0_csr_axi_awready),                                       //  output,   width = 1,          .awready
		.s0_wdata          (agilex_hps_io96b0_csr_axi_wdata),                                         //   input,  width = 32,          .wdata
		.s0_wstrb          (agilex_hps_io96b0_csr_axi_wstrb),                                         //   input,   width = 4,          .wstrb
		.s0_wvalid         (agilex_hps_io96b0_csr_axi_wvalid),                                        //   input,   width = 1,          .wvalid
		.s0_wready         (agilex_hps_io96b0_csr_axi_wready),                                        //  output,   width = 1,          .wready
		.s0_bresp          (agilex_hps_io96b0_csr_axi_bresp),                                         //  output,   width = 2,          .bresp
		.s0_bvalid         (agilex_hps_io96b0_csr_axi_bvalid),                                        //  output,   width = 1,          .bvalid
		.s0_bready         (agilex_hps_io96b0_csr_axi_bready),                                        //   input,   width = 1,          .bready
		.s0_araddr         (agilex_hps_io96b0_csr_axi_araddr),                                        //   input,  width = 32,          .araddr
		.s0_arprot         (agilex_hps_io96b0_csr_axi_arprot),                                        //   input,   width = 3,          .arprot
		.s0_arvalid        (agilex_hps_io96b0_csr_axi_arvalid),                                       //   input,   width = 1,          .arvalid
		.s0_arready        (agilex_hps_io96b0_csr_axi_arready),                                       //  output,   width = 1,          .arready
		.s0_rdata          (agilex_hps_io96b0_csr_axi_rdata),                                         //  output,  width = 32,          .rdata
		.s0_rresp          (agilex_hps_io96b0_csr_axi_rresp),                                         //  output,   width = 2,          .rresp
		.s0_rvalid         (agilex_hps_io96b0_csr_axi_rvalid),                                        //  output,   width = 1,          .rvalid
		.s0_rready         (agilex_hps_io96b0_csr_axi_rready),                                        //   input,   width = 1,          .rready
		.m0_wuser_datachk  (),                                                                        // (terminated),                        
		.m0_wuser_data     (),                                                                        // (terminated),                        
		.m0_wuser_poison   (),                                                                        // (terminated),                        
		.m0_awuser_addrchk (),                                                                        // (terminated),                        
		.m0_awuser_sai     (),                                                                        // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                                                 // (terminated),                        
		.m0_ruser_data     (4'b0000),                                                                 // (terminated),                        
		.m0_ruser_poison   (1'b0),                                                                    // (terminated),                        
		.m0_aruser_addrchk (),                                                                        // (terminated),                        
		.m0_aruser_sai     (),                                                                        // (terminated),                        
		.s0_ruser_datachk  (),                                                                        // (terminated),                        
		.s0_ruser_data     (),                                                                        // (terminated),                        
		.s0_ruser_poison   (),                                                                        // (terminated),                        
		.s0_awuser_addrchk (4'b0000),                                                                 // (terminated),                        
		.s0_awuser_sai     (4'b0000),                                                                 // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                                                 // (terminated),                        
		.s0_wuser_data     (4'b0000),                                                                 // (terminated),                        
		.s0_wuser_poison   (1'b0),                                                                    // (terminated),                        
		.s0_aruser_addrchk (4'b0000),                                                                 // (terminated),                        
		.s0_aruser_sai     (4'b0000)                                                                  // (terminated),                        
	);

endmodule
