// system.v

// Generated using ACDS version 23.4 79

`timescale 1 ps / 1 ps
module system (
		input  wire [15:0] core_current_export,       //       core_current.export
		input  wire [15:0] core_voltage_export,       //       core_voltage.export
		input  wire [15:0] fan_speed1_export,         //         fan_speed1.export
		input  wire [15:0] fan_speed2_export,         //         fan_speed2.export
		input  wire [15:0] pin_status_export,         //         pin_status.export
		input  wire [15:0] power_in_current_export,   //   power_in_current.export
		input  wire [15:0] power_in_voltage_export,   //   power_in_voltage.export
		input  wire [15:0] temperature_board1_export, // temperature_board1.export
		input  wire [15:0] temperature_board2_export, // temperature_board2.export
		input  wire [15:0] temperature_board3_export, // temperature_board3.export
		input  wire [15:0] temperature_fpga_export,   //   temperature_fpga.export
		input  wire [15:0] temperature_power_export,  //  temperature_power.export
		input  wire [15:0] temperature_sdm_export,    //    temperature_sdm.export
		input  wire [15:0] temperature_xcvr1_export,  //  temperature_xcvr1.export
		input  wire [15:0] temperature_xcvr2_export,  //  temperature_xcvr2.export
		input  wire [15:0] temperature_xcvr3_export,  //  temperature_xcvr3.export
		input  wire        clock_in_clk,              //           clock_in.clk
		input  wire        reset_in0_reset,           //          reset_in0.reset
		input  wire        reset_in1_reset            //          reset_in1.reset
	);

	wire         clock_in_out_clk_clk;                                        // clock_in:out_clk -> [board_info_core_current:clk, board_info_core_voltage:clk, board_info_fan_speed1:clk, board_info_fan_speed2:clk, board_info_pin_status:clk, board_info_power_in_current:clk, board_info_power_in_voltage:clk, board_info_temperature_board1:clk, board_info_temperature_board2:clk, board_info_temperature_board3:clk, board_info_temperature_fpga:clk, board_info_temperature_power:clk, board_info_temperature_sdm:clk, board_info_temperature_xcvr1:clk, board_info_temperature_xcvr2:clk, board_info_temperature_xcvr3:clk, irq_mapper:clk, jtag_uart:clk, mm_interconnect_0:clock_in_out_clk_clk, nios2_gen2:clk, onchip_memory2:clk, reset_controller:clk, rst_controller:clk, rst_controller_001:clk, sysid_qsys:clock, timer:clk]
	wire  [31:0] nios2_gen2_data_master_readdata;                             // mm_interconnect_0:nios2_gen2_data_master_readdata -> nios2_gen2:d_readdata
	wire         nios2_gen2_data_master_waitrequest;                          // mm_interconnect_0:nios2_gen2_data_master_waitrequest -> nios2_gen2:d_waitrequest
	wire         nios2_gen2_data_master_debugaccess;                          // nios2_gen2:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_data_master_debugaccess
	wire  [20:0] nios2_gen2_data_master_address;                              // nios2_gen2:d_address -> mm_interconnect_0:nios2_gen2_data_master_address
	wire   [3:0] nios2_gen2_data_master_byteenable;                           // nios2_gen2:d_byteenable -> mm_interconnect_0:nios2_gen2_data_master_byteenable
	wire         nios2_gen2_data_master_read;                                 // nios2_gen2:d_read -> mm_interconnect_0:nios2_gen2_data_master_read
	wire         nios2_gen2_data_master_readdatavalid;                        // mm_interconnect_0:nios2_gen2_data_master_readdatavalid -> nios2_gen2:d_readdatavalid
	wire         nios2_gen2_data_master_write;                                // nios2_gen2:d_write -> mm_interconnect_0:nios2_gen2_data_master_write
	wire  [31:0] nios2_gen2_data_master_writedata;                            // nios2_gen2:d_writedata -> mm_interconnect_0:nios2_gen2_data_master_writedata
	wire  [31:0] nios2_gen2_instruction_master_readdata;                      // mm_interconnect_0:nios2_gen2_instruction_master_readdata -> nios2_gen2:i_readdata
	wire         nios2_gen2_instruction_master_waitrequest;                   // mm_interconnect_0:nios2_gen2_instruction_master_waitrequest -> nios2_gen2:i_waitrequest
	wire  [20:0] nios2_gen2_instruction_master_address;                       // nios2_gen2:i_address -> mm_interconnect_0:nios2_gen2_instruction_master_address
	wire         nios2_gen2_instruction_master_read;                          // nios2_gen2:i_read -> mm_interconnect_0:nios2_gen2_instruction_master_read
	wire         nios2_gen2_instruction_master_readdatavalid;                 // mm_interconnect_0:nios2_gen2_instruction_master_readdatavalid -> nios2_gen2:i_readdatavalid
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect;    // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata;      // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest;   // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
	wire   [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address;       // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;          // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;         // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata;     // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
	wire  [31:0] mm_interconnect_0_sysid_qsys_control_slave_readdata;         // sysid_qsys:readdata -> mm_interconnect_0:sysid_qsys_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_qsys_control_slave_address;          // mm_interconnect_0:sysid_qsys_control_slave_address -> sysid_qsys:address
	wire  [31:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_readdata;       // nios2_gen2:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_debug_mem_slave_readdata
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_waitrequest;    // nios2_gen2:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_debug_mem_slave_waitrequest
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_debugaccess;    // mm_interconnect_0:nios2_gen2_debug_mem_slave_debugaccess -> nios2_gen2:debug_mem_slave_debugaccess
	wire   [8:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_address;        // mm_interconnect_0:nios2_gen2_debug_mem_slave_address -> nios2_gen2:debug_mem_slave_address
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_read;           // mm_interconnect_0:nios2_gen2_debug_mem_slave_read -> nios2_gen2:debug_mem_slave_read
	wire   [3:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_byteenable;     // mm_interconnect_0:nios2_gen2_debug_mem_slave_byteenable -> nios2_gen2:debug_mem_slave_byteenable
	wire         mm_interconnect_0_nios2_gen2_debug_mem_slave_write;          // mm_interconnect_0:nios2_gen2_debug_mem_slave_write -> nios2_gen2:debug_mem_slave_write
	wire  [31:0] mm_interconnect_0_nios2_gen2_debug_mem_slave_writedata;      // mm_interconnect_0:nios2_gen2_debug_mem_slave_writedata -> nios2_gen2:debug_mem_slave_writedata
	wire         mm_interconnect_0_onchip_memory2_s1_chipselect;              // mm_interconnect_0:onchip_memory2_s1_chipselect -> onchip_memory2:chipselect
	wire  [31:0] mm_interconnect_0_onchip_memory2_s1_readdata;                // onchip_memory2:readdata -> mm_interconnect_0:onchip_memory2_s1_readdata
	wire  [16:0] mm_interconnect_0_onchip_memory2_s1_address;                 // mm_interconnect_0:onchip_memory2_s1_address -> onchip_memory2:address
	wire   [3:0] mm_interconnect_0_onchip_memory2_s1_byteenable;              // mm_interconnect_0:onchip_memory2_s1_byteenable -> onchip_memory2:byteenable
	wire         mm_interconnect_0_onchip_memory2_s1_write;                   // mm_interconnect_0:onchip_memory2_s1_write -> onchip_memory2:write
	wire  [31:0] mm_interconnect_0_onchip_memory2_s1_writedata;               // mm_interconnect_0:onchip_memory2_s1_writedata -> onchip_memory2:writedata
	wire         mm_interconnect_0_onchip_memory2_s1_clken;                   // mm_interconnect_0:onchip_memory2_s1_clken -> onchip_memory2:clken
	wire  [31:0] mm_interconnect_0_board_info_temperature_fpga_s1_readdata;   // board_info_temperature_fpga:readdata -> mm_interconnect_0:board_info_temperature_fpga_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_fpga_s1_address;    // mm_interconnect_0:board_info_temperature_fpga_s1_address -> board_info_temperature_fpga:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_board1_s1_readdata; // board_info_temperature_board1:readdata -> mm_interconnect_0:board_info_temperature_board1_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_board1_s1_address;  // mm_interconnect_0:board_info_temperature_board1_s1_address -> board_info_temperature_board1:address
	wire  [31:0] mm_interconnect_0_board_info_fan_speed1_s1_readdata;         // board_info_fan_speed1:readdata -> mm_interconnect_0:board_info_fan_speed1_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_fan_speed1_s1_address;          // mm_interconnect_0:board_info_fan_speed1_s1_address -> board_info_fan_speed1:address
	wire  [31:0] mm_interconnect_0_board_info_fan_speed2_s1_readdata;         // board_info_fan_speed2:readdata -> mm_interconnect_0:board_info_fan_speed2_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_fan_speed2_s1_address;          // mm_interconnect_0:board_info_fan_speed2_s1_address -> board_info_fan_speed2:address
	wire  [31:0] mm_interconnect_0_board_info_core_current_s1_readdata;       // board_info_core_current:readdata -> mm_interconnect_0:board_info_core_current_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_core_current_s1_address;        // mm_interconnect_0:board_info_core_current_s1_address -> board_info_core_current:address
	wire  [31:0] mm_interconnect_0_board_info_core_voltage_s1_readdata;       // board_info_core_voltage:readdata -> mm_interconnect_0:board_info_core_voltage_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_core_voltage_s1_address;        // mm_interconnect_0:board_info_core_voltage_s1_address -> board_info_core_voltage:address
	wire  [31:0] mm_interconnect_0_board_info_power_in_current_s1_readdata;   // board_info_power_in_current:readdata -> mm_interconnect_0:board_info_power_in_current_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_power_in_current_s1_address;    // mm_interconnect_0:board_info_power_in_current_s1_address -> board_info_power_in_current:address
	wire  [31:0] mm_interconnect_0_board_info_power_in_voltage_s1_readdata;   // board_info_power_in_voltage:readdata -> mm_interconnect_0:board_info_power_in_voltage_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_power_in_voltage_s1_address;    // mm_interconnect_0:board_info_power_in_voltage_s1_address -> board_info_power_in_voltage:address
	wire  [31:0] mm_interconnect_0_board_info_pin_status_s1_readdata;         // board_info_pin_status:readdata -> mm_interconnect_0:board_info_pin_status_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_pin_status_s1_address;          // mm_interconnect_0:board_info_pin_status_s1_address -> board_info_pin_status:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_sdm_s1_readdata;    // board_info_temperature_sdm:readdata -> mm_interconnect_0:board_info_temperature_sdm_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_sdm_s1_address;     // mm_interconnect_0:board_info_temperature_sdm_s1_address -> board_info_temperature_sdm:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_xcvr1_s1_readdata;  // board_info_temperature_xcvr1:readdata -> mm_interconnect_0:board_info_temperature_xcvr1_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_xcvr1_s1_address;   // mm_interconnect_0:board_info_temperature_xcvr1_s1_address -> board_info_temperature_xcvr1:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_board2_s1_readdata; // board_info_temperature_board2:readdata -> mm_interconnect_0:board_info_temperature_board2_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_board2_s1_address;  // mm_interconnect_0:board_info_temperature_board2_s1_address -> board_info_temperature_board2:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_xcvr2_s1_readdata;  // board_info_temperature_xcvr2:readdata -> mm_interconnect_0:board_info_temperature_xcvr2_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_xcvr2_s1_address;   // mm_interconnect_0:board_info_temperature_xcvr2_s1_address -> board_info_temperature_xcvr2:address
	wire         mm_interconnect_0_timer_s1_chipselect;                       // mm_interconnect_0:timer_s1_chipselect -> timer:chipselect
	wire  [15:0] mm_interconnect_0_timer_s1_readdata;                         // timer:readdata -> mm_interconnect_0:timer_s1_readdata
	wire   [2:0] mm_interconnect_0_timer_s1_address;                          // mm_interconnect_0:timer_s1_address -> timer:address
	wire         mm_interconnect_0_timer_s1_write;                            // mm_interconnect_0:timer_s1_write -> timer:write_n
	wire  [15:0] mm_interconnect_0_timer_s1_writedata;                        // mm_interconnect_0:timer_s1_writedata -> timer:writedata
	wire  [31:0] mm_interconnect_0_board_info_temperature_power_s1_readdata;  // board_info_temperature_power:readdata -> mm_interconnect_0:board_info_temperature_power_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_power_s1_address;   // mm_interconnect_0:board_info_temperature_power_s1_address -> board_info_temperature_power:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_board3_s1_readdata; // board_info_temperature_board3:readdata -> mm_interconnect_0:board_info_temperature_board3_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_board3_s1_address;  // mm_interconnect_0:board_info_temperature_board3_s1_address -> board_info_temperature_board3:address
	wire  [31:0] mm_interconnect_0_board_info_temperature_xcvr3_s1_readdata;  // board_info_temperature_xcvr3:readdata -> mm_interconnect_0:board_info_temperature_xcvr3_s1_readdata
	wire   [1:0] mm_interconnect_0_board_info_temperature_xcvr3_s1_address;   // mm_interconnect_0:board_info_temperature_xcvr3_s1_address -> board_info_temperature_xcvr3:address
	wire         irq_mapper_receiver0_irq;                                    // jtag_uart:av_irq -> irq_mapper:receiver0_irq
	wire         irq_mapper_receiver1_irq;                                    // timer:irq -> irq_mapper:receiver1_irq
	wire  [31:0] nios2_gen2_irq_irq;                                          // irq_mapper:sender_irq -> nios2_gen2:irq
	wire         rst_controller_reset_out_reset;                              // rst_controller:reset_out -> [board_info_core_current:reset_n, board_info_core_voltage:reset_n, board_info_fan_speed1:reset_n, board_info_fan_speed2:reset_n, board_info_pin_status:reset_n, board_info_power_in_current:reset_n, board_info_power_in_voltage:reset_n, board_info_temperature_board1:reset_n, board_info_temperature_board2:reset_n, board_info_temperature_board3:reset_n, board_info_temperature_fpga:reset_n, board_info_temperature_power:reset_n, board_info_temperature_sdm:reset_n, board_info_temperature_xcvr1:reset_n, board_info_temperature_xcvr2:reset_n, board_info_temperature_xcvr3:reset_n, jtag_uart:rst_n, mm_interconnect_0:jtag_uart_reset_reset_bridge_in_reset_reset, onchip_memory2:reset, rst_translator:in_reset, sysid_qsys:reset_n, timer:reset_n]
	wire         rst_controller_reset_out_reset_req;                          // rst_controller:reset_req -> [onchip_memory2:reset_req, rst_translator:reset_req_in]
	wire         reset_controller_reset_out_reset;                            // reset_controller:reset_out -> [rst_controller:reset_in0, rst_controller_001:reset_in1]
	wire         rst_controller_001_reset_out_reset;                          // rst_controller_001:reset_out -> [irq_mapper:reset, mm_interconnect_0:nios2_gen2_reset_reset_bridge_in_reset_reset, nios2_gen2:reset_n]
	wire         rst_controller_001_reset_out_reset_req;                      // rst_controller_001:reset_req -> [nios2_gen2:reset_req, rst_translator_001:reset_req_in]
	wire         nios2_gen2_debug_reset_request_reset;                        // nios2_gen2:debug_reset_request -> rst_controller_001:reset_in0

	board_info_pio board_info_core_current (
		.clk      (clock_in_out_clk_clk),                                  //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                       //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_core_current_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_core_current_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (core_current_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_core_voltage (
		.clk      (clock_in_out_clk_clk),                                  //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                       //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_core_voltage_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_core_voltage_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (core_voltage_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_fan_speed1 (
		.clk      (clock_in_out_clk_clk),                                //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_fan_speed1_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_fan_speed1_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (fan_speed1_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_fan_speed2 (
		.clk      (clock_in_out_clk_clk),                                //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_fan_speed2_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_fan_speed2_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (fan_speed2_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_pin_status (
		.clk      (clock_in_out_clk_clk),                                //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_pin_status_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_pin_status_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (pin_status_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_power_in_current (
		.clk      (clock_in_out_clk_clk),                                      //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                           //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_power_in_current_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_power_in_current_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (power_in_current_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_power_in_voltage (
		.clk      (clock_in_out_clk_clk),                                      //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                           //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_power_in_voltage_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_power_in_voltage_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (power_in_voltage_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_board1 (
		.clk      (clock_in_out_clk_clk),                                        //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                             //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_board1_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_board1_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_board1_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_board2 (
		.clk      (clock_in_out_clk_clk),                                        //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                             //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_board2_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_board2_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_board2_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_board3 (
		.clk      (clock_in_out_clk_clk),                                        //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                             //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_board3_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_board3_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_board3_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_fpga (
		.clk      (clock_in_out_clk_clk),                                      //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                           //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_fpga_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_fpga_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_fpga_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_power (
		.clk      (clock_in_out_clk_clk),                                       //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                            //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_power_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_power_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_power_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_sdm (
		.clk      (clock_in_out_clk_clk),                                     //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                          //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_sdm_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_sdm_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_sdm_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_xcvr1 (
		.clk      (clock_in_out_clk_clk),                                       //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                            //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_xcvr1_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_xcvr1_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_xcvr1_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_xcvr2 (
		.clk      (clock_in_out_clk_clk),                                       //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                            //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_xcvr2_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_xcvr2_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_xcvr2_export)                                    //   input,  width = 16, external_connection.export
	);

	board_info_pio board_info_temperature_xcvr3 (
		.clk      (clock_in_out_clk_clk),                                       //   input,   width = 1,                 clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                            //   input,   width = 1,               reset.reset_n
		.address  (mm_interconnect_0_board_info_temperature_xcvr3_s1_address),  //   input,   width = 2,                  s1.address
		.readdata (mm_interconnect_0_board_info_temperature_xcvr3_s1_readdata), //  output,  width = 32,                    .readdata
		.in_port  (temperature_xcvr3_export)                                    //   input,  width = 16, external_connection.export
	);

	clock_in clock_in (
		.in_clk  (clock_in_clk),         //   input,  width = 1,  in_clk.clk
		.out_clk (clock_in_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	jtag_uart jtag_uart (
		.clk            (clock_in_out_clk_clk),                                      //   input,   width = 1,               clk.clk
		.rst_n          (~rst_controller_reset_out_reset),                           //   input,   width = 1,             reset.reset_n
		.av_chipselect  (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),  //   input,   width = 1, avalon_jtag_slave.chipselect
		.av_address     (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),     //   input,   width = 1,                  .address
		.av_read_n      (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),       //   input,   width = 1,                  .read_n
		.av_readdata    (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),    //  output,  width = 32,                  .readdata
		.av_write_n     (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),      //   input,   width = 1,                  .write_n
		.av_writedata   (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),   //   input,  width = 32,                  .writedata
		.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), //  output,   width = 1,                  .waitrequest
		.av_irq         (irq_mapper_receiver0_irq)                                   //  output,   width = 1,               irq.irq
	);

	nios2_gen2 nios2_gen2 (
		.clk                                 (clock_in_out_clk_clk),                                     //   input,   width = 1,                       clk.clk
		.reset_n                             (~rst_controller_001_reset_out_reset),                      //   input,   width = 1,                     reset.reset_n
		.reset_req                           (rst_controller_001_reset_out_reset_req),                   //   input,   width = 1,                          .reset_req
		.d_address                           (nios2_gen2_data_master_address),                           //  output,  width = 21,               data_master.address
		.d_byteenable                        (nios2_gen2_data_master_byteenable),                        //  output,   width = 4,                          .byteenable
		.d_read                              (nios2_gen2_data_master_read),                              //  output,   width = 1,                          .read
		.d_readdata                          (nios2_gen2_data_master_readdata),                          //   input,  width = 32,                          .readdata
		.d_waitrequest                       (nios2_gen2_data_master_waitrequest),                       //   input,   width = 1,                          .waitrequest
		.d_write                             (nios2_gen2_data_master_write),                             //  output,   width = 1,                          .write
		.d_writedata                         (nios2_gen2_data_master_writedata),                         //  output,  width = 32,                          .writedata
		.d_readdatavalid                     (nios2_gen2_data_master_readdatavalid),                     //   input,   width = 1,                          .readdatavalid
		.debug_mem_slave_debugaccess_to_roms (nios2_gen2_data_master_debugaccess),                       //  output,   width = 1,                          .debugaccess
		.i_address                           (nios2_gen2_instruction_master_address),                    //  output,  width = 21,        instruction_master.address
		.i_read                              (nios2_gen2_instruction_master_read),                       //  output,   width = 1,                          .read
		.i_readdata                          (nios2_gen2_instruction_master_readdata),                   //   input,  width = 32,                          .readdata
		.i_waitrequest                       (nios2_gen2_instruction_master_waitrequest),                //   input,   width = 1,                          .waitrequest
		.i_readdatavalid                     (nios2_gen2_instruction_master_readdatavalid),              //   input,   width = 1,                          .readdatavalid
		.irq                                 (nios2_gen2_irq_irq),                                       //   input,  width = 32,                       irq.irq
		.debug_reset_request                 (nios2_gen2_debug_reset_request_reset),                     //  output,   width = 1,       debug_reset_request.reset
		.debug_mem_slave_address             (mm_interconnect_0_nios2_gen2_debug_mem_slave_address),     //   input,   width = 9,           debug_mem_slave.address
		.debug_mem_slave_byteenable          (mm_interconnect_0_nios2_gen2_debug_mem_slave_byteenable),  //   input,   width = 4,                          .byteenable
		.debug_mem_slave_debugaccess         (mm_interconnect_0_nios2_gen2_debug_mem_slave_debugaccess), //   input,   width = 1,                          .debugaccess
		.debug_mem_slave_read                (mm_interconnect_0_nios2_gen2_debug_mem_slave_read),        //   input,   width = 1,                          .read
		.debug_mem_slave_readdata            (mm_interconnect_0_nios2_gen2_debug_mem_slave_readdata),    //  output,  width = 32,                          .readdata
		.debug_mem_slave_waitrequest         (mm_interconnect_0_nios2_gen2_debug_mem_slave_waitrequest), //  output,   width = 1,                          .waitrequest
		.debug_mem_slave_write               (mm_interconnect_0_nios2_gen2_debug_mem_slave_write),       //   input,   width = 1,                          .write
		.debug_mem_slave_writedata           (mm_interconnect_0_nios2_gen2_debug_mem_slave_writedata),   //   input,  width = 32,                          .writedata
		.dummy_ci_port                       ()                                                          //  output,   width = 1, custom_instruction_master.readra
	);

	onchip_memory2 onchip_memory2 (
		.clk        (clock_in_out_clk_clk),                           //   input,   width = 1,   clk1.clk
		.address    (mm_interconnect_0_onchip_memory2_s1_address),    //   input,  width = 17,     s1.address
		.clken      (mm_interconnect_0_onchip_memory2_s1_clken),      //   input,   width = 1,       .clken
		.chipselect (mm_interconnect_0_onchip_memory2_s1_chipselect), //   input,   width = 1,       .chipselect
		.write      (mm_interconnect_0_onchip_memory2_s1_write),      //   input,   width = 1,       .write
		.readdata   (mm_interconnect_0_onchip_memory2_s1_readdata),   //  output,  width = 32,       .readdata
		.writedata  (mm_interconnect_0_onchip_memory2_s1_writedata),  //   input,  width = 32,       .writedata
		.byteenable (mm_interconnect_0_onchip_memory2_s1_byteenable), //   input,   width = 4,       .byteenable
		.reset      (rst_controller_reset_out_reset),                 //   input,   width = 1, reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)              //   input,   width = 1,       .reset_req
	);

	reset_controller reset_controller (
		.reset_in0 (reset_in0_reset),                  //   input,  width = 1, reset_in0.reset
		.reset_in1 (reset_in1_reset),                  //   input,  width = 1, reset_in1.reset
		.clk       (clock_in_out_clk_clk),             //   input,  width = 1,       clk.clk
		.reset_out (reset_controller_reset_out_reset)  //  output,  width = 1, reset_out.reset
	);

	sysid_qsys sysid_qsys (
		.clock    (clock_in_out_clk_clk),                                //   input,   width = 1,           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                     //   input,   width = 1,         reset.reset_n
		.readdata (mm_interconnect_0_sysid_qsys_control_slave_readdata), //  output,  width = 32, control_slave.readdata
		.address  (mm_interconnect_0_sysid_qsys_control_slave_address)   //   input,   width = 1,              .address
	);

	timer timer (
		.clk        (clock_in_out_clk_clk),                  //   input,   width = 1,   clk.clk
		.reset_n    (~rst_controller_reset_out_reset),       //   input,   width = 1, reset.reset_n
		.address    (mm_interconnect_0_timer_s1_address),    //   input,   width = 3,    s1.address
		.writedata  (mm_interconnect_0_timer_s1_writedata),  //   input,  width = 16,      .writedata
		.readdata   (mm_interconnect_0_timer_s1_readdata),   //  output,  width = 16,      .readdata
		.chipselect (mm_interconnect_0_timer_s1_chipselect), //   input,   width = 1,      .chipselect
		.write_n    (~mm_interconnect_0_timer_s1_write),     //   input,   width = 1,      .write_n
		.irq        (irq_mapper_receiver1_irq)               //  output,   width = 1,   irq.irq
	);

	system_altera_mm_interconnect_1920_mh2lfeq mm_interconnect_0 (
		.nios2_gen2_data_master_address               (nios2_gen2_data_master_address),                              //   input,  width = 21,                 nios2_gen2_data_master.address
		.nios2_gen2_data_master_waitrequest           (nios2_gen2_data_master_waitrequest),                          //  output,   width = 1,                                       .waitrequest
		.nios2_gen2_data_master_byteenable            (nios2_gen2_data_master_byteenable),                           //   input,   width = 4,                                       .byteenable
		.nios2_gen2_data_master_read                  (nios2_gen2_data_master_read),                                 //   input,   width = 1,                                       .read
		.nios2_gen2_data_master_readdata              (nios2_gen2_data_master_readdata),                             //  output,  width = 32,                                       .readdata
		.nios2_gen2_data_master_readdatavalid         (nios2_gen2_data_master_readdatavalid),                        //  output,   width = 1,                                       .readdatavalid
		.nios2_gen2_data_master_write                 (nios2_gen2_data_master_write),                                //   input,   width = 1,                                       .write
		.nios2_gen2_data_master_writedata             (nios2_gen2_data_master_writedata),                            //   input,  width = 32,                                       .writedata
		.nios2_gen2_data_master_debugaccess           (nios2_gen2_data_master_debugaccess),                          //   input,   width = 1,                                       .debugaccess
		.nios2_gen2_instruction_master_address        (nios2_gen2_instruction_master_address),                       //   input,  width = 21,          nios2_gen2_instruction_master.address
		.nios2_gen2_instruction_master_waitrequest    (nios2_gen2_instruction_master_waitrequest),                   //  output,   width = 1,                                       .waitrequest
		.nios2_gen2_instruction_master_read           (nios2_gen2_instruction_master_read),                          //   input,   width = 1,                                       .read
		.nios2_gen2_instruction_master_readdata       (nios2_gen2_instruction_master_readdata),                      //  output,  width = 32,                                       .readdata
		.nios2_gen2_instruction_master_readdatavalid  (nios2_gen2_instruction_master_readdatavalid),                 //  output,   width = 1,                                       .readdatavalid
		.jtag_uart_avalon_jtag_slave_address          (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address),       //  output,   width = 1,            jtag_uart_avalon_jtag_slave.address
		.jtag_uart_avalon_jtag_slave_write            (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write),         //  output,   width = 1,                                       .write
		.jtag_uart_avalon_jtag_slave_read             (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read),          //  output,   width = 1,                                       .read
		.jtag_uart_avalon_jtag_slave_readdata         (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata),      //   input,  width = 32,                                       .readdata
		.jtag_uart_avalon_jtag_slave_writedata        (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata),     //  output,  width = 32,                                       .writedata
		.jtag_uart_avalon_jtag_slave_waitrequest      (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest),   //   input,   width = 1,                                       .waitrequest
		.jtag_uart_avalon_jtag_slave_chipselect       (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect),    //  output,   width = 1,                                       .chipselect
		.sysid_qsys_control_slave_address             (mm_interconnect_0_sysid_qsys_control_slave_address),          //  output,   width = 1,               sysid_qsys_control_slave.address
		.sysid_qsys_control_slave_readdata            (mm_interconnect_0_sysid_qsys_control_slave_readdata),         //   input,  width = 32,                                       .readdata
		.nios2_gen2_debug_mem_slave_address           (mm_interconnect_0_nios2_gen2_debug_mem_slave_address),        //  output,   width = 9,             nios2_gen2_debug_mem_slave.address
		.nios2_gen2_debug_mem_slave_write             (mm_interconnect_0_nios2_gen2_debug_mem_slave_write),          //  output,   width = 1,                                       .write
		.nios2_gen2_debug_mem_slave_read              (mm_interconnect_0_nios2_gen2_debug_mem_slave_read),           //  output,   width = 1,                                       .read
		.nios2_gen2_debug_mem_slave_readdata          (mm_interconnect_0_nios2_gen2_debug_mem_slave_readdata),       //   input,  width = 32,                                       .readdata
		.nios2_gen2_debug_mem_slave_writedata         (mm_interconnect_0_nios2_gen2_debug_mem_slave_writedata),      //  output,  width = 32,                                       .writedata
		.nios2_gen2_debug_mem_slave_byteenable        (mm_interconnect_0_nios2_gen2_debug_mem_slave_byteenable),     //  output,   width = 4,                                       .byteenable
		.nios2_gen2_debug_mem_slave_waitrequest       (mm_interconnect_0_nios2_gen2_debug_mem_slave_waitrequest),    //   input,   width = 1,                                       .waitrequest
		.nios2_gen2_debug_mem_slave_debugaccess       (mm_interconnect_0_nios2_gen2_debug_mem_slave_debugaccess),    //  output,   width = 1,                                       .debugaccess
		.onchip_memory2_s1_address                    (mm_interconnect_0_onchip_memory2_s1_address),                 //  output,  width = 17,                      onchip_memory2_s1.address
		.onchip_memory2_s1_write                      (mm_interconnect_0_onchip_memory2_s1_write),                   //  output,   width = 1,                                       .write
		.onchip_memory2_s1_readdata                   (mm_interconnect_0_onchip_memory2_s1_readdata),                //   input,  width = 32,                                       .readdata
		.onchip_memory2_s1_writedata                  (mm_interconnect_0_onchip_memory2_s1_writedata),               //  output,  width = 32,                                       .writedata
		.onchip_memory2_s1_byteenable                 (mm_interconnect_0_onchip_memory2_s1_byteenable),              //  output,   width = 4,                                       .byteenable
		.onchip_memory2_s1_chipselect                 (mm_interconnect_0_onchip_memory2_s1_chipselect),              //  output,   width = 1,                                       .chipselect
		.onchip_memory2_s1_clken                      (mm_interconnect_0_onchip_memory2_s1_clken),                   //  output,   width = 1,                                       .clken
		.board_info_temperature_fpga_s1_address       (mm_interconnect_0_board_info_temperature_fpga_s1_address),    //  output,   width = 2,         board_info_temperature_fpga_s1.address
		.board_info_temperature_fpga_s1_readdata      (mm_interconnect_0_board_info_temperature_fpga_s1_readdata),   //   input,  width = 32,                                       .readdata
		.board_info_temperature_board1_s1_address     (mm_interconnect_0_board_info_temperature_board1_s1_address),  //  output,   width = 2,       board_info_temperature_board1_s1.address
		.board_info_temperature_board1_s1_readdata    (mm_interconnect_0_board_info_temperature_board1_s1_readdata), //   input,  width = 32,                                       .readdata
		.board_info_fan_speed1_s1_address             (mm_interconnect_0_board_info_fan_speed1_s1_address),          //  output,   width = 2,               board_info_fan_speed1_s1.address
		.board_info_fan_speed1_s1_readdata            (mm_interconnect_0_board_info_fan_speed1_s1_readdata),         //   input,  width = 32,                                       .readdata
		.board_info_fan_speed2_s1_address             (mm_interconnect_0_board_info_fan_speed2_s1_address),          //  output,   width = 2,               board_info_fan_speed2_s1.address
		.board_info_fan_speed2_s1_readdata            (mm_interconnect_0_board_info_fan_speed2_s1_readdata),         //   input,  width = 32,                                       .readdata
		.board_info_core_current_s1_address           (mm_interconnect_0_board_info_core_current_s1_address),        //  output,   width = 2,             board_info_core_current_s1.address
		.board_info_core_current_s1_readdata          (mm_interconnect_0_board_info_core_current_s1_readdata),       //   input,  width = 32,                                       .readdata
		.board_info_core_voltage_s1_address           (mm_interconnect_0_board_info_core_voltage_s1_address),        //  output,   width = 2,             board_info_core_voltage_s1.address
		.board_info_core_voltage_s1_readdata          (mm_interconnect_0_board_info_core_voltage_s1_readdata),       //   input,  width = 32,                                       .readdata
		.board_info_power_in_current_s1_address       (mm_interconnect_0_board_info_power_in_current_s1_address),    //  output,   width = 2,         board_info_power_in_current_s1.address
		.board_info_power_in_current_s1_readdata      (mm_interconnect_0_board_info_power_in_current_s1_readdata),   //   input,  width = 32,                                       .readdata
		.board_info_power_in_voltage_s1_address       (mm_interconnect_0_board_info_power_in_voltage_s1_address),    //  output,   width = 2,         board_info_power_in_voltage_s1.address
		.board_info_power_in_voltage_s1_readdata      (mm_interconnect_0_board_info_power_in_voltage_s1_readdata),   //   input,  width = 32,                                       .readdata
		.board_info_pin_status_s1_address             (mm_interconnect_0_board_info_pin_status_s1_address),          //  output,   width = 2,               board_info_pin_status_s1.address
		.board_info_pin_status_s1_readdata            (mm_interconnect_0_board_info_pin_status_s1_readdata),         //   input,  width = 32,                                       .readdata
		.board_info_temperature_sdm_s1_address        (mm_interconnect_0_board_info_temperature_sdm_s1_address),     //  output,   width = 2,          board_info_temperature_sdm_s1.address
		.board_info_temperature_sdm_s1_readdata       (mm_interconnect_0_board_info_temperature_sdm_s1_readdata),    //   input,  width = 32,                                       .readdata
		.board_info_temperature_xcvr1_s1_address      (mm_interconnect_0_board_info_temperature_xcvr1_s1_address),   //  output,   width = 2,        board_info_temperature_xcvr1_s1.address
		.board_info_temperature_xcvr1_s1_readdata     (mm_interconnect_0_board_info_temperature_xcvr1_s1_readdata),  //   input,  width = 32,                                       .readdata
		.board_info_temperature_board2_s1_address     (mm_interconnect_0_board_info_temperature_board2_s1_address),  //  output,   width = 2,       board_info_temperature_board2_s1.address
		.board_info_temperature_board2_s1_readdata    (mm_interconnect_0_board_info_temperature_board2_s1_readdata), //   input,  width = 32,                                       .readdata
		.board_info_temperature_xcvr2_s1_address      (mm_interconnect_0_board_info_temperature_xcvr2_s1_address),   //  output,   width = 2,        board_info_temperature_xcvr2_s1.address
		.board_info_temperature_xcvr2_s1_readdata     (mm_interconnect_0_board_info_temperature_xcvr2_s1_readdata),  //   input,  width = 32,                                       .readdata
		.timer_s1_address                             (mm_interconnect_0_timer_s1_address),                          //  output,   width = 3,                               timer_s1.address
		.timer_s1_write                               (mm_interconnect_0_timer_s1_write),                            //  output,   width = 1,                                       .write
		.timer_s1_readdata                            (mm_interconnect_0_timer_s1_readdata),                         //   input,  width = 16,                                       .readdata
		.timer_s1_writedata                           (mm_interconnect_0_timer_s1_writedata),                        //  output,  width = 16,                                       .writedata
		.timer_s1_chipselect                          (mm_interconnect_0_timer_s1_chipselect),                       //  output,   width = 1,                                       .chipselect
		.board_info_temperature_power_s1_address      (mm_interconnect_0_board_info_temperature_power_s1_address),   //  output,   width = 2,        board_info_temperature_power_s1.address
		.board_info_temperature_power_s1_readdata     (mm_interconnect_0_board_info_temperature_power_s1_readdata),  //   input,  width = 32,                                       .readdata
		.board_info_temperature_board3_s1_address     (mm_interconnect_0_board_info_temperature_board3_s1_address),  //  output,   width = 2,       board_info_temperature_board3_s1.address
		.board_info_temperature_board3_s1_readdata    (mm_interconnect_0_board_info_temperature_board3_s1_readdata), //   input,  width = 32,                                       .readdata
		.board_info_temperature_xcvr3_s1_address      (mm_interconnect_0_board_info_temperature_xcvr3_s1_address),   //  output,   width = 2,        board_info_temperature_xcvr3_s1.address
		.board_info_temperature_xcvr3_s1_readdata     (mm_interconnect_0_board_info_temperature_xcvr3_s1_readdata),  //   input,  width = 32,                                       .readdata
		.nios2_gen2_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),                          //   input,   width = 1, nios2_gen2_reset_reset_bridge_in_reset.reset
		.jtag_uart_reset_reset_bridge_in_reset_reset  (rst_controller_reset_out_reset),                              //   input,   width = 1,  jtag_uart_reset_reset_bridge_in_reset.reset
		.clock_in_out_clk_clk                         (clock_in_out_clk_clk)                                         //   input,   width = 1,                       clock_in_out_clk.clk
	);

	system_altera_irq_mapper_2001_aobnkmq irq_mapper (
		.clk           (clock_in_out_clk_clk),               //   input,   width = 1,       clk.clk
		.reset         (rst_controller_001_reset_out_reset), //   input,   width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),           //   input,   width = 1, receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),           //   input,   width = 1, receiver1.irq
		.sender_irq    (nios2_gen2_irq_irq)                  //  output,  width = 32,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (reset_controller_reset_out_reset),   //   input,  width = 1, reset_in0.reset
		.clk            (clock_in_out_clk_clk),               //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset),     //  output,  width = 1, reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req), //  output,  width = 1,          .reset_req
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (2),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (nios2_gen2_debug_reset_request_reset),   //   input,  width = 1, reset_in0.reset
		.reset_in1      (reset_controller_reset_out_reset),       //   input,  width = 1, reset_in1.reset
		.clk            (clock_in_out_clk_clk),                   //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset),     //  output,  width = 1, reset_out.reset
		.reset_req      (rst_controller_001_reset_out_reset_req), //  output,  width = 1,          .reset_req
		.reset_req_in0  (1'b0),                                   // (terminated),                       
		.reset_req_in1  (1'b0),                                   // (terminated),                       
		.reset_in2      (1'b0),                                   // (terminated),                       
		.reset_req_in2  (1'b0),                                   // (terminated),                       
		.reset_in3      (1'b0),                                   // (terminated),                       
		.reset_req_in3  (1'b0),                                   // (terminated),                       
		.reset_in4      (1'b0),                                   // (terminated),                       
		.reset_req_in4  (1'b0),                                   // (terminated),                       
		.reset_in5      (1'b0),                                   // (terminated),                       
		.reset_req_in5  (1'b0),                                   // (terminated),                       
		.reset_in6      (1'b0),                                   // (terminated),                       
		.reset_req_in6  (1'b0),                                   // (terminated),                       
		.reset_in7      (1'b0),                                   // (terminated),                       
		.reset_req_in7  (1'b0),                                   // (terminated),                       
		.reset_in8      (1'b0),                                   // (terminated),                       
		.reset_req_in8  (1'b0),                                   // (terminated),                       
		.reset_in9      (1'b0),                                   // (terminated),                       
		.reset_req_in9  (1'b0),                                   // (terminated),                       
		.reset_in10     (1'b0),                                   // (terminated),                       
		.reset_req_in10 (1'b0),                                   // (terminated),                       
		.reset_in11     (1'b0),                                   // (terminated),                       
		.reset_req_in11 (1'b0),                                   // (terminated),                       
		.reset_in12     (1'b0),                                   // (terminated),                       
		.reset_req_in12 (1'b0),                                   // (terminated),                       
		.reset_in13     (1'b0),                                   // (terminated),                       
		.reset_req_in13 (1'b0),                                   // (terminated),                       
		.reset_in14     (1'b0),                                   // (terminated),                       
		.reset_req_in14 (1'b0),                                   // (terminated),                       
		.reset_in15     (1'b0),                                   // (terminated),                       
		.reset_req_in15 (1'b0)                                    // (terminated),                       
	);

endmodule
