module system (
		input  wire [15:0] core_current_export,       //       core_current.export
		input  wire [15:0] core_voltage_export,       //       core_voltage.export
		input  wire [15:0] fan_speed_export,          //          fan_speed.export
		input  wire [15:0] pin_status_export,         //         pin_status.export
		input  wire [15:0] power_in_voltage_export,   //   power_in_voltage.export
		input  wire [15:0] temperature_board1_export, // temperature_board1.export
		input  wire [15:0] temperature_board2_export, // temperature_board2.export
		input  wire [15:0] temperature_fpga_export,   //   temperature_fpga.export
		input  wire [15:0] temperature_power_export,  //  temperature_power.export
		input  wire [15:0] vcc1p2_current_export,     //     vcc1p2_current.export
		input  wire [15:0] vcc1p2_voltage_export,     //     vcc1p2_voltage.export
		input  wire        clock_in_clk,              //           clock_in.clk
		input  wire        reset_in0_reset,           //          reset_in0.reset
		input  wire        reset_in1_reset            //          reset_in1.reset
	);
endmodule

