// gts_inst.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module gts_inst (
		output wire [0:0] o_pma_cu_clk  // o_pma_cu_clk.clk, PMA clock from PLL for proper calculation.
	);

	gts_inst_intel_srcss_gts_300_wphg27q #(
		.SRC_RS_DISABLE      (1),
		.NUM_LANES_SHORELINE (1),
		.NUM_BANKS_SHORELINE (1)
	) intel_srcss_gts_inst (
		.o_pma_cu_clk      (o_pma_cu_clk), //  output,  width = 1, o_pma_cu_clk.clk
		.o_src_rs_grant    (),             // (terminated),                          
		.i_src_rs_priority (1'b0),         // (terminated),                          
		.i_src_rs_req      (1'b0)          // (terminated),                          
	);

endmodule
