/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'intel_niosv_g' in SOPC Builder design 'system'
 *
 * Generated: Sun Apr 21 10:29:39 CST 2024
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "intel_niosv_g"
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_DATA_ADDR_WIDTH 0x20
#define ALT_CPU_DCACHE_LINE_SIZE 32
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_DCACHE_SIZE 4096
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HAS_CSR_SUPPORT 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_ICACHE_LINE_SIZE 32
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5
#define ALT_CPU_ICACHE_SIZE 4096
#define ALT_CPU_INST_ADDR_WIDTH 0x20
#define ALT_CPU_MTIME_OFFSET 0x00090000
#define ALT_CPU_NAME "intel_niosv_g"
#define ALT_CPU_NIOSV_CORE_VARIANT 3
#define ALT_CPU_NUM_GPR 32
#define ALT_CPU_RESET_ADDR 0x00000000
#define ALT_CPU_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND
#define ALT_CPU_TIMER_DEVICE_TYPE 2


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define BANTAMLAKE_CPU_FREQ 50000000u
#define BANTAMLAKE_DATA_ADDR_WIDTH 0x20
#define BANTAMLAKE_DCACHE_LINE_SIZE 32
#define BANTAMLAKE_DCACHE_LINE_SIZE_LOG2 5
#define BANTAMLAKE_DCACHE_SIZE 4096
#define BANTAMLAKE_HAS_CSR_SUPPORT 1
#define BANTAMLAKE_HAS_DEBUG_STUB
#define BANTAMLAKE_ICACHE_LINE_SIZE 32
#define BANTAMLAKE_ICACHE_LINE_SIZE_LOG2 5
#define BANTAMLAKE_ICACHE_SIZE 4096
#define BANTAMLAKE_INST_ADDR_WIDTH 0x20
#define BANTAMLAKE_MTIME_OFFSET 0x00090000
#define BANTAMLAKE_NIOSV_CORE_VARIANT 3
#define BANTAMLAKE_NUM_GPR 32
#define BANTAMLAKE_RESET_ADDR 0x00000000
#define BANTAMLAKE_TICKS_PER_SEC NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND
#define BANTAMLAKE_TIMER_DEVICE_TYPE 2


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __INTEL_NIOSV_G
#define __INTEL_ONCHIP_MEMORY


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "AGILEX5"
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
#define ALT_IRQ_BASE NULL
#define ALT_LOG_PORT "/dev/null"
#define ALT_LOG_PORT_BASE 0x0
#define ALT_LOG_PORT_DEV null
#define ALT_LOG_PORT_TYPE ""
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x90118
#define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x90118
#define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x90118
#define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_SYSTEM_NAME "system"
#define ALT_SYS_CLK_TICKS_PER_SEC ALT_CPU_TICKS_PER_SEC
#define ALT_TIMESTAMP_CLK_TIMER_DEVICE_TYPE ALT_CPU_TIMER_DEVICE_TYPE


/*
 * board_info_core_current configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_core_current altera_avalon_pio
#define BOARD_INFO_CORE_CURRENT_BASE 0x90060
#define BOARD_INFO_CORE_CURRENT_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_CORE_CURRENT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_CORE_CURRENT_CAPTURE 0
#define BOARD_INFO_CORE_CURRENT_DATA_WIDTH 16
#define BOARD_INFO_CORE_CURRENT_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_CORE_CURRENT_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_CORE_CURRENT_EDGE_TYPE "NONE"
#define BOARD_INFO_CORE_CURRENT_FREQ 50000000
#define BOARD_INFO_CORE_CURRENT_HAS_IN 1
#define BOARD_INFO_CORE_CURRENT_HAS_OUT 0
#define BOARD_INFO_CORE_CURRENT_HAS_TRI 0
#define BOARD_INFO_CORE_CURRENT_IRQ -1
#define BOARD_INFO_CORE_CURRENT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_CORE_CURRENT_IRQ_TYPE "NONE"
#define BOARD_INFO_CORE_CURRENT_NAME "/dev/board_info_core_current"
#define BOARD_INFO_CORE_CURRENT_RESET_VALUE 0
#define BOARD_INFO_CORE_CURRENT_SPAN 16
#define BOARD_INFO_CORE_CURRENT_TYPE "altera_avalon_pio"


/*
 * board_info_core_voltage configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_core_voltage altera_avalon_pio
#define BOARD_INFO_CORE_VOLTAGE_BASE 0x90070
#define BOARD_INFO_CORE_VOLTAGE_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_CORE_VOLTAGE_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_CORE_VOLTAGE_CAPTURE 0
#define BOARD_INFO_CORE_VOLTAGE_DATA_WIDTH 16
#define BOARD_INFO_CORE_VOLTAGE_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_CORE_VOLTAGE_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_CORE_VOLTAGE_EDGE_TYPE "NONE"
#define BOARD_INFO_CORE_VOLTAGE_FREQ 50000000
#define BOARD_INFO_CORE_VOLTAGE_HAS_IN 1
#define BOARD_INFO_CORE_VOLTAGE_HAS_OUT 0
#define BOARD_INFO_CORE_VOLTAGE_HAS_TRI 0
#define BOARD_INFO_CORE_VOLTAGE_IRQ -1
#define BOARD_INFO_CORE_VOLTAGE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_CORE_VOLTAGE_IRQ_TYPE "NONE"
#define BOARD_INFO_CORE_VOLTAGE_NAME "/dev/board_info_core_voltage"
#define BOARD_INFO_CORE_VOLTAGE_RESET_VALUE 0
#define BOARD_INFO_CORE_VOLTAGE_SPAN 16
#define BOARD_INFO_CORE_VOLTAGE_TYPE "altera_avalon_pio"


/*
 * board_info_fan_speed configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_fan_speed altera_avalon_pio
#define BOARD_INFO_FAN_SPEED_BASE 0x900d0
#define BOARD_INFO_FAN_SPEED_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_FAN_SPEED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_FAN_SPEED_CAPTURE 0
#define BOARD_INFO_FAN_SPEED_DATA_WIDTH 16
#define BOARD_INFO_FAN_SPEED_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_FAN_SPEED_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_FAN_SPEED_EDGE_TYPE "NONE"
#define BOARD_INFO_FAN_SPEED_FREQ 50000000
#define BOARD_INFO_FAN_SPEED_HAS_IN 1
#define BOARD_INFO_FAN_SPEED_HAS_OUT 0
#define BOARD_INFO_FAN_SPEED_HAS_TRI 0
#define BOARD_INFO_FAN_SPEED_IRQ -1
#define BOARD_INFO_FAN_SPEED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_FAN_SPEED_IRQ_TYPE "NONE"
#define BOARD_INFO_FAN_SPEED_NAME "/dev/board_info_fan_speed"
#define BOARD_INFO_FAN_SPEED_RESET_VALUE 0
#define BOARD_INFO_FAN_SPEED_SPAN 16
#define BOARD_INFO_FAN_SPEED_TYPE "altera_avalon_pio"


/*
 * board_info_pin_status configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_pin_status altera_avalon_pio
#define BOARD_INFO_PIN_STATUS_BASE 0x900a0
#define BOARD_INFO_PIN_STATUS_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_PIN_STATUS_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_PIN_STATUS_CAPTURE 0
#define BOARD_INFO_PIN_STATUS_DATA_WIDTH 16
#define BOARD_INFO_PIN_STATUS_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_PIN_STATUS_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_PIN_STATUS_EDGE_TYPE "NONE"
#define BOARD_INFO_PIN_STATUS_FREQ 50000000
#define BOARD_INFO_PIN_STATUS_HAS_IN 1
#define BOARD_INFO_PIN_STATUS_HAS_OUT 0
#define BOARD_INFO_PIN_STATUS_HAS_TRI 0
#define BOARD_INFO_PIN_STATUS_IRQ -1
#define BOARD_INFO_PIN_STATUS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_PIN_STATUS_IRQ_TYPE "NONE"
#define BOARD_INFO_PIN_STATUS_NAME "/dev/board_info_pin_status"
#define BOARD_INFO_PIN_STATUS_RESET_VALUE 0
#define BOARD_INFO_PIN_STATUS_SPAN 16
#define BOARD_INFO_PIN_STATUS_TYPE "altera_avalon_pio"


/*
 * board_info_power_in_voltage configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_power_in_voltage altera_avalon_pio
#define BOARD_INFO_POWER_IN_VOLTAGE_BASE 0x90100
#define BOARD_INFO_POWER_IN_VOLTAGE_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_POWER_IN_VOLTAGE_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_POWER_IN_VOLTAGE_CAPTURE 0
#define BOARD_INFO_POWER_IN_VOLTAGE_DATA_WIDTH 16
#define BOARD_INFO_POWER_IN_VOLTAGE_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_POWER_IN_VOLTAGE_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_POWER_IN_VOLTAGE_EDGE_TYPE "NONE"
#define BOARD_INFO_POWER_IN_VOLTAGE_FREQ 50000000
#define BOARD_INFO_POWER_IN_VOLTAGE_HAS_IN 1
#define BOARD_INFO_POWER_IN_VOLTAGE_HAS_OUT 0
#define BOARD_INFO_POWER_IN_VOLTAGE_HAS_TRI 0
#define BOARD_INFO_POWER_IN_VOLTAGE_IRQ -1
#define BOARD_INFO_POWER_IN_VOLTAGE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_POWER_IN_VOLTAGE_IRQ_TYPE "NONE"
#define BOARD_INFO_POWER_IN_VOLTAGE_NAME "/dev/board_info_power_in_voltage"
#define BOARD_INFO_POWER_IN_VOLTAGE_RESET_VALUE 0
#define BOARD_INFO_POWER_IN_VOLTAGE_SPAN 16
#define BOARD_INFO_POWER_IN_VOLTAGE_TYPE "altera_avalon_pio"


/*
 * board_info_temperature_board1 configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_temperature_board1 altera_avalon_pio
#define BOARD_INFO_TEMPERATURE_BOARD1_BASE 0x900b0
#define BOARD_INFO_TEMPERATURE_BOARD1_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_TEMPERATURE_BOARD1_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_TEMPERATURE_BOARD1_CAPTURE 0
#define BOARD_INFO_TEMPERATURE_BOARD1_DATA_WIDTH 16
#define BOARD_INFO_TEMPERATURE_BOARD1_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_TEMPERATURE_BOARD1_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_TEMPERATURE_BOARD1_EDGE_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_BOARD1_FREQ 50000000
#define BOARD_INFO_TEMPERATURE_BOARD1_HAS_IN 1
#define BOARD_INFO_TEMPERATURE_BOARD1_HAS_OUT 0
#define BOARD_INFO_TEMPERATURE_BOARD1_HAS_TRI 0
#define BOARD_INFO_TEMPERATURE_BOARD1_IRQ -1
#define BOARD_INFO_TEMPERATURE_BOARD1_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_TEMPERATURE_BOARD1_IRQ_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_BOARD1_NAME "/dev/board_info_temperature_board1"
#define BOARD_INFO_TEMPERATURE_BOARD1_RESET_VALUE 0
#define BOARD_INFO_TEMPERATURE_BOARD1_SPAN 16
#define BOARD_INFO_TEMPERATURE_BOARD1_TYPE "altera_avalon_pio"


/*
 * board_info_temperature_board2 configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_temperature_board2 altera_avalon_pio
#define BOARD_INFO_TEMPERATURE_BOARD2_BASE 0x90090
#define BOARD_INFO_TEMPERATURE_BOARD2_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_TEMPERATURE_BOARD2_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_TEMPERATURE_BOARD2_CAPTURE 0
#define BOARD_INFO_TEMPERATURE_BOARD2_DATA_WIDTH 16
#define BOARD_INFO_TEMPERATURE_BOARD2_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_TEMPERATURE_BOARD2_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_TEMPERATURE_BOARD2_EDGE_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_BOARD2_FREQ 50000000
#define BOARD_INFO_TEMPERATURE_BOARD2_HAS_IN 1
#define BOARD_INFO_TEMPERATURE_BOARD2_HAS_OUT 0
#define BOARD_INFO_TEMPERATURE_BOARD2_HAS_TRI 0
#define BOARD_INFO_TEMPERATURE_BOARD2_IRQ -1
#define BOARD_INFO_TEMPERATURE_BOARD2_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_TEMPERATURE_BOARD2_IRQ_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_BOARD2_NAME "/dev/board_info_temperature_board2"
#define BOARD_INFO_TEMPERATURE_BOARD2_RESET_VALUE 0
#define BOARD_INFO_TEMPERATURE_BOARD2_SPAN 16
#define BOARD_INFO_TEMPERATURE_BOARD2_TYPE "altera_avalon_pio"


/*
 * board_info_temperature_fpga configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_temperature_fpga altera_avalon_pio
#define BOARD_INFO_TEMPERATURE_FPGA_BASE 0x900c0
#define BOARD_INFO_TEMPERATURE_FPGA_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_TEMPERATURE_FPGA_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_TEMPERATURE_FPGA_CAPTURE 0
#define BOARD_INFO_TEMPERATURE_FPGA_DATA_WIDTH 16
#define BOARD_INFO_TEMPERATURE_FPGA_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_TEMPERATURE_FPGA_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_TEMPERATURE_FPGA_EDGE_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_FPGA_FREQ 50000000
#define BOARD_INFO_TEMPERATURE_FPGA_HAS_IN 1
#define BOARD_INFO_TEMPERATURE_FPGA_HAS_OUT 0
#define BOARD_INFO_TEMPERATURE_FPGA_HAS_TRI 0
#define BOARD_INFO_TEMPERATURE_FPGA_IRQ -1
#define BOARD_INFO_TEMPERATURE_FPGA_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_TEMPERATURE_FPGA_IRQ_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_FPGA_NAME "/dev/board_info_temperature_fpga"
#define BOARD_INFO_TEMPERATURE_FPGA_RESET_VALUE 0
#define BOARD_INFO_TEMPERATURE_FPGA_SPAN 16
#define BOARD_INFO_TEMPERATURE_FPGA_TYPE "altera_avalon_pio"


/*
 * board_info_temperature_power configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_temperature_power altera_avalon_pio
#define BOARD_INFO_TEMPERATURE_POWER_BASE 0x90080
#define BOARD_INFO_TEMPERATURE_POWER_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_TEMPERATURE_POWER_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_TEMPERATURE_POWER_CAPTURE 0
#define BOARD_INFO_TEMPERATURE_POWER_DATA_WIDTH 16
#define BOARD_INFO_TEMPERATURE_POWER_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_TEMPERATURE_POWER_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_TEMPERATURE_POWER_EDGE_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_POWER_FREQ 50000000
#define BOARD_INFO_TEMPERATURE_POWER_HAS_IN 1
#define BOARD_INFO_TEMPERATURE_POWER_HAS_OUT 0
#define BOARD_INFO_TEMPERATURE_POWER_HAS_TRI 0
#define BOARD_INFO_TEMPERATURE_POWER_IRQ -1
#define BOARD_INFO_TEMPERATURE_POWER_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_TEMPERATURE_POWER_IRQ_TYPE "NONE"
#define BOARD_INFO_TEMPERATURE_POWER_NAME "/dev/board_info_temperature_power"
#define BOARD_INFO_TEMPERATURE_POWER_RESET_VALUE 0
#define BOARD_INFO_TEMPERATURE_POWER_SPAN 16
#define BOARD_INFO_TEMPERATURE_POWER_TYPE "altera_avalon_pio"


/*
 * board_info_vcc1p2_current configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_vcc1p2_current altera_avalon_pio
#define BOARD_INFO_VCC1P2_CURRENT_BASE 0x900e0
#define BOARD_INFO_VCC1P2_CURRENT_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_VCC1P2_CURRENT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_VCC1P2_CURRENT_CAPTURE 0
#define BOARD_INFO_VCC1P2_CURRENT_DATA_WIDTH 16
#define BOARD_INFO_VCC1P2_CURRENT_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_VCC1P2_CURRENT_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_VCC1P2_CURRENT_EDGE_TYPE "NONE"
#define BOARD_INFO_VCC1P2_CURRENT_FREQ 50000000
#define BOARD_INFO_VCC1P2_CURRENT_HAS_IN 1
#define BOARD_INFO_VCC1P2_CURRENT_HAS_OUT 0
#define BOARD_INFO_VCC1P2_CURRENT_HAS_TRI 0
#define BOARD_INFO_VCC1P2_CURRENT_IRQ -1
#define BOARD_INFO_VCC1P2_CURRENT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_VCC1P2_CURRENT_IRQ_TYPE "NONE"
#define BOARD_INFO_VCC1P2_CURRENT_NAME "/dev/board_info_vcc1p2_current"
#define BOARD_INFO_VCC1P2_CURRENT_RESET_VALUE 0
#define BOARD_INFO_VCC1P2_CURRENT_SPAN 16
#define BOARD_INFO_VCC1P2_CURRENT_TYPE "altera_avalon_pio"


/*
 * board_info_vcc1p2_voltage configuration
 *
 */

#define ALT_MODULE_CLASS_board_info_vcc1p2_voltage altera_avalon_pio
#define BOARD_INFO_VCC1P2_VOLTAGE_BASE 0x900f0
#define BOARD_INFO_VCC1P2_VOLTAGE_BIT_CLEARING_EDGE_REGISTER 0
#define BOARD_INFO_VCC1P2_VOLTAGE_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BOARD_INFO_VCC1P2_VOLTAGE_CAPTURE 0
#define BOARD_INFO_VCC1P2_VOLTAGE_DATA_WIDTH 16
#define BOARD_INFO_VCC1P2_VOLTAGE_DO_TEST_BENCH_WIRING 0
#define BOARD_INFO_VCC1P2_VOLTAGE_DRIVEN_SIM_VALUE 0
#define BOARD_INFO_VCC1P2_VOLTAGE_EDGE_TYPE "NONE"
#define BOARD_INFO_VCC1P2_VOLTAGE_FREQ 50000000
#define BOARD_INFO_VCC1P2_VOLTAGE_HAS_IN 1
#define BOARD_INFO_VCC1P2_VOLTAGE_HAS_OUT 0
#define BOARD_INFO_VCC1P2_VOLTAGE_HAS_TRI 0
#define BOARD_INFO_VCC1P2_VOLTAGE_IRQ -1
#define BOARD_INFO_VCC1P2_VOLTAGE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define BOARD_INFO_VCC1P2_VOLTAGE_IRQ_TYPE "NONE"
#define BOARD_INFO_VCC1P2_VOLTAGE_NAME "/dev/board_info_vcc1p2_voltage"
#define BOARD_INFO_VCC1P2_VOLTAGE_RESET_VALUE 0
#define BOARD_INFO_VCC1P2_VOLTAGE_SPAN 16
#define BOARD_INFO_VCC1P2_VOLTAGE_TYPE "altera_avalon_pio"


/*
 * hal2 configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK INTEL_NIOSV_G
#define ALT_TIMESTAMP_CLK INTEL_NIOSV_G
#define INTEL_FPGA_DFL_START_ADDRESS 0xffffffffffffffff
#define INTEL_FPGA_USE_DFL_WALKER 0


/*
 * intel_niosv_g_hal_driver configuration
 *
 */

#define NIOSV_INTERNAL_TIMER_TICKS_PER_SECOND 1000


/*
 * intel_onchip_memory configuration
 *
 */

#define ALT_MODULE_CLASS_intel_onchip_memory intel_onchip_memory
#define INTEL_ONCHIP_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define INTEL_ONCHIP_MEMORY_BASE 0x0
#define INTEL_ONCHIP_MEMORY_CONTENTS_INFO ""
#define INTEL_ONCHIP_MEMORY_DUAL_PORT 0
#define INTEL_ONCHIP_MEMORY_GUI_RAM_BLOCK_TYPE "AUTO"
#define INTEL_ONCHIP_MEMORY_INIT_CONTENTS_FILE "system_intel_onchip_memory_0_intel_onchip_memory"
#define INTEL_ONCHIP_MEMORY_INIT_MEM_CONTENT 1
#define INTEL_ONCHIP_MEMORY_INSTANCE_ID "NONE"
#define INTEL_ONCHIP_MEMORY_IRQ -1
#define INTEL_ONCHIP_MEMORY_IRQ_INTERRUPT_CONTROLLER_ID -1
#define INTEL_ONCHIP_MEMORY_NAME "/dev/intel_onchip_memory"
#define INTEL_ONCHIP_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
#define INTEL_ONCHIP_MEMORY_RAM_BLOCK_TYPE "AUTO"
#define INTEL_ONCHIP_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
#define INTEL_ONCHIP_MEMORY_SINGLE_CLOCK_OP 0
#define INTEL_ONCHIP_MEMORY_SIZE_MULTIPLE 1
#define INTEL_ONCHIP_MEMORY_SIZE_VALUE 524288
#define INTEL_ONCHIP_MEMORY_SPAN 524288
#define INTEL_ONCHIP_MEMORY_TYPE "intel_onchip_memory"
#define INTEL_ONCHIP_MEMORY_WRITABLE 1


/*
 * jtag_uart configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x90118
#define JTAG_UART_IRQ 1
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_SPAN 8
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8


/*
 * sysid_qsys configuration
 *
 */

#define ALT_MODULE_CLASS_sysid_qsys altera_avalon_sysid_qsys
#define SYSID_QSYS_BASE 0x90110
#define SYSID_QSYS_ID 0
#define SYSID_QSYS_IRQ -1
#define SYSID_QSYS_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSID_QSYS_NAME "/dev/sysid_qsys"
#define SYSID_QSYS_SPAN 8
#define SYSID_QSYS_TIMESTAMP 0
#define SYSID_QSYS_TYPE "altera_avalon_sysid_qsys"


/*
 * timer configuration
 *
 */

#define ALT_MODULE_CLASS_timer altera_avalon_timer
#define TIMER_ALWAYS_RUN 0
#define TIMER_BASE 0x90040
#define TIMER_COUNTER_SIZE 32
#define TIMER_FIXED_PERIOD 0
#define TIMER_FREQ 50000000
#define TIMER_IRQ 0
#define TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_LOAD_VALUE 49999
#define TIMER_MULT 0.001
#define TIMER_NAME "/dev/timer"
#define TIMER_PERIOD 1
#define TIMER_PERIOD_UNITS "ms"
#define TIMER_RESET_OUTPUT 0
#define TIMER_SNAPSHOT 1
#define TIMER_SPAN 32
#define TIMER_TICKS_PER_SEC 1000
#define TIMER_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_TIMER_DEVICE_TYPE 1
#define TIMER_TYPE "altera_avalon_timer"

#endif /* __SYSTEM_H_ */
