// agilex_hps.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module agilex_hps (
		output wire         h2f_reset_reset,                        //                h2f_reset.reset,         Active high reset from the HPS Reset Manager.
		input  wire         hps2fpga_axi_clock_clk,                 //       hps2fpga_axi_clock.clk,           Clock from a single source in the FPGA.
		input  wire         hps2fpga_axi_reset_reset,               //       hps2fpga_axi_reset.reset,         Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   hps2fpga_awid,                          //                 hps2fpga.awid,          Identification tag for a write transaction.
		output wire [37:0]  hps2fpga_awaddr,                        //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [7:0]   hps2fpga_awlen,                         //                         .awlen,         The exact number of data transfers in a write transaction.
		output wire [2:0]   hps2fpga_awsize,                        //                         .awsize,        The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   hps2fpga_awburst,                       //                         .awburst,       Indicates how address changes between each transfer in a write transaction.
		output wire         hps2fpga_awlock,                        //                         .awlock,        Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   hps2fpga_awcache,                       //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_awprot,                        //                         .awprot,        Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         hps2fpga_awvalid,                       //                         .awvalid,       Indicates that the write address channel signals are valid.
		input  wire         hps2fpga_awready,                       //                         .awready,       Indicates that a transfer on the write address channel can be accepted.
		output wire [127:0] hps2fpga_wdata,                         //                         .wdata,         Write data.
		output wire [15:0]  hps2fpga_wstrb,                         //                         .wstrb,         Write strobes, indicate which byte lanes hold valid data.
		output wire         hps2fpga_wlast,                         //                         .wlast,         User-defined extension for the write data channel.
		output wire         hps2fpga_wvalid,                        //                         .wvalid,        Indicates that the write data channel signals are valid.
		input  wire         hps2fpga_wready,                        //                         .wready,        Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   hps2fpga_bid,                           //                         .bid,           Transaction identifier for the write response.
		input  wire [1:0]   hps2fpga_bresp,                         //                         .bresp,         Write response, indicates the status of a write transaction.
		input  wire         hps2fpga_bvalid,                        //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire         hps2fpga_bready,                        //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   hps2fpga_arid,                          //                         .arid,          Transaction identifier for the read transaction.
		output wire [37:0]  hps2fpga_araddr,                        //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [7:0]   hps2fpga_arlen,                         //                         .arlen,         The exact number of data transfers in a read transaction.
		output wire [2:0]   hps2fpga_arsize,                        //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   hps2fpga_arburst,                       //                         .arburst,       Indicates how address changes between each transfer in a read transaction.
		output wire         hps2fpga_arlock,                        //                         .arlock,        Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   hps2fpga_arcache,                       //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_arprot,                        //                         .arprot,        Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         hps2fpga_arvalid,                       //                         .arvalid,       Indicates that the read address channel signals are valid.
		input  wire         hps2fpga_arready,                       //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   hps2fpga_rid,                           //                         .rid,           Identification tag for read data and response.
		input  wire [127:0] hps2fpga_rdata,                         //                         .rdata,         Read data.
		input  wire [1:0]   hps2fpga_rresp,                         //                         .rresp,         Read response, indicates the status of a read transfer.
		input  wire         hps2fpga_rlast,                         //                         .rlast,         Indicates whether this is the last data transfer in a read transaction.
		input  wire         hps2fpga_rvalid,                        //                         .rvalid,        Indicates that the read data channel signals are valid.
		output wire         hps2fpga_rready,                        //                         .rready,        Indicates that a transfer on the read data channel can be accepted.
		input  wire         lwhps2fpga_axi_clock_clk,               //     lwhps2fpga_axi_clock.clk,           clock from a single source in the FPGA.
		input  wire         lwhps2fpga_axi_reset_reset,             //     lwhps2fpga_axi_reset.reset,         Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   lwhps2fpga_awid,                        //               lwhps2fpga.awid,          Identification tag for a write transaction.
		output wire [28:0]  lwhps2fpga_awaddr,                      //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [7:0]   lwhps2fpga_awlen,                       //                         .awlen,         The exact number of data transfers in a write transaction.
		output wire [2:0]   lwhps2fpga_awsize,                      //                         .awsize,        The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   lwhps2fpga_awburst,                     //                         .awburst,       Indicates how address changes between each transfer in a write transaction.
		output wire         lwhps2fpga_awlock,                      //                         .awlock,        Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   lwhps2fpga_awcache,                     //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_awprot,                      //                         .awprot,        Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_awvalid,                     //                         .awvalid,       Indicates that the write address channel signals are valid.
		input  wire         lwhps2fpga_awready,                     //                         .awready,       Indicates that a transfer on the write address channel can be accepted.
		output wire [31:0]  lwhps2fpga_wdata,                       //                         .wdata,         Write data.
		output wire [3:0]   lwhps2fpga_wstrb,                       //                         .wstrb,         Write strobes, indicate which byte lanes hold valid data.
		output wire         lwhps2fpga_wlast,                       //                         .wlast,         User-defined extension for the write data channel.
		output wire         lwhps2fpga_wvalid,                      //                         .wvalid,        Indicates that the write data channel signals are valid.
		input  wire         lwhps2fpga_wready,                      //                         .wready,        Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   lwhps2fpga_bid,                         //                         .bid,           Transaction identifier for the write response.
		input  wire [1:0]   lwhps2fpga_bresp,                       //                         .bresp,         Write response, indicates the status of a write transaction.
		input  wire         lwhps2fpga_bvalid,                      //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire         lwhps2fpga_bready,                      //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   lwhps2fpga_arid,                        //                         .arid,          Transaction identifier for the read transaction.
		output wire [28:0]  lwhps2fpga_araddr,                      //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [7:0]   lwhps2fpga_arlen,                       //                         .arlen,         The exact number of data transfers in a read transaction.
		output wire [2:0]   lwhps2fpga_arsize,                      //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   lwhps2fpga_arburst,                     //                         .arburst,       Indicates how address changes between each transfer in a read transaction.
		output wire         lwhps2fpga_arlock,                      //                         .arlock,        Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   lwhps2fpga_arcache,                     //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_arprot,                      //                         .arprot,        Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_arvalid,                     //                         .arvalid,       Indicates that the read address channel signals are valid.
		input  wire         lwhps2fpga_arready,                     //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   lwhps2fpga_rid,                         //                         .rid,           Identification tag for read data and response.
		input  wire [31:0]  lwhps2fpga_rdata,                       //                         .rdata,         Read data.
		input  wire [1:0]   lwhps2fpga_rresp,                       //                         .rresp,         Read response, indicates the status of a read transfer.
		input  wire         lwhps2fpga_rlast,                       //                         .rlast,         Indicates whether this is the last data transfer in a read transaction.
		input  wire         lwhps2fpga_rvalid,                      //                         .rvalid,        Indicates that the read data channel signals are valid.
		output wire         lwhps2fpga_rready,                      //                         .rready,        Indicates that a transfer on the read data channel can be accepted.
		output wire         emac2_app_rst_reset_n,                  //            emac2_app_rst.reset_n,       EMAC2 application clock reset output.
		output wire         h2f_warm_reset_handshake_reset_req,     // h2f_warm_reset_handshake.reset_req,     HPS warm reset request. Identical to watchdog reset except this is asserted by SDM.
		input  wire         h2f_warm_reset_handshake_reset_ack,     //                         .reset_ack,     HPS warm reset acknowledge response to SDM. Should be asserted when all HPS soft logic is successfully in reset.
		input  wire         hps_io_hps_osc_clk,                     //                   hps_io.hps_osc_clk,   HPS input clock pin for EOSC reference clock.
		inout  wire         hps_io_sdmmc_data0,                     //                         .sdmmc_data0,   SDMMC data[0].
		inout  wire         hps_io_sdmmc_data1,                     //                         .sdmmc_data1,   SDMMC data[1].
		output wire         hps_io_sdmmc_cclk,                      //                         .sdmmc_cclk,    SDMMC output clock.
		inout  wire         hps_io_sdmmc_data2,                     //                         .sdmmc_data2,   SDMMC data[2].
		inout  wire         hps_io_sdmmc_data3,                     //                         .sdmmc_data3,   SDMMC data[3].
		inout  wire         hps_io_sdmmc_cmd,                       //                         .sdmmc_cmd,     SDMMC command.
		input  wire         hps_io_usb1_clk,                        //                         .usb1_clk,      ULPI PHY clock input.
		output wire         hps_io_usb1_stp,                        //                         .usb1_stp,      ULPI stop output control.
		input  wire         hps_io_usb1_dir,                        //                         .usb1_dir,      Data bus control.
		inout  wire         hps_io_usb1_data0,                      //                         .usb1_data0,    USB data[0].
		inout  wire         hps_io_usb1_data1,                      //                         .usb1_data1,    USB data[1].
		input  wire         hps_io_usb1_nxt,                        //                         .usb1_nxt,      ULPI next data control.
		inout  wire         hps_io_usb1_data2,                      //                         .usb1_data2,    USB data[2].
		inout  wire         hps_io_usb1_data3,                      //                         .usb1_data3,    USB data[3].
		inout  wire         hps_io_usb1_data4,                      //                         .usb1_data4,    USB data[4].
		inout  wire         hps_io_usb1_data5,                      //                         .usb1_data5,    USB data[5].
		inout  wire         hps_io_usb1_data6,                      //                         .usb1_data6,    USB data[6].
		inout  wire         hps_io_usb1_data7,                      //                         .usb1_data7,    USB data[7].
		output wire         hps_io_emac2_tx_clk,                    //                         .emac2_tx_clk,  EMAC2 transmit clock.
		output wire         hps_io_emac2_tx_ctl,                    //                         .emac2_tx_ctl,  EMAC2 transmit data enable.
		input  wire         hps_io_emac2_rx_clk,                    //                         .emac2_rx_clk,  EMAC2 receive clock.
		input  wire         hps_io_emac2_rx_ctl,                    //                         .emac2_rx_ctl,  EMAC2 receive data enable.
		output wire         hps_io_emac2_txd0,                      //                         .emac2_txd0,    EMAC2 transmit data[0].
		output wire         hps_io_emac2_txd1,                      //                         .emac2_txd1,    EMAC2 transmit data[1].
		input  wire         hps_io_emac2_rxd0,                      //                         .emac2_rxd0,    EMAC2 receive data[0].
		input  wire         hps_io_emac2_rxd1,                      //                         .emac2_rxd1,    EMAC2 receive data[1].
		output wire         hps_io_emac2_txd2,                      //                         .emac2_txd2,    EMAC2 transmit data[2].
		output wire         hps_io_emac2_txd3,                      //                         .emac2_txd3,    EMAC2 transmit data[3].
		input  wire         hps_io_emac2_rxd2,                      //                         .emac2_rxd2,    EMAC2 receive data[2].
		input  wire         hps_io_emac2_rxd3,                      //                         .emac2_rxd3,    EMAC2 receive data[3].
		inout  wire         hps_io_mdio2_mdio,                      //                         .mdio2_mdio,    EMAC2 MDIO data.
		output wire         hps_io_mdio2_mdc,                       //                         .mdio2_mdc,     EMAC2 MDIO clock.
		output wire         hps_io_uart0_tx,                        //                         .uart0_tx,      UART0 transmit data.
		input  wire         hps_io_uart0_rx,                        //                         .uart0_rx,      UART0 receive data.
		inout  wire         hps_io_i2c0_sda,                        //                         .i2c0_sda,      I2C0 serial data.
		inout  wire         hps_io_i2c0_scl,                        //                         .i2c0_scl,      I2C0 clock.
		inout  wire         hps_io_gpio0,                           //                         .gpio0,         GPIO0 IO0
		inout  wire         hps_io_gpio1,                           //                         .gpio1,         GPIO0 IO1
		inout  wire         hps_io_gpio8,                           //                         .gpio8,         GPIO0 IO8
		inout  wire         hps_io_gpio9,                           //                         .gpio9,         GPIO0 IO9
		inout  wire         hps_io_gpio10,                          //                         .gpio10,        GPIO0 IO10
		inout  wire         hps_io_gpio11,                          //                         .gpio11,        GPIO0 IO11
		inout  wire         hps_io_gpio28,                          //                         .gpio28,        GPIO1 IO4
		input  wire         usb31_io_vbus_det,                      //                 usb31_io.vbus_det,      VBUS detect.
		input  wire         usb31_io_flt_bar,                       //                         .flt_bar,       Connected to overcurrent input on USB3.1 controller.
		output wire [1:0]   usb31_io_usb_ctrl,                      //                         .usb_ctrl,      USB3.1 control output to connect to UMC.
		input  wire         usb31_io_usb31_id,                      //                         .usb31_id,      USB ID.
		input  wire [62:0]  fpga2hps_interrupt_irq,                 //       fpga2hps_interrupt.irq,           FPGA-to-HPS interrupts.
		input  wire         usb31_phy_pma_cpu_clk_clk,              //    usb31_phy_pma_cpu_clk.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_refclk_p_clk,                 //       usb31_phy_refclk_p.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_refclk_n_clk,                 //       usb31_phy_refclk_n.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_rx_serial_n_i_rx_serial_n,    //    usb31_phy_rx_serial_n.i_rx_serial_n, Differential pair for RX serial data port. Historically was hidden; however now used in pam4 signal simulation model, hence needs to be connected by user.
		input  wire         usb31_phy_rx_serial_p_i_rx_serial_p,    //    usb31_phy_rx_serial_p.i_rx_serial_p, TX serial data port.
		output wire         usb31_phy_tx_serial_n_o_tx_serial_n,    //    usb31_phy_tx_serial_n.o_tx_serial_n, Differential pair for TX serial data port. Historically was hidden; however now used in pam4 signal simulation model, hence needs to be connected by user.
		output wire         usb31_phy_tx_serial_p_o_tx_serial_p,    //    usb31_phy_tx_serial_p.o_tx_serial_p, TX serial data port.
		input  wire         usb31_phy_reconfig_rst_reset,           //   usb31_phy_reconfig_rst.reset,         reconfig_reset
		input  wire         usb31_phy_reconfig_clk_clk,             //   usb31_phy_reconfig_clk.clk,           reconfig_clk
		input  wire [20:0]  usb31_phy_reconfig_slave_address,       // usb31_phy_reconfig_slave.address,       Address for Ethernet CSRs
		input  wire [3:0]   usb31_phy_reconfig_slave_byteenable,    //                         .byteenable,    Byte enable for read/write to Ethernet CSRs
		output wire         usb31_phy_reconfig_slave_readdatavalid, //                         .readdatavalid, Read data from Ethernet CSRs is valid
		input  wire         usb31_phy_reconfig_slave_read,          //                         .read,          Read command for Ethernet CSRs
		input  wire         usb31_phy_reconfig_slave_write,         //                         .write,         Write command for Ethernet CSRs
		output wire [31:0]  usb31_phy_reconfig_slave_readdata,      //                         .readdata,      Read data from reads to Ethernet CSRs
		input  wire [31:0]  usb31_phy_reconfig_slave_writedata,     //                         .writedata,     Data for writes to Ethernet CSRs
		output wire         usb31_phy_reconfig_slave_waitrequest,   //                         .waitrequest,   AVMM stall signal for operation on Ethernet CSRs
		input  wire         f2sdram_axi_clock_clk,                  //        f2sdram_axi_clock.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         f2sdram_axi_reset_reset,                //        f2sdram_axi_reset.reset,         Active high reset for f2sdram soft logic on FPGA. The actual bridge reset is driven by internal HPS Reset Manager.
		input  wire [31:0]  f2sdram_araddr,                         //                  f2sdram.araddr,        Address of the first transfer in a read transaction.
		input  wire [1:0]   f2sdram_arburst,                        //                         .arburst,       Burst type indicating how address changes between each transfer in a read transaction.
		input  wire [3:0]   f2sdram_arcache,                        //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_arid,                           //                         .arid,          Identification tag for a read transaction.
		input  wire [7:0]   f2sdram_arlen,                          //                         .arlen,         The exact number of data transfers in a read transaction.
		input  wire         f2sdram_arlock,                         //                         .arlock,        Provides info on atomic characteristics of a read transaction.
		input  wire [2:0]   f2sdram_arprot,                         //                         .arprot,        Protection attributes of a read transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_arqos,                          //                         .arqos,         Quality service identifier for a read transaction.
		output wire         f2sdram_arready,                        //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [2:0]   f2sdram_arsize,                         //                         .arsize,        The number of bytes in each data transfer of a read transaction.
		input  wire         f2sdram_arvalid,                        //                         .arvalid,       Indicates the read address channel signals are valid.
		input  wire [31:0]  f2sdram_awaddr,                         //                         .awaddr,        The address of the first transfer in a write transaction.
		input  wire [1:0]   f2sdram_awburst,                        //                         .awburst,       Burst type indicating how address changes between each transfer in a write transaction.
		input  wire [3:0]   f2sdram_awcache,                        //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_awid,                           //                         .awid,          Identification tag for a write transaction.
		input  wire [7:0]   f2sdram_awlen,                          //                         .awlen,         The exact number of data transfers in a write transaction.
		input  wire         f2sdram_awlock,                         //                         .awlock,        Provides info on atomic characteristics of a write transaction.
		input  wire [2:0]   f2sdram_awprot,                         //                         .awprot,        Protection attributes of a write transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_awqos,                          //                         .awqos,         Quality of servide identifier for a write transaction.
		output wire         f2sdram_awready,                        //                         .awready,       Indicates that a transfer on the write channel address can be accepted.
		input  wire [2:0]   f2sdram_awsize,                         //                         .awsize,        The number of bytes in each data transfer of a write transaction.
		input  wire         f2sdram_awvalid,                        //                         .awvalid,       Indicates the write address channel signals are valid.
		output wire [4:0]   f2sdram_bid,                            //                         .bid,           Identification tag for a write response.
		input  wire         f2sdram_bready,                         //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [1:0]   f2sdram_bresp,                          //                         .bresp,         Write response indicating the status of a write transaction.
		output wire         f2sdram_bvalid,                         //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire [255:0] f2sdram_rdata,                          //                         .rdata,         Read data.
		output wire [4:0]   f2sdram_rid,                            //                         .rid,           Identification tag for read data and response.
		output wire         f2sdram_rlast,                          //                         .rlast,         Indicates the last data transfer in a read transaction.
		input  wire         f2sdram_rready,                         //                         .rready,        Indicates a transfer on the read data channel can be accepted.
		output wire [1:0]   f2sdram_rresp,                          //                         .rresp,         Read response indicating the status of a read transfer.
		output wire         f2sdram_rvalid,                         //                         .rvalid,        Indicates the read channel data channel signals are valid.
		input  wire [255:0] f2sdram_wdata,                          //                         .wdata,         Write data.
		input  wire         f2sdram_wlast,                          //                         .wlast,         Indicates the last data transfer in a write transaction.
		output wire         f2sdram_wready,                         //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		input  wire [31:0]  f2sdram_wstrb,                          //                         .wstrb,         Write strobes indicating which bye lanes hold valid data.
		input  wire         f2sdram_wvalid,                         //                         .wvalid,        Indicates the write channel data signals are valid.
		input  wire [7:0]   f2sdram_aruser,                         //                         .aruser,        Extension for the read address channel.
		input  wire [7:0]   f2sdram_awuser,                         //                         .awuser,        Extension for the write address channel.
		input  wire [7:0]   f2sdram_wuser,                          //                         .wuser,         Extension for the write data channel.
		output wire [7:0]   f2sdram_buser,                          //                         .buser,         Extension for the write response channel.
		input  wire [3:0]   f2sdram_arregion,                       //                         .arregion,      Region indicator for a read transaction.
		output wire [7:0]   f2sdram_ruser,                          //                         .ruser,         Extension for the read data channel.
		input  wire [3:0]   f2sdram_awregion,                       //                         .awregion,      Region indicator for a write transaction.
		input  wire         io96b0_csr_axi_clk_clk,                 //       io96b0_csr_axi_clk.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_csr_axi_rst_reset_n,             //       io96b0_csr_axi_rst.reset_n,       Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_csr_axi_arready,                 //           io96b0_csr_axi.arready,       Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_csr_axi_awready,                 //                         .awready,       Indicates a transfer on the write address channel can be accepted.
		input  wire [1:0]   io96b0_csr_axi_bresp,                   //                         .bresp,         Indicates status of write transaction.
		input  wire         io96b0_csr_axi_bvalid,                  //                         .bvalid,        Indicates write response channel signals are valid.
		input  wire [31:0]  io96b0_csr_axi_rdata,                   //                         .rdata,         Read data.
		input  wire [1:0]   io96b0_csr_axi_rresp,                   //                         .rresp,         Indicates status of read transaction.
		input  wire         io96b0_csr_axi_rvalid,                  //                         .rvalid,        Indicates read data channel signals are valid.
		input  wire         io96b0_csr_axi_wready,                  //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		output wire [31:0]  io96b0_csr_axi_araddr,                  //                         .araddr,        The address of the first transfer in a read transaction.
		output wire         io96b0_csr_axi_arvalid,                 //                         .arvalid,       Indicates read address channel signals are valid.
		output wire [31:0]  io96b0_csr_axi_awaddr,                  //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire         io96b0_csr_axi_awvalid,                 //                         .awvalid,       Indicates write address channel signals are valid.
		output wire         io96b0_csr_axi_bready,                  //                         .bready,        Indicates a transfer on the write response channel can be accepted.
		output wire         io96b0_csr_axi_rready,                  //                         .rready,        Indicates a transfer on the read data channel can be accepted.
		output wire [31:0]  io96b0_csr_axi_wdata,                   //                         .wdata,         Write data.
		output wire [3:0]   io96b0_csr_axi_wstrb,                   //                         .wstrb,         Write strobes indicating which bye lanes hold valid data.
		output wire         io96b0_csr_axi_wvalid,                  //                         .wvalid,        Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_csr_axi_arprot,                  //                         .arprot,        Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_csr_axi_awprot,                  //                         .awprot,        Placegolder AWPROT. Protection attributes not supported for this bridge.
		input  wire         io96b0_ch0_axi_clk_clk,                 //       io96b0_ch0_axi_clk.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_ch0_axi_rst_reset_n,             //       io96b0_ch0_axi_rst.reset_n,       Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_ch0_axi_arready,                 //           io96b0_ch0_axi.arready,       Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_ch0_axi_awready,                 //                         .awready,       Indicates a transfer on the write address channel can be accepted.
		input  wire [6:0]   io96b0_ch0_axi_bid,                     //                         .bid,           Identification tag for a write response.
		input  wire [1:0]   io96b0_ch0_axi_bresp,                   //                         .bresp,         Indicates the status of a write transaction.
		input  wire         io96b0_ch0_axi_bvalid,                  //                         .bvalid,        Indicates write response channel signals are valid.
		input  wire [255:0] io96b0_ch0_axi_rdata,                   //                         .rdata,         Read data.
		input  wire [6:0]   io96b0_ch0_axi_rid,                     //                         .rid,           Identification tag for read data and response.
		input  wire         io96b0_ch0_axi_rlast,                   //                         .rlast,         Indicates the last data transfer in a read transaction.
		input  wire [1:0]   io96b0_ch0_axi_rresp,                   //                         .rresp,         Indicates the status of a read transfer.
		input  wire [31:0]  io96b0_ch0_axi_ruser,                   //                         .ruser,         Extension of read data channel.
		input  wire         io96b0_ch0_axi_rvalid,                  //                         .rvalid,        Indicates read data channel signals are valid.
		input  wire         io96b0_ch0_axi_wready,                  //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		output wire [43:0]  io96b0_ch0_axi_araddr,                  //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [1:0]   io96b0_ch0_axi_arburst,                 //                         .arburst,       Burst type indicating how address changes between each transfer in a read transaction.
		output wire [6:0]   io96b0_ch0_axi_arid,                    //                         .arid,          Identification tag for a read transaction.
		output wire [7:0]   io96b0_ch0_axi_arlen,                   //                         .arlen,         Exact number of data transfers in a read transaction.
		output wire         io96b0_ch0_axi_arlock,                  //                         .arlock,        Provides info on atomic characteristics of a read transaction.
		output wire [3:0]   io96b0_ch0_axi_arqos,                   //                         .arqos,         Quality of service identifier for a read transaction.
		output wire [2:0]   io96b0_ch0_axi_arsize,                  //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [13:0]  io96b0_ch0_axi_aruser,                  //                         .aruser,        Extension of read address channel.
		output wire         io96b0_ch0_axi_arvalid,                 //                         .arvalid,       Indicates read address channel signals are valid.
		output wire [43:0]  io96b0_ch0_axi_awaddr,                  //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [1:0]   io96b0_ch0_axi_awburst,                 //                         .awburst,       Burst type indicating how address changes between each transfer in a write transaction.
		output wire [6:0]   io96b0_ch0_axi_awid,                    //                         .awid,          Identification tag for a write transaction.
		output wire [7:0]   io96b0_ch0_axi_awlen,                   //                         .awlen,         Exact number of data transfers in a write transaction.
		output wire         io96b0_ch0_axi_awlock,                  //                         .awlock,        Provides info on atomic characteristics of a write transaction.
		output wire [3:0]   io96b0_ch0_axi_awqos,                   //                         .awqos,         Quality of service identifier for a write transaction.
		output wire [2:0]   io96b0_ch0_axi_awsize,                  //                         .awsize,        Number of bytes in each data transfer in a write transaction.
		output wire [13:0]  io96b0_ch0_axi_awuser,                  //                         .awuser,        Extension of write address channel.
		output wire         io96b0_ch0_axi_awvalid,                 //                         .awvalid,       Indicates write address channel signals are valid.
		output wire         io96b0_ch0_axi_bready,                  //                         .bready,        Indicates a transfer on write response channel can be accepted.
		output wire         io96b0_ch0_axi_rready,                  //                         .rready,        Indicates a transfer on read data channel can be accepted.
		output wire [255:0] io96b0_ch0_axi_wdata,                   //                         .wdata,         Write data.
		output wire         io96b0_ch0_axi_wlast,                   //                         .wlast,         Indicates the last data transfer in a write transaction.
		output wire [31:0]  io96b0_ch0_axi_wstrb,                   //                         .wstrb,         Write strobes indicating which byte lanes hold valid data.
		output wire [31:0]  io96b0_ch0_axi_wuser,                   //                         .wuser,         Extension of the write data channel.
		output wire         io96b0_ch0_axi_wvalid,                  //                         .wvalid,        Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_ch0_axi_arprot,                  //                         .arprot,        Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_ch0_axi_awprot                   //                         .awprot,        Placeholder AWPROT. Protection attributes not supported for this bridge.
	);

	agilex_hps_intel_agilex_5_soc_300_7k7syei intel_agilex_5_soc_inst (
		.h2f_reset_reset                        (h2f_reset_reset),                        //  output,    width = 1,                h2f_reset.reset
		.hps2fpga_axi_clock_clk                 (hps2fpga_axi_clock_clk),                 //   input,    width = 1,       hps2fpga_axi_clock.clk
		.hps2fpga_axi_reset_reset               (hps2fpga_axi_reset_reset),               //   input,    width = 1,       hps2fpga_axi_reset.reset
		.hps2fpga_awid                          (hps2fpga_awid),                          //  output,    width = 4,                 hps2fpga.awid
		.hps2fpga_awaddr                        (hps2fpga_awaddr),                        //  output,   width = 38,                         .awaddr
		.hps2fpga_awlen                         (hps2fpga_awlen),                         //  output,    width = 8,                         .awlen
		.hps2fpga_awsize                        (hps2fpga_awsize),                        //  output,    width = 3,                         .awsize
		.hps2fpga_awburst                       (hps2fpga_awburst),                       //  output,    width = 2,                         .awburst
		.hps2fpga_awlock                        (hps2fpga_awlock),                        //  output,    width = 1,                         .awlock
		.hps2fpga_awcache                       (hps2fpga_awcache),                       //  output,    width = 4,                         .awcache
		.hps2fpga_awprot                        (hps2fpga_awprot),                        //  output,    width = 3,                         .awprot
		.hps2fpga_awvalid                       (hps2fpga_awvalid),                       //  output,    width = 1,                         .awvalid
		.hps2fpga_awready                       (hps2fpga_awready),                       //   input,    width = 1,                         .awready
		.hps2fpga_wdata                         (hps2fpga_wdata),                         //  output,  width = 128,                         .wdata
		.hps2fpga_wstrb                         (hps2fpga_wstrb),                         //  output,   width = 16,                         .wstrb
		.hps2fpga_wlast                         (hps2fpga_wlast),                         //  output,    width = 1,                         .wlast
		.hps2fpga_wvalid                        (hps2fpga_wvalid),                        //  output,    width = 1,                         .wvalid
		.hps2fpga_wready                        (hps2fpga_wready),                        //   input,    width = 1,                         .wready
		.hps2fpga_bid                           (hps2fpga_bid),                           //   input,    width = 4,                         .bid
		.hps2fpga_bresp                         (hps2fpga_bresp),                         //   input,    width = 2,                         .bresp
		.hps2fpga_bvalid                        (hps2fpga_bvalid),                        //   input,    width = 1,                         .bvalid
		.hps2fpga_bready                        (hps2fpga_bready),                        //  output,    width = 1,                         .bready
		.hps2fpga_arid                          (hps2fpga_arid),                          //  output,    width = 4,                         .arid
		.hps2fpga_araddr                        (hps2fpga_araddr),                        //  output,   width = 38,                         .araddr
		.hps2fpga_arlen                         (hps2fpga_arlen),                         //  output,    width = 8,                         .arlen
		.hps2fpga_arsize                        (hps2fpga_arsize),                        //  output,    width = 3,                         .arsize
		.hps2fpga_arburst                       (hps2fpga_arburst),                       //  output,    width = 2,                         .arburst
		.hps2fpga_arlock                        (hps2fpga_arlock),                        //  output,    width = 1,                         .arlock
		.hps2fpga_arcache                       (hps2fpga_arcache),                       //  output,    width = 4,                         .arcache
		.hps2fpga_arprot                        (hps2fpga_arprot),                        //  output,    width = 3,                         .arprot
		.hps2fpga_arvalid                       (hps2fpga_arvalid),                       //  output,    width = 1,                         .arvalid
		.hps2fpga_arready                       (hps2fpga_arready),                       //   input,    width = 1,                         .arready
		.hps2fpga_rid                           (hps2fpga_rid),                           //   input,    width = 4,                         .rid
		.hps2fpga_rdata                         (hps2fpga_rdata),                         //   input,  width = 128,                         .rdata
		.hps2fpga_rresp                         (hps2fpga_rresp),                         //   input,    width = 2,                         .rresp
		.hps2fpga_rlast                         (hps2fpga_rlast),                         //   input,    width = 1,                         .rlast
		.hps2fpga_rvalid                        (hps2fpga_rvalid),                        //   input,    width = 1,                         .rvalid
		.hps2fpga_rready                        (hps2fpga_rready),                        //  output,    width = 1,                         .rready
		.lwhps2fpga_axi_clock_clk               (lwhps2fpga_axi_clock_clk),               //   input,    width = 1,     lwhps2fpga_axi_clock.clk
		.lwhps2fpga_axi_reset_reset             (lwhps2fpga_axi_reset_reset),             //   input,    width = 1,     lwhps2fpga_axi_reset.reset
		.lwhps2fpga_awid                        (lwhps2fpga_awid),                        //  output,    width = 4,               lwhps2fpga.awid
		.lwhps2fpga_awaddr                      (lwhps2fpga_awaddr),                      //  output,   width = 29,                         .awaddr
		.lwhps2fpga_awlen                       (lwhps2fpga_awlen),                       //  output,    width = 8,                         .awlen
		.lwhps2fpga_awsize                      (lwhps2fpga_awsize),                      //  output,    width = 3,                         .awsize
		.lwhps2fpga_awburst                     (lwhps2fpga_awburst),                     //  output,    width = 2,                         .awburst
		.lwhps2fpga_awlock                      (lwhps2fpga_awlock),                      //  output,    width = 1,                         .awlock
		.lwhps2fpga_awcache                     (lwhps2fpga_awcache),                     //  output,    width = 4,                         .awcache
		.lwhps2fpga_awprot                      (lwhps2fpga_awprot),                      //  output,    width = 3,                         .awprot
		.lwhps2fpga_awvalid                     (lwhps2fpga_awvalid),                     //  output,    width = 1,                         .awvalid
		.lwhps2fpga_awready                     (lwhps2fpga_awready),                     //   input,    width = 1,                         .awready
		.lwhps2fpga_wdata                       (lwhps2fpga_wdata),                       //  output,   width = 32,                         .wdata
		.lwhps2fpga_wstrb                       (lwhps2fpga_wstrb),                       //  output,    width = 4,                         .wstrb
		.lwhps2fpga_wlast                       (lwhps2fpga_wlast),                       //  output,    width = 1,                         .wlast
		.lwhps2fpga_wvalid                      (lwhps2fpga_wvalid),                      //  output,    width = 1,                         .wvalid
		.lwhps2fpga_wready                      (lwhps2fpga_wready),                      //   input,    width = 1,                         .wready
		.lwhps2fpga_bid                         (lwhps2fpga_bid),                         //   input,    width = 4,                         .bid
		.lwhps2fpga_bresp                       (lwhps2fpga_bresp),                       //   input,    width = 2,                         .bresp
		.lwhps2fpga_bvalid                      (lwhps2fpga_bvalid),                      //   input,    width = 1,                         .bvalid
		.lwhps2fpga_bready                      (lwhps2fpga_bready),                      //  output,    width = 1,                         .bready
		.lwhps2fpga_arid                        (lwhps2fpga_arid),                        //  output,    width = 4,                         .arid
		.lwhps2fpga_araddr                      (lwhps2fpga_araddr),                      //  output,   width = 29,                         .araddr
		.lwhps2fpga_arlen                       (lwhps2fpga_arlen),                       //  output,    width = 8,                         .arlen
		.lwhps2fpga_arsize                      (lwhps2fpga_arsize),                      //  output,    width = 3,                         .arsize
		.lwhps2fpga_arburst                     (lwhps2fpga_arburst),                     //  output,    width = 2,                         .arburst
		.lwhps2fpga_arlock                      (lwhps2fpga_arlock),                      //  output,    width = 1,                         .arlock
		.lwhps2fpga_arcache                     (lwhps2fpga_arcache),                     //  output,    width = 4,                         .arcache
		.lwhps2fpga_arprot                      (lwhps2fpga_arprot),                      //  output,    width = 3,                         .arprot
		.lwhps2fpga_arvalid                     (lwhps2fpga_arvalid),                     //  output,    width = 1,                         .arvalid
		.lwhps2fpga_arready                     (lwhps2fpga_arready),                     //   input,    width = 1,                         .arready
		.lwhps2fpga_rid                         (lwhps2fpga_rid),                         //   input,    width = 4,                         .rid
		.lwhps2fpga_rdata                       (lwhps2fpga_rdata),                       //   input,   width = 32,                         .rdata
		.lwhps2fpga_rresp                       (lwhps2fpga_rresp),                       //   input,    width = 2,                         .rresp
		.lwhps2fpga_rlast                       (lwhps2fpga_rlast),                       //   input,    width = 1,                         .rlast
		.lwhps2fpga_rvalid                      (lwhps2fpga_rvalid),                      //   input,    width = 1,                         .rvalid
		.lwhps2fpga_rready                      (lwhps2fpga_rready),                      //  output,    width = 1,                         .rready
		.emac2_app_rst_reset_n                  (emac2_app_rst_reset_n),                  //  output,    width = 1,            emac2_app_rst.reset_n
		.h2f_warm_reset_handshake_reset_req     (h2f_warm_reset_handshake_reset_req),     //  output,    width = 1, h2f_warm_reset_handshake.reset_req
		.h2f_warm_reset_handshake_reset_ack     (h2f_warm_reset_handshake_reset_ack),     //   input,    width = 1,                         .reset_ack
		.hps_io_hps_osc_clk                     (hps_io_hps_osc_clk),                     //   input,    width = 1,                   hps_io.hps_osc_clk
		.hps_io_sdmmc_data0                     (hps_io_sdmmc_data0),                     //   inout,    width = 1,                         .sdmmc_data0
		.hps_io_sdmmc_data1                     (hps_io_sdmmc_data1),                     //   inout,    width = 1,                         .sdmmc_data1
		.hps_io_sdmmc_cclk                      (hps_io_sdmmc_cclk),                      //  output,    width = 1,                         .sdmmc_cclk
		.hps_io_sdmmc_data2                     (hps_io_sdmmc_data2),                     //   inout,    width = 1,                         .sdmmc_data2
		.hps_io_sdmmc_data3                     (hps_io_sdmmc_data3),                     //   inout,    width = 1,                         .sdmmc_data3
		.hps_io_sdmmc_cmd                       (hps_io_sdmmc_cmd),                       //   inout,    width = 1,                         .sdmmc_cmd
		.hps_io_usb1_clk                        (hps_io_usb1_clk),                        //   input,    width = 1,                         .usb1_clk
		.hps_io_usb1_stp                        (hps_io_usb1_stp),                        //  output,    width = 1,                         .usb1_stp
		.hps_io_usb1_dir                        (hps_io_usb1_dir),                        //   input,    width = 1,                         .usb1_dir
		.hps_io_usb1_data0                      (hps_io_usb1_data0),                      //   inout,    width = 1,                         .usb1_data0
		.hps_io_usb1_data1                      (hps_io_usb1_data1),                      //   inout,    width = 1,                         .usb1_data1
		.hps_io_usb1_nxt                        (hps_io_usb1_nxt),                        //   input,    width = 1,                         .usb1_nxt
		.hps_io_usb1_data2                      (hps_io_usb1_data2),                      //   inout,    width = 1,                         .usb1_data2
		.hps_io_usb1_data3                      (hps_io_usb1_data3),                      //   inout,    width = 1,                         .usb1_data3
		.hps_io_usb1_data4                      (hps_io_usb1_data4),                      //   inout,    width = 1,                         .usb1_data4
		.hps_io_usb1_data5                      (hps_io_usb1_data5),                      //   inout,    width = 1,                         .usb1_data5
		.hps_io_usb1_data6                      (hps_io_usb1_data6),                      //   inout,    width = 1,                         .usb1_data6
		.hps_io_usb1_data7                      (hps_io_usb1_data7),                      //   inout,    width = 1,                         .usb1_data7
		.hps_io_emac2_tx_clk                    (hps_io_emac2_tx_clk),                    //  output,    width = 1,                         .emac2_tx_clk
		.hps_io_emac2_tx_ctl                    (hps_io_emac2_tx_ctl),                    //  output,    width = 1,                         .emac2_tx_ctl
		.hps_io_emac2_rx_clk                    (hps_io_emac2_rx_clk),                    //   input,    width = 1,                         .emac2_rx_clk
		.hps_io_emac2_rx_ctl                    (hps_io_emac2_rx_ctl),                    //   input,    width = 1,                         .emac2_rx_ctl
		.hps_io_emac2_txd0                      (hps_io_emac2_txd0),                      //  output,    width = 1,                         .emac2_txd0
		.hps_io_emac2_txd1                      (hps_io_emac2_txd1),                      //  output,    width = 1,                         .emac2_txd1
		.hps_io_emac2_rxd0                      (hps_io_emac2_rxd0),                      //   input,    width = 1,                         .emac2_rxd0
		.hps_io_emac2_rxd1                      (hps_io_emac2_rxd1),                      //   input,    width = 1,                         .emac2_rxd1
		.hps_io_emac2_txd2                      (hps_io_emac2_txd2),                      //  output,    width = 1,                         .emac2_txd2
		.hps_io_emac2_txd3                      (hps_io_emac2_txd3),                      //  output,    width = 1,                         .emac2_txd3
		.hps_io_emac2_rxd2                      (hps_io_emac2_rxd2),                      //   input,    width = 1,                         .emac2_rxd2
		.hps_io_emac2_rxd3                      (hps_io_emac2_rxd3),                      //   input,    width = 1,                         .emac2_rxd3
		.hps_io_mdio2_mdio                      (hps_io_mdio2_mdio),                      //   inout,    width = 1,                         .mdio2_mdio
		.hps_io_mdio2_mdc                       (hps_io_mdio2_mdc),                       //  output,    width = 1,                         .mdio2_mdc
		.hps_io_uart0_tx                        (hps_io_uart0_tx),                        //  output,    width = 1,                         .uart0_tx
		.hps_io_uart0_rx                        (hps_io_uart0_rx),                        //   input,    width = 1,                         .uart0_rx
		.hps_io_i2c0_sda                        (hps_io_i2c0_sda),                        //   inout,    width = 1,                         .i2c0_sda
		.hps_io_i2c0_scl                        (hps_io_i2c0_scl),                        //   inout,    width = 1,                         .i2c0_scl
		.hps_io_gpio0                           (hps_io_gpio0),                           //   inout,    width = 1,                         .gpio0
		.hps_io_gpio1                           (hps_io_gpio1),                           //   inout,    width = 1,                         .gpio1
		.hps_io_gpio8                           (hps_io_gpio8),                           //   inout,    width = 1,                         .gpio8
		.hps_io_gpio9                           (hps_io_gpio9),                           //   inout,    width = 1,                         .gpio9
		.hps_io_gpio10                          (hps_io_gpio10),                          //   inout,    width = 1,                         .gpio10
		.hps_io_gpio11                          (hps_io_gpio11),                          //   inout,    width = 1,                         .gpio11
		.hps_io_gpio28                          (hps_io_gpio28),                          //   inout,    width = 1,                         .gpio28
		.usb31_io_vbus_det                      (usb31_io_vbus_det),                      //   input,    width = 1,                 usb31_io.vbus_det
		.usb31_io_flt_bar                       (usb31_io_flt_bar),                       //   input,    width = 1,                         .flt_bar
		.usb31_io_usb_ctrl                      (usb31_io_usb_ctrl),                      //  output,    width = 2,                         .usb_ctrl
		.usb31_io_usb31_id                      (usb31_io_usb31_id),                      //   input,    width = 1,                         .usb31_id
		.fpga2hps_interrupt_irq                 (fpga2hps_interrupt_irq),                 //   input,   width = 63,       fpga2hps_interrupt.irq
		.usb31_phy_pma_cpu_clk_clk              (usb31_phy_pma_cpu_clk_clk),              //   input,    width = 1,    usb31_phy_pma_cpu_clk.clk
		.usb31_phy_refclk_p_clk                 (usb31_phy_refclk_p_clk),                 //   input,    width = 1,       usb31_phy_refclk_p.clk
		.usb31_phy_refclk_n_clk                 (usb31_phy_refclk_n_clk),                 //   input,    width = 1,       usb31_phy_refclk_n.clk
		.usb31_phy_rx_serial_n_i_rx_serial_n    (usb31_phy_rx_serial_n_i_rx_serial_n),    //   input,    width = 1,    usb31_phy_rx_serial_n.i_rx_serial_n
		.usb31_phy_rx_serial_p_i_rx_serial_p    (usb31_phy_rx_serial_p_i_rx_serial_p),    //   input,    width = 1,    usb31_phy_rx_serial_p.i_rx_serial_p
		.usb31_phy_tx_serial_n_o_tx_serial_n    (usb31_phy_tx_serial_n_o_tx_serial_n),    //  output,    width = 1,    usb31_phy_tx_serial_n.o_tx_serial_n
		.usb31_phy_tx_serial_p_o_tx_serial_p    (usb31_phy_tx_serial_p_o_tx_serial_p),    //  output,    width = 1,    usb31_phy_tx_serial_p.o_tx_serial_p
		.usb31_phy_reconfig_rst_reset           (usb31_phy_reconfig_rst_reset),           //   input,    width = 1,   usb31_phy_reconfig_rst.reset
		.usb31_phy_reconfig_clk_clk             (usb31_phy_reconfig_clk_clk),             //   input,    width = 1,   usb31_phy_reconfig_clk.clk
		.usb31_phy_reconfig_slave_address       (usb31_phy_reconfig_slave_address),       //   input,   width = 21, usb31_phy_reconfig_slave.address
		.usb31_phy_reconfig_slave_byteenable    (usb31_phy_reconfig_slave_byteenable),    //   input,    width = 4,                         .byteenable
		.usb31_phy_reconfig_slave_readdatavalid (usb31_phy_reconfig_slave_readdatavalid), //  output,    width = 1,                         .readdatavalid
		.usb31_phy_reconfig_slave_read          (usb31_phy_reconfig_slave_read),          //   input,    width = 1,                         .read
		.usb31_phy_reconfig_slave_write         (usb31_phy_reconfig_slave_write),         //   input,    width = 1,                         .write
		.usb31_phy_reconfig_slave_readdata      (usb31_phy_reconfig_slave_readdata),      //  output,   width = 32,                         .readdata
		.usb31_phy_reconfig_slave_writedata     (usb31_phy_reconfig_slave_writedata),     //   input,   width = 32,                         .writedata
		.usb31_phy_reconfig_slave_waitrequest   (usb31_phy_reconfig_slave_waitrequest),   //  output,    width = 1,                         .waitrequest
		.f2sdram_axi_clock_clk                  (f2sdram_axi_clock_clk),                  //   input,    width = 1,        f2sdram_axi_clock.clk
		.f2sdram_axi_reset_reset                (f2sdram_axi_reset_reset),                //   input,    width = 1,        f2sdram_axi_reset.reset
		.f2sdram_araddr                         (f2sdram_araddr),                         //   input,   width = 32,                  f2sdram.araddr
		.f2sdram_arburst                        (f2sdram_arburst),                        //   input,    width = 2,                         .arburst
		.f2sdram_arcache                        (f2sdram_arcache),                        //   input,    width = 4,                         .arcache
		.f2sdram_arid                           (f2sdram_arid),                           //   input,    width = 5,                         .arid
		.f2sdram_arlen                          (f2sdram_arlen),                          //   input,    width = 8,                         .arlen
		.f2sdram_arlock                         (f2sdram_arlock),                         //   input,    width = 1,                         .arlock
		.f2sdram_arprot                         (f2sdram_arprot),                         //   input,    width = 3,                         .arprot
		.f2sdram_arqos                          (f2sdram_arqos),                          //   input,    width = 4,                         .arqos
		.f2sdram_arready                        (f2sdram_arready),                        //  output,    width = 1,                         .arready
		.f2sdram_arsize                         (f2sdram_arsize),                         //   input,    width = 3,                         .arsize
		.f2sdram_arvalid                        (f2sdram_arvalid),                        //   input,    width = 1,                         .arvalid
		.f2sdram_awaddr                         (f2sdram_awaddr),                         //   input,   width = 32,                         .awaddr
		.f2sdram_awburst                        (f2sdram_awburst),                        //   input,    width = 2,                         .awburst
		.f2sdram_awcache                        (f2sdram_awcache),                        //   input,    width = 4,                         .awcache
		.f2sdram_awid                           (f2sdram_awid),                           //   input,    width = 5,                         .awid
		.f2sdram_awlen                          (f2sdram_awlen),                          //   input,    width = 8,                         .awlen
		.f2sdram_awlock                         (f2sdram_awlock),                         //   input,    width = 1,                         .awlock
		.f2sdram_awprot                         (f2sdram_awprot),                         //   input,    width = 3,                         .awprot
		.f2sdram_awqos                          (f2sdram_awqos),                          //   input,    width = 4,                         .awqos
		.f2sdram_awready                        (f2sdram_awready),                        //  output,    width = 1,                         .awready
		.f2sdram_awsize                         (f2sdram_awsize),                         //   input,    width = 3,                         .awsize
		.f2sdram_awvalid                        (f2sdram_awvalid),                        //   input,    width = 1,                         .awvalid
		.f2sdram_bid                            (f2sdram_bid),                            //  output,    width = 5,                         .bid
		.f2sdram_bready                         (f2sdram_bready),                         //   input,    width = 1,                         .bready
		.f2sdram_bresp                          (f2sdram_bresp),                          //  output,    width = 2,                         .bresp
		.f2sdram_bvalid                         (f2sdram_bvalid),                         //  output,    width = 1,                         .bvalid
		.f2sdram_rdata                          (f2sdram_rdata),                          //  output,  width = 256,                         .rdata
		.f2sdram_rid                            (f2sdram_rid),                            //  output,    width = 5,                         .rid
		.f2sdram_rlast                          (f2sdram_rlast),                          //  output,    width = 1,                         .rlast
		.f2sdram_rready                         (f2sdram_rready),                         //   input,    width = 1,                         .rready
		.f2sdram_rresp                          (f2sdram_rresp),                          //  output,    width = 2,                         .rresp
		.f2sdram_rvalid                         (f2sdram_rvalid),                         //  output,    width = 1,                         .rvalid
		.f2sdram_wdata                          (f2sdram_wdata),                          //   input,  width = 256,                         .wdata
		.f2sdram_wlast                          (f2sdram_wlast),                          //   input,    width = 1,                         .wlast
		.f2sdram_wready                         (f2sdram_wready),                         //  output,    width = 1,                         .wready
		.f2sdram_wstrb                          (f2sdram_wstrb),                          //   input,   width = 32,                         .wstrb
		.f2sdram_wvalid                         (f2sdram_wvalid),                         //   input,    width = 1,                         .wvalid
		.f2sdram_aruser                         (f2sdram_aruser),                         //   input,    width = 8,                         .aruser
		.f2sdram_awuser                         (f2sdram_awuser),                         //   input,    width = 8,                         .awuser
		.f2sdram_wuser                          (f2sdram_wuser),                          //   input,    width = 8,                         .wuser
		.f2sdram_buser                          (f2sdram_buser),                          //  output,    width = 8,                         .buser
		.f2sdram_arregion                       (f2sdram_arregion),                       //   input,    width = 4,                         .arregion
		.f2sdram_ruser                          (f2sdram_ruser),                          //  output,    width = 8,                         .ruser
		.f2sdram_awregion                       (f2sdram_awregion),                       //   input,    width = 4,                         .awregion
		.io96b0_csr_axi_clk_clk                 (io96b0_csr_axi_clk_clk),                 //   input,    width = 1,       io96b0_csr_axi_clk.clk
		.io96b0_csr_axi_rst_reset_n             (io96b0_csr_axi_rst_reset_n),             //   input,    width = 1,       io96b0_csr_axi_rst.reset_n
		.io96b0_csr_axi_arready                 (io96b0_csr_axi_arready),                 //   input,    width = 1,           io96b0_csr_axi.arready
		.io96b0_csr_axi_awready                 (io96b0_csr_axi_awready),                 //   input,    width = 1,                         .awready
		.io96b0_csr_axi_bresp                   (io96b0_csr_axi_bresp),                   //   input,    width = 2,                         .bresp
		.io96b0_csr_axi_bvalid                  (io96b0_csr_axi_bvalid),                  //   input,    width = 1,                         .bvalid
		.io96b0_csr_axi_rdata                   (io96b0_csr_axi_rdata),                   //   input,   width = 32,                         .rdata
		.io96b0_csr_axi_rresp                   (io96b0_csr_axi_rresp),                   //   input,    width = 2,                         .rresp
		.io96b0_csr_axi_rvalid                  (io96b0_csr_axi_rvalid),                  //   input,    width = 1,                         .rvalid
		.io96b0_csr_axi_wready                  (io96b0_csr_axi_wready),                  //   input,    width = 1,                         .wready
		.io96b0_csr_axi_araddr                  (io96b0_csr_axi_araddr),                  //  output,   width = 32,                         .araddr
		.io96b0_csr_axi_arvalid                 (io96b0_csr_axi_arvalid),                 //  output,    width = 1,                         .arvalid
		.io96b0_csr_axi_awaddr                  (io96b0_csr_axi_awaddr),                  //  output,   width = 32,                         .awaddr
		.io96b0_csr_axi_awvalid                 (io96b0_csr_axi_awvalid),                 //  output,    width = 1,                         .awvalid
		.io96b0_csr_axi_bready                  (io96b0_csr_axi_bready),                  //  output,    width = 1,                         .bready
		.io96b0_csr_axi_rready                  (io96b0_csr_axi_rready),                  //  output,    width = 1,                         .rready
		.io96b0_csr_axi_wdata                   (io96b0_csr_axi_wdata),                   //  output,   width = 32,                         .wdata
		.io96b0_csr_axi_wstrb                   (io96b0_csr_axi_wstrb),                   //  output,    width = 4,                         .wstrb
		.io96b0_csr_axi_wvalid                  (io96b0_csr_axi_wvalid),                  //  output,    width = 1,                         .wvalid
		.io96b0_csr_axi_arprot                  (io96b0_csr_axi_arprot),                  //  output,    width = 3,                         .arprot
		.io96b0_csr_axi_awprot                  (io96b0_csr_axi_awprot),                  //  output,    width = 3,                         .awprot
		.io96b0_ch0_axi_clk_clk                 (io96b0_ch0_axi_clk_clk),                 //   input,    width = 1,       io96b0_ch0_axi_clk.clk
		.io96b0_ch0_axi_rst_reset_n             (io96b0_ch0_axi_rst_reset_n),             //   input,    width = 1,       io96b0_ch0_axi_rst.reset_n
		.io96b0_ch0_axi_arready                 (io96b0_ch0_axi_arready),                 //   input,    width = 1,           io96b0_ch0_axi.arready
		.io96b0_ch0_axi_awready                 (io96b0_ch0_axi_awready),                 //   input,    width = 1,                         .awready
		.io96b0_ch0_axi_bid                     (io96b0_ch0_axi_bid),                     //   input,    width = 7,                         .bid
		.io96b0_ch0_axi_bresp                   (io96b0_ch0_axi_bresp),                   //   input,    width = 2,                         .bresp
		.io96b0_ch0_axi_bvalid                  (io96b0_ch0_axi_bvalid),                  //   input,    width = 1,                         .bvalid
		.io96b0_ch0_axi_rdata                   (io96b0_ch0_axi_rdata),                   //   input,  width = 256,                         .rdata
		.io96b0_ch0_axi_rid                     (io96b0_ch0_axi_rid),                     //   input,    width = 7,                         .rid
		.io96b0_ch0_axi_rlast                   (io96b0_ch0_axi_rlast),                   //   input,    width = 1,                         .rlast
		.io96b0_ch0_axi_rresp                   (io96b0_ch0_axi_rresp),                   //   input,    width = 2,                         .rresp
		.io96b0_ch0_axi_ruser                   (io96b0_ch0_axi_ruser),                   //   input,   width = 32,                         .ruser
		.io96b0_ch0_axi_rvalid                  (io96b0_ch0_axi_rvalid),                  //   input,    width = 1,                         .rvalid
		.io96b0_ch0_axi_wready                  (io96b0_ch0_axi_wready),                  //   input,    width = 1,                         .wready
		.io96b0_ch0_axi_araddr                  (io96b0_ch0_axi_araddr),                  //  output,   width = 44,                         .araddr
		.io96b0_ch0_axi_arburst                 (io96b0_ch0_axi_arburst),                 //  output,    width = 2,                         .arburst
		.io96b0_ch0_axi_arid                    (io96b0_ch0_axi_arid),                    //  output,    width = 7,                         .arid
		.io96b0_ch0_axi_arlen                   (io96b0_ch0_axi_arlen),                   //  output,    width = 8,                         .arlen
		.io96b0_ch0_axi_arlock                  (io96b0_ch0_axi_arlock),                  //  output,    width = 1,                         .arlock
		.io96b0_ch0_axi_arqos                   (io96b0_ch0_axi_arqos),                   //  output,    width = 4,                         .arqos
		.io96b0_ch0_axi_arsize                  (io96b0_ch0_axi_arsize),                  //  output,    width = 3,                         .arsize
		.io96b0_ch0_axi_aruser                  (io96b0_ch0_axi_aruser),                  //  output,   width = 14,                         .aruser
		.io96b0_ch0_axi_arvalid                 (io96b0_ch0_axi_arvalid),                 //  output,    width = 1,                         .arvalid
		.io96b0_ch0_axi_awaddr                  (io96b0_ch0_axi_awaddr),                  //  output,   width = 44,                         .awaddr
		.io96b0_ch0_axi_awburst                 (io96b0_ch0_axi_awburst),                 //  output,    width = 2,                         .awburst
		.io96b0_ch0_axi_awid                    (io96b0_ch0_axi_awid),                    //  output,    width = 7,                         .awid
		.io96b0_ch0_axi_awlen                   (io96b0_ch0_axi_awlen),                   //  output,    width = 8,                         .awlen
		.io96b0_ch0_axi_awlock                  (io96b0_ch0_axi_awlock),                  //  output,    width = 1,                         .awlock
		.io96b0_ch0_axi_awqos                   (io96b0_ch0_axi_awqos),                   //  output,    width = 4,                         .awqos
		.io96b0_ch0_axi_awsize                  (io96b0_ch0_axi_awsize),                  //  output,    width = 3,                         .awsize
		.io96b0_ch0_axi_awuser                  (io96b0_ch0_axi_awuser),                  //  output,   width = 14,                         .awuser
		.io96b0_ch0_axi_awvalid                 (io96b0_ch0_axi_awvalid),                 //  output,    width = 1,                         .awvalid
		.io96b0_ch0_axi_bready                  (io96b0_ch0_axi_bready),                  //  output,    width = 1,                         .bready
		.io96b0_ch0_axi_rready                  (io96b0_ch0_axi_rready),                  //  output,    width = 1,                         .rready
		.io96b0_ch0_axi_wdata                   (io96b0_ch0_axi_wdata),                   //  output,  width = 256,                         .wdata
		.io96b0_ch0_axi_wlast                   (io96b0_ch0_axi_wlast),                   //  output,    width = 1,                         .wlast
		.io96b0_ch0_axi_wstrb                   (io96b0_ch0_axi_wstrb),                   //  output,   width = 32,                         .wstrb
		.io96b0_ch0_axi_wuser                   (io96b0_ch0_axi_wuser),                   //  output,   width = 32,                         .wuser
		.io96b0_ch0_axi_wvalid                  (io96b0_ch0_axi_wvalid),                  //  output,    width = 1,                         .wvalid
		.io96b0_ch0_axi_arprot                  (io96b0_ch0_axi_arprot),                  //  output,    width = 3,                         .arprot
		.io96b0_ch0_axi_awprot                  (io96b0_ch0_axi_awprot)                   //  output,    width = 3,                         .awprot
	);

endmodule
