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2024.05.17.11:03:18 | Datasheet

Overview

All Components
ext_hps_f2sdram_master altera_address_span_extender 19.2.0
subsys_hps hps_subsys 1.0
subsys_hps_agilex_hps intel_agilex_5_soc 3.0.0
subsys_periph peripheral_subsys 1.0
subsys_periph_button_pio altera_avalon_pio 19.2.3
subsys_periph_dipsw_pio altera_avalon_pio 19.2.3
subsys_periph_led_pio altera_avalon_pio 19.2.3
subsys_periph_pb_cpu_0 altera_avalon_mm_bridge 20.1.0
subsys_periph_sysid altera_avalon_sysid_qsys 19.1.6
Memory Map

| ext_hps_f2sdram_master | subsys_debug | subsys_debug_fpga_m | subsys_debug_hps_f2sdram | subsys_hps | subsys_hps_agilex_hps | subsys_hps_f2sdram_adapter | subsys_periph_pb_cpu_0
expanded_master | fpga_m_master | hps_f2sdram_master | master | master | hps2fpga | lwhps2fpga | hps2fpga | lwhps2fpga | io96b0_csr_axi | io96b0_ch0_axi | axi4_man | m0
ext_hps_f2sdram_master |  |  |  |  |  |  |  |  |  |  |  |  |
windowed_slave |  |  | 0x0000_0000 - 0xffff_ffff |  | 0x0000_0000 - 0xffff_ffff |  |  |  |  |  |  |  |
ocm |  |  |  |  |  |  |  |  |  |  |  |  |
axi_s1 |  | 0x0004_0000 - 0x0007_ffff |  | 0x0004_0000 - 0x0007_ffff |  | 0x0000_0000_0000_0000 - 0x0000_0000_0003_ffff |  | 0x0000_0000_0000_0000 - 0x0000_0000_0003_ffff |  |  |  |  |
subsys_hps |  |  |  |  |  |  |  |  |  |  |  |  |
usb31_phy_reconfig_slave |  |  |  |  |  |  |  |  |  |  |  |  |
f2sdram_adapter_axi4_sub |  |  |  |  |  |  |  |  |  |  |  |  |
subsys_hps_agilex_hps |  |  |  |  |  |  |  |  |  |  |  |  |
usb31_phy_reconfig_slave |  | 0x0080_0000 - 0x00ff_ffff |  | 0x0080_0000 - 0x00ff_ffff |  |  | 0x0080_0000 - 0x00ff_ffff |  | 0x0080_0000 - 0x00ff_ffff |  |  |  |
f2sdram |  |  |  |  |  |  |  |  |  |  |  | 0x0000_0000 - 0xffff_ffff |
subsys_hps_emif_hps |  |  |  |  |  |  |  |  |  |  |  |  |
s0_axi4 |  |  |  |  |  |  |  |  |  |  | 0x0000_0000_0000_0000 - 0x0000_00ff_ffff_ffff |  |
s0_axil |  |  |  |  |  |  |  |  |  | 0x0000_0000 - 0x07ff_ffff |  |  |
subsys_hps_f2sdram_adapter |  |  |  |  |  |  |  |  |  |  |  |  |
axi4_sub | 0x0000_0000_0000_0000 - 0x0000_0000_ffff_ffff |  | 0x0000_0000 - 0xffff_ffff |  | 0x0000_0000 - 0xffff_ffff |  |  |  |  |  |  |  |
subsys_periph |  |  |  |  |  |  |  |  |  |  |  |  |
pb_cpu_0_s0 |  |  |  |  |  |  |  |  |  |  |  |  |
subsys_periph_button_pio |  |  |  |  |  |  |  |  |  |  |  |  |
s1 |  |  |  |  |  |  | 0x0001_0060 - 0x0001_006f |  | 0x0001_0060 - 0x0001_006f |  |  |  | 0x0001_0060 - 0x0001_006f
subsys_periph_dipsw_pio |  |  |  |  |  |  |  |  |  |  |  |  |
s1 |  |  |  |  |  |  | 0x0001_0070 - 0x0001_007f |  | 0x0001_0070 - 0x0001_007f |  |  |  | 0x0001_0070 - 0x0001_007f
subsys_periph_led_pio |  |  |  |  |  |  |  |  |  |  |  |  |
s1 |  |  |  |  |  |  | 0x0001_0080 - 0x0001_008f |  | 0x0001_0080 - 0x0001_008f |  |  |  | 0x0001_0080 - 0x0001_008f
subsys_periph_pb_cpu_0 |  |  |  |  |  |  |  |  |  |  |  |  |
s0 |  |  |  |  |  |  | 0x0000_0000 - 0x0001_ffff |  | 0x0000_0000 - 0x0001_ffff |  |  |  |
subsys_periph_sysid |  |  |  |  |  |  |  |  |  |  |  |  |
control_slave |  |  |  |  |  |  | 0x0001_0000 - 0x0001_0007 |  | 0x0001_0000 - 0x0001_0007 |  |  |  | 0x0001_0000 - 0x0001_0007

## clk_100

altera_clock_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## ext_hps_f2sdram_master

altera_address_span_extender v19.2.0

subsys_debug_hps_f2sdram | master | ext_hps_f2sdram_master
windowed_slave
clk_100 | out_clk
clock
rst_in | out_reset
reset
|  | expanded_master | subsys_hps_f2sdram_adapter
|  | axi4_sub

## Parameters
generateLegacySim | false

## Software Assignments
BURSTCOUNT_WIDTH | 1
BYTEENABLE_WIDTH | 4
CNTL_ADDRESS_WIDTH | 1
DATA_WIDTH | 32
MASTER_ADDRESS_WIDTH | 33
MAX_BURST_BYTES | 4
MAX_BURST_WORDS | 1
SLAVE_ADDRESS_SHIFT | 2
SLAVE_ADDRESS_WIDTH | 30
SUB_WINDOW_COUNT | 1

## ocm

intel_onchip_memory v1.4.8

subsys_debug_fpga_m | master | ocm
axi_s1
subsys_hps_agilex_hps | hps2fpga
axi_s1
clk_100 | out_clk
clk1
rst_in | out_reset
reset1

## Parameters
generateLegacySim | false

## Software Assignments
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR | 0
CONTENTS_INFO | ""
DUAL_PORT | 0
GUI_RAM_BLOCK_TYPE | AUTO
INIT_CONTENTS_FILE | ocm_intel_onchip_memory_inst
INIT_MEM_CONTENT | 1
INSTANCE_ID | NONE
NON_DEFAULT_INIT_FILE_ENABLED | 0
RAM_BLOCK_TYPE | AUTO
READ_DURING_WRITE_MODE | DONT_CARE
SINGLE_CLOCK_OP | 1
SIZE_MULTIPLE | 1
SIZE_VALUE | 262144
WRITABLE | 1

## rst_in

altera_reset_bridge v19.2.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## user_rst_clkgate_0

intel_user_rst_clkgate v1.0.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_debug

jtag_subsys v1.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_debug_fpga_m

altera_jtag_avalon_master v19.1

subsys_debug_jtag_clk | out_clk | subsys_debug_fpga_m
clk
subsys_debug_jtag_rst_in | out_reset
clk_reset
|  | master | ocm
|  | axi_s1
|  | master | subsys_hps_agilex_hps
|  | usb31_phy_reconfig_slave

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_debug_hps_f2sdram

altera_jtag_avalon_master v19.1

subsys_debug_jtag_clk | out_clk | subsys_debug_hps_f2sdram
clk
subsys_debug_jtag_rst_in | out_reset
clk_reset
|  | master | ext_hps_f2sdram_master
|  | windowed_slave

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_debug_jtag_clk

altera_clock_bridge v19.2.0

clk_100 | out_clk | subsys_debug_jtag_clk
in_clk
|  | out_clk | subsys_debug_fpga_m
|  | clk
|  | out_clk | subsys_debug_jtag_rst_in
|  | clk
|  | out_clk | subsys_debug_hps_f2sdram
|  | clk

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_debug_jtag_rst_in

altera_reset_bridge v19.2.0

subsys_debug_jtag_clk | out_clk | subsys_debug_jtag_rst_in
clk
rst_in | out_reset
in_reset
|  | out_reset | subsys_debug_fpga_m
|  | clk_reset
|  | out_reset | subsys_debug_hps_f2sdram
|  | clk_reset

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_hps

hps_subsys v1.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_hps_agilex_hps

intel_agilex_5_soc v3.0.0

subsys_hps_f2sdram_adapter | axi4_man | subsys_hps_agilex_hps
f2sdram
subsys_hps_emif_hps | s0_axil_clk
io96b0_csr_axi_clk
usr_clk_0
io96b0_ch0_axi_clk
s0_axil_rst_n
io96b0_csr_axi_rst
usr_rst_n_0
io96b0_ch0_axi_rst
subsys_debug_fpga_m | master
usb31_phy_reconfig_slave
clk_100 | out_clk
f2sdram_axi_clock
out_clk
hps2fpga_axi_clock
out_clk
lwhps2fpga_axi_clock
out_clk
usb31_phy_reconfig_clk
rst_in | out_reset
f2sdram_axi_reset
out_reset
hps2fpga_axi_reset
out_reset
lwhps2fpga_axi_reset
out_reset
usb31_phy_reconfig_rst
|  | io96b0_ch0_axi | subsys_hps_emif_hps
|  | s0_axi4
|  | io96b0_csr_axi
|  | s0_axil
|  | hps2fpga | ocm
|  | axi_s1
|  | lwhps2fpga | subsys_periph_pb_cpu_0
|  | s0
|  | fpga2hps_interrupt | subsys_periph_button_pio
|  | irq
|  | fpga2hps_interrupt | subsys_periph_dipsw_pio
|  | irq

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_hps_emif_hps

emif_hps_ph2 v6.1.0

subsys_hps_agilex_hps | io96b0_ch0_axi | subsys_hps_emif_hps
s0_axi4
io96b0_csr_axi
s0_axil
|  | s0_axil_clk | subsys_hps_agilex_hps
|  | io96b0_csr_axi_clk
|  | usr_clk_0
|  | io96b0_ch0_axi_clk
|  | s0_axil_rst_n
|  | io96b0_csr_axi_rst
|  | usr_rst_n_0
|  | io96b0_ch0_axi_rst

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_hps_f2sdram_adapter

f2sdram_adapter v1.0

ext_hps_f2sdram_master | expanded_master | subsys_hps_f2sdram_adapter
axi4_sub
clk_100 | out_clk
clock
rst_in | out_reset
reset
|  | axi4_man | subsys_hps_agilex_hps
|  | f2sdram

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_hps_gts_inst

intel_srcss_gts v3.0.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_periph

peripheral_subsys v1.0

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_periph_button_pio

altera_avalon_pio v19.2.3

subsys_periph_pb_cpu_0 | m0 | subsys_periph_button_pio
s1
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset
subsys_hps_agilex_hps | fpga2hps_interrupt
irq

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 1
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | FALLING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## subsys_periph_dipsw_pio

altera_avalon_pio v19.2.3

subsys_periph_pb_cpu_0 | m0 | subsys_periph_dipsw_pio
s1
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset
subsys_hps_agilex_hps | fpga2hps_interrupt
irq

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 1
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 1
DATA_WIDTH | 4
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | FALLING
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 0
HAS_TRI | 0
IRQ_TYPE | EDGE
RESET_VALUE | 0

## subsys_periph_led_pio

altera_avalon_pio v19.2.3

subsys_periph_pb_cpu_0 | m0 | subsys_periph_led_pio
s1
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
CAPTURE | 0
DATA_WIDTH | 3
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0
EDGE_TYPE | NONE
FREQ | 100000000
HAS_IN | 1
HAS_OUT | 1
HAS_TRI | 0
IRQ_TYPE | NONE
RESET_VALUE | 1

## subsys_periph_pb_cpu_0

altera_avalon_mm_bridge v20.1.0

subsys_periph_periph_clk | out_clk | subsys_periph_pb_cpu_0
clk
subsys_periph_periph_rst_in | out_reset
reset
subsys_hps_agilex_hps | lwhps2fpga
s0
|  | m0 | subsys_periph_sysid
|  | control_slave
|  | m0 | subsys_periph_led_pio
|  | s1
|  | m0 | subsys_periph_dipsw_pio
|  | s1
|  | m0 | subsys_periph_button_pio
|  | s1

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_periph_periph_clk

altera_clock_bridge v19.2.0

clk_100 | out_clk | subsys_periph_periph_clk
in_clk
|  | out_clk | subsys_periph_sysid
|  | clk
|  | out_clk | subsys_periph_pb_cpu_0
|  | clk
|  | out_clk | subsys_periph_periph_rst_in
|  | clk
|  | out_clk | subsys_periph_led_pio
|  | clk
|  | out_clk | subsys_periph_dipsw_pio
|  | clk
|  | out_clk | subsys_periph_button_pio
|  | clk

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_periph_periph_rst_in

altera_reset_bridge v19.2.0

subsys_periph_periph_clk | out_clk | subsys_periph_periph_rst_in
clk
rst_in | out_reset
in_reset
|  | out_reset | subsys_periph_sysid
|  | reset
|  | out_reset | subsys_periph_led_pio
|  | reset
|  | out_reset | subsys_periph_dipsw_pio
|  | reset
|  | out_reset | subsys_periph_button_pio
|  | reset
|  | out_reset | subsys_periph_pb_cpu_0
|  | reset

## Parameters
generateLegacySim | false

## Software Assignments (none)

## subsys_periph_sysid

altera_avalon_sysid_qsys v19.1.6

subsys_periph_pb_cpu_0 | m0 | subsys_periph_sysid
control_slave
subsys_periph_periph_clk | out_clk
clk
subsys_periph_periph_rst_in | out_reset
reset

## Parameters
generateLegacySim | false

## Software Assignments
ID | -1395275010
TIMESTAMP | 0

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