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// Copyright 2021 Intel Corporation. 
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module add_a_b_s0_s1 #(
    parameter SIZE = 5
)(
    input [SIZE-1:0] a,
    input [SIZE-1:0] b,
    input s0,
    input s1,
    output [SIZE-1:0] out
);
    wire [SIZE:0] left;
    wire [SIZE:0] right;
    wire temp;
    
    assign left = {a ^ b, s0};
    assign right = {a[SIZE-2:0] & b[SIZE-2:0], s1, s0};
    assign {out, temp} = left + right;
    
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "Vd3tEFjpZj96rI/+F/VvE60mTEymAEQpoSTBEGkPZDn8vLE37C5u3t6a/YuDWdcpDICg4yaS41BVZL43rgMWoo/ODQa6HJ+98xz96XdaxZoH7knVWHHmdjwNoot126KwBXxYxMAyWcKq2a9b9HntBfzAKtQF4cCehbSzlUccpMg8lYZJJ73s4nMHdujybKqOU3uA0uLLaEuflzNF5/A5MXI1hPhdpBgL5/hYcV95h9PmjVb8CQfO6l8R29kDNSwBKD4x/GdKBZqgnjk632EQt/RZ7A7HNFwzE/tgpduXbEdnQzzv3kKl05dZxIZ9S1qwco/YydcFSfcHZpI4wk20cdXy95czxPGYz0W/qe1Aajo7jGS4QfTbhgDGBKI5sl/bMya2MDTZIru4PXYwqEYJPu5AzwegKP813/fPy/k9slPs/egtJoG3LU5r9AH1H5CrFme6pPo0a3hXXIfd+3RGefldcV9ClLbkRnDf14o2lJ8a6FLrwpUk8ML7KFd1EzL/4DdNgDQGCcBvpUZlie1McivWE/vEAdEntHda88x4g4zJuJauvglrD+l4lKrCo30zTILoTLyPkEjKx66OsoGK+21zDslF1PYbpH4uqSAVvZRlxGty3+JipDYh2FsDJdI98zNYdeIjYFVcF7vswHSy7NeED0mRTli92d9KYssX+Q54xLJX9nXnakeQZ3oKv6W8jHPmCjkoMHNLdkIsrdoVprFdYHTa3+Ic6930WXC5GFi1G/DzMUeSitQjURfxtth8Kb3siFMk/vpR2FwWKs2q/ZKV6TB2YRuddbdEzhUWIMWuO0RieRm8dO5OoP7rT9BvZ5dxLXmVnRXeBGX9iYgD2quYZCEZ9ZWlvFtxoj9mtqNAD/cDfFm6Sbl910wrDKddDWSlbtFgVzuje7jFp7sbC6WyAdWITUN7r7PcmyX3Ia2CoyHwjoWZskJrzW8JrFx1iVYkI4zH/mV4irUIR1qtKiiHi6eRPXpeKrIT7Cs1R7TSPYggIliocRCMweN8LWo3"
`endif