	emif_hps u0 (
		.noc_aclk_0              (_connected_to_noc_aclk_0_),              //  output,    width = 1,      usr_clk_0.clk
		.s0_axi4_araddr          (_connected_to_s0_axi4_araddr_),          //   input,   width = 40,        s0_axi4.araddr
		.s0_axi4_arburst         (_connected_to_s0_axi4_arburst_),         //   input,    width = 2,               .arburst
		.s0_axi4_arid            (_connected_to_s0_axi4_arid_),            //   input,    width = 7,               .arid
		.s0_axi4_arlen           (_connected_to_s0_axi4_arlen_),           //   input,    width = 8,               .arlen
		.s0_axi4_arlock          (_connected_to_s0_axi4_arlock_),          //   input,    width = 1,               .arlock
		.s0_axi4_arqos           (_connected_to_s0_axi4_arqos_),           //   input,    width = 4,               .arqos
		.s0_axi4_arsize          (_connected_to_s0_axi4_arsize_),          //   input,    width = 3,               .arsize
		.s0_axi4_arvalid         (_connected_to_s0_axi4_arvalid_),         //   input,    width = 1,               .arvalid
		.s0_axi4_aruser          (_connected_to_s0_axi4_aruser_),          //   input,   width = 14,               .aruser
		.s0_axi4_arprot          (_connected_to_s0_axi4_arprot_),          //   input,    width = 3,               .arprot
		.s0_axi4_awaddr          (_connected_to_s0_axi4_awaddr_),          //   input,   width = 40,               .awaddr
		.s0_axi4_awburst         (_connected_to_s0_axi4_awburst_),         //   input,    width = 2,               .awburst
		.s0_axi4_awid            (_connected_to_s0_axi4_awid_),            //   input,    width = 7,               .awid
		.s0_axi4_awlen           (_connected_to_s0_axi4_awlen_),           //   input,    width = 8,               .awlen
		.s0_axi4_awlock          (_connected_to_s0_axi4_awlock_),          //   input,    width = 1,               .awlock
		.s0_axi4_awqos           (_connected_to_s0_axi4_awqos_),           //   input,    width = 4,               .awqos
		.s0_axi4_awsize          (_connected_to_s0_axi4_awsize_),          //   input,    width = 3,               .awsize
		.s0_axi4_awvalid         (_connected_to_s0_axi4_awvalid_),         //   input,    width = 1,               .awvalid
		.s0_axi4_awuser          (_connected_to_s0_axi4_awuser_),          //   input,   width = 14,               .awuser
		.s0_axi4_awprot          (_connected_to_s0_axi4_awprot_),          //   input,    width = 3,               .awprot
		.s0_axi4_bready          (_connected_to_s0_axi4_bready_),          //   input,    width = 1,               .bready
		.s0_axi4_rready          (_connected_to_s0_axi4_rready_),          //   input,    width = 1,               .rready
		.s0_axi4_wdata           (_connected_to_s0_axi4_wdata_),           //   input,  width = 256,               .wdata
		.s0_axi4_wstrb           (_connected_to_s0_axi4_wstrb_),           //   input,   width = 32,               .wstrb
		.s0_axi4_wlast           (_connected_to_s0_axi4_wlast_),           //   input,    width = 1,               .wlast
		.s0_axi4_wvalid          (_connected_to_s0_axi4_wvalid_),          //   input,    width = 1,               .wvalid
		.s0_axi4_wuser           (_connected_to_s0_axi4_wuser_),           //   input,   width = 32,               .wuser
		.s0_axi4_ruser           (_connected_to_s0_axi4_ruser_),           //  output,   width = 32,               .ruser
		.s0_axi4_arready         (_connected_to_s0_axi4_arready_),         //  output,    width = 1,               .arready
		.s0_axi4_awready         (_connected_to_s0_axi4_awready_),         //  output,    width = 1,               .awready
		.s0_axi4_bid             (_connected_to_s0_axi4_bid_),             //  output,    width = 7,               .bid
		.s0_axi4_bresp           (_connected_to_s0_axi4_bresp_),           //  output,    width = 2,               .bresp
		.s0_axi4_bvalid          (_connected_to_s0_axi4_bvalid_),          //  output,    width = 1,               .bvalid
		.s0_axi4_rdata           (_connected_to_s0_axi4_rdata_),           //  output,  width = 256,               .rdata
		.s0_axi4_rid             (_connected_to_s0_axi4_rid_),             //  output,    width = 7,               .rid
		.s0_axi4_rlast           (_connected_to_s0_axi4_rlast_),           //  output,    width = 1,               .rlast
		.s0_axi4_rresp           (_connected_to_s0_axi4_rresp_),           //  output,    width = 2,               .rresp
		.s0_axi4_rvalid          (_connected_to_s0_axi4_rvalid_),          //  output,    width = 1,               .rvalid
		.s0_axi4_wready          (_connected_to_s0_axi4_wready_),          //  output,    width = 1,               .wready
		.emif_mem_0_mem_ck_t     (_connected_to_emif_mem_0_mem_ck_t_),     //  output,    width = 1,     emif_mem_0.mem_ck_t
		.emif_mem_0_mem_ck_c     (_connected_to_emif_mem_0_mem_ck_c_),     //  output,    width = 1,               .mem_ck_c
		.emif_mem_0_mem_cke      (_connected_to_emif_mem_0_mem_cke_),      //  output,    width = 1,               .mem_cke
		.emif_mem_0_mem_odt      (_connected_to_emif_mem_0_mem_odt_),      //  output,    width = 1,               .mem_odt
		.emif_mem_0_mem_cs_n     (_connected_to_emif_mem_0_mem_cs_n_),     //  output,    width = 1,               .mem_cs_n
		.emif_mem_0_mem_a        (_connected_to_emif_mem_0_mem_a_),        //  output,   width = 17,               .mem_a
		.emif_mem_0_mem_ba       (_connected_to_emif_mem_0_mem_ba_),       //  output,    width = 2,               .mem_ba
		.emif_mem_0_mem_bg       (_connected_to_emif_mem_0_mem_bg_),       //  output,    width = 1,               .mem_bg
		.emif_mem_0_mem_act_n    (_connected_to_emif_mem_0_mem_act_n_),    //  output,    width = 1,               .mem_act_n
		.emif_mem_0_mem_par      (_connected_to_emif_mem_0_mem_par_),      //  output,    width = 1,               .mem_par
		.emif_mem_0_mem_alert_n  (_connected_to_emif_mem_0_mem_alert_n_),  //   input,    width = 1,               .mem_alert_n
		.emif_mem_0_mem_reset_n  (_connected_to_emif_mem_0_mem_reset_n_),  //  output,    width = 1,               .mem_reset_n
		.emif_mem_0_mem_dq       (_connected_to_emif_mem_0_mem_dq_),       //   inout,   width = 32,               .mem_dq
		.emif_mem_0_mem_dqs_t    (_connected_to_emif_mem_0_mem_dqs_t_),    //   inout,    width = 4,               .mem_dqs_t
		.emif_mem_0_mem_dqs_c    (_connected_to_emif_mem_0_mem_dqs_c_),    //   inout,    width = 4,               .mem_dqs_c
		.emif_mem_0_mem_dbi_n    (_connected_to_emif_mem_0_mem_dbi_n_),    //   inout,    width = 4,               .mem_dbi_n
		.emif_oct_0_oct_rzqin    (_connected_to_emif_oct_0_oct_rzqin_),    //   input,    width = 1,     emif_oct_0.oct_rzqin
		.s0_noc_axi4lite_clk     (_connected_to_s0_noc_axi4lite_clk_),     //  output,    width = 1,    s0_axil_clk.clk
		.s0_noc_axi4lite_rst_n   (_connected_to_s0_noc_axi4lite_rst_n_),   //  output,    width = 1,  s0_axil_rst_n.reset_n
		.s0_noc_axi4lite_awaddr  (_connected_to_s0_noc_axi4lite_awaddr_),  //   input,   width = 27,        s0_axil.awaddr
		.s0_noc_axi4lite_awvalid (_connected_to_s0_noc_axi4lite_awvalid_), //   input,    width = 1,               .awvalid
		.s0_noc_axi4lite_awready (_connected_to_s0_noc_axi4lite_awready_), //  output,    width = 1,               .awready
		.s0_noc_axi4lite_wdata   (_connected_to_s0_noc_axi4lite_wdata_),   //   input,   width = 32,               .wdata
		.s0_noc_axi4lite_wstrb   (_connected_to_s0_noc_axi4lite_wstrb_),   //   input,    width = 4,               .wstrb
		.s0_noc_axi4lite_wvalid  (_connected_to_s0_noc_axi4lite_wvalid_),  //   input,    width = 1,               .wvalid
		.s0_noc_axi4lite_wready  (_connected_to_s0_noc_axi4lite_wready_),  //  output,    width = 1,               .wready
		.s0_noc_axi4lite_bresp   (_connected_to_s0_noc_axi4lite_bresp_),   //  output,    width = 2,               .bresp
		.s0_noc_axi4lite_bvalid  (_connected_to_s0_noc_axi4lite_bvalid_),  //  output,    width = 1,               .bvalid
		.s0_noc_axi4lite_bready  (_connected_to_s0_noc_axi4lite_bready_),  //   input,    width = 1,               .bready
		.s0_noc_axi4lite_araddr  (_connected_to_s0_noc_axi4lite_araddr_),  //   input,   width = 27,               .araddr
		.s0_noc_axi4lite_arvalid (_connected_to_s0_noc_axi4lite_arvalid_), //   input,    width = 1,               .arvalid
		.s0_noc_axi4lite_arready (_connected_to_s0_noc_axi4lite_arready_), //  output,    width = 1,               .arready
		.s0_noc_axi4lite_rdata   (_connected_to_s0_noc_axi4lite_rdata_),   //  output,   width = 32,               .rdata
		.s0_noc_axi4lite_rresp   (_connected_to_s0_noc_axi4lite_rresp_),   //  output,    width = 2,               .rresp
		.s0_noc_axi4lite_rvalid  (_connected_to_s0_noc_axi4lite_rvalid_),  //  output,    width = 1,               .rvalid
		.s0_noc_axi4lite_rready  (_connected_to_s0_noc_axi4lite_rready_),  //   input,    width = 1,               .rready
		.s0_noc_axi4lite_awprot  (_connected_to_s0_noc_axi4lite_awprot_),  //   input,    width = 3,               .awprot
		.s0_noc_axi4lite_arprot  (_connected_to_s0_noc_axi4lite_arprot_),  //   input,    width = 3,               .arprot
		.out_reset_0_n           (_connected_to_out_reset_0_n_),           //  output,    width = 1,    usr_rst_n_0.reset_n
		.emif_ref_clk_0_clk      (_connected_to_emif_ref_clk_0_clk_)       //   input,    width = 1, emif_ref_clk_0.clk
	);

