set ::GLOBAL_phy_arch_name                  emif_hps_emif_ph2_phy_arch_fp_610_y5glxty

set var(MEM_TECHNOLOGY)                     MEM_TECHNOLOGY_DDR4
set var(PHY_REFCLK_FREQ_MHZ)                150.0
set var(PHY_MEMCLK_FREQ_MHZ)                1200.0
set var(MEM_DQ_WIDTH)                       32
set var(PHY_NOC_EN)                         true
set var(MEM_CLK_ASYNC)                      1
set var(CLK_DIV_VCO_MEM)                    1
set var(CLK_DIV_MEM_REF)                    8
set var(CLK_DIV_MEM_PHY)                    2
set var(PLL_C_DIV_0)                        2
set var(PLL_C_DIV_1)                        256
set var(PLL_N_DIV)                          1
set var(PLL_M_DIV)                          8
set var(CLK_DIV_VCO_CORE)                   4
set var(DQ_PER_DQS)                         8
set var(LOCKSTEP_ROLE)                      OFF
