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module ff_macro_c2p # (
 parameter DATA_WIDTH = 256,
 parameter NUM_FLOPS = 1 // based on number of flops you need in 1 dir 
 ) (
 input logic clk,

 input [DATA_WIDTH -1:0] in_data ,

 output [DATA_WIDTH -1:0] out_data

);


 (* altera_attribute = {"-name FORCE_HYPER_REGISTER_FOR_CORE_PERIPHERY_TRANSFER ON; -name HYPER_REGISTER_DELAY_CHAIN 350"} *)
    reg [DATA_WIDTH-1:0] in_data_reg [NUM_FLOPS:0];    

    assign in_data_reg[0] = in_data;


    genvar i;
    
    generate 
    for (i=0 ; i<NUM_FLOPS ; i=i+1 ) begin
      always @(posedge clk) begin
          in_data_reg[i+1] <= in_data_reg[i];
      end
    end
    endgenerate

    assign out_data = in_data_reg[NUM_FLOPS];



    
endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "Vd3tEFjpZj96rI/+F/VvE60mTEymAEQpoSTBEGkPZDn8vLE37C5u3t6a/YuDWdcpDICg4yaS41BVZL43rgMWoo/ODQa6HJ+98xz96XdaxZoH7knVWHHmdjwNoot126KwBXxYxMAyWcKq2a9b9HntBfzAKtQF4cCehbSzlUccpMg8lYZJJ73s4nMHdujybKqOU3uA0uLLaEuflzNF5/A5MXI1hPhdpBgL5/hYcV95h9OPKkwGnHtWvjJlmM0U3/pTZg5J02su9gU+MiWvyF9tQCDkIuAY3AMrb8g1iJWXJxdOrZA3x6mTAPDOpk+fhSFVawOgPq3XAwonVF1B9+7RN+TecoZadPcEt9aU6eyGOs2JzTPOL0wY0Ft0IlG3dbvtw9ODUeNfJzQS8ig5BFokLSJri+AJ/U/gXRd5pGMrUqgiUd+jq3JkLOJO0NiamMVI6LUnu40Tr+YIrq6M6Q4S6jNAtJNDyYvntJCDm4ivKR1oXJHslGrms6a+K4BdY/zo49SE63Veh19Swra4yB9xY+FaUQ1h62cR6HdtXf8NXoI0Bx55V8C0EonnOme5M5rtzyoCMnBV9kwM+pVjYB7cFdsnNVF75h8vfXFcwGSu8XgKSBHC7eRCRQ4uuKbc7dLoJvVKNY7RcMjmfV3JfdymUGWMif5yGhnUWWd0/lCQiwnJIcqsxOGGAxkyPMYVulOLIKoj89IqxzZeX8Mn06ogt39HcDImxtqJuYJgQ0GMt6xvC8bO4xpzQ18xe17zLdk78B5RqcD2KnK6swYcPMuhn0Wu2LI8Tw4CrNmdt+6tV2n7uio4eL3c+lL3r81bLr1UlX68bSj4y5W/tcLUQ4EoGqWeQcVz2C46PAyrFKohMHwUx2OCD0YuONtFIeTyN+yZoPl3nlA9bqGWgrT6McJpuRsum3T+N3043YUvb+sc8wAL+BDXcVKC0Gdy5N68OSsgOtOeAO4QJFB6DxhJAjunSXN2iCkt+xiDHDuzkfookYBcpoGnfU+cmchJYa9qdLZo"
`endif