// qsys_top_altera_mm_interconnect_1920_vlx36uy.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module qsys_top_altera_mm_interconnect_1920_vlx36uy (
		input  wire [32:0]  ext_hps_f2sdram_master_expanded_master_address,                                      //                                        ext_hps_f2sdram_master_expanded_master.address
		output wire         ext_hps_f2sdram_master_expanded_master_waitrequest,                                  //                                                                              .waitrequest
		input  wire [0:0]   ext_hps_f2sdram_master_expanded_master_burstcount,                                   //                                                                              .burstcount
		input  wire [3:0]   ext_hps_f2sdram_master_expanded_master_byteenable,                                   //                                                                              .byteenable
		input  wire         ext_hps_f2sdram_master_expanded_master_read,                                         //                                                                              .read
		output wire [31:0]  ext_hps_f2sdram_master_expanded_master_readdata,                                     //                                                                              .readdata
		output wire         ext_hps_f2sdram_master_expanded_master_readdatavalid,                                //                                                                              .readdatavalid
		input  wire         ext_hps_f2sdram_master_expanded_master_write,                                        //                                                                              .write
		input  wire [31:0]  ext_hps_f2sdram_master_expanded_master_writedata,                                    //                                                                              .writedata
		output wire [4:0]   subsys_hps_f2sdram_adapter_axi4_sub_awid,                                            //                                           subsys_hps_f2sdram_adapter_axi4_sub.awid
		output wire [31:0]  subsys_hps_f2sdram_adapter_axi4_sub_awaddr,                                          //                                                                              .awaddr
		output wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_awlen,                                           //                                                                              .awlen
		output wire [2:0]   subsys_hps_f2sdram_adapter_axi4_sub_awsize,                                          //                                                                              .awsize
		output wire [1:0]   subsys_hps_f2sdram_adapter_axi4_sub_awburst,                                         //                                                                              .awburst
		output wire [0:0]   subsys_hps_f2sdram_adapter_axi4_sub_awlock,                                          //                                                                              .awlock
		output wire [3:0]   subsys_hps_f2sdram_adapter_axi4_sub_awcache,                                         //                                                                              .awcache
		output wire [2:0]   subsys_hps_f2sdram_adapter_axi4_sub_awprot,                                          //                                                                              .awprot
		output wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_awuser,                                          //                                                                              .awuser
		output wire [3:0]   subsys_hps_f2sdram_adapter_axi4_sub_awqos,                                           //                                                                              .awqos
		output wire [3:0]   subsys_hps_f2sdram_adapter_axi4_sub_awregion,                                        //                                                                              .awregion
		output wire         subsys_hps_f2sdram_adapter_axi4_sub_awvalid,                                         //                                                                              .awvalid
		input  wire         subsys_hps_f2sdram_adapter_axi4_sub_awready,                                         //                                                                              .awready
		output wire [255:0] subsys_hps_f2sdram_adapter_axi4_sub_wdata,                                           //                                                                              .wdata
		output wire [31:0]  subsys_hps_f2sdram_adapter_axi4_sub_wstrb,                                           //                                                                              .wstrb
		output wire         subsys_hps_f2sdram_adapter_axi4_sub_wlast,                                           //                                                                              .wlast
		output wire         subsys_hps_f2sdram_adapter_axi4_sub_wvalid,                                          //                                                                              .wvalid
		output wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_wuser,                                           //                                                                              .wuser
		input  wire         subsys_hps_f2sdram_adapter_axi4_sub_wready,                                          //                                                                              .wready
		input  wire [4:0]   subsys_hps_f2sdram_adapter_axi4_sub_bid,                                             //                                                                              .bid
		input  wire [1:0]   subsys_hps_f2sdram_adapter_axi4_sub_bresp,                                           //                                                                              .bresp
		input  wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_buser,                                           //                                                                              .buser
		input  wire         subsys_hps_f2sdram_adapter_axi4_sub_bvalid,                                          //                                                                              .bvalid
		output wire         subsys_hps_f2sdram_adapter_axi4_sub_bready,                                          //                                                                              .bready
		output wire [4:0]   subsys_hps_f2sdram_adapter_axi4_sub_arid,                                            //                                                                              .arid
		output wire [31:0]  subsys_hps_f2sdram_adapter_axi4_sub_araddr,                                          //                                                                              .araddr
		output wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_arlen,                                           //                                                                              .arlen
		output wire [2:0]   subsys_hps_f2sdram_adapter_axi4_sub_arsize,                                          //                                                                              .arsize
		output wire [1:0]   subsys_hps_f2sdram_adapter_axi4_sub_arburst,                                         //                                                                              .arburst
		output wire [0:0]   subsys_hps_f2sdram_adapter_axi4_sub_arlock,                                          //                                                                              .arlock
		output wire [3:0]   subsys_hps_f2sdram_adapter_axi4_sub_arcache,                                         //                                                                              .arcache
		output wire [2:0]   subsys_hps_f2sdram_adapter_axi4_sub_arprot,                                          //                                                                              .arprot
		output wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_aruser,                                          //                                                                              .aruser
		output wire [3:0]   subsys_hps_f2sdram_adapter_axi4_sub_arqos,                                           //                                                                              .arqos
		output wire [3:0]   subsys_hps_f2sdram_adapter_axi4_sub_arregion,                                        //                                                                              .arregion
		output wire         subsys_hps_f2sdram_adapter_axi4_sub_arvalid,                                         //                                                                              .arvalid
		input  wire         subsys_hps_f2sdram_adapter_axi4_sub_arready,                                         //                                                                              .arready
		input  wire [4:0]   subsys_hps_f2sdram_adapter_axi4_sub_rid,                                             //                                                                              .rid
		input  wire [255:0] subsys_hps_f2sdram_adapter_axi4_sub_rdata,                                           //                                                                              .rdata
		input  wire [1:0]   subsys_hps_f2sdram_adapter_axi4_sub_rresp,                                           //                                                                              .rresp
		input  wire         subsys_hps_f2sdram_adapter_axi4_sub_rlast,                                           //                                                                              .rlast
		input  wire         subsys_hps_f2sdram_adapter_axi4_sub_rvalid,                                          //                                                                              .rvalid
		output wire         subsys_hps_f2sdram_adapter_axi4_sub_rready,                                          //                                                                              .rready
		input  wire [7:0]   subsys_hps_f2sdram_adapter_axi4_sub_ruser,                                           //                                                                              .ruser
		input  wire         ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset,                            //                            ext_hps_f2sdram_master_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire         ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset, // ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire         clk_100_out_clk_clk                                                                  //                                                               clk_100_out_clk.clk,          Clock Input
	);

	wire          ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_waitrequest;   // ext_hps_f2sdram_master_expanded_master_agent:av_waitrequest -> ext_hps_f2sdram_master_expanded_master_translator:uav_waitrequest
	wire   [31:0] ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_readdata;      // ext_hps_f2sdram_master_expanded_master_agent:av_readdata -> ext_hps_f2sdram_master_expanded_master_translator:uav_readdata
	wire          ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_debugaccess;   // ext_hps_f2sdram_master_expanded_master_translator:uav_debugaccess -> ext_hps_f2sdram_master_expanded_master_agent:av_debugaccess
	wire   [32:0] ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_address;       // ext_hps_f2sdram_master_expanded_master_translator:uav_address -> ext_hps_f2sdram_master_expanded_master_agent:av_address
	wire          ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_read;          // ext_hps_f2sdram_master_expanded_master_translator:uav_read -> ext_hps_f2sdram_master_expanded_master_agent:av_read
	wire    [3:0] ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_byteenable;    // ext_hps_f2sdram_master_expanded_master_translator:uav_byteenable -> ext_hps_f2sdram_master_expanded_master_agent:av_byteenable
	wire          ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_readdatavalid; // ext_hps_f2sdram_master_expanded_master_agent:av_readdatavalid -> ext_hps_f2sdram_master_expanded_master_translator:uav_readdatavalid
	wire          ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_lock;          // ext_hps_f2sdram_master_expanded_master_translator:uav_lock -> ext_hps_f2sdram_master_expanded_master_agent:av_lock
	wire          ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_write;         // ext_hps_f2sdram_master_expanded_master_translator:uav_write -> ext_hps_f2sdram_master_expanded_master_agent:av_write
	wire   [31:0] ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_writedata;     // ext_hps_f2sdram_master_expanded_master_translator:uav_writedata -> ext_hps_f2sdram_master_expanded_master_agent:av_writedata
	wire    [2:0] ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_burstcount;    // ext_hps_f2sdram_master_expanded_master_translator:uav_burstcount -> ext_hps_f2sdram_master_expanded_master_agent:av_burstcount
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_ruser;                         // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_ruser -> subsys_hps_f2sdram_adapter_axi4_sub_agent:ruser
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wuser;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:wuser -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_wuser
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awburst;                       // subsys_hps_f2sdram_adapter_axi4_sub_agent:awburst -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awburst
	wire    [3:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arregion;                      // subsys_hps_f2sdram_adapter_axi4_sub_agent:arregion -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arregion
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awuser;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:awuser -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awuser
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arlen;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:arlen -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arlen
	wire    [3:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arqos;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:arqos -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arqos
	wire   [31:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wstrb;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:wstrb -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_wstrb
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wready;                        // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_wready -> subsys_hps_f2sdram_adapter_axi4_sub_agent:wready
	wire    [0:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rid;                           // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_rid -> subsys_hps_f2sdram_adapter_axi4_sub_agent:rid
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rready;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:rready -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_rready
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awlen;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:awlen -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awlen
	wire    [3:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awqos;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:awqos -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awqos
	wire    [3:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arcache;                       // subsys_hps_f2sdram_adapter_axi4_sub_agent:arcache -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arcache
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wvalid;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:wvalid -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_wvalid
	wire   [32:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_araddr;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:araddr -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_araddr
	wire    [2:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arprot;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:arprot -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arprot
	wire    [2:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awprot;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:awprot -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awprot
	wire  [255:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wdata;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:wdata -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_wdata
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arvalid;                       // subsys_hps_f2sdram_adapter_axi4_sub_agent:arvalid -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arvalid
	wire    [3:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awcache;                       // subsys_hps_f2sdram_adapter_axi4_sub_agent:awcache -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awcache
	wire    [0:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arid;                          // subsys_hps_f2sdram_adapter_axi4_sub_agent:arid -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arid
	wire    [0:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arlock;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:arlock -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arlock
	wire    [0:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awlock;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:awlock -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awlock
	wire   [32:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awaddr;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:awaddr -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awaddr
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bresp;                         // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_bresp -> subsys_hps_f2sdram_adapter_axi4_sub_agent:bresp
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arready;                       // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arready -> subsys_hps_f2sdram_adapter_axi4_sub_agent:arready
	wire  [255:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rdata;                         // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_rdata -> subsys_hps_f2sdram_adapter_axi4_sub_agent:rdata
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awready;                       // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awready -> subsys_hps_f2sdram_adapter_axi4_sub_agent:awready
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arburst;                       // subsys_hps_f2sdram_adapter_axi4_sub_agent:arburst -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arburst
	wire    [2:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arsize;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:arsize -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_arsize
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bready;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:bready -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_bready
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rlast;                         // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_rlast -> subsys_hps_f2sdram_adapter_axi4_sub_agent:rlast
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wlast;                         // subsys_hps_f2sdram_adapter_axi4_sub_agent:wlast -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_wlast
	wire    [3:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awregion;                      // subsys_hps_f2sdram_adapter_axi4_sub_agent:awregion -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awregion
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_buser;                         // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_buser -> subsys_hps_f2sdram_adapter_axi4_sub_agent:buser
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rresp;                         // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_rresp -> subsys_hps_f2sdram_adapter_axi4_sub_agent:rresp
	wire    [0:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awid;                          // subsys_hps_f2sdram_adapter_axi4_sub_agent:awid -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awid
	wire    [0:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bid;                           // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_bid -> subsys_hps_f2sdram_adapter_axi4_sub_agent:bid
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bvalid;                        // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_bvalid -> subsys_hps_f2sdram_adapter_axi4_sub_agent:bvalid
	wire    [2:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awsize;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:awsize -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awsize
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awvalid;                       // subsys_hps_f2sdram_adapter_axi4_sub_agent:awvalid -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_awvalid
	wire    [7:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_aruser;                        // subsys_hps_f2sdram_adapter_axi4_sub_agent:aruser -> subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_aruser
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rvalid;                        // subsys_hps_f2sdram_adapter_axi4_sub_translator:s0_rvalid -> subsys_hps_f2sdram_adapter_axi4_sub_agent:rvalid
	wire          ext_hps_f2sdram_master_expanded_master_agent_cp_valid;                                     // ext_hps_f2sdram_master_expanded_master_agent:cp_valid -> router:sink_valid
	wire  [163:0] ext_hps_f2sdram_master_expanded_master_agent_cp_data;                                      // ext_hps_f2sdram_master_expanded_master_agent:cp_data -> router:sink_data
	wire          ext_hps_f2sdram_master_expanded_master_agent_cp_ready;                                     // router:sink_ready -> ext_hps_f2sdram_master_expanded_master_agent:cp_ready
	wire          ext_hps_f2sdram_master_expanded_master_agent_cp_startofpacket;                             // ext_hps_f2sdram_master_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          ext_hps_f2sdram_master_expanded_master_agent_cp_endofpacket;                               // ext_hps_f2sdram_master_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          router_src_valid;                                                                          // router:src_valid -> ext_hps_f2sdram_master_expanded_master_limiter:cmd_sink_valid
	wire  [163:0] router_src_data;                                                                           // router:src_data -> ext_hps_f2sdram_master_expanded_master_limiter:cmd_sink_data
	wire          router_src_ready;                                                                          // ext_hps_f2sdram_master_expanded_master_limiter:cmd_sink_ready -> router:src_ready
	wire    [1:0] router_src_channel;                                                                        // router:src_channel -> ext_hps_f2sdram_master_expanded_master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                                  // router:src_startofpacket -> ext_hps_f2sdram_master_expanded_master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                                    // router:src_endofpacket -> ext_hps_f2sdram_master_expanded_master_limiter:cmd_sink_endofpacket
	wire          ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_valid;                              // ext_hps_f2sdram_master_expanded_master_limiter:rsp_src_valid -> ext_hps_f2sdram_master_expanded_master_agent:rp_valid
	wire  [163:0] ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_data;                               // ext_hps_f2sdram_master_expanded_master_limiter:rsp_src_data -> ext_hps_f2sdram_master_expanded_master_agent:rp_data
	wire          ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_ready;                              // ext_hps_f2sdram_master_expanded_master_agent:rp_ready -> ext_hps_f2sdram_master_expanded_master_limiter:rsp_src_ready
	wire    [1:0] ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_channel;                            // ext_hps_f2sdram_master_expanded_master_limiter:rsp_src_channel -> ext_hps_f2sdram_master_expanded_master_agent:rp_channel
	wire          ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_startofpacket;                      // ext_hps_f2sdram_master_expanded_master_limiter:rsp_src_startofpacket -> ext_hps_f2sdram_master_expanded_master_agent:rp_startofpacket
	wire          ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_endofpacket;                        // ext_hps_f2sdram_master_expanded_master_limiter:rsp_src_endofpacket -> ext_hps_f2sdram_master_expanded_master_agent:rp_endofpacket
	wire          cmd_mux_src_valid;                                                                         // cmd_mux:src_valid -> subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:in_valid
	wire  [163:0] cmd_mux_src_data;                                                                          // cmd_mux:src_data -> subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:in_data
	wire          cmd_mux_src_ready;                                                                         // subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:in_ready -> cmd_mux:src_ready
	wire    [1:0] cmd_mux_src_channel;                                                                       // cmd_mux:src_channel -> subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:in_channel
	wire          cmd_mux_src_startofpacket;                                                                 // cmd_mux:src_startofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                                   // cmd_mux:src_endofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:in_endofpacket
	wire          cmd_mux_001_src_valid;                                                                     // cmd_mux_001:src_valid -> subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:in_valid
	wire  [163:0] cmd_mux_001_src_data;                                                                      // cmd_mux_001:src_data -> subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:in_data
	wire          cmd_mux_001_src_ready;                                                                     // subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
	wire    [1:0] cmd_mux_001_src_channel;                                                                   // cmd_mux_001:src_channel -> subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:in_channel
	wire          cmd_mux_001_src_startofpacket;                                                             // cmd_mux_001:src_startofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                               // cmd_mux_001:src_endofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:in_endofpacket
	wire          router_001_src_valid;                                                                      // router_001:src_valid -> subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:in_valid
	wire  [415:0] router_001_src_data;                                                                       // router_001:src_data -> subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:in_data
	wire          router_001_src_ready;                                                                      // subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:in_ready -> router_001:src_ready
	wire    [1:0] router_001_src_channel;                                                                    // router_001:src_channel -> subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:in_channel
	wire          router_001_src_startofpacket;                                                              // router_001:src_startofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:in_startofpacket
	wire          router_001_src_endofpacket;                                                                // router_001:src_endofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:in_endofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_valid;                        // subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
	wire  [163:0] subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_data;                         // subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:out_data -> rsp_demux:sink_data
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_ready;                        // rsp_demux:sink_ready -> subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:out_ready
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_channel;                      // subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_startofpacket;                // subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_endofpacket;                  // subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
	wire          router_002_src_valid;                                                                      // router_002:src_valid -> subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:in_valid
	wire  [415:0] router_002_src_data;                                                                       // router_002:src_data -> subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:in_data
	wire          router_002_src_ready;                                                                      // subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:in_ready -> router_002:src_ready
	wire    [1:0] router_002_src_channel;                                                                    // router_002:src_channel -> subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:in_channel
	wire          router_002_src_startofpacket;                                                              // router_002:src_startofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:in_startofpacket
	wire          router_002_src_endofpacket;                                                                // router_002:src_endofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:in_endofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_valid;                        // subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
	wire  [163:0] subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_data;                         // subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_ready;                        // rsp_demux_001:sink_ready -> subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:out_ready
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_channel;                      // subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_startofpacket;                // subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_endofpacket;                  // subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
	wire    [0:0] ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_valid;                              // ext_hps_f2sdram_master_expanded_master_limiter:cmd_src_valid -> limiter_pipeline:in_valid
	wire  [163:0] ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_data;                               // ext_hps_f2sdram_master_expanded_master_limiter:cmd_src_data -> limiter_pipeline:in_data
	wire          ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_ready;                              // limiter_pipeline:in_ready -> ext_hps_f2sdram_master_expanded_master_limiter:cmd_src_ready
	wire    [1:0] ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_channel;                            // ext_hps_f2sdram_master_expanded_master_limiter:cmd_src_channel -> limiter_pipeline:in_channel
	wire          ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_startofpacket;                      // ext_hps_f2sdram_master_expanded_master_limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
	wire          ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_endofpacket;                        // ext_hps_f2sdram_master_expanded_master_limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
	wire          limiter_pipeline_source0_valid;                                                            // limiter_pipeline:out_valid -> cmd_demux:sink_valid
	wire  [163:0] limiter_pipeline_source0_data;                                                             // limiter_pipeline:out_data -> cmd_demux:sink_data
	wire          limiter_pipeline_source0_ready;                                                            // cmd_demux:sink_ready -> limiter_pipeline:out_ready
	wire    [1:0] limiter_pipeline_source0_channel;                                                          // limiter_pipeline:out_channel -> cmd_demux:sink_channel
	wire          limiter_pipeline_source0_startofpacket;                                                    // limiter_pipeline:out_startofpacket -> cmd_demux:sink_startofpacket
	wire          limiter_pipeline_source0_endofpacket;                                                      // limiter_pipeline:out_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                                         // rsp_mux:src_valid -> limiter_pipeline_001:in_valid
	wire  [163:0] rsp_mux_src_data;                                                                          // rsp_mux:src_data -> limiter_pipeline_001:in_data
	wire          rsp_mux_src_ready;                                                                         // limiter_pipeline_001:in_ready -> rsp_mux:src_ready
	wire    [1:0] rsp_mux_src_channel;                                                                       // rsp_mux:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_mux_src_startofpacket;                                                                 // rsp_mux:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire          rsp_mux_src_endofpacket;                                                                   // rsp_mux:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                                        // limiter_pipeline_001:out_valid -> ext_hps_f2sdram_master_expanded_master_limiter:rsp_sink_valid
	wire  [163:0] limiter_pipeline_001_source0_data;                                                         // limiter_pipeline_001:out_data -> ext_hps_f2sdram_master_expanded_master_limiter:rsp_sink_data
	wire          limiter_pipeline_001_source0_ready;                                                        // ext_hps_f2sdram_master_expanded_master_limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire    [1:0] limiter_pipeline_001_source0_channel;                                                      // limiter_pipeline_001:out_channel -> ext_hps_f2sdram_master_expanded_master_limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_startofpacket;                                                // limiter_pipeline_001:out_startofpacket -> ext_hps_f2sdram_master_expanded_master_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_001_source0_endofpacket;                                                  // limiter_pipeline_001:out_endofpacket -> ext_hps_f2sdram_master_expanded_master_limiter:rsp_sink_endofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_valid;                        // subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:out_valid -> agent_pipeline:in_valid
	wire  [415:0] subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_data;                         // subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:out_data -> agent_pipeline:in_data
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_ready;                        // agent_pipeline:in_ready -> subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:out_ready
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_channel;                      // subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:out_channel -> agent_pipeline:in_channel
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_startofpacket;                // subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:out_startofpacket -> agent_pipeline:in_startofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_endofpacket;                  // subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter:out_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                                              // agent_pipeline:out_valid -> subsys_hps_f2sdram_adapter_axi4_sub_agent:write_cp_valid
	wire  [415:0] agent_pipeline_source0_data;                                                               // agent_pipeline:out_data -> subsys_hps_f2sdram_adapter_axi4_sub_agent:write_cp_data
	wire          agent_pipeline_source0_ready;                                                              // subsys_hps_f2sdram_adapter_axi4_sub_agent:write_cp_ready -> agent_pipeline:out_ready
	wire    [1:0] agent_pipeline_source0_channel;                                                            // agent_pipeline:out_channel -> subsys_hps_f2sdram_adapter_axi4_sub_agent:write_cp_channel
	wire          agent_pipeline_source0_startofpacket;                                                      // agent_pipeline:out_startofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_agent:write_cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                                                        // agent_pipeline:out_endofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_agent:write_cp_endofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_valid;                        // subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:out_valid -> agent_pipeline_001:in_valid
	wire  [415:0] subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_data;                         // subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:out_data -> agent_pipeline_001:in_data
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_ready;                        // agent_pipeline_001:in_ready -> subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:out_ready
	wire    [1:0] subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_channel;                      // subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:out_channel -> agent_pipeline_001:in_channel
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_startofpacket;                // subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:out_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_endofpacket;                  // subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter:out_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                                                          // agent_pipeline_001:out_valid -> subsys_hps_f2sdram_adapter_axi4_sub_agent:read_cp_valid
	wire  [415:0] agent_pipeline_001_source0_data;                                                           // agent_pipeline_001:out_data -> subsys_hps_f2sdram_adapter_axi4_sub_agent:read_cp_data
	wire          agent_pipeline_001_source0_ready;                                                          // subsys_hps_f2sdram_adapter_axi4_sub_agent:read_cp_ready -> agent_pipeline_001:out_ready
	wire    [1:0] agent_pipeline_001_source0_channel;                                                        // agent_pipeline_001:out_channel -> subsys_hps_f2sdram_adapter_axi4_sub_agent:read_cp_channel
	wire          agent_pipeline_001_source0_startofpacket;                                                  // agent_pipeline_001:out_startofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_agent:read_cp_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                                                    // agent_pipeline_001:out_endofpacket -> subsys_hps_f2sdram_adapter_axi4_sub_agent:read_cp_endofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_valid;                                  // subsys_hps_f2sdram_adapter_axi4_sub_agent:write_rp_valid -> agent_pipeline_002:in_valid
	wire  [415:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_data;                                   // subsys_hps_f2sdram_adapter_axi4_sub_agent:write_rp_data -> agent_pipeline_002:in_data
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_ready;                                  // agent_pipeline_002:in_ready -> subsys_hps_f2sdram_adapter_axi4_sub_agent:write_rp_ready
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_startofpacket;                          // subsys_hps_f2sdram_adapter_axi4_sub_agent:write_rp_startofpacket -> agent_pipeline_002:in_startofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_endofpacket;                            // subsys_hps_f2sdram_adapter_axi4_sub_agent:write_rp_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          agent_pipeline_002_source0_valid;                                                          // agent_pipeline_002:out_valid -> router_001:sink_valid
	wire  [415:0] agent_pipeline_002_source0_data;                                                           // agent_pipeline_002:out_data -> router_001:sink_data
	wire          agent_pipeline_002_source0_ready;                                                          // router_001:sink_ready -> agent_pipeline_002:out_ready
	wire          agent_pipeline_002_source0_startofpacket;                                                  // agent_pipeline_002:out_startofpacket -> router_001:sink_startofpacket
	wire          agent_pipeline_002_source0_endofpacket;                                                    // agent_pipeline_002:out_endofpacket -> router_001:sink_endofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_valid;                                   // subsys_hps_f2sdram_adapter_axi4_sub_agent:read_rp_valid -> agent_pipeline_003:in_valid
	wire  [415:0] subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_data;                                    // subsys_hps_f2sdram_adapter_axi4_sub_agent:read_rp_data -> agent_pipeline_003:in_data
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_ready;                                   // agent_pipeline_003:in_ready -> subsys_hps_f2sdram_adapter_axi4_sub_agent:read_rp_ready
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_startofpacket;                           // subsys_hps_f2sdram_adapter_axi4_sub_agent:read_rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire          subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_endofpacket;                             // subsys_hps_f2sdram_adapter_axi4_sub_agent:read_rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          agent_pipeline_003_source0_valid;                                                          // agent_pipeline_003:out_valid -> router_002:sink_valid
	wire  [415:0] agent_pipeline_003_source0_data;                                                           // agent_pipeline_003:out_data -> router_002:sink_data
	wire          agent_pipeline_003_source0_ready;                                                          // router_002:sink_ready -> agent_pipeline_003:out_ready
	wire          agent_pipeline_003_source0_startofpacket;                                                  // agent_pipeline_003:out_startofpacket -> router_002:sink_startofpacket
	wire          agent_pipeline_003_source0_endofpacket;                                                    // agent_pipeline_003:out_endofpacket -> router_002:sink_endofpacket
	wire          cmd_demux_src0_valid;                                                                      // cmd_demux:src0_valid -> mux_pipeline:in_valid
	wire  [163:0] cmd_demux_src0_data;                                                                       // cmd_demux:src0_data -> mux_pipeline:in_data
	wire          cmd_demux_src0_ready;                                                                      // mux_pipeline:in_ready -> cmd_demux:src0_ready
	wire    [1:0] cmd_demux_src0_channel;                                                                    // cmd_demux:src0_channel -> mux_pipeline:in_channel
	wire          cmd_demux_src0_startofpacket;                                                              // cmd_demux:src0_startofpacket -> mux_pipeline:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                                // cmd_demux:src0_endofpacket -> mux_pipeline:in_endofpacket
	wire          mux_pipeline_source0_valid;                                                                // mux_pipeline:out_valid -> cmd_mux:sink0_valid
	wire  [163:0] mux_pipeline_source0_data;                                                                 // mux_pipeline:out_data -> cmd_mux:sink0_data
	wire          mux_pipeline_source0_ready;                                                                // cmd_mux:sink0_ready -> mux_pipeline:out_ready
	wire    [1:0] mux_pipeline_source0_channel;                                                              // mux_pipeline:out_channel -> cmd_mux:sink0_channel
	wire          mux_pipeline_source0_startofpacket;                                                        // mux_pipeline:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          mux_pipeline_source0_endofpacket;                                                          // mux_pipeline:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_src1_valid;                                                                      // cmd_demux:src1_valid -> mux_pipeline_001:in_valid
	wire  [163:0] cmd_demux_src1_data;                                                                       // cmd_demux:src1_data -> mux_pipeline_001:in_data
	wire          cmd_demux_src1_ready;                                                                      // mux_pipeline_001:in_ready -> cmd_demux:src1_ready
	wire    [1:0] cmd_demux_src1_channel;                                                                    // cmd_demux:src1_channel -> mux_pipeline_001:in_channel
	wire          cmd_demux_src1_startofpacket;                                                              // cmd_demux:src1_startofpacket -> mux_pipeline_001:in_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                                // cmd_demux:src1_endofpacket -> mux_pipeline_001:in_endofpacket
	wire          mux_pipeline_001_source0_valid;                                                            // mux_pipeline_001:out_valid -> cmd_mux_001:sink0_valid
	wire  [163:0] mux_pipeline_001_source0_data;                                                             // mux_pipeline_001:out_data -> cmd_mux_001:sink0_data
	wire          mux_pipeline_001_source0_ready;                                                            // cmd_mux_001:sink0_ready -> mux_pipeline_001:out_ready
	wire    [1:0] mux_pipeline_001_source0_channel;                                                          // mux_pipeline_001:out_channel -> cmd_mux_001:sink0_channel
	wire          mux_pipeline_001_source0_startofpacket;                                                    // mux_pipeline_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          mux_pipeline_001_source0_endofpacket;                                                      // mux_pipeline_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          rsp_demux_src0_valid;                                                                      // rsp_demux:src0_valid -> mux_pipeline_002:in_valid
	wire  [163:0] rsp_demux_src0_data;                                                                       // rsp_demux:src0_data -> mux_pipeline_002:in_data
	wire          rsp_demux_src0_ready;                                                                      // mux_pipeline_002:in_ready -> rsp_demux:src0_ready
	wire    [1:0] rsp_demux_src0_channel;                                                                    // rsp_demux:src0_channel -> mux_pipeline_002:in_channel
	wire          rsp_demux_src0_startofpacket;                                                              // rsp_demux:src0_startofpacket -> mux_pipeline_002:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                                // rsp_demux:src0_endofpacket -> mux_pipeline_002:in_endofpacket
	wire          mux_pipeline_002_source0_valid;                                                            // mux_pipeline_002:out_valid -> rsp_mux:sink0_valid
	wire  [163:0] mux_pipeline_002_source0_data;                                                             // mux_pipeline_002:out_data -> rsp_mux:sink0_data
	wire          mux_pipeline_002_source0_ready;                                                            // rsp_mux:sink0_ready -> mux_pipeline_002:out_ready
	wire    [1:0] mux_pipeline_002_source0_channel;                                                          // mux_pipeline_002:out_channel -> rsp_mux:sink0_channel
	wire          mux_pipeline_002_source0_startofpacket;                                                    // mux_pipeline_002:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          mux_pipeline_002_source0_endofpacket;                                                      // mux_pipeline_002:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          rsp_demux_001_src0_valid;                                                                  // rsp_demux_001:src0_valid -> mux_pipeline_003:in_valid
	wire  [163:0] rsp_demux_001_src0_data;                                                                   // rsp_demux_001:src0_data -> mux_pipeline_003:in_data
	wire          rsp_demux_001_src0_ready;                                                                  // mux_pipeline_003:in_ready -> rsp_demux_001:src0_ready
	wire    [1:0] rsp_demux_001_src0_channel;                                                                // rsp_demux_001:src0_channel -> mux_pipeline_003:in_channel
	wire          rsp_demux_001_src0_startofpacket;                                                          // rsp_demux_001:src0_startofpacket -> mux_pipeline_003:in_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                            // rsp_demux_001:src0_endofpacket -> mux_pipeline_003:in_endofpacket
	wire          mux_pipeline_003_source0_valid;                                                            // mux_pipeline_003:out_valid -> rsp_mux:sink1_valid
	wire  [163:0] mux_pipeline_003_source0_data;                                                             // mux_pipeline_003:out_data -> rsp_mux:sink1_data
	wire          mux_pipeline_003_source0_ready;                                                            // rsp_mux:sink1_ready -> mux_pipeline_003:out_ready
	wire    [1:0] mux_pipeline_003_source0_channel;                                                          // mux_pipeline_003:out_channel -> rsp_mux:sink1_channel
	wire          mux_pipeline_003_source0_startofpacket;                                                    // mux_pipeline_003:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire          mux_pipeline_003_source0_endofpacket;                                                      // mux_pipeline_003:out_endofpacket -> rsp_mux:sink1_endofpacket

	qsys_top_altera_merlin_master_translator_192_lykd4la #(
		.AV_ADDRESS_W                (33),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (33),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (1),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) ext_hps_f2sdram_master_expanded_master_translator (
		.clk                    (clk_100_out_clk_clk),                                                                       //   input,   width = 1,                       clk.clk
		.reset                  (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset),       //   input,   width = 1,                     reset.reset
		.uav_address            (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_address),       //  output,  width = 33, avalon_universal_master_0.address
		.uav_burstcount         (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (ext_hps_f2sdram_master_expanded_master_address),                                            //   input,  width = 33,      avalon_anti_master_0.address
		.av_waitrequest         (ext_hps_f2sdram_master_expanded_master_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_burstcount          (ext_hps_f2sdram_master_expanded_master_burstcount),                                         //   input,   width = 1,                          .burstcount
		.av_byteenable          (ext_hps_f2sdram_master_expanded_master_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (ext_hps_f2sdram_master_expanded_master_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (ext_hps_f2sdram_master_expanded_master_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (ext_hps_f2sdram_master_expanded_master_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (ext_hps_f2sdram_master_expanded_master_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (ext_hps_f2sdram_master_expanded_master_writedata),                                          //   input,  width = 32,                          .writedata
		.av_beginbursttransfer  (1'b0),                                                                                      // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                                      // (terminated),                                        
		.av_chipselect          (1'b0),                                                                                      // (terminated),                                        
		.av_lock                (1'b0),                                                                                      // (terminated),                                        
		.av_debugaccess         (1'b0),                                                                                      // (terminated),                                        
		.uav_outputenable       (1'b0),                                                                                      // (terminated),                                        
		.uav_clken              (),                                                                                          // (terminated),                                        
		.av_clken               (1'b1),                                                                                      // (terminated),                                        
		.uav_response           (2'b00),                                                                                     // (terminated),                                        
		.av_response            (),                                                                                          // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                                      // (terminated),                                        
		.av_writeresponsevalid  ()                                                                                           // (terminated),                                        
	);

	qsys_top_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (1),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (1),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (1),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (1),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (5),
		.DATA_WIDTH                        (256),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (1),
		.M0_ADDR_WIDTH                     (32),
		.S0_WRITE_ADDR_USER_WIDTH          (8),
		.S0_READ_ADDR_USER_WIDTH           (8),
		.M0_WRITE_ADDR_USER_WIDTH          (8),
		.M0_READ_ADDR_USER_WIDTH           (8),
		.S0_WRITE_DATA_USER_WIDTH          (8),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (8),
		.S0_READ_DATA_USER_WIDTH           (8),
		.M0_WRITE_DATA_USER_WIDTH          (8),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (8),
		.M0_READ_DATA_USER_WIDTH           (8),
		.S0_ADDR_WIDTH                     (33),
		.USE_S0_AWUSER                     (1),
		.USE_S0_ARUSER                     (1),
		.USE_S0_WUSER                      (1),
		.USE_S0_RUSER                      (1),
		.USE_S0_BUSER                      (1),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) subsys_hps_f2sdram_adapter_axi4_sub_translator (
		.aclk              (clk_100_out_clk_clk),                                                                  //   input,    width = 1,       clk.clk
		.aresetn           (~ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset_n
		.m0_awid           (subsys_hps_f2sdram_adapter_axi4_sub_awid),                                             //  output,    width = 5,        m0.awid
		.m0_awaddr         (subsys_hps_f2sdram_adapter_axi4_sub_awaddr),                                           //  output,   width = 32,          .awaddr
		.m0_awlen          (subsys_hps_f2sdram_adapter_axi4_sub_awlen),                                            //  output,    width = 8,          .awlen
		.m0_awsize         (subsys_hps_f2sdram_adapter_axi4_sub_awsize),                                           //  output,    width = 3,          .awsize
		.m0_awburst        (subsys_hps_f2sdram_adapter_axi4_sub_awburst),                                          //  output,    width = 2,          .awburst
		.m0_awlock         (subsys_hps_f2sdram_adapter_axi4_sub_awlock),                                           //  output,    width = 1,          .awlock
		.m0_awcache        (subsys_hps_f2sdram_adapter_axi4_sub_awcache),                                          //  output,    width = 4,          .awcache
		.m0_awprot         (subsys_hps_f2sdram_adapter_axi4_sub_awprot),                                           //  output,    width = 3,          .awprot
		.m0_awuser         (subsys_hps_f2sdram_adapter_axi4_sub_awuser),                                           //  output,    width = 8,          .awuser
		.m0_awqos          (subsys_hps_f2sdram_adapter_axi4_sub_awqos),                                            //  output,    width = 4,          .awqos
		.m0_awregion       (subsys_hps_f2sdram_adapter_axi4_sub_awregion),                                         //  output,    width = 4,          .awregion
		.m0_awvalid        (subsys_hps_f2sdram_adapter_axi4_sub_awvalid),                                          //  output,    width = 1,          .awvalid
		.m0_awready        (subsys_hps_f2sdram_adapter_axi4_sub_awready),                                          //   input,    width = 1,          .awready
		.m0_wdata          (subsys_hps_f2sdram_adapter_axi4_sub_wdata),                                            //  output,  width = 256,          .wdata
		.m0_wstrb          (subsys_hps_f2sdram_adapter_axi4_sub_wstrb),                                            //  output,   width = 32,          .wstrb
		.m0_wlast          (subsys_hps_f2sdram_adapter_axi4_sub_wlast),                                            //  output,    width = 1,          .wlast
		.m0_wvalid         (subsys_hps_f2sdram_adapter_axi4_sub_wvalid),                                           //  output,    width = 1,          .wvalid
		.m0_wuser          (subsys_hps_f2sdram_adapter_axi4_sub_wuser),                                            //  output,    width = 8,          .wuser
		.m0_wready         (subsys_hps_f2sdram_adapter_axi4_sub_wready),                                           //   input,    width = 1,          .wready
		.m0_bid            (subsys_hps_f2sdram_adapter_axi4_sub_bid),                                              //   input,    width = 5,          .bid
		.m0_bresp          (subsys_hps_f2sdram_adapter_axi4_sub_bresp),                                            //   input,    width = 2,          .bresp
		.m0_buser          (subsys_hps_f2sdram_adapter_axi4_sub_buser),                                            //   input,    width = 8,          .buser
		.m0_bvalid         (subsys_hps_f2sdram_adapter_axi4_sub_bvalid),                                           //   input,    width = 1,          .bvalid
		.m0_bready         (subsys_hps_f2sdram_adapter_axi4_sub_bready),                                           //  output,    width = 1,          .bready
		.m0_arid           (subsys_hps_f2sdram_adapter_axi4_sub_arid),                                             //  output,    width = 5,          .arid
		.m0_araddr         (subsys_hps_f2sdram_adapter_axi4_sub_araddr),                                           //  output,   width = 32,          .araddr
		.m0_arlen          (subsys_hps_f2sdram_adapter_axi4_sub_arlen),                                            //  output,    width = 8,          .arlen
		.m0_arsize         (subsys_hps_f2sdram_adapter_axi4_sub_arsize),                                           //  output,    width = 3,          .arsize
		.m0_arburst        (subsys_hps_f2sdram_adapter_axi4_sub_arburst),                                          //  output,    width = 2,          .arburst
		.m0_arlock         (subsys_hps_f2sdram_adapter_axi4_sub_arlock),                                           //  output,    width = 1,          .arlock
		.m0_arcache        (subsys_hps_f2sdram_adapter_axi4_sub_arcache),                                          //  output,    width = 4,          .arcache
		.m0_arprot         (subsys_hps_f2sdram_adapter_axi4_sub_arprot),                                           //  output,    width = 3,          .arprot
		.m0_aruser         (subsys_hps_f2sdram_adapter_axi4_sub_aruser),                                           //  output,    width = 8,          .aruser
		.m0_arqos          (subsys_hps_f2sdram_adapter_axi4_sub_arqos),                                            //  output,    width = 4,          .arqos
		.m0_arregion       (subsys_hps_f2sdram_adapter_axi4_sub_arregion),                                         //  output,    width = 4,          .arregion
		.m0_arvalid        (subsys_hps_f2sdram_adapter_axi4_sub_arvalid),                                          //  output,    width = 1,          .arvalid
		.m0_arready        (subsys_hps_f2sdram_adapter_axi4_sub_arready),                                          //   input,    width = 1,          .arready
		.m0_rid            (subsys_hps_f2sdram_adapter_axi4_sub_rid),                                              //   input,    width = 5,          .rid
		.m0_rdata          (subsys_hps_f2sdram_adapter_axi4_sub_rdata),                                            //   input,  width = 256,          .rdata
		.m0_rresp          (subsys_hps_f2sdram_adapter_axi4_sub_rresp),                                            //   input,    width = 2,          .rresp
		.m0_rlast          (subsys_hps_f2sdram_adapter_axi4_sub_rlast),                                            //   input,    width = 1,          .rlast
		.m0_rvalid         (subsys_hps_f2sdram_adapter_axi4_sub_rvalid),                                           //   input,    width = 1,          .rvalid
		.m0_rready         (subsys_hps_f2sdram_adapter_axi4_sub_rready),                                           //  output,    width = 1,          .rready
		.m0_ruser          (subsys_hps_f2sdram_adapter_axi4_sub_ruser),                                            //   input,    width = 8,          .ruser
		.s0_awid           (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awid),                     //   input,    width = 1,        s0.awid
		.s0_awaddr         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awaddr),                   //   input,   width = 33,          .awaddr
		.s0_awlen          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awlen),                    //   input,    width = 8,          .awlen
		.s0_awsize         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awsize),                   //   input,    width = 3,          .awsize
		.s0_awburst        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awburst),                  //   input,    width = 2,          .awburst
		.s0_awlock         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awlock),                   //   input,    width = 1,          .awlock
		.s0_awcache        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awcache),                  //   input,    width = 4,          .awcache
		.s0_awprot         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awprot),                   //   input,    width = 3,          .awprot
		.s0_awuser         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awuser),                   //   input,    width = 8,          .awuser
		.s0_awqos          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awqos),                    //   input,    width = 4,          .awqos
		.s0_awregion       (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awregion),                 //   input,    width = 4,          .awregion
		.s0_awvalid        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awvalid),                  //   input,    width = 1,          .awvalid
		.s0_awready        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awready),                  //  output,    width = 1,          .awready
		.s0_wdata          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wdata),                    //   input,  width = 256,          .wdata
		.s0_wstrb          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wstrb),                    //   input,   width = 32,          .wstrb
		.s0_wlast          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wlast),                    //   input,    width = 1,          .wlast
		.s0_wvalid         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wvalid),                   //   input,    width = 1,          .wvalid
		.s0_wuser          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wuser),                    //   input,    width = 8,          .wuser
		.s0_wready         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wready),                   //  output,    width = 1,          .wready
		.s0_bid            (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bid),                      //  output,    width = 1,          .bid
		.s0_bresp          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bresp),                    //  output,    width = 2,          .bresp
		.s0_buser          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_buser),                    //  output,    width = 8,          .buser
		.s0_bvalid         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bvalid),                   //  output,    width = 1,          .bvalid
		.s0_bready         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bready),                   //   input,    width = 1,          .bready
		.s0_arid           (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arid),                     //   input,    width = 1,          .arid
		.s0_araddr         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_araddr),                   //   input,   width = 33,          .araddr
		.s0_arlen          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arlen),                    //   input,    width = 8,          .arlen
		.s0_arsize         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arsize),                   //   input,    width = 3,          .arsize
		.s0_arburst        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arburst),                  //   input,    width = 2,          .arburst
		.s0_arlock         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arlock),                   //   input,    width = 1,          .arlock
		.s0_arcache        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arcache),                  //   input,    width = 4,          .arcache
		.s0_arprot         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arprot),                   //   input,    width = 3,          .arprot
		.s0_aruser         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_aruser),                   //   input,    width = 8,          .aruser
		.s0_arqos          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arqos),                    //   input,    width = 4,          .arqos
		.s0_arregion       (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arregion),                 //   input,    width = 4,          .arregion
		.s0_arvalid        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arvalid),                  //   input,    width = 1,          .arvalid
		.s0_arready        (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arready),                  //  output,    width = 1,          .arready
		.s0_rid            (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rid),                      //  output,    width = 1,          .rid
		.s0_rdata          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rdata),                    //  output,  width = 256,          .rdata
		.s0_rresp          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rresp),                    //  output,    width = 2,          .rresp
		.s0_rlast          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rlast),                    //  output,    width = 1,          .rlast
		.s0_rvalid         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rvalid),                   //  output,    width = 1,          .rvalid
		.s0_rready         (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rready),                   //   input,    width = 1,          .rready
		.s0_ruser          (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_ruser),                    //  output,    width = 8,          .ruser
		.m0_awuser_addrchk (),                                                                                     // (terminated),                         
		.m0_awuser_sai     (),                                                                                     // (terminated),                         
		.m0_wuser_datachk  (),                                                                                     // (terminated),                         
		.m0_wuser_data     (),                                                                                     // (terminated),                         
		.m0_wuser_poison   (),                                                                                     // (terminated),                         
		.m0_aruser_addrchk (),                                                                                     // (terminated),                         
		.m0_aruser_sai     (),                                                                                     // (terminated),                         
		.m0_ruser_datachk  (32'b00000000000000000000000000000000),                                                 // (terminated),                         
		.m0_ruser_data     (4'b0000),                                                                              // (terminated),                         
		.m0_ruser_poison   (4'b0000),                                                                              // (terminated),                         
		.s0_awuser_addrchk (4'b0000),                                                                              // (terminated),                         
		.s0_awuser_sai     (4'b0000),                                                                              // (terminated),                         
		.s0_wuser_datachk  (32'b00000000000000000000000000000000),                                                 // (terminated),                         
		.s0_wuser_data     (4'b0000),                                                                              // (terminated),                         
		.s0_wuser_poison   (4'b0000),                                                                              // (terminated),                         
		.s0_aruser_addrchk (4'b0000),                                                                              // (terminated),                         
		.s0_aruser_sai     (4'b0000),                                                                              // (terminated),                         
		.s0_ruser_datachk  (),                                                                                     // (terminated),                         
		.s0_ruser_data     (),                                                                                     // (terminated),                         
		.s0_ruser_poison   (),                                                                                     // (terminated),                         
		.s0_wid            (1'b0),                                                                                 // (terminated),                         
		.s0_ardomain       (2'b00),                                                                                // (terminated),                         
		.s0_arsnoop        (4'b0000),                                                                              // (terminated),                         
		.s0_arbar          (2'b00),                                                                                // (terminated),                         
		.s0_awdomain       (2'b00),                                                                                // (terminated),                         
		.s0_awsnoop        (3'b000),                                                                               // (terminated),                         
		.s0_awbar          (2'b00),                                                                                // (terminated),                         
		.s0_awunique       (1'b0),                                                                                 // (terminated),                         
		.m0_wid            (),                                                                                     // (terminated),                         
		.m0_ardomain       (),                                                                                     // (terminated),                         
		.m0_arsnoop        (),                                                                                     // (terminated),                         
		.m0_arbar          (),                                                                                     // (terminated),                         
		.m0_awdomain       (),                                                                                     // (terminated),                         
		.m0_awsnoop        (),                                                                                     // (terminated),                         
		.m0_awbar          (),                                                                                     // (terminated),                         
		.m0_awunique       ()                                                                                      // (terminated),                         
	);

	qsys_top_altera_merlin_master_agent_1922_fy3n5ti #(
		.PKT_WUNIQUE               (148),
		.PKT_DOMAIN_H              (147),
		.PKT_DOMAIN_L              (146),
		.PKT_SNOOP_H               (145),
		.PKT_SNOOP_L               (142),
		.PKT_BARRIER_H             (141),
		.PKT_BARRIER_L             (140),
		.PKT_ORI_BURST_SIZE_H      (139),
		.PKT_ORI_BURST_SIZE_L      (137),
		.PKT_RESPONSE_STATUS_H     (136),
		.PKT_RESPONSE_STATUS_L     (135),
		.PKT_QOS_H                 (124),
		.PKT_QOS_L                 (121),
		.PKT_DATA_SIDEBAND_H       (119),
		.PKT_DATA_SIDEBAND_L       (112),
		.PKT_ADDR_SIDEBAND_H       (111),
		.PKT_ADDR_SIDEBAND_L       (104),
		.PKT_BURST_TYPE_H          (103),
		.PKT_BURST_TYPE_L          (102),
		.PKT_CACHE_H               (134),
		.PKT_CACHE_L               (131),
		.PKT_THREAD_ID_H           (127),
		.PKT_THREAD_ID_L           (127),
		.PKT_BURST_SIZE_H          (101),
		.PKT_BURST_SIZE_L          (99),
		.PKT_TRANS_EXCLUSIVE       (74),
		.PKT_TRANS_LOCK            (73),
		.PKT_BEGIN_BURST           (120),
		.PKT_PROTECTION_H          (130),
		.PKT_PROTECTION_L          (128),
		.PKT_BURSTWRAP_H           (98),
		.PKT_BURSTWRAP_L           (89),
		.PKT_BYTE_CNT_H            (88),
		.PKT_BYTE_CNT_L            (75),
		.PKT_ADDR_H                (68),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (69),
		.PKT_TRANS_POSTED          (70),
		.PKT_TRANS_WRITE           (71),
		.PKT_TRANS_READ            (72),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (125),
		.PKT_SRC_ID_L              (125),
		.PKT_DEST_ID_H             (126),
		.PKT_DEST_ID_L             (126),
		.PKT_POISON_H              (149),
		.PKT_POISON_L              (149),
		.PKT_DATACHK_H             (150),
		.PKT_DATACHK_L             (150),
		.PKT_ADDRCHK_H             (153),
		.PKT_ADDRCHK_L             (152),
		.PKT_SAI_H                 (154),
		.PKT_SAI_L                 (154),
		.PKT_USER_DATA_H           (151),
		.PKT_USER_DATA_L           (151),
		.ST_DATA_W                 (164),
		.ST_CHANNEL_W              (2),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (1023),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.ROLE_BASED_USER           (0)
	) ext_hps_f2sdram_master_expanded_master_agent (
		.clk                   (clk_100_out_clk_clk),                                                                       //   input,    width = 1,       clk.clk
		.reset                 (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset),       //   input,    width = 1, clk_reset.reset
		.av_address            (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_address),       //   input,   width = 33,        av.address
		.av_write              (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (ext_hps_f2sdram_master_expanded_master_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (ext_hps_f2sdram_master_expanded_master_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (ext_hps_f2sdram_master_expanded_master_agent_cp_data),                                      //  output,  width = 164,          .data
		.cp_startofpacket      (ext_hps_f2sdram_master_expanded_master_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (ext_hps_f2sdram_master_expanded_master_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (ext_hps_f2sdram_master_expanded_master_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_data),                               //   input,  width = 164,          .data
		.rp_channel            (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_channel),                            //   input,    width = 2,          .channel
		.rp_startofpacket      (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                                          // (terminated),                         
		.av_writeresponsevalid ()                                                                                           // (terminated),                         
	);

	qsys_top_altera_merlin_axi_slave_ni_1990_gahnivi #(
		.PKT_QOS_H                   (376),
		.PKT_QOS_L                   (373),
		.PKT_THREAD_ID_H             (379),
		.PKT_THREAD_ID_L             (379),
		.PKT_RESPONSE_STATUS_H       (388),
		.PKT_RESPONSE_STATUS_L       (387),
		.PKT_BEGIN_BURST             (372),
		.PKT_CACHE_H                 (386),
		.PKT_CACHE_L                 (383),
		.PKT_DATA_SIDEBAND_H         (371),
		.PKT_DATA_SIDEBAND_L         (364),
		.PKT_ADDR_SIDEBAND_H         (363),
		.PKT_ADDR_SIDEBAND_L         (356),
		.PKT_BURST_TYPE_H            (355),
		.PKT_BURST_TYPE_L            (354),
		.PKT_PROTECTION_H            (382),
		.PKT_PROTECTION_L            (380),
		.PKT_BURST_SIZE_H            (353),
		.PKT_BURST_SIZE_L            (351),
		.PKT_BURSTWRAP_H             (350),
		.PKT_BURSTWRAP_L             (341),
		.PKT_BYTE_CNT_H              (340),
		.PKT_BYTE_CNT_L              (327),
		.PKT_ADDR_H                  (320),
		.PKT_ADDR_L                  (288),
		.PKT_TRANS_EXCLUSIVE         (326),
		.PKT_TRANS_LOCK              (325),
		.PKT_TRANS_COMPRESSED_READ   (321),
		.PKT_TRANS_POSTED            (322),
		.PKT_TRANS_WRITE             (323),
		.PKT_TRANS_READ              (324),
		.PKT_DATA_H                  (255),
		.PKT_DATA_L                  (0),
		.PKT_BYTEEN_H                (287),
		.PKT_BYTEEN_L                (256),
		.PKT_SRC_ID_H                (377),
		.PKT_SRC_ID_L                (377),
		.PKT_DEST_ID_H               (378),
		.PKT_DEST_ID_L               (378),
		.PKT_ORI_BURST_SIZE_L        (389),
		.PKT_ORI_BURST_SIZE_H        (391),
		.PKT_DOMAIN_L                (398),
		.PKT_DOMAIN_H                (399),
		.PKT_SNOOP_L                 (394),
		.PKT_SNOOP_H                 (397),
		.PKT_BARRIER_L               (392),
		.PKT_BARRIER_H               (393),
		.PKT_WUNIQUE                 (400),
		.PKT_EOP_OOO                 (407),
		.PKT_SOP_OOO                 (408),
		.PKT_POISON_H                (401),
		.PKT_POISON_L                (401),
		.PKT_DATACHK_H               (402),
		.PKT_DATACHK_L               (402),
		.PKT_ADDRCHK_H               (405),
		.PKT_ADDRCHK_L               (404),
		.PKT_SAI_H                   (406),
		.PKT_SAI_L                   (406),
		.PKT_USER_DATA_H             (403),
		.PKT_USER_DATA_L             (403),
		.SAI_WIDTH                   (1),
		.ADDRCHK_WIDTH               (1),
		.USER_DATA_WIDTH             (1),
		.ADDR_USER_WIDTH             (8),
		.DATA_USER_WIDTH             (8),
		.ST_DATA_W                   (416),
		.ADDR_WIDTH                  (33),
		.RDATA_WIDTH                 (256),
		.WDATA_WIDTH                 (256),
		.ST_CHANNEL_W                (2),
		.AXI_SLAVE_ID_W              (1),
		.ACE_LITE_SUPPORT            (0),
		.PASS_ID_TO_SLAVE            (1),
		.AXI_VERSION                 ("AXI4"),
		.WRITE_ACCEPTANCE_CAPABILITY (1),
		.READ_ACCEPTANCE_CAPABILITY  (1),
		.USE_PKT_DATACHK             (0),
		.USE_PKT_ADDRCHK             (0),
		.SYNC_RESET                  (1),
		.USE_MEMORY_BLOCKS           (0),
		.ROLE_BASED_USER             (0),
		.ENABLE_OOO                  (0),
		.REORDER_BUFFER              (0)
	) subsys_hps_f2sdram_adapter_axi4_sub_agent (
		.aclk                   (clk_100_out_clk_clk),                                                                  //   input,    width = 1,        clock_sink.clk
		.aresetn                (~ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        reset_sink.reset_n
		.read_cp_valid          (agent_pipeline_001_source0_valid),                                                     //   input,    width = 1,           read_cp.valid
		.read_cp_ready          (agent_pipeline_001_source0_ready),                                                     //  output,    width = 1,                  .ready
		.read_cp_data           (agent_pipeline_001_source0_data),                                                      //   input,  width = 416,                  .data
		.read_cp_channel        (agent_pipeline_001_source0_channel),                                                   //   input,    width = 2,                  .channel
		.read_cp_startofpacket  (agent_pipeline_001_source0_startofpacket),                                             //   input,    width = 1,                  .startofpacket
		.read_cp_endofpacket    (agent_pipeline_001_source0_endofpacket),                                               //   input,    width = 1,                  .endofpacket
		.write_cp_ready         (agent_pipeline_source0_ready),                                                         //  output,    width = 1,          write_cp.ready
		.write_cp_valid         (agent_pipeline_source0_valid),                                                         //   input,    width = 1,                  .valid
		.write_cp_data          (agent_pipeline_source0_data),                                                          //   input,  width = 416,                  .data
		.write_cp_channel       (agent_pipeline_source0_channel),                                                       //   input,    width = 2,                  .channel
		.write_cp_startofpacket (agent_pipeline_source0_startofpacket),                                                 //   input,    width = 1,                  .startofpacket
		.write_cp_endofpacket   (agent_pipeline_source0_endofpacket),                                                   //   input,    width = 1,                  .endofpacket
		.read_rp_ready          (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_ready),                              //   input,    width = 1,           read_rp.ready
		.read_rp_valid          (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_valid),                              //  output,    width = 1,                  .valid
		.read_rp_data           (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_data),                               //  output,  width = 416,                  .data
		.read_rp_startofpacket  (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_startofpacket),                      //  output,    width = 1,                  .startofpacket
		.read_rp_endofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_endofpacket),                        //  output,    width = 1,                  .endofpacket
		.write_rp_ready         (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_ready),                             //   input,    width = 1,          write_rp.ready
		.write_rp_valid         (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_valid),                             //  output,    width = 1,                  .valid
		.write_rp_data          (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_data),                              //  output,  width = 416,                  .data
		.write_rp_startofpacket (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_startofpacket),                     //  output,    width = 1,                  .startofpacket
		.write_rp_endofpacket   (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_endofpacket),                       //  output,    width = 1,                  .endofpacket
		.awid                   (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awid),                     //  output,    width = 1, altera_axi_master.awid
		.awaddr                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awaddr),                   //  output,   width = 33,                  .awaddr
		.awlen                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awlen),                    //  output,    width = 8,                  .awlen
		.awsize                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awsize),                   //  output,    width = 3,                  .awsize
		.awburst                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awburst),                  //  output,    width = 2,                  .awburst
		.awlock                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awlock),                   //  output,    width = 1,                  .awlock
		.awcache                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awcache),                  //  output,    width = 4,                  .awcache
		.awprot                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awprot),                   //  output,    width = 3,                  .awprot
		.awuser                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awuser),                   //  output,    width = 8,                  .awuser
		.awvalid                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awvalid),                  //  output,    width = 1,                  .awvalid
		.awready                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awready),                  //   input,    width = 1,                  .awready
		.wdata                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wdata),                    //  output,  width = 256,                  .wdata
		.wstrb                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wstrb),                    //  output,   width = 32,                  .wstrb
		.wlast                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wlast),                    //  output,    width = 1,                  .wlast
		.wvalid                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wvalid),                   //  output,    width = 1,                  .wvalid
		.wready                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wready),                   //   input,    width = 1,                  .wready
		.bid                    (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bid),                      //   input,    width = 1,                  .bid
		.bresp                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bresp),                    //   input,    width = 2,                  .bresp
		.bvalid                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bvalid),                   //   input,    width = 1,                  .bvalid
		.bready                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_bready),                   //  output,    width = 1,                  .bready
		.arid                   (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arid),                     //  output,    width = 1,                  .arid
		.araddr                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_araddr),                   //  output,   width = 33,                  .araddr
		.arlen                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arlen),                    //  output,    width = 8,                  .arlen
		.arsize                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arsize),                   //  output,    width = 3,                  .arsize
		.arburst                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arburst),                  //  output,    width = 2,                  .arburst
		.arlock                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arlock),                   //  output,    width = 1,                  .arlock
		.arcache                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arcache),                  //  output,    width = 4,                  .arcache
		.arprot                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arprot),                   //  output,    width = 3,                  .arprot
		.aruser                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_aruser),                   //  output,    width = 8,                  .aruser
		.arvalid                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arvalid),                  //  output,    width = 1,                  .arvalid
		.arready                (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arready),                  //   input,    width = 1,                  .arready
		.rid                    (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rid),                      //   input,    width = 1,                  .rid
		.rdata                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rdata),                    //   input,  width = 256,                  .rdata
		.rresp                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rresp),                    //   input,    width = 2,                  .rresp
		.rlast                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rlast),                    //   input,    width = 1,                  .rlast
		.rvalid                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rvalid),                   //   input,    width = 1,                  .rvalid
		.rready                 (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_rready),                   //  output,    width = 1,                  .rready
		.wuser                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_wuser),                    //  output,    width = 8,                  .wuser
		.awqos                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awqos),                    //  output,    width = 4,                  .awqos
		.awregion               (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_awregion),                 //  output,    width = 4,                  .awregion
		.ruser                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_ruser),                    //   input,    width = 8,                  .ruser
		.buser                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_buser),                    //   input,    width = 8,                  .buser
		.arqos                  (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arqos),                    //  output,    width = 4,                  .arqos
		.arregion               (subsys_hps_f2sdram_adapter_axi4_sub_agent_altera_axi_master_arregion),                 //  output,    width = 4,                  .arregion
		.awuser_addrchk         (),                                                                                     // (terminated),                                 
		.awuser_sai             (),                                                                                     // (terminated),                                 
		.wuser_datachk          (),                                                                                     // (terminated),                                 
		.wuser_data             (),                                                                                     // (terminated),                                 
		.wuser_poison           (),                                                                                     // (terminated),                                 
		.aruser_addrchk         (),                                                                                     // (terminated),                                 
		.aruser_sai             (),                                                                                     // (terminated),                                 
		.ruser_datachk          (32'b00000000000000000000000000000000),                                                 // (terminated),                                 
		.ruser_data             (1'b0),                                                                                 // (terminated),                                 
		.ruser_poison           (4'b0000),                                                                              // (terminated),                                 
		.wid                    (),                                                                                     // (terminated),                                 
		.arsnoop                (),                                                                                     // (terminated),                                 
		.ardomain               (),                                                                                     // (terminated),                                 
		.arbar                  (),                                                                                     // (terminated),                                 
		.awsnoop                (),                                                                                     // (terminated),                                 
		.awdomain               (),                                                                                     // (terminated),                                 
		.awbar                  (),                                                                                     // (terminated),                                 
		.awunique               ()                                                                                      // (terminated),                                 
	);

	qsys_top_altera_merlin_router_1921_z4h5mxa router (
		.sink_ready         (ext_hps_f2sdram_master_expanded_master_agent_cp_ready),                               //  output,    width = 1,      sink.ready
		.sink_valid         (ext_hps_f2sdram_master_expanded_master_agent_cp_valid),                               //   input,    width = 1,          .valid
		.sink_data          (ext_hps_f2sdram_master_expanded_master_agent_cp_data),                                //   input,  width = 164,          .data
		.sink_startofpacket (ext_hps_f2sdram_master_expanded_master_agent_cp_startofpacket),                       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (ext_hps_f2sdram_master_expanded_master_agent_cp_endofpacket),                         //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset              (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                                                    //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                                                    //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                                                     //  output,  width = 164,          .data
		.src_channel        (router_src_channel),                                                                  //  output,    width = 2,          .channel
		.src_startofpacket  (router_src_startofpacket),                                                            //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                                                               //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_begsb3y router_001 (
		.sink_ready         (agent_pipeline_002_source0_ready),                                                    //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_002_source0_valid),                                                    //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_002_source0_data),                                                     //   input,  width = 416,          .data
		.sink_startofpacket (agent_pipeline_002_source0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_002_source0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset              (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                                                                //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                                                                //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                                                                 //  output,  width = 416,          .data
		.src_channel        (router_001_src_channel),                                                              //  output,    width = 2,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                                                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                                                           //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_begsb3y router_002 (
		.sink_ready         (agent_pipeline_003_source0_ready),                                                    //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),                                                    //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_003_source0_data),                                                     //   input,  width = 416,          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket),                                            //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),                                              //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset              (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                                                                //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                                                                //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                                                                 //  output,  width = 416,          .data
		.src_channel        (router_002_src_channel),                                                              //  output,    width = 2,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                                                        //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                                                           //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_traffic_limiter_1921_hlh4v7a #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (126),
		.PKT_DEST_ID_L                        (126),
		.PKT_SRC_ID_H                         (125),
		.PKT_SRC_ID_L                         (125),
		.PKT_BYTE_CNT_H                       (88),
		.PKT_BYTE_CNT_L                       (75),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (70),
		.PKT_TRANS_WRITE                      (71),
		.PKT_TRANS_SEQ_H                      (163),
		.PKT_TRANS_SEQ_L                      (157),
		.MAX_OUTSTANDING_RESPONSES            (14),
		.PIPELINED                            (0),
		.ST_DATA_W                            (164),
		.ST_CHANNEL_W                         (2),
		.VALID_WIDTH                          (1),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (1),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) ext_hps_f2sdram_master_expanded_master_limiter (
		.clk                    (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset                  (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                                                    //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                                                    //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                                                     //   input,  width = 164,          .data
		.cmd_sink_channel       (router_src_channel),                                                                  //   input,    width = 2,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                                            //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                                              //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_ready),                        //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_data),                         //  output,  width = 164,          .data
		.cmd_src_channel        (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_channel),                      //  output,    width = 2,          .channel
		.cmd_src_startofpacket  (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_startofpacket),                //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_endofpacket),                  //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_valid),                        //  output,    width = 1,          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),                                                  //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),                                                  //   input,    width = 1,          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),                                                //   input,    width = 2,          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),                                                   //   input,  width = 164,          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket),                                          //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),                                            //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_ready),                        //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_valid),                        //  output,    width = 1,          .valid
		.rsp_src_data           (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_data),                         //  output,  width = 164,          .data
		.rsp_src_channel        (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_channel),                      //  output,    width = 2,          .channel
		.rsp_src_startofpacket  (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_startofpacket),                //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (ext_hps_f2sdram_master_expanded_master_limiter_rsp_src_endofpacket)                   //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_3debjva cmd_demux (
		.clk                (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset              (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (limiter_pipeline_source0_ready),                                                      //  output,    width = 1,      sink.ready
		.sink_channel       (limiter_pipeline_source0_channel),                                                    //   input,    width = 2,          .channel
		.sink_data          (limiter_pipeline_source0_data),                                                       //   input,  width = 164,          .data
		.sink_startofpacket (limiter_pipeline_source0_startofpacket),                                              //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (limiter_pipeline_source0_endofpacket),                                                //   input,    width = 1,          .endofpacket
		.sink_valid         (limiter_pipeline_source0_valid),                                                      //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_src0_ready),                                                                //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                                                                //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_src0_data),                                                                 //  output,  width = 164,          .data
		.src0_channel       (cmd_demux_src0_channel),                                                              //  output,    width = 2,          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                                                        //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                                                          //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                                                                //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                                                                //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_src1_data),                                                                 //  output,  width = 164,          .data
		.src1_channel       (cmd_demux_src1_channel),                                                              //  output,    width = 2,          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                                                        //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket)                                                           //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_hsurnqa cmd_mux (
		.clk                 (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset               (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                                                                   //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                                                                   //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                                                                    //  output,  width = 164,          .data
		.src_channel         (cmd_mux_src_channel),                                                                 //  output,    width = 2,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                                                           //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                                                             //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_source0_ready),                                                          //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_source0_valid),                                                          //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_source0_channel),                                                        //   input,    width = 2,          .channel
		.sink0_data          (mux_pipeline_source0_data),                                                           //   input,  width = 164,          .data
		.sink0_startofpacket (mux_pipeline_source0_startofpacket),                                                  //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_source0_endofpacket)                                                     //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_hsurnqa cmd_mux_001 (
		.clk                 (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset               (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                                                               //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                                                               //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                                                                //  output,  width = 164,          .data
		.src_channel         (cmd_mux_001_src_channel),                                                             //  output,    width = 2,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                                                       //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                                                         //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_001_source0_ready),                                                      //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_001_source0_valid),                                                      //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_001_source0_channel),                                                    //   input,    width = 2,          .channel
		.sink0_data          (mux_pipeline_001_source0_data),                                                       //   input,  width = 164,          .data
		.sink0_startofpacket (mux_pipeline_001_source0_startofpacket),                                              //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_001_source0_endofpacket)                                                 //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_4fs5uoa rsp_demux (
		.clk                (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset              (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_ready),                  //  output,    width = 1,      sink.ready
		.sink_channel       (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_channel),                //   input,    width = 2,          .channel
		.sink_data          (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_data),                   //   input,  width = 164,          .data
		.sink_startofpacket (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_startofpacket),          //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_endofpacket),            //   input,    width = 1,          .endofpacket
		.sink_valid         (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_valid),                  //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                                                                //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                                                                //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                                                                 //  output,  width = 164,          .data
		.src0_channel       (rsp_demux_src0_channel),                                                              //  output,    width = 2,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                                                        //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket)                                                           //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_4fs5uoa rsp_demux_001 (
		.clk                (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset              (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_ready),                  //  output,    width = 1,      sink.ready
		.sink_channel       (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_channel),                //   input,    width = 2,          .channel
		.sink_data          (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_data),                   //   input,  width = 164,          .data
		.sink_startofpacket (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_startofpacket),          //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_endofpacket),            //   input,    width = 1,          .endofpacket
		.sink_valid         (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_valid),                  //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                                                            //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                                                            //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                                                             //  output,  width = 164,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                                                          //  output,    width = 2,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),                                                    //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket)                                                       //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_2nuun3q rsp_mux (
		.clk                 (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset               (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                                                                   //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                                                                   //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                                                                    //  output,  width = 164,          .data
		.src_channel         (rsp_mux_src_channel),                                                                 //  output,    width = 2,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                                                           //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                                                             //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_002_source0_ready),                                                      //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_002_source0_valid),                                                      //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_002_source0_channel),                                                    //   input,    width = 2,          .channel
		.sink0_data          (mux_pipeline_002_source0_data),                                                       //   input,  width = 164,          .data
		.sink0_startofpacket (mux_pipeline_002_source0_startofpacket),                                              //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_002_source0_endofpacket),                                                //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_003_source0_ready),                                                      //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_003_source0_valid),                                                      //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_003_source0_channel),                                                    //   input,    width = 2,          .channel
		.sink1_data          (mux_pipeline_003_source0_data),                                                       //   input,  width = 164,          .data
		.sink1_startofpacket (mux_pipeline_003_source0_startofpacket),                                              //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_003_source0_endofpacket)                                                 //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_width_adapter_1940_xh3mmbq #(
		.IN_PKT_ADDR_H                 (68),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (88),
		.IN_PKT_BYTE_CNT_L             (75),
		.IN_PKT_TRANS_COMPRESSED_READ  (69),
		.IN_PKT_TRANS_WRITE            (71),
		.IN_PKT_BURSTWRAP_H            (98),
		.IN_PKT_BURSTWRAP_L            (89),
		.IN_PKT_BURST_SIZE_H           (101),
		.IN_PKT_BURST_SIZE_L           (99),
		.IN_PKT_RESPONSE_STATUS_H      (136),
		.IN_PKT_RESPONSE_STATUS_L      (135),
		.IN_PKT_TRANS_EXCLUSIVE        (74),
		.IN_PKT_BURST_TYPE_H           (103),
		.IN_PKT_BURST_TYPE_L           (102),
		.IN_PKT_ORI_BURST_SIZE_L       (137),
		.IN_PKT_ORI_BURST_SIZE_H       (139),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (164),
		.OUT_PKT_ADDR_H                (320),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (340),
		.OUT_PKT_BYTE_CNT_L            (327),
		.OUT_PKT_TRANS_COMPRESSED_READ (321),
		.OUT_PKT_BURST_SIZE_H          (353),
		.OUT_PKT_BURST_SIZE_L          (351),
		.OUT_PKT_RESPONSE_STATUS_H     (388),
		.OUT_PKT_RESPONSE_STATUS_L     (387),
		.OUT_PKT_TRANS_EXCLUSIVE       (326),
		.OUT_PKT_BURST_TYPE_H          (355),
		.OUT_PKT_BURST_TYPE_L          (354),
		.OUT_PKT_ORI_BURST_SIZE_L      (389),
		.OUT_PKT_ORI_BURST_SIZE_H      (391),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (407),
		.OUT_PKT_SOP_OOO               (408),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (416),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset                (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_mux_src_valid),                                                                   //   input,    width = 1,      sink.valid
		.in_channel           (cmd_mux_src_channel),                                                                 //   input,    width = 2,          .channel
		.in_startofpacket     (cmd_mux_src_startofpacket),                                                           //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_mux_src_endofpacket),                                                             //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_mux_src_ready),                                                                   //  output,    width = 1,          .ready
		.in_data              (cmd_mux_src_data),                                                                    //   input,  width = 164,          .data
		.out_endofpacket      (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_endofpacket),            //  output,    width = 1,       src.endofpacket
		.out_data             (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_data),                   //  output,  width = 416,          .data
		.out_channel          (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_channel),                //  output,    width = 2,          .channel
		.out_valid            (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_valid),                  //  output,    width = 1,          .valid
		.out_ready            (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_ready),                  //   input,    width = 1,          .ready
		.out_startofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                               // (terminated),                         
	);

	qsys_top_altera_merlin_width_adapter_1940_xh3mmbq #(
		.IN_PKT_ADDR_H                 (68),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (88),
		.IN_PKT_BYTE_CNT_L             (75),
		.IN_PKT_TRANS_COMPRESSED_READ  (69),
		.IN_PKT_TRANS_WRITE            (71),
		.IN_PKT_BURSTWRAP_H            (98),
		.IN_PKT_BURSTWRAP_L            (89),
		.IN_PKT_BURST_SIZE_H           (101),
		.IN_PKT_BURST_SIZE_L           (99),
		.IN_PKT_RESPONSE_STATUS_H      (136),
		.IN_PKT_RESPONSE_STATUS_L      (135),
		.IN_PKT_TRANS_EXCLUSIVE        (74),
		.IN_PKT_BURST_TYPE_H           (103),
		.IN_PKT_BURST_TYPE_L           (102),
		.IN_PKT_ORI_BURST_SIZE_L       (137),
		.IN_PKT_ORI_BURST_SIZE_H       (139),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (164),
		.OUT_PKT_ADDR_H                (320),
		.OUT_PKT_ADDR_L                (288),
		.OUT_PKT_DATA_H                (255),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (287),
		.OUT_PKT_BYTEEN_L              (256),
		.OUT_PKT_BYTE_CNT_H            (340),
		.OUT_PKT_BYTE_CNT_L            (327),
		.OUT_PKT_TRANS_COMPRESSED_READ (321),
		.OUT_PKT_BURST_SIZE_H          (353),
		.OUT_PKT_BURST_SIZE_L          (351),
		.OUT_PKT_RESPONSE_STATUS_H     (388),
		.OUT_PKT_RESPONSE_STATUS_L     (387),
		.OUT_PKT_TRANS_EXCLUSIVE       (326),
		.OUT_PKT_BURST_TYPE_H          (355),
		.OUT_PKT_BURST_TYPE_L          (354),
		.OUT_PKT_ORI_BURST_SIZE_L      (389),
		.OUT_PKT_ORI_BURST_SIZE_H      (391),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (407),
		.OUT_PKT_SOP_OOO               (408),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (416),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset                (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_mux_001_src_valid),                                                               //   input,    width = 1,      sink.valid
		.in_channel           (cmd_mux_001_src_channel),                                                             //   input,    width = 2,          .channel
		.in_startofpacket     (cmd_mux_001_src_startofpacket),                                                       //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_mux_001_src_endofpacket),                                                         //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_mux_001_src_ready),                                                               //  output,    width = 1,          .ready
		.in_data              (cmd_mux_001_src_data),                                                                //   input,  width = 164,          .data
		.out_endofpacket      (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_endofpacket),            //  output,    width = 1,       src.endofpacket
		.out_data             (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_data),                   //  output,  width = 416,          .data
		.out_channel          (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_channel),                //  output,    width = 2,          .channel
		.out_valid            (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_valid),                  //  output,    width = 1,          .valid
		.out_ready            (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_ready),                  //   input,    width = 1,          .ready
		.out_startofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                               // (terminated),                         
	);

	qsys_top_altera_merlin_width_adapter_1940_hltmjiy #(
		.IN_PKT_ADDR_H                 (320),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (340),
		.IN_PKT_BYTE_CNT_L             (327),
		.IN_PKT_TRANS_COMPRESSED_READ  (321),
		.IN_PKT_TRANS_WRITE            (323),
		.IN_PKT_BURSTWRAP_H            (350),
		.IN_PKT_BURSTWRAP_L            (341),
		.IN_PKT_BURST_SIZE_H           (353),
		.IN_PKT_BURST_SIZE_L           (351),
		.IN_PKT_RESPONSE_STATUS_H      (388),
		.IN_PKT_RESPONSE_STATUS_L      (387),
		.IN_PKT_TRANS_EXCLUSIVE        (326),
		.IN_PKT_BURST_TYPE_H           (355),
		.IN_PKT_BURST_TYPE_L           (354),
		.IN_PKT_ORI_BURST_SIZE_L       (389),
		.IN_PKT_ORI_BURST_SIZE_H       (391),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (416),
		.OUT_PKT_ADDR_H                (68),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (88),
		.OUT_PKT_BYTE_CNT_L            (75),
		.OUT_PKT_TRANS_COMPRESSED_READ (69),
		.OUT_PKT_BURST_SIZE_H          (101),
		.OUT_PKT_BURST_SIZE_L          (99),
		.OUT_PKT_RESPONSE_STATUS_H     (136),
		.OUT_PKT_RESPONSE_STATUS_L     (135),
		.OUT_PKT_TRANS_EXCLUSIVE       (74),
		.OUT_PKT_BURST_TYPE_H          (103),
		.OUT_PKT_BURST_TYPE_L          (102),
		.OUT_PKT_ORI_BURST_SIZE_L      (137),
		.OUT_PKT_ORI_BURST_SIZE_H      (139),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (155),
		.OUT_PKT_SOP_OOO               (156),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (164),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset                (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_valid             (router_001_src_valid),                                                                //   input,    width = 1,      sink.valid
		.in_channel           (router_001_src_channel),                                                              //   input,    width = 2,          .channel
		.in_startofpacket     (router_001_src_startofpacket),                                                        //   input,    width = 1,          .startofpacket
		.in_endofpacket       (router_001_src_endofpacket),                                                          //   input,    width = 1,          .endofpacket
		.in_ready             (router_001_src_ready),                                                                //  output,    width = 1,          .ready
		.in_data              (router_001_src_data),                                                                 //   input,  width = 416,          .data
		.out_endofpacket      (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_endofpacket),            //  output,    width = 1,       src.endofpacket
		.out_data             (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_data),                   //  output,  width = 164,          .data
		.out_channel          (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_channel),                //  output,    width = 2,          .channel
		.out_valid            (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_valid),                  //  output,    width = 1,          .valid
		.out_ready            (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_ready),                  //   input,    width = 1,          .ready
		.out_startofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_wr_rsp_width_adapter_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                               // (terminated),                         
	);

	qsys_top_altera_merlin_width_adapter_1940_hltmjiy #(
		.IN_PKT_ADDR_H                 (320),
		.IN_PKT_ADDR_L                 (288),
		.IN_PKT_DATA_H                 (255),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (287),
		.IN_PKT_BYTEEN_L               (256),
		.IN_PKT_BYTE_CNT_H             (340),
		.IN_PKT_BYTE_CNT_L             (327),
		.IN_PKT_TRANS_COMPRESSED_READ  (321),
		.IN_PKT_TRANS_WRITE            (323),
		.IN_PKT_BURSTWRAP_H            (350),
		.IN_PKT_BURSTWRAP_L            (341),
		.IN_PKT_BURST_SIZE_H           (353),
		.IN_PKT_BURST_SIZE_L           (351),
		.IN_PKT_RESPONSE_STATUS_H      (388),
		.IN_PKT_RESPONSE_STATUS_L      (387),
		.IN_PKT_TRANS_EXCLUSIVE        (326),
		.IN_PKT_BURST_TYPE_H           (355),
		.IN_PKT_BURST_TYPE_L           (354),
		.IN_PKT_ORI_BURST_SIZE_L       (389),
		.IN_PKT_ORI_BURST_SIZE_H       (391),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (416),
		.OUT_PKT_ADDR_H                (68),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (88),
		.OUT_PKT_BYTE_CNT_L            (75),
		.OUT_PKT_TRANS_COMPRESSED_READ (69),
		.OUT_PKT_BURST_SIZE_H          (101),
		.OUT_PKT_BURST_SIZE_L          (99),
		.OUT_PKT_RESPONSE_STATUS_H     (136),
		.OUT_PKT_RESPONSE_STATUS_L     (135),
		.OUT_PKT_TRANS_EXCLUSIVE       (74),
		.OUT_PKT_BURST_TYPE_H          (103),
		.OUT_PKT_BURST_TYPE_L          (102),
		.OUT_PKT_ORI_BURST_SIZE_L      (137),
		.OUT_PKT_ORI_BURST_SIZE_H      (139),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (155),
		.OUT_PKT_SOP_OOO               (156),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (164),
		.ST_CHANNEL_W                  (2),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (0),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                                 //   input,    width = 1,       clk.clk
		.reset                (ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.in_valid             (router_002_src_valid),                                                                //   input,    width = 1,      sink.valid
		.in_channel           (router_002_src_channel),                                                              //   input,    width = 2,          .channel
		.in_startofpacket     (router_002_src_startofpacket),                                                        //   input,    width = 1,          .startofpacket
		.in_endofpacket       (router_002_src_endofpacket),                                                          //   input,    width = 1,          .endofpacket
		.in_ready             (router_002_src_ready),                                                                //  output,    width = 1,          .ready
		.in_data              (router_002_src_data),                                                                 //   input,  width = 416,          .data
		.out_endofpacket      (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_endofpacket),            //  output,    width = 1,       src.endofpacket
		.out_data             (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_data),                   //  output,  width = 164,          .data
		.out_channel          (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_channel),                //  output,    width = 2,          .channel
		.out_valid            (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_valid),                  //  output,    width = 1,          .valid
		.out_ready            (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_ready),                  //   input,    width = 1,          .ready
		.out_startofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_rd_rsp_width_adapter_src_startofpacket),          //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                               // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (164),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline (
		.clk               (clk_100_out_clk_clk),                                                  //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset),             //   input,    width = 1, cr0_reset.reset
		.in_ready          (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_data),          //   input,  width = 164,          .data
		.in_channel        (ext_hps_f2sdram_master_expanded_master_limiter_cmd_src_channel),       //   input,    width = 2,          .channel
		.out_ready         (limiter_pipeline_source0_ready),                                       //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),                                       //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket),                               //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),                                 //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_source0_data),                                        //  output,  width = 164,          .data
		.out_channel       (limiter_pipeline_source0_channel),                                     //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                 // (terminated),                         
		.out_empty         (),                                                                     // (terminated),                         
		.out_error         (),                                                                     // (terminated),                         
		.in_error          (1'b0)                                                                  // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (164),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                                      //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_mux_src_ready),                                        //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_mux_src_valid),                                        //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_mux_src_startofpacket),                                //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_mux_src_endofpacket),                                  //   input,    width = 1,          .endofpacket
		.in_data           (rsp_mux_src_data),                                         //   input,  width = 164,          .data
		.in_channel        (rsp_mux_src_channel),                                      //   input,    width = 2,          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),                       //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),                       //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket),               //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),                 //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),                        //  output,  width = 164,          .data
		.out_channel       (limiter_pipeline_001_source0_channel),                     //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_error          (1'b0)                                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (416),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline (
		.clk               (clk_100_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset),                   //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_data),          //   input,  width = 416,          .data
		.in_channel        (subsys_hps_f2sdram_adapter_axi4_sub_wr_cmd_width_adapter_src_channel),       //   input,    width = 2,          .channel
		.out_ready         (agent_pipeline_source0_ready),                                               //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_source0_valid),                                               //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),                                       //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),                                         //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_source0_data),                                                //  output,  width = 416,          .data
		.out_channel       (agent_pipeline_source0_channel),                                             //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                       // (terminated),                         
		.out_empty         (),                                                                           // (terminated),                         
		.out_error         (),                                                                           // (terminated),                         
		.in_error          (1'b0)                                                                        // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (416),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                                                        //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset),                   //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_data),          //   input,  width = 416,          .data
		.in_channel        (subsys_hps_f2sdram_adapter_axi4_sub_rd_cmd_width_adapter_src_channel),       //   input,    width = 2,          .channel
		.out_ready         (agent_pipeline_001_source0_ready),                                           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),                                           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket),                                   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),                                     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),                                            //  output,  width = 416,          .data
		.out_channel       (agent_pipeline_001_source0_channel),                                         //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                                       // (terminated),                         
		.out_empty         (),                                                                           // (terminated),                         
		.out_error         (),                                                                           // (terminated),                         
		.in_error          (1'b0)                                                                        // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (416),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_002 (
		.clk               (clk_100_out_clk_clk),                                              //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_f2sdram_adapter_axi4_sub_agent_write_rp_data),          //   input,  width = 416,          .data
		.out_ready         (agent_pipeline_002_source0_ready),                                 //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),                                 //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket),                         //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),                           //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),                                  //  output,  width = 416,          .data
		.in_empty          (1'b0),                                                             // (terminated),                         
		.out_empty         (),                                                                 // (terminated),                         
		.out_error         (),                                                                 // (terminated),                         
		.in_error          (1'b0),                                                             // (terminated),                         
		.out_channel       (),                                                                 // (terminated),                         
		.in_channel        (1'b0)                                                              // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (416),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_003 (
		.clk               (clk_100_out_clk_clk),                                             //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset),        //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_f2sdram_adapter_axi4_sub_agent_read_rp_data),          //   input,  width = 416,          .data
		.out_ready         (agent_pipeline_003_source0_ready),                                //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),                                //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket),                        //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),                          //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),                                 //  output,  width = 416,          .data
		.in_empty          (1'b0),                                                            // (terminated),                         
		.out_empty         (),                                                                // (terminated),                         
		.out_error         (),                                                                // (terminated),                         
		.in_error          (1'b0),                                                            // (terminated),                         
		.out_channel       (),                                                                // (terminated),                         
		.in_channel        (1'b0)                                                             // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (164),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline (
		.clk               (clk_100_out_clk_clk),                                      //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_src0_ready),                                     //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_src0_valid),                                     //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_src0_startofpacket),                             //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_src0_endofpacket),                               //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_src0_data),                                      //   input,  width = 164,          .data
		.in_channel        (cmd_demux_src0_channel),                                   //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_source0_ready),                               //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_source0_valid),                               //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_source0_startofpacket),                       //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_source0_endofpacket),                         //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_source0_data),                                //  output,  width = 164,          .data
		.out_channel       (mux_pipeline_source0_channel),                             //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_error          (1'b0)                                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (164),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                                      //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_src1_ready),                                     //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_src1_valid),                                     //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_src1_startofpacket),                             //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_src1_endofpacket),                               //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_src1_data),                                      //   input,  width = 164,          .data
		.in_channel        (cmd_demux_src1_channel),                                   //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_001_source0_ready),                           //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_001_source0_valid),                           //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_001_source0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_001_source0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_001_source0_data),                            //  output,  width = 164,          .data
		.out_channel       (mux_pipeline_001_source0_channel),                         //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_error          (1'b0)                                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (164),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_002 (
		.clk               (clk_100_out_clk_clk),                                      //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_src0_ready),                                     //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_src0_valid),                                     //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_src0_startofpacket),                             //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_src0_endofpacket),                               //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_src0_data),                                      //   input,  width = 164,          .data
		.in_channel        (rsp_demux_src0_channel),                                   //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_002_source0_ready),                           //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_002_source0_valid),                           //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_002_source0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_002_source0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_002_source0_data),                            //  output,  width = 164,          .data
		.out_channel       (mux_pipeline_002_source0_channel),                         //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_error          (1'b0)                                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (164),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (2),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_003 (
		.clk               (clk_100_out_clk_clk),                                      //   input,    width = 1,       cr0.clk
		.reset             (ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_001_src0_ready),                                 //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_001_src0_valid),                                 //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_001_src0_startofpacket),                         //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_001_src0_endofpacket),                           //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_001_src0_data),                                  //   input,  width = 164,          .data
		.in_channel        (rsp_demux_001_src0_channel),                               //   input,    width = 2,          .channel
		.out_ready         (mux_pipeline_003_source0_ready),                           //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_003_source0_valid),                           //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_003_source0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_003_source0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_003_source0_data),                            //  output,  width = 164,          .data
		.out_channel       (mux_pipeline_003_source0_channel),                         //  output,    width = 2,          .channel
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_error          (1'b0)                                                      // (terminated),                         
	);

endmodule
