// qsys_top_altera_mm_interconnect_1920_23wdfky.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module qsys_top_altera_mm_interconnect_1920_23wdfky (
		input  wire [31:0] subsys_debug_hps_f2sdram_master_address,             //          subsys_debug_hps_f2sdram_master.address
		output wire        subsys_debug_hps_f2sdram_master_waitrequest,         //                                         .waitrequest
		input  wire [3:0]  subsys_debug_hps_f2sdram_master_byteenable,          //                                         .byteenable
		input  wire        subsys_debug_hps_f2sdram_master_read,                //                                         .read
		output wire [31:0] subsys_debug_hps_f2sdram_master_readdata,            //                                         .readdata
		output wire        subsys_debug_hps_f2sdram_master_readdatavalid,       //                                         .readdatavalid
		input  wire        subsys_debug_hps_f2sdram_master_write,               //                                         .write
		input  wire [31:0] subsys_debug_hps_f2sdram_master_writedata,           //                                         .writedata
		output wire [29:0] ext_hps_f2sdram_master_windowed_slave_address,       //    ext_hps_f2sdram_master_windowed_slave.address
		output wire        ext_hps_f2sdram_master_windowed_slave_write,         //                                         .write
		output wire        ext_hps_f2sdram_master_windowed_slave_read,          //                                         .read
		input  wire [31:0] ext_hps_f2sdram_master_windowed_slave_readdata,      //                                         .readdata
		output wire [31:0] ext_hps_f2sdram_master_windowed_slave_writedata,     //                                         .writedata
		output wire [0:0]  ext_hps_f2sdram_master_windowed_slave_burstcount,    //                                         .burstcount
		output wire [3:0]  ext_hps_f2sdram_master_windowed_slave_byteenable,    //                                         .byteenable
		input  wire        ext_hps_f2sdram_master_windowed_slave_readdatavalid, //                                         .readdatavalid
		input  wire        ext_hps_f2sdram_master_windowed_slave_waitrequest,   //                                         .waitrequest
		input  wire        subsys_debug_reset_reset_bridge_in_reset_reset,      // subsys_debug_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire        clk_100_out_clk_clk                                  //                          clk_100_out_clk.clk,          Clock Input
	);

	wire         subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_waitrequest;   // ext_hps_f2sdram_master_windowed_slave_translator:uav_waitrequest -> subsys_debug_hps_f2sdram_master_translator:uav_waitrequest
	wire  [31:0] subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_readdata;      // ext_hps_f2sdram_master_windowed_slave_translator:uav_readdata -> subsys_debug_hps_f2sdram_master_translator:uav_readdata
	wire         subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_debugaccess;   // subsys_debug_hps_f2sdram_master_translator:uav_debugaccess -> ext_hps_f2sdram_master_windowed_slave_translator:uav_debugaccess
	wire  [31:0] subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_address;       // subsys_debug_hps_f2sdram_master_translator:uav_address -> ext_hps_f2sdram_master_windowed_slave_translator:uav_address
	wire         subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_read;          // subsys_debug_hps_f2sdram_master_translator:uav_read -> ext_hps_f2sdram_master_windowed_slave_translator:uav_read
	wire   [3:0] subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_byteenable;    // subsys_debug_hps_f2sdram_master_translator:uav_byteenable -> ext_hps_f2sdram_master_windowed_slave_translator:uav_byteenable
	wire         subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_readdatavalid; // ext_hps_f2sdram_master_windowed_slave_translator:uav_readdatavalid -> subsys_debug_hps_f2sdram_master_translator:uav_readdatavalid
	wire         subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_lock;          // subsys_debug_hps_f2sdram_master_translator:uav_lock -> ext_hps_f2sdram_master_windowed_slave_translator:uav_lock
	wire         subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_write;         // subsys_debug_hps_f2sdram_master_translator:uav_write -> ext_hps_f2sdram_master_windowed_slave_translator:uav_write
	wire  [31:0] subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_writedata;     // subsys_debug_hps_f2sdram_master_translator:uav_writedata -> ext_hps_f2sdram_master_windowed_slave_translator:uav_writedata
	wire   [2:0] subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_burstcount;    // subsys_debug_hps_f2sdram_master_translator:uav_burstcount -> ext_hps_f2sdram_master_windowed_slave_translator:uav_burstcount

	qsys_top_altera_merlin_master_translator_192_lykd4la #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (32),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) subsys_debug_hps_f2sdram_master_translator (
		.clk                    (clk_100_out_clk_clk),                                                                //   input,   width = 1,                       clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),                                     //   input,   width = 1,                     reset.reset
		.uav_address            (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_address),       //  output,  width = 32, avalon_universal_master_0.address
		.uav_burstcount         (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (subsys_debug_hps_f2sdram_master_address),                                            //   input,  width = 32,      avalon_anti_master_0.address
		.av_waitrequest         (subsys_debug_hps_f2sdram_master_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_byteenable          (subsys_debug_hps_f2sdram_master_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (subsys_debug_hps_f2sdram_master_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (subsys_debug_hps_f2sdram_master_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (subsys_debug_hps_f2sdram_master_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (subsys_debug_hps_f2sdram_master_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (subsys_debug_hps_f2sdram_master_writedata),                                          //   input,  width = 32,                          .writedata
		.av_burstcount          (1'b1),                                                                               // (terminated),                                        
		.av_beginbursttransfer  (1'b0),                                                                               // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                               // (terminated),                                        
		.av_chipselect          (1'b0),                                                                               // (terminated),                                        
		.av_lock                (1'b0),                                                                               // (terminated),                                        
		.av_debugaccess         (1'b0),                                                                               // (terminated),                                        
		.uav_outputenable       (1'b0),                                                                               // (terminated),                                        
		.uav_clken              (),                                                                                   // (terminated),                                        
		.av_clken               (1'b1),                                                                               // (terminated),                                        
		.uav_response           (2'b00),                                                                              // (terminated),                                        
		.av_response            (),                                                                                   // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                               // (terminated),                                        
		.av_writeresponsevalid  ()                                                                                    // (terminated),                                        
	);

	qsys_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (30),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (32),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) ext_hps_f2sdram_master_windowed_slave_translator (
		.clk                    (clk_100_out_clk_clk),                                                                //   input,   width = 1,                      clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),                                     //   input,   width = 1,                    reset.reset
		.uav_address            (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_address),       //   input,  width = 32, avalon_universal_slave_0.address
		.uav_burstcount         (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_read),          //   input,   width = 1,                         .read
		.uav_write              (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (subsys_debug_hps_f2sdram_master_translator_avalon_universal_master_0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (ext_hps_f2sdram_master_windowed_slave_address),                                      //  output,  width = 30,      avalon_anti_slave_0.address
		.av_write               (ext_hps_f2sdram_master_windowed_slave_write),                                        //  output,   width = 1,                         .write
		.av_read                (ext_hps_f2sdram_master_windowed_slave_read),                                         //  output,   width = 1,                         .read
		.av_readdata            (ext_hps_f2sdram_master_windowed_slave_readdata),                                     //   input,  width = 32,                         .readdata
		.av_writedata           (ext_hps_f2sdram_master_windowed_slave_writedata),                                    //  output,  width = 32,                         .writedata
		.av_burstcount          (ext_hps_f2sdram_master_windowed_slave_burstcount),                                   //  output,   width = 1,                         .burstcount
		.av_byteenable          (ext_hps_f2sdram_master_windowed_slave_byteenable),                                   //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (ext_hps_f2sdram_master_windowed_slave_readdatavalid),                                //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (ext_hps_f2sdram_master_windowed_slave_waitrequest),                                  //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                                                   // (terminated),                                       
		.av_beginbursttransfer  (),                                                                                   // (terminated),                                       
		.av_writebyteenable     (),                                                                                   // (terminated),                                       
		.av_lock                (),                                                                                   // (terminated),                                       
		.av_chipselect          (),                                                                                   // (terminated),                                       
		.av_clken               (),                                                                                   // (terminated),                                       
		.uav_clken              (1'b0),                                                                               // (terminated),                                       
		.av_debugaccess         (),                                                                                   // (terminated),                                       
		.av_outputenable        (),                                                                                   // (terminated),                                       
		.uav_response           (),                                                                                   // (terminated),                                       
		.av_response            (2'b00),                                                                              // (terminated),                                       
		.uav_writeresponsevalid (),                                                                                   // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                                                // (terminated),                                       
	);

endmodule
