// f2sdram_adapter.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module f2sdram_adapter (
		input  wire         clk,          //    clock.clk
		input  wire         reset,        //    reset.reset
		output wire [31:0]  man_araddr,   // axi4_man.araddr
		output wire [1:0]   man_arburst,  //         .arburst
		output wire [3:0]   man_arcache,  //         .arcache
		output wire [4:0]   man_arid,     //         .arid
		output wire [7:0]   man_arlen,    //         .arlen
		output wire         man_arlock,   //         .arlock
		output wire [2:0]   man_arprot,   //         .arprot
		output wire [3:0]   man_arqos,    //         .arqos
		input  wire         man_arready,  //         .arready
		output wire [2:0]   man_arsize,   //         .arsize
		output wire         man_arvalid,  //         .arvalid
		output wire [31:0]  man_awaddr,   //         .awaddr
		output wire [1:0]   man_awburst,  //         .awburst
		output wire [3:0]   man_awcache,  //         .awcache
		output wire [4:0]   man_awid,     //         .awid
		output wire [7:0]   man_awlen,    //         .awlen
		output wire         man_awlock,   //         .awlock
		output wire [2:0]   man_awprot,   //         .awprot
		output wire [3:0]   man_awqos,    //         .awqos
		input  wire         man_awready,  //         .awready
		output wire [2:0]   man_awsize,   //         .awsize
		output wire         man_awvalid,  //         .awvalid
		input  wire [4:0]   man_bid,      //         .bid
		output wire         man_bready,   //         .bready
		input  wire [1:0]   man_bresp,    //         .bresp
		input  wire         man_bvalid,   //         .bvalid
		input  wire [255:0] man_rdata,    //         .rdata
		input  wire [4:0]   man_rid,      //         .rid
		input  wire         man_rlast,    //         .rlast
		output wire         man_rready,   //         .rready
		input  wire [1:0]   man_rresp,    //         .rresp
		input  wire         man_rvalid,   //         .rvalid
		output wire [255:0] man_wdata,    //         .wdata
		output wire         man_wlast,    //         .wlast
		input  wire         man_wready,   //         .wready
		output wire [31:0]  man_wstrb,    //         .wstrb
		output wire         man_wvalid,   //         .wvalid
		output wire [7:0]   man_aruser,   //         .aruser
		output wire [7:0]   man_awuser,   //         .awuser
		output wire [7:0]   man_wuser,    //         .wuser
		input  wire [7:0]   man_buser,    //         .buser
		output wire [3:0]   man_arregion, //         .arregion
		input  wire [7:0]   man_ruser,    //         .ruser
		output wire [3:0]   man_awregion, //         .awregion
		input  wire [31:0]  sub_araddr,   // axi4_sub.araddr
		input  wire [1:0]   sub_arburst,  //         .arburst
		input  wire [3:0]   sub_arcache,  //         .arcache
		input  wire [4:0]   sub_arid,     //         .arid
		input  wire [7:0]   sub_arlen,    //         .arlen
		input  wire         sub_arlock,   //         .arlock
		input  wire [2:0]   sub_arprot,   //         .arprot
		input  wire [3:0]   sub_arqos,    //         .arqos
		output wire         sub_arready,  //         .arready
		input  wire [2:0]   sub_arsize,   //         .arsize
		input  wire         sub_arvalid,  //         .arvalid
		input  wire [31:0]  sub_awaddr,   //         .awaddr
		input  wire [1:0]   sub_awburst,  //         .awburst
		input  wire [3:0]   sub_awcache,  //         .awcache
		input  wire [4:0]   sub_awid,     //         .awid
		input  wire [7:0]   sub_awlen,    //         .awlen
		input  wire         sub_awlock,   //         .awlock
		input  wire [2:0]   sub_awprot,   //         .awprot
		input  wire [3:0]   sub_awqos,    //         .awqos
		output wire         sub_awready,  //         .awready
		input  wire [2:0]   sub_awsize,   //         .awsize
		input  wire         sub_awvalid,  //         .awvalid
		output wire [4:0]   sub_bid,      //         .bid
		input  wire         sub_bready,   //         .bready
		output wire [1:0]   sub_bresp,    //         .bresp
		output wire         sub_bvalid,   //         .bvalid
		output wire [255:0] sub_rdata,    //         .rdata
		output wire [4:0]   sub_rid,      //         .rid
		output wire         sub_rlast,    //         .rlast
		input  wire         sub_rready,   //         .rready
		output wire [1:0]   sub_rresp,    //         .rresp
		output wire         sub_rvalid,   //         .rvalid
		input  wire [255:0] sub_wdata,    //         .wdata
		input  wire         sub_wlast,    //         .wlast
		output wire         sub_wready,   //         .wready
		input  wire [31:0]  sub_wstrb,    //         .wstrb
		input  wire         sub_wvalid,   //         .wvalid
		input  wire [7:0]   sub_aruser,   //         .aruser
		input  wire [7:0]   sub_awuser,   //         .awuser
		input  wire [7:0]   sub_wuser,    //         .wuser
		output wire [7:0]   sub_buser,    //         .buser
		input  wire [3:0]   sub_arregion, //         .arregion
		output wire [7:0]   sub_ruser,    //         .ruser
		input  wire [3:0]   sub_awregion  //         .awregion
	);

	f2sdram_adapter_f2sdram_adapter_10_6slyhjq #(
		.DATA_WIDTH (256)
	) f2sdram_adapter_inst (
		.clk          (clk),          //   input,    width = 1,    clock.clk
		.reset        (reset),        //   input,    width = 1,    reset.reset
		.man_araddr   (man_araddr),   //  output,   width = 32, axi4_man.araddr
		.man_arburst  (man_arburst),  //  output,    width = 2,         .arburst
		.man_arcache  (man_arcache),  //  output,    width = 4,         .arcache
		.man_arid     (man_arid),     //  output,    width = 5,         .arid
		.man_arlen    (man_arlen),    //  output,    width = 8,         .arlen
		.man_arlock   (man_arlock),   //  output,    width = 1,         .arlock
		.man_arprot   (man_arprot),   //  output,    width = 3,         .arprot
		.man_arqos    (man_arqos),    //  output,    width = 4,         .arqos
		.man_arready  (man_arready),  //   input,    width = 1,         .arready
		.man_arsize   (man_arsize),   //  output,    width = 3,         .arsize
		.man_arvalid  (man_arvalid),  //  output,    width = 1,         .arvalid
		.man_awaddr   (man_awaddr),   //  output,   width = 32,         .awaddr
		.man_awburst  (man_awburst),  //  output,    width = 2,         .awburst
		.man_awcache  (man_awcache),  //  output,    width = 4,         .awcache
		.man_awid     (man_awid),     //  output,    width = 5,         .awid
		.man_awlen    (man_awlen),    //  output,    width = 8,         .awlen
		.man_awlock   (man_awlock),   //  output,    width = 1,         .awlock
		.man_awprot   (man_awprot),   //  output,    width = 3,         .awprot
		.man_awqos    (man_awqos),    //  output,    width = 4,         .awqos
		.man_awready  (man_awready),  //   input,    width = 1,         .awready
		.man_awsize   (man_awsize),   //  output,    width = 3,         .awsize
		.man_awvalid  (man_awvalid),  //  output,    width = 1,         .awvalid
		.man_bid      (man_bid),      //   input,    width = 5,         .bid
		.man_bready   (man_bready),   //  output,    width = 1,         .bready
		.man_bresp    (man_bresp),    //   input,    width = 2,         .bresp
		.man_bvalid   (man_bvalid),   //   input,    width = 1,         .bvalid
		.man_rdata    (man_rdata),    //   input,  width = 256,         .rdata
		.man_rid      (man_rid),      //   input,    width = 5,         .rid
		.man_rlast    (man_rlast),    //   input,    width = 1,         .rlast
		.man_rready   (man_rready),   //  output,    width = 1,         .rready
		.man_rresp    (man_rresp),    //   input,    width = 2,         .rresp
		.man_rvalid   (man_rvalid),   //   input,    width = 1,         .rvalid
		.man_wdata    (man_wdata),    //  output,  width = 256,         .wdata
		.man_wlast    (man_wlast),    //  output,    width = 1,         .wlast
		.man_wready   (man_wready),   //   input,    width = 1,         .wready
		.man_wstrb    (man_wstrb),    //  output,   width = 32,         .wstrb
		.man_wvalid   (man_wvalid),   //  output,    width = 1,         .wvalid
		.man_aruser   (man_aruser),   //  output,    width = 8,         .aruser
		.man_awuser   (man_awuser),   //  output,    width = 8,         .awuser
		.man_wuser    (man_wuser),    //  output,    width = 8,         .wuser
		.man_buser    (man_buser),    //   input,    width = 8,         .buser
		.man_arregion (man_arregion), //  output,    width = 4,         .arregion
		.man_ruser    (man_ruser),    //   input,    width = 8,         .ruser
		.man_awregion (man_awregion), //  output,    width = 4,         .awregion
		.sub_araddr   (sub_araddr),   //   input,   width = 32, axi4_sub.araddr
		.sub_arburst  (sub_arburst),  //   input,    width = 2,         .arburst
		.sub_arcache  (sub_arcache),  //   input,    width = 4,         .arcache
		.sub_arid     (sub_arid),     //   input,    width = 5,         .arid
		.sub_arlen    (sub_arlen),    //   input,    width = 8,         .arlen
		.sub_arlock   (sub_arlock),   //   input,    width = 1,         .arlock
		.sub_arprot   (sub_arprot),   //   input,    width = 3,         .arprot
		.sub_arqos    (sub_arqos),    //   input,    width = 4,         .arqos
		.sub_arready  (sub_arready),  //  output,    width = 1,         .arready
		.sub_arsize   (sub_arsize),   //   input,    width = 3,         .arsize
		.sub_arvalid  (sub_arvalid),  //   input,    width = 1,         .arvalid
		.sub_awaddr   (sub_awaddr),   //   input,   width = 32,         .awaddr
		.sub_awburst  (sub_awburst),  //   input,    width = 2,         .awburst
		.sub_awcache  (sub_awcache),  //   input,    width = 4,         .awcache
		.sub_awid     (sub_awid),     //   input,    width = 5,         .awid
		.sub_awlen    (sub_awlen),    //   input,    width = 8,         .awlen
		.sub_awlock   (sub_awlock),   //   input,    width = 1,         .awlock
		.sub_awprot   (sub_awprot),   //   input,    width = 3,         .awprot
		.sub_awqos    (sub_awqos),    //   input,    width = 4,         .awqos
		.sub_awready  (sub_awready),  //  output,    width = 1,         .awready
		.sub_awsize   (sub_awsize),   //   input,    width = 3,         .awsize
		.sub_awvalid  (sub_awvalid),  //   input,    width = 1,         .awvalid
		.sub_bid      (sub_bid),      //  output,    width = 5,         .bid
		.sub_bready   (sub_bready),   //   input,    width = 1,         .bready
		.sub_bresp    (sub_bresp),    //  output,    width = 2,         .bresp
		.sub_bvalid   (sub_bvalid),   //  output,    width = 1,         .bvalid
		.sub_rdata    (sub_rdata),    //  output,  width = 256,         .rdata
		.sub_rid      (sub_rid),      //  output,    width = 5,         .rid
		.sub_rlast    (sub_rlast),    //  output,    width = 1,         .rlast
		.sub_rready   (sub_rready),   //   input,    width = 1,         .rready
		.sub_rresp    (sub_rresp),    //  output,    width = 2,         .rresp
		.sub_rvalid   (sub_rvalid),   //  output,    width = 1,         .rvalid
		.sub_wdata    (sub_wdata),    //   input,  width = 256,         .wdata
		.sub_wlast    (sub_wlast),    //   input,    width = 1,         .wlast
		.sub_wready   (sub_wready),   //  output,    width = 1,         .wready
		.sub_wstrb    (sub_wstrb),    //   input,   width = 32,         .wstrb
		.sub_wvalid   (sub_wvalid),   //   input,    width = 1,         .wvalid
		.sub_aruser   (sub_aruser),   //   input,    width = 8,         .aruser
		.sub_awuser   (sub_awuser),   //   input,    width = 8,         .awuser
		.sub_wuser    (sub_wuser),    //   input,    width = 8,         .wuser
		.sub_buser    (sub_buser),    //  output,    width = 8,         .buser
		.sub_arregion (sub_arregion), //   input,    width = 4,         .arregion
		.sub_ruser    (sub_ruser),    //  output,    width = 8,         .ruser
		.sub_awregion (sub_awregion)  //   input,    width = 4,         .awregion
	);

endmodule
