// qsys_top.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module qsys_top (
		input  wire        clk_100_clk,                           //                        clk_100.clk
		input  wire        reset_reset_n,                         //                          reset.reset_n
		output wire        ninit_done_ninit_done,                 //                     ninit_done.ninit_done
		input  wire        hps_io_hps_osc_clk,                    //                         hps_io.hps_osc_clk
		inout  wire        hps_io_sdmmc_data0,                    //                               .sdmmc_data0
		inout  wire        hps_io_sdmmc_data1,                    //                               .sdmmc_data1
		output wire        hps_io_sdmmc_cclk,                     //                               .sdmmc_cclk
		inout  wire        hps_io_sdmmc_data2,                    //                               .sdmmc_data2
		inout  wire        hps_io_sdmmc_data3,                    //                               .sdmmc_data3
		inout  wire        hps_io_sdmmc_cmd,                      //                               .sdmmc_cmd
		input  wire        hps_io_usb1_clk,                       //                               .usb1_clk
		output wire        hps_io_usb1_stp,                       //                               .usb1_stp
		input  wire        hps_io_usb1_dir,                       //                               .usb1_dir
		inout  wire        hps_io_usb1_data0,                     //                               .usb1_data0
		inout  wire        hps_io_usb1_data1,                     //                               .usb1_data1
		input  wire        hps_io_usb1_nxt,                       //                               .usb1_nxt
		inout  wire        hps_io_usb1_data2,                     //                               .usb1_data2
		inout  wire        hps_io_usb1_data3,                     //                               .usb1_data3
		inout  wire        hps_io_usb1_data4,                     //                               .usb1_data4
		inout  wire        hps_io_usb1_data5,                     //                               .usb1_data5
		inout  wire        hps_io_usb1_data6,                     //                               .usb1_data6
		inout  wire        hps_io_usb1_data7,                     //                               .usb1_data7
		output wire        hps_io_emac2_tx_clk,                   //                               .emac2_tx_clk
		output wire        hps_io_emac2_tx_ctl,                   //                               .emac2_tx_ctl
		input  wire        hps_io_emac2_rx_clk,                   //                               .emac2_rx_clk
		input  wire        hps_io_emac2_rx_ctl,                   //                               .emac2_rx_ctl
		output wire        hps_io_emac2_txd0,                     //                               .emac2_txd0
		output wire        hps_io_emac2_txd1,                     //                               .emac2_txd1
		input  wire        hps_io_emac2_rxd0,                     //                               .emac2_rxd0
		input  wire        hps_io_emac2_rxd1,                     //                               .emac2_rxd1
		output wire        hps_io_emac2_txd2,                     //                               .emac2_txd2
		output wire        hps_io_emac2_txd3,                     //                               .emac2_txd3
		input  wire        hps_io_emac2_rxd2,                     //                               .emac2_rxd2
		input  wire        hps_io_emac2_rxd3,                     //                               .emac2_rxd3
		inout  wire        hps_io_mdio2_mdio,                     //                               .mdio2_mdio
		output wire        hps_io_mdio2_mdc,                      //                               .mdio2_mdc
		output wire        hps_io_uart0_tx,                       //                               .uart0_tx
		input  wire        hps_io_uart0_rx,                       //                               .uart0_rx
		inout  wire        hps_io_i2c0_sda,                       //                               .i2c0_sda
		inout  wire        hps_io_i2c0_scl,                       //                               .i2c0_scl
		inout  wire        hps_io_gpio0,                          //                               .gpio0
		inout  wire        hps_io_gpio1,                          //                               .gpio1
		inout  wire        hps_io_gpio8,                          //                               .gpio8
		inout  wire        hps_io_gpio9,                          //                               .gpio9
		inout  wire        hps_io_gpio10,                         //                               .gpio10
		inout  wire        hps_io_gpio11,                         //                               .gpio11
		inout  wire        hps_io_gpio28,                         //                               .gpio28
		input  wire        usb31_io_vbus_det,                     //                       usb31_io.vbus_det
		input  wire        usb31_io_flt_bar,                      //                               .flt_bar
		output wire [1:0]  usb31_io_usb_ctrl,                     //                               .usb_ctrl
		input  wire        usb31_io_usb31_id,                     //                               .usb31_id
		input  wire        usb31_phy_pma_cpu_clk_clk,             //          usb31_phy_pma_cpu_clk.clk
		input  wire        usb31_phy_refclk_p_clk,                //             usb31_phy_refclk_p.clk
		input  wire        usb31_phy_refclk_n_clk,                //             usb31_phy_refclk_n.clk
		input  wire        usb31_phy_rx_serial_n_i_rx_serial_n,   //          usb31_phy_rx_serial_n.i_rx_serial_n
		input  wire        usb31_phy_rx_serial_p_i_rx_serial_p,   //          usb31_phy_rx_serial_p.i_rx_serial_p
		output wire        usb31_phy_tx_serial_n_o_tx_serial_n,   //          usb31_phy_tx_serial_n.o_tx_serial_n
		output wire        usb31_phy_tx_serial_p_o_tx_serial_p,   //          usb31_phy_tx_serial_p.o_tx_serial_p
		output wire        emif_hps_emif_mem_0_mem_ck_t,          //            emif_hps_emif_mem_0.mem_ck_t
		output wire        emif_hps_emif_mem_0_mem_ck_c,          //                               .mem_ck_c
		output wire        emif_hps_emif_mem_0_mem_cke,           //                               .mem_cke
		output wire        emif_hps_emif_mem_0_mem_odt,           //                               .mem_odt
		output wire        emif_hps_emif_mem_0_mem_cs_n,          //                               .mem_cs_n
		output wire [16:0] emif_hps_emif_mem_0_mem_a,             //                               .mem_a
		output wire [1:0]  emif_hps_emif_mem_0_mem_ba,            //                               .mem_ba
		output wire        emif_hps_emif_mem_0_mem_bg,            //                               .mem_bg
		output wire        emif_hps_emif_mem_0_mem_act_n,         //                               .mem_act_n
		output wire        emif_hps_emif_mem_0_mem_par,           //                               .mem_par
		input  wire        emif_hps_emif_mem_0_mem_alert_n,       //                               .mem_alert_n
		output wire        emif_hps_emif_mem_0_mem_reset_n,       //                               .mem_reset_n
		inout  wire [31:0] emif_hps_emif_mem_0_mem_dq,            //                               .mem_dq
		inout  wire [3:0]  emif_hps_emif_mem_0_mem_dqs_t,         //                               .mem_dqs_t
		inout  wire [3:0]  emif_hps_emif_mem_0_mem_dqs_c,         //                               .mem_dqs_c
		inout  wire [3:0]  emif_hps_emif_mem_0_mem_dbi_n,         //                               .mem_dbi_n
		input  wire        emif_hps_emif_oct_0_oct_rzqin,         //            emif_hps_emif_oct_0.oct_rzqin
		input  wire        emif_hps_emif_ref_clk_0_clk,           //        emif_hps_emif_ref_clk_0.clk
		output wire [0:0]  o_pma_cu_clk_clk,                      //                   o_pma_cu_clk.clk
		input  wire [3:0]  button_pio_external_connection_export, // button_pio_external_connection.export
		input  wire [3:0]  dipsw_pio_external_connection_export,  //  dipsw_pio_external_connection.export
		input  wire [2:0]  led_pio_external_connection_in_port,   //    led_pio_external_connection.in_port
		output wire [2:0]  led_pio_external_connection_out_port   //                               .out_port
	);

	wire          clk_100_out_clk_clk;                                                   // clk_100:out_clk -> [ext_hps_f2sdram_master:clk, mm_interconnect_0:clk_100_out_clk_clk, mm_interconnect_1:clk_100_out_clk_clk, mm_interconnect_2:clk_100_out_clk_clk, ocm:clk, rst_controller:clk, rst_controller_001:clk, subsys_debug:clk_clk, subsys_hps:f2sdram_adapter_clk_clk, subsys_hps:f2sdram_clk_clk, subsys_hps:hps2fpga_clk_clk, subsys_hps:lwhps2fpga_clk_clk, subsys_hps:usb31_phy_reconfig_clk_clk, subsys_periph:clk_clk]
	wire          rst_in_out_reset_reset;                                                // rst_in:out_reset_n -> [rst_controller:reset_in0, rst_controller_001:reset_in0, subsys_hps:f2sdram_rst_reset, subsys_hps:hps2fpga_rst_reset, subsys_hps:lwhps2fpga_rst_reset, subsys_hps:usb31_phy_reconfig_rst_reset]
	wire          ext_hps_f2sdram_master_expanded_master_waitrequest;                    // mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_waitrequest -> ext_hps_f2sdram_master:avm_m0_waitrequest
	wire   [31:0] ext_hps_f2sdram_master_expanded_master_readdata;                       // mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_readdata -> ext_hps_f2sdram_master:avm_m0_readdata
	wire   [32:0] ext_hps_f2sdram_master_expanded_master_address;                        // ext_hps_f2sdram_master:avm_m0_address -> mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_address
	wire          ext_hps_f2sdram_master_expanded_master_read;                           // ext_hps_f2sdram_master:avm_m0_read -> mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_read
	wire    [3:0] ext_hps_f2sdram_master_expanded_master_byteenable;                     // ext_hps_f2sdram_master:avm_m0_byteenable -> mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_byteenable
	wire          ext_hps_f2sdram_master_expanded_master_readdatavalid;                  // mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_readdatavalid -> ext_hps_f2sdram_master:avm_m0_readdatavalid
	wire          ext_hps_f2sdram_master_expanded_master_write;                          // ext_hps_f2sdram_master:avm_m0_write -> mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_write
	wire   [31:0] ext_hps_f2sdram_master_expanded_master_writedata;                      // ext_hps_f2sdram_master:avm_m0_writedata -> mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_writedata
	wire    [0:0] ext_hps_f2sdram_master_expanded_master_burstcount;                     // ext_hps_f2sdram_master:avm_m0_burstcount -> mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_burstcount
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_ruser;           // subsys_hps:f2sdram_adapter_axi4_sub_ruser -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_ruser
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wuser;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_wuser -> subsys_hps:f2sdram_adapter_axi4_sub_wuser
	wire    [1:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awburst;         // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awburst -> subsys_hps:f2sdram_adapter_axi4_sub_awburst
	wire    [3:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arregion;        // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arregion -> subsys_hps:f2sdram_adapter_axi4_sub_arregion
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awuser;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awuser -> subsys_hps:f2sdram_adapter_axi4_sub_awuser
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arlen;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arlen -> subsys_hps:f2sdram_adapter_axi4_sub_arlen
	wire    [3:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arqos;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arqos -> subsys_hps:f2sdram_adapter_axi4_sub_arqos
	wire   [31:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wstrb;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_wstrb -> subsys_hps:f2sdram_adapter_axi4_sub_wstrb
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wready;          // subsys_hps:f2sdram_adapter_axi4_sub_wready -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_wready
	wire    [4:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rid;             // subsys_hps:f2sdram_adapter_axi4_sub_rid -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_rid
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rready;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_rready -> subsys_hps:f2sdram_adapter_axi4_sub_rready
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awlen;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awlen -> subsys_hps:f2sdram_adapter_axi4_sub_awlen
	wire    [3:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awqos;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awqos -> subsys_hps:f2sdram_adapter_axi4_sub_awqos
	wire    [3:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arcache;         // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arcache -> subsys_hps:f2sdram_adapter_axi4_sub_arcache
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wvalid;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_wvalid -> subsys_hps:f2sdram_adapter_axi4_sub_wvalid
	wire   [31:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_araddr;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_araddr -> subsys_hps:f2sdram_adapter_axi4_sub_araddr
	wire    [2:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arprot;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arprot -> subsys_hps:f2sdram_adapter_axi4_sub_arprot
	wire    [2:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awprot;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awprot -> subsys_hps:f2sdram_adapter_axi4_sub_awprot
	wire  [255:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wdata;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_wdata -> subsys_hps:f2sdram_adapter_axi4_sub_wdata
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arvalid;         // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arvalid -> subsys_hps:f2sdram_adapter_axi4_sub_arvalid
	wire    [3:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awcache;         // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awcache -> subsys_hps:f2sdram_adapter_axi4_sub_awcache
	wire    [4:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arid;            // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arid -> subsys_hps:f2sdram_adapter_axi4_sub_arid
	wire    [0:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arlock;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arlock -> subsys_hps:f2sdram_adapter_axi4_sub_arlock
	wire    [0:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awlock;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awlock -> subsys_hps:f2sdram_adapter_axi4_sub_awlock
	wire   [31:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awaddr;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awaddr -> subsys_hps:f2sdram_adapter_axi4_sub_awaddr
	wire    [1:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bresp;           // subsys_hps:f2sdram_adapter_axi4_sub_bresp -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_bresp
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arready;         // subsys_hps:f2sdram_adapter_axi4_sub_arready -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arready
	wire  [255:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rdata;           // subsys_hps:f2sdram_adapter_axi4_sub_rdata -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_rdata
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awready;         // subsys_hps:f2sdram_adapter_axi4_sub_awready -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awready
	wire    [1:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arburst;         // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arburst -> subsys_hps:f2sdram_adapter_axi4_sub_arburst
	wire    [2:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arsize;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_arsize -> subsys_hps:f2sdram_adapter_axi4_sub_arsize
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bready;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_bready -> subsys_hps:f2sdram_adapter_axi4_sub_bready
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rlast;           // subsys_hps:f2sdram_adapter_axi4_sub_rlast -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_rlast
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wlast;           // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_wlast -> subsys_hps:f2sdram_adapter_axi4_sub_wlast
	wire    [3:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awregion;        // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awregion -> subsys_hps:f2sdram_adapter_axi4_sub_awregion
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_buser;           // subsys_hps:f2sdram_adapter_axi4_sub_buser -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_buser
	wire    [1:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rresp;           // subsys_hps:f2sdram_adapter_axi4_sub_rresp -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_rresp
	wire    [4:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awid;            // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awid -> subsys_hps:f2sdram_adapter_axi4_sub_awid
	wire    [4:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bid;             // subsys_hps:f2sdram_adapter_axi4_sub_bid -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_bid
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bvalid;          // subsys_hps:f2sdram_adapter_axi4_sub_bvalid -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_bvalid
	wire    [2:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awsize;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awsize -> subsys_hps:f2sdram_adapter_axi4_sub_awsize
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awvalid;         // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_awvalid -> subsys_hps:f2sdram_adapter_axi4_sub_awvalid
	wire    [7:0] mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_aruser;          // mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_aruser -> subsys_hps:f2sdram_adapter_axi4_sub_aruser
	wire          mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rvalid;          // subsys_hps:f2sdram_adapter_axi4_sub_rvalid -> mm_interconnect_0:subsys_hps_f2sdram_adapter_axi4_sub_rvalid
	wire   [31:0] subsys_debug_fpga_m_master_readdata;                                   // mm_interconnect_1:subsys_debug_fpga_m_master_readdata -> subsys_debug:fpga_m_master_readdata
	wire          subsys_debug_fpga_m_master_waitrequest;                                // mm_interconnect_1:subsys_debug_fpga_m_master_waitrequest -> subsys_debug:fpga_m_master_waitrequest
	wire   [31:0] subsys_debug_fpga_m_master_address;                                    // subsys_debug:fpga_m_master_address -> mm_interconnect_1:subsys_debug_fpga_m_master_address
	wire          subsys_debug_fpga_m_master_read;                                       // subsys_debug:fpga_m_master_read -> mm_interconnect_1:subsys_debug_fpga_m_master_read
	wire    [3:0] subsys_debug_fpga_m_master_byteenable;                                 // subsys_debug:fpga_m_master_byteenable -> mm_interconnect_1:subsys_debug_fpga_m_master_byteenable
	wire          subsys_debug_fpga_m_master_readdatavalid;                              // mm_interconnect_1:subsys_debug_fpga_m_master_readdatavalid -> subsys_debug:fpga_m_master_readdatavalid
	wire          subsys_debug_fpga_m_master_write;                                      // subsys_debug:fpga_m_master_write -> mm_interconnect_1:subsys_debug_fpga_m_master_write
	wire   [31:0] subsys_debug_fpga_m_master_writedata;                                  // subsys_debug:fpga_m_master_writedata -> mm_interconnect_1:subsys_debug_fpga_m_master_writedata
	wire    [1:0] subsys_hps_hps2fpga_awburst;                                           // subsys_hps:hps2fpga_awburst -> mm_interconnect_1:subsys_hps_hps2fpga_awburst
	wire    [7:0] subsys_hps_hps2fpga_arlen;                                             // subsys_hps:hps2fpga_arlen -> mm_interconnect_1:subsys_hps_hps2fpga_arlen
	wire   [15:0] subsys_hps_hps2fpga_wstrb;                                             // subsys_hps:hps2fpga_wstrb -> mm_interconnect_1:subsys_hps_hps2fpga_wstrb
	wire          subsys_hps_hps2fpga_wready;                                            // mm_interconnect_1:subsys_hps_hps2fpga_wready -> subsys_hps:hps2fpga_wready
	wire    [3:0] subsys_hps_hps2fpga_rid;                                               // mm_interconnect_1:subsys_hps_hps2fpga_rid -> subsys_hps:hps2fpga_rid
	wire          subsys_hps_hps2fpga_rready;                                            // subsys_hps:hps2fpga_rready -> mm_interconnect_1:subsys_hps_hps2fpga_rready
	wire    [7:0] subsys_hps_hps2fpga_awlen;                                             // subsys_hps:hps2fpga_awlen -> mm_interconnect_1:subsys_hps_hps2fpga_awlen
	wire    [3:0] subsys_hps_hps2fpga_arcache;                                           // subsys_hps:hps2fpga_arcache -> mm_interconnect_1:subsys_hps_hps2fpga_arcache
	wire          subsys_hps_hps2fpga_wvalid;                                            // subsys_hps:hps2fpga_wvalid -> mm_interconnect_1:subsys_hps_hps2fpga_wvalid
	wire   [37:0] subsys_hps_hps2fpga_araddr;                                            // subsys_hps:hps2fpga_araddr -> mm_interconnect_1:subsys_hps_hps2fpga_araddr
	wire    [2:0] subsys_hps_hps2fpga_arprot;                                            // subsys_hps:hps2fpga_arprot -> mm_interconnect_1:subsys_hps_hps2fpga_arprot
	wire    [2:0] subsys_hps_hps2fpga_awprot;                                            // subsys_hps:hps2fpga_awprot -> mm_interconnect_1:subsys_hps_hps2fpga_awprot
	wire  [127:0] subsys_hps_hps2fpga_wdata;                                             // subsys_hps:hps2fpga_wdata -> mm_interconnect_1:subsys_hps_hps2fpga_wdata
	wire          subsys_hps_hps2fpga_arvalid;                                           // subsys_hps:hps2fpga_arvalid -> mm_interconnect_1:subsys_hps_hps2fpga_arvalid
	wire    [3:0] subsys_hps_hps2fpga_awcache;                                           // subsys_hps:hps2fpga_awcache -> mm_interconnect_1:subsys_hps_hps2fpga_awcache
	wire    [3:0] subsys_hps_hps2fpga_arid;                                              // subsys_hps:hps2fpga_arid -> mm_interconnect_1:subsys_hps_hps2fpga_arid
	wire          subsys_hps_hps2fpga_arlock;                                            // subsys_hps:hps2fpga_arlock -> mm_interconnect_1:subsys_hps_hps2fpga_arlock
	wire          subsys_hps_hps2fpga_awlock;                                            // subsys_hps:hps2fpga_awlock -> mm_interconnect_1:subsys_hps_hps2fpga_awlock
	wire   [37:0] subsys_hps_hps2fpga_awaddr;                                            // subsys_hps:hps2fpga_awaddr -> mm_interconnect_1:subsys_hps_hps2fpga_awaddr
	wire    [1:0] subsys_hps_hps2fpga_bresp;                                             // mm_interconnect_1:subsys_hps_hps2fpga_bresp -> subsys_hps:hps2fpga_bresp
	wire          subsys_hps_hps2fpga_arready;                                           // mm_interconnect_1:subsys_hps_hps2fpga_arready -> subsys_hps:hps2fpga_arready
	wire  [127:0] subsys_hps_hps2fpga_rdata;                                             // mm_interconnect_1:subsys_hps_hps2fpga_rdata -> subsys_hps:hps2fpga_rdata
	wire          subsys_hps_hps2fpga_awready;                                           // mm_interconnect_1:subsys_hps_hps2fpga_awready -> subsys_hps:hps2fpga_awready
	wire    [1:0] subsys_hps_hps2fpga_arburst;                                           // subsys_hps:hps2fpga_arburst -> mm_interconnect_1:subsys_hps_hps2fpga_arburst
	wire    [2:0] subsys_hps_hps2fpga_arsize;                                            // subsys_hps:hps2fpga_arsize -> mm_interconnect_1:subsys_hps_hps2fpga_arsize
	wire          subsys_hps_hps2fpga_bready;                                            // subsys_hps:hps2fpga_bready -> mm_interconnect_1:subsys_hps_hps2fpga_bready
	wire          subsys_hps_hps2fpga_rlast;                                             // mm_interconnect_1:subsys_hps_hps2fpga_rlast -> subsys_hps:hps2fpga_rlast
	wire          subsys_hps_hps2fpga_wlast;                                             // subsys_hps:hps2fpga_wlast -> mm_interconnect_1:subsys_hps_hps2fpga_wlast
	wire    [1:0] subsys_hps_hps2fpga_rresp;                                             // mm_interconnect_1:subsys_hps_hps2fpga_rresp -> subsys_hps:hps2fpga_rresp
	wire    [3:0] subsys_hps_hps2fpga_awid;                                              // subsys_hps:hps2fpga_awid -> mm_interconnect_1:subsys_hps_hps2fpga_awid
	wire    [3:0] subsys_hps_hps2fpga_bid;                                               // mm_interconnect_1:subsys_hps_hps2fpga_bid -> subsys_hps:hps2fpga_bid
	wire          subsys_hps_hps2fpga_bvalid;                                            // mm_interconnect_1:subsys_hps_hps2fpga_bvalid -> subsys_hps:hps2fpga_bvalid
	wire    [2:0] subsys_hps_hps2fpga_awsize;                                            // subsys_hps:hps2fpga_awsize -> mm_interconnect_1:subsys_hps_hps2fpga_awsize
	wire          subsys_hps_hps2fpga_awvalid;                                           // subsys_hps:hps2fpga_awvalid -> mm_interconnect_1:subsys_hps_hps2fpga_awvalid
	wire          subsys_hps_hps2fpga_rvalid;                                            // mm_interconnect_1:subsys_hps_hps2fpga_rvalid -> subsys_hps:hps2fpga_rvalid
	wire    [1:0] subsys_hps_lwhps2fpga_awburst;                                         // subsys_hps:lwhps2fpga_awburst -> mm_interconnect_1:subsys_hps_lwhps2fpga_awburst
	wire    [7:0] subsys_hps_lwhps2fpga_arlen;                                           // subsys_hps:lwhps2fpga_arlen -> mm_interconnect_1:subsys_hps_lwhps2fpga_arlen
	wire    [3:0] subsys_hps_lwhps2fpga_wstrb;                                           // subsys_hps:lwhps2fpga_wstrb -> mm_interconnect_1:subsys_hps_lwhps2fpga_wstrb
	wire          subsys_hps_lwhps2fpga_wready;                                          // mm_interconnect_1:subsys_hps_lwhps2fpga_wready -> subsys_hps:lwhps2fpga_wready
	wire    [3:0] subsys_hps_lwhps2fpga_rid;                                             // mm_interconnect_1:subsys_hps_lwhps2fpga_rid -> subsys_hps:lwhps2fpga_rid
	wire          subsys_hps_lwhps2fpga_rready;                                          // subsys_hps:lwhps2fpga_rready -> mm_interconnect_1:subsys_hps_lwhps2fpga_rready
	wire    [7:0] subsys_hps_lwhps2fpga_awlen;                                           // subsys_hps:lwhps2fpga_awlen -> mm_interconnect_1:subsys_hps_lwhps2fpga_awlen
	wire    [3:0] subsys_hps_lwhps2fpga_arcache;                                         // subsys_hps:lwhps2fpga_arcache -> mm_interconnect_1:subsys_hps_lwhps2fpga_arcache
	wire          subsys_hps_lwhps2fpga_wvalid;                                          // subsys_hps:lwhps2fpga_wvalid -> mm_interconnect_1:subsys_hps_lwhps2fpga_wvalid
	wire   [28:0] subsys_hps_lwhps2fpga_araddr;                                          // subsys_hps:lwhps2fpga_araddr -> mm_interconnect_1:subsys_hps_lwhps2fpga_araddr
	wire    [2:0] subsys_hps_lwhps2fpga_arprot;                                          // subsys_hps:lwhps2fpga_arprot -> mm_interconnect_1:subsys_hps_lwhps2fpga_arprot
	wire    [2:0] subsys_hps_lwhps2fpga_awprot;                                          // subsys_hps:lwhps2fpga_awprot -> mm_interconnect_1:subsys_hps_lwhps2fpga_awprot
	wire   [31:0] subsys_hps_lwhps2fpga_wdata;                                           // subsys_hps:lwhps2fpga_wdata -> mm_interconnect_1:subsys_hps_lwhps2fpga_wdata
	wire          subsys_hps_lwhps2fpga_arvalid;                                         // subsys_hps:lwhps2fpga_arvalid -> mm_interconnect_1:subsys_hps_lwhps2fpga_arvalid
	wire    [3:0] subsys_hps_lwhps2fpga_awcache;                                         // subsys_hps:lwhps2fpga_awcache -> mm_interconnect_1:subsys_hps_lwhps2fpga_awcache
	wire    [3:0] subsys_hps_lwhps2fpga_arid;                                            // subsys_hps:lwhps2fpga_arid -> mm_interconnect_1:subsys_hps_lwhps2fpga_arid
	wire          subsys_hps_lwhps2fpga_arlock;                                          // subsys_hps:lwhps2fpga_arlock -> mm_interconnect_1:subsys_hps_lwhps2fpga_arlock
	wire          subsys_hps_lwhps2fpga_awlock;                                          // subsys_hps:lwhps2fpga_awlock -> mm_interconnect_1:subsys_hps_lwhps2fpga_awlock
	wire   [28:0] subsys_hps_lwhps2fpga_awaddr;                                          // subsys_hps:lwhps2fpga_awaddr -> mm_interconnect_1:subsys_hps_lwhps2fpga_awaddr
	wire    [1:0] subsys_hps_lwhps2fpga_bresp;                                           // mm_interconnect_1:subsys_hps_lwhps2fpga_bresp -> subsys_hps:lwhps2fpga_bresp
	wire          subsys_hps_lwhps2fpga_arready;                                         // mm_interconnect_1:subsys_hps_lwhps2fpga_arready -> subsys_hps:lwhps2fpga_arready
	wire   [31:0] subsys_hps_lwhps2fpga_rdata;                                           // mm_interconnect_1:subsys_hps_lwhps2fpga_rdata -> subsys_hps:lwhps2fpga_rdata
	wire          subsys_hps_lwhps2fpga_awready;                                         // mm_interconnect_1:subsys_hps_lwhps2fpga_awready -> subsys_hps:lwhps2fpga_awready
	wire    [1:0] subsys_hps_lwhps2fpga_arburst;                                         // subsys_hps:lwhps2fpga_arburst -> mm_interconnect_1:subsys_hps_lwhps2fpga_arburst
	wire    [2:0] subsys_hps_lwhps2fpga_arsize;                                          // subsys_hps:lwhps2fpga_arsize -> mm_interconnect_1:subsys_hps_lwhps2fpga_arsize
	wire          subsys_hps_lwhps2fpga_bready;                                          // subsys_hps:lwhps2fpga_bready -> mm_interconnect_1:subsys_hps_lwhps2fpga_bready
	wire          subsys_hps_lwhps2fpga_rlast;                                           // mm_interconnect_1:subsys_hps_lwhps2fpga_rlast -> subsys_hps:lwhps2fpga_rlast
	wire          subsys_hps_lwhps2fpga_wlast;                                           // subsys_hps:lwhps2fpga_wlast -> mm_interconnect_1:subsys_hps_lwhps2fpga_wlast
	wire    [1:0] subsys_hps_lwhps2fpga_rresp;                                           // mm_interconnect_1:subsys_hps_lwhps2fpga_rresp -> subsys_hps:lwhps2fpga_rresp
	wire    [3:0] subsys_hps_lwhps2fpga_awid;                                            // subsys_hps:lwhps2fpga_awid -> mm_interconnect_1:subsys_hps_lwhps2fpga_awid
	wire    [3:0] subsys_hps_lwhps2fpga_bid;                                             // mm_interconnect_1:subsys_hps_lwhps2fpga_bid -> subsys_hps:lwhps2fpga_bid
	wire          subsys_hps_lwhps2fpga_bvalid;                                          // mm_interconnect_1:subsys_hps_lwhps2fpga_bvalid -> subsys_hps:lwhps2fpga_bvalid
	wire    [2:0] subsys_hps_lwhps2fpga_awsize;                                          // subsys_hps:lwhps2fpga_awsize -> mm_interconnect_1:subsys_hps_lwhps2fpga_awsize
	wire          subsys_hps_lwhps2fpga_awvalid;                                         // subsys_hps:lwhps2fpga_awvalid -> mm_interconnect_1:subsys_hps_lwhps2fpga_awvalid
	wire          subsys_hps_lwhps2fpga_rvalid;                                          // mm_interconnect_1:subsys_hps_lwhps2fpga_rvalid -> subsys_hps:lwhps2fpga_rvalid
	wire    [1:0] mm_interconnect_1_ocm_axi_s1_awburst;                                  // mm_interconnect_1:ocm_axi_s1_awburst -> ocm:s1_awburst
	wire    [7:0] mm_interconnect_1_ocm_axi_s1_arlen;                                    // mm_interconnect_1:ocm_axi_s1_arlen -> ocm:s1_arlen
	wire   [15:0] mm_interconnect_1_ocm_axi_s1_wstrb;                                    // mm_interconnect_1:ocm_axi_s1_wstrb -> ocm:s1_wstrb
	wire          mm_interconnect_1_ocm_axi_s1_wready;                                   // ocm:s1_wready -> mm_interconnect_1:ocm_axi_s1_wready
	wire    [9:0] mm_interconnect_1_ocm_axi_s1_rid;                                      // ocm:s1_rid -> mm_interconnect_1:ocm_axi_s1_rid
	wire          mm_interconnect_1_ocm_axi_s1_rready;                                   // mm_interconnect_1:ocm_axi_s1_rready -> ocm:s1_rready
	wire    [7:0] mm_interconnect_1_ocm_axi_s1_awlen;                                    // mm_interconnect_1:ocm_axi_s1_awlen -> ocm:s1_awlen
	wire          mm_interconnect_1_ocm_axi_s1_wvalid;                                   // mm_interconnect_1:ocm_axi_s1_wvalid -> ocm:s1_wvalid
	wire   [17:0] mm_interconnect_1_ocm_axi_s1_araddr;                                   // mm_interconnect_1:ocm_axi_s1_araddr -> ocm:s1_araddr
	wire  [127:0] mm_interconnect_1_ocm_axi_s1_wdata;                                    // mm_interconnect_1:ocm_axi_s1_wdata -> ocm:s1_wdata
	wire          mm_interconnect_1_ocm_axi_s1_arvalid;                                  // mm_interconnect_1:ocm_axi_s1_arvalid -> ocm:s1_arvalid
	wire    [9:0] mm_interconnect_1_ocm_axi_s1_arid;                                     // mm_interconnect_1:ocm_axi_s1_arid -> ocm:s1_arid
	wire   [17:0] mm_interconnect_1_ocm_axi_s1_awaddr;                                   // mm_interconnect_1:ocm_axi_s1_awaddr -> ocm:s1_awaddr
	wire    [1:0] mm_interconnect_1_ocm_axi_s1_bresp;                                    // ocm:s1_bresp -> mm_interconnect_1:ocm_axi_s1_bresp
	wire          mm_interconnect_1_ocm_axi_s1_arready;                                  // ocm:s1_arready -> mm_interconnect_1:ocm_axi_s1_arready
	wire  [127:0] mm_interconnect_1_ocm_axi_s1_rdata;                                    // ocm:s1_rdata -> mm_interconnect_1:ocm_axi_s1_rdata
	wire          mm_interconnect_1_ocm_axi_s1_awready;                                  // ocm:s1_awready -> mm_interconnect_1:ocm_axi_s1_awready
	wire    [1:0] mm_interconnect_1_ocm_axi_s1_arburst;                                  // mm_interconnect_1:ocm_axi_s1_arburst -> ocm:s1_arburst
	wire    [2:0] mm_interconnect_1_ocm_axi_s1_arsize;                                   // mm_interconnect_1:ocm_axi_s1_arsize -> ocm:s1_arsize
	wire          mm_interconnect_1_ocm_axi_s1_bready;                                   // mm_interconnect_1:ocm_axi_s1_bready -> ocm:s1_bready
	wire          mm_interconnect_1_ocm_axi_s1_rlast;                                    // ocm:s1_rlast -> mm_interconnect_1:ocm_axi_s1_rlast
	wire          mm_interconnect_1_ocm_axi_s1_wlast;                                    // mm_interconnect_1:ocm_axi_s1_wlast -> ocm:s1_wlast
	wire    [1:0] mm_interconnect_1_ocm_axi_s1_rresp;                                    // ocm:s1_rresp -> mm_interconnect_1:ocm_axi_s1_rresp
	wire    [9:0] mm_interconnect_1_ocm_axi_s1_awid;                                     // mm_interconnect_1:ocm_axi_s1_awid -> ocm:s1_awid
	wire    [9:0] mm_interconnect_1_ocm_axi_s1_bid;                                      // ocm:s1_bid -> mm_interconnect_1:ocm_axi_s1_bid
	wire          mm_interconnect_1_ocm_axi_s1_bvalid;                                   // ocm:s1_bvalid -> mm_interconnect_1:ocm_axi_s1_bvalid
	wire    [2:0] mm_interconnect_1_ocm_axi_s1_awsize;                                   // mm_interconnect_1:ocm_axi_s1_awsize -> ocm:s1_awsize
	wire          mm_interconnect_1_ocm_axi_s1_awvalid;                                  // mm_interconnect_1:ocm_axi_s1_awvalid -> ocm:s1_awvalid
	wire          mm_interconnect_1_ocm_axi_s1_rvalid;                                   // ocm:s1_rvalid -> mm_interconnect_1:ocm_axi_s1_rvalid
	wire   [31:0] mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_readdata;        // subsys_hps:usb31_phy_reconfig_slave_readdata -> mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_readdata
	wire          mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_waitrequest;     // subsys_hps:usb31_phy_reconfig_slave_waitrequest -> mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_waitrequest
	wire   [20:0] mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_address;         // mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_address -> subsys_hps:usb31_phy_reconfig_slave_address
	wire          mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_read;            // mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_read -> subsys_hps:usb31_phy_reconfig_slave_read
	wire    [3:0] mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_byteenable;      // mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_byteenable -> subsys_hps:usb31_phy_reconfig_slave_byteenable
	wire          mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_readdatavalid;   // subsys_hps:usb31_phy_reconfig_slave_readdatavalid -> mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_readdatavalid
	wire          mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_write;           // mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_write -> subsys_hps:usb31_phy_reconfig_slave_write
	wire   [31:0] mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_writedata;       // mm_interconnect_1:subsys_hps_usb31_phy_reconfig_slave_writedata -> subsys_hps:usb31_phy_reconfig_slave_writedata
	wire   [31:0] mm_interconnect_1_subsys_periph_pb_cpu_0_s0_readdata;                  // subsys_periph:pb_cpu_0_s0_readdata -> mm_interconnect_1:subsys_periph_pb_cpu_0_s0_readdata
	wire          mm_interconnect_1_subsys_periph_pb_cpu_0_s0_waitrequest;               // subsys_periph:pb_cpu_0_s0_waitrequest -> mm_interconnect_1:subsys_periph_pb_cpu_0_s0_waitrequest
	wire          mm_interconnect_1_subsys_periph_pb_cpu_0_s0_debugaccess;               // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_debugaccess -> subsys_periph:pb_cpu_0_s0_debugaccess
	wire   [16:0] mm_interconnect_1_subsys_periph_pb_cpu_0_s0_address;                   // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_address -> subsys_periph:pb_cpu_0_s0_address
	wire          mm_interconnect_1_subsys_periph_pb_cpu_0_s0_read;                      // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_read -> subsys_periph:pb_cpu_0_s0_read
	wire    [3:0] mm_interconnect_1_subsys_periph_pb_cpu_0_s0_byteenable;                // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_byteenable -> subsys_periph:pb_cpu_0_s0_byteenable
	wire          mm_interconnect_1_subsys_periph_pb_cpu_0_s0_readdatavalid;             // subsys_periph:pb_cpu_0_s0_readdatavalid -> mm_interconnect_1:subsys_periph_pb_cpu_0_s0_readdatavalid
	wire          mm_interconnect_1_subsys_periph_pb_cpu_0_s0_write;                     // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_write -> subsys_periph:pb_cpu_0_s0_write
	wire   [31:0] mm_interconnect_1_subsys_periph_pb_cpu_0_s0_writedata;                 // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_writedata -> subsys_periph:pb_cpu_0_s0_writedata
	wire    [0:0] mm_interconnect_1_subsys_periph_pb_cpu_0_s0_burstcount;                // mm_interconnect_1:subsys_periph_pb_cpu_0_s0_burstcount -> subsys_periph:pb_cpu_0_s0_burstcount
	wire   [31:0] subsys_debug_hps_f2sdram_master_readdata;                              // mm_interconnect_2:subsys_debug_hps_f2sdram_master_readdata -> subsys_debug:hps_f2sdram_master_readdata
	wire          subsys_debug_hps_f2sdram_master_waitrequest;                           // mm_interconnect_2:subsys_debug_hps_f2sdram_master_waitrequest -> subsys_debug:hps_f2sdram_master_waitrequest
	wire   [31:0] subsys_debug_hps_f2sdram_master_address;                               // subsys_debug:hps_f2sdram_master_address -> mm_interconnect_2:subsys_debug_hps_f2sdram_master_address
	wire          subsys_debug_hps_f2sdram_master_read;                                  // subsys_debug:hps_f2sdram_master_read -> mm_interconnect_2:subsys_debug_hps_f2sdram_master_read
	wire    [3:0] subsys_debug_hps_f2sdram_master_byteenable;                            // subsys_debug:hps_f2sdram_master_byteenable -> mm_interconnect_2:subsys_debug_hps_f2sdram_master_byteenable
	wire          subsys_debug_hps_f2sdram_master_readdatavalid;                         // mm_interconnect_2:subsys_debug_hps_f2sdram_master_readdatavalid -> subsys_debug:hps_f2sdram_master_readdatavalid
	wire          subsys_debug_hps_f2sdram_master_write;                                 // subsys_debug:hps_f2sdram_master_write -> mm_interconnect_2:subsys_debug_hps_f2sdram_master_write
	wire   [31:0] subsys_debug_hps_f2sdram_master_writedata;                             // subsys_debug:hps_f2sdram_master_writedata -> mm_interconnect_2:subsys_debug_hps_f2sdram_master_writedata
	wire   [31:0] mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_readdata;      // ext_hps_f2sdram_master:avs_s0_readdata -> mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_readdata
	wire          mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_waitrequest;   // ext_hps_f2sdram_master:avs_s0_waitrequest -> mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_waitrequest
	wire   [29:0] mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_address;       // mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_address -> ext_hps_f2sdram_master:avs_s0_address
	wire          mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_read;          // mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_read -> ext_hps_f2sdram_master:avs_s0_read
	wire    [3:0] mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_byteenable;    // mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_byteenable -> ext_hps_f2sdram_master:avs_s0_byteenable
	wire          mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_readdatavalid; // ext_hps_f2sdram_master:avs_s0_readdatavalid -> mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_readdatavalid
	wire          mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_write;         // mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_write -> ext_hps_f2sdram_master:avs_s0_write
	wire   [31:0] mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_writedata;     // mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_writedata -> ext_hps_f2sdram_master:avs_s0_writedata
	wire    [0:0] mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_burstcount;    // mm_interconnect_2:ext_hps_f2sdram_master_windowed_slave_burstcount -> ext_hps_f2sdram_master:avs_s0_burstcount
	wire          irq_mapper_receiver0_irq;                                              // subsys_periph:button_pio_irq_irq -> irq_mapper:receiver0_irq
	wire          irq_mapper_receiver1_irq;                                              // subsys_periph:dipsw_pio_irq_irq -> irq_mapper:receiver1_irq
	wire   [62:0] subsys_hps_f2h_irq_in_irq;                                             // irq_mapper:sender_irq -> subsys_hps:f2h_irq_in_irq
	wire          rst_controller_reset_out_reset;                                        // rst_controller:reset_out -> [ext_hps_f2sdram_master:reset, ocm:reset, subsys_hps:f2sdram_adapter_rst_reset]
	wire          rst_controller_reset_out_reset_req;                                    // rst_controller:reset_req -> [ocm:reset_req, rst_translator:reset_req_in]
	wire          rst_controller_001_reset_out_reset;                                    // rst_controller_001:reset_out -> [mm_interconnect_0:ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_0:ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset, mm_interconnect_1:ocm_reset1_reset_bridge_in_reset_reset, mm_interconnect_1:subsys_debug_reset_reset_bridge_in_reset_reset, mm_interconnect_2:subsys_debug_reset_reset_bridge_in_reset_reset, subsys_debug:reset_reset_n, subsys_periph:reset_reset_n]

	clk_100 clk_100 (
		.in_clk  (clk_100_clk),         //   input,  width = 1,  in_clk.clk
		.out_clk (clk_100_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	ext_hps_f2sdram_master ext_hps_f2sdram_master (
		.clk                  (clk_100_out_clk_clk),                                                   //   input,   width = 1,           clock.clk
		.reset                (rst_controller_reset_out_reset),                                        //   input,   width = 1,           reset.reset
		.avs_s0_address       (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_address),       //   input,  width = 30,  windowed_slave.address
		.avs_s0_read          (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_read),          //   input,   width = 1,                .read
		.avs_s0_readdata      (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_readdata),      //  output,  width = 32,                .readdata
		.avs_s0_write         (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_write),         //   input,   width = 1,                .write
		.avs_s0_writedata     (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_writedata),     //   input,  width = 32,                .writedata
		.avs_s0_readdatavalid (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_readdatavalid), //  output,   width = 1,                .readdatavalid
		.avs_s0_waitrequest   (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_waitrequest),   //  output,   width = 1,                .waitrequest
		.avs_s0_byteenable    (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_byteenable),    //   input,   width = 4,                .byteenable
		.avs_s0_burstcount    (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_burstcount),    //   input,   width = 1,                .burstcount
		.avm_m0_address       (ext_hps_f2sdram_master_expanded_master_address),                        //  output,  width = 33, expanded_master.address
		.avm_m0_read          (ext_hps_f2sdram_master_expanded_master_read),                           //  output,   width = 1,                .read
		.avm_m0_waitrequest   (ext_hps_f2sdram_master_expanded_master_waitrequest),                    //   input,   width = 1,                .waitrequest
		.avm_m0_readdata      (ext_hps_f2sdram_master_expanded_master_readdata),                       //   input,  width = 32,                .readdata
		.avm_m0_write         (ext_hps_f2sdram_master_expanded_master_write),                          //  output,   width = 1,                .write
		.avm_m0_writedata     (ext_hps_f2sdram_master_expanded_master_writedata),                      //  output,  width = 32,                .writedata
		.avm_m0_readdatavalid (ext_hps_f2sdram_master_expanded_master_readdatavalid),                  //   input,   width = 1,                .readdatavalid
		.avm_m0_byteenable    (ext_hps_f2sdram_master_expanded_master_byteenable),                     //  output,   width = 4,                .byteenable
		.avm_m0_burstcount    (ext_hps_f2sdram_master_expanded_master_burstcount)                      //  output,   width = 1,                .burstcount
	);

	ocm ocm (
		.clk        (clk_100_out_clk_clk),                  //   input,    width = 1,   clk1.clk
		.s1_arid    (mm_interconnect_1_ocm_axi_s1_arid),    //   input,   width = 10, axi_s1.arid
		.s1_araddr  (mm_interconnect_1_ocm_axi_s1_araddr),  //   input,   width = 18,       .araddr
		.s1_arlen   (mm_interconnect_1_ocm_axi_s1_arlen),   //   input,    width = 8,       .arlen
		.s1_arsize  (mm_interconnect_1_ocm_axi_s1_arsize),  //   input,    width = 3,       .arsize
		.s1_arburst (mm_interconnect_1_ocm_axi_s1_arburst), //   input,    width = 2,       .arburst
		.s1_arready (mm_interconnect_1_ocm_axi_s1_arready), //  output,    width = 1,       .arready
		.s1_arvalid (mm_interconnect_1_ocm_axi_s1_arvalid), //   input,    width = 1,       .arvalid
		.s1_awid    (mm_interconnect_1_ocm_axi_s1_awid),    //   input,   width = 10,       .awid
		.s1_awaddr  (mm_interconnect_1_ocm_axi_s1_awaddr),  //   input,   width = 18,       .awaddr
		.s1_awlen   (mm_interconnect_1_ocm_axi_s1_awlen),   //   input,    width = 8,       .awlen
		.s1_awsize  (mm_interconnect_1_ocm_axi_s1_awsize),  //   input,    width = 3,       .awsize
		.s1_awburst (mm_interconnect_1_ocm_axi_s1_awburst), //   input,    width = 2,       .awburst
		.s1_awready (mm_interconnect_1_ocm_axi_s1_awready), //  output,    width = 1,       .awready
		.s1_awvalid (mm_interconnect_1_ocm_axi_s1_awvalid), //   input,    width = 1,       .awvalid
		.s1_rid     (mm_interconnect_1_ocm_axi_s1_rid),     //  output,   width = 10,       .rid
		.s1_rdata   (mm_interconnect_1_ocm_axi_s1_rdata),   //  output,  width = 128,       .rdata
		.s1_rlast   (mm_interconnect_1_ocm_axi_s1_rlast),   //  output,    width = 1,       .rlast
		.s1_rready  (mm_interconnect_1_ocm_axi_s1_rready),  //   input,    width = 1,       .rready
		.s1_rvalid  (mm_interconnect_1_ocm_axi_s1_rvalid),  //  output,    width = 1,       .rvalid
		.s1_rresp   (mm_interconnect_1_ocm_axi_s1_rresp),   //  output,    width = 2,       .rresp
		.s1_wdata   (mm_interconnect_1_ocm_axi_s1_wdata),   //   input,  width = 128,       .wdata
		.s1_wstrb   (mm_interconnect_1_ocm_axi_s1_wstrb),   //   input,   width = 16,       .wstrb
		.s1_wlast   (mm_interconnect_1_ocm_axi_s1_wlast),   //   input,    width = 1,       .wlast
		.s1_wready  (mm_interconnect_1_ocm_axi_s1_wready),  //  output,    width = 1,       .wready
		.s1_wvalid  (mm_interconnect_1_ocm_axi_s1_wvalid),  //   input,    width = 1,       .wvalid
		.s1_bid     (mm_interconnect_1_ocm_axi_s1_bid),     //  output,   width = 10,       .bid
		.s1_bresp   (mm_interconnect_1_ocm_axi_s1_bresp),   //  output,    width = 2,       .bresp
		.s1_bready  (mm_interconnect_1_ocm_axi_s1_bready),  //   input,    width = 1,       .bready
		.s1_bvalid  (mm_interconnect_1_ocm_axi_s1_bvalid),  //  output,    width = 1,       .bvalid
		.reset      (rst_controller_reset_out_reset),       //   input,    width = 1, reset1.reset
		.reset_req  (rst_controller_reset_out_reset_req)    //   input,    width = 1,       .reset_req
	);

	rst_in rst_in (
		.in_reset_n  (reset_reset_n),          //   input,  width = 1,  in_reset.reset_n
		.out_reset_n (rst_in_out_reset_reset)  //  output,  width = 1, out_reset.reset_n
	);

	user_rst_clkgate_0 user_rst_clkgate_0 (
		.ninit_done (ninit_done_ninit_done)  //  output,  width = 1, ninit_done.ninit_done
	);

	jtag_subsys subsys_debug (
		.fpga_m_master_address            (subsys_debug_fpga_m_master_address),            //  output,  width = 32,      fpga_m_master.address
		.fpga_m_master_readdata           (subsys_debug_fpga_m_master_readdata),           //   input,  width = 32,                   .readdata
		.fpga_m_master_read               (subsys_debug_fpga_m_master_read),               //  output,   width = 1,                   .read
		.fpga_m_master_write              (subsys_debug_fpga_m_master_write),              //  output,   width = 1,                   .write
		.fpga_m_master_writedata          (subsys_debug_fpga_m_master_writedata),          //  output,  width = 32,                   .writedata
		.fpga_m_master_waitrequest        (subsys_debug_fpga_m_master_waitrequest),        //   input,   width = 1,                   .waitrequest
		.fpga_m_master_readdatavalid      (subsys_debug_fpga_m_master_readdatavalid),      //   input,   width = 1,                   .readdatavalid
		.fpga_m_master_byteenable         (subsys_debug_fpga_m_master_byteenable),         //  output,   width = 4,                   .byteenable
		.hps_f2sdram_master_address       (subsys_debug_hps_f2sdram_master_address),       //  output,  width = 32, hps_f2sdram_master.address
		.hps_f2sdram_master_readdata      (subsys_debug_hps_f2sdram_master_readdata),      //   input,  width = 32,                   .readdata
		.hps_f2sdram_master_read          (subsys_debug_hps_f2sdram_master_read),          //  output,   width = 1,                   .read
		.hps_f2sdram_master_write         (subsys_debug_hps_f2sdram_master_write),         //  output,   width = 1,                   .write
		.hps_f2sdram_master_writedata     (subsys_debug_hps_f2sdram_master_writedata),     //  output,  width = 32,                   .writedata
		.hps_f2sdram_master_waitrequest   (subsys_debug_hps_f2sdram_master_waitrequest),   //   input,   width = 1,                   .waitrequest
		.hps_f2sdram_master_readdatavalid (subsys_debug_hps_f2sdram_master_readdatavalid), //   input,   width = 1,                   .readdatavalid
		.hps_f2sdram_master_byteenable    (subsys_debug_hps_f2sdram_master_byteenable),    //  output,   width = 4,                   .byteenable
		.clk_clk                          (clk_100_out_clk_clk),                           //   input,   width = 1,                clk.clk
		.reset_reset_n                    (~rst_controller_001_reset_out_reset)            //   input,   width = 1,              reset.reset_n
	);

	hps_subsys subsys_hps (
		.h2f_reset_reset                        (),                                                                    //  output,    width = 1,                h2f_reset.reset
		.hps2fpga_clk_clk                       (clk_100_out_clk_clk),                                                 //   input,    width = 1,             hps2fpga_clk.clk
		.hps2fpga_rst_reset                     (~rst_in_out_reset_reset),                                             //   input,    width = 1,             hps2fpga_rst.reset
		.hps2fpga_awid                          (subsys_hps_hps2fpga_awid),                                            //  output,    width = 4,                 hps2fpga.awid
		.hps2fpga_awaddr                        (subsys_hps_hps2fpga_awaddr),                                          //  output,   width = 38,                         .awaddr
		.hps2fpga_awlen                         (subsys_hps_hps2fpga_awlen),                                           //  output,    width = 8,                         .awlen
		.hps2fpga_awsize                        (subsys_hps_hps2fpga_awsize),                                          //  output,    width = 3,                         .awsize
		.hps2fpga_awburst                       (subsys_hps_hps2fpga_awburst),                                         //  output,    width = 2,                         .awburst
		.hps2fpga_awlock                        (subsys_hps_hps2fpga_awlock),                                          //  output,    width = 1,                         .awlock
		.hps2fpga_awcache                       (subsys_hps_hps2fpga_awcache),                                         //  output,    width = 4,                         .awcache
		.hps2fpga_awprot                        (subsys_hps_hps2fpga_awprot),                                          //  output,    width = 3,                         .awprot
		.hps2fpga_awvalid                       (subsys_hps_hps2fpga_awvalid),                                         //  output,    width = 1,                         .awvalid
		.hps2fpga_awready                       (subsys_hps_hps2fpga_awready),                                         //   input,    width = 1,                         .awready
		.hps2fpga_wdata                         (subsys_hps_hps2fpga_wdata),                                           //  output,  width = 128,                         .wdata
		.hps2fpga_wstrb                         (subsys_hps_hps2fpga_wstrb),                                           //  output,   width = 16,                         .wstrb
		.hps2fpga_wlast                         (subsys_hps_hps2fpga_wlast),                                           //  output,    width = 1,                         .wlast
		.hps2fpga_wvalid                        (subsys_hps_hps2fpga_wvalid),                                          //  output,    width = 1,                         .wvalid
		.hps2fpga_wready                        (subsys_hps_hps2fpga_wready),                                          //   input,    width = 1,                         .wready
		.hps2fpga_bid                           (subsys_hps_hps2fpga_bid),                                             //   input,    width = 4,                         .bid
		.hps2fpga_bresp                         (subsys_hps_hps2fpga_bresp),                                           //   input,    width = 2,                         .bresp
		.hps2fpga_bvalid                        (subsys_hps_hps2fpga_bvalid),                                          //   input,    width = 1,                         .bvalid
		.hps2fpga_bready                        (subsys_hps_hps2fpga_bready),                                          //  output,    width = 1,                         .bready
		.hps2fpga_arid                          (subsys_hps_hps2fpga_arid),                                            //  output,    width = 4,                         .arid
		.hps2fpga_araddr                        (subsys_hps_hps2fpga_araddr),                                          //  output,   width = 38,                         .araddr
		.hps2fpga_arlen                         (subsys_hps_hps2fpga_arlen),                                           //  output,    width = 8,                         .arlen
		.hps2fpga_arsize                        (subsys_hps_hps2fpga_arsize),                                          //  output,    width = 3,                         .arsize
		.hps2fpga_arburst                       (subsys_hps_hps2fpga_arburst),                                         //  output,    width = 2,                         .arburst
		.hps2fpga_arlock                        (subsys_hps_hps2fpga_arlock),                                          //  output,    width = 1,                         .arlock
		.hps2fpga_arcache                       (subsys_hps_hps2fpga_arcache),                                         //  output,    width = 4,                         .arcache
		.hps2fpga_arprot                        (subsys_hps_hps2fpga_arprot),                                          //  output,    width = 3,                         .arprot
		.hps2fpga_arvalid                       (subsys_hps_hps2fpga_arvalid),                                         //  output,    width = 1,                         .arvalid
		.hps2fpga_arready                       (subsys_hps_hps2fpga_arready),                                         //   input,    width = 1,                         .arready
		.hps2fpga_rid                           (subsys_hps_hps2fpga_rid),                                             //   input,    width = 4,                         .rid
		.hps2fpga_rdata                         (subsys_hps_hps2fpga_rdata),                                           //   input,  width = 128,                         .rdata
		.hps2fpga_rresp                         (subsys_hps_hps2fpga_rresp),                                           //   input,    width = 2,                         .rresp
		.hps2fpga_rlast                         (subsys_hps_hps2fpga_rlast),                                           //   input,    width = 1,                         .rlast
		.hps2fpga_rvalid                        (subsys_hps_hps2fpga_rvalid),                                          //   input,    width = 1,                         .rvalid
		.hps2fpga_rready                        (subsys_hps_hps2fpga_rready),                                          //  output,    width = 1,                         .rready
		.lwhps2fpga_clk_clk                     (clk_100_out_clk_clk),                                                 //   input,    width = 1,           lwhps2fpga_clk.clk
		.lwhps2fpga_rst_reset                   (~rst_in_out_reset_reset),                                             //   input,    width = 1,           lwhps2fpga_rst.reset
		.lwhps2fpga_awid                        (subsys_hps_lwhps2fpga_awid),                                          //  output,    width = 4,               lwhps2fpga.awid
		.lwhps2fpga_awaddr                      (subsys_hps_lwhps2fpga_awaddr),                                        //  output,   width = 29,                         .awaddr
		.lwhps2fpga_awlen                       (subsys_hps_lwhps2fpga_awlen),                                         //  output,    width = 8,                         .awlen
		.lwhps2fpga_awsize                      (subsys_hps_lwhps2fpga_awsize),                                        //  output,    width = 3,                         .awsize
		.lwhps2fpga_awburst                     (subsys_hps_lwhps2fpga_awburst),                                       //  output,    width = 2,                         .awburst
		.lwhps2fpga_awlock                      (subsys_hps_lwhps2fpga_awlock),                                        //  output,    width = 1,                         .awlock
		.lwhps2fpga_awcache                     (subsys_hps_lwhps2fpga_awcache),                                       //  output,    width = 4,                         .awcache
		.lwhps2fpga_awprot                      (subsys_hps_lwhps2fpga_awprot),                                        //  output,    width = 3,                         .awprot
		.lwhps2fpga_awvalid                     (subsys_hps_lwhps2fpga_awvalid),                                       //  output,    width = 1,                         .awvalid
		.lwhps2fpga_awready                     (subsys_hps_lwhps2fpga_awready),                                       //   input,    width = 1,                         .awready
		.lwhps2fpga_wdata                       (subsys_hps_lwhps2fpga_wdata),                                         //  output,   width = 32,                         .wdata
		.lwhps2fpga_wstrb                       (subsys_hps_lwhps2fpga_wstrb),                                         //  output,    width = 4,                         .wstrb
		.lwhps2fpga_wlast                       (subsys_hps_lwhps2fpga_wlast),                                         //  output,    width = 1,                         .wlast
		.lwhps2fpga_wvalid                      (subsys_hps_lwhps2fpga_wvalid),                                        //  output,    width = 1,                         .wvalid
		.lwhps2fpga_wready                      (subsys_hps_lwhps2fpga_wready),                                        //   input,    width = 1,                         .wready
		.lwhps2fpga_bid                         (subsys_hps_lwhps2fpga_bid),                                           //   input,    width = 4,                         .bid
		.lwhps2fpga_bresp                       (subsys_hps_lwhps2fpga_bresp),                                         //   input,    width = 2,                         .bresp
		.lwhps2fpga_bvalid                      (subsys_hps_lwhps2fpga_bvalid),                                        //   input,    width = 1,                         .bvalid
		.lwhps2fpga_bready                      (subsys_hps_lwhps2fpga_bready),                                        //  output,    width = 1,                         .bready
		.lwhps2fpga_arid                        (subsys_hps_lwhps2fpga_arid),                                          //  output,    width = 4,                         .arid
		.lwhps2fpga_araddr                      (subsys_hps_lwhps2fpga_araddr),                                        //  output,   width = 29,                         .araddr
		.lwhps2fpga_arlen                       (subsys_hps_lwhps2fpga_arlen),                                         //  output,    width = 8,                         .arlen
		.lwhps2fpga_arsize                      (subsys_hps_lwhps2fpga_arsize),                                        //  output,    width = 3,                         .arsize
		.lwhps2fpga_arburst                     (subsys_hps_lwhps2fpga_arburst),                                       //  output,    width = 2,                         .arburst
		.lwhps2fpga_arlock                      (subsys_hps_lwhps2fpga_arlock),                                        //  output,    width = 1,                         .arlock
		.lwhps2fpga_arcache                     (subsys_hps_lwhps2fpga_arcache),                                       //  output,    width = 4,                         .arcache
		.lwhps2fpga_arprot                      (subsys_hps_lwhps2fpga_arprot),                                        //  output,    width = 3,                         .arprot
		.lwhps2fpga_arvalid                     (subsys_hps_lwhps2fpga_arvalid),                                       //  output,    width = 1,                         .arvalid
		.lwhps2fpga_arready                     (subsys_hps_lwhps2fpga_arready),                                       //   input,    width = 1,                         .arready
		.lwhps2fpga_rid                         (subsys_hps_lwhps2fpga_rid),                                           //   input,    width = 4,                         .rid
		.lwhps2fpga_rdata                       (subsys_hps_lwhps2fpga_rdata),                                         //   input,   width = 32,                         .rdata
		.lwhps2fpga_rresp                       (subsys_hps_lwhps2fpga_rresp),                                         //   input,    width = 2,                         .rresp
		.lwhps2fpga_rlast                       (subsys_hps_lwhps2fpga_rlast),                                         //   input,    width = 1,                         .rlast
		.lwhps2fpga_rvalid                      (subsys_hps_lwhps2fpga_rvalid),                                        //   input,    width = 1,                         .rvalid
		.lwhps2fpga_rready                      (subsys_hps_lwhps2fpga_rready),                                        //  output,    width = 1,                         .rready
		.hps_io_hps_osc_clk                     (hps_io_hps_osc_clk),                                                  //   input,    width = 1,                   hps_io.hps_osc_clk
		.hps_io_sdmmc_data0                     (hps_io_sdmmc_data0),                                                  //   inout,    width = 1,                         .sdmmc_data0
		.hps_io_sdmmc_data1                     (hps_io_sdmmc_data1),                                                  //   inout,    width = 1,                         .sdmmc_data1
		.hps_io_sdmmc_cclk                      (hps_io_sdmmc_cclk),                                                   //  output,    width = 1,                         .sdmmc_cclk
		.hps_io_sdmmc_data2                     (hps_io_sdmmc_data2),                                                  //   inout,    width = 1,                         .sdmmc_data2
		.hps_io_sdmmc_data3                     (hps_io_sdmmc_data3),                                                  //   inout,    width = 1,                         .sdmmc_data3
		.hps_io_sdmmc_cmd                       (hps_io_sdmmc_cmd),                                                    //   inout,    width = 1,                         .sdmmc_cmd
		.hps_io_usb1_clk                        (hps_io_usb1_clk),                                                     //   input,    width = 1,                         .usb1_clk
		.hps_io_usb1_stp                        (hps_io_usb1_stp),                                                     //  output,    width = 1,                         .usb1_stp
		.hps_io_usb1_dir                        (hps_io_usb1_dir),                                                     //   input,    width = 1,                         .usb1_dir
		.hps_io_usb1_data0                      (hps_io_usb1_data0),                                                   //   inout,    width = 1,                         .usb1_data0
		.hps_io_usb1_data1                      (hps_io_usb1_data1),                                                   //   inout,    width = 1,                         .usb1_data1
		.hps_io_usb1_nxt                        (hps_io_usb1_nxt),                                                     //   input,    width = 1,                         .usb1_nxt
		.hps_io_usb1_data2                      (hps_io_usb1_data2),                                                   //   inout,    width = 1,                         .usb1_data2
		.hps_io_usb1_data3                      (hps_io_usb1_data3),                                                   //   inout,    width = 1,                         .usb1_data3
		.hps_io_usb1_data4                      (hps_io_usb1_data4),                                                   //   inout,    width = 1,                         .usb1_data4
		.hps_io_usb1_data5                      (hps_io_usb1_data5),                                                   //   inout,    width = 1,                         .usb1_data5
		.hps_io_usb1_data6                      (hps_io_usb1_data6),                                                   //   inout,    width = 1,                         .usb1_data6
		.hps_io_usb1_data7                      (hps_io_usb1_data7),                                                   //   inout,    width = 1,                         .usb1_data7
		.hps_io_emac2_tx_clk                    (hps_io_emac2_tx_clk),                                                 //  output,    width = 1,                         .emac2_tx_clk
		.hps_io_emac2_tx_ctl                    (hps_io_emac2_tx_ctl),                                                 //  output,    width = 1,                         .emac2_tx_ctl
		.hps_io_emac2_rx_clk                    (hps_io_emac2_rx_clk),                                                 //   input,    width = 1,                         .emac2_rx_clk
		.hps_io_emac2_rx_ctl                    (hps_io_emac2_rx_ctl),                                                 //   input,    width = 1,                         .emac2_rx_ctl
		.hps_io_emac2_txd0                      (hps_io_emac2_txd0),                                                   //  output,    width = 1,                         .emac2_txd0
		.hps_io_emac2_txd1                      (hps_io_emac2_txd1),                                                   //  output,    width = 1,                         .emac2_txd1
		.hps_io_emac2_rxd0                      (hps_io_emac2_rxd0),                                                   //   input,    width = 1,                         .emac2_rxd0
		.hps_io_emac2_rxd1                      (hps_io_emac2_rxd1),                                                   //   input,    width = 1,                         .emac2_rxd1
		.hps_io_emac2_txd2                      (hps_io_emac2_txd2),                                                   //  output,    width = 1,                         .emac2_txd2
		.hps_io_emac2_txd3                      (hps_io_emac2_txd3),                                                   //  output,    width = 1,                         .emac2_txd3
		.hps_io_emac2_rxd2                      (hps_io_emac2_rxd2),                                                   //   input,    width = 1,                         .emac2_rxd2
		.hps_io_emac2_rxd3                      (hps_io_emac2_rxd3),                                                   //   input,    width = 1,                         .emac2_rxd3
		.hps_io_mdio2_mdio                      (hps_io_mdio2_mdio),                                                   //   inout,    width = 1,                         .mdio2_mdio
		.hps_io_mdio2_mdc                       (hps_io_mdio2_mdc),                                                    //  output,    width = 1,                         .mdio2_mdc
		.hps_io_uart0_tx                        (hps_io_uart0_tx),                                                     //  output,    width = 1,                         .uart0_tx
		.hps_io_uart0_rx                        (hps_io_uart0_rx),                                                     //   input,    width = 1,                         .uart0_rx
		.hps_io_i2c0_sda                        (hps_io_i2c0_sda),                                                     //   inout,    width = 1,                         .i2c0_sda
		.hps_io_i2c0_scl                        (hps_io_i2c0_scl),                                                     //   inout,    width = 1,                         .i2c0_scl
		.hps_io_gpio0                           (hps_io_gpio0),                                                        //   inout,    width = 1,                         .gpio0
		.hps_io_gpio1                           (hps_io_gpio1),                                                        //   inout,    width = 1,                         .gpio1
		.hps_io_gpio8                           (hps_io_gpio8),                                                        //   inout,    width = 1,                         .gpio8
		.hps_io_gpio9                           (hps_io_gpio9),                                                        //   inout,    width = 1,                         .gpio9
		.hps_io_gpio10                          (hps_io_gpio10),                                                       //   inout,    width = 1,                         .gpio10
		.hps_io_gpio11                          (hps_io_gpio11),                                                       //   inout,    width = 1,                         .gpio11
		.hps_io_gpio28                          (hps_io_gpio28),                                                       //   inout,    width = 1,                         .gpio28
		.usb31_io_vbus_det                      (usb31_io_vbus_det),                                                   //   input,    width = 1,                 usb31_io.vbus_det
		.usb31_io_flt_bar                       (usb31_io_flt_bar),                                                    //   input,    width = 1,                         .flt_bar
		.usb31_io_usb_ctrl                      (usb31_io_usb_ctrl),                                                   //  output,    width = 2,                         .usb_ctrl
		.usb31_io_usb31_id                      (usb31_io_usb31_id),                                                   //   input,    width = 1,                         .usb31_id
		.f2h_irq_in_irq                         (subsys_hps_f2h_irq_in_irq),                                           //   input,   width = 63,               f2h_irq_in.irq
		.usb31_phy_pma_cpu_clk_clk              (usb31_phy_pma_cpu_clk_clk),                                           //   input,    width = 1,    usb31_phy_pma_cpu_clk.clk
		.usb31_phy_refclk_p_clk                 (usb31_phy_refclk_p_clk),                                              //   input,    width = 1,       usb31_phy_refclk_p.clk
		.usb31_phy_refclk_n_clk                 (usb31_phy_refclk_n_clk),                                              //   input,    width = 1,       usb31_phy_refclk_n.clk
		.usb31_phy_rx_serial_n_i_rx_serial_n    (usb31_phy_rx_serial_n_i_rx_serial_n),                                 //   input,    width = 1,    usb31_phy_rx_serial_n.i_rx_serial_n
		.usb31_phy_rx_serial_p_i_rx_serial_p    (usb31_phy_rx_serial_p_i_rx_serial_p),                                 //   input,    width = 1,    usb31_phy_rx_serial_p.i_rx_serial_p
		.usb31_phy_tx_serial_n_o_tx_serial_n    (usb31_phy_tx_serial_n_o_tx_serial_n),                                 //  output,    width = 1,    usb31_phy_tx_serial_n.o_tx_serial_n
		.usb31_phy_tx_serial_p_o_tx_serial_p    (usb31_phy_tx_serial_p_o_tx_serial_p),                                 //  output,    width = 1,    usb31_phy_tx_serial_p.o_tx_serial_p
		.usb31_phy_reconfig_rst_reset           (~rst_in_out_reset_reset),                                             //   input,    width = 1,   usb31_phy_reconfig_rst.reset
		.usb31_phy_reconfig_clk_clk             (clk_100_out_clk_clk),                                                 //   input,    width = 1,   usb31_phy_reconfig_clk.clk
		.usb31_phy_reconfig_slave_address       (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_address),       //   input,   width = 21, usb31_phy_reconfig_slave.address
		.usb31_phy_reconfig_slave_byteenable    (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_byteenable),    //   input,    width = 4,                         .byteenable
		.usb31_phy_reconfig_slave_readdatavalid (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_readdatavalid), //  output,    width = 1,                         .readdatavalid
		.usb31_phy_reconfig_slave_read          (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_read),          //   input,    width = 1,                         .read
		.usb31_phy_reconfig_slave_write         (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_write),         //   input,    width = 1,                         .write
		.usb31_phy_reconfig_slave_readdata      (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_readdata),      //  output,   width = 32,                         .readdata
		.usb31_phy_reconfig_slave_writedata     (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_writedata),     //   input,   width = 32,                         .writedata
		.usb31_phy_reconfig_slave_waitrequest   (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_waitrequest),   //  output,    width = 1,                         .waitrequest
		.f2sdram_clk_clk                        (clk_100_out_clk_clk),                                                 //   input,    width = 1,              f2sdram_clk.clk
		.f2sdram_rst_reset                      (~rst_in_out_reset_reset),                                             //   input,    width = 1,              f2sdram_rst.reset
		.emif_hps_emif_mem_0_mem_ck_t           (emif_hps_emif_mem_0_mem_ck_t),                                        //  output,    width = 1,      emif_hps_emif_mem_0.mem_ck_t
		.emif_hps_emif_mem_0_mem_ck_c           (emif_hps_emif_mem_0_mem_ck_c),                                        //  output,    width = 1,                         .mem_ck_c
		.emif_hps_emif_mem_0_mem_cke            (emif_hps_emif_mem_0_mem_cke),                                         //  output,    width = 1,                         .mem_cke
		.emif_hps_emif_mem_0_mem_odt            (emif_hps_emif_mem_0_mem_odt),                                         //  output,    width = 1,                         .mem_odt
		.emif_hps_emif_mem_0_mem_cs_n           (emif_hps_emif_mem_0_mem_cs_n),                                        //  output,    width = 1,                         .mem_cs_n
		.emif_hps_emif_mem_0_mem_a              (emif_hps_emif_mem_0_mem_a),                                           //  output,   width = 17,                         .mem_a
		.emif_hps_emif_mem_0_mem_ba             (emif_hps_emif_mem_0_mem_ba),                                          //  output,    width = 2,                         .mem_ba
		.emif_hps_emif_mem_0_mem_bg             (emif_hps_emif_mem_0_mem_bg),                                          //  output,    width = 1,                         .mem_bg
		.emif_hps_emif_mem_0_mem_act_n          (emif_hps_emif_mem_0_mem_act_n),                                       //  output,    width = 1,                         .mem_act_n
		.emif_hps_emif_mem_0_mem_par            (emif_hps_emif_mem_0_mem_par),                                         //  output,    width = 1,                         .mem_par
		.emif_hps_emif_mem_0_mem_alert_n        (emif_hps_emif_mem_0_mem_alert_n),                                     //   input,    width = 1,                         .mem_alert_n
		.emif_hps_emif_mem_0_mem_reset_n        (emif_hps_emif_mem_0_mem_reset_n),                                     //  output,    width = 1,                         .mem_reset_n
		.emif_hps_emif_mem_0_mem_dq             (emif_hps_emif_mem_0_mem_dq),                                          //   inout,   width = 32,                         .mem_dq
		.emif_hps_emif_mem_0_mem_dqs_t          (emif_hps_emif_mem_0_mem_dqs_t),                                       //   inout,    width = 4,                         .mem_dqs_t
		.emif_hps_emif_mem_0_mem_dqs_c          (emif_hps_emif_mem_0_mem_dqs_c),                                       //   inout,    width = 4,                         .mem_dqs_c
		.emif_hps_emif_mem_0_mem_dbi_n          (emif_hps_emif_mem_0_mem_dbi_n),                                       //   inout,    width = 4,                         .mem_dbi_n
		.emif_hps_emif_oct_0_oct_rzqin          (emif_hps_emif_oct_0_oct_rzqin),                                       //   input,    width = 1,      emif_hps_emif_oct_0.oct_rzqin
		.emif_hps_emif_ref_clk_0_clk            (emif_hps_emif_ref_clk_0_clk),                                         //   input,    width = 1,  emif_hps_emif_ref_clk_0.clk
		.f2sdram_adapter_clk_clk                (clk_100_out_clk_clk),                                                 //   input,    width = 1,      f2sdram_adapter_clk.clk
		.f2sdram_adapter_rst_reset              (rst_controller_reset_out_reset),                                      //   input,    width = 1,      f2sdram_adapter_rst.reset
		.f2sdram_adapter_axi4_sub_araddr        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_araddr),        //   input,   width = 32, f2sdram_adapter_axi4_sub.araddr
		.f2sdram_adapter_axi4_sub_arburst       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arburst),       //   input,    width = 2,                         .arburst
		.f2sdram_adapter_axi4_sub_arcache       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arcache),       //   input,    width = 4,                         .arcache
		.f2sdram_adapter_axi4_sub_arid          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arid),          //   input,    width = 5,                         .arid
		.f2sdram_adapter_axi4_sub_arlen         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arlen),         //   input,    width = 8,                         .arlen
		.f2sdram_adapter_axi4_sub_arlock        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arlock),        //   input,    width = 1,                         .arlock
		.f2sdram_adapter_axi4_sub_arprot        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arprot),        //   input,    width = 3,                         .arprot
		.f2sdram_adapter_axi4_sub_arqos         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arqos),         //   input,    width = 4,                         .arqos
		.f2sdram_adapter_axi4_sub_arready       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arready),       //  output,    width = 1,                         .arready
		.f2sdram_adapter_axi4_sub_arsize        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arsize),        //   input,    width = 3,                         .arsize
		.f2sdram_adapter_axi4_sub_arvalid       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arvalid),       //   input,    width = 1,                         .arvalid
		.f2sdram_adapter_axi4_sub_awaddr        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awaddr),        //   input,   width = 32,                         .awaddr
		.f2sdram_adapter_axi4_sub_awburst       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awburst),       //   input,    width = 2,                         .awburst
		.f2sdram_adapter_axi4_sub_awcache       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awcache),       //   input,    width = 4,                         .awcache
		.f2sdram_adapter_axi4_sub_awid          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awid),          //   input,    width = 5,                         .awid
		.f2sdram_adapter_axi4_sub_awlen         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awlen),         //   input,    width = 8,                         .awlen
		.f2sdram_adapter_axi4_sub_awlock        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awlock),        //   input,    width = 1,                         .awlock
		.f2sdram_adapter_axi4_sub_awprot        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awprot),        //   input,    width = 3,                         .awprot
		.f2sdram_adapter_axi4_sub_awqos         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awqos),         //   input,    width = 4,                         .awqos
		.f2sdram_adapter_axi4_sub_awready       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awready),       //  output,    width = 1,                         .awready
		.f2sdram_adapter_axi4_sub_awsize        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awsize),        //   input,    width = 3,                         .awsize
		.f2sdram_adapter_axi4_sub_awvalid       (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awvalid),       //   input,    width = 1,                         .awvalid
		.f2sdram_adapter_axi4_sub_bid           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bid),           //  output,    width = 5,                         .bid
		.f2sdram_adapter_axi4_sub_bready        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bready),        //   input,    width = 1,                         .bready
		.f2sdram_adapter_axi4_sub_bresp         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bresp),         //  output,    width = 2,                         .bresp
		.f2sdram_adapter_axi4_sub_bvalid        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bvalid),        //  output,    width = 1,                         .bvalid
		.f2sdram_adapter_axi4_sub_rdata         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rdata),         //  output,  width = 256,                         .rdata
		.f2sdram_adapter_axi4_sub_rid           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rid),           //  output,    width = 5,                         .rid
		.f2sdram_adapter_axi4_sub_rlast         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rlast),         //  output,    width = 1,                         .rlast
		.f2sdram_adapter_axi4_sub_rready        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rready),        //   input,    width = 1,                         .rready
		.f2sdram_adapter_axi4_sub_rresp         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rresp),         //  output,    width = 2,                         .rresp
		.f2sdram_adapter_axi4_sub_rvalid        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rvalid),        //  output,    width = 1,                         .rvalid
		.f2sdram_adapter_axi4_sub_wdata         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wdata),         //   input,  width = 256,                         .wdata
		.f2sdram_adapter_axi4_sub_wlast         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wlast),         //   input,    width = 1,                         .wlast
		.f2sdram_adapter_axi4_sub_wready        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wready),        //  output,    width = 1,                         .wready
		.f2sdram_adapter_axi4_sub_wstrb         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wstrb),         //   input,   width = 32,                         .wstrb
		.f2sdram_adapter_axi4_sub_wvalid        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wvalid),        //   input,    width = 1,                         .wvalid
		.f2sdram_adapter_axi4_sub_aruser        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_aruser),        //   input,    width = 8,                         .aruser
		.f2sdram_adapter_axi4_sub_awuser        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awuser),        //   input,    width = 8,                         .awuser
		.f2sdram_adapter_axi4_sub_wuser         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wuser),         //   input,    width = 8,                         .wuser
		.f2sdram_adapter_axi4_sub_buser         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_buser),         //  output,    width = 8,                         .buser
		.f2sdram_adapter_axi4_sub_arregion      (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arregion),      //   input,    width = 4,                         .arregion
		.f2sdram_adapter_axi4_sub_ruser         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_ruser),         //  output,    width = 8,                         .ruser
		.f2sdram_adapter_axi4_sub_awregion      (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awregion),      //   input,    width = 4,                         .awregion
		.o_pma_cu_clk_clk                       (o_pma_cu_clk_clk)                                                     //  output,    width = 1,             o_pma_cu_clk.clk
	);

	peripheral_subsys subsys_periph (
		.button_pio_external_connection_export (button_pio_external_connection_export),                     //   input,   width = 4, button_pio_external_connection.export
		.button_pio_irq_irq                    (irq_mapper_receiver0_irq),                                  //  output,   width = 1,                 button_pio_irq.irq
		.dipsw_pio_external_connection_export  (dipsw_pio_external_connection_export),                      //   input,   width = 4,  dipsw_pio_external_connection.export
		.dipsw_pio_irq_irq                     (irq_mapper_receiver1_irq),                                  //  output,   width = 1,                  dipsw_pio_irq.irq
		.led_pio_external_connection_in_port   (led_pio_external_connection_in_port),                       //   input,   width = 3,    led_pio_external_connection.in_port
		.led_pio_external_connection_out_port  (led_pio_external_connection_out_port),                      //  output,   width = 3,                               .out_port
		.pb_cpu_0_s0_waitrequest               (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_waitrequest),   //  output,   width = 1,                    pb_cpu_0_s0.waitrequest
		.pb_cpu_0_s0_readdata                  (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_readdata),      //  output,  width = 32,                               .readdata
		.pb_cpu_0_s0_readdatavalid             (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_readdatavalid), //  output,   width = 1,                               .readdatavalid
		.pb_cpu_0_s0_burstcount                (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_burstcount),    //   input,   width = 1,                               .burstcount
		.pb_cpu_0_s0_writedata                 (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_writedata),     //   input,  width = 32,                               .writedata
		.pb_cpu_0_s0_address                   (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_address),       //   input,  width = 17,                               .address
		.pb_cpu_0_s0_write                     (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_write),         //   input,   width = 1,                               .write
		.pb_cpu_0_s0_read                      (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_read),          //   input,   width = 1,                               .read
		.pb_cpu_0_s0_byteenable                (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_byteenable),    //   input,   width = 4,                               .byteenable
		.pb_cpu_0_s0_debugaccess               (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_debugaccess),   //   input,   width = 1,                               .debugaccess
		.clk_clk                               (clk_100_out_clk_clk),                                       //   input,   width = 1,                            clk.clk
		.reset_reset_n                         (~rst_controller_001_reset_out_reset)                        //   input,   width = 1,                          reset.reset_n
	);

	qsys_top_altera_mm_interconnect_1920_vlx36uy mm_interconnect_0 (
		.ext_hps_f2sdram_master_expanded_master_address                                      (ext_hps_f2sdram_master_expanded_master_address),                 //   input,   width = 33,                                        ext_hps_f2sdram_master_expanded_master.address
		.ext_hps_f2sdram_master_expanded_master_waitrequest                                  (ext_hps_f2sdram_master_expanded_master_waitrequest),             //  output,    width = 1,                                                                              .waitrequest
		.ext_hps_f2sdram_master_expanded_master_burstcount                                   (ext_hps_f2sdram_master_expanded_master_burstcount),              //   input,    width = 1,                                                                              .burstcount
		.ext_hps_f2sdram_master_expanded_master_byteenable                                   (ext_hps_f2sdram_master_expanded_master_byteenable),              //   input,    width = 4,                                                                              .byteenable
		.ext_hps_f2sdram_master_expanded_master_read                                         (ext_hps_f2sdram_master_expanded_master_read),                    //   input,    width = 1,                                                                              .read
		.ext_hps_f2sdram_master_expanded_master_readdata                                     (ext_hps_f2sdram_master_expanded_master_readdata),                //  output,   width = 32,                                                                              .readdata
		.ext_hps_f2sdram_master_expanded_master_readdatavalid                                (ext_hps_f2sdram_master_expanded_master_readdatavalid),           //  output,    width = 1,                                                                              .readdatavalid
		.ext_hps_f2sdram_master_expanded_master_write                                        (ext_hps_f2sdram_master_expanded_master_write),                   //   input,    width = 1,                                                                              .write
		.ext_hps_f2sdram_master_expanded_master_writedata                                    (ext_hps_f2sdram_master_expanded_master_writedata),               //   input,   width = 32,                                                                              .writedata
		.subsys_hps_f2sdram_adapter_axi4_sub_awid                                            (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awid),     //  output,    width = 5,                                           subsys_hps_f2sdram_adapter_axi4_sub.awid
		.subsys_hps_f2sdram_adapter_axi4_sub_awaddr                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awaddr),   //  output,   width = 32,                                                                              .awaddr
		.subsys_hps_f2sdram_adapter_axi4_sub_awlen                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awlen),    //  output,    width = 8,                                                                              .awlen
		.subsys_hps_f2sdram_adapter_axi4_sub_awsize                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awsize),   //  output,    width = 3,                                                                              .awsize
		.subsys_hps_f2sdram_adapter_axi4_sub_awburst                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awburst),  //  output,    width = 2,                                                                              .awburst
		.subsys_hps_f2sdram_adapter_axi4_sub_awlock                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awlock),   //  output,    width = 1,                                                                              .awlock
		.subsys_hps_f2sdram_adapter_axi4_sub_awcache                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awcache),  //  output,    width = 4,                                                                              .awcache
		.subsys_hps_f2sdram_adapter_axi4_sub_awprot                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awprot),   //  output,    width = 3,                                                                              .awprot
		.subsys_hps_f2sdram_adapter_axi4_sub_awuser                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awuser),   //  output,    width = 8,                                                                              .awuser
		.subsys_hps_f2sdram_adapter_axi4_sub_awqos                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awqos),    //  output,    width = 4,                                                                              .awqos
		.subsys_hps_f2sdram_adapter_axi4_sub_awregion                                        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awregion), //  output,    width = 4,                                                                              .awregion
		.subsys_hps_f2sdram_adapter_axi4_sub_awvalid                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awvalid),  //  output,    width = 1,                                                                              .awvalid
		.subsys_hps_f2sdram_adapter_axi4_sub_awready                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_awready),  //   input,    width = 1,                                                                              .awready
		.subsys_hps_f2sdram_adapter_axi4_sub_wdata                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wdata),    //  output,  width = 256,                                                                              .wdata
		.subsys_hps_f2sdram_adapter_axi4_sub_wstrb                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wstrb),    //  output,   width = 32,                                                                              .wstrb
		.subsys_hps_f2sdram_adapter_axi4_sub_wlast                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wlast),    //  output,    width = 1,                                                                              .wlast
		.subsys_hps_f2sdram_adapter_axi4_sub_wvalid                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wvalid),   //  output,    width = 1,                                                                              .wvalid
		.subsys_hps_f2sdram_adapter_axi4_sub_wuser                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wuser),    //  output,    width = 8,                                                                              .wuser
		.subsys_hps_f2sdram_adapter_axi4_sub_wready                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_wready),   //   input,    width = 1,                                                                              .wready
		.subsys_hps_f2sdram_adapter_axi4_sub_bid                                             (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bid),      //   input,    width = 5,                                                                              .bid
		.subsys_hps_f2sdram_adapter_axi4_sub_bresp                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bresp),    //   input,    width = 2,                                                                              .bresp
		.subsys_hps_f2sdram_adapter_axi4_sub_buser                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_buser),    //   input,    width = 8,                                                                              .buser
		.subsys_hps_f2sdram_adapter_axi4_sub_bvalid                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bvalid),   //   input,    width = 1,                                                                              .bvalid
		.subsys_hps_f2sdram_adapter_axi4_sub_bready                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_bready),   //  output,    width = 1,                                                                              .bready
		.subsys_hps_f2sdram_adapter_axi4_sub_arid                                            (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arid),     //  output,    width = 5,                                                                              .arid
		.subsys_hps_f2sdram_adapter_axi4_sub_araddr                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_araddr),   //  output,   width = 32,                                                                              .araddr
		.subsys_hps_f2sdram_adapter_axi4_sub_arlen                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arlen),    //  output,    width = 8,                                                                              .arlen
		.subsys_hps_f2sdram_adapter_axi4_sub_arsize                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arsize),   //  output,    width = 3,                                                                              .arsize
		.subsys_hps_f2sdram_adapter_axi4_sub_arburst                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arburst),  //  output,    width = 2,                                                                              .arburst
		.subsys_hps_f2sdram_adapter_axi4_sub_arlock                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arlock),   //  output,    width = 1,                                                                              .arlock
		.subsys_hps_f2sdram_adapter_axi4_sub_arcache                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arcache),  //  output,    width = 4,                                                                              .arcache
		.subsys_hps_f2sdram_adapter_axi4_sub_arprot                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arprot),   //  output,    width = 3,                                                                              .arprot
		.subsys_hps_f2sdram_adapter_axi4_sub_aruser                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_aruser),   //  output,    width = 8,                                                                              .aruser
		.subsys_hps_f2sdram_adapter_axi4_sub_arqos                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arqos),    //  output,    width = 4,                                                                              .arqos
		.subsys_hps_f2sdram_adapter_axi4_sub_arregion                                        (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arregion), //  output,    width = 4,                                                                              .arregion
		.subsys_hps_f2sdram_adapter_axi4_sub_arvalid                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arvalid),  //  output,    width = 1,                                                                              .arvalid
		.subsys_hps_f2sdram_adapter_axi4_sub_arready                                         (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_arready),  //   input,    width = 1,                                                                              .arready
		.subsys_hps_f2sdram_adapter_axi4_sub_rid                                             (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rid),      //   input,    width = 5,                                                                              .rid
		.subsys_hps_f2sdram_adapter_axi4_sub_rdata                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rdata),    //   input,  width = 256,                                                                              .rdata
		.subsys_hps_f2sdram_adapter_axi4_sub_rresp                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rresp),    //   input,    width = 2,                                                                              .rresp
		.subsys_hps_f2sdram_adapter_axi4_sub_rlast                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rlast),    //   input,    width = 1,                                                                              .rlast
		.subsys_hps_f2sdram_adapter_axi4_sub_rvalid                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rvalid),   //   input,    width = 1,                                                                              .rvalid
		.subsys_hps_f2sdram_adapter_axi4_sub_rready                                          (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_rready),   //  output,    width = 1,                                                                              .rready
		.subsys_hps_f2sdram_adapter_axi4_sub_ruser                                           (mm_interconnect_0_subsys_hps_f2sdram_adapter_axi4_sub_ruser),    //   input,    width = 8,                                                                              .ruser
		.ext_hps_f2sdram_master_reset_reset_bridge_in_reset_reset                            (rst_controller_001_reset_out_reset),                             //   input,    width = 1,                            ext_hps_f2sdram_master_reset_reset_bridge_in_reset.reset
		.ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),                             //   input,    width = 1, ext_hps_f2sdram_master_expanded_master_translator_reset_reset_bridge_in_reset.reset
		.clk_100_out_clk_clk                                                                 (clk_100_out_clk_clk)                                             //   input,    width = 1,                                                               clk_100_out_clk.clk
	);

	qsys_top_altera_mm_interconnect_1920_jt5szha mm_interconnect_1 (
		.subsys_debug_fpga_m_master_address                (subsys_debug_fpga_m_master_address),                                  //   input,   width = 32,               subsys_debug_fpga_m_master.address
		.subsys_debug_fpga_m_master_waitrequest            (subsys_debug_fpga_m_master_waitrequest),                              //  output,    width = 1,                                         .waitrequest
		.subsys_debug_fpga_m_master_byteenable             (subsys_debug_fpga_m_master_byteenable),                               //   input,    width = 4,                                         .byteenable
		.subsys_debug_fpga_m_master_read                   (subsys_debug_fpga_m_master_read),                                     //   input,    width = 1,                                         .read
		.subsys_debug_fpga_m_master_readdata               (subsys_debug_fpga_m_master_readdata),                                 //  output,   width = 32,                                         .readdata
		.subsys_debug_fpga_m_master_readdatavalid          (subsys_debug_fpga_m_master_readdatavalid),                            //  output,    width = 1,                                         .readdatavalid
		.subsys_debug_fpga_m_master_write                  (subsys_debug_fpga_m_master_write),                                    //   input,    width = 1,                                         .write
		.subsys_debug_fpga_m_master_writedata              (subsys_debug_fpga_m_master_writedata),                                //   input,   width = 32,                                         .writedata
		.subsys_hps_hps2fpga_awid                          (subsys_hps_hps2fpga_awid),                                            //   input,    width = 4,                      subsys_hps_hps2fpga.awid
		.subsys_hps_hps2fpga_awaddr                        (subsys_hps_hps2fpga_awaddr),                                          //   input,   width = 38,                                         .awaddr
		.subsys_hps_hps2fpga_awlen                         (subsys_hps_hps2fpga_awlen),                                           //   input,    width = 8,                                         .awlen
		.subsys_hps_hps2fpga_awsize                        (subsys_hps_hps2fpga_awsize),                                          //   input,    width = 3,                                         .awsize
		.subsys_hps_hps2fpga_awburst                       (subsys_hps_hps2fpga_awburst),                                         //   input,    width = 2,                                         .awburst
		.subsys_hps_hps2fpga_awlock                        (subsys_hps_hps2fpga_awlock),                                          //   input,    width = 1,                                         .awlock
		.subsys_hps_hps2fpga_awcache                       (subsys_hps_hps2fpga_awcache),                                         //   input,    width = 4,                                         .awcache
		.subsys_hps_hps2fpga_awprot                        (subsys_hps_hps2fpga_awprot),                                          //   input,    width = 3,                                         .awprot
		.subsys_hps_hps2fpga_awvalid                       (subsys_hps_hps2fpga_awvalid),                                         //   input,    width = 1,                                         .awvalid
		.subsys_hps_hps2fpga_awready                       (subsys_hps_hps2fpga_awready),                                         //  output,    width = 1,                                         .awready
		.subsys_hps_hps2fpga_wdata                         (subsys_hps_hps2fpga_wdata),                                           //   input,  width = 128,                                         .wdata
		.subsys_hps_hps2fpga_wstrb                         (subsys_hps_hps2fpga_wstrb),                                           //   input,   width = 16,                                         .wstrb
		.subsys_hps_hps2fpga_wlast                         (subsys_hps_hps2fpga_wlast),                                           //   input,    width = 1,                                         .wlast
		.subsys_hps_hps2fpga_wvalid                        (subsys_hps_hps2fpga_wvalid),                                          //   input,    width = 1,                                         .wvalid
		.subsys_hps_hps2fpga_wready                        (subsys_hps_hps2fpga_wready),                                          //  output,    width = 1,                                         .wready
		.subsys_hps_hps2fpga_bid                           (subsys_hps_hps2fpga_bid),                                             //  output,    width = 4,                                         .bid
		.subsys_hps_hps2fpga_bresp                         (subsys_hps_hps2fpga_bresp),                                           //  output,    width = 2,                                         .bresp
		.subsys_hps_hps2fpga_bvalid                        (subsys_hps_hps2fpga_bvalid),                                          //  output,    width = 1,                                         .bvalid
		.subsys_hps_hps2fpga_bready                        (subsys_hps_hps2fpga_bready),                                          //   input,    width = 1,                                         .bready
		.subsys_hps_hps2fpga_arid                          (subsys_hps_hps2fpga_arid),                                            //   input,    width = 4,                                         .arid
		.subsys_hps_hps2fpga_araddr                        (subsys_hps_hps2fpga_araddr),                                          //   input,   width = 38,                                         .araddr
		.subsys_hps_hps2fpga_arlen                         (subsys_hps_hps2fpga_arlen),                                           //   input,    width = 8,                                         .arlen
		.subsys_hps_hps2fpga_arsize                        (subsys_hps_hps2fpga_arsize),                                          //   input,    width = 3,                                         .arsize
		.subsys_hps_hps2fpga_arburst                       (subsys_hps_hps2fpga_arburst),                                         //   input,    width = 2,                                         .arburst
		.subsys_hps_hps2fpga_arlock                        (subsys_hps_hps2fpga_arlock),                                          //   input,    width = 1,                                         .arlock
		.subsys_hps_hps2fpga_arcache                       (subsys_hps_hps2fpga_arcache),                                         //   input,    width = 4,                                         .arcache
		.subsys_hps_hps2fpga_arprot                        (subsys_hps_hps2fpga_arprot),                                          //   input,    width = 3,                                         .arprot
		.subsys_hps_hps2fpga_arvalid                       (subsys_hps_hps2fpga_arvalid),                                         //   input,    width = 1,                                         .arvalid
		.subsys_hps_hps2fpga_arready                       (subsys_hps_hps2fpga_arready),                                         //  output,    width = 1,                                         .arready
		.subsys_hps_hps2fpga_rid                           (subsys_hps_hps2fpga_rid),                                             //  output,    width = 4,                                         .rid
		.subsys_hps_hps2fpga_rdata                         (subsys_hps_hps2fpga_rdata),                                           //  output,  width = 128,                                         .rdata
		.subsys_hps_hps2fpga_rresp                         (subsys_hps_hps2fpga_rresp),                                           //  output,    width = 2,                                         .rresp
		.subsys_hps_hps2fpga_rlast                         (subsys_hps_hps2fpga_rlast),                                           //  output,    width = 1,                                         .rlast
		.subsys_hps_hps2fpga_rvalid                        (subsys_hps_hps2fpga_rvalid),                                          //  output,    width = 1,                                         .rvalid
		.subsys_hps_hps2fpga_rready                        (subsys_hps_hps2fpga_rready),                                          //   input,    width = 1,                                         .rready
		.subsys_hps_lwhps2fpga_awid                        (subsys_hps_lwhps2fpga_awid),                                          //   input,    width = 4,                    subsys_hps_lwhps2fpga.awid
		.subsys_hps_lwhps2fpga_awaddr                      (subsys_hps_lwhps2fpga_awaddr),                                        //   input,   width = 29,                                         .awaddr
		.subsys_hps_lwhps2fpga_awlen                       (subsys_hps_lwhps2fpga_awlen),                                         //   input,    width = 8,                                         .awlen
		.subsys_hps_lwhps2fpga_awsize                      (subsys_hps_lwhps2fpga_awsize),                                        //   input,    width = 3,                                         .awsize
		.subsys_hps_lwhps2fpga_awburst                     (subsys_hps_lwhps2fpga_awburst),                                       //   input,    width = 2,                                         .awburst
		.subsys_hps_lwhps2fpga_awlock                      (subsys_hps_lwhps2fpga_awlock),                                        //   input,    width = 1,                                         .awlock
		.subsys_hps_lwhps2fpga_awcache                     (subsys_hps_lwhps2fpga_awcache),                                       //   input,    width = 4,                                         .awcache
		.subsys_hps_lwhps2fpga_awprot                      (subsys_hps_lwhps2fpga_awprot),                                        //   input,    width = 3,                                         .awprot
		.subsys_hps_lwhps2fpga_awvalid                     (subsys_hps_lwhps2fpga_awvalid),                                       //   input,    width = 1,                                         .awvalid
		.subsys_hps_lwhps2fpga_awready                     (subsys_hps_lwhps2fpga_awready),                                       //  output,    width = 1,                                         .awready
		.subsys_hps_lwhps2fpga_wdata                       (subsys_hps_lwhps2fpga_wdata),                                         //   input,   width = 32,                                         .wdata
		.subsys_hps_lwhps2fpga_wstrb                       (subsys_hps_lwhps2fpga_wstrb),                                         //   input,    width = 4,                                         .wstrb
		.subsys_hps_lwhps2fpga_wlast                       (subsys_hps_lwhps2fpga_wlast),                                         //   input,    width = 1,                                         .wlast
		.subsys_hps_lwhps2fpga_wvalid                      (subsys_hps_lwhps2fpga_wvalid),                                        //   input,    width = 1,                                         .wvalid
		.subsys_hps_lwhps2fpga_wready                      (subsys_hps_lwhps2fpga_wready),                                        //  output,    width = 1,                                         .wready
		.subsys_hps_lwhps2fpga_bid                         (subsys_hps_lwhps2fpga_bid),                                           //  output,    width = 4,                                         .bid
		.subsys_hps_lwhps2fpga_bresp                       (subsys_hps_lwhps2fpga_bresp),                                         //  output,    width = 2,                                         .bresp
		.subsys_hps_lwhps2fpga_bvalid                      (subsys_hps_lwhps2fpga_bvalid),                                        //  output,    width = 1,                                         .bvalid
		.subsys_hps_lwhps2fpga_bready                      (subsys_hps_lwhps2fpga_bready),                                        //   input,    width = 1,                                         .bready
		.subsys_hps_lwhps2fpga_arid                        (subsys_hps_lwhps2fpga_arid),                                          //   input,    width = 4,                                         .arid
		.subsys_hps_lwhps2fpga_araddr                      (subsys_hps_lwhps2fpga_araddr),                                        //   input,   width = 29,                                         .araddr
		.subsys_hps_lwhps2fpga_arlen                       (subsys_hps_lwhps2fpga_arlen),                                         //   input,    width = 8,                                         .arlen
		.subsys_hps_lwhps2fpga_arsize                      (subsys_hps_lwhps2fpga_arsize),                                        //   input,    width = 3,                                         .arsize
		.subsys_hps_lwhps2fpga_arburst                     (subsys_hps_lwhps2fpga_arburst),                                       //   input,    width = 2,                                         .arburst
		.subsys_hps_lwhps2fpga_arlock                      (subsys_hps_lwhps2fpga_arlock),                                        //   input,    width = 1,                                         .arlock
		.subsys_hps_lwhps2fpga_arcache                     (subsys_hps_lwhps2fpga_arcache),                                       //   input,    width = 4,                                         .arcache
		.subsys_hps_lwhps2fpga_arprot                      (subsys_hps_lwhps2fpga_arprot),                                        //   input,    width = 3,                                         .arprot
		.subsys_hps_lwhps2fpga_arvalid                     (subsys_hps_lwhps2fpga_arvalid),                                       //   input,    width = 1,                                         .arvalid
		.subsys_hps_lwhps2fpga_arready                     (subsys_hps_lwhps2fpga_arready),                                       //  output,    width = 1,                                         .arready
		.subsys_hps_lwhps2fpga_rid                         (subsys_hps_lwhps2fpga_rid),                                           //  output,    width = 4,                                         .rid
		.subsys_hps_lwhps2fpga_rdata                       (subsys_hps_lwhps2fpga_rdata),                                         //  output,   width = 32,                                         .rdata
		.subsys_hps_lwhps2fpga_rresp                       (subsys_hps_lwhps2fpga_rresp),                                         //  output,    width = 2,                                         .rresp
		.subsys_hps_lwhps2fpga_rlast                       (subsys_hps_lwhps2fpga_rlast),                                         //  output,    width = 1,                                         .rlast
		.subsys_hps_lwhps2fpga_rvalid                      (subsys_hps_lwhps2fpga_rvalid),                                        //  output,    width = 1,                                         .rvalid
		.subsys_hps_lwhps2fpga_rready                      (subsys_hps_lwhps2fpga_rready),                                        //   input,    width = 1,                                         .rready
		.ocm_axi_s1_awid                                   (mm_interconnect_1_ocm_axi_s1_awid),                                   //  output,   width = 10,                               ocm_axi_s1.awid
		.ocm_axi_s1_awaddr                                 (mm_interconnect_1_ocm_axi_s1_awaddr),                                 //  output,   width = 18,                                         .awaddr
		.ocm_axi_s1_awlen                                  (mm_interconnect_1_ocm_axi_s1_awlen),                                  //  output,    width = 8,                                         .awlen
		.ocm_axi_s1_awsize                                 (mm_interconnect_1_ocm_axi_s1_awsize),                                 //  output,    width = 3,                                         .awsize
		.ocm_axi_s1_awburst                                (mm_interconnect_1_ocm_axi_s1_awburst),                                //  output,    width = 2,                                         .awburst
		.ocm_axi_s1_awvalid                                (mm_interconnect_1_ocm_axi_s1_awvalid),                                //  output,    width = 1,                                         .awvalid
		.ocm_axi_s1_awready                                (mm_interconnect_1_ocm_axi_s1_awready),                                //   input,    width = 1,                                         .awready
		.ocm_axi_s1_wdata                                  (mm_interconnect_1_ocm_axi_s1_wdata),                                  //  output,  width = 128,                                         .wdata
		.ocm_axi_s1_wstrb                                  (mm_interconnect_1_ocm_axi_s1_wstrb),                                  //  output,   width = 16,                                         .wstrb
		.ocm_axi_s1_wlast                                  (mm_interconnect_1_ocm_axi_s1_wlast),                                  //  output,    width = 1,                                         .wlast
		.ocm_axi_s1_wvalid                                 (mm_interconnect_1_ocm_axi_s1_wvalid),                                 //  output,    width = 1,                                         .wvalid
		.ocm_axi_s1_wready                                 (mm_interconnect_1_ocm_axi_s1_wready),                                 //   input,    width = 1,                                         .wready
		.ocm_axi_s1_bid                                    (mm_interconnect_1_ocm_axi_s1_bid),                                    //   input,   width = 10,                                         .bid
		.ocm_axi_s1_bresp                                  (mm_interconnect_1_ocm_axi_s1_bresp),                                  //   input,    width = 2,                                         .bresp
		.ocm_axi_s1_bvalid                                 (mm_interconnect_1_ocm_axi_s1_bvalid),                                 //   input,    width = 1,                                         .bvalid
		.ocm_axi_s1_bready                                 (mm_interconnect_1_ocm_axi_s1_bready),                                 //  output,    width = 1,                                         .bready
		.ocm_axi_s1_arid                                   (mm_interconnect_1_ocm_axi_s1_arid),                                   //  output,   width = 10,                                         .arid
		.ocm_axi_s1_araddr                                 (mm_interconnect_1_ocm_axi_s1_araddr),                                 //  output,   width = 18,                                         .araddr
		.ocm_axi_s1_arlen                                  (mm_interconnect_1_ocm_axi_s1_arlen),                                  //  output,    width = 8,                                         .arlen
		.ocm_axi_s1_arsize                                 (mm_interconnect_1_ocm_axi_s1_arsize),                                 //  output,    width = 3,                                         .arsize
		.ocm_axi_s1_arburst                                (mm_interconnect_1_ocm_axi_s1_arburst),                                //  output,    width = 2,                                         .arburst
		.ocm_axi_s1_arvalid                                (mm_interconnect_1_ocm_axi_s1_arvalid),                                //  output,    width = 1,                                         .arvalid
		.ocm_axi_s1_arready                                (mm_interconnect_1_ocm_axi_s1_arready),                                //   input,    width = 1,                                         .arready
		.ocm_axi_s1_rid                                    (mm_interconnect_1_ocm_axi_s1_rid),                                    //   input,   width = 10,                                         .rid
		.ocm_axi_s1_rdata                                  (mm_interconnect_1_ocm_axi_s1_rdata),                                  //   input,  width = 128,                                         .rdata
		.ocm_axi_s1_rresp                                  (mm_interconnect_1_ocm_axi_s1_rresp),                                  //   input,    width = 2,                                         .rresp
		.ocm_axi_s1_rlast                                  (mm_interconnect_1_ocm_axi_s1_rlast),                                  //   input,    width = 1,                                         .rlast
		.ocm_axi_s1_rvalid                                 (mm_interconnect_1_ocm_axi_s1_rvalid),                                 //   input,    width = 1,                                         .rvalid
		.ocm_axi_s1_rready                                 (mm_interconnect_1_ocm_axi_s1_rready),                                 //  output,    width = 1,                                         .rready
		.subsys_hps_usb31_phy_reconfig_slave_address       (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_address),       //  output,   width = 21,      subsys_hps_usb31_phy_reconfig_slave.address
		.subsys_hps_usb31_phy_reconfig_slave_write         (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_write),         //  output,    width = 1,                                         .write
		.subsys_hps_usb31_phy_reconfig_slave_read          (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_read),          //  output,    width = 1,                                         .read
		.subsys_hps_usb31_phy_reconfig_slave_readdata      (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_readdata),      //   input,   width = 32,                                         .readdata
		.subsys_hps_usb31_phy_reconfig_slave_writedata     (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_writedata),     //  output,   width = 32,                                         .writedata
		.subsys_hps_usb31_phy_reconfig_slave_byteenable    (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_byteenable),    //  output,    width = 4,                                         .byteenable
		.subsys_hps_usb31_phy_reconfig_slave_readdatavalid (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_readdatavalid), //   input,    width = 1,                                         .readdatavalid
		.subsys_hps_usb31_phy_reconfig_slave_waitrequest   (mm_interconnect_1_subsys_hps_usb31_phy_reconfig_slave_waitrequest),   //   input,    width = 1,                                         .waitrequest
		.subsys_periph_pb_cpu_0_s0_address                 (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_address),                 //  output,   width = 17,                subsys_periph_pb_cpu_0_s0.address
		.subsys_periph_pb_cpu_0_s0_write                   (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_write),                   //  output,    width = 1,                                         .write
		.subsys_periph_pb_cpu_0_s0_read                    (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_read),                    //  output,    width = 1,                                         .read
		.subsys_periph_pb_cpu_0_s0_readdata                (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_readdata),                //   input,   width = 32,                                         .readdata
		.subsys_periph_pb_cpu_0_s0_writedata               (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_writedata),               //  output,   width = 32,                                         .writedata
		.subsys_periph_pb_cpu_0_s0_burstcount              (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_burstcount),              //  output,    width = 1,                                         .burstcount
		.subsys_periph_pb_cpu_0_s0_byteenable              (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_byteenable),              //  output,    width = 4,                                         .byteenable
		.subsys_periph_pb_cpu_0_s0_readdatavalid           (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_readdatavalid),           //   input,    width = 1,                                         .readdatavalid
		.subsys_periph_pb_cpu_0_s0_waitrequest             (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_waitrequest),             //   input,    width = 1,                                         .waitrequest
		.subsys_periph_pb_cpu_0_s0_debugaccess             (mm_interconnect_1_subsys_periph_pb_cpu_0_s0_debugaccess),             //  output,    width = 1,                                         .debugaccess
		.subsys_debug_reset_reset_bridge_in_reset_reset    (rst_controller_001_reset_out_reset),                                  //   input,    width = 1, subsys_debug_reset_reset_bridge_in_reset.reset
		.ocm_reset1_reset_bridge_in_reset_reset            (rst_controller_001_reset_out_reset),                                  //   input,    width = 1,         ocm_reset1_reset_bridge_in_reset.reset
		.clk_100_out_clk_clk                               (clk_100_out_clk_clk)                                                  //   input,    width = 1,                          clk_100_out_clk.clk
	);

	qsys_top_altera_mm_interconnect_1920_23wdfky mm_interconnect_2 (
		.subsys_debug_hps_f2sdram_master_address             (subsys_debug_hps_f2sdram_master_address),                               //   input,  width = 32,          subsys_debug_hps_f2sdram_master.address
		.subsys_debug_hps_f2sdram_master_waitrequest         (subsys_debug_hps_f2sdram_master_waitrequest),                           //  output,   width = 1,                                         .waitrequest
		.subsys_debug_hps_f2sdram_master_byteenable          (subsys_debug_hps_f2sdram_master_byteenable),                            //   input,   width = 4,                                         .byteenable
		.subsys_debug_hps_f2sdram_master_read                (subsys_debug_hps_f2sdram_master_read),                                  //   input,   width = 1,                                         .read
		.subsys_debug_hps_f2sdram_master_readdata            (subsys_debug_hps_f2sdram_master_readdata),                              //  output,  width = 32,                                         .readdata
		.subsys_debug_hps_f2sdram_master_readdatavalid       (subsys_debug_hps_f2sdram_master_readdatavalid),                         //  output,   width = 1,                                         .readdatavalid
		.subsys_debug_hps_f2sdram_master_write               (subsys_debug_hps_f2sdram_master_write),                                 //   input,   width = 1,                                         .write
		.subsys_debug_hps_f2sdram_master_writedata           (subsys_debug_hps_f2sdram_master_writedata),                             //   input,  width = 32,                                         .writedata
		.ext_hps_f2sdram_master_windowed_slave_address       (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_address),       //  output,  width = 30,    ext_hps_f2sdram_master_windowed_slave.address
		.ext_hps_f2sdram_master_windowed_slave_write         (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_write),         //  output,   width = 1,                                         .write
		.ext_hps_f2sdram_master_windowed_slave_read          (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_read),          //  output,   width = 1,                                         .read
		.ext_hps_f2sdram_master_windowed_slave_readdata      (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_readdata),      //   input,  width = 32,                                         .readdata
		.ext_hps_f2sdram_master_windowed_slave_writedata     (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_writedata),     //  output,  width = 32,                                         .writedata
		.ext_hps_f2sdram_master_windowed_slave_burstcount    (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_burstcount),    //  output,   width = 1,                                         .burstcount
		.ext_hps_f2sdram_master_windowed_slave_byteenable    (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_byteenable),    //  output,   width = 4,                                         .byteenable
		.ext_hps_f2sdram_master_windowed_slave_readdatavalid (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_readdatavalid), //   input,   width = 1,                                         .readdatavalid
		.ext_hps_f2sdram_master_windowed_slave_waitrequest   (mm_interconnect_2_ext_hps_f2sdram_master_windowed_slave_waitrequest),   //   input,   width = 1,                                         .waitrequest
		.subsys_debug_reset_reset_bridge_in_reset_reset      (rst_controller_001_reset_out_reset),                                    //   input,   width = 1, subsys_debug_reset_reset_bridge_in_reset.reset
		.clk_100_out_clk_clk                                 (clk_100_out_clk_clk)                                                    //   input,   width = 1,                          clk_100_out_clk.clk
	);

	qsys_top_altera_irq_mapper_2001_xpo2xca irq_mapper (
		.clk           (),                          //   input,   width = 1,       clk.clk
		.reset         (),                          //   input,   width = 1, clk_reset.reset
		.receiver0_irq (irq_mapper_receiver0_irq),  //   input,   width = 1, receiver0.irq
		.receiver1_irq (irq_mapper_receiver1_irq),  //   input,   width = 1, receiver1.irq
		.sender_irq    (subsys_hps_f2h_irq_in_irq)  //  output,  width = 63,    sender.irq
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (1),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~rst_in_out_reset_reset),            //   input,  width = 1, reset_in0.reset
		.clk            (clk_100_out_clk_clk),                //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset),     //  output,  width = 1, reset_out.reset
		.reset_req      (rst_controller_reset_out_reset_req), //  output,  width = 1,          .reset_req
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (~rst_in_out_reset_reset),            //   input,  width = 1, reset_in0.reset
		.clk            (clk_100_out_clk_clk),                //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
