// hps_subsys.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module hps_subsys (
		output wire         h2f_reset_reset,                        //                h2f_reset.reset
		input  wire         hps2fpga_clk_clk,                       //             hps2fpga_clk.clk
		input  wire         hps2fpga_rst_reset,                     //             hps2fpga_rst.reset
		output wire [3:0]   hps2fpga_awid,                          //                 hps2fpga.awid
		output wire [37:0]  hps2fpga_awaddr,                        //                         .awaddr
		output wire [7:0]   hps2fpga_awlen,                         //                         .awlen
		output wire [2:0]   hps2fpga_awsize,                        //                         .awsize
		output wire [1:0]   hps2fpga_awburst,                       //                         .awburst
		output wire         hps2fpga_awlock,                        //                         .awlock
		output wire [3:0]   hps2fpga_awcache,                       //                         .awcache
		output wire [2:0]   hps2fpga_awprot,                        //                         .awprot
		output wire         hps2fpga_awvalid,                       //                         .awvalid
		input  wire         hps2fpga_awready,                       //                         .awready
		output wire [127:0] hps2fpga_wdata,                         //                         .wdata
		output wire [15:0]  hps2fpga_wstrb,                         //                         .wstrb
		output wire         hps2fpga_wlast,                         //                         .wlast
		output wire         hps2fpga_wvalid,                        //                         .wvalid
		input  wire         hps2fpga_wready,                        //                         .wready
		input  wire [3:0]   hps2fpga_bid,                           //                         .bid
		input  wire [1:0]   hps2fpga_bresp,                         //                         .bresp
		input  wire         hps2fpga_bvalid,                        //                         .bvalid
		output wire         hps2fpga_bready,                        //                         .bready
		output wire [3:0]   hps2fpga_arid,                          //                         .arid
		output wire [37:0]  hps2fpga_araddr,                        //                         .araddr
		output wire [7:0]   hps2fpga_arlen,                         //                         .arlen
		output wire [2:0]   hps2fpga_arsize,                        //                         .arsize
		output wire [1:0]   hps2fpga_arburst,                       //                         .arburst
		output wire         hps2fpga_arlock,                        //                         .arlock
		output wire [3:0]   hps2fpga_arcache,                       //                         .arcache
		output wire [2:0]   hps2fpga_arprot,                        //                         .arprot
		output wire         hps2fpga_arvalid,                       //                         .arvalid
		input  wire         hps2fpga_arready,                       //                         .arready
		input  wire [3:0]   hps2fpga_rid,                           //                         .rid
		input  wire [127:0] hps2fpga_rdata,                         //                         .rdata
		input  wire [1:0]   hps2fpga_rresp,                         //                         .rresp
		input  wire         hps2fpga_rlast,                         //                         .rlast
		input  wire         hps2fpga_rvalid,                        //                         .rvalid
		output wire         hps2fpga_rready,                        //                         .rready
		input  wire         lwhps2fpga_clk_clk,                     //           lwhps2fpga_clk.clk
		input  wire         lwhps2fpga_rst_reset,                   //           lwhps2fpga_rst.reset
		output wire [3:0]   lwhps2fpga_awid,                        //               lwhps2fpga.awid
		output wire [28:0]  lwhps2fpga_awaddr,                      //                         .awaddr
		output wire [7:0]   lwhps2fpga_awlen,                       //                         .awlen
		output wire [2:0]   lwhps2fpga_awsize,                      //                         .awsize
		output wire [1:0]   lwhps2fpga_awburst,                     //                         .awburst
		output wire         lwhps2fpga_awlock,                      //                         .awlock
		output wire [3:0]   lwhps2fpga_awcache,                     //                         .awcache
		output wire [2:0]   lwhps2fpga_awprot,                      //                         .awprot
		output wire         lwhps2fpga_awvalid,                     //                         .awvalid
		input  wire         lwhps2fpga_awready,                     //                         .awready
		output wire [31:0]  lwhps2fpga_wdata,                       //                         .wdata
		output wire [3:0]   lwhps2fpga_wstrb,                       //                         .wstrb
		output wire         lwhps2fpga_wlast,                       //                         .wlast
		output wire         lwhps2fpga_wvalid,                      //                         .wvalid
		input  wire         lwhps2fpga_wready,                      //                         .wready
		input  wire [3:0]   lwhps2fpga_bid,                         //                         .bid
		input  wire [1:0]   lwhps2fpga_bresp,                       //                         .bresp
		input  wire         lwhps2fpga_bvalid,                      //                         .bvalid
		output wire         lwhps2fpga_bready,                      //                         .bready
		output wire [3:0]   lwhps2fpga_arid,                        //                         .arid
		output wire [28:0]  lwhps2fpga_araddr,                      //                         .araddr
		output wire [7:0]   lwhps2fpga_arlen,                       //                         .arlen
		output wire [2:0]   lwhps2fpga_arsize,                      //                         .arsize
		output wire [1:0]   lwhps2fpga_arburst,                     //                         .arburst
		output wire         lwhps2fpga_arlock,                      //                         .arlock
		output wire [3:0]   lwhps2fpga_arcache,                     //                         .arcache
		output wire [2:0]   lwhps2fpga_arprot,                      //                         .arprot
		output wire         lwhps2fpga_arvalid,                     //                         .arvalid
		input  wire         lwhps2fpga_arready,                     //                         .arready
		input  wire [3:0]   lwhps2fpga_rid,                         //                         .rid
		input  wire [31:0]  lwhps2fpga_rdata,                       //                         .rdata
		input  wire [1:0]   lwhps2fpga_rresp,                       //                         .rresp
		input  wire         lwhps2fpga_rlast,                       //                         .rlast
		input  wire         lwhps2fpga_rvalid,                      //                         .rvalid
		output wire         lwhps2fpga_rready,                      //                         .rready
		input  wire         hps_io_hps_osc_clk,                     //                   hps_io.hps_osc_clk
		inout  wire         hps_io_sdmmc_data0,                     //                         .sdmmc_data0
		inout  wire         hps_io_sdmmc_data1,                     //                         .sdmmc_data1
		output wire         hps_io_sdmmc_cclk,                      //                         .sdmmc_cclk
		inout  wire         hps_io_sdmmc_data2,                     //                         .sdmmc_data2
		inout  wire         hps_io_sdmmc_data3,                     //                         .sdmmc_data3
		inout  wire         hps_io_sdmmc_cmd,                       //                         .sdmmc_cmd
		input  wire         hps_io_usb1_clk,                        //                         .usb1_clk
		output wire         hps_io_usb1_stp,                        //                         .usb1_stp
		input  wire         hps_io_usb1_dir,                        //                         .usb1_dir
		inout  wire         hps_io_usb1_data0,                      //                         .usb1_data0
		inout  wire         hps_io_usb1_data1,                      //                         .usb1_data1
		input  wire         hps_io_usb1_nxt,                        //                         .usb1_nxt
		inout  wire         hps_io_usb1_data2,                      //                         .usb1_data2
		inout  wire         hps_io_usb1_data3,                      //                         .usb1_data3
		inout  wire         hps_io_usb1_data4,                      //                         .usb1_data4
		inout  wire         hps_io_usb1_data5,                      //                         .usb1_data5
		inout  wire         hps_io_usb1_data6,                      //                         .usb1_data6
		inout  wire         hps_io_usb1_data7,                      //                         .usb1_data7
		output wire         hps_io_emac2_tx_clk,                    //                         .emac2_tx_clk
		output wire         hps_io_emac2_tx_ctl,                    //                         .emac2_tx_ctl
		input  wire         hps_io_emac2_rx_clk,                    //                         .emac2_rx_clk
		input  wire         hps_io_emac2_rx_ctl,                    //                         .emac2_rx_ctl
		output wire         hps_io_emac2_txd0,                      //                         .emac2_txd0
		output wire         hps_io_emac2_txd1,                      //                         .emac2_txd1
		input  wire         hps_io_emac2_rxd0,                      //                         .emac2_rxd0
		input  wire         hps_io_emac2_rxd1,                      //                         .emac2_rxd1
		output wire         hps_io_emac2_txd2,                      //                         .emac2_txd2
		output wire         hps_io_emac2_txd3,                      //                         .emac2_txd3
		input  wire         hps_io_emac2_rxd2,                      //                         .emac2_rxd2
		input  wire         hps_io_emac2_rxd3,                      //                         .emac2_rxd3
		inout  wire         hps_io_mdio2_mdio,                      //                         .mdio2_mdio
		output wire         hps_io_mdio2_mdc,                       //                         .mdio2_mdc
		output wire         hps_io_uart0_tx,                        //                         .uart0_tx
		input  wire         hps_io_uart0_rx,                        //                         .uart0_rx
		inout  wire         hps_io_i2c0_sda,                        //                         .i2c0_sda
		inout  wire         hps_io_i2c0_scl,                        //                         .i2c0_scl
		inout  wire         hps_io_gpio0,                           //                         .gpio0
		inout  wire         hps_io_gpio1,                           //                         .gpio1
		inout  wire         hps_io_gpio8,                           //                         .gpio8
		inout  wire         hps_io_gpio9,                           //                         .gpio9
		inout  wire         hps_io_gpio10,                          //                         .gpio10
		inout  wire         hps_io_gpio11,                          //                         .gpio11
		inout  wire         hps_io_gpio28,                          //                         .gpio28
		input  wire         usb31_io_vbus_det,                      //                 usb31_io.vbus_det
		input  wire         usb31_io_flt_bar,                       //                         .flt_bar
		output wire [1:0]   usb31_io_usb_ctrl,                      //                         .usb_ctrl
		input  wire         usb31_io_usb31_id,                      //                         .usb31_id
		input  wire [62:0]  f2h_irq_in_irq,                         //               f2h_irq_in.irq
		input  wire         usb31_phy_pma_cpu_clk_clk,              //    usb31_phy_pma_cpu_clk.clk
		input  wire         usb31_phy_refclk_p_clk,                 //       usb31_phy_refclk_p.clk
		input  wire         usb31_phy_refclk_n_clk,                 //       usb31_phy_refclk_n.clk
		input  wire         usb31_phy_rx_serial_n_i_rx_serial_n,    //    usb31_phy_rx_serial_n.i_rx_serial_n
		input  wire         usb31_phy_rx_serial_p_i_rx_serial_p,    //    usb31_phy_rx_serial_p.i_rx_serial_p
		output wire         usb31_phy_tx_serial_n_o_tx_serial_n,    //    usb31_phy_tx_serial_n.o_tx_serial_n
		output wire         usb31_phy_tx_serial_p_o_tx_serial_p,    //    usb31_phy_tx_serial_p.o_tx_serial_p
		input  wire         usb31_phy_reconfig_rst_reset,           //   usb31_phy_reconfig_rst.reset
		input  wire         usb31_phy_reconfig_clk_clk,             //   usb31_phy_reconfig_clk.clk
		input  wire [20:0]  usb31_phy_reconfig_slave_address,       // usb31_phy_reconfig_slave.address
		input  wire [3:0]   usb31_phy_reconfig_slave_byteenable,    //                         .byteenable
		output wire         usb31_phy_reconfig_slave_readdatavalid, //                         .readdatavalid
		input  wire         usb31_phy_reconfig_slave_read,          //                         .read
		input  wire         usb31_phy_reconfig_slave_write,         //                         .write
		output wire [31:0]  usb31_phy_reconfig_slave_readdata,      //                         .readdata
		input  wire [31:0]  usb31_phy_reconfig_slave_writedata,     //                         .writedata
		output wire         usb31_phy_reconfig_slave_waitrequest,   //                         .waitrequest
		input  wire         f2sdram_clk_clk,                        //              f2sdram_clk.clk
		input  wire         f2sdram_rst_reset,                      //              f2sdram_rst.reset
		output wire         emif_hps_emif_mem_0_mem_ck_t,           //      emif_hps_emif_mem_0.mem_ck_t
		output wire         emif_hps_emif_mem_0_mem_ck_c,           //                         .mem_ck_c
		output wire         emif_hps_emif_mem_0_mem_cke,            //                         .mem_cke
		output wire         emif_hps_emif_mem_0_mem_odt,            //                         .mem_odt
		output wire         emif_hps_emif_mem_0_mem_cs_n,           //                         .mem_cs_n
		output wire [16:0]  emif_hps_emif_mem_0_mem_a,              //                         .mem_a
		output wire [1:0]   emif_hps_emif_mem_0_mem_ba,             //                         .mem_ba
		output wire         emif_hps_emif_mem_0_mem_bg,             //                         .mem_bg
		output wire         emif_hps_emif_mem_0_mem_act_n,          //                         .mem_act_n
		output wire         emif_hps_emif_mem_0_mem_par,            //                         .mem_par
		input  wire         emif_hps_emif_mem_0_mem_alert_n,        //                         .mem_alert_n
		output wire         emif_hps_emif_mem_0_mem_reset_n,        //                         .mem_reset_n
		inout  wire [31:0]  emif_hps_emif_mem_0_mem_dq,             //                         .mem_dq
		inout  wire [3:0]   emif_hps_emif_mem_0_mem_dqs_t,          //                         .mem_dqs_t
		inout  wire [3:0]   emif_hps_emif_mem_0_mem_dqs_c,          //                         .mem_dqs_c
		inout  wire [3:0]   emif_hps_emif_mem_0_mem_dbi_n,          //                         .mem_dbi_n
		input  wire         emif_hps_emif_oct_0_oct_rzqin,          //      emif_hps_emif_oct_0.oct_rzqin
		input  wire         emif_hps_emif_ref_clk_0_clk,            //  emif_hps_emif_ref_clk_0.clk
		input  wire         f2sdram_adapter_clk_clk,                //      f2sdram_adapter_clk.clk
		input  wire         f2sdram_adapter_rst_reset,              //      f2sdram_adapter_rst.reset
		input  wire [31:0]  f2sdram_adapter_axi4_sub_araddr,        // f2sdram_adapter_axi4_sub.araddr
		input  wire [1:0]   f2sdram_adapter_axi4_sub_arburst,       //                         .arburst
		input  wire [3:0]   f2sdram_adapter_axi4_sub_arcache,       //                         .arcache
		input  wire [4:0]   f2sdram_adapter_axi4_sub_arid,          //                         .arid
		input  wire [7:0]   f2sdram_adapter_axi4_sub_arlen,         //                         .arlen
		input  wire         f2sdram_adapter_axi4_sub_arlock,        //                         .arlock
		input  wire [2:0]   f2sdram_adapter_axi4_sub_arprot,        //                         .arprot
		input  wire [3:0]   f2sdram_adapter_axi4_sub_arqos,         //                         .arqos
		output wire         f2sdram_adapter_axi4_sub_arready,       //                         .arready
		input  wire [2:0]   f2sdram_adapter_axi4_sub_arsize,        //                         .arsize
		input  wire         f2sdram_adapter_axi4_sub_arvalid,       //                         .arvalid
		input  wire [31:0]  f2sdram_adapter_axi4_sub_awaddr,        //                         .awaddr
		input  wire [1:0]   f2sdram_adapter_axi4_sub_awburst,       //                         .awburst
		input  wire [3:0]   f2sdram_adapter_axi4_sub_awcache,       //                         .awcache
		input  wire [4:0]   f2sdram_adapter_axi4_sub_awid,          //                         .awid
		input  wire [7:0]   f2sdram_adapter_axi4_sub_awlen,         //                         .awlen
		input  wire         f2sdram_adapter_axi4_sub_awlock,        //                         .awlock
		input  wire [2:0]   f2sdram_adapter_axi4_sub_awprot,        //                         .awprot
		input  wire [3:0]   f2sdram_adapter_axi4_sub_awqos,         //                         .awqos
		output wire         f2sdram_adapter_axi4_sub_awready,       //                         .awready
		input  wire [2:0]   f2sdram_adapter_axi4_sub_awsize,        //                         .awsize
		input  wire         f2sdram_adapter_axi4_sub_awvalid,       //                         .awvalid
		output wire [4:0]   f2sdram_adapter_axi4_sub_bid,           //                         .bid
		input  wire         f2sdram_adapter_axi4_sub_bready,        //                         .bready
		output wire [1:0]   f2sdram_adapter_axi4_sub_bresp,         //                         .bresp
		output wire         f2sdram_adapter_axi4_sub_bvalid,        //                         .bvalid
		output wire [255:0] f2sdram_adapter_axi4_sub_rdata,         //                         .rdata
		output wire [4:0]   f2sdram_adapter_axi4_sub_rid,           //                         .rid
		output wire         f2sdram_adapter_axi4_sub_rlast,         //                         .rlast
		input  wire         f2sdram_adapter_axi4_sub_rready,        //                         .rready
		output wire [1:0]   f2sdram_adapter_axi4_sub_rresp,         //                         .rresp
		output wire         f2sdram_adapter_axi4_sub_rvalid,        //                         .rvalid
		input  wire [255:0] f2sdram_adapter_axi4_sub_wdata,         //                         .wdata
		input  wire         f2sdram_adapter_axi4_sub_wlast,         //                         .wlast
		output wire         f2sdram_adapter_axi4_sub_wready,        //                         .wready
		input  wire [31:0]  f2sdram_adapter_axi4_sub_wstrb,         //                         .wstrb
		input  wire         f2sdram_adapter_axi4_sub_wvalid,        //                         .wvalid
		input  wire [7:0]   f2sdram_adapter_axi4_sub_aruser,        //                         .aruser
		input  wire [7:0]   f2sdram_adapter_axi4_sub_awuser,        //                         .awuser
		input  wire [7:0]   f2sdram_adapter_axi4_sub_wuser,         //                         .wuser
		output wire [7:0]   f2sdram_adapter_axi4_sub_buser,         //                         .buser
		input  wire [3:0]   f2sdram_adapter_axi4_sub_arregion,      //                         .arregion
		output wire [7:0]   f2sdram_adapter_axi4_sub_ruser,         //                         .ruser
		input  wire [3:0]   f2sdram_adapter_axi4_sub_awregion,      //                         .awregion
		output wire [0:0]   o_pma_cu_clk_clk                        //             o_pma_cu_clk.clk
	);

	wire    [7:0] f2sdram_adapter_axi4_man_ruser;             // agilex_hps:f2sdram_ruser -> f2sdram_adapter:man_ruser
	wire    [7:0] f2sdram_adapter_axi4_man_wuser;             // f2sdram_adapter:man_wuser -> agilex_hps:f2sdram_wuser
	wire    [1:0] f2sdram_adapter_axi4_man_awburst;           // f2sdram_adapter:man_awburst -> agilex_hps:f2sdram_awburst
	wire    [3:0] f2sdram_adapter_axi4_man_arregion;          // f2sdram_adapter:man_arregion -> agilex_hps:f2sdram_arregion
	wire    [7:0] f2sdram_adapter_axi4_man_arlen;             // f2sdram_adapter:man_arlen -> agilex_hps:f2sdram_arlen
	wire    [3:0] f2sdram_adapter_axi4_man_arqos;             // f2sdram_adapter:man_arqos -> agilex_hps:f2sdram_arqos
	wire    [7:0] f2sdram_adapter_axi4_man_awuser;            // f2sdram_adapter:man_awuser -> agilex_hps:f2sdram_awuser
	wire          f2sdram_adapter_axi4_man_wready;            // agilex_hps:f2sdram_wready -> f2sdram_adapter:man_wready
	wire   [31:0] f2sdram_adapter_axi4_man_wstrb;             // f2sdram_adapter:man_wstrb -> agilex_hps:f2sdram_wstrb
	wire    [4:0] f2sdram_adapter_axi4_man_rid;               // agilex_hps:f2sdram_rid -> f2sdram_adapter:man_rid
	wire          f2sdram_adapter_axi4_man_rready;            // f2sdram_adapter:man_rready -> agilex_hps:f2sdram_rready
	wire    [7:0] f2sdram_adapter_axi4_man_awlen;             // f2sdram_adapter:man_awlen -> agilex_hps:f2sdram_awlen
	wire    [3:0] f2sdram_adapter_axi4_man_awqos;             // f2sdram_adapter:man_awqos -> agilex_hps:f2sdram_awqos
	wire    [3:0] f2sdram_adapter_axi4_man_arcache;           // f2sdram_adapter:man_arcache -> agilex_hps:f2sdram_arcache
	wire   [31:0] f2sdram_adapter_axi4_man_araddr;            // f2sdram_adapter:man_araddr -> agilex_hps:f2sdram_araddr
	wire          f2sdram_adapter_axi4_man_wvalid;            // f2sdram_adapter:man_wvalid -> agilex_hps:f2sdram_wvalid
	wire    [2:0] f2sdram_adapter_axi4_man_arprot;            // f2sdram_adapter:man_arprot -> agilex_hps:f2sdram_arprot
	wire          f2sdram_adapter_axi4_man_arvalid;           // f2sdram_adapter:man_arvalid -> agilex_hps:f2sdram_arvalid
	wire    [2:0] f2sdram_adapter_axi4_man_awprot;            // f2sdram_adapter:man_awprot -> agilex_hps:f2sdram_awprot
	wire  [255:0] f2sdram_adapter_axi4_man_wdata;             // f2sdram_adapter:man_wdata -> agilex_hps:f2sdram_wdata
	wire    [4:0] f2sdram_adapter_axi4_man_arid;              // f2sdram_adapter:man_arid -> agilex_hps:f2sdram_arid
	wire    [3:0] f2sdram_adapter_axi4_man_awcache;           // f2sdram_adapter:man_awcache -> agilex_hps:f2sdram_awcache
	wire          f2sdram_adapter_axi4_man_arlock;            // f2sdram_adapter:man_arlock -> agilex_hps:f2sdram_arlock
	wire          f2sdram_adapter_axi4_man_awlock;            // f2sdram_adapter:man_awlock -> agilex_hps:f2sdram_awlock
	wire   [31:0] f2sdram_adapter_axi4_man_awaddr;            // f2sdram_adapter:man_awaddr -> agilex_hps:f2sdram_awaddr
	wire          f2sdram_adapter_axi4_man_arready;           // agilex_hps:f2sdram_arready -> f2sdram_adapter:man_arready
	wire    [1:0] f2sdram_adapter_axi4_man_bresp;             // agilex_hps:f2sdram_bresp -> f2sdram_adapter:man_bresp
	wire  [255:0] f2sdram_adapter_axi4_man_rdata;             // agilex_hps:f2sdram_rdata -> f2sdram_adapter:man_rdata
	wire    [1:0] f2sdram_adapter_axi4_man_arburst;           // f2sdram_adapter:man_arburst -> agilex_hps:f2sdram_arburst
	wire          f2sdram_adapter_axi4_man_awready;           // agilex_hps:f2sdram_awready -> f2sdram_adapter:man_awready
	wire    [2:0] f2sdram_adapter_axi4_man_arsize;            // f2sdram_adapter:man_arsize -> agilex_hps:f2sdram_arsize
	wire          f2sdram_adapter_axi4_man_bready;            // f2sdram_adapter:man_bready -> agilex_hps:f2sdram_bready
	wire          f2sdram_adapter_axi4_man_rlast;             // agilex_hps:f2sdram_rlast -> f2sdram_adapter:man_rlast
	wire          f2sdram_adapter_axi4_man_wlast;             // f2sdram_adapter:man_wlast -> agilex_hps:f2sdram_wlast
	wire    [3:0] f2sdram_adapter_axi4_man_awregion;          // f2sdram_adapter:man_awregion -> agilex_hps:f2sdram_awregion
	wire    [7:0] f2sdram_adapter_axi4_man_buser;             // agilex_hps:f2sdram_buser -> f2sdram_adapter:man_buser
	wire    [1:0] f2sdram_adapter_axi4_man_rresp;             // agilex_hps:f2sdram_rresp -> f2sdram_adapter:man_rresp
	wire    [4:0] f2sdram_adapter_axi4_man_awid;              // f2sdram_adapter:man_awid -> agilex_hps:f2sdram_awid
	wire    [4:0] f2sdram_adapter_axi4_man_bid;               // agilex_hps:f2sdram_bid -> f2sdram_adapter:man_bid
	wire          f2sdram_adapter_axi4_man_bvalid;            // agilex_hps:f2sdram_bvalid -> f2sdram_adapter:man_bvalid
	wire    [2:0] f2sdram_adapter_axi4_man_awsize;            // f2sdram_adapter:man_awsize -> agilex_hps:f2sdram_awsize
	wire          f2sdram_adapter_axi4_man_awvalid;           // f2sdram_adapter:man_awvalid -> agilex_hps:f2sdram_awvalid
	wire          f2sdram_adapter_axi4_man_rvalid;            // agilex_hps:f2sdram_rvalid -> f2sdram_adapter:man_rvalid
	wire    [7:0] f2sdram_adapter_axi4_man_aruser;            // f2sdram_adapter:man_aruser -> agilex_hps:f2sdram_aruser
	wire          emif_hps_s0_axil_clk_clk;                   // emif_hps:s0_noc_axi4lite_clk -> [agilex_hps:io96b0_csr_axi_clk_clk, mm_interconnect_2:emif_hps_s0_axil_clk_clk, rst_controller_002:clk]
	wire          emif_hps_usr_clk_0_clk;                     // emif_hps:noc_aclk_0 -> [agilex_hps:io96b0_ch0_axi_clk_clk, mm_interconnect_1:emif_hps_usr_clk_0_clk, rst_controller:clk, rst_controller_001:clk]
	wire          emif_hps_s0_axil_rst_n_reset;               // emif_hps:s0_noc_axi4lite_rst_n -> [agilex_hps:io96b0_csr_axi_rst_reset_n, rst_controller_002:reset_in0]
	wire   [31:0] agilex_hps_io96b0_ch0_axi_ruser;            // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_ruser -> agilex_hps:io96b0_ch0_axi_ruser
	wire   [31:0] agilex_hps_io96b0_ch0_axi_wuser;            // agilex_hps:io96b0_ch0_axi_wuser -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_wuser
	wire    [1:0] agilex_hps_io96b0_ch0_axi_awburst;          // agilex_hps:io96b0_ch0_axi_awburst -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awburst
	wire    [7:0] agilex_hps_io96b0_ch0_axi_arlen;            // agilex_hps:io96b0_ch0_axi_arlen -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arlen
	wire    [3:0] agilex_hps_io96b0_ch0_axi_arqos;            // agilex_hps:io96b0_ch0_axi_arqos -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arqos
	wire   [13:0] agilex_hps_io96b0_ch0_axi_awuser;           // agilex_hps:io96b0_ch0_axi_awuser -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awuser
	wire          agilex_hps_io96b0_ch0_axi_wready;           // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_wready -> agilex_hps:io96b0_ch0_axi_wready
	wire   [31:0] agilex_hps_io96b0_ch0_axi_wstrb;            // agilex_hps:io96b0_ch0_axi_wstrb -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_wstrb
	wire    [6:0] agilex_hps_io96b0_ch0_axi_rid;              // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_rid -> agilex_hps:io96b0_ch0_axi_rid
	wire          agilex_hps_io96b0_ch0_axi_rready;           // agilex_hps:io96b0_ch0_axi_rready -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_rready
	wire    [7:0] agilex_hps_io96b0_ch0_axi_awlen;            // agilex_hps:io96b0_ch0_axi_awlen -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awlen
	wire    [3:0] agilex_hps_io96b0_ch0_axi_awqos;            // agilex_hps:io96b0_ch0_axi_awqos -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awqos
	wire   [43:0] agilex_hps_io96b0_ch0_axi_araddr;           // agilex_hps:io96b0_ch0_axi_araddr -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_araddr
	wire          agilex_hps_io96b0_ch0_axi_wvalid;           // agilex_hps:io96b0_ch0_axi_wvalid -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_wvalid
	wire    [2:0] agilex_hps_io96b0_ch0_axi_arprot;           // agilex_hps:io96b0_ch0_axi_arprot -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arprot
	wire          agilex_hps_io96b0_ch0_axi_arvalid;          // agilex_hps:io96b0_ch0_axi_arvalid -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arvalid
	wire  [255:0] agilex_hps_io96b0_ch0_axi_wdata;            // agilex_hps:io96b0_ch0_axi_wdata -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_wdata
	wire    [2:0] agilex_hps_io96b0_ch0_axi_awprot;           // agilex_hps:io96b0_ch0_axi_awprot -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awprot
	wire    [6:0] agilex_hps_io96b0_ch0_axi_arid;             // agilex_hps:io96b0_ch0_axi_arid -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arid
	wire          agilex_hps_io96b0_ch0_axi_arlock;           // agilex_hps:io96b0_ch0_axi_arlock -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arlock
	wire          agilex_hps_io96b0_ch0_axi_awlock;           // agilex_hps:io96b0_ch0_axi_awlock -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awlock
	wire   [43:0] agilex_hps_io96b0_ch0_axi_awaddr;           // agilex_hps:io96b0_ch0_axi_awaddr -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awaddr
	wire          agilex_hps_io96b0_ch0_axi_arready;          // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arready -> agilex_hps:io96b0_ch0_axi_arready
	wire    [1:0] agilex_hps_io96b0_ch0_axi_bresp;            // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_bresp -> agilex_hps:io96b0_ch0_axi_bresp
	wire  [255:0] agilex_hps_io96b0_ch0_axi_rdata;            // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_rdata -> agilex_hps:io96b0_ch0_axi_rdata
	wire          agilex_hps_io96b0_ch0_axi_awready;          // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awready -> agilex_hps:io96b0_ch0_axi_awready
	wire    [1:0] agilex_hps_io96b0_ch0_axi_arburst;          // agilex_hps:io96b0_ch0_axi_arburst -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arburst
	wire    [2:0] agilex_hps_io96b0_ch0_axi_arsize;           // agilex_hps:io96b0_ch0_axi_arsize -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_arsize
	wire          agilex_hps_io96b0_ch0_axi_rlast;            // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_rlast -> agilex_hps:io96b0_ch0_axi_rlast
	wire          agilex_hps_io96b0_ch0_axi_bready;           // agilex_hps:io96b0_ch0_axi_bready -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_bready
	wire          agilex_hps_io96b0_ch0_axi_wlast;            // agilex_hps:io96b0_ch0_axi_wlast -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_wlast
	wire    [1:0] agilex_hps_io96b0_ch0_axi_rresp;            // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_rresp -> agilex_hps:io96b0_ch0_axi_rresp
	wire    [6:0] agilex_hps_io96b0_ch0_axi_bid;              // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_bid -> agilex_hps:io96b0_ch0_axi_bid
	wire    [6:0] agilex_hps_io96b0_ch0_axi_awid;             // agilex_hps:io96b0_ch0_axi_awid -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awid
	wire          agilex_hps_io96b0_ch0_axi_bvalid;           // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_bvalid -> agilex_hps:io96b0_ch0_axi_bvalid
	wire          agilex_hps_io96b0_ch0_axi_rvalid;           // mm_interconnect_1:agilex_hps_io96b0_ch0_axi_rvalid -> agilex_hps:io96b0_ch0_axi_rvalid
	wire   [13:0] agilex_hps_io96b0_ch0_axi_aruser;           // agilex_hps:io96b0_ch0_axi_aruser -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_aruser
	wire    [2:0] agilex_hps_io96b0_ch0_axi_awsize;           // agilex_hps:io96b0_ch0_axi_awsize -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awsize
	wire          agilex_hps_io96b0_ch0_axi_awvalid;          // agilex_hps:io96b0_ch0_axi_awvalid -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_awvalid
	wire   [31:0] mm_interconnect_1_emif_hps_s0_axi4_ruser;   // emif_hps:s0_axi4_ruser -> mm_interconnect_1:emif_hps_s0_axi4_ruser
	wire   [31:0] mm_interconnect_1_emif_hps_s0_axi4_wuser;   // mm_interconnect_1:emif_hps_s0_axi4_wuser -> emif_hps:s0_axi4_wuser
	wire    [1:0] mm_interconnect_1_emif_hps_s0_axi4_awburst; // mm_interconnect_1:emif_hps_s0_axi4_awburst -> emif_hps:s0_axi4_awburst
	wire   [13:0] mm_interconnect_1_emif_hps_s0_axi4_awuser;  // mm_interconnect_1:emif_hps_s0_axi4_awuser -> emif_hps:s0_axi4_awuser
	wire    [7:0] mm_interconnect_1_emif_hps_s0_axi4_arlen;   // mm_interconnect_1:emif_hps_s0_axi4_arlen -> emif_hps:s0_axi4_arlen
	wire    [3:0] mm_interconnect_1_emif_hps_s0_axi4_arqos;   // mm_interconnect_1:emif_hps_s0_axi4_arqos -> emif_hps:s0_axi4_arqos
	wire   [31:0] mm_interconnect_1_emif_hps_s0_axi4_wstrb;   // mm_interconnect_1:emif_hps_s0_axi4_wstrb -> emif_hps:s0_axi4_wstrb
	wire          mm_interconnect_1_emif_hps_s0_axi4_wready;  // emif_hps:s0_axi4_wready -> mm_interconnect_1:emif_hps_s0_axi4_wready
	wire    [6:0] mm_interconnect_1_emif_hps_s0_axi4_rid;     // emif_hps:s0_axi4_rid -> mm_interconnect_1:emif_hps_s0_axi4_rid
	wire          mm_interconnect_1_emif_hps_s0_axi4_rready;  // mm_interconnect_1:emif_hps_s0_axi4_rready -> emif_hps:s0_axi4_rready
	wire    [7:0] mm_interconnect_1_emif_hps_s0_axi4_awlen;   // mm_interconnect_1:emif_hps_s0_axi4_awlen -> emif_hps:s0_axi4_awlen
	wire    [3:0] mm_interconnect_1_emif_hps_s0_axi4_awqos;   // mm_interconnect_1:emif_hps_s0_axi4_awqos -> emif_hps:s0_axi4_awqos
	wire          mm_interconnect_1_emif_hps_s0_axi4_wvalid;  // mm_interconnect_1:emif_hps_s0_axi4_wvalid -> emif_hps:s0_axi4_wvalid
	wire   [39:0] mm_interconnect_1_emif_hps_s0_axi4_araddr;  // mm_interconnect_1:emif_hps_s0_axi4_araddr -> emif_hps:s0_axi4_araddr
	wire    [2:0] mm_interconnect_1_emif_hps_s0_axi4_arprot;  // mm_interconnect_1:emif_hps_s0_axi4_arprot -> emif_hps:s0_axi4_arprot
	wire    [2:0] mm_interconnect_1_emif_hps_s0_axi4_awprot;  // mm_interconnect_1:emif_hps_s0_axi4_awprot -> emif_hps:s0_axi4_awprot
	wire  [255:0] mm_interconnect_1_emif_hps_s0_axi4_wdata;   // mm_interconnect_1:emif_hps_s0_axi4_wdata -> emif_hps:s0_axi4_wdata
	wire          mm_interconnect_1_emif_hps_s0_axi4_arvalid; // mm_interconnect_1:emif_hps_s0_axi4_arvalid -> emif_hps:s0_axi4_arvalid
	wire    [6:0] mm_interconnect_1_emif_hps_s0_axi4_arid;    // mm_interconnect_1:emif_hps_s0_axi4_arid -> emif_hps:s0_axi4_arid
	wire    [0:0] mm_interconnect_1_emif_hps_s0_axi4_arlock;  // mm_interconnect_1:emif_hps_s0_axi4_arlock -> emif_hps:s0_axi4_arlock
	wire    [0:0] mm_interconnect_1_emif_hps_s0_axi4_awlock;  // mm_interconnect_1:emif_hps_s0_axi4_awlock -> emif_hps:s0_axi4_awlock
	wire   [39:0] mm_interconnect_1_emif_hps_s0_axi4_awaddr;  // mm_interconnect_1:emif_hps_s0_axi4_awaddr -> emif_hps:s0_axi4_awaddr
	wire    [1:0] mm_interconnect_1_emif_hps_s0_axi4_bresp;   // emif_hps:s0_axi4_bresp -> mm_interconnect_1:emif_hps_s0_axi4_bresp
	wire          mm_interconnect_1_emif_hps_s0_axi4_arready; // emif_hps:s0_axi4_arready -> mm_interconnect_1:emif_hps_s0_axi4_arready
	wire  [255:0] mm_interconnect_1_emif_hps_s0_axi4_rdata;   // emif_hps:s0_axi4_rdata -> mm_interconnect_1:emif_hps_s0_axi4_rdata
	wire          mm_interconnect_1_emif_hps_s0_axi4_awready; // emif_hps:s0_axi4_awready -> mm_interconnect_1:emif_hps_s0_axi4_awready
	wire    [1:0] mm_interconnect_1_emif_hps_s0_axi4_arburst; // mm_interconnect_1:emif_hps_s0_axi4_arburst -> emif_hps:s0_axi4_arburst
	wire    [2:0] mm_interconnect_1_emif_hps_s0_axi4_arsize;  // mm_interconnect_1:emif_hps_s0_axi4_arsize -> emif_hps:s0_axi4_arsize
	wire          mm_interconnect_1_emif_hps_s0_axi4_bready;  // mm_interconnect_1:emif_hps_s0_axi4_bready -> emif_hps:s0_axi4_bready
	wire          mm_interconnect_1_emif_hps_s0_axi4_rlast;   // emif_hps:s0_axi4_rlast -> mm_interconnect_1:emif_hps_s0_axi4_rlast
	wire          mm_interconnect_1_emif_hps_s0_axi4_wlast;   // mm_interconnect_1:emif_hps_s0_axi4_wlast -> emif_hps:s0_axi4_wlast
	wire    [1:0] mm_interconnect_1_emif_hps_s0_axi4_rresp;   // emif_hps:s0_axi4_rresp -> mm_interconnect_1:emif_hps_s0_axi4_rresp
	wire    [6:0] mm_interconnect_1_emif_hps_s0_axi4_awid;    // mm_interconnect_1:emif_hps_s0_axi4_awid -> emif_hps:s0_axi4_awid
	wire    [6:0] mm_interconnect_1_emif_hps_s0_axi4_bid;     // emif_hps:s0_axi4_bid -> mm_interconnect_1:emif_hps_s0_axi4_bid
	wire          mm_interconnect_1_emif_hps_s0_axi4_bvalid;  // emif_hps:s0_axi4_bvalid -> mm_interconnect_1:emif_hps_s0_axi4_bvalid
	wire    [2:0] mm_interconnect_1_emif_hps_s0_axi4_awsize;  // mm_interconnect_1:emif_hps_s0_axi4_awsize -> emif_hps:s0_axi4_awsize
	wire          mm_interconnect_1_emif_hps_s0_axi4_awvalid; // mm_interconnect_1:emif_hps_s0_axi4_awvalid -> emif_hps:s0_axi4_awvalid
	wire   [13:0] mm_interconnect_1_emif_hps_s0_axi4_aruser;  // mm_interconnect_1:emif_hps_s0_axi4_aruser -> emif_hps:s0_axi4_aruser
	wire          mm_interconnect_1_emif_hps_s0_axi4_rvalid;  // emif_hps:s0_axi4_rvalid -> mm_interconnect_1:emif_hps_s0_axi4_rvalid
	wire   [31:0] agilex_hps_io96b0_csr_axi_awaddr;           // agilex_hps:io96b0_csr_axi_awaddr -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_awaddr
	wire          agilex_hps_io96b0_csr_axi_arready;          // mm_interconnect_2:agilex_hps_io96b0_csr_axi_arready -> agilex_hps:io96b0_csr_axi_arready
	wire    [1:0] agilex_hps_io96b0_csr_axi_bresp;            // mm_interconnect_2:agilex_hps_io96b0_csr_axi_bresp -> agilex_hps:io96b0_csr_axi_bresp
	wire   [31:0] agilex_hps_io96b0_csr_axi_rdata;            // mm_interconnect_2:agilex_hps_io96b0_csr_axi_rdata -> agilex_hps:io96b0_csr_axi_rdata
	wire          agilex_hps_io96b0_csr_axi_wready;           // mm_interconnect_2:agilex_hps_io96b0_csr_axi_wready -> agilex_hps:io96b0_csr_axi_wready
	wire    [3:0] agilex_hps_io96b0_csr_axi_wstrb;            // agilex_hps:io96b0_csr_axi_wstrb -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_wstrb
	wire          agilex_hps_io96b0_csr_axi_awready;          // mm_interconnect_2:agilex_hps_io96b0_csr_axi_awready -> agilex_hps:io96b0_csr_axi_awready
	wire          agilex_hps_io96b0_csr_axi_rready;           // agilex_hps:io96b0_csr_axi_rready -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_rready
	wire          agilex_hps_io96b0_csr_axi_bready;           // agilex_hps:io96b0_csr_axi_bready -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_bready
	wire   [31:0] agilex_hps_io96b0_csr_axi_araddr;           // agilex_hps:io96b0_csr_axi_araddr -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_araddr
	wire          agilex_hps_io96b0_csr_axi_wvalid;           // agilex_hps:io96b0_csr_axi_wvalid -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_wvalid
	wire    [1:0] agilex_hps_io96b0_csr_axi_rresp;            // mm_interconnect_2:agilex_hps_io96b0_csr_axi_rresp -> agilex_hps:io96b0_csr_axi_rresp
	wire    [2:0] agilex_hps_io96b0_csr_axi_arprot;           // agilex_hps:io96b0_csr_axi_arprot -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_arprot
	wire          agilex_hps_io96b0_csr_axi_arvalid;          // agilex_hps:io96b0_csr_axi_arvalid -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_arvalid
	wire   [31:0] agilex_hps_io96b0_csr_axi_wdata;            // agilex_hps:io96b0_csr_axi_wdata -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_wdata
	wire    [2:0] agilex_hps_io96b0_csr_axi_awprot;           // agilex_hps:io96b0_csr_axi_awprot -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_awprot
	wire          agilex_hps_io96b0_csr_axi_bvalid;           // mm_interconnect_2:agilex_hps_io96b0_csr_axi_bvalid -> agilex_hps:io96b0_csr_axi_bvalid
	wire          agilex_hps_io96b0_csr_axi_rvalid;           // mm_interconnect_2:agilex_hps_io96b0_csr_axi_rvalid -> agilex_hps:io96b0_csr_axi_rvalid
	wire          agilex_hps_io96b0_csr_axi_awvalid;          // agilex_hps:io96b0_csr_axi_awvalid -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_awvalid
	wire   [26:0] mm_interconnect_2_emif_hps_s0_axil_awaddr;  // mm_interconnect_2:emif_hps_s0_axil_awaddr -> emif_hps:s0_noc_axi4lite_awaddr
	wire    [1:0] mm_interconnect_2_emif_hps_s0_axil_bresp;   // emif_hps:s0_noc_axi4lite_bresp -> mm_interconnect_2:emif_hps_s0_axil_bresp
	wire          mm_interconnect_2_emif_hps_s0_axil_arready; // emif_hps:s0_noc_axi4lite_arready -> mm_interconnect_2:emif_hps_s0_axil_arready
	wire   [31:0] mm_interconnect_2_emif_hps_s0_axil_rdata;   // emif_hps:s0_noc_axi4lite_rdata -> mm_interconnect_2:emif_hps_s0_axil_rdata
	wire    [3:0] mm_interconnect_2_emif_hps_s0_axil_wstrb;   // mm_interconnect_2:emif_hps_s0_axil_wstrb -> emif_hps:s0_noc_axi4lite_wstrb
	wire          mm_interconnect_2_emif_hps_s0_axil_wready;  // emif_hps:s0_noc_axi4lite_wready -> mm_interconnect_2:emif_hps_s0_axil_wready
	wire          mm_interconnect_2_emif_hps_s0_axil_awready; // emif_hps:s0_noc_axi4lite_awready -> mm_interconnect_2:emif_hps_s0_axil_awready
	wire          mm_interconnect_2_emif_hps_s0_axil_rready;  // mm_interconnect_2:emif_hps_s0_axil_rready -> emif_hps:s0_noc_axi4lite_rready
	wire          mm_interconnect_2_emif_hps_s0_axil_bready;  // mm_interconnect_2:emif_hps_s0_axil_bready -> emif_hps:s0_noc_axi4lite_bready
	wire          mm_interconnect_2_emif_hps_s0_axil_wvalid;  // mm_interconnect_2:emif_hps_s0_axil_wvalid -> emif_hps:s0_noc_axi4lite_wvalid
	wire   [26:0] mm_interconnect_2_emif_hps_s0_axil_araddr;  // mm_interconnect_2:emif_hps_s0_axil_araddr -> emif_hps:s0_noc_axi4lite_araddr
	wire    [2:0] mm_interconnect_2_emif_hps_s0_axil_arprot;  // mm_interconnect_2:emif_hps_s0_axil_arprot -> emif_hps:s0_noc_axi4lite_arprot
	wire    [1:0] mm_interconnect_2_emif_hps_s0_axil_rresp;   // emif_hps:s0_noc_axi4lite_rresp -> mm_interconnect_2:emif_hps_s0_axil_rresp
	wire    [2:0] mm_interconnect_2_emif_hps_s0_axil_awprot;  // mm_interconnect_2:emif_hps_s0_axil_awprot -> emif_hps:s0_noc_axi4lite_awprot
	wire   [31:0] mm_interconnect_2_emif_hps_s0_axil_wdata;   // mm_interconnect_2:emif_hps_s0_axil_wdata -> emif_hps:s0_noc_axi4lite_wdata
	wire          mm_interconnect_2_emif_hps_s0_axil_arvalid; // mm_interconnect_2:emif_hps_s0_axil_arvalid -> emif_hps:s0_noc_axi4lite_arvalid
	wire          mm_interconnect_2_emif_hps_s0_axil_bvalid;  // emif_hps:s0_noc_axi4lite_bvalid -> mm_interconnect_2:emif_hps_s0_axil_bvalid
	wire          mm_interconnect_2_emif_hps_s0_axil_awvalid; // mm_interconnect_2:emif_hps_s0_axil_awvalid -> emif_hps:s0_noc_axi4lite_awvalid
	wire          mm_interconnect_2_emif_hps_s0_axil_rvalid;  // emif_hps:s0_noc_axi4lite_rvalid -> mm_interconnect_2:emif_hps_s0_axil_rvalid
	wire          rst_controller_reset_out_reset;             // rst_controller:reset_out -> agilex_hps:io96b0_ch0_axi_rst_reset_n
	wire          emif_hps_usr_rst_n_0_reset;                 // emif_hps:out_reset_0_n -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
	wire          rst_controller_001_reset_out_reset;         // rst_controller_001:reset_out -> mm_interconnect_1:agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset_reset
	wire          rst_controller_002_reset_out_reset;         // rst_controller_002:reset_out -> mm_interconnect_2:agilex_hps_io96b0_csr_axi_id_pad_clk_reset_reset_bridge_in_reset_reset

	agilex_hps agilex_hps (
		.h2f_reset_reset                        (h2f_reset_reset),                        //  output,    width = 1,                h2f_reset.reset
		.hps2fpga_axi_clock_clk                 (hps2fpga_clk_clk),                       //   input,    width = 1,       hps2fpga_axi_clock.clk
		.hps2fpga_axi_reset_reset               (hps2fpga_rst_reset),                     //   input,    width = 1,       hps2fpga_axi_reset.reset
		.hps2fpga_awid                          (hps2fpga_awid),                          //  output,    width = 4,                 hps2fpga.awid
		.hps2fpga_awaddr                        (hps2fpga_awaddr),                        //  output,   width = 38,                         .awaddr
		.hps2fpga_awlen                         (hps2fpga_awlen),                         //  output,    width = 8,                         .awlen
		.hps2fpga_awsize                        (hps2fpga_awsize),                        //  output,    width = 3,                         .awsize
		.hps2fpga_awburst                       (hps2fpga_awburst),                       //  output,    width = 2,                         .awburst
		.hps2fpga_awlock                        (hps2fpga_awlock),                        //  output,    width = 1,                         .awlock
		.hps2fpga_awcache                       (hps2fpga_awcache),                       //  output,    width = 4,                         .awcache
		.hps2fpga_awprot                        (hps2fpga_awprot),                        //  output,    width = 3,                         .awprot
		.hps2fpga_awvalid                       (hps2fpga_awvalid),                       //  output,    width = 1,                         .awvalid
		.hps2fpga_awready                       (hps2fpga_awready),                       //   input,    width = 1,                         .awready
		.hps2fpga_wdata                         (hps2fpga_wdata),                         //  output,  width = 128,                         .wdata
		.hps2fpga_wstrb                         (hps2fpga_wstrb),                         //  output,   width = 16,                         .wstrb
		.hps2fpga_wlast                         (hps2fpga_wlast),                         //  output,    width = 1,                         .wlast
		.hps2fpga_wvalid                        (hps2fpga_wvalid),                        //  output,    width = 1,                         .wvalid
		.hps2fpga_wready                        (hps2fpga_wready),                        //   input,    width = 1,                         .wready
		.hps2fpga_bid                           (hps2fpga_bid),                           //   input,    width = 4,                         .bid
		.hps2fpga_bresp                         (hps2fpga_bresp),                         //   input,    width = 2,                         .bresp
		.hps2fpga_bvalid                        (hps2fpga_bvalid),                        //   input,    width = 1,                         .bvalid
		.hps2fpga_bready                        (hps2fpga_bready),                        //  output,    width = 1,                         .bready
		.hps2fpga_arid                          (hps2fpga_arid),                          //  output,    width = 4,                         .arid
		.hps2fpga_araddr                        (hps2fpga_araddr),                        //  output,   width = 38,                         .araddr
		.hps2fpga_arlen                         (hps2fpga_arlen),                         //  output,    width = 8,                         .arlen
		.hps2fpga_arsize                        (hps2fpga_arsize),                        //  output,    width = 3,                         .arsize
		.hps2fpga_arburst                       (hps2fpga_arburst),                       //  output,    width = 2,                         .arburst
		.hps2fpga_arlock                        (hps2fpga_arlock),                        //  output,    width = 1,                         .arlock
		.hps2fpga_arcache                       (hps2fpga_arcache),                       //  output,    width = 4,                         .arcache
		.hps2fpga_arprot                        (hps2fpga_arprot),                        //  output,    width = 3,                         .arprot
		.hps2fpga_arvalid                       (hps2fpga_arvalid),                       //  output,    width = 1,                         .arvalid
		.hps2fpga_arready                       (hps2fpga_arready),                       //   input,    width = 1,                         .arready
		.hps2fpga_rid                           (hps2fpga_rid),                           //   input,    width = 4,                         .rid
		.hps2fpga_rdata                         (hps2fpga_rdata),                         //   input,  width = 128,                         .rdata
		.hps2fpga_rresp                         (hps2fpga_rresp),                         //   input,    width = 2,                         .rresp
		.hps2fpga_rlast                         (hps2fpga_rlast),                         //   input,    width = 1,                         .rlast
		.hps2fpga_rvalid                        (hps2fpga_rvalid),                        //   input,    width = 1,                         .rvalid
		.hps2fpga_rready                        (hps2fpga_rready),                        //  output,    width = 1,                         .rready
		.lwhps2fpga_axi_clock_clk               (lwhps2fpga_clk_clk),                     //   input,    width = 1,     lwhps2fpga_axi_clock.clk
		.lwhps2fpga_axi_reset_reset             (lwhps2fpga_rst_reset),                   //   input,    width = 1,     lwhps2fpga_axi_reset.reset
		.lwhps2fpga_awid                        (lwhps2fpga_awid),                        //  output,    width = 4,               lwhps2fpga.awid
		.lwhps2fpga_awaddr                      (lwhps2fpga_awaddr),                      //  output,   width = 29,                         .awaddr
		.lwhps2fpga_awlen                       (lwhps2fpga_awlen),                       //  output,    width = 8,                         .awlen
		.lwhps2fpga_awsize                      (lwhps2fpga_awsize),                      //  output,    width = 3,                         .awsize
		.lwhps2fpga_awburst                     (lwhps2fpga_awburst),                     //  output,    width = 2,                         .awburst
		.lwhps2fpga_awlock                      (lwhps2fpga_awlock),                      //  output,    width = 1,                         .awlock
		.lwhps2fpga_awcache                     (lwhps2fpga_awcache),                     //  output,    width = 4,                         .awcache
		.lwhps2fpga_awprot                      (lwhps2fpga_awprot),                      //  output,    width = 3,                         .awprot
		.lwhps2fpga_awvalid                     (lwhps2fpga_awvalid),                     //  output,    width = 1,                         .awvalid
		.lwhps2fpga_awready                     (lwhps2fpga_awready),                     //   input,    width = 1,                         .awready
		.lwhps2fpga_wdata                       (lwhps2fpga_wdata),                       //  output,   width = 32,                         .wdata
		.lwhps2fpga_wstrb                       (lwhps2fpga_wstrb),                       //  output,    width = 4,                         .wstrb
		.lwhps2fpga_wlast                       (lwhps2fpga_wlast),                       //  output,    width = 1,                         .wlast
		.lwhps2fpga_wvalid                      (lwhps2fpga_wvalid),                      //  output,    width = 1,                         .wvalid
		.lwhps2fpga_wready                      (lwhps2fpga_wready),                      //   input,    width = 1,                         .wready
		.lwhps2fpga_bid                         (lwhps2fpga_bid),                         //   input,    width = 4,                         .bid
		.lwhps2fpga_bresp                       (lwhps2fpga_bresp),                       //   input,    width = 2,                         .bresp
		.lwhps2fpga_bvalid                      (lwhps2fpga_bvalid),                      //   input,    width = 1,                         .bvalid
		.lwhps2fpga_bready                      (lwhps2fpga_bready),                      //  output,    width = 1,                         .bready
		.lwhps2fpga_arid                        (lwhps2fpga_arid),                        //  output,    width = 4,                         .arid
		.lwhps2fpga_araddr                      (lwhps2fpga_araddr),                      //  output,   width = 29,                         .araddr
		.lwhps2fpga_arlen                       (lwhps2fpga_arlen),                       //  output,    width = 8,                         .arlen
		.lwhps2fpga_arsize                      (lwhps2fpga_arsize),                      //  output,    width = 3,                         .arsize
		.lwhps2fpga_arburst                     (lwhps2fpga_arburst),                     //  output,    width = 2,                         .arburst
		.lwhps2fpga_arlock                      (lwhps2fpga_arlock),                      //  output,    width = 1,                         .arlock
		.lwhps2fpga_arcache                     (lwhps2fpga_arcache),                     //  output,    width = 4,                         .arcache
		.lwhps2fpga_arprot                      (lwhps2fpga_arprot),                      //  output,    width = 3,                         .arprot
		.lwhps2fpga_arvalid                     (lwhps2fpga_arvalid),                     //  output,    width = 1,                         .arvalid
		.lwhps2fpga_arready                     (lwhps2fpga_arready),                     //   input,    width = 1,                         .arready
		.lwhps2fpga_rid                         (lwhps2fpga_rid),                         //   input,    width = 4,                         .rid
		.lwhps2fpga_rdata                       (lwhps2fpga_rdata),                       //   input,   width = 32,                         .rdata
		.lwhps2fpga_rresp                       (lwhps2fpga_rresp),                       //   input,    width = 2,                         .rresp
		.lwhps2fpga_rlast                       (lwhps2fpga_rlast),                       //   input,    width = 1,                         .rlast
		.lwhps2fpga_rvalid                      (lwhps2fpga_rvalid),                      //   input,    width = 1,                         .rvalid
		.lwhps2fpga_rready                      (lwhps2fpga_rready),                      //  output,    width = 1,                         .rready
		.emac2_app_rst_reset_n                  (),                                       //  output,    width = 1,            emac2_app_rst.reset_n
		.h2f_warm_reset_handshake_reset_req     (),                                       //  output,    width = 1, h2f_warm_reset_handshake.reset_req
		.h2f_warm_reset_handshake_reset_ack     (),                                       //   input,    width = 1,                         .reset_ack
		.hps_io_hps_osc_clk                     (hps_io_hps_osc_clk),                     //   input,    width = 1,                   hps_io.hps_osc_clk
		.hps_io_sdmmc_data0                     (hps_io_sdmmc_data0),                     //   inout,    width = 1,                         .sdmmc_data0
		.hps_io_sdmmc_data1                     (hps_io_sdmmc_data1),                     //   inout,    width = 1,                         .sdmmc_data1
		.hps_io_sdmmc_cclk                      (hps_io_sdmmc_cclk),                      //  output,    width = 1,                         .sdmmc_cclk
		.hps_io_sdmmc_data2                     (hps_io_sdmmc_data2),                     //   inout,    width = 1,                         .sdmmc_data2
		.hps_io_sdmmc_data3                     (hps_io_sdmmc_data3),                     //   inout,    width = 1,                         .sdmmc_data3
		.hps_io_sdmmc_cmd                       (hps_io_sdmmc_cmd),                       //   inout,    width = 1,                         .sdmmc_cmd
		.hps_io_usb1_clk                        (hps_io_usb1_clk),                        //   input,    width = 1,                         .usb1_clk
		.hps_io_usb1_stp                        (hps_io_usb1_stp),                        //  output,    width = 1,                         .usb1_stp
		.hps_io_usb1_dir                        (hps_io_usb1_dir),                        //   input,    width = 1,                         .usb1_dir
		.hps_io_usb1_data0                      (hps_io_usb1_data0),                      //   inout,    width = 1,                         .usb1_data0
		.hps_io_usb1_data1                      (hps_io_usb1_data1),                      //   inout,    width = 1,                         .usb1_data1
		.hps_io_usb1_nxt                        (hps_io_usb1_nxt),                        //   input,    width = 1,                         .usb1_nxt
		.hps_io_usb1_data2                      (hps_io_usb1_data2),                      //   inout,    width = 1,                         .usb1_data2
		.hps_io_usb1_data3                      (hps_io_usb1_data3),                      //   inout,    width = 1,                         .usb1_data3
		.hps_io_usb1_data4                      (hps_io_usb1_data4),                      //   inout,    width = 1,                         .usb1_data4
		.hps_io_usb1_data5                      (hps_io_usb1_data5),                      //   inout,    width = 1,                         .usb1_data5
		.hps_io_usb1_data6                      (hps_io_usb1_data6),                      //   inout,    width = 1,                         .usb1_data6
		.hps_io_usb1_data7                      (hps_io_usb1_data7),                      //   inout,    width = 1,                         .usb1_data7
		.hps_io_emac2_tx_clk                    (hps_io_emac2_tx_clk),                    //  output,    width = 1,                         .emac2_tx_clk
		.hps_io_emac2_tx_ctl                    (hps_io_emac2_tx_ctl),                    //  output,    width = 1,                         .emac2_tx_ctl
		.hps_io_emac2_rx_clk                    (hps_io_emac2_rx_clk),                    //   input,    width = 1,                         .emac2_rx_clk
		.hps_io_emac2_rx_ctl                    (hps_io_emac2_rx_ctl),                    //   input,    width = 1,                         .emac2_rx_ctl
		.hps_io_emac2_txd0                      (hps_io_emac2_txd0),                      //  output,    width = 1,                         .emac2_txd0
		.hps_io_emac2_txd1                      (hps_io_emac2_txd1),                      //  output,    width = 1,                         .emac2_txd1
		.hps_io_emac2_rxd0                      (hps_io_emac2_rxd0),                      //   input,    width = 1,                         .emac2_rxd0
		.hps_io_emac2_rxd1                      (hps_io_emac2_rxd1),                      //   input,    width = 1,                         .emac2_rxd1
		.hps_io_emac2_txd2                      (hps_io_emac2_txd2),                      //  output,    width = 1,                         .emac2_txd2
		.hps_io_emac2_txd3                      (hps_io_emac2_txd3),                      //  output,    width = 1,                         .emac2_txd3
		.hps_io_emac2_rxd2                      (hps_io_emac2_rxd2),                      //   input,    width = 1,                         .emac2_rxd2
		.hps_io_emac2_rxd3                      (hps_io_emac2_rxd3),                      //   input,    width = 1,                         .emac2_rxd3
		.hps_io_mdio2_mdio                      (hps_io_mdio2_mdio),                      //   inout,    width = 1,                         .mdio2_mdio
		.hps_io_mdio2_mdc                       (hps_io_mdio2_mdc),                       //  output,    width = 1,                         .mdio2_mdc
		.hps_io_uart0_tx                        (hps_io_uart0_tx),                        //  output,    width = 1,                         .uart0_tx
		.hps_io_uart0_rx                        (hps_io_uart0_rx),                        //   input,    width = 1,                         .uart0_rx
		.hps_io_i2c0_sda                        (hps_io_i2c0_sda),                        //   inout,    width = 1,                         .i2c0_sda
		.hps_io_i2c0_scl                        (hps_io_i2c0_scl),                        //   inout,    width = 1,                         .i2c0_scl
		.hps_io_gpio0                           (hps_io_gpio0),                           //   inout,    width = 1,                         .gpio0
		.hps_io_gpio1                           (hps_io_gpio1),                           //   inout,    width = 1,                         .gpio1
		.hps_io_gpio8                           (hps_io_gpio8),                           //   inout,    width = 1,                         .gpio8
		.hps_io_gpio9                           (hps_io_gpio9),                           //   inout,    width = 1,                         .gpio9
		.hps_io_gpio10                          (hps_io_gpio10),                          //   inout,    width = 1,                         .gpio10
		.hps_io_gpio11                          (hps_io_gpio11),                          //   inout,    width = 1,                         .gpio11
		.hps_io_gpio28                          (hps_io_gpio28),                          //   inout,    width = 1,                         .gpio28
		.usb31_io_vbus_det                      (usb31_io_vbus_det),                      //   input,    width = 1,                 usb31_io.vbus_det
		.usb31_io_flt_bar                       (usb31_io_flt_bar),                       //   input,    width = 1,                         .flt_bar
		.usb31_io_usb_ctrl                      (usb31_io_usb_ctrl),                      //  output,    width = 2,                         .usb_ctrl
		.usb31_io_usb31_id                      (usb31_io_usb31_id),                      //   input,    width = 1,                         .usb31_id
		.fpga2hps_interrupt_irq                 (f2h_irq_in_irq),                         //   input,   width = 63,       fpga2hps_interrupt.irq
		.usb31_phy_pma_cpu_clk_clk              (usb31_phy_pma_cpu_clk_clk),              //   input,    width = 1,    usb31_phy_pma_cpu_clk.clk
		.usb31_phy_refclk_p_clk                 (usb31_phy_refclk_p_clk),                 //   input,    width = 1,       usb31_phy_refclk_p.clk
		.usb31_phy_refclk_n_clk                 (usb31_phy_refclk_n_clk),                 //   input,    width = 1,       usb31_phy_refclk_n.clk
		.usb31_phy_rx_serial_n_i_rx_serial_n    (usb31_phy_rx_serial_n_i_rx_serial_n),    //   input,    width = 1,    usb31_phy_rx_serial_n.i_rx_serial_n
		.usb31_phy_rx_serial_p_i_rx_serial_p    (usb31_phy_rx_serial_p_i_rx_serial_p),    //   input,    width = 1,    usb31_phy_rx_serial_p.i_rx_serial_p
		.usb31_phy_tx_serial_n_o_tx_serial_n    (usb31_phy_tx_serial_n_o_tx_serial_n),    //  output,    width = 1,    usb31_phy_tx_serial_n.o_tx_serial_n
		.usb31_phy_tx_serial_p_o_tx_serial_p    (usb31_phy_tx_serial_p_o_tx_serial_p),    //  output,    width = 1,    usb31_phy_tx_serial_p.o_tx_serial_p
		.usb31_phy_reconfig_rst_reset           (usb31_phy_reconfig_rst_reset),           //   input,    width = 1,   usb31_phy_reconfig_rst.reset
		.usb31_phy_reconfig_clk_clk             (usb31_phy_reconfig_clk_clk),             //   input,    width = 1,   usb31_phy_reconfig_clk.clk
		.usb31_phy_reconfig_slave_address       (usb31_phy_reconfig_slave_address),       //   input,   width = 21, usb31_phy_reconfig_slave.address
		.usb31_phy_reconfig_slave_byteenable    (usb31_phy_reconfig_slave_byteenable),    //   input,    width = 4,                         .byteenable
		.usb31_phy_reconfig_slave_readdatavalid (usb31_phy_reconfig_slave_readdatavalid), //  output,    width = 1,                         .readdatavalid
		.usb31_phy_reconfig_slave_read          (usb31_phy_reconfig_slave_read),          //   input,    width = 1,                         .read
		.usb31_phy_reconfig_slave_write         (usb31_phy_reconfig_slave_write),         //   input,    width = 1,                         .write
		.usb31_phy_reconfig_slave_readdata      (usb31_phy_reconfig_slave_readdata),      //  output,   width = 32,                         .readdata
		.usb31_phy_reconfig_slave_writedata     (usb31_phy_reconfig_slave_writedata),     //   input,   width = 32,                         .writedata
		.usb31_phy_reconfig_slave_waitrequest   (usb31_phy_reconfig_slave_waitrequest),   //  output,    width = 1,                         .waitrequest
		.f2sdram_axi_clock_clk                  (f2sdram_clk_clk),                        //   input,    width = 1,        f2sdram_axi_clock.clk
		.f2sdram_axi_reset_reset                (f2sdram_rst_reset),                      //   input,    width = 1,        f2sdram_axi_reset.reset
		.f2sdram_araddr                         (f2sdram_adapter_axi4_man_araddr),        //   input,   width = 32,                  f2sdram.araddr
		.f2sdram_arburst                        (f2sdram_adapter_axi4_man_arburst),       //   input,    width = 2,                         .arburst
		.f2sdram_arcache                        (f2sdram_adapter_axi4_man_arcache),       //   input,    width = 4,                         .arcache
		.f2sdram_arid                           (f2sdram_adapter_axi4_man_arid),          //   input,    width = 5,                         .arid
		.f2sdram_arlen                          (f2sdram_adapter_axi4_man_arlen),         //   input,    width = 8,                         .arlen
		.f2sdram_arlock                         (f2sdram_adapter_axi4_man_arlock),        //   input,    width = 1,                         .arlock
		.f2sdram_arprot                         (f2sdram_adapter_axi4_man_arprot),        //   input,    width = 3,                         .arprot
		.f2sdram_arqos                          (f2sdram_adapter_axi4_man_arqos),         //   input,    width = 4,                         .arqos
		.f2sdram_arready                        (f2sdram_adapter_axi4_man_arready),       //  output,    width = 1,                         .arready
		.f2sdram_arsize                         (f2sdram_adapter_axi4_man_arsize),        //   input,    width = 3,                         .arsize
		.f2sdram_arvalid                        (f2sdram_adapter_axi4_man_arvalid),       //   input,    width = 1,                         .arvalid
		.f2sdram_awaddr                         (f2sdram_adapter_axi4_man_awaddr),        //   input,   width = 32,                         .awaddr
		.f2sdram_awburst                        (f2sdram_adapter_axi4_man_awburst),       //   input,    width = 2,                         .awburst
		.f2sdram_awcache                        (f2sdram_adapter_axi4_man_awcache),       //   input,    width = 4,                         .awcache
		.f2sdram_awid                           (f2sdram_adapter_axi4_man_awid),          //   input,    width = 5,                         .awid
		.f2sdram_awlen                          (f2sdram_adapter_axi4_man_awlen),         //   input,    width = 8,                         .awlen
		.f2sdram_awlock                         (f2sdram_adapter_axi4_man_awlock),        //   input,    width = 1,                         .awlock
		.f2sdram_awprot                         (f2sdram_adapter_axi4_man_awprot),        //   input,    width = 3,                         .awprot
		.f2sdram_awqos                          (f2sdram_adapter_axi4_man_awqos),         //   input,    width = 4,                         .awqos
		.f2sdram_awready                        (f2sdram_adapter_axi4_man_awready),       //  output,    width = 1,                         .awready
		.f2sdram_awsize                         (f2sdram_adapter_axi4_man_awsize),        //   input,    width = 3,                         .awsize
		.f2sdram_awvalid                        (f2sdram_adapter_axi4_man_awvalid),       //   input,    width = 1,                         .awvalid
		.f2sdram_bid                            (f2sdram_adapter_axi4_man_bid),           //  output,    width = 5,                         .bid
		.f2sdram_bready                         (f2sdram_adapter_axi4_man_bready),        //   input,    width = 1,                         .bready
		.f2sdram_bresp                          (f2sdram_adapter_axi4_man_bresp),         //  output,    width = 2,                         .bresp
		.f2sdram_bvalid                         (f2sdram_adapter_axi4_man_bvalid),        //  output,    width = 1,                         .bvalid
		.f2sdram_rdata                          (f2sdram_adapter_axi4_man_rdata),         //  output,  width = 256,                         .rdata
		.f2sdram_rid                            (f2sdram_adapter_axi4_man_rid),           //  output,    width = 5,                         .rid
		.f2sdram_rlast                          (f2sdram_adapter_axi4_man_rlast),         //  output,    width = 1,                         .rlast
		.f2sdram_rready                         (f2sdram_adapter_axi4_man_rready),        //   input,    width = 1,                         .rready
		.f2sdram_rresp                          (f2sdram_adapter_axi4_man_rresp),         //  output,    width = 2,                         .rresp
		.f2sdram_rvalid                         (f2sdram_adapter_axi4_man_rvalid),        //  output,    width = 1,                         .rvalid
		.f2sdram_wdata                          (f2sdram_adapter_axi4_man_wdata),         //   input,  width = 256,                         .wdata
		.f2sdram_wlast                          (f2sdram_adapter_axi4_man_wlast),         //   input,    width = 1,                         .wlast
		.f2sdram_wready                         (f2sdram_adapter_axi4_man_wready),        //  output,    width = 1,                         .wready
		.f2sdram_wstrb                          (f2sdram_adapter_axi4_man_wstrb),         //   input,   width = 32,                         .wstrb
		.f2sdram_wvalid                         (f2sdram_adapter_axi4_man_wvalid),        //   input,    width = 1,                         .wvalid
		.f2sdram_aruser                         (f2sdram_adapter_axi4_man_aruser),        //   input,    width = 8,                         .aruser
		.f2sdram_awuser                         (f2sdram_adapter_axi4_man_awuser),        //   input,    width = 8,                         .awuser
		.f2sdram_wuser                          (f2sdram_adapter_axi4_man_wuser),         //   input,    width = 8,                         .wuser
		.f2sdram_buser                          (f2sdram_adapter_axi4_man_buser),         //  output,    width = 8,                         .buser
		.f2sdram_arregion                       (f2sdram_adapter_axi4_man_arregion),      //   input,    width = 4,                         .arregion
		.f2sdram_ruser                          (f2sdram_adapter_axi4_man_ruser),         //  output,    width = 8,                         .ruser
		.f2sdram_awregion                       (f2sdram_adapter_axi4_man_awregion),      //   input,    width = 4,                         .awregion
		.io96b0_csr_axi_clk_clk                 (emif_hps_s0_axil_clk_clk),               //   input,    width = 1,       io96b0_csr_axi_clk.clk
		.io96b0_csr_axi_rst_reset_n             (emif_hps_s0_axil_rst_n_reset),           //   input,    width = 1,       io96b0_csr_axi_rst.reset_n
		.io96b0_csr_axi_arready                 (agilex_hps_io96b0_csr_axi_arready),      //   input,    width = 1,           io96b0_csr_axi.arready
		.io96b0_csr_axi_awready                 (agilex_hps_io96b0_csr_axi_awready),      //   input,    width = 1,                         .awready
		.io96b0_csr_axi_bresp                   (agilex_hps_io96b0_csr_axi_bresp),        //   input,    width = 2,                         .bresp
		.io96b0_csr_axi_bvalid                  (agilex_hps_io96b0_csr_axi_bvalid),       //   input,    width = 1,                         .bvalid
		.io96b0_csr_axi_rdata                   (agilex_hps_io96b0_csr_axi_rdata),        //   input,   width = 32,                         .rdata
		.io96b0_csr_axi_rresp                   (agilex_hps_io96b0_csr_axi_rresp),        //   input,    width = 2,                         .rresp
		.io96b0_csr_axi_rvalid                  (agilex_hps_io96b0_csr_axi_rvalid),       //   input,    width = 1,                         .rvalid
		.io96b0_csr_axi_wready                  (agilex_hps_io96b0_csr_axi_wready),       //   input,    width = 1,                         .wready
		.io96b0_csr_axi_araddr                  (agilex_hps_io96b0_csr_axi_araddr),       //  output,   width = 32,                         .araddr
		.io96b0_csr_axi_arvalid                 (agilex_hps_io96b0_csr_axi_arvalid),      //  output,    width = 1,                         .arvalid
		.io96b0_csr_axi_awaddr                  (agilex_hps_io96b0_csr_axi_awaddr),       //  output,   width = 32,                         .awaddr
		.io96b0_csr_axi_awvalid                 (agilex_hps_io96b0_csr_axi_awvalid),      //  output,    width = 1,                         .awvalid
		.io96b0_csr_axi_bready                  (agilex_hps_io96b0_csr_axi_bready),       //  output,    width = 1,                         .bready
		.io96b0_csr_axi_rready                  (agilex_hps_io96b0_csr_axi_rready),       //  output,    width = 1,                         .rready
		.io96b0_csr_axi_wdata                   (agilex_hps_io96b0_csr_axi_wdata),        //  output,   width = 32,                         .wdata
		.io96b0_csr_axi_wstrb                   (agilex_hps_io96b0_csr_axi_wstrb),        //  output,    width = 4,                         .wstrb
		.io96b0_csr_axi_wvalid                  (agilex_hps_io96b0_csr_axi_wvalid),       //  output,    width = 1,                         .wvalid
		.io96b0_csr_axi_arprot                  (agilex_hps_io96b0_csr_axi_arprot),       //  output,    width = 3,                         .arprot
		.io96b0_csr_axi_awprot                  (agilex_hps_io96b0_csr_axi_awprot),       //  output,    width = 3,                         .awprot
		.io96b0_ch0_axi_clk_clk                 (emif_hps_usr_clk_0_clk),                 //   input,    width = 1,       io96b0_ch0_axi_clk.clk
		.io96b0_ch0_axi_rst_reset_n             (~rst_controller_reset_out_reset),        //   input,    width = 1,       io96b0_ch0_axi_rst.reset_n
		.io96b0_ch0_axi_arready                 (agilex_hps_io96b0_ch0_axi_arready),      //   input,    width = 1,           io96b0_ch0_axi.arready
		.io96b0_ch0_axi_awready                 (agilex_hps_io96b0_ch0_axi_awready),      //   input,    width = 1,                         .awready
		.io96b0_ch0_axi_bid                     (agilex_hps_io96b0_ch0_axi_bid),          //   input,    width = 7,                         .bid
		.io96b0_ch0_axi_bresp                   (agilex_hps_io96b0_ch0_axi_bresp),        //   input,    width = 2,                         .bresp
		.io96b0_ch0_axi_bvalid                  (agilex_hps_io96b0_ch0_axi_bvalid),       //   input,    width = 1,                         .bvalid
		.io96b0_ch0_axi_rdata                   (agilex_hps_io96b0_ch0_axi_rdata),        //   input,  width = 256,                         .rdata
		.io96b0_ch0_axi_rid                     (agilex_hps_io96b0_ch0_axi_rid),          //   input,    width = 7,                         .rid
		.io96b0_ch0_axi_rlast                   (agilex_hps_io96b0_ch0_axi_rlast),        //   input,    width = 1,                         .rlast
		.io96b0_ch0_axi_rresp                   (agilex_hps_io96b0_ch0_axi_rresp),        //   input,    width = 2,                         .rresp
		.io96b0_ch0_axi_ruser                   (agilex_hps_io96b0_ch0_axi_ruser),        //   input,   width = 32,                         .ruser
		.io96b0_ch0_axi_rvalid                  (agilex_hps_io96b0_ch0_axi_rvalid),       //   input,    width = 1,                         .rvalid
		.io96b0_ch0_axi_wready                  (agilex_hps_io96b0_ch0_axi_wready),       //   input,    width = 1,                         .wready
		.io96b0_ch0_axi_araddr                  (agilex_hps_io96b0_ch0_axi_araddr),       //  output,   width = 44,                         .araddr
		.io96b0_ch0_axi_arburst                 (agilex_hps_io96b0_ch0_axi_arburst),      //  output,    width = 2,                         .arburst
		.io96b0_ch0_axi_arid                    (agilex_hps_io96b0_ch0_axi_arid),         //  output,    width = 7,                         .arid
		.io96b0_ch0_axi_arlen                   (agilex_hps_io96b0_ch0_axi_arlen),        //  output,    width = 8,                         .arlen
		.io96b0_ch0_axi_arlock                  (agilex_hps_io96b0_ch0_axi_arlock),       //  output,    width = 1,                         .arlock
		.io96b0_ch0_axi_arqos                   (agilex_hps_io96b0_ch0_axi_arqos),        //  output,    width = 4,                         .arqos
		.io96b0_ch0_axi_arsize                  (agilex_hps_io96b0_ch0_axi_arsize),       //  output,    width = 3,                         .arsize
		.io96b0_ch0_axi_aruser                  (agilex_hps_io96b0_ch0_axi_aruser),       //  output,   width = 14,                         .aruser
		.io96b0_ch0_axi_arvalid                 (agilex_hps_io96b0_ch0_axi_arvalid),      //  output,    width = 1,                         .arvalid
		.io96b0_ch0_axi_awaddr                  (agilex_hps_io96b0_ch0_axi_awaddr),       //  output,   width = 44,                         .awaddr
		.io96b0_ch0_axi_awburst                 (agilex_hps_io96b0_ch0_axi_awburst),      //  output,    width = 2,                         .awburst
		.io96b0_ch0_axi_awid                    (agilex_hps_io96b0_ch0_axi_awid),         //  output,    width = 7,                         .awid
		.io96b0_ch0_axi_awlen                   (agilex_hps_io96b0_ch0_axi_awlen),        //  output,    width = 8,                         .awlen
		.io96b0_ch0_axi_awlock                  (agilex_hps_io96b0_ch0_axi_awlock),       //  output,    width = 1,                         .awlock
		.io96b0_ch0_axi_awqos                   (agilex_hps_io96b0_ch0_axi_awqos),        //  output,    width = 4,                         .awqos
		.io96b0_ch0_axi_awsize                  (agilex_hps_io96b0_ch0_axi_awsize),       //  output,    width = 3,                         .awsize
		.io96b0_ch0_axi_awuser                  (agilex_hps_io96b0_ch0_axi_awuser),       //  output,   width = 14,                         .awuser
		.io96b0_ch0_axi_awvalid                 (agilex_hps_io96b0_ch0_axi_awvalid),      //  output,    width = 1,                         .awvalid
		.io96b0_ch0_axi_bready                  (agilex_hps_io96b0_ch0_axi_bready),       //  output,    width = 1,                         .bready
		.io96b0_ch0_axi_rready                  (agilex_hps_io96b0_ch0_axi_rready),       //  output,    width = 1,                         .rready
		.io96b0_ch0_axi_wdata                   (agilex_hps_io96b0_ch0_axi_wdata),        //  output,  width = 256,                         .wdata
		.io96b0_ch0_axi_wlast                   (agilex_hps_io96b0_ch0_axi_wlast),        //  output,    width = 1,                         .wlast
		.io96b0_ch0_axi_wstrb                   (agilex_hps_io96b0_ch0_axi_wstrb),        //  output,   width = 32,                         .wstrb
		.io96b0_ch0_axi_wuser                   (agilex_hps_io96b0_ch0_axi_wuser),        //  output,   width = 32,                         .wuser
		.io96b0_ch0_axi_wvalid                  (agilex_hps_io96b0_ch0_axi_wvalid),       //  output,    width = 1,                         .wvalid
		.io96b0_ch0_axi_arprot                  (agilex_hps_io96b0_ch0_axi_arprot),       //  output,    width = 3,                         .arprot
		.io96b0_ch0_axi_awprot                  (agilex_hps_io96b0_ch0_axi_awprot)        //  output,    width = 3,                         .awprot
	);

	emif_hps emif_hps (
		.noc_aclk_0              (emif_hps_usr_clk_0_clk),                     //  output,    width = 1,      usr_clk_0.clk
		.s0_axi4_araddr          (mm_interconnect_1_emif_hps_s0_axi4_araddr),  //   input,   width = 40,        s0_axi4.araddr
		.s0_axi4_arburst         (mm_interconnect_1_emif_hps_s0_axi4_arburst), //   input,    width = 2,               .arburst
		.s0_axi4_arid            (mm_interconnect_1_emif_hps_s0_axi4_arid),    //   input,    width = 7,               .arid
		.s0_axi4_arlen           (mm_interconnect_1_emif_hps_s0_axi4_arlen),   //   input,    width = 8,               .arlen
		.s0_axi4_arlock          (mm_interconnect_1_emif_hps_s0_axi4_arlock),  //   input,    width = 1,               .arlock
		.s0_axi4_arqos           (mm_interconnect_1_emif_hps_s0_axi4_arqos),   //   input,    width = 4,               .arqos
		.s0_axi4_arsize          (mm_interconnect_1_emif_hps_s0_axi4_arsize),  //   input,    width = 3,               .arsize
		.s0_axi4_arvalid         (mm_interconnect_1_emif_hps_s0_axi4_arvalid), //   input,    width = 1,               .arvalid
		.s0_axi4_aruser          (mm_interconnect_1_emif_hps_s0_axi4_aruser),  //   input,   width = 14,               .aruser
		.s0_axi4_arprot          (mm_interconnect_1_emif_hps_s0_axi4_arprot),  //   input,    width = 3,               .arprot
		.s0_axi4_awaddr          (mm_interconnect_1_emif_hps_s0_axi4_awaddr),  //   input,   width = 40,               .awaddr
		.s0_axi4_awburst         (mm_interconnect_1_emif_hps_s0_axi4_awburst), //   input,    width = 2,               .awburst
		.s0_axi4_awid            (mm_interconnect_1_emif_hps_s0_axi4_awid),    //   input,    width = 7,               .awid
		.s0_axi4_awlen           (mm_interconnect_1_emif_hps_s0_axi4_awlen),   //   input,    width = 8,               .awlen
		.s0_axi4_awlock          (mm_interconnect_1_emif_hps_s0_axi4_awlock),  //   input,    width = 1,               .awlock
		.s0_axi4_awqos           (mm_interconnect_1_emif_hps_s0_axi4_awqos),   //   input,    width = 4,               .awqos
		.s0_axi4_awsize          (mm_interconnect_1_emif_hps_s0_axi4_awsize),  //   input,    width = 3,               .awsize
		.s0_axi4_awvalid         (mm_interconnect_1_emif_hps_s0_axi4_awvalid), //   input,    width = 1,               .awvalid
		.s0_axi4_awuser          (mm_interconnect_1_emif_hps_s0_axi4_awuser),  //   input,   width = 14,               .awuser
		.s0_axi4_awprot          (mm_interconnect_1_emif_hps_s0_axi4_awprot),  //   input,    width = 3,               .awprot
		.s0_axi4_bready          (mm_interconnect_1_emif_hps_s0_axi4_bready),  //   input,    width = 1,               .bready
		.s0_axi4_rready          (mm_interconnect_1_emif_hps_s0_axi4_rready),  //   input,    width = 1,               .rready
		.s0_axi4_wdata           (mm_interconnect_1_emif_hps_s0_axi4_wdata),   //   input,  width = 256,               .wdata
		.s0_axi4_wstrb           (mm_interconnect_1_emif_hps_s0_axi4_wstrb),   //   input,   width = 32,               .wstrb
		.s0_axi4_wlast           (mm_interconnect_1_emif_hps_s0_axi4_wlast),   //   input,    width = 1,               .wlast
		.s0_axi4_wvalid          (mm_interconnect_1_emif_hps_s0_axi4_wvalid),  //   input,    width = 1,               .wvalid
		.s0_axi4_wuser           (mm_interconnect_1_emif_hps_s0_axi4_wuser),   //   input,   width = 32,               .wuser
		.s0_axi4_ruser           (mm_interconnect_1_emif_hps_s0_axi4_ruser),   //  output,   width = 32,               .ruser
		.s0_axi4_arready         (mm_interconnect_1_emif_hps_s0_axi4_arready), //  output,    width = 1,               .arready
		.s0_axi4_awready         (mm_interconnect_1_emif_hps_s0_axi4_awready), //  output,    width = 1,               .awready
		.s0_axi4_bid             (mm_interconnect_1_emif_hps_s0_axi4_bid),     //  output,    width = 7,               .bid
		.s0_axi4_bresp           (mm_interconnect_1_emif_hps_s0_axi4_bresp),   //  output,    width = 2,               .bresp
		.s0_axi4_bvalid          (mm_interconnect_1_emif_hps_s0_axi4_bvalid),  //  output,    width = 1,               .bvalid
		.s0_axi4_rdata           (mm_interconnect_1_emif_hps_s0_axi4_rdata),   //  output,  width = 256,               .rdata
		.s0_axi4_rid             (mm_interconnect_1_emif_hps_s0_axi4_rid),     //  output,    width = 7,               .rid
		.s0_axi4_rlast           (mm_interconnect_1_emif_hps_s0_axi4_rlast),   //  output,    width = 1,               .rlast
		.s0_axi4_rresp           (mm_interconnect_1_emif_hps_s0_axi4_rresp),   //  output,    width = 2,               .rresp
		.s0_axi4_rvalid          (mm_interconnect_1_emif_hps_s0_axi4_rvalid),  //  output,    width = 1,               .rvalid
		.s0_axi4_wready          (mm_interconnect_1_emif_hps_s0_axi4_wready),  //  output,    width = 1,               .wready
		.emif_mem_0_mem_ck_t     (emif_hps_emif_mem_0_mem_ck_t),               //  output,    width = 1,     emif_mem_0.mem_ck_t
		.emif_mem_0_mem_ck_c     (emif_hps_emif_mem_0_mem_ck_c),               //  output,    width = 1,               .mem_ck_c
		.emif_mem_0_mem_cke      (emif_hps_emif_mem_0_mem_cke),                //  output,    width = 1,               .mem_cke
		.emif_mem_0_mem_odt      (emif_hps_emif_mem_0_mem_odt),                //  output,    width = 1,               .mem_odt
		.emif_mem_0_mem_cs_n     (emif_hps_emif_mem_0_mem_cs_n),               //  output,    width = 1,               .mem_cs_n
		.emif_mem_0_mem_a        (emif_hps_emif_mem_0_mem_a),                  //  output,   width = 17,               .mem_a
		.emif_mem_0_mem_ba       (emif_hps_emif_mem_0_mem_ba),                 //  output,    width = 2,               .mem_ba
		.emif_mem_0_mem_bg       (emif_hps_emif_mem_0_mem_bg),                 //  output,    width = 1,               .mem_bg
		.emif_mem_0_mem_act_n    (emif_hps_emif_mem_0_mem_act_n),              //  output,    width = 1,               .mem_act_n
		.emif_mem_0_mem_par      (emif_hps_emif_mem_0_mem_par),                //  output,    width = 1,               .mem_par
		.emif_mem_0_mem_alert_n  (emif_hps_emif_mem_0_mem_alert_n),            //   input,    width = 1,               .mem_alert_n
		.emif_mem_0_mem_reset_n  (emif_hps_emif_mem_0_mem_reset_n),            //  output,    width = 1,               .mem_reset_n
		.emif_mem_0_mem_dq       (emif_hps_emif_mem_0_mem_dq),                 //   inout,   width = 32,               .mem_dq
		.emif_mem_0_mem_dqs_t    (emif_hps_emif_mem_0_mem_dqs_t),              //   inout,    width = 4,               .mem_dqs_t
		.emif_mem_0_mem_dqs_c    (emif_hps_emif_mem_0_mem_dqs_c),              //   inout,    width = 4,               .mem_dqs_c
		.emif_mem_0_mem_dbi_n    (emif_hps_emif_mem_0_mem_dbi_n),              //   inout,    width = 4,               .mem_dbi_n
		.emif_oct_0_oct_rzqin    (emif_hps_emif_oct_0_oct_rzqin),              //   input,    width = 1,     emif_oct_0.oct_rzqin
		.s0_noc_axi4lite_clk     (emif_hps_s0_axil_clk_clk),                   //  output,    width = 1,    s0_axil_clk.clk
		.s0_noc_axi4lite_rst_n   (emif_hps_s0_axil_rst_n_reset),               //  output,    width = 1,  s0_axil_rst_n.reset_n
		.s0_noc_axi4lite_awaddr  (mm_interconnect_2_emif_hps_s0_axil_awaddr),  //   input,   width = 27,        s0_axil.awaddr
		.s0_noc_axi4lite_awvalid (mm_interconnect_2_emif_hps_s0_axil_awvalid), //   input,    width = 1,               .awvalid
		.s0_noc_axi4lite_awready (mm_interconnect_2_emif_hps_s0_axil_awready), //  output,    width = 1,               .awready
		.s0_noc_axi4lite_wdata   (mm_interconnect_2_emif_hps_s0_axil_wdata),   //   input,   width = 32,               .wdata
		.s0_noc_axi4lite_wstrb   (mm_interconnect_2_emif_hps_s0_axil_wstrb),   //   input,    width = 4,               .wstrb
		.s0_noc_axi4lite_wvalid  (mm_interconnect_2_emif_hps_s0_axil_wvalid),  //   input,    width = 1,               .wvalid
		.s0_noc_axi4lite_wready  (mm_interconnect_2_emif_hps_s0_axil_wready),  //  output,    width = 1,               .wready
		.s0_noc_axi4lite_bresp   (mm_interconnect_2_emif_hps_s0_axil_bresp),   //  output,    width = 2,               .bresp
		.s0_noc_axi4lite_bvalid  (mm_interconnect_2_emif_hps_s0_axil_bvalid),  //  output,    width = 1,               .bvalid
		.s0_noc_axi4lite_bready  (mm_interconnect_2_emif_hps_s0_axil_bready),  //   input,    width = 1,               .bready
		.s0_noc_axi4lite_araddr  (mm_interconnect_2_emif_hps_s0_axil_araddr),  //   input,   width = 27,               .araddr
		.s0_noc_axi4lite_arvalid (mm_interconnect_2_emif_hps_s0_axil_arvalid), //   input,    width = 1,               .arvalid
		.s0_noc_axi4lite_arready (mm_interconnect_2_emif_hps_s0_axil_arready), //  output,    width = 1,               .arready
		.s0_noc_axi4lite_rdata   (mm_interconnect_2_emif_hps_s0_axil_rdata),   //  output,   width = 32,               .rdata
		.s0_noc_axi4lite_rresp   (mm_interconnect_2_emif_hps_s0_axil_rresp),   //  output,    width = 2,               .rresp
		.s0_noc_axi4lite_rvalid  (mm_interconnect_2_emif_hps_s0_axil_rvalid),  //  output,    width = 1,               .rvalid
		.s0_noc_axi4lite_rready  (mm_interconnect_2_emif_hps_s0_axil_rready),  //   input,    width = 1,               .rready
		.s0_noc_axi4lite_awprot  (mm_interconnect_2_emif_hps_s0_axil_awprot),  //   input,    width = 3,               .awprot
		.s0_noc_axi4lite_arprot  (mm_interconnect_2_emif_hps_s0_axil_arprot),  //   input,    width = 3,               .arprot
		.out_reset_0_n           (emif_hps_usr_rst_n_0_reset),                 //  output,    width = 1,    usr_rst_n_0.reset_n
		.emif_ref_clk_0_clk      (emif_hps_emif_ref_clk_0_clk)                 //   input,    width = 1, emif_ref_clk_0.clk
	);

	f2sdram_adapter f2sdram_adapter (
		.clk          (f2sdram_adapter_clk_clk),           //   input,    width = 1,    clock.clk
		.reset        (f2sdram_adapter_rst_reset),         //   input,    width = 1,    reset.reset
		.man_araddr   (f2sdram_adapter_axi4_man_araddr),   //  output,   width = 32, axi4_man.araddr
		.man_arburst  (f2sdram_adapter_axi4_man_arburst),  //  output,    width = 2,         .arburst
		.man_arcache  (f2sdram_adapter_axi4_man_arcache),  //  output,    width = 4,         .arcache
		.man_arid     (f2sdram_adapter_axi4_man_arid),     //  output,    width = 5,         .arid
		.man_arlen    (f2sdram_adapter_axi4_man_arlen),    //  output,    width = 8,         .arlen
		.man_arlock   (f2sdram_adapter_axi4_man_arlock),   //  output,    width = 1,         .arlock
		.man_arprot   (f2sdram_adapter_axi4_man_arprot),   //  output,    width = 3,         .arprot
		.man_arqos    (f2sdram_adapter_axi4_man_arqos),    //  output,    width = 4,         .arqos
		.man_arready  (f2sdram_adapter_axi4_man_arready),  //   input,    width = 1,         .arready
		.man_arsize   (f2sdram_adapter_axi4_man_arsize),   //  output,    width = 3,         .arsize
		.man_arvalid  (f2sdram_adapter_axi4_man_arvalid),  //  output,    width = 1,         .arvalid
		.man_awaddr   (f2sdram_adapter_axi4_man_awaddr),   //  output,   width = 32,         .awaddr
		.man_awburst  (f2sdram_adapter_axi4_man_awburst),  //  output,    width = 2,         .awburst
		.man_awcache  (f2sdram_adapter_axi4_man_awcache),  //  output,    width = 4,         .awcache
		.man_awid     (f2sdram_adapter_axi4_man_awid),     //  output,    width = 5,         .awid
		.man_awlen    (f2sdram_adapter_axi4_man_awlen),    //  output,    width = 8,         .awlen
		.man_awlock   (f2sdram_adapter_axi4_man_awlock),   //  output,    width = 1,         .awlock
		.man_awprot   (f2sdram_adapter_axi4_man_awprot),   //  output,    width = 3,         .awprot
		.man_awqos    (f2sdram_adapter_axi4_man_awqos),    //  output,    width = 4,         .awqos
		.man_awready  (f2sdram_adapter_axi4_man_awready),  //   input,    width = 1,         .awready
		.man_awsize   (f2sdram_adapter_axi4_man_awsize),   //  output,    width = 3,         .awsize
		.man_awvalid  (f2sdram_adapter_axi4_man_awvalid),  //  output,    width = 1,         .awvalid
		.man_bid      (f2sdram_adapter_axi4_man_bid),      //   input,    width = 5,         .bid
		.man_bready   (f2sdram_adapter_axi4_man_bready),   //  output,    width = 1,         .bready
		.man_bresp    (f2sdram_adapter_axi4_man_bresp),    //   input,    width = 2,         .bresp
		.man_bvalid   (f2sdram_adapter_axi4_man_bvalid),   //   input,    width = 1,         .bvalid
		.man_rdata    (f2sdram_adapter_axi4_man_rdata),    //   input,  width = 256,         .rdata
		.man_rid      (f2sdram_adapter_axi4_man_rid),      //   input,    width = 5,         .rid
		.man_rlast    (f2sdram_adapter_axi4_man_rlast),    //   input,    width = 1,         .rlast
		.man_rready   (f2sdram_adapter_axi4_man_rready),   //  output,    width = 1,         .rready
		.man_rresp    (f2sdram_adapter_axi4_man_rresp),    //   input,    width = 2,         .rresp
		.man_rvalid   (f2sdram_adapter_axi4_man_rvalid),   //   input,    width = 1,         .rvalid
		.man_wdata    (f2sdram_adapter_axi4_man_wdata),    //  output,  width = 256,         .wdata
		.man_wlast    (f2sdram_adapter_axi4_man_wlast),    //  output,    width = 1,         .wlast
		.man_wready   (f2sdram_adapter_axi4_man_wready),   //   input,    width = 1,         .wready
		.man_wstrb    (f2sdram_adapter_axi4_man_wstrb),    //  output,   width = 32,         .wstrb
		.man_wvalid   (f2sdram_adapter_axi4_man_wvalid),   //  output,    width = 1,         .wvalid
		.man_aruser   (f2sdram_adapter_axi4_man_aruser),   //  output,    width = 8,         .aruser
		.man_awuser   (f2sdram_adapter_axi4_man_awuser),   //  output,    width = 8,         .awuser
		.man_wuser    (f2sdram_adapter_axi4_man_wuser),    //  output,    width = 8,         .wuser
		.man_buser    (f2sdram_adapter_axi4_man_buser),    //   input,    width = 8,         .buser
		.man_arregion (f2sdram_adapter_axi4_man_arregion), //  output,    width = 4,         .arregion
		.man_ruser    (f2sdram_adapter_axi4_man_ruser),    //   input,    width = 8,         .ruser
		.man_awregion (f2sdram_adapter_axi4_man_awregion), //  output,    width = 4,         .awregion
		.sub_araddr   (f2sdram_adapter_axi4_sub_araddr),   //   input,   width = 32, axi4_sub.araddr
		.sub_arburst  (f2sdram_adapter_axi4_sub_arburst),  //   input,    width = 2,         .arburst
		.sub_arcache  (f2sdram_adapter_axi4_sub_arcache),  //   input,    width = 4,         .arcache
		.sub_arid     (f2sdram_adapter_axi4_sub_arid),     //   input,    width = 5,         .arid
		.sub_arlen    (f2sdram_adapter_axi4_sub_arlen),    //   input,    width = 8,         .arlen
		.sub_arlock   (f2sdram_adapter_axi4_sub_arlock),   //   input,    width = 1,         .arlock
		.sub_arprot   (f2sdram_adapter_axi4_sub_arprot),   //   input,    width = 3,         .arprot
		.sub_arqos    (f2sdram_adapter_axi4_sub_arqos),    //   input,    width = 4,         .arqos
		.sub_arready  (f2sdram_adapter_axi4_sub_arready),  //  output,    width = 1,         .arready
		.sub_arsize   (f2sdram_adapter_axi4_sub_arsize),   //   input,    width = 3,         .arsize
		.sub_arvalid  (f2sdram_adapter_axi4_sub_arvalid),  //   input,    width = 1,         .arvalid
		.sub_awaddr   (f2sdram_adapter_axi4_sub_awaddr),   //   input,   width = 32,         .awaddr
		.sub_awburst  (f2sdram_adapter_axi4_sub_awburst),  //   input,    width = 2,         .awburst
		.sub_awcache  (f2sdram_adapter_axi4_sub_awcache),  //   input,    width = 4,         .awcache
		.sub_awid     (f2sdram_adapter_axi4_sub_awid),     //   input,    width = 5,         .awid
		.sub_awlen    (f2sdram_adapter_axi4_sub_awlen),    //   input,    width = 8,         .awlen
		.sub_awlock   (f2sdram_adapter_axi4_sub_awlock),   //   input,    width = 1,         .awlock
		.sub_awprot   (f2sdram_adapter_axi4_sub_awprot),   //   input,    width = 3,         .awprot
		.sub_awqos    (f2sdram_adapter_axi4_sub_awqos),    //   input,    width = 4,         .awqos
		.sub_awready  (f2sdram_adapter_axi4_sub_awready),  //  output,    width = 1,         .awready
		.sub_awsize   (f2sdram_adapter_axi4_sub_awsize),   //   input,    width = 3,         .awsize
		.sub_awvalid  (f2sdram_adapter_axi4_sub_awvalid),  //   input,    width = 1,         .awvalid
		.sub_bid      (f2sdram_adapter_axi4_sub_bid),      //  output,    width = 5,         .bid
		.sub_bready   (f2sdram_adapter_axi4_sub_bready),   //   input,    width = 1,         .bready
		.sub_bresp    (f2sdram_adapter_axi4_sub_bresp),    //  output,    width = 2,         .bresp
		.sub_bvalid   (f2sdram_adapter_axi4_sub_bvalid),   //  output,    width = 1,         .bvalid
		.sub_rdata    (f2sdram_adapter_axi4_sub_rdata),    //  output,  width = 256,         .rdata
		.sub_rid      (f2sdram_adapter_axi4_sub_rid),      //  output,    width = 5,         .rid
		.sub_rlast    (f2sdram_adapter_axi4_sub_rlast),    //  output,    width = 1,         .rlast
		.sub_rready   (f2sdram_adapter_axi4_sub_rready),   //   input,    width = 1,         .rready
		.sub_rresp    (f2sdram_adapter_axi4_sub_rresp),    //  output,    width = 2,         .rresp
		.sub_rvalid   (f2sdram_adapter_axi4_sub_rvalid),   //  output,    width = 1,         .rvalid
		.sub_wdata    (f2sdram_adapter_axi4_sub_wdata),    //   input,  width = 256,         .wdata
		.sub_wlast    (f2sdram_adapter_axi4_sub_wlast),    //   input,    width = 1,         .wlast
		.sub_wready   (f2sdram_adapter_axi4_sub_wready),   //  output,    width = 1,         .wready
		.sub_wstrb    (f2sdram_adapter_axi4_sub_wstrb),    //   input,   width = 32,         .wstrb
		.sub_wvalid   (f2sdram_adapter_axi4_sub_wvalid),   //   input,    width = 1,         .wvalid
		.sub_aruser   (f2sdram_adapter_axi4_sub_aruser),   //   input,    width = 8,         .aruser
		.sub_awuser   (f2sdram_adapter_axi4_sub_awuser),   //   input,    width = 8,         .awuser
		.sub_wuser    (f2sdram_adapter_axi4_sub_wuser),    //   input,    width = 8,         .wuser
		.sub_buser    (f2sdram_adapter_axi4_sub_buser),    //  output,    width = 8,         .buser
		.sub_arregion (f2sdram_adapter_axi4_sub_arregion), //   input,    width = 4,         .arregion
		.sub_ruser    (f2sdram_adapter_axi4_sub_ruser),    //  output,    width = 8,         .ruser
		.sub_awregion (f2sdram_adapter_axi4_sub_awregion)  //   input,    width = 4,         .awregion
	);

	gts_inst gts_inst (
		.o_pma_cu_clk (o_pma_cu_clk_clk)  //  output,  width = 1, o_pma_cu_clk.clk
	);

	hps_subsys_altera_mm_interconnect_1920_wopmpeq mm_interconnect_1 (
		.agilex_hps_io96b0_ch0_axi_awid                                             (agilex_hps_io96b0_ch0_axi_awid),             //   input,    width = 7,                                            agilex_hps_io96b0_ch0_axi.awid
		.agilex_hps_io96b0_ch0_axi_awaddr                                           (agilex_hps_io96b0_ch0_axi_awaddr),           //   input,   width = 44,                                                                     .awaddr
		.agilex_hps_io96b0_ch0_axi_awlen                                            (agilex_hps_io96b0_ch0_axi_awlen),            //   input,    width = 8,                                                                     .awlen
		.agilex_hps_io96b0_ch0_axi_awsize                                           (agilex_hps_io96b0_ch0_axi_awsize),           //   input,    width = 3,                                                                     .awsize
		.agilex_hps_io96b0_ch0_axi_awburst                                          (agilex_hps_io96b0_ch0_axi_awburst),          //   input,    width = 2,                                                                     .awburst
		.agilex_hps_io96b0_ch0_axi_awlock                                           (agilex_hps_io96b0_ch0_axi_awlock),           //   input,    width = 1,                                                                     .awlock
		.agilex_hps_io96b0_ch0_axi_awprot                                           (agilex_hps_io96b0_ch0_axi_awprot),           //   input,    width = 3,                                                                     .awprot
		.agilex_hps_io96b0_ch0_axi_awuser                                           (agilex_hps_io96b0_ch0_axi_awuser),           //   input,   width = 14,                                                                     .awuser
		.agilex_hps_io96b0_ch0_axi_awqos                                            (agilex_hps_io96b0_ch0_axi_awqos),            //   input,    width = 4,                                                                     .awqos
		.agilex_hps_io96b0_ch0_axi_awvalid                                          (agilex_hps_io96b0_ch0_axi_awvalid),          //   input,    width = 1,                                                                     .awvalid
		.agilex_hps_io96b0_ch0_axi_awready                                          (agilex_hps_io96b0_ch0_axi_awready),          //  output,    width = 1,                                                                     .awready
		.agilex_hps_io96b0_ch0_axi_wdata                                            (agilex_hps_io96b0_ch0_axi_wdata),            //   input,  width = 256,                                                                     .wdata
		.agilex_hps_io96b0_ch0_axi_wstrb                                            (agilex_hps_io96b0_ch0_axi_wstrb),            //   input,   width = 32,                                                                     .wstrb
		.agilex_hps_io96b0_ch0_axi_wlast                                            (agilex_hps_io96b0_ch0_axi_wlast),            //   input,    width = 1,                                                                     .wlast
		.agilex_hps_io96b0_ch0_axi_wvalid                                           (agilex_hps_io96b0_ch0_axi_wvalid),           //   input,    width = 1,                                                                     .wvalid
		.agilex_hps_io96b0_ch0_axi_wuser                                            (agilex_hps_io96b0_ch0_axi_wuser),            //   input,   width = 32,                                                                     .wuser
		.agilex_hps_io96b0_ch0_axi_wready                                           (agilex_hps_io96b0_ch0_axi_wready),           //  output,    width = 1,                                                                     .wready
		.agilex_hps_io96b0_ch0_axi_bid                                              (agilex_hps_io96b0_ch0_axi_bid),              //  output,    width = 7,                                                                     .bid
		.agilex_hps_io96b0_ch0_axi_bresp                                            (agilex_hps_io96b0_ch0_axi_bresp),            //  output,    width = 2,                                                                     .bresp
		.agilex_hps_io96b0_ch0_axi_bvalid                                           (agilex_hps_io96b0_ch0_axi_bvalid),           //  output,    width = 1,                                                                     .bvalid
		.agilex_hps_io96b0_ch0_axi_bready                                           (agilex_hps_io96b0_ch0_axi_bready),           //   input,    width = 1,                                                                     .bready
		.agilex_hps_io96b0_ch0_axi_arid                                             (agilex_hps_io96b0_ch0_axi_arid),             //   input,    width = 7,                                                                     .arid
		.agilex_hps_io96b0_ch0_axi_araddr                                           (agilex_hps_io96b0_ch0_axi_araddr),           //   input,   width = 44,                                                                     .araddr
		.agilex_hps_io96b0_ch0_axi_arlen                                            (agilex_hps_io96b0_ch0_axi_arlen),            //   input,    width = 8,                                                                     .arlen
		.agilex_hps_io96b0_ch0_axi_arsize                                           (agilex_hps_io96b0_ch0_axi_arsize),           //   input,    width = 3,                                                                     .arsize
		.agilex_hps_io96b0_ch0_axi_arburst                                          (agilex_hps_io96b0_ch0_axi_arburst),          //   input,    width = 2,                                                                     .arburst
		.agilex_hps_io96b0_ch0_axi_arlock                                           (agilex_hps_io96b0_ch0_axi_arlock),           //   input,    width = 1,                                                                     .arlock
		.agilex_hps_io96b0_ch0_axi_arprot                                           (agilex_hps_io96b0_ch0_axi_arprot),           //   input,    width = 3,                                                                     .arprot
		.agilex_hps_io96b0_ch0_axi_aruser                                           (agilex_hps_io96b0_ch0_axi_aruser),           //   input,   width = 14,                                                                     .aruser
		.agilex_hps_io96b0_ch0_axi_arqos                                            (agilex_hps_io96b0_ch0_axi_arqos),            //   input,    width = 4,                                                                     .arqos
		.agilex_hps_io96b0_ch0_axi_arvalid                                          (agilex_hps_io96b0_ch0_axi_arvalid),          //   input,    width = 1,                                                                     .arvalid
		.agilex_hps_io96b0_ch0_axi_arready                                          (agilex_hps_io96b0_ch0_axi_arready),          //  output,    width = 1,                                                                     .arready
		.agilex_hps_io96b0_ch0_axi_rid                                              (agilex_hps_io96b0_ch0_axi_rid),              //  output,    width = 7,                                                                     .rid
		.agilex_hps_io96b0_ch0_axi_rdata                                            (agilex_hps_io96b0_ch0_axi_rdata),            //  output,  width = 256,                                                                     .rdata
		.agilex_hps_io96b0_ch0_axi_rresp                                            (agilex_hps_io96b0_ch0_axi_rresp),            //  output,    width = 2,                                                                     .rresp
		.agilex_hps_io96b0_ch0_axi_rlast                                            (agilex_hps_io96b0_ch0_axi_rlast),            //  output,    width = 1,                                                                     .rlast
		.agilex_hps_io96b0_ch0_axi_rvalid                                           (agilex_hps_io96b0_ch0_axi_rvalid),           //  output,    width = 1,                                                                     .rvalid
		.agilex_hps_io96b0_ch0_axi_rready                                           (agilex_hps_io96b0_ch0_axi_rready),           //   input,    width = 1,                                                                     .rready
		.agilex_hps_io96b0_ch0_axi_ruser                                            (agilex_hps_io96b0_ch0_axi_ruser),            //  output,   width = 32,                                                                     .ruser
		.emif_hps_s0_axi4_awid                                                      (mm_interconnect_1_emif_hps_s0_axi4_awid),    //  output,    width = 7,                                                     emif_hps_s0_axi4.awid
		.emif_hps_s0_axi4_awaddr                                                    (mm_interconnect_1_emif_hps_s0_axi4_awaddr),  //  output,   width = 40,                                                                     .awaddr
		.emif_hps_s0_axi4_awlen                                                     (mm_interconnect_1_emif_hps_s0_axi4_awlen),   //  output,    width = 8,                                                                     .awlen
		.emif_hps_s0_axi4_awsize                                                    (mm_interconnect_1_emif_hps_s0_axi4_awsize),  //  output,    width = 3,                                                                     .awsize
		.emif_hps_s0_axi4_awburst                                                   (mm_interconnect_1_emif_hps_s0_axi4_awburst), //  output,    width = 2,                                                                     .awburst
		.emif_hps_s0_axi4_awlock                                                    (mm_interconnect_1_emif_hps_s0_axi4_awlock),  //  output,    width = 1,                                                                     .awlock
		.emif_hps_s0_axi4_awprot                                                    (mm_interconnect_1_emif_hps_s0_axi4_awprot),  //  output,    width = 3,                                                                     .awprot
		.emif_hps_s0_axi4_awuser                                                    (mm_interconnect_1_emif_hps_s0_axi4_awuser),  //  output,   width = 14,                                                                     .awuser
		.emif_hps_s0_axi4_awqos                                                     (mm_interconnect_1_emif_hps_s0_axi4_awqos),   //  output,    width = 4,                                                                     .awqos
		.emif_hps_s0_axi4_awvalid                                                   (mm_interconnect_1_emif_hps_s0_axi4_awvalid), //  output,    width = 1,                                                                     .awvalid
		.emif_hps_s0_axi4_awready                                                   (mm_interconnect_1_emif_hps_s0_axi4_awready), //   input,    width = 1,                                                                     .awready
		.emif_hps_s0_axi4_wdata                                                     (mm_interconnect_1_emif_hps_s0_axi4_wdata),   //  output,  width = 256,                                                                     .wdata
		.emif_hps_s0_axi4_wstrb                                                     (mm_interconnect_1_emif_hps_s0_axi4_wstrb),   //  output,   width = 32,                                                                     .wstrb
		.emif_hps_s0_axi4_wlast                                                     (mm_interconnect_1_emif_hps_s0_axi4_wlast),   //  output,    width = 1,                                                                     .wlast
		.emif_hps_s0_axi4_wvalid                                                    (mm_interconnect_1_emif_hps_s0_axi4_wvalid),  //  output,    width = 1,                                                                     .wvalid
		.emif_hps_s0_axi4_wuser                                                     (mm_interconnect_1_emif_hps_s0_axi4_wuser),   //  output,   width = 32,                                                                     .wuser
		.emif_hps_s0_axi4_wready                                                    (mm_interconnect_1_emif_hps_s0_axi4_wready),  //   input,    width = 1,                                                                     .wready
		.emif_hps_s0_axi4_bid                                                       (mm_interconnect_1_emif_hps_s0_axi4_bid),     //   input,    width = 7,                                                                     .bid
		.emif_hps_s0_axi4_bresp                                                     (mm_interconnect_1_emif_hps_s0_axi4_bresp),   //   input,    width = 2,                                                                     .bresp
		.emif_hps_s0_axi4_bvalid                                                    (mm_interconnect_1_emif_hps_s0_axi4_bvalid),  //   input,    width = 1,                                                                     .bvalid
		.emif_hps_s0_axi4_bready                                                    (mm_interconnect_1_emif_hps_s0_axi4_bready),  //  output,    width = 1,                                                                     .bready
		.emif_hps_s0_axi4_arid                                                      (mm_interconnect_1_emif_hps_s0_axi4_arid),    //  output,    width = 7,                                                                     .arid
		.emif_hps_s0_axi4_araddr                                                    (mm_interconnect_1_emif_hps_s0_axi4_araddr),  //  output,   width = 40,                                                                     .araddr
		.emif_hps_s0_axi4_arlen                                                     (mm_interconnect_1_emif_hps_s0_axi4_arlen),   //  output,    width = 8,                                                                     .arlen
		.emif_hps_s0_axi4_arsize                                                    (mm_interconnect_1_emif_hps_s0_axi4_arsize),  //  output,    width = 3,                                                                     .arsize
		.emif_hps_s0_axi4_arburst                                                   (mm_interconnect_1_emif_hps_s0_axi4_arburst), //  output,    width = 2,                                                                     .arburst
		.emif_hps_s0_axi4_arlock                                                    (mm_interconnect_1_emif_hps_s0_axi4_arlock),  //  output,    width = 1,                                                                     .arlock
		.emif_hps_s0_axi4_arprot                                                    (mm_interconnect_1_emif_hps_s0_axi4_arprot),  //  output,    width = 3,                                                                     .arprot
		.emif_hps_s0_axi4_aruser                                                    (mm_interconnect_1_emif_hps_s0_axi4_aruser),  //  output,   width = 14,                                                                     .aruser
		.emif_hps_s0_axi4_arqos                                                     (mm_interconnect_1_emif_hps_s0_axi4_arqos),   //  output,    width = 4,                                                                     .arqos
		.emif_hps_s0_axi4_arvalid                                                   (mm_interconnect_1_emif_hps_s0_axi4_arvalid), //  output,    width = 1,                                                                     .arvalid
		.emif_hps_s0_axi4_arready                                                   (mm_interconnect_1_emif_hps_s0_axi4_arready), //   input,    width = 1,                                                                     .arready
		.emif_hps_s0_axi4_rid                                                       (mm_interconnect_1_emif_hps_s0_axi4_rid),     //   input,    width = 7,                                                                     .rid
		.emif_hps_s0_axi4_rdata                                                     (mm_interconnect_1_emif_hps_s0_axi4_rdata),   //   input,  width = 256,                                                                     .rdata
		.emif_hps_s0_axi4_rresp                                                     (mm_interconnect_1_emif_hps_s0_axi4_rresp),   //   input,    width = 2,                                                                     .rresp
		.emif_hps_s0_axi4_rlast                                                     (mm_interconnect_1_emif_hps_s0_axi4_rlast),   //   input,    width = 1,                                                                     .rlast
		.emif_hps_s0_axi4_rvalid                                                    (mm_interconnect_1_emif_hps_s0_axi4_rvalid),  //   input,    width = 1,                                                                     .rvalid
		.emif_hps_s0_axi4_rready                                                    (mm_interconnect_1_emif_hps_s0_axi4_rready),  //  output,    width = 1,                                                                     .rready
		.emif_hps_s0_axi4_ruser                                                     (mm_interconnect_1_emif_hps_s0_axi4_ruser),   //   input,   width = 32,                                                                     .ruser
		.agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),         //   input,    width = 1, agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset.reset
		.emif_hps_usr_clk_0_clk                                                     (emif_hps_usr_clk_0_clk)                      //   input,    width = 1,                                                   emif_hps_usr_clk_0.clk
	);

	hps_subsys_altera_mm_interconnect_1920_zvx2jfy mm_interconnect_2 (
		.emif_hps_s0_axil_awaddr                                                (mm_interconnect_2_emif_hps_s0_axil_awaddr),  //  output,  width = 27,                                                 emif_hps_s0_axil.awaddr
		.emif_hps_s0_axil_awprot                                                (mm_interconnect_2_emif_hps_s0_axil_awprot),  //  output,   width = 3,                                                                 .awprot
		.emif_hps_s0_axil_awvalid                                               (mm_interconnect_2_emif_hps_s0_axil_awvalid), //  output,   width = 1,                                                                 .awvalid
		.emif_hps_s0_axil_awready                                               (mm_interconnect_2_emif_hps_s0_axil_awready), //   input,   width = 1,                                                                 .awready
		.emif_hps_s0_axil_wdata                                                 (mm_interconnect_2_emif_hps_s0_axil_wdata),   //  output,  width = 32,                                                                 .wdata
		.emif_hps_s0_axil_wstrb                                                 (mm_interconnect_2_emif_hps_s0_axil_wstrb),   //  output,   width = 4,                                                                 .wstrb
		.emif_hps_s0_axil_wvalid                                                (mm_interconnect_2_emif_hps_s0_axil_wvalid),  //  output,   width = 1,                                                                 .wvalid
		.emif_hps_s0_axil_wready                                                (mm_interconnect_2_emif_hps_s0_axil_wready),  //   input,   width = 1,                                                                 .wready
		.emif_hps_s0_axil_bresp                                                 (mm_interconnect_2_emif_hps_s0_axil_bresp),   //   input,   width = 2,                                                                 .bresp
		.emif_hps_s0_axil_bvalid                                                (mm_interconnect_2_emif_hps_s0_axil_bvalid),  //   input,   width = 1,                                                                 .bvalid
		.emif_hps_s0_axil_bready                                                (mm_interconnect_2_emif_hps_s0_axil_bready),  //  output,   width = 1,                                                                 .bready
		.emif_hps_s0_axil_araddr                                                (mm_interconnect_2_emif_hps_s0_axil_araddr),  //  output,  width = 27,                                                                 .araddr
		.emif_hps_s0_axil_arprot                                                (mm_interconnect_2_emif_hps_s0_axil_arprot),  //  output,   width = 3,                                                                 .arprot
		.emif_hps_s0_axil_arvalid                                               (mm_interconnect_2_emif_hps_s0_axil_arvalid), //  output,   width = 1,                                                                 .arvalid
		.emif_hps_s0_axil_arready                                               (mm_interconnect_2_emif_hps_s0_axil_arready), //   input,   width = 1,                                                                 .arready
		.emif_hps_s0_axil_rdata                                                 (mm_interconnect_2_emif_hps_s0_axil_rdata),   //   input,  width = 32,                                                                 .rdata
		.emif_hps_s0_axil_rresp                                                 (mm_interconnect_2_emif_hps_s0_axil_rresp),   //   input,   width = 2,                                                                 .rresp
		.emif_hps_s0_axil_rvalid                                                (mm_interconnect_2_emif_hps_s0_axil_rvalid),  //   input,   width = 1,                                                                 .rvalid
		.emif_hps_s0_axil_rready                                                (mm_interconnect_2_emif_hps_s0_axil_rready),  //  output,   width = 1,                                                                 .rready
		.agilex_hps_io96b0_csr_axi_awaddr                                       (agilex_hps_io96b0_csr_axi_awaddr),           //   input,  width = 32,                                        agilex_hps_io96b0_csr_axi.awaddr
		.agilex_hps_io96b0_csr_axi_awprot                                       (agilex_hps_io96b0_csr_axi_awprot),           //   input,   width = 3,                                                                 .awprot
		.agilex_hps_io96b0_csr_axi_awvalid                                      (agilex_hps_io96b0_csr_axi_awvalid),          //   input,   width = 1,                                                                 .awvalid
		.agilex_hps_io96b0_csr_axi_awready                                      (agilex_hps_io96b0_csr_axi_awready),          //  output,   width = 1,                                                                 .awready
		.agilex_hps_io96b0_csr_axi_wdata                                        (agilex_hps_io96b0_csr_axi_wdata),            //   input,  width = 32,                                                                 .wdata
		.agilex_hps_io96b0_csr_axi_wstrb                                        (agilex_hps_io96b0_csr_axi_wstrb),            //   input,   width = 4,                                                                 .wstrb
		.agilex_hps_io96b0_csr_axi_wvalid                                       (agilex_hps_io96b0_csr_axi_wvalid),           //   input,   width = 1,                                                                 .wvalid
		.agilex_hps_io96b0_csr_axi_wready                                       (agilex_hps_io96b0_csr_axi_wready),           //  output,   width = 1,                                                                 .wready
		.agilex_hps_io96b0_csr_axi_bresp                                        (agilex_hps_io96b0_csr_axi_bresp),            //  output,   width = 2,                                                                 .bresp
		.agilex_hps_io96b0_csr_axi_bvalid                                       (agilex_hps_io96b0_csr_axi_bvalid),           //  output,   width = 1,                                                                 .bvalid
		.agilex_hps_io96b0_csr_axi_bready                                       (agilex_hps_io96b0_csr_axi_bready),           //   input,   width = 1,                                                                 .bready
		.agilex_hps_io96b0_csr_axi_araddr                                       (agilex_hps_io96b0_csr_axi_araddr),           //   input,  width = 32,                                                                 .araddr
		.agilex_hps_io96b0_csr_axi_arprot                                       (agilex_hps_io96b0_csr_axi_arprot),           //   input,   width = 3,                                                                 .arprot
		.agilex_hps_io96b0_csr_axi_arvalid                                      (agilex_hps_io96b0_csr_axi_arvalid),          //   input,   width = 1,                                                                 .arvalid
		.agilex_hps_io96b0_csr_axi_arready                                      (agilex_hps_io96b0_csr_axi_arready),          //  output,   width = 1,                                                                 .arready
		.agilex_hps_io96b0_csr_axi_rdata                                        (agilex_hps_io96b0_csr_axi_rdata),            //  output,  width = 32,                                                                 .rdata
		.agilex_hps_io96b0_csr_axi_rresp                                        (agilex_hps_io96b0_csr_axi_rresp),            //  output,   width = 2,                                                                 .rresp
		.agilex_hps_io96b0_csr_axi_rvalid                                       (agilex_hps_io96b0_csr_axi_rvalid),           //  output,   width = 1,                                                                 .rvalid
		.agilex_hps_io96b0_csr_axi_rready                                       (agilex_hps_io96b0_csr_axi_rready),           //   input,   width = 1,                                                                 .rready
		.agilex_hps_io96b0_csr_axi_id_pad_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset),         //   input,   width = 1, agilex_hps_io96b0_csr_axi_id_pad_clk_reset_reset_bridge_in_reset.reset
		.emif_hps_s0_axil_clk_clk                                               (emif_hps_s0_axil_clk_clk)                    //   input,   width = 1,                                             emif_hps_s0_axil_clk.clk
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~emif_hps_usr_rst_n_0_reset),    //   input,  width = 1, reset_in0.reset
		.clk            (emif_hps_usr_clk_0_clk),         //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                               // (terminated),                       
		.reset_req_in0  (1'b0),                           // (terminated),                       
		.reset_in1      (1'b0),                           // (terminated),                       
		.reset_req_in1  (1'b0),                           // (terminated),                       
		.reset_in2      (1'b0),                           // (terminated),                       
		.reset_req_in2  (1'b0),                           // (terminated),                       
		.reset_in3      (1'b0),                           // (terminated),                       
		.reset_req_in3  (1'b0),                           // (terminated),                       
		.reset_in4      (1'b0),                           // (terminated),                       
		.reset_req_in4  (1'b0),                           // (terminated),                       
		.reset_in5      (1'b0),                           // (terminated),                       
		.reset_req_in5  (1'b0),                           // (terminated),                       
		.reset_in6      (1'b0),                           // (terminated),                       
		.reset_req_in6  (1'b0),                           // (terminated),                       
		.reset_in7      (1'b0),                           // (terminated),                       
		.reset_req_in7  (1'b0),                           // (terminated),                       
		.reset_in8      (1'b0),                           // (terminated),                       
		.reset_req_in8  (1'b0),                           // (terminated),                       
		.reset_in9      (1'b0),                           // (terminated),                       
		.reset_req_in9  (1'b0),                           // (terminated),                       
		.reset_in10     (1'b0),                           // (terminated),                       
		.reset_req_in10 (1'b0),                           // (terminated),                       
		.reset_in11     (1'b0),                           // (terminated),                       
		.reset_req_in11 (1'b0),                           // (terminated),                       
		.reset_in12     (1'b0),                           // (terminated),                       
		.reset_req_in12 (1'b0),                           // (terminated),                       
		.reset_in13     (1'b0),                           // (terminated),                       
		.reset_req_in13 (1'b0),                           // (terminated),                       
		.reset_in14     (1'b0),                           // (terminated),                       
		.reset_req_in14 (1'b0),                           // (terminated),                       
		.reset_in15     (1'b0),                           // (terminated),                       
		.reset_req_in15 (1'b0)                            // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (~emif_hps_usr_rst_n_0_reset),        //   input,  width = 1, reset_in0.reset
		.clk            (emif_hps_usr_clk_0_clk),             //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_002 (
		.reset_in0      (~emif_hps_s0_axil_rst_n_reset),      //   input,  width = 1, reset_in0.reset
		.clk            (emif_hps_s0_axil_clk_clk),           //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_002_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
