// emif_hps_altera_gpio_2210_vrazwmy.v

// This file was auto-generated from altera_gpio_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module emif_hps_altera_gpio_2210_vrazwmy (
		output wire [0:0] dout,   //   dout.export, Data output to the FPGA core in input or bidirectional mode, DATA_SIZE depends on the register mode: Bypass or simple register - DATA_SIZE = SIZE DDIO - DATA_SIZE = 2 x SIZE
		input  wire [0:0] pad_in  // pad_in.export, Input signal from the pad.
	);

	altera_gpio #(
		.SIZE                (1),
		.PIN_TYPE            ("input"),
		.REGISTER_MODE       ("none"),
		.HALF_RATE           ("false"),
		.DDIO_WITH_DELAY     ("false"),
		.SEPARATE_I_O_CLOCKS ("false"),
		.BUFFER_TYPE         ("single-ended"),
		.PSEUDO_DIFF         ("false"),
		.ARESET_MODE         ("none"),
		.SRESET_MODE         ("none"),
		.OPEN_DRAIN          ("false"),
		.BUS_HOLD            ("false"),
		.ENABLE_OE           ("false"),
		.ENABLE_CKE          ("false"),
		.ENABLE_TERM         ("false")
	) core (
		.dout               (dout),   //  output,  width = 1,   dout.export
		.pad_in             (pad_in), //   input,  width = 1, pad_in.export
		.cke                (1'b1),   // (terminated),                    
		.ck_in              (1'b0),   // (terminated),                    
		.ck_out             (1'b0),   // (terminated),                    
		.ck                 (1'b0),   // (terminated),                    
		.din                (1'b0),   // (terminated),                    
		.oe                 (1'b0),   // (terminated),                    
		.pad_io             (),       // (terminated),                    
		.pad_io_b           (),       // (terminated),                    
		.pad_in_b           (1'b0),   // (terminated),                    
		.pad_out            (),       // (terminated),                    
		.pad_out_b          (),       // (terminated),                    
		.terminationcontrol (1'b0),   // (terminated),                    
		.aclr               (1'b0),   // (terminated),                    
		.aset               (1'b0),   // (terminated),                    
		.sclr               (1'b0),   // (terminated),                    
		.sset               (1'b0)    // (terminated),                    
	);

endmodule
