// ext_hps_f2sdram_master.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module ext_hps_f2sdram_master #(
		parameter SYNC_RESET = 0
	) (
		input  wire        clk,                  //           clock.clk
		input  wire        reset,                //           reset.reset
		input  wire [29:0] avs_s0_address,       //  windowed_slave.address
		input  wire        avs_s0_read,          //                .read
		output wire [31:0] avs_s0_readdata,      //                .readdata
		input  wire        avs_s0_write,         //                .write
		input  wire [31:0] avs_s0_writedata,     //                .writedata
		output wire        avs_s0_readdatavalid, //                .readdatavalid
		output wire        avs_s0_waitrequest,   //                .waitrequest
		input  wire [3:0]  avs_s0_byteenable,    //                .byteenable
		input  wire [0:0]  avs_s0_burstcount,    //                .burstcount
		output wire [32:0] avm_m0_address,       // expanded_master.address
		output wire        avm_m0_read,          //                .read
		input  wire        avm_m0_waitrequest,   //                .waitrequest
		input  wire [31:0] avm_m0_readdata,      //                .readdata
		output wire        avm_m0_write,         //                .write
		output wire [31:0] avm_m0_writedata,     //                .writedata
		input  wire        avm_m0_readdatavalid, //                .readdatavalid
		output wire [3:0]  avm_m0_byteenable,    //                .byteenable
		output wire [0:0]  avm_m0_burstcount     //                .burstcount
	);

	ext_hps_f2sdram_master_altera_address_span_extender_1920_ce2ojky #(
		.DATA_WIDTH           (32),
		.BYTEENABLE_WIDTH     (4),
		.MASTER_ADDRESS_WIDTH (33),
		.SLAVE_ADDRESS_WIDTH  (30),
		.SLAVE_ADDRESS_SHIFT  (2),
		.BURSTCOUNT_WIDTH     (1),
		.CNTL_ADDRESS_WIDTH   (1),
		.SUB_WINDOW_COUNT     (1),
		.MASTER_ADDRESS_DEF   (64'b0000000000000000000000000000000000000000000000000000000000000000),
		.SYNC_RESET           (SYNC_RESET)
	) altera_address_span_extender_inst (
		.clk                  (clk),                                                                  //   input,   width = 1,           clock.clk
		.reset                (reset),                                                                //   input,   width = 1,           reset.reset
		.avs_s0_address       (avs_s0_address),                                                       //   input,  width = 30,  windowed_slave.address
		.avs_s0_read          (avs_s0_read),                                                          //   input,   width = 1,                .read
		.avs_s0_readdata      (avs_s0_readdata),                                                      //  output,  width = 32,                .readdata
		.avs_s0_write         (avs_s0_write),                                                         //   input,   width = 1,                .write
		.avs_s0_writedata     (avs_s0_writedata),                                                     //   input,  width = 32,                .writedata
		.avs_s0_readdatavalid (avs_s0_readdatavalid),                                                 //  output,   width = 1,                .readdatavalid
		.avs_s0_waitrequest   (avs_s0_waitrequest),                                                   //  output,   width = 1,                .waitrequest
		.avs_s0_byteenable    (avs_s0_byteenable),                                                    //   input,   width = 4,                .byteenable
		.avs_s0_burstcount    (avs_s0_burstcount),                                                    //   input,   width = 1,                .burstcount
		.avm_m0_address       (avm_m0_address),                                                       //  output,  width = 33, expanded_master.address
		.avm_m0_read          (avm_m0_read),                                                          //  output,   width = 1,                .read
		.avm_m0_waitrequest   (avm_m0_waitrequest),                                                   //   input,   width = 1,                .waitrequest
		.avm_m0_readdata      (avm_m0_readdata),                                                      //   input,  width = 32,                .readdata
		.avm_m0_write         (avm_m0_write),                                                         //  output,   width = 1,                .write
		.avm_m0_writedata     (avm_m0_writedata),                                                     //  output,  width = 32,                .writedata
		.avm_m0_readdatavalid (avm_m0_readdatavalid),                                                 //   input,   width = 1,                .readdatavalid
		.avm_m0_byteenable    (avm_m0_byteenable),                                                    //  output,   width = 4,                .byteenable
		.avm_m0_burstcount    (avm_m0_burstcount),                                                    //  output,   width = 1,                .burstcount
		.avs_cntl_address     (1'b0),                                                                 // (terminated),                              
		.avs_cntl_read        (1'b0),                                                                 // (terminated),                              
		.avs_cntl_readdata    (),                                                                     // (terminated),                              
		.avs_cntl_write       (1'b0),                                                                 // (terminated),                              
		.avs_cntl_writedata   (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated),                              
		.avs_cntl_byteenable  (8'b00000000)                                                           // (terminated),                              
	);

endmodule
