// (C) 2001-2024 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.


// Source: /nfs/site/disks/smx_rtl_1/users/sujoymit/dmx/rels/sm_hssi_top.snap-view-rtl-REVA-WW31.1

module usb #(
	parameter x_decoder_sm_flux_rx_demux_0__sel = "SEL_UNUSED",
	parameter x_decoder_sm_flux_rx_rxword_clk_demux_0__sel = "SEL_UNUSED",
	parameter x_decoder_sm_flux_tx_txword_clk_demux_0__sel = "SEL_UNUSED",
	parameter x_mux_sm_flux_dpma_clk_mux_0__sel = "SEL_UNUSED",
	parameter x_mux_sm_flux_tx_mux_0__sel = "SEL_UNUSED",
	parameter x_mux_sm_flux_tx_txword_clk_mux_0__sel = "SEL_UNUSED",
	parameter x_mux_sm_hssi_pcie_pcs_rst_mux_0__sel = "SEL_UNUSED",
	parameter x_mux_sm_xcvrif_rx_ch_clk_mux_0__sel = "SEL_UNUSED",
	parameter x_mux_sm_xcvrif_tx_ch_clk_mux_0__sel = "SEL_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_refclk_select = "CH0_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_flux_mode = "CH0_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_loopback_mode = "CH0_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_pcie_mode = "CH0_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_monitor_en = "CH0_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_preloaded_hardware_configs = "CH0_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_sim_mode = "CH0_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_width = "CH0_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_bonding_category = "CH0_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_refclk_select = "CH0_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_gen_en = "CH0_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_preloaded_hardware_configs = "CH0_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_sim_mode = "CH0_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_user_clk_only_mode = "CH0_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_width = "CH0_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_refclk_select = "CH1_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_flux_mode = "CH1_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_loopback_mode = "CH1_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_pcie_mode = "CH1_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_monitor_en = "CH1_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_preloaded_hardware_configs = "CH1_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_sim_mode = "CH1_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_width = "CH1_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_bonding_category = "CH1_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_refclk_select = "CH1_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_gen_en = "CH1_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_preloaded_hardware_configs = "CH1_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_sim_mode = "CH1_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_user_clk_only_mode = "CH1_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_width = "CH1_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_refclk_select = "CH2_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_flux_mode = "CH2_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_loopback_mode = "CH2_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_pcie_mode = "CH2_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_monitor_en = "CH2_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_preloaded_hardware_configs = "CH2_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_sim_mode = "CH2_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_width = "CH2_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_bonding_category = "CH2_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_refclk_select = "CH2_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_gen_en = "CH2_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_preloaded_hardware_configs = "CH2_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_sim_mode = "CH2_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_user_clk_only_mode = "CH2_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_width = "CH2_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_refclk_select = "CH3_CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_flux_mode = "CH3_FLUX_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_loopback_mode = "CH3_LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_pcie_mode = "CH3_PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_monitor_en = "CH3_RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_preloaded_hardware_configs = "CH3_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_sim_mode = "CH3_RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_width = "CH3_RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_bonding_category = "CH3_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_refclk_select = "CH3_TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_gen_en = "CH3_TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_preloaded_hardware_configs = "CH3_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_sim_mode = "CH3_TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_user_clk_only_mode = "CH3_TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_width = "CH3_TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_f_out_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_f_pfd_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_f_ref_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_f_vco_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_m_counter = 9'b000000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_n_counter = 6'b000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__cdr_refclk_select = "CDR_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_0_enable = "CLK_DEBUG_SELECT_0_ENABLE_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_0_setting = "CLK_DEBUG_SELECT_0_SETTING_SLOW_MEDIUM",
	parameter x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_1_enable = "CLK_DEBUG_SELECT_1_ENABLE_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_1_setting = "CLK_DEBUG_SELECT_1_SETTING_SLOW_MEDIUM",
	parameter x_std_ipfluxtop_uxtop_wrap_0__duplex_mode = "DUPLEX_MODE_DUPLEX",
	parameter x_std_ipfluxtop_uxtop_wrap_0__ick_tx_word_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__lane_common_ref_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__loopback_mode = "LOOPBACK_MODE_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__pcie_mode = "PCIE_MODE_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__pcs_ref_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_adaptation_mode = "RX_ADAPTATION_MODE_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_cdrdivout_en = "RX_CDRDIVOUT_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_datarate_bps = 37'b0000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_en = "FALSE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_eq_dfe_tap_1 = 6'b000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_eq_hf_boost = 6'b000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_eq_vga_gain = 7'b0000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_external_couple_type = "RX_EXTERNAL_COUPLE_TYPE_AC",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_force_cdr_ltr = "FALSE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_invert_pin = "RX_INVERT_PIN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_onchip_termination_setting = "RX_ONCHIP_TERMINATION_SETTING_R_1",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_divider = 8'b00000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_en = "RX_POSTDIV_CLK_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_fractional_en = "RX_POSTDIV_CLK_FRACTIONAL_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_prbs_monitor_en = "RX_PRBS_MONITOR_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_preloaded_hardware_configs = "RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_protocol_hint = "RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_sim_mode = "RX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_termination_mode = "RX_TERMINATION_MODE_HIGH_Z",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_width = "RX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__rx_word_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__speed_grade = "SPEED_GRADE_DASH_1",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_bond_size = "TX_BOND_SIZE_UNUSED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_bonding_category = "TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_datarate_bps = 37'b0000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_en = "FALSE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_eq_main_tap = 6'b000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_eq_post_tap_1 = 5'b00000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_eq_pre_tap_1 = 5'b00000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_eq_pre_tap_2 = 3'b000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_invert_pin = "TX_INVERT_PIN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_master_pll_mode = "TX_MASTER_PLL_MODE_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_bw_sel = "TX_PLL_BW_SEL_LOW",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_out_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_pfd_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_ref_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_vco_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_fb_counter = 2'b10,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_feed_forward_gain = 8'b00000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_k_counter = 22'b0000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_l_counter = 6'b000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_m_counter = 9'b000000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_n_counter = 6'b000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_postdiv_sel = "TX_PLL_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_pll_refclk_select = "TX_PLL_REFCLK_SELECT_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_cdr_refclk_divider = 8'b00000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_cdr_refclk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_divider = 8'b00000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_fractional_en = "TX_POSTDIV_CLK_FRACTIONAL_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_prbs_gen_en = "TX_PRBS_GEN_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_prbs_pattern = 4'b0001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_preloaded_hardware_configs = "TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_protocol_hint = "TX_PROTOCOL_HINT_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_sim_mode = "TX_SIM_MODE_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_spread_spectrum_en = "TX_SPREAD_SPECTRUM_EN_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_synthdiv_out_divider = 8'b00000001,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_synthdiv_out_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_user_clk_only_mode = "TX_USER_CLK_ONLY_MODE_ENABLE",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_width = "TX_WIDTH_DISABLED",
	parameter x_std_ipfluxtop_uxtop_wrap_0__tx_word_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_ipfluxtop_uxtop_wrap_0__usb_mode = "USB_MODE_DISABLED",
	parameter x_std_sm_flux_ingress_0__clkrx_refclk_cssm_fw_control = "CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_flux_ingress_0__clkrx_refclk_sector_specifies_refclk_ready = "CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_flux_ingress_0__dr_enabled = "DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_flux_ingress_0__flux_mode = "FLUX_MODE_DISABLED",
	parameter x_std_sm_flux_ingress_0__local_refclk_cssm_fw_control = "LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_flux_ingress_0__local_refclk_sector_specifies_refclk_ready = "LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_flux_ingress_0__rx_dl_enable = "RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_flux_ingress_0__rx_dl_rx_lat_bit_for_async = 18'b000000000000000000,
	parameter x_std_sm_flux_ingress_0__rx_dl_rxbit_cntr_pma = "RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_flux_ingress_0__rx_dl_rxbit_rollover = 18'b000000000000000000,
	parameter x_std_sm_flux_ingress_0__rx_fec_type_used = "RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_flux_ingress_0__rx_protocol_hint = "RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_flux_ingress_0__rx_sim_mode = "RX_SIM_MODE_ENABLE",
	parameter x_std_sm_flux_ingress_0__rx_user1_clk_mux_dynamic_sel = "RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_flux_ingress_0__rx_user2_clk_mux_dynamic_sel = "RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_flux_ingress_0__sequencer_reg_en = "SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_flux_ingress_0__tx_bond_size = "TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_flux_ingress_0__tx_dl_enable = "TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_flux_ingress_0__tx_sim_mode = "TX_SIM_MODE_ENABLE",
	parameter x_std_sm_flux_ingress_0__tx_user1_clk_mux_dynamic_sel = "TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_flux_ingress_0__tx_user2_clk_mux_dynamic_sel = "TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_hssi_pcie_pcs_lane_0__hps_clkmux = "HPS_CLKMUX_UNUSED",
	parameter x_std_sm_hssi_pcie_pcs_lane_0__hpsrx_mux = "HPSRX_MUX_UNUSED",
	parameter x_std_sm_hssi_pcie_pcs_lane_0__hpstx_demux = "HPSTX_DEMUX_UNUSED",
	parameter x_std_sm_hssi_pcie_pcs_lane_0__pcie_pcs_mode = "PCIE_PCS_MODE_PCIE",
	parameter x_std_sm_hssi_pcie_pcs_lane_0__pclk_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_sm_hssi_pcie_pcs_lane_0__sris_enable = "SRIS_ENABLE_DISABLED",
	parameter x_std_sm_hssi_pld_chnl_dp_0__dr_enabled = "DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_hssi_pld_chnl_dp_0__duplex_mode = "DUPLEX_MODE_DUPLEX",
	parameter x_std_sm_hssi_pld_chnl_dp_0__pld_channel_identifier = "PLD_CHANNEL_IDENTIFIER_GENERIC",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_clkout1_divider = "RX_CLKOUT1_DIVIDER_DIV1",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_clkout2_divider = "RX_CLKOUT2_DIVIDER_DIV1",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_en = "FALSE",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_fifo_mode = "RX_FIFO_MODE_PHASE_COMP",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_fifo_width = "RX_FIFO_WIDTH_DOUBLE_WIDTH",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_fifo_wr_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_user1_clk_dynamic_mux = "RX_USER1_CLK_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_hssi_pld_chnl_dp_0__rx_user2_clk_dynamic_mux = "RX_USER2_CLK_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_hssi_pld_chnl_dp_0__sup_mode = "SUP_MODE_USER_MODE",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_clkout1_divider = "TX_CLKOUT1_DIVIDER_DIV1",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_clkout2_divider = "TX_CLKOUT2_DIVIDER_DIV1",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_en = "FALSE",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_fifo_mode = "TX_FIFO_MODE_PHASE_COMP",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_fifo_rd_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_fifo_width = "TX_FIFO_WIDTH_DOUBLE_WIDTH",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_user1_clk_dynamic_mux = "TX_USER1_CLK_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_hssi_pld_chnl_dp_0__tx_user2_clk_dynamic_mux = "TX_USER2_CLK_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_hssi_pld_chnl_dp_0__vc_rx_pldif_wm_en = "VC_RX_PLDIF_WM_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_cssm_fw_control = "CH0_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_sector_specifies_refclk_ready = "CH0_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_dr_enabled = "CH0_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_flux_mode = "CH0_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_lc_postdiv_sel = "CH0_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch0_local_refclk_cssm_fw_control = "CH0_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_local_refclk_sector_specifies_refclk_ready = "CH0_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_loopback_mode = "CH0_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_rst_mux_static_sel = "CH0_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_enable = "CH0_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_rx_lat_bit_for_async = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_cntr_pma = "CH0_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_rollover = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch0_rx_fec_type_used = "CH0_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_preloaded_hardware_configs = "CH0_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_protocol_hint = "CH0_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_user1_clk_mux_dynamic_sel = "CH0_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_user2_clk_mux_dynamic_sel = "CH0_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_rx_width = "CH0_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch0_sequencer_reg_en = "CH0_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_bond_size = "CH0_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_bonding_category = "CH0_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_dl_enable = "CH0_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_preloaded_hardware_configs = "CH0_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_user1_clk_mux_dynamic_sel = "CH0_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch0_tx_user2_clk_mux_dynamic_sel = "CH0_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_cssm_fw_control = "CH1_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_sector_specifies_refclk_ready = "CH1_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_dr_enabled = "CH1_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_flux_mode = "CH1_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_lc_postdiv_sel = "CH1_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch1_local_refclk_cssm_fw_control = "CH1_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_local_refclk_sector_specifies_refclk_ready = "CH1_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_loopback_mode = "CH1_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_rst_mux_static_sel = "CH1_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_enable = "CH1_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_rx_lat_bit_for_async = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_cntr_pma = "CH1_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_rollover = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch1_rx_fec_type_used = "CH1_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_preloaded_hardware_configs = "CH1_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_protocol_hint = "CH1_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_user1_clk_mux_dynamic_sel = "CH1_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_user2_clk_mux_dynamic_sel = "CH1_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_rx_width = "CH1_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch1_sequencer_reg_en = "CH1_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_bond_size = "CH1_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_bonding_category = "CH1_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_dl_enable = "CH1_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_preloaded_hardware_configs = "CH1_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_user1_clk_mux_dynamic_sel = "CH1_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch1_tx_user2_clk_mux_dynamic_sel = "CH1_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_cssm_fw_control = "CH2_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_sector_specifies_refclk_ready = "CH2_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_dr_enabled = "CH2_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_flux_mode = "CH2_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_lc_postdiv_sel = "CH2_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch2_local_refclk_cssm_fw_control = "CH2_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_local_refclk_sector_specifies_refclk_ready = "CH2_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_loopback_mode = "CH2_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_rst_mux_static_sel = "CH2_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_enable = "CH2_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_rx_lat_bit_for_async = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_cntr_pma = "CH2_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_rollover = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch2_rx_fec_type_used = "CH2_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_preloaded_hardware_configs = "CH2_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_protocol_hint = "CH2_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_user1_clk_mux_dynamic_sel = "CH2_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_user2_clk_mux_dynamic_sel = "CH2_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_rx_width = "CH2_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch2_sequencer_reg_en = "CH2_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_bond_size = "CH2_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_bonding_category = "CH2_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_dl_enable = "CH2_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_preloaded_hardware_configs = "CH2_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_user1_clk_mux_dynamic_sel = "CH2_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch2_tx_user2_clk_mux_dynamic_sel = "CH2_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_cssm_fw_control = "CH3_CLKRX_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_sector_specifies_refclk_ready = "CH3_CLKRX_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_dr_enabled = "CH3_DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_flux_mode = "CH3_FLUX_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_lc_postdiv_sel = "CH3_LC_POSTDIV_SEL_SYNTH_FAST",
	parameter x_std_sm_ux_toolbox_0__ch3_local_refclk_cssm_fw_control = "CH3_LOCAL_REFCLK_CSSM_FW_CONTROL_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_local_refclk_sector_specifies_refclk_ready = "CH3_LOCAL_REFCLK_SECTOR_SPECIFIES_REFCLK_READY_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_loopback_mode = "CH3_LOOPBACK_MODE_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_rst_mux_static_sel = "CH3_RST_MUX_STATIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_enable = "CH3_RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_rx_lat_bit_for_async = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_cntr_pma = "CH3_RX_DL_RXBIT_CNTR_PMA_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_rollover = 18'b000000000000000000,
	parameter x_std_sm_ux_toolbox_0__ch3_rx_fec_type_used = "CH3_RX_FEC_TYPE_USED_NONE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_preloaded_hardware_configs = "CH3_RX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_protocol_hint = "CH3_RX_PROTOCOL_HINT_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_user1_clk_mux_dynamic_sel = "CH3_RX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_user2_clk_mux_dynamic_sel = "CH3_RX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_rx_width = "CH3_RX_WIDTH_DISABLED",
	parameter x_std_sm_ux_toolbox_0__ch3_sequencer_reg_en = "CH3_SEQUENCER_REG_EN_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_bond_size = "CH3_TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_bonding_category = "CH3_TX_BONDING_CATEGORY_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_dl_enable = "CH3_TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_preloaded_hardware_configs = "CH3_TX_PRELOADED_HARDWARE_CONFIGS_NONE",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_user1_clk_mux_dynamic_sel = "CH3_TX_USER1_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_ux_toolbox_0__ch3_tx_user2_clk_mux_dynamic_sel = "CH3_TX_USER2_CLK_MUX_DYNAMIC_SEL_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__dr_enabled = "DR_ENABLED_DR_DISABLED",
	parameter x_std_sm_xcvrif_1ch_0__duplex_mode = "DUPLEX_MODE_DUPLEX",
	parameter x_std_sm_xcvrif_1ch_0__eth_rx_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_sm_xcvrif_1ch_0__eth_tx_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_sm_xcvrif_1ch_0__loopback_mode = "LOOPBACK_MODE_ENABLE",
	parameter x_std_sm_xcvrif_1ch_0__rx_bond_size = "RX_BOND_SIZE_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__rx_bonding_mode = "RX_BONDING_MODE_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__rx_dl_enable = "RX_DL_ENABLE_ENABLE",
	parameter x_std_sm_xcvrif_1ch_0__rx_en = "FALSE",
	parameter x_std_sm_xcvrif_1ch_0__rx_fifo_mode = "RX_FIFO_MODE_PHASE_COMP",
	parameter x_std_sm_xcvrif_1ch_0__rx_fifo_rd_en_dynamic_mux = "RX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__rx_gb_width = "RX_GB_WIDTH_DISABLED",
	parameter x_std_sm_xcvrif_1ch_0__rx_word_clk_dynamic_mux = "RX_WORD_CLK_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__sim_mode = "SIM_MODE_ENABLE",
	parameter x_std_sm_xcvrif_1ch_0__sup_mode = "SUP_MODE_USER_MODE",
	parameter x_std_sm_xcvrif_1ch_0__tx_bond_size = "TX_BOND_SIZE_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__tx_bonding_mode = "TX_BONDING_MODE_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__tx_dl_enable = "TX_DL_ENABLE_ENABLE",
	parameter x_std_sm_xcvrif_1ch_0__tx_dynamic_mux = "TX_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__tx_en = "FALSE",
	parameter x_std_sm_xcvrif_1ch_0__tx_fifo_mode = "TX_FIFO_MODE_PHASE_COMP",
	parameter x_std_sm_xcvrif_1ch_0__tx_fifo_rd_en_dynamic_mux = "TX_FIFO_RD_EN_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__tx_gb_width = "TX_GB_WIDTH_DISABLED",
	parameter x_std_sm_xcvrif_1ch_0__tx_rst_dynamic_mux = "TX_RST_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__tx_word_clk_dynamic_mux = "TX_WORD_CLK_DYNAMIC_MUX_UNUSED",
	parameter x_std_sm_xcvrif_1ch_0__xcvr_rxword_clk_hz = 36'b000000000000000000000000000000000000,
	parameter x_std_sm_xcvrif_1ch_0__xcvr_txword_clk_hz = 36'b000000000000000000000000000000000000
)
 (
	input [11:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async,
	input [13:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async,
	input [17:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr,
	input [19:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr,
	input [20:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr,
	input [2:0] x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel,
	input [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate,
	input [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate,
	input [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint,
	input [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin,
	input [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2,
	input [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3,
	input [31:0] x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata,
	input [31:0] x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata,
	input [31:0] x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata,
	input [31:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata,
	input [31:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata,
	input [39:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata,
	input [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt,
	input [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown,
	input [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak,
	input [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader,
	input [3:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be,
	input [3:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_be,
	input [3:0] x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux,
	input [42:0] x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data,
	input [4:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex,
	input [5:0] x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in,
	input [5:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs,
	input [5:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1,
	input [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1,
	input [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3,
	input [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata,
	input [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async,
	input [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux,
	input [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data,
	input [7:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus,
	input [99:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async,
	input [9:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct,
	input [9:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra,
	input x_dynMux_sm_xcvrif_rx_fifo_rd_en_mux_0__i_x4,
	input x_dynMux_sm_xcvrif_tx_fifo_rd_en_mux_0__i_x6_bot,
	input x_dynMux_sm_xcvrif_tx_rst_mux_0__i_x6_bot,
	input x_dynMux_sm_xcvrif_tx_rst_mux_1__i_x6_bot,
	input x_dynMux_sm_xcvrif_tx_word_clk_mux_0__i_x6_bot,
	input x_mux_sm_flux_dpma_clk_mux_0__i_global_downward_syspll_c2_clk,
	input x_mux_sm_flux_dpma_clk_mux_0__i_global_upward_syspll_c2_clk,
	input x_mux_sm_flux_dpma_clk_mux_0__i_local_syspll_c2_clk,
	input x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_hps_rst_rstn,
	input x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_same_quad_pcs_rst_rstn,
	input x_mux_sm_xcvrif_rx_ch_clk_mux_0__i_sys_clk,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane0,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane1,
	input x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane3,
	input x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_n_l0_ux,
	input x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_p_l0_ux,
	input x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_in,
	input x_std_ipfluxtop_uxtop_wrap_0__ioack_hsref_left_p_ux_bidir_in,
	input x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_in,
	input x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_in,
	input x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_valid,
	input x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_waitreq,
	input x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_valid,
	input x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_waitreq,
	input x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_valid,
	input x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_waitreq,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_pcs_pclk,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_asyncpowerchangeack,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_blockaligncontrol,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_cfg_hw_auto_sp_dis,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_dirchange,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_ebuf_mode,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_encodedecodebypass,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_getlocalpresetcoefficients,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_invalidrequest,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lowpin_nt,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclkchangeack,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxelecidle_disable_a,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqclr,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqeval,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqinprogress,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqtraining,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpolarity,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxstandby,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxtermination,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_srisenable,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcmnmode_disable_a,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcompliance,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatavalid,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdtctrx_lb,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txelecidle,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txoneszeros,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txstartblock,
	input x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txswing,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_dl_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_mux_select,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_flop,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_gen_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_trig_flop,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_sampling_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_dl_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_mux_select,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_flop,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_gen_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_trig_flop,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_rx_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_signal_ok,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_tx_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_read,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_rstn,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_write,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_reset_clk_row,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_rx_clk_in_row_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_tx_clk_in_row_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_rx_pld_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_tx_pld_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_ready,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_pma_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_sfrz,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_tx_pma_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_csr_ret,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_rx_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_tx_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_rx_fec_sfrz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_tx_fec_sfrz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_rx_xcvrif_sfrz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_tx_xcvrif_sfrz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_rx_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_signal_ok,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_tx_rst_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_rxdata_fifo_rd_en,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_2_r03f_rx_mac_srfz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_3_c2f_tx_deskew_srfz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_fifo_wr_en,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_direct,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_direct,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_direct,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstepcs_rx_pcs_fully_aligned,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstfec_fec_rx_rdy_n,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_tx_fifo_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk1_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk2_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk1_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk2_clk,
	input x_std_sm_hssi_pld_chnl_dp_0__i_ux_chnl_refclk_mux,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch0_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch1_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_read,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn,
	input x_std_sm_ux_toolbox_0__i_ch3_lavmm_write,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1,
	input x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1,
	input x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1,
	input x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1,
	input x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a,
	input x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1,
	input x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1,
	input x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1,
	input x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit,
	input x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1,
	output [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3,
	output [17:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients,
	output [19:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr,
	output [19:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr,
	output [19:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel,
	output [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel,
	output [1:0] x_std_sm_xcvrif_1ch_0__o_tx_source_sel,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1,
	output [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1,
	output [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3,
	output [2:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus,
	output [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel,
	output [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel,
	output [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel,
	output [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel,
	output [2:0] x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel,
	output [31:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata,
	output [31:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata,
	output [31:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata,
	output [31:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata,
	output [31:0] x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata,
	output [39:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata,
	output [3:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be,
	output [3:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be,
	output [3:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be,
	output [3:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak,
	output [3:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader,
	output [3:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async,
	output [3:0] x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc,
	output [42:0] x_std_sm_xcvrif_1ch_0__o_rx_data,
	output [49:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch0,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch1,
	output [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch3,
	output [5:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback,
	output [5:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs,
	output [5:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf,
	output [6:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1,
	output [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1,
	output [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3,
	output [79:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata,
	output [79:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data,
	output [7:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit,
	output [7:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus,
	output [7:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async,
	output [99:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async,
	output [9:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct,
	output [9:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra,
	output \x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstartblock[0] ,
	output x_decoder_sm_flux_tx_txword_clk_demux_0__o_eth_txword_clk,
	output x_dynMux_sm_flux_rx_user_clk_mux_0__o_ux_rxuser_clk,
	output x_dynMux_sm_flux_rx_user_clk_mux_1__o_ux_rxuser_clk,
	output x_dynMux_sm_flux_tx_user_clk_mux_0__o_ux_txuser_clk,
	output x_dynMux_sm_flux_tx_user_clk_mux_1__o_ux_txuser_clk,
	output x_mux_sm_xcvrif_rx_ch_clk_mux_0__o_eth_rx_ch_clk,
	output x_mux_sm_xcvrif_tx_ch_clk_mux_0__o_eth_tx_ch_clk,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_cpi_int,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1,
	output x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3,
	output x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_out,
	output x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_out,
	output x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_out,
	output x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_n_l0_ux,
	output x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_p_l0_ux,
	output x_std_sm_flux_ingress_0__o_ock_pcs_cdrfbclk,
	output x_std_sm_flux_ingress_0__o_ock_pcs_ref,
	output x_std_sm_flux_ingress_0__o_rst_flux0_cpi_cmn_busy,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_clk,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_read,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_rstn,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_write,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_clk,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_read,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_rstn,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_write,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_clk,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_read,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_rstn,
	output x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_write,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_pcs_pclk,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxcoefficientsvalid,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_pclkchangeok,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_phystatus,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatavalid,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxelecidlea,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstandbystatus,
	output x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxvalid,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_dl_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_pulse,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_sample_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_sclk_sample_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_trig_sample_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_dl_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_pulse,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_sample_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_sclk_sample_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_trig_sample_sync,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_valid,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_waitreq,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_flux0_cpi_cmn_busy,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_oflux_rx_srds_rdy,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_all_synthlockstatus,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_rxstatus,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_txstatus,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlock2data,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlockstatus,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstepcs_rx_pcs_fully_aligned,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstfec_fec_rx_rdy_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_empty,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_full,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pempty,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pfull,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_empty,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_full,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pempty,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pfull,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk1_clk,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk2_clk,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk1_clk,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk2_clk,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_chnl_refclk_mux,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_tx_ch_ptr_smpl,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_rx_latency_pulse,
	output x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_tx_latency_pulse,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_rx_rst_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_signal_ok,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_tx_rst_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_direct,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_direct,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_direct,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_rx_pld_rst_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_tx_pld_rst_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_ready,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_csr_ret,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_rx_rst_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_tx_rst_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_rx_fec_sfrz_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_tx_fec_sfrz_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_2_r03f_rx_mac_srfz_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_3_c2f_tx_deskew_srfz_n,
	output x_std_sm_hssi_pld_chnl_dp_0__o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n,
	output x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid,
	output x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1,
	output x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1,
	output x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1,
	output x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a,
	output x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit,
	output x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit,
	output x_std_sm_xcvrif_1ch_0__o_ch_xcvrif_rx_fifo_rd_en,
	output x_std_sm_xcvrif_1ch_0__o_ch_xcvrif_tx_fifo_rd_en,
	output x_std_sm_xcvrif_1ch_0__o_pma_rx_sf,
	output x_std_sm_xcvrif_1ch_0__o_tx_rst_rd_sync_rst_n,
	output x_std_sm_xcvrif_1ch_0__o_tx_rst_wr_sync_rst_n
);
	wire [0:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstartblock_0;
	wire [11:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0;
	wire [124:0] ux_toolbox_u0__o_sync_cfg_data_ch2_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0;
	wire [124:0] x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0;
	wire [13:0] o_ch2_eth_xcvrif_rx_async_1;
	wire [13:0] o_pcie_ch2_rxeq_best_eye_vala_1;
	wire [13:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0;
	wire [15:2] oflux_mem_DRam0Addr_1;
	wire [16:0] o_ss_ch3_lavmm_pcie_addr_0;
	wire [16:2] oflux_mem_IRam0Addr_1;
	wire [17:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0;
	wire [17:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0;
	wire [19:0] eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0;
	wire [19:0] flux_ingress_u2__o_lavmm_addr_0;
	wire [19:0] iflux_mem_DRam0CheckData_0;
	wire [19:0] o_ch3_lavmm_ux_addr_0;
	wire [19:0] o_ss_ch3_lavmm_ethe_addr_0;
	wire [19:0] oflux_mem_DRam0CheckWrData_1;
	wire [19:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0;
	wire [19:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0;
	wire [19:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0;
	wire [19:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0;
	wire [1:0] flux_ingress_u2__o_ux_rxuser1_sel_0;
	wire [1:0] flux_ingress_u2__o_ux_rxuser2_sel_0;
	wire [1:0] flux_ingress_u2__o_ux_txuser1_sel_0;
	wire [1:0] flux_ingress_u2__o_ux_txuser2_sel_0;
	wire [1:0] o_pcie_ch2_rxmargin_status_gray_a_1;
	wire [1:0] o_uxq2_pcie_l1ctrla_0;
	wire [1:0] pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0;
	wire [1:0] ux_toolbox_u0__o_ux2_rxuser1_sel_0;
	wire [1:0] ux_toolbox_u0__o_ux2_rxuser2_sel_0;
	wire [1:0] ux_toolbox_u0__o_ux2_txuser1_sel_0;
	wire [1:0] ux_toolbox_u0__o_ux2_txuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0;
	wire [1:0] x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0;
	wire [1:0] x_std_sm_xcvrif_1ch_0__o_tx_source_sel_0;
	wire [1:0] xcvrif_1ch_u2__o_rx_xcvr_wordclk_sel_0;
	wire [20:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0;
	wire [249:0] ux_toolbox_u0__o_sync_interface_control_ch2_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0;
	wire [249:0] x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0;
	wire [256:0] oflux_egress_direct_lane2_1;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0;
	wire [256:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0;
	wire [2:0] o_flux_apb_pprot_0;
	wire [2:0] o_uxq2_rxeq_precal_code_selnt_0;
	wire [2:0] o_uxq2_rxpstate_0;
	wire [2:0] o_uxq2_rxwidth_0;
	wire [2:0] o_uxq2_txclkdivrate_0;
	wire [2:0] o_uxq2_txdrv_levnm2_0;
	wire [2:0] o_uxq2_txpstate_0;
	wire [2:0] o_uxq2_txwidth_0;
	wire [2:0] rx_fifo_en_sel_ch2_0;
	wire [2:0] x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0;
	wire [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0;
	wire [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0;
	wire [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0;
	wire [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0;
	wire [2:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0;
	wire [2:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0;
	wire [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0;
	wire [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0;
	wire [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0;
	wire [2:0] x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0;
	wire [2:0] x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0;
	wire [2:0] xcvrif_1ch_u2__o_tx_rst_source_sel_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0;
	wire [319:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0;
	wire [31:0] eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0;
	wire [31:0] flux_ingress_u2__i_lavmm_rdata_0;
	wire [31:0] flux_ingress_u2__o_lavmm_wdata_0;
	wire [31:0] iflux_mem_DRam0Data_0;
	wire [31:0] iflux_mem_IRam0Data_0;
	wire [31:0] iflux_mem_TraceMemData_0;
	wire [31:0] iflux_mem_qfifo_rd_data_0;
	wire [31:0] o_ch2_lavmm_pcie_rdata_1;
	wire [31:0] o_ch2_lavmm_rdata_1;
	wire [31:0] o_ch2_lavmm_xcvrif_rdata_0;
	wire [31:0] o_ch3_lavmm_ux_wdata_0;
	wire [31:0] o_eth_rx_data_2;
	wire [31:0] o_flux_apb_paddr_0;
	wire [31:0] o_flux_apb_pwdata_0;
	wire [31:0] o_ss_ch3_lavmm_ethe_wdata_0;
	wire [31:0] o_ss_ch3_lavmm_pcie_wdata_0;
	wire [31:0] o_ux_tx_ch2_data_1;
	wire [31:0] oflux_ext_pcs_prdata_1;
	wire [31:0] oflux_mem_DRam0WrData_1;
	wire [31:0] oflux_mem_IRam0WrData_1;
	wire [31:0] oflux_mem_TraceMemWrData_1;
	wire [31:0] oflux_mem_qfifo_wr_data_1;
	wire [31:0] pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0;
	wire [31:0] x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0;
	wire [31:0] x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0;
	wire [31:0] x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0;
	wire [31:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0;
	wire [31:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0;
	wire [31:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0;
	wire [31:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0;
	wire [31:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0;
	wire [31:0] x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0;
	wire [39:0] flux_mux_wrapper_u2__i_rx_data_0;
	wire [39:0] o_pcie_rx_data_2;
	wire [39:0] o_tx_data_2;
	wire [39:0] o_uxq2_txword_0;
	wire [39:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0;
	wire [39:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0;
	wire [3:0] eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0;
	wire [3:0] flux_ingress_u2__o_lavmm_be_0;
	wire [3:0] o_ch3_lavmm_ux_be_0;
	wire [3:0] o_flux_apb_pstrb_0;
	wire [3:0] o_ss_ch3_lavmm_ethe_be_0;
	wire [3:0] o_ss_ch3_lavmm_pcie_be_0;
	wire [3:0] o_uxq2_rxrate_0;
	wire [3:0] o_uxq2_txdrv_slew_0;
	wire [3:0] o_uxq2_txelecidle_0;
	wire [3:0] o_uxq2_txrate_0;
	wire [3:0] oflux_mem_DRam0ByteEn_1;
	wire [3:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0;
	wire [3:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0;
	wire [3:0] x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0;
	wire [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0;
	wire [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0;
	wire [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0;
	wire [3:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0;
	wire [3:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0;
	wire [3:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0;
	wire [3:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0;
	wire [3:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0;
	wire [3:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0;
	wire [3:0] x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0;
	wire [3:0] x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0;
	wire [42:0] x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0;
	wire [42:0] x_std_sm_xcvrif_1ch_0__o_rx_data_0;
	wire [49:0] o_ss_async_pldif_ch2_1;
	wire [49:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0;
	wire [4:0] o_uxq2_txdrv_levnm1_0;
	wire [4:0] o_uxq2_txdrv_levnp1_0;
	wire [4:0] ux_toolbox_u0__o_sync_common_control_ch2_0;
	wire [4:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0;
	wire [4:0] x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0;
	wire [5:0] o_uxq2_txdrv_levn_0;
	wire [5:0] x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0;
	wire [5:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0;
	wire [5:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0;
	wire [5:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0;
	wire [5:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0;
	wire [5:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0;
	wire [6:0] iflux_mem_IRam0CheckData_0;
	wire [6:0] o_ss_ch3_eth_xcvrif_tx_async_0;
	wire [6:0] o_ux_tx_ch2_sync_data_1;
	wire [6:0] o_uxq2_rxmargin_offset_nt_0;
	wire [6:0] oflux_mem_IRam0CheckWrData_1;
	wire [6:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0;
	wire [703:0] uxwrap_bus_out_lane2_1;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0;
	wire [703:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0;
	wire [767:0] uxwrap_bus_in_lane2_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0;
	wire [767:0] x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0;
	wire [79:0] o_flux_pcs_txword_lane2_0;
	wire [79:0] oflux_pcs_rxword_lane2_1;
	wire [79:0] ux_quad_u0__i_ss_async_pldif_ch2_0;
	wire [79:0] ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0;
	wire [79:0] x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0;
	wire [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0;
	wire [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0;
	wire [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0;
	wire [79:0] x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0;
	wire [79:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0;
	wire [79:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0;
	wire [7:0] x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0;
	wire [7:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0;
	wire [7:0] x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0;
	wire [7:0] x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0;
	wire [8:0] oflux_mem_TraceMemAddr_1;
	wire [8:0] oflux_mem_qfifo_rd_addr_1;
	wire [8:0] oflux_mem_qfifo_wr_addr_1;
	wire [99:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0;
	wire [99:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0;
	wire [9:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0;
	wire [9:0] x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0;
	wire [9:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0;
	wire [9:0] x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0;
	wire car_cpu_bresetn_1;
	wire car_cpu_clk_1;
	wire eth_lavmm_dec_u3__o_lavmm_xcvrif_clk_0;
	wire eth_lavmm_dec_u3__o_lavmm_xcvrif_read_0;
	wire eth_lavmm_dec_u3__o_lavmm_xcvrif_rstn_0;
	wire eth_lavmm_dec_u3__o_lavmm_xcvrif_write_0;
	wire flux_ingress_cnoc_clk_u0__o_cnoc_clk_2;
	wire flux_ingress_u2__i_lavmm_rdata_valid_0;
	wire flux_ingress_u2__i_lavmm_waitreq_0;
	wire flux_ingress_u2__i_rx_dl_ch_bit_0;
	wire flux_ingress_u2__o_dat_pcs_measlatrndtripbit_0;
	wire flux_ingress_u2__o_ft_rx_sclk_sync_ch_0;
	wire flux_ingress_u2__o_ft_tx_sclk_sync_ch_0;
	wire flux_ingress_u2__o_ick_sclk_rx_0;
	wire flux_ingress_u2__o_lavmm_clk_0;
	wire flux_ingress_u2__o_lavmm_read_0;
	wire flux_ingress_u2__o_lavmm_rstn_0;
	wire flux_ingress_u2__o_lavmm_write_0;
	wire flux_ingress_u2__o_ock_pcs_txword_0;
	wire flux_ingress_u2__o_octl_pcs_txstatus_a_0;
	wire flux_ingress_u2__o_pcs_rxpostdiv_0;
	wire flux_ingress_u2__o_pcs_rxword_0;
	wire flux_ingress_u2__o_rst_ux_rx_pma_rst_n_0;
	wire flux_ingress_u2__o_rst_ux_tx_pma_rst_n_0;
	wire flux_ingress_u2__o_sclk_return_sel_rx_0;
	wire flux_ingress_u2__o_sclk_return_sel_tx_0;
	wire flux_ingress_u2__o_ux_txlc_clk_0;
	wire mac_pcs_fec_top_u0__o_ft_ux_rx_sclk_sync_ch2_0;
	wire mac_pcs_fec_top_u0__o_ft_ux_tx_sclk_sync_ch2_0;
	wire mac_pcs_fec_top_u0__o_ux_sclk_rx_ch2_0;
	wire mac_pcs_fec_top_u0__o_ux_sclk_tx_ch2_0;
	wire n1_14;
	wire n1_1;
	wire n1_3;
	wire n2_0;
	wire o_ch2_eth_xcvrif_rx_direct_1;
	wire o_ch2_lavmm_pcie_rdata_valid_1;
	wire o_ch2_lavmm_pcie_waitreq_1;
	wire o_ch2_lavmm_rdata_valid_1;
	wire o_ch2_lavmm_waitreq_1;
	wire o_ch2_lavmm_xcvrif_rdata_valid_0;
	wire o_ch2_lavmm_xcvrif_waitreq_0;
	wire o_ch2_rstxcvrif_tx_rst_n_0;
	wire o_ch2_tx_rst_rd_sync_rst_n_0;
	wire o_ch2_tx_rst_wr_sync_rst_n_0;
	wire o_ch2_xcvrif_rx_fifo_rd_en_0;
	wire o_ch2_xcvrif_tx_fifo_rd_en_0;
	wire o_ch3_lavmm_ux_clk_0;
	wire o_ch3_lavmm_ux_read_0;
	wire o_ch3_lavmm_ux_rstn_0;
	wire o_ch3_lavmm_ux_write_0;
	wire o_ch3_rst_flux0_cpi_cmn_busy_2;
	wire o_ch3_rst_oflux_rx_srds_rdy_2;
	wire o_ch3_rst_ux_all_synthlockstatus_2;
	wire o_ch3_rst_ux_octl_pcs_rxstatus_2;
	wire o_ch3_rst_ux_octl_pcs_txstatus_2;
	wire o_ch3_rst_ux_rxcdrlock2data_2;
	wire o_ch3_rst_ux_rxcdrlockstatus_2;
	wire o_ch_xcvrif_rx_fifo_rd_en_2;
	wire o_ch_xcvrif_tx_fifo_rd_en_2;
	wire o_eth_rx_ch2_clk_4;
	wire o_eth_tx_ch2_clk_4;
	wire o_flux_apb_clk_0;
	wire o_flux_apb_penable_0;
	wire o_flux_apb_psel_0;
	wire o_flux_apb_pwrite_0;
	wire o_flux_apb_rst_n_0;
	wire o_flux_sclk_mux_0;
	wire o_ft_eth_rx_async_pulse_ch2_1;
	wire o_ft_eth_tx_async_pulse_ch2_1;
	wire o_ick_sclk_tx_ch2_0;
	wire o_local_pcs2_pipe_rstn_1;
	wire o_pcie_ch2_rxeq_donea_1;
	wire o_pcie_ch2_rxmargin_nacka_1;
	wire o_pcie_ch2_rxmargin_statusa_1;
	wire o_pcie_ch2_rxsignaldetect_lfpsa_1;
	wire o_pcie_ch2_rxsignaldetecta_1;
	wire o_pcie_ch2_synthlcfast_postdiv_1;
	wire o_pcie_ch2_synthlcmed_postdiv_1;
	wire o_pcie_ch2_synthlcslow_postdiv_1;
	wire o_pcie_ch2_txdetectrx_acka_1;
	wire o_pcie_ch2_txdetectrx_statct_1;
	wire o_pcs_txword_2;
	wire o_pcs_txword_ch0_0;
	wire o_pcs_txword_ch1_0;
	wire o_pcs_txword_ch2_0;
	wire o_pcs_txword_ch3_0;
	wire o_quartus_connection_to_serdes_lane2_0;
	wire o_rx_dl_ch2_bit_1;
	wire o_rx_latency_ch2_pulse_0;
	wire o_ss_ch3_eth_xcvrif_tx_direct_0;
	wire o_ss_ch3_lavmm_ethe_clk_0;
	wire o_ss_ch3_lavmm_ethe_read_0;
	wire o_ss_ch3_lavmm_ethe_rstn_0;
	wire o_ss_ch3_lavmm_ethe_write_0;
	wire o_ss_ch3_lavmm_pcie_clk_0;
	wire o_ss_ch3_lavmm_pcie_read_0;
	wire o_ss_ch3_lavmm_pcie_rstn_0;
	wire o_ss_ch3_lavmm_pcie_write_0;
	wire o_ss_ch3_rstxcvrif_e4_lphy_rx_rst_n_0;
	wire o_ss_ch3_rstxcvrif_lphy_signal_ok_0;
	wire o_ss_ch3_rstxcvrif_rx_reset_sfreeze_xcvrif_0;
	wire o_ss_ch3_rstxcvrif_tx_reset_sfreeze_xcvrif_0;
	wire o_tx_dl_ch2_bit_0;
	wire o_tx_latency_ch2_pulse_0;
	wire o_ux2_ock_pma_clk_1;
	wire o_ux_dpma_clk_2;
	wire o_ux_eth_rxword_clk_2;
	wire o_ux_eth_txword_clk_2;
	wire o_ux_pcie_rxword_clk_2;
	wire o_ux_pcie_txword_clk_2;
	wire o_uxq2_lfps_ennt_0;
	wire o_uxq2_pma_cmn_ctrl_0;
	wire o_uxq2_pma_ctrl_0;
	wire o_uxq2_rst_pcs_rx_b_a_0;
	wire o_uxq2_rst_pcs_tx_b_a_0;
	wire o_uxq2_rxeiosdetectstata_0;
	wire o_uxq2_rxeq_starta_0;
	wire o_uxq2_rxeq_static_ena_0;
	wire o_uxq2_rxmargin_direction_nt_0;
	wire o_uxq2_rxmargin_mode_nt_0;
	wire o_uxq2_rxmargin_offset_change_a_0;
	wire o_uxq2_rxmargin_start_a_0;
	wire o_uxq2_rxterm_hiz_ena_0;
	wire o_uxq2_tstbus_lane_0;
	wire o_uxq2_txbeacona_0;
	wire o_uxq2_txdetectrx_reqa_0;
	wire o_xcvr_rxword_ch_clk_2;
	wire o_xcvr_txword_ch_clk_2;
	wire oflux_cpi_int_1;
	wire oflux_ext_pcs_pready_1;
	wire oflux_ext_pcs_pslverr_1;
	wire oflux_int0_1;
	wire oflux_int1_1;
	wire oflux_int2_1;
	wire oflux_int3_1;
	wire oflux_mem_DRam0En_1;
	wire oflux_mem_DRam0Wr_1;
	wire oflux_mem_IRam0En_1;
	wire oflux_mem_IRam0Wr_1;
	wire oflux_mem_TraceMemEn_1;
	wire oflux_mem_TraceMemWr_1;
	wire oflux_mem_qfifo_rd_en_1;
	wire oflux_mem_qfifo_wr_en_1;
	wire oflux_octl_pcs_txptr_smpl_lane2_1;
	wire oflux_srds_rdy0_1;
	wire oflux_srds_rdy1_1;
	wire oflux_srds_rdy2_1;
	wire oflux_srds_rdy3_1;
	wire oflux_srds_rx_clk_lane0_1;
	wire oflux_srds_rx_clk_lane1_1;
	wire oflux_srds_rx_clk_lane2_1;
	wire oflux_srds_rx_clk_lane3_1;
	wire oflux_srds_rx_divn_clk_lane2_1;
	wire oflux_srds_tx_clk_lane2_1;
	wire pcie_pcs_rst_mux_u2__o_rstn_0;
	wire pcie_top_x4_u0__o_ft_ch3_rst_ux_rx_pma_rst_n_0;
	wire pcie_top_x4_u0__o_ft_ch3_rst_ux_rx_sfrz_0;
	wire pcie_top_x4_u0__o_ft_ch3_rst_ux_tx_pma_rst_n_0;
	wire pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_valid_0;
	wire pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_waitreq_0;
	wire quartus_i_dft_hssi_scan_mode_0;
	wire s3000_51_1__hssi_rstn_vcc_hssi__rst_n;
	wire s4706_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit;
	wire s4708_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit;
	wire tmp;
	wire tmp_100;
	wire tmp_101;
	wire tmp_102;
	wire tmp_103;
	wire tmp_104;
	wire tmp_105;
	wire tmp_106;
	wire tmp_107;
	wire tmp_108;
	wire tmp_109;
	wire tmp_10;
	wire tmp_110;
	wire tmp_111;
	wire tmp_112;
	wire tmp_113;
	wire tmp_114;
	wire tmp_115;
	wire tmp_116;
	wire tmp_117;
	wire tmp_118;
	wire tmp_119;
	wire tmp_11;
	wire tmp_120;
	wire tmp_121;
	wire tmp_122;
	wire tmp_123;
	wire tmp_124;
	wire tmp_125;
	wire tmp_126;
	wire tmp_127;
	wire tmp_128;
	wire tmp_129;
	wire tmp_12;
	wire tmp_130;
	wire tmp_131;
	wire tmp_132;
	wire tmp_133;
	wire tmp_134;
	wire tmp_135;
	wire tmp_136;
	wire tmp_137;
	wire tmp_138;
	wire tmp_139;
	wire tmp_13;
	wire tmp_140;
	wire tmp_141;
	wire tmp_142;
	wire tmp_143;
	wire tmp_144;
	wire tmp_145;
	wire tmp_146;
	wire tmp_147;
	wire tmp_148;
	wire tmp_149;
	wire tmp_14;
	wire tmp_150;
	wire tmp_151;
	wire tmp_152;
	wire tmp_153;
	wire tmp_154;
	wire tmp_155;
	wire tmp_156;
	wire tmp_157;
	wire tmp_158;
	wire tmp_159;
	wire tmp_15;
	wire tmp_160;
	wire tmp_161;
	wire tmp_162;
	wire tmp_163;
	wire tmp_164;
	wire tmp_165;
	wire tmp_166;
	wire tmp_167;
	wire tmp_168;
	wire tmp_169;
	wire tmp_16;
	wire tmp_170;
	wire tmp_171;
	wire tmp_172;
	wire tmp_173;
	wire tmp_174;
	wire tmp_175;
	wire tmp_176;
	wire tmp_177;
	wire tmp_178;
	wire tmp_179;
	wire tmp_17;
	wire tmp_180;
	wire tmp_181;
	wire tmp_182;
	wire tmp_183;
	wire tmp_184;
	wire tmp_185;
	wire tmp_186;
	wire tmp_187;
	wire tmp_188;
	wire tmp_189;
	wire tmp_18;
	wire tmp_190;
	wire tmp_191;
	wire tmp_192;
	wire tmp_193;
	wire tmp_194;
	wire tmp_195;
	wire tmp_196;
	wire tmp_197;
	wire tmp_198;
	wire tmp_199;
	wire tmp_19;
	wire tmp_1;
	wire tmp_200;
	wire tmp_201;
	wire tmp_202;
	wire tmp_203;
	wire tmp_204;
	wire tmp_205;
	wire tmp_206;
	wire tmp_207;
	wire tmp_208;
	wire tmp_209;
	wire tmp_20;
	wire tmp_210;
	wire tmp_211;
	wire tmp_212;
	wire tmp_213;
	wire tmp_214;
	wire tmp_215;
	wire tmp_216;
	wire tmp_217;
	wire tmp_218;
	wire tmp_219;
	wire tmp_21;
	wire tmp_220;
	wire tmp_221;
	wire tmp_222;
	wire tmp_223;
	wire tmp_224;
	wire tmp_225;
	wire tmp_226;
	wire tmp_227;
	wire tmp_228;
	wire tmp_229;
	wire tmp_22;
	wire tmp_230;
	wire tmp_231;
	wire tmp_232;
	wire tmp_233;
	wire tmp_234;
	wire tmp_235;
	wire tmp_236;
	wire tmp_237;
	wire tmp_238;
	wire tmp_239;
	wire tmp_23;
	wire tmp_240;
	wire tmp_241;
	wire tmp_242;
	wire tmp_243;
	wire tmp_244;
	wire tmp_245;
	wire tmp_246;
	wire tmp_247;
	wire tmp_248;
	wire tmp_249;
	wire tmp_24;
	wire tmp_250;
	wire tmp_251;
	wire tmp_252;
	wire tmp_253;
	wire tmp_254;
	wire tmp_255;
	wire tmp_256;
	wire tmp_257;
	wire tmp_258;
	wire tmp_259;
	wire tmp_25;
	wire tmp_260;
	wire tmp_261;
	wire tmp_262;
	wire tmp_263;
	wire tmp_264;
	wire tmp_265;
	wire tmp_266;
	wire tmp_267;
	wire tmp_268;
	wire tmp_269;
	wire tmp_26;
	wire tmp_270;
	wire tmp_271;
	wire tmp_272;
	wire tmp_273;
	wire tmp_274;
	wire tmp_275;
	wire tmp_276;
	wire tmp_277;
	wire tmp_278;
	wire tmp_279;
	wire tmp_27;
	wire tmp_280;
	wire tmp_281;
	wire tmp_282;
	wire tmp_283;
	wire tmp_284;
	wire tmp_285;
	wire tmp_286;
	wire tmp_287;
	wire tmp_288;
	wire tmp_289;
	wire tmp_28;
	wire tmp_290;
	wire tmp_291;
	wire tmp_292;
	wire tmp_293;
	wire tmp_294;
	wire tmp_295;
	wire tmp_296;
	wire tmp_297;
	wire tmp_298;
	wire tmp_299;
	wire tmp_29;
	wire tmp_2;
	wire tmp_300;
	wire tmp_301;
	wire tmp_302;
	wire tmp_303;
	wire tmp_304;
	wire tmp_305;
	wire tmp_306;
	wire tmp_307;
	wire tmp_308;
	wire tmp_309;
	wire tmp_30;
	wire tmp_310;
	wire tmp_311;
	wire tmp_312;
	wire tmp_313;
	wire tmp_314;
	wire tmp_315;
	wire tmp_316;
	wire tmp_317;
	wire tmp_318;
	wire tmp_319;
	wire tmp_31;
	wire tmp_320;
	wire tmp_321;
	wire tmp_322;
	wire tmp_323;
	wire tmp_324;
	wire tmp_325;
	wire tmp_326;
	wire tmp_327;
	wire tmp_328;
	wire tmp_329;
	wire tmp_32;
	wire tmp_330;
	wire tmp_331;
	wire tmp_332;
	wire tmp_333;
	wire tmp_334;
	wire tmp_335;
	wire tmp_336;
	wire tmp_337;
	wire tmp_338;
	wire tmp_339;
	wire tmp_33;
	wire tmp_340;
	wire tmp_341;
	wire tmp_342;
	wire tmp_343;
	wire tmp_344;
	wire tmp_345;
	wire tmp_346;
	wire tmp_347;
	wire tmp_348;
	wire tmp_349;
	wire tmp_34;
	wire tmp_350;
	wire tmp_351;
	wire tmp_352;
	wire tmp_353;
	wire tmp_354;
	wire tmp_355;
	wire tmp_356;
	wire tmp_357;
	wire tmp_358;
	wire tmp_359;
	wire tmp_35;
	wire tmp_360;
	wire tmp_361;
	wire tmp_362;
	wire tmp_363;
	wire tmp_364;
	wire tmp_365;
	wire tmp_366;
	wire tmp_367;
	wire tmp_368;
	wire tmp_369;
	wire tmp_36;
	wire tmp_370;
	wire tmp_371;
	wire tmp_372;
	wire tmp_373;
	wire tmp_374;
	wire tmp_375;
	wire tmp_376;
	wire tmp_377;
	wire tmp_378;
	wire tmp_379;
	wire tmp_37;
	wire tmp_380;
	wire tmp_381;
	wire tmp_382;
	wire tmp_383;
	wire tmp_384;
	wire tmp_385;
	wire tmp_386;
	wire tmp_387;
	wire tmp_388;
	wire tmp_389;
	wire tmp_38;
	wire tmp_390;
	wire tmp_391;
	wire tmp_392;
	wire tmp_393;
	wire tmp_394;
	wire tmp_395;
	wire tmp_396;
	wire tmp_397;
	wire tmp_398;
	wire tmp_399;
	wire tmp_39;
	wire tmp_3;
	wire tmp_400;
	wire tmp_401;
	wire tmp_402;
	wire tmp_403;
	wire tmp_404;
	wire tmp_405;
	wire tmp_406;
	wire tmp_407;
	wire tmp_408;
	wire tmp_409;
	wire tmp_40;
	wire tmp_410;
	wire tmp_411;
	wire tmp_412;
	wire tmp_413;
	wire tmp_414;
	wire tmp_415;
	wire tmp_416;
	wire tmp_417;
	wire tmp_418;
	wire tmp_419;
	wire tmp_41;
	wire tmp_420;
	wire tmp_421;
	wire tmp_422;
	wire tmp_423;
	wire tmp_424;
	wire tmp_425;
	wire tmp_426;
	wire tmp_427;
	wire tmp_428;
	wire tmp_429;
	wire tmp_42;
	wire tmp_430;
	wire tmp_431;
	wire tmp_432;
	wire tmp_433;
	wire tmp_434;
	wire tmp_435;
	wire tmp_436;
	wire tmp_437;
	wire tmp_438;
	wire tmp_439;
	wire tmp_43;
	wire tmp_440;
	wire tmp_441;
	wire tmp_442;
	wire tmp_443;
	wire tmp_444;
	wire tmp_445;
	wire tmp_446;
	wire tmp_447;
	wire tmp_448;
	wire tmp_449;
	wire tmp_44;
	wire tmp_450;
	wire tmp_451;
	wire tmp_452;
	wire tmp_453;
	wire tmp_454;
	wire tmp_455;
	wire tmp_456;
	wire tmp_457;
	wire tmp_458;
	wire tmp_459;
	wire tmp_45;
	wire tmp_460;
	wire tmp_461;
	wire tmp_462;
	wire tmp_463;
	wire tmp_464;
	wire tmp_465;
	wire tmp_466;
	wire tmp_467;
	wire tmp_468;
	wire tmp_469;
	wire tmp_46;
	wire tmp_470;
	wire tmp_471;
	wire tmp_472;
	wire tmp_473;
	wire tmp_474;
	wire tmp_475;
	wire tmp_476;
	wire tmp_477;
	wire tmp_478;
	wire tmp_479;
	wire tmp_47;
	wire tmp_480;
	wire tmp_481;
	wire tmp_482;
	wire tmp_483;
	wire tmp_484;
	wire tmp_485;
	wire tmp_486;
	wire tmp_487;
	wire tmp_488;
	wire tmp_489;
	wire tmp_48;
	wire tmp_490;
	wire tmp_491;
	wire tmp_492;
	wire tmp_493;
	wire tmp_494;
	wire tmp_495;
	wire tmp_496;
	wire tmp_497;
	wire tmp_498;
	wire tmp_499;
	wire tmp_49;
	wire tmp_4;
	wire tmp_500;
	wire tmp_501;
	wire tmp_502;
	wire tmp_503;
	wire tmp_504;
	wire tmp_505;
	wire tmp_506;
	wire tmp_507;
	wire tmp_508;
	wire tmp_509;
	wire tmp_50;
	wire tmp_510;
	wire tmp_511;
	wire tmp_512;
	wire tmp_513;
	wire tmp_514;
	wire tmp_515;
	wire tmp_516;
	wire tmp_517;
	wire tmp_518;
	wire tmp_519;
	wire tmp_51;
	wire tmp_520;
	wire tmp_521;
	wire tmp_522;
	wire tmp_523;
	wire tmp_524;
	wire tmp_525;
	wire tmp_526;
	wire tmp_527;
	wire tmp_528;
	wire tmp_529;
	wire tmp_52;
	wire tmp_530;
	wire tmp_531;
	wire tmp_532;
	wire tmp_533;
	wire tmp_534;
	wire tmp_535;
	wire tmp_536;
	wire tmp_537;
	wire tmp_538;
	wire tmp_539;
	wire tmp_53;
	wire tmp_540;
	wire tmp_541;
	wire tmp_542;
	wire tmp_543;
	wire tmp_544;
	wire tmp_545;
	wire tmp_546;
	wire tmp_547;
	wire tmp_548;
	wire tmp_549;
	wire tmp_54;
	wire tmp_550;
	wire tmp_551;
	wire tmp_552;
	wire tmp_553;
	wire tmp_554;
	wire tmp_555;
	wire tmp_55;
	wire tmp_56;
	wire tmp_57;
	wire tmp_58;
	wire tmp_59;
	wire tmp_5;
	wire tmp_60;
	wire tmp_61;
	wire tmp_62;
	wire tmp_63;
	wire tmp_64;
	wire tmp_65;
	wire tmp_66;
	wire tmp_67;
	wire tmp_68;
	wire tmp_69;
	wire tmp_6;
	wire tmp_70;
	wire tmp_71;
	wire tmp_72;
	wire tmp_73;
	wire tmp_74;
	wire tmp_75;
	wire tmp_76;
	wire tmp_77;
	wire tmp_78;
	wire tmp_79;
	wire tmp_7;
	wire tmp_80;
	wire tmp_81;
	wire tmp_82;
	wire tmp_83;
	wire tmp_84;
	wire tmp_85;
	wire tmp_86;
	wire tmp_87;
	wire tmp_88;
	wire tmp_89;
	wire tmp_8;
	wire tmp_90;
	wire tmp_91;
	wire tmp_92;
	wire tmp_93;
	wire tmp_94;
	wire tmp_95;
	wire tmp_96;
	wire tmp_97;
	wire tmp_98;
	wire tmp_99;
	wire tmp_9;
	wire ux_quad_u0__o_ux0_top_eth_txword_clk_0;
	wire ux_toolbox_u0__i_tx_dl_ch2_bit_0;
	wire ux_toolbox_u0__o_dat_pcs_measlatbit_ch2_0;
	wire ux_toolbox_u0__o_ft_rx_async_pulse_ch2_0;
	wire ux_toolbox_u0__o_ft_tx_async_pulse_ch2_0;
	wire ux_toolbox_u0__o_ictl_pcs_txenable_ch2_a_0;
	wire x_dynMux_sm_flux_rx_user_clk_mux_0__o_ux_rxuser_clk_1;
	wire x_dynMux_sm_flux_rx_user_clk_mux_1__o_ux_rxuser_clk_1;
	wire x_dynMux_sm_flux_tx_user_clk_mux_0__o_ux_txuser_clk_1;
	wire x_dynMux_sm_flux_tx_user_clk_mux_1__o_ux_txuser_clk_1;
	wire x_dynMux_sm_xcvrif_rx_fifo_rd_en_mux_0__i_x4_1;
	wire x_mux_sm_flux_dpma_clk_mux_0__i_global_downward_syspll_c2_clk_1;
	wire x_mux_sm_flux_dpma_clk_mux_0__i_global_upward_syspll_c2_clk_1;
	wire x_mux_sm_flux_dpma_clk_mux_0__i_local_syspll_c2_clk_1;
	wire x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_hps_rst_rstn_1;
	wire x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_same_quad_pcs_rst_rstn_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1_1;
	wire x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_n_l0_ux_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_p_l0_ux_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_in_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_out_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_hsref_left_p_ux_bidir_in_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_in_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_out_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_in_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_out_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_n_l0_ux_1;
	wire x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_p_l0_ux_1;
	wire x_std_sm_flux_ingress_0__o_ock_pcs_cdrfbclk_1;
	wire x_std_sm_flux_ingress_0__o_ock_pcs_ref_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_valid_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_waitreq_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_valid_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_waitreq_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_valid_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_waitreq_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_clk_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_read_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_rstn_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_write_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_clk_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_read_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_rstn_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_write_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_clk_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_read_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_rstn_1;
	wire x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_write_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_pcs_pclk_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_asyncpowerchangeack_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_blockaligncontrol_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_cfg_hw_auto_sp_dis_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_dirchange_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_ebuf_mode_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_encodedecodebypass_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_getlocalpresetcoefficients_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_invalidrequest_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lowpin_nt_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclkchangeack_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxelecidle_disable_a_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqclr_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqeval_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqinprogress_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqtraining_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpolarity_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxstandby_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxtermination_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_srisenable_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcmnmode_disable_a_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcompliance_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatavalid_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdtctrx_lb_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txelecidle_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txoneszeros_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txstartblock_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txswing_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_pcs_pclk_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxcoefficientsvalid_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_pclkchangeok_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_phystatus_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatavalid_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxelecidlea_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstandbystatus_1;
	wire x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxvalid_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_dl_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_mux_select_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_flop_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_gen_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_trig_flop_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_sampling_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_dl_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_mux_select_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_flop_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_gen_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_trig_flop_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_rx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_signal_ok_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_tx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_read_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_rstn_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_write_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_reset_clk_row_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_rx_clk_in_row_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_tx_clk_in_row_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_rx_pld_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_tx_pld_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_ready_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_pma_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_sfrz_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_tx_pma_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_csr_ret_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_rx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_tx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_rx_fec_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_tx_fec_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_rx_xcvrif_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_tx_xcvrif_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_rx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_signal_ok_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_tx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_rxdata_fifo_rd_en_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_2_r03f_rx_mac_srfz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_3_c2f_tx_deskew_srfz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_fifo_wr_en_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_direct_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_direct_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_direct_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstepcs_rx_pcs_fully_aligned_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstfec_fec_rx_rdy_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_tx_fifo_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk1_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk2_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk1_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk2_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__i_ux_chnl_refclk_mux_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_dl_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_pulse_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_sample_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_sclk_sample_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_trig_sample_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_dl_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_pulse_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_sample_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_sclk_sample_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_trig_sample_sync_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_valid_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_waitreq_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_flux0_cpi_cmn_busy_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_oflux_rx_srds_rdy_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_all_synthlockstatus_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_rxstatus_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_txstatus_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlock2data_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlockstatus_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstepcs_rx_pcs_fully_aligned_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstfec_fec_rx_rdy_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_empty_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_full_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pempty_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pfull_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_empty_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_full_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pempty_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pfull_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk1_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk2_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk1_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk2_clk_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_chnl_refclk_mux_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_tx_ch_ptr_smpl_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_rx_latency_pulse_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_tx_latency_pulse_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_rx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_signal_ok_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_tx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_direct_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_direct_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_direct_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_rx_pld_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_tx_pld_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_ready_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_csr_ret_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_rx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_tx_rst_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_rx_fec_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_tx_fec_sfrz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_2_r03f_rx_mac_srfz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_3_c2f_tx_deskew_srfz_n_1;
	wire x_std_sm_hssi_pld_chnl_dp_0__o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch0_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch1_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_read_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn_1;
	wire x_std_sm_ux_toolbox_0__i_ch3_lavmm_write_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a_1;
	wire x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1_1;
	wire x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit_1;
	wire x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit_1;
	wire x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid_1;
	wire x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1_1;
	wire x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1_1;
	wire x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1_1;
	wire x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a_1;
	wire x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit_1;
	wire x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit_1;
	wire x_std_sm_xcvrif_1ch_0__o_pma_rx_sf_1;
	wire xcvrif_tx_esys_clk_mux_u0__o_esys_ch_clk_2;
	wire xcvrif_tx_rd_rst_mux_u2__o_ch_xcvrif_tx_rst_n_0;
	wire xcvrif_tx_rst_mux_u2__o_ch_xcvrif_tx_rst_n_0;
	assign \x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstartblock[0]  = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstartblock_0[0];
	assign n1_1 = 1'b0;
	assign n1_14 = 1'b0;
	assign n1_3 = 1'b0;
	assign n2_0 = 1'b1;
	assign o_flux_sclk_mux_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ext_cpu_fast_clk;
	assign o_pcs_txword_ch0_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane0;
	assign o_pcs_txword_ch1_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane1;
	assign o_pcs_txword_ch3_0 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_srds_tx_clk_lane3;
	assign pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1] = 1'b0;
	assign quartus_i_dft_hssi_scan_mode_0 = 1'b0;
	assign s3000_51_1__hssi_rstn_vcc_hssi__rst_n = x_dynMux_sm_xcvrif_tx_rst_mux_1__i_x6_bot;
	assign s4706_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit = x_dynMux_sm_xcvrif_tx_fifo_rd_en_mux_0__i_x6_bot;
	assign s4708_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit = x_dynMux_sm_xcvrif_tx_rst_mux_0__i_x6_bot;
	assign ux_quad_u0__o_ux0_top_eth_txword_clk_0 = x_dynMux_sm_xcvrif_tx_word_clk_mux_0__i_x6_bot;
	assign x_decoder_sm_flux_tx_txword_clk_demux_0__o_eth_txword_clk = o_ux_eth_txword_clk_2;
	assign x_dynMux_sm_flux_rx_user_clk_mux_0__o_ux_rxuser_clk = x_dynMux_sm_flux_rx_user_clk_mux_0__o_ux_rxuser_clk_1;
	assign x_dynMux_sm_flux_rx_user_clk_mux_1__o_ux_rxuser_clk = x_dynMux_sm_flux_rx_user_clk_mux_1__o_ux_rxuser_clk_1;
	assign x_dynMux_sm_flux_tx_user_clk_mux_0__o_ux_txuser_clk = x_dynMux_sm_flux_tx_user_clk_mux_0__o_ux_txuser_clk_1;
	assign x_dynMux_sm_flux_tx_user_clk_mux_1__o_ux_txuser_clk = x_dynMux_sm_flux_tx_user_clk_mux_1__o_ux_txuser_clk_1;
	assign x_dynMux_sm_xcvrif_rx_fifo_rd_en_mux_0__i_x4_1 = x_dynMux_sm_xcvrif_rx_fifo_rd_en_mux_0__i_x4;
	assign x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0[0] = x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel[0];
	assign x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0[1] = x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel[1];
	assign x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0[2] = x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel[2];
	assign x_mux_sm_flux_dpma_clk_mux_0__i_global_downward_syspll_c2_clk_1 = x_mux_sm_flux_dpma_clk_mux_0__i_global_downward_syspll_c2_clk;
	assign x_mux_sm_flux_dpma_clk_mux_0__i_global_upward_syspll_c2_clk_1 = x_mux_sm_flux_dpma_clk_mux_0__i_global_upward_syspll_c2_clk;
	assign x_mux_sm_flux_dpma_clk_mux_0__i_local_syspll_c2_clk_1 = x_mux_sm_flux_dpma_clk_mux_0__i_local_syspll_c2_clk;
	assign x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_hps_rst_rstn_1 = x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_hps_rst_rstn;
	assign x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_same_quad_pcs_rst_rstn_1 = x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_same_quad_pcs_rst_rstn;
	assign x_mux_sm_xcvrif_rx_ch_clk_mux_0__o_eth_rx_ch_clk = o_eth_rx_ch2_clk_4;
	assign x_mux_sm_xcvrif_tx_ch_clk_mux_0__o_eth_tx_ch_clk = o_eth_tx_ch2_clk_4;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3_1 = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1[9];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[0];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[100];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[101];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[102];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[103];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[104];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[105];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[106];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[107];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[108];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[109];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[10];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[110];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[111];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[112];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[113];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[114];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[115];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[116];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[117];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[118];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[119];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[11];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[120];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[121];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[122];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[123];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[124];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[125];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[126];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[127];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[128];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[129];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[12];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[130];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[131];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[132];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[133];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[134];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[135];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[136];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[137];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[138];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[139];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[13];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[140];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[141];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[142];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[143];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[144];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[145];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[146];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[147];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[148];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[149];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[14];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[150];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[151];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[152];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[153];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[154];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[155];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[156];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[157];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[158];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[159];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[15];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[160];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[161];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[162];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[163];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[164];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[165];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[166];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[167];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[168];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[169];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[16];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[170];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[171];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[172];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[173];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[174];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[175];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[176];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[177];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[178];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[179];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[17];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[180];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[181];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[182];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[183];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[184];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[185];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[186];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[187];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[188];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[189];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[18];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[190];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[191];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[192];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[193];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[194];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[195];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[196];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[197];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[198];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[199];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[19];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[1];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[200];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[201];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[202];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[203];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[204];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[205];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[206];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[207];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[208];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[209];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[20];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[210];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[211];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[212];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[213];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[214];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[215];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[216];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[217];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[218];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[219];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[21];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[220];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[221];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[222];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[223];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[224];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[225];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[226];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[227];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[228];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[229];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[22];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[230];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[231];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[232];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[233];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[234];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[235];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[236];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[237];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[238];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[239];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[23];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[240];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[241];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[242];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[243];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[244];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[245];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[246];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[247];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[248];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[249];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[24];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[250];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[251];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[252];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[253];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[254];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[255];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[256];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[257];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[258];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[259];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[25];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[260];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[261];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[262];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[263];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[264];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[265];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[266];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[267];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[268];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[269];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[26];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[270];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[271];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[272];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[273];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[274];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[275];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[276];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[277];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[278];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[279];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[27];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[280];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[281];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[282];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[283];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[284];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[285];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[286];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[287];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[288];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[289];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[28];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[290];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[291];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[292];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[293];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[294];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[295];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[296];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[297];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[298];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[299];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[29];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[2];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[300];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[301];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[302];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[303];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[304];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[305];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[306];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[307];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[308];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[309];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[30];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[310];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[311];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[312];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[313];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[314];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[315];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[316];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[317];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[318];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[319];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[31];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[32];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[33];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[34];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[35];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[36];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[37];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[38];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[39];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[3];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[40];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[41];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[42];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[43];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[44];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[45];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[46];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[47];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[48];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[49];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[4];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[50];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[51];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[52];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[53];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[54];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[55];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[56];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[57];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[58];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[59];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[5];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[60];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[61];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[62];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[63];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[64];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[65];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[66];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[67];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[68];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[69];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[6];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[70];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[71];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[72];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[73];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[74];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[75];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[76];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[77];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[78];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[79];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[7];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[80];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[81];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[82];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[83];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[84];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[85];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[86];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[87];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[88];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[89];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[8];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[90];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[91];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[92];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[93];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[94];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[95];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[96];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[97];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[98];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[99];
	//assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_cpi_int = oflux_cpi_int_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int0 = oflux_int0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int1 = oflux_int1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_int3 = oflux_int3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy0 = oflux_srds_rdy0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy1 = oflux_srds_rdy1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rdy3 = oflux_srds_rdy3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane0 = oflux_srds_rx_clk_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane1 = oflux_srds_rx_clk_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_clk_lane3 = oflux_srds_rx_clk_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3 = x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3_1;
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane1_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[704] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[704];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[705] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[705];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[706] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[706];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[707] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[707];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[708] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[708];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[709] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[709];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[710] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[710];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[711] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[711];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[712] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[712];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[713] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[713];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[714] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[714];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[715] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[715];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[716] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[716];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[717] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[717];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[718] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[718];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[719] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[719];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[720] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[720];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[721] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[721];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[722] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[722];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[723] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[723];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[724] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[724];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[725] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[725];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[726] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[726];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[727] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[727];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[728] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[728];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[729] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[729];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[730] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[730];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[731] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[731];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[732] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[732];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[733] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[733];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[734] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[734];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[735] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[735];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[736] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[736];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[737] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[737];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[738] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[738];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[739] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[739];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[740] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[740];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[741] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[741];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[742] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[742];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[743] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[743];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[744] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[744];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[745] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[745];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[746] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[746];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[747] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[747];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[748] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[748];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[749] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[749];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[750] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[750];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[751] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[751];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[752] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[752];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[753] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[753];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[754] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[754];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[755] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[755];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[756] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[756];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[757] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[757];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[758] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[758];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[759] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[759];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[760] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[760];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[761] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[761];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[762] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[762];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[763] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[763];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[764] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[764];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[765] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[765];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[766] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[766];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[767] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[767];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane3_0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane0[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1[9];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[0] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[0];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[100] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[100];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[101] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[101];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[102] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[102];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[103] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[103];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[104] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[104];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[105] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[105];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[106] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[106];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[107] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[107];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[108] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[108];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[109] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[109];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[10] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[10];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[110] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[110];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[111] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[111];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[112] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[112];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[113] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[113];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[114] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[114];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[115] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[115];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[116] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[116];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[117] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[117];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[118] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[118];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[119] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[119];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[11] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[11];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[120] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[120];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[121] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[121];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[122] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[122];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[123] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[123];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[124] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[124];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[125] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[125];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[126] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[126];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[127] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[127];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[128] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[128];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[129] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[129];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[12] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[12];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[130] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[130];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[131] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[131];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[132] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[132];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[133] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[133];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[134] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[134];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[135] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[135];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[136] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[136];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[137] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[137];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[138] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[138];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[139] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[139];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[13] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[13];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[140] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[140];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[141] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[141];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[142] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[142];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[143] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[143];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[144] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[144];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[145] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[145];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[146] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[146];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[147] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[147];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[148] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[148];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[149] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[149];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[14] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[14];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[150] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[150];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[151] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[151];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[152] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[152];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[153] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[153];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[154] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[154];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[155] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[155];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[156] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[156];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[157] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[157];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[158] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[158];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[159] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[159];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[15] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[15];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[160] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[160];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[161] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[161];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[162] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[162];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[163] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[163];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[164] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[164];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[165] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[165];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[166] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[166];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[167] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[167];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[168] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[168];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[169] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[169];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[16] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[16];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[170] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[170];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[171] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[171];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[172] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[172];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[173] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[173];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[174] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[174];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[175] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[175];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[176] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[176];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[177] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[177];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[178] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[178];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[179] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[179];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[17] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[17];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[180] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[180];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[181] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[181];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[182] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[182];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[183] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[183];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[184] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[184];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[185] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[185];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[186] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[186];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[187] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[187];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[188] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[188];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[189] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[189];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[18] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[18];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[190] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[190];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[191] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[191];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[192] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[192];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[193] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[193];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[194] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[194];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[195] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[195];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[196] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[196];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[197] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[197];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[198] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[198];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[199] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[199];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[19] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[19];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[1] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[1];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[200] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[200];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[201] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[201];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[202] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[202];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[203] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[203];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[204] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[204];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[205] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[205];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[206] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[206];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[207] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[207];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[208] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[208];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[209] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[209];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[20] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[20];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[210] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[210];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[211] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[211];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[212] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[212];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[213] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[213];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[214] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[214];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[215] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[215];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[216] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[216];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[217] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[217];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[218] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[218];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[219] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[219];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[21] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[21];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[220] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[220];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[221] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[221];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[222] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[222];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[223] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[223];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[224] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[224];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[225] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[225];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[226] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[226];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[227] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[227];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[228] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[228];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[229] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[229];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[22] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[22];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[230] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[230];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[231] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[231];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[232] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[232];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[233] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[233];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[234] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[234];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[235] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[235];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[236] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[236];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[237] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[237];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[238] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[238];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[239] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[239];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[23] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[23];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[240] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[240];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[241] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[241];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[242] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[242];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[243] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[243];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[244] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[244];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[245] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[245];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[246] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[246];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[247] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[247];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[248] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[248];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[249] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[249];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[24] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[24];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[250] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[250];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[251] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[251];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[252] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[252];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[253] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[253];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[254] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[254];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[255] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[255];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[256] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[256];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[257] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[257];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[258] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[258];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[259] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[259];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[25] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[25];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[260] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[260];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[261] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[261];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[262] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[262];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[263] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[263];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[264] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[264];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[265] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[265];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[266] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[266];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[267] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[267];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[268] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[268];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[269] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[269];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[26] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[26];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[270] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[270];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[271] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[271];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[272] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[272];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[273] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[273];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[274] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[274];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[275] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[275];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[276] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[276];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[277] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[277];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[278] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[278];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[279] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[279];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[27] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[27];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[280] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[280];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[281] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[281];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[282] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[282];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[283] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[283];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[284] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[284];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[285] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[285];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[286] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[286];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[287] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[287];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[288] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[288];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[289] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[289];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[28] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[28];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[290] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[290];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[291] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[291];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[292] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[292];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[293] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[293];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[294] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[294];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[295] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[295];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[296] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[296];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[297] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[297];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[298] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[298];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[299] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[299];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[29] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[29];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[2] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[2];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[300] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[300];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[301] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[301];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[302] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[302];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[303] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[303];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[304] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[304];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[305] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[305];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[306] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[306];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[307] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[307];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[308] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[308];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[309] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[309];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[30] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[30];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[310] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[310];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[311] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[311];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[312] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[312];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[313] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[313];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[314] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[314];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[315] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[315];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[316] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[316];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[317] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[317];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[318] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[318];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[319] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[319];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[31] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[31];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[320] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[320];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[321] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[321];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[322] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[322];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[323] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[323];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[324] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[324];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[325] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[325];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[326] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[326];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[327] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[327];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[328] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[328];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[329] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[329];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[32] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[32];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[330] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[330];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[331] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[331];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[332] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[332];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[333] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[333];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[334] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[334];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[335] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[335];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[336] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[336];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[337] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[337];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[338] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[338];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[339] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[339];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[33] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[33];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[340] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[340];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[341] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[341];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[342] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[342];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[343] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[343];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[344] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[344];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[345] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[345];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[346] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[346];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[347] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[347];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[348] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[348];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[349] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[349];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[34] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[34];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[350] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[350];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[351] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[351];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[352] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[352];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[353] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[353];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[354] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[354];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[355] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[355];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[356] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[356];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[357] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[357];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[358] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[358];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[359] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[359];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[35] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[35];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[360] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[360];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[361] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[361];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[362] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[362];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[363] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[363];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[364] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[364];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[365] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[365];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[366] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[366];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[367] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[367];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[368] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[368];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[369] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[369];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[36] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[36];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[370] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[370];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[371] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[371];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[372] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[372];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[373] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[373];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[374] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[374];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[375] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[375];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[376] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[376];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[377] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[377];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[378] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[378];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[379] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[379];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[37] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[37];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[380] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[380];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[381] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[381];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[382] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[382];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[383] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[383];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[384] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[384];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[385] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[385];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[386] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[386];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[387] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[387];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[388] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[388];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[389] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[389];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[38] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[38];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[390] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[390];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[391] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[391];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[392] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[392];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[393] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[393];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[394] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[394];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[395] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[395];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[396] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[396];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[397] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[397];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[398] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[398];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[399] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[399];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[39] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[39];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[3] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[3];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[400] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[400];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[401] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[401];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[402] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[402];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[403] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[403];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[404] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[404];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[405] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[405];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[406] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[406];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[407] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[407];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[408] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[408];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[409] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[409];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[40] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[40];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[410] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[410];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[411] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[411];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[412] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[412];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[413] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[413];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[414] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[414];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[415] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[415];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[416] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[416];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[417] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[417];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[418] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[418];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[419] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[419];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[41] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[41];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[420] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[420];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[421] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[421];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[422] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[422];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[423] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[423];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[424] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[424];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[425] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[425];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[426] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[426];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[427] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[427];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[428] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[428];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[429] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[429];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[42] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[42];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[430] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[430];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[431] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[431];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[432] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[432];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[433] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[433];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[434] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[434];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[435] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[435];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[436] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[436];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[437] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[437];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[438] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[438];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[439] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[439];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[43] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[43];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[440] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[440];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[441] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[441];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[442] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[442];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[443] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[443];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[444] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[444];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[445] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[445];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[446] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[446];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[447] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[447];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[448] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[448];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[449] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[449];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[44] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[44];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[450] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[450];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[451] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[451];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[452] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[452];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[453] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[453];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[454] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[454];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[455] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[455];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[456] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[456];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[457] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[457];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[458] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[458];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[459] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[459];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[45] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[45];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[460] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[460];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[461] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[461];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[462] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[462];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[463] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[463];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[464] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[464];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[465] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[465];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[466] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[466];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[467] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[467];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[468] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[468];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[469] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[469];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[46] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[46];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[470] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[470];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[471] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[471];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[472] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[472];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[473] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[473];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[474] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[474];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[475] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[475];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[476] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[476];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[477] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[477];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[478] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[478];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[479] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[479];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[47] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[47];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[480] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[480];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[481] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[481];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[482] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[482];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[483] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[483];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[484] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[484];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[485] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[485];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[486] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[486];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[487] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[487];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[488] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[488];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[489] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[489];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[48] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[48];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[490] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[490];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[491] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[491];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[492] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[492];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[493] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[493];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[494] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[494];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[495] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[495];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[496] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[496];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[497] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[497];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[498] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[498];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[499] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[499];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[49] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[49];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[4] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[4];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[500] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[500];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[501] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[501];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[502] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[502];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[503] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[503];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[504] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[504];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[505] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[505];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[506] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[506];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[507] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[507];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[508] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[508];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[509] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[509];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[50] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[50];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[510] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[510];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[511] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[511];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[512] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[512];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[513] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[513];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[514] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[514];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[515] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[515];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[516] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[516];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[517] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[517];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[518] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[518];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[519] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[519];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[51] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[51];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[520] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[520];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[521] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[521];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[522] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[522];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[523] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[523];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[524] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[524];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[525] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[525];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[526] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[526];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[527] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[527];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[528] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[528];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[529] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[529];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[52] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[52];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[530] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[530];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[531] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[531];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[532] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[532];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[533] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[533];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[534] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[534];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[535] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[535];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[536] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[536];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[537] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[537];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[538] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[538];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[539] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[539];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[53] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[53];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[540] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[540];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[541] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[541];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[542] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[542];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[543] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[543];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[544] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[544];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[545] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[545];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[546] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[546];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[547] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[547];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[548] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[548];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[549] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[549];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[54] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[54];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[550] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[550];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[551] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[551];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[552] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[552];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[553] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[553];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[554] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[554];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[555] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[555];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[556] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[556];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[557] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[557];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[558] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[558];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[559] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[559];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[55] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[55];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[560] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[560];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[561] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[561];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[562] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[562];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[563] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[563];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[564] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[564];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[565] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[565];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[566] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[566];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[567] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[567];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[568] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[568];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[569] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[569];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[56] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[56];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[570] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[570];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[571] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[571];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[572] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[572];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[573] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[573];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[574] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[574];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[575] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[575];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[576] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[576];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[577] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[577];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[578] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[578];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[579] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[579];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[57] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[57];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[580] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[580];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[581] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[581];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[582] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[582];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[583] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[583];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[584] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[584];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[585] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[585];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[586] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[586];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[587] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[587];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[588] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[588];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[589] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[589];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[58] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[58];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[590] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[590];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[591] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[591];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[592] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[592];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[593] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[593];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[594] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[594];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[595] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[595];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[596] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[596];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[597] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[597];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[598] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[598];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[599] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[599];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[59] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[59];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[5] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[5];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[600] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[600];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[601] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[601];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[602] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[602];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[603] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[603];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[604] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[604];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[605] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[605];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[606] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[606];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[607] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[607];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[608] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[608];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[609] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[609];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[60] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[60];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[610] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[610];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[611] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[611];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[612] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[612];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[613] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[613];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[614] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[614];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[615] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[615];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[616] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[616];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[617] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[617];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[618] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[618];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[619] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[619];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[61] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[61];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[620] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[620];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[621] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[621];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[622] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[622];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[623] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[623];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[624] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[624];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[625] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[625];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[626] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[626];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[627] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[627];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[628] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[628];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[629] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[629];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[62] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[62];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[630] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[630];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[631] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[631];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[632] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[632];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[633] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[633];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[634] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[634];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[635] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[635];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[636] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[636];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[637] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[637];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[638] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[638];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[639] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[639];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[63] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[63];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[640] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[640];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[641] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[641];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[642] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[642];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[643] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[643];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[644] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[644];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[645] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[645];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[646] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[646];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[647] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[647];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[648] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[648];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[649] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[649];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[64] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[64];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[650] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[650];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[651] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[651];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[652] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[652];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[653] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[653];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[654] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[654];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[655] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[655];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[656] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[656];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[657] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[657];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[658] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[658];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[659] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[659];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[65] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[65];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[660] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[660];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[661] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[661];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[662] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[662];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[663] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[663];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[664] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[664];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[665] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[665];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[666] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[666];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[667] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[667];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[668] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[668];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[669] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[669];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[66] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[66];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[670] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[670];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[671] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[671];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[672] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[672];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[673] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[673];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[674] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[674];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[675] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[675];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[676] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[676];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[677] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[677];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[678] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[678];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[679] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[679];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[67] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[67];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[680] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[680];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[681] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[681];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[682] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[682];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[683] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[683];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[684] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[684];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[685] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[685];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[686] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[686];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[687] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[687];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[688] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[688];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[689] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[689];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[68] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[68];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[690] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[690];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[691] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[691];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[692] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[692];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[693] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[693];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[694] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[694];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[695] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[695];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[696] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[696];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[697] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[697];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[698] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[698];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[699] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[699];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[69] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[69];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[6] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[6];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[700] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[700];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[701] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[701];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[702] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[702];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[703] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[703];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[70] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[70];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[71] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[71];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[72] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[72];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[73] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[73];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[74] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[74];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[75] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[75];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[76] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[76];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[77] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[77];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[78] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[78];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[79] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[79];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[7] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[7];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[80] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[80];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[81] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[81];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[82] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[82];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[83] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[83];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[84] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[84];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[85] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[85];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[86] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[86];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[87] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[87];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[88] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[88];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[89] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[89];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[8] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[8];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[90] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[90];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[91] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[91];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[92] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[92];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[93] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[93];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[94] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[94];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[95] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[95];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[96] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[96];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[97] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[97];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[98] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[98];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[99] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[99];
	assign x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[9] = x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3[9];
	assign x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_n_l0_ux_1 = x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_n_l0_ux;
	assign x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_p_l0_ux_1 = x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_p_l0_ux;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_in_1 = x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_in;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_out = x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_out_1;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_hsref_left_p_ux_bidir_in_1 = x_std_ipfluxtop_uxtop_wrap_0__ioack_hsref_left_p_ux_bidir_in;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[0] = x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in[0];
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[1] = x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in[1];
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[2] = x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in[2];
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[3] = x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in[3];
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[4] = x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in[4];
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[5] = x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in[5];
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_in_1 = x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_in;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_out = x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_out_1;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_in_1 = x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_in;
	assign x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_out = x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_out_1;
	assign x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_n_l0_ux = x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_n_l0_ux_1;
	assign x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_p_l0_ux = x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_p_l0_ux_1;
	assign x_std_sm_flux_ingress_0__o_ock_pcs_cdrfbclk = x_std_sm_flux_ingress_0__o_ock_pcs_cdrfbclk_1;
	assign x_std_sm_flux_ingress_0__o_ock_pcs_ref = x_std_sm_flux_ingress_0__o_ock_pcs_ref_1;
	assign x_std_sm_flux_ingress_0__o_rst_flux0_cpi_cmn_busy = o_ch3_rst_flux0_cpi_cmn_busy_2;
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[0] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[10] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[11] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[12] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[13] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[14] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[15] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[16] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[17] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[18] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[19] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[1] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[20] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[20];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[21] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[21];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[22] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[22];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[23] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[23];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[24] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[24];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[25] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[25];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[26] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[26];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[27] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[27];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[28] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[28];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[29] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[29];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[2] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[30] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[30];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[31] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[31];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[3] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[4] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[5] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[6] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[7] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[8] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[9] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_valid_1 = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_valid;
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_waitreq_1 = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_waitreq;
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[0] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[10] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[11] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[12] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[13] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[14] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[15] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[16] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[17] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[18] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[19] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[1] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[20] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[20];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[21] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[21];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[22] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[22];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[23] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[23];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[24] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[24];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[25] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[25];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[26] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[26];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[27] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[27];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[28] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[28];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[29] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[29];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[2] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[30] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[30];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[31] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[31];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[3] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[4] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[5] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[6] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[7] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[8] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[9] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_valid_1 = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_valid;
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_waitreq_1 = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_waitreq;
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[0] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[10] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[11] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[12] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[13] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[14] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[15] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[16] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[17] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[18] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[19] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[1] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[20] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[20];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[21] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[21];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[22] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[22];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[23] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[23];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[24] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[24];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[25] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[25];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[26] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[26];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[27] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[27];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[28] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[28];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[29] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[29];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[2] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[30] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[30];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[31] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[31];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[3] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[4] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[5] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[6] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[7] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[8] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[9] = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_valid_1 = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_valid;
	assign x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_waitreq_1 = x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_waitreq;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[10] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[11] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[12] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[13] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[14] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[15] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[16] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[17] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[18] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[19] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[4] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[5] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[6] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[7] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[8] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr[9] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_clk = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_clk_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_read = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_read_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_rstn = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_rstn_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[10] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[11] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[12] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[13] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[14] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[15] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[16] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[17] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[18] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[19] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[20] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[20];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[21] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[21];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[22] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[22];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[23] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[23];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[24] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[24];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[25] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[25];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[26] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[26];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[27] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[27];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[28] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[28];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[29] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[29];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[30] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[30];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[31] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[31];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[4] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[5] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[6] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[7] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[8] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata[9] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_write = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_write_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[10] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[11] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[12] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[13] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[14] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[15] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[16] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[17] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[18] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[19] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[4] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[5] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[6] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[7] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[8] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr[9] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_clk = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_clk_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_read = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_read_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_rstn = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_rstn_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[10] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[11] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[12] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[13] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[14] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[15] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[16] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[17] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[18] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[19] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[20] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[20];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[21] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[21];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[22] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[22];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[23] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[23];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[24] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[24];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[25] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[25];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[26] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[26];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[27] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[27];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[28] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[28];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[29] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[29];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[30] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[30];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[31] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[31];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[4] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[5] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[6] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[7] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[8] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata[9] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_write = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_write_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[10] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[11] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[12] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[13] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[14] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[15] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[16] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[17] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[18] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[19] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[4] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[5] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[6] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[7] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[8] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr[9] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_clk = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_clk_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_read = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_read_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_rstn = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_rstn_1;
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[0] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[0];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[10] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[10];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[11] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[11];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[12] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[12];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[13] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[13];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[14] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[14];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[15] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[15];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[16] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[16];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[17] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[17];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[18] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[18];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[19] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[19];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[1] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[1];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[20] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[20];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[21] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[21];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[22] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[22];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[23] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[23];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[24] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[24];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[25] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[25];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[26] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[26];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[27] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[27];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[28] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[28];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[29] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[29];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[2] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[2];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[30] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[30];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[31] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[31];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[3] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[3];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[4] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[4];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[5] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[5];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[6] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[6];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[7] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[7];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[8] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[8];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata[9] = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[9];
	assign x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_write = x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_write_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_pcs_pclk_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_pcs_pclk;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_asyncpowerchangeack_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_asyncpowerchangeack;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_blockaligncontrol_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_blockaligncontrol;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_cfg_hw_auto_sp_dis_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_cfg_hw_auto_sp_dis;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_dirchange_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_dirchange;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_ebuf_mode_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_ebuf_mode;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_encodedecodebypass_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_encodedecodebypass;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[4] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[5] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_getlocalpresetcoefficients_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_getlocalpresetcoefficients;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_invalidrequest_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_invalidrequest;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[4] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[5] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[4] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lowpin_nt_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lowpin_nt;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[4] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[5] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[6] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[7] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclkchangeack_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclkchangeack;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxelecidle_disable_a_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxelecidle_disable_a;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqclr_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqclr;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqeval_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqeval;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqinprogress_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqinprogress;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqtraining_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqtraining;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpolarity_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpolarity;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxstandby_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxstandby;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxtermination_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxtermination;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_srisenable_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_srisenable;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcmnmode_disable_a_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcmnmode_disable_a;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcompliance_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcompliance;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[10] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[10];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[11] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[11];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[12] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[12];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[13] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[13];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[14] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[14];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[15] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[15];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[16] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[16];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[17] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[17];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[18] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[18];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[19] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[19];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[20] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[20];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[21] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[21];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[22] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[22];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[23] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[23];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[24] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[24];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[25] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[25];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[26] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[26];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[27] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[27];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[28] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[28];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[29] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[29];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[30] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[30];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[31] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[31];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[32] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[32];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[33] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[33];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[34] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[34];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[35] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[35];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[36] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[36];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[37] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[37];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[38] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[38];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[39] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[39];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[4] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[5] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[6] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[7] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[8] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[8];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[9] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata[9];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatavalid_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatavalid;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[10] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[10];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[11] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[11];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[12] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[12];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[13] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[13];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[14] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[14];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[15] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[15];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[16] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[16];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[17] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[17];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[4] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[5] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[6] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[7] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[8] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[8];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[9] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph[9];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdtctrx_lb_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdtctrx_lb;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txelecidle_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txelecidle;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txoneszeros_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txoneszeros;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txstartblock_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txstartblock;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txswing_1 = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txswing;
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[3] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0[0] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0[1] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0[2] = x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_pcs_pclk = x_std_sm_hssi_pcie_pcs_lane_0__o_pcs_pclk_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[6] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit[7] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxcoefficientsvalid = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxcoefficientsvalid_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[10] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[10];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[11] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[11];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[12] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[12];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[13] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[13];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[14] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[14];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[15] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[15];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[16] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[16];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[17] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[17];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[6] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[7] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[8] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[8];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients[9] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[9];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[6] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus[7] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_pclkchangeok = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_pclkchangeok_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_phystatus = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_phystatus_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[10] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[10];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[11] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[11];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[12] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[12];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[13] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[13];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[14] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[14];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[15] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[15];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[16] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[16];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[17] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[17];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[18] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[18];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[19] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[19];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[20] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[20];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[21] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[21];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[22] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[22];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[23] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[23];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[24] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[24];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[25] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[25];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[26] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[26];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[27] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[27];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[28] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[28];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[29] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[29];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[30] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[30];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[31] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[31];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[32] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[32];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[33] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[33];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[34] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[34];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[35] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[35];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[36] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[36];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[37] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[37];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[38] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[38];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[39] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[39];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[4] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[4];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[5] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[5];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[6] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[6];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[7] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[7];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[8] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[8];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata[9] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[9];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatavalid = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatavalid_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxelecidlea = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxelecidlea_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstandbystatus = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstandbystatus_1;
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader[0] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[0];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader[1] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[1];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader[2] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[2];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader[3] = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[3];
	assign x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxvalid = x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxvalid_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_dl_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_dl_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_mux_select_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_mux_select;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_flop_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_flop;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_gen_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_gen_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_trig_flop_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_trig_flop;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_sampling_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_sampling_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_dl_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_dl_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_mux_select_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_mux_select;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_flop_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_flop;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_gen_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_gen_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_trig_flop_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_trig_flop;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_rx_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_rx_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_signal_ok_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_signal_ok;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_tx_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_tx_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_read_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_read;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_rstn_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_rstn;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[21] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[22] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[23] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[24] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[25] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[26] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[27] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[28] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[29] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[30] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[31] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_write_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_write;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_reset_clk_row_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_reset_clk_row;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_rx_clk_in_row_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_rx_clk_in_row_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_tx_clk_in_row_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_tx_clk_in_row_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_rx_pld_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_rx_pld_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_tx_pld_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_tx_pld_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_ready_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_ready;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_pma_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_pma_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_sfrz_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_sfrz;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_tx_pma_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_tx_pma_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_csr_ret_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_csr_ret;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_rx_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_rx_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_tx_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_tx_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_rx_fec_sfrz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_rx_fec_sfrz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_tx_fec_sfrz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_tx_fec_sfrz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_rx_xcvrif_sfrz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_rx_xcvrif_sfrz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_tx_xcvrif_sfrz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_tx_xcvrif_sfrz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_rx_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_rx_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_signal_ok_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_signal_ok;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_tx_rst_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_tx_rst_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_rxdata_fifo_rd_en_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_rxdata_fifo_rd_en;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_2_r03f_rx_mac_srfz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_2_r03f_rx_mac_srfz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_3_c2f_tx_deskew_srfz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_3_c2f_tx_deskew_srfz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[21] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[22] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[23] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[24] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[25] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[26] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[27] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[28] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[29] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[30] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[31] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[32] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[33] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[34] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[35] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[36] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[37] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[38] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[39] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[40] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[41] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[42] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[43] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[44] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[45] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[46] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[47] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[48] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[49] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[50] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[51] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[52] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[53] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[54] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[55] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[56] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[57] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[58] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[59] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[60] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[61] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[62] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[63] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[64] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[65] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[66] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[67] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[68] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[69] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[70] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[71] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[72] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[73] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[74] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[75] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[76] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[77] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[78] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[79] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[21] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[22] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[23] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[24] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[25] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[26] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[27] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[28] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[29] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[30] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[31] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[32] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[33] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[34] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[35] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[36] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[37] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[38] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[39] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[40] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[41] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[42] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[43] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[44] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[45] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[46] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[47] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[48] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[49] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[50] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[51] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[52] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[53] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[54] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[55] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[56] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[57] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[58] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[59] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[60] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[61] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[62] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[63] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[64] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[65] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[66] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[67] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[68] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[69] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[70] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[71] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[72] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[73] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[74] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[75] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[76] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[77] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[78] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[79] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[80] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[80];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[81] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[81];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[82] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[82];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[83] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[83];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[84] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[84];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[85] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[85];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[86] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[86];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[87] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[87];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[88] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[88];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[89] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[89];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[90] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[90];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[91] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[91];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[92] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[92];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[93] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[93];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[94] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[94];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[95] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[95];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[96] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[96];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[97] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[97];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[98] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[98];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[99] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[99];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_fifo_wr_en_1 = x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_fifo_wr_en;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[21] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[22] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[23] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[24] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[25] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[26] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[27] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[28] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[29] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[30] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[31] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[32] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[33] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[34] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[35] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[36] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[37] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[38] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[39] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[40] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[41] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[42] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[43] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[44] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[45] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[46] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[47] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[48] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[49] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[50] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[51] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[52] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[53] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[54] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[55] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[56] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[57] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[58] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[59] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[60] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[61] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[62] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[63] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[64] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[65] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[66] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[67] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[68] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[69] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[70] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[71] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[72] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[73] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[74] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[75] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[76] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[77] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[78] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[79] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[21] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[22] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[23] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[24] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[25] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[26] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[27] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[28] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[29] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[30] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[31] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[32] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[33] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[34] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[35] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[36] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[37] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[38] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[39] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[40] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[41] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[42] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[43] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[44] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[45] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[46] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[47] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[48] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[49] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[50] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[51] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[52] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[53] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[54] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[55] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[56] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[57] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[58] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[59] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[60] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[61] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[62] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[63] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[64] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[65] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[66] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[67] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[68] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[69] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[70] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[71] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[72] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[73] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[74] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[75] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[76] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[77] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[78] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[79] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_direct_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_direct;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_direct_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_direct;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_direct_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_direct;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstepcs_rx_pcs_fully_aligned_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstepcs_rx_pcs_fully_aligned;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstfec_fec_rx_rdy_n_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstfec_fec_rx_rdy_n;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[0] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[10] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[11] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[12] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[13] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[14] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[15] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[16] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[17] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[18] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[19] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[1] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[20] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[21] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[22] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[23] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[24] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[25] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[26] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[27] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[28] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[29] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[2] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[30] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[31] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[32] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[33] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[34] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[35] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[36] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[37] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[38] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[39] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[3] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[40] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[41] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[42] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[43] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[44] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[45] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[46] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[47] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[48] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[49] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[4] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[50] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[51] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[52] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[53] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[54] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[55] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[56] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[57] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[58] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[59] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[5] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[60] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[61] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[62] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[63] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[64] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[65] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[66] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[67] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[68] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[69] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[6] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[70] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[71] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[72] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[73] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[74] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[75] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[76] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[77] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[78] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[79] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[7] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[8] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[9] = x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_tx_fifo_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_tx_fifo_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk1_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk1_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk2_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk2_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk1_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk1_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk2_clk_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk2_clk;
	assign x_std_sm_hssi_pld_chnl_dp_0__i_ux_chnl_refclk_mux_1 = x_std_sm_hssi_pld_chnl_dp_0__i_ux_chnl_refclk_mux;
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel[0] = x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel[1] = x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel[2] = x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel[0] = x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel[1] = x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel[2] = x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel[0] = x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel[1] = x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel[2] = x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel[0] = x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel[1] = x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel[2] = x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_dl_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_dl_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_pulse = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_pulse_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_sample_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_sample_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_sclk_sample_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_sclk_sample_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_trig_sample_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_trig_sample_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_dl_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_dl_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_pulse = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_pulse_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_sample_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_sample_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_sclk_sample_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_sclk_sample_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_trig_sample_sync = x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_trig_sample_sync_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[0] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[10] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[11] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[12] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[13] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[14] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[15] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[16] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[17] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[18] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[19] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[1] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[20] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[21] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[22] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[23] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[24] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[25] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[26] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[27] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[28] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[29] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[2] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[30] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[31] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[3] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[4] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[5] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[6] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[7] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[8] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata[9] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_valid = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_valid_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_waitreq = x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_waitreq_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_flux0_cpi_cmn_busy = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_flux0_cpi_cmn_busy_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_oflux_rx_srds_rdy = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_oflux_rx_srds_rdy_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_all_synthlockstatus = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_all_synthlockstatus_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_rxstatus = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_rxstatus_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_txstatus = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_txstatus_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlock2data = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlock2data_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlockstatus = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlockstatus_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstepcs_rx_pcs_fully_aligned = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstepcs_rx_pcs_fully_aligned_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstfec_fec_rx_rdy_n = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstfec_fec_rx_rdy_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[0] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[10] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[11] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[12] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[13] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[14] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[15] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[16] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[17] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[18] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[19] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[1] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[20] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[21] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[22] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[23] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[24] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[25] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[26] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[27] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[28] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[29] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[2] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[30] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[31] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[32] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[33] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[34] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[35] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[36] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[37] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[38] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[39] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[3] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[40] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[41] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[42] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[43] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[44] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[45] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[46] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[47] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[48] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[49] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[4] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[50] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[51] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[52] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[53] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[54] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[55] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[56] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[57] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[58] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[59] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[5] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[60] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[61] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[62] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[63] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[64] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[65] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[66] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[67] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[68] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[69] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[6] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[70] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[71] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[72] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[73] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[74] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[75] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[76] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[77] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[78] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[79] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[7] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[8] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata[9] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[0] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[10] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[11] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[12] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[13] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[14] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[15] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[16] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[17] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[18] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[19] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[1] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[20] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[21] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[22] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[23] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[24] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[25] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[26] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[27] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[28] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[29] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[2] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[30] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[31] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[32] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[33] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[34] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[35] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[36] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[37] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[38] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[39] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[3] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[40] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[41] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[42] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[43] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[44] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[45] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[46] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[47] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[48] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[49] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[4] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[50] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[51] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[52] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[53] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[54] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[55] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[56] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[57] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[58] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[59] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[5] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[60] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[61] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[62] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[63] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[64] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[65] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[66] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[67] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[68] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[69] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[6] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[70] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[71] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[72] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[73] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[74] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[75] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[76] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[77] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[78] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[79] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[7] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[80] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[80];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[81] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[81];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[82] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[82];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[83] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[83];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[84] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[84];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[85] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[85];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[86] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[86];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[87] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[87];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[88] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[88];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[89] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[89];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[8] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[90] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[90];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[91] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[91];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[92] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[92];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[93] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[93];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[94] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[94];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[95] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[95];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[96] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[96];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[97] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[97];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[98] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[98];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[99] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[99];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async[9] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[0] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[1] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[2] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[3] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[4] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[5] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[6] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[7] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[8] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct[9] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[0] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[1] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[2] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[3] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[4] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[5] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[6] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[7] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[8] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra[9] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_empty = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_empty_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_full = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_full_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pempty = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pempty_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pfull = x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pfull_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_empty = x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_empty_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_full = x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_full_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pempty = x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pempty_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pfull = x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pfull_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk1_clk = x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk1_clk_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk2_clk = x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk2_clk_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk1_clk = x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk1_clk_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk2_clk = x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk2_clk_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_chnl_refclk_mux = x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_chnl_refclk_mux_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_tx_ch_ptr_smpl = x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_tx_ch_ptr_smpl_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[0] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[10] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[11] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[12] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[13] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[14] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[15] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[16] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[17] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[18] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[19] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[1] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[20] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[21] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[22] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[23] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[24] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[25] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[26] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[27] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[28] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[29] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[2] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[30] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[31] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[32] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[33] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[34] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[35] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[36] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[37] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[38] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[39] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[3] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[40] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[41] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[42] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[43] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[44] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[45] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[46] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[47] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[48] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[49] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[4] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[5] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[6] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[7] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[8] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async[9] = x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[9];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_rx_latency_pulse = x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_rx_latency_pulse_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_tx_latency_pulse = x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_tx_latency_pulse_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_rx_rst_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_rx_rst_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_signal_ok = x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_signal_ok_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_tx_rst_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_tx_rst_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async[0] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async[1] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async[2] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async[3] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_direct = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_direct_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[0] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[1] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[2] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[3] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[4] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[5] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async[6] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_direct = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_direct_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[0] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[1] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[2] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[3] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[4] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[5] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[6] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async[7] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_direct = x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_direct_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_rx_pld_rst_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_rx_pld_rst_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_tx_pld_rst_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_tx_pld_rst_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_ready = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_ready_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_csr_ret = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_csr_ret_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_rx_rst_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_rx_rst_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_tx_rst_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_tx_rst_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_rx_fec_sfrz_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_rx_fec_sfrz_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_tx_fec_sfrz_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_tx_fec_sfrz_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_2_r03f_rx_mac_srfz_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_2_r03f_rx_mac_srfz_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_3_c2f_tx_deskew_srfz_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_3_c2f_tx_deskew_srfz_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n = x_std_sm_hssi_pld_chnl_dp_0__o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n_1;
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[0] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[0];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[10] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[10];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[11] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[11];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[12] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[12];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[13] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[13];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[14] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[14];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[15] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[15];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[16] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[16];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[17] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[17];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[18] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[18];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[19] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[19];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[1] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[1];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[20] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[20];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[21] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[21];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[22] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[22];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[23] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[23];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[24] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[24];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[25] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[25];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[26] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[26];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[27] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[27];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[28] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[28];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[29] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[29];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[2] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[2];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[30] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[30];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[31] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[31];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[32] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[32];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[33] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[33];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[34] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[34];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[35] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[35];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[36] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[36];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[37] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[37];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[38] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[38];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[39] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[39];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[3] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[3];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[40] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[40];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[41] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[41];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[42] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[42];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[43] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[43];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[44] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[44];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[45] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[45];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[46] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[46];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[47] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[47];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[48] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[48];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[49] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[49];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[4] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[4];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[50] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[50];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[51] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[51];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[52] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[52];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[53] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[53];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[54] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[54];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[55] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[55];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[56] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[56];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[57] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[57];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[58] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[58];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[59] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[59];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[5] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[5];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[60] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[60];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[61] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[61];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[62] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[62];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[63] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[63];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[64] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[64];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[65] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[65];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[66] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[66];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[67] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[67];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[68] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[68];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[69] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[69];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[6] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[6];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[70] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[70];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[71] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[71];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[72] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[72];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[73] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[73];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[74] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[74];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[75] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[75];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[76] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[76];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[77] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[77];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[78] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[78];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[79] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[79];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[7] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[7];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[8] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[8];
	assign x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data[9] = x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[9];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch0_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch0_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch1_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch1_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[0] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[0];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[10] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[10];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[11] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[11];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[12] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[12];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[13] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[13];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[14] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[14];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[15] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[15];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[16] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[16];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[17] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[17];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[18] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[18];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[19] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[19];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[1] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[1];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[2] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[2];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[3] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[3];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[4] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[4];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[5] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[5];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[6] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[6];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[7] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[7];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[8] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[8];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[9] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr[9];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[0] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[0];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[1] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[1];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[2] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[2];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[3] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_be[3];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_read_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_read;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn;
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[0] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[0];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[10] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[10];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[11] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[11];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[12] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[12];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[13] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[13];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[14] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[14];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[15] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[15];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[16] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[16];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[17] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[17];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[18] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[18];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[19] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[19];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[1] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[1];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[20] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[20];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[21] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[21];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[22] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[22];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[23] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[23];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[24] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[24];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[25] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[25];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[26] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[26];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[27] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[27];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[28] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[28];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[29] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[29];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[2] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[2];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[30] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[30];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[31] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[31];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[3] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[3];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[4] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[4];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[5] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[5];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[6] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[6];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[7] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[7];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[8] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[8];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[9] = x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata[9];
	assign x_std_sm_ux_toolbox_0__i_ch3_lavmm_write_1 = x_std_sm_ux_toolbox_0__i_ch3_lavmm_write;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1;
	assign x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3_1 = x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1;
	assign x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3_1 = x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1;
	assign x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3_1 = x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1;
	assign x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3_1 = x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a;
	assign x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a_1 = x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a;
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[0] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[0];
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[1] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[1];
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[2] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[2];
	assign x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[3] = x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux[3];
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3_1 = x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1;
	assign x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3_1 = x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1;
	assign x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3_1 = x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit;
	assign x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit_1 = x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit;
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[0] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[0];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[10] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[10];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[11] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[11];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[12] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[12];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[13] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[13];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[14] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[14];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[15] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[15];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[16] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[16];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[17] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[17];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[18] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[18];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[19] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[19];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[1] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[1];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[20] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[20];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[21] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[21];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[22] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[22];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[23] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[23];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[24] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[24];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[25] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[25];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[26] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[26];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[27] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[27];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[28] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[28];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[29] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[29];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[2] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[2];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[30] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[30];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[31] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[31];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[3] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[3];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[4] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[4];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[5] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[5];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[6] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[6];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[7] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[7];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[8] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[8];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata[9] = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[9];
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid = x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid_1;
	assign x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq = x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1_1;
	assign x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3 = x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1_1;
	assign x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3 = x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1_1;
	assign x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3 = x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a_1;
	assign x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a = x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a_1;
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[0] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[0];
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[1] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[1];
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[2] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[2];
	assign x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc[3] = x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[3];
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit_1;
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit_1;
	assign x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit = x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit_1;
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[0] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[100] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[101] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[102] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[103] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[104] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[105] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[106] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[107] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[108] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[109] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[10] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[110] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[111] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[112] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[113] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[114] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[115] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[116] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[117] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[118] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[119] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[11] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[120] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[121] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[122] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[123] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[124] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[12] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[13] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[14] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[15] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[16] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[17] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[18] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[19] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[1] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[20] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[21] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[22] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[23] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[24] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[25] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[26] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[27] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[28] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[29] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[2] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[30] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[31] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[32] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[33] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[34] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[35] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[36] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[37] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[38] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[39] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[3] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[40] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[41] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[42] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[43] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[44] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[45] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[46] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[47] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[48] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[49] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[4] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[50] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[51] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[52] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[53] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[54] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[55] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[56] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[57] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[58] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[59] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[5] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[60] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[61] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[62] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[63] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[64] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[65] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[66] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[67] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[68] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[69] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[6] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[70] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[71] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[72] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[73] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[74] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[75] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[76] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[77] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[78] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[79] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[7] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[80] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[81] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[82] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[83] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[84] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[85] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[86] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[87] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[88] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[89] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[8] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[90] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[91] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[92] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[93] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[94] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[95] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[96] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[97] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[98] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[99] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3[9] = x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch0[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch1[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[0] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[1] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[2] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[3] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_common_control_ch3[4] = x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch1_0[9];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[0] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[0];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[100] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[100];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[101] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[101];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[102] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[102];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[103] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[103];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[104] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[104];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[105] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[105];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[106] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[106];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[107] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[107];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[108] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[108];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[109] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[109];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[10] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[10];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[110] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[110];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[111] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[111];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[112] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[112];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[113] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[113];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[114] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[114];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[115] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[115];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[116] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[116];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[117] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[117];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[118] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[118];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[119] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[119];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[11] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[11];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[120] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[120];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[121] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[121];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[122] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[122];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[123] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[123];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[124] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[124];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[125] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[125];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[126] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[126];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[127] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[127];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[128] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[128];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[129] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[129];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[12] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[12];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[130] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[130];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[131] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[131];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[132] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[132];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[133] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[133];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[134] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[134];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[135] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[135];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[136] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[136];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[137] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[137];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[138] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[138];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[139] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[139];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[13] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[13];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[140] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[140];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[141] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[141];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[142] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[142];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[143] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[143];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[144] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[144];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[145] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[145];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[146] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[146];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[147] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[147];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[148] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[148];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[149] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[149];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[14] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[14];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[150] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[150];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[151] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[151];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[152] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[152];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[153] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[153];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[154] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[154];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[155] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[155];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[156] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[156];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[157] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[157];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[158] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[158];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[159] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[159];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[15] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[15];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[160] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[160];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[161] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[161];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[162] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[162];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[163] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[163];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[164] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[164];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[165] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[165];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[166] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[166];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[167] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[167];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[168] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[168];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[169] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[169];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[16] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[16];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[170] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[170];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[171] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[171];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[172] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[172];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[173] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[173];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[174] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[174];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[175] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[175];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[176] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[176];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[177] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[177];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[178] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[178];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[179] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[179];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[17] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[17];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[180] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[180];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[181] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[181];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[182] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[182];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[183] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[183];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[184] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[184];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[185] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[185];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[186] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[186];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[187] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[187];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[188] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[188];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[189] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[189];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[18] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[18];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[190] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[190];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[191] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[191];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[192] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[192];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[193] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[193];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[194] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[194];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[195] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[195];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[196] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[196];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[197] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[197];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[198] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[198];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[199] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[199];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[19] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[19];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[1] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[1];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[200] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[200];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[201] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[201];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[202] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[202];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[203] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[203];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[204] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[204];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[205] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[205];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[206] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[206];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[207] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[207];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[208] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[208];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[209] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[209];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[20] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[20];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[210] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[210];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[211] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[211];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[212] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[212];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[213] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[213];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[214] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[214];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[215] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[215];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[216] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[216];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[217] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[217];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[218] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[218];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[219] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[219];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[21] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[21];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[220] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[220];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[221] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[221];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[222] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[222];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[223] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[223];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[224] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[224];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[225] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[225];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[226] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[226];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[227] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[227];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[228] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[228];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[229] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[229];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[22] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[22];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[230] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[230];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[231] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[231];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[232] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[232];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[233] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[233];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[234] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[234];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[235] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[235];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[236] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[236];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[237] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[237];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[238] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[238];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[239] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[239];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[23] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[23];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[240] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[240];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[241] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[241];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[242] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[242];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[243] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[243];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[244] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[244];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[245] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[245];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[246] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[246];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[247] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[247];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[248] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[248];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[249] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[249];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[24] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[24];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[25] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[25];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[26] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[26];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[27] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[27];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[28] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[28];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[29] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[29];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[2] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[2];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[30] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[30];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[31] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[31];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[32] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[32];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[33] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[33];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[34] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[34];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[35] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[35];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[36] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[36];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[37] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[37];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[38] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[38];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[39] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[39];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[3] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[3];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[40] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[40];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[41] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[41];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[42] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[42];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[43] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[43];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[44] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[44];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[45] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[45];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[46] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[46];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[47] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[47];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[48] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[48];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[49] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[49];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[4] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[4];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[50] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[50];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[51] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[51];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[52] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[52];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[53] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[53];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[54] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[54];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[55] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[55];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[56] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[56];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[57] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[57];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[58] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[58];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[59] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[59];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[5] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[5];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[60] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[60];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[61] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[61];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[62] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[62];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[63] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[63];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[64] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[64];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[65] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[65];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[66] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[66];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[67] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[67];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[68] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[68];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[69] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[69];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[6] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[6];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[70] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[70];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[71] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[71];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[72] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[72];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[73] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[73];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[74] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[74];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[75] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[75];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[76] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[76];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[77] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[77];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[78] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[78];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[79] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[79];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[7] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[7];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[80] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[80];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[81] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[81];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[82] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[82];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[83] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[83];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[84] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[84];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[85] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[85];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[86] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[86];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[87] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[87];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[88] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[88];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[89] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[89];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[8] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[8];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[90] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[90];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[91] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[91];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[92] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[92];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[93] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[93];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[94] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[94];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[95] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[95];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[96] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[96];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[97] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[97];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[98] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[98];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[99] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[99];
	assign x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3[9] = x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[9];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[1];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel[0] = x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[0];
	assign x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel[1] = x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[1];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[0] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[0];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[10] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[10];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[11] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[11];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[12] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[12];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[13] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[13];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[14] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[14];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[15] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[15];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[16] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[16];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[17] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[17];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[18] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[18];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[19] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[19];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[1] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[1];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[20] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[20];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[21] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[21];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[22] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[22];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[23] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[23];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[24] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[24];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[25] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[25];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[26] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[26];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[27] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[27];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[28] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[28];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[29] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[29];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[2] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[2];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[30] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[30];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[31] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[31];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[32] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[32];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[33] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[33];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[34] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[34];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[35] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[35];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[36] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[36];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[37] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[37];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[38] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[38];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[39] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[39];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[3] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[3];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[40] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[40];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[41] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[41];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[42] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[42];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[4] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[4];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[5] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[5];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[6] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[6];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[7] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[7];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[8] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[8];
	assign x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[9] = x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data[9];
	assign x_std_sm_xcvrif_1ch_0__o_ch_xcvrif_rx_fifo_rd_en = o_ch2_xcvrif_rx_fifo_rd_en_0;
	assign x_std_sm_xcvrif_1ch_0__o_ch_xcvrif_tx_fifo_rd_en = o_ch2_xcvrif_tx_fifo_rd_en_0;
	assign x_std_sm_xcvrif_1ch_0__o_pma_rx_sf = x_std_sm_xcvrif_1ch_0__o_pma_rx_sf_1;
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[0] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[0];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[10] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[10];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[11] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[11];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[12] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[12];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[13] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[13];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[14] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[14];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[15] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[15];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[16] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[16];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[17] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[17];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[18] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[18];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[19] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[19];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[1] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[1];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[20] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[20];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[21] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[21];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[22] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[22];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[23] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[23];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[24] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[24];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[25] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[25];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[26] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[26];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[27] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[27];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[28] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[28];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[29] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[29];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[2] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[2];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[30] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[30];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[31] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[31];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[32] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[32];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[33] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[33];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[34] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[34];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[35] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[35];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[36] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[36];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[37] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[37];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[38] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[38];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[39] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[39];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[3] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[3];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[40] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[40];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[41] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[41];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[42] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[42];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[4] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[4];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[5] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[5];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[6] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[6];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[7] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[7];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[8] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[8];
	assign x_std_sm_xcvrif_1ch_0__o_rx_data[9] = x_std_sm_xcvrif_1ch_0__o_rx_data_0[9];
	assign x_std_sm_xcvrif_1ch_0__o_tx_rst_rd_sync_rst_n = o_ch2_tx_rst_rd_sync_rst_n_0;
	assign x_std_sm_xcvrif_1ch_0__o_tx_rst_wr_sync_rst_n = o_ch2_tx_rst_wr_sync_rst_n_0;
	assign x_std_sm_xcvrif_1ch_0__o_tx_source_sel[0] = x_std_sm_xcvrif_1ch_0__o_tx_source_sel_0[0];
	assign x_std_sm_xcvrif_1ch_0__o_tx_source_sel[1] = x_std_sm_xcvrif_1ch_0__o_tx_source_sel_0[1];
	assign x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel[0] = x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0[0];
	assign x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel[1] = x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0[1];
	assign x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel[2] = x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0[2];
	assign xcvrif_tx_esys_clk_mux_u0__o_esys_ch_clk_2 = x_mux_sm_xcvrif_rx_ch_clk_mux_0__i_sys_clk;


	tennm_sm_hssi_eth_lavmm_dec x_std_sm_hssi_eth_lavmm_dec_0 (
		.i_lavmm_addr({ o_ss_ch3_lavmm_ethe_addr_0[19], o_ss_ch3_lavmm_ethe_addr_0[18], o_ss_ch3_lavmm_ethe_addr_0[17], o_ss_ch3_lavmm_ethe_addr_0[16], o_ss_ch3_lavmm_ethe_addr_0[15], o_ss_ch3_lavmm_ethe_addr_0[14], o_ss_ch3_lavmm_ethe_addr_0[13], o_ss_ch3_lavmm_ethe_addr_0[12], o_ss_ch3_lavmm_ethe_addr_0[11], o_ss_ch3_lavmm_ethe_addr_0[10], o_ss_ch3_lavmm_ethe_addr_0[9], o_ss_ch3_lavmm_ethe_addr_0[8], o_ss_ch3_lavmm_ethe_addr_0[7], o_ss_ch3_lavmm_ethe_addr_0[6], o_ss_ch3_lavmm_ethe_addr_0[5], o_ss_ch3_lavmm_ethe_addr_0[4], o_ss_ch3_lavmm_ethe_addr_0[3], o_ss_ch3_lavmm_ethe_addr_0[2], o_ss_ch3_lavmm_ethe_addr_0[1], o_ss_ch3_lavmm_ethe_addr_0[0] }),
		.i_lavmm_be({ o_ss_ch3_lavmm_ethe_be_0[3], o_ss_ch3_lavmm_ethe_be_0[2], o_ss_ch3_lavmm_ethe_be_0[1], o_ss_ch3_lavmm_ethe_be_0[0] }),
		.i_lavmm_clk(o_ss_ch3_lavmm_ethe_clk_0),
		.i_lavmm_deskew_rdata({ x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[31], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[30], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[29], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[28], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[27], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[26], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[25], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[24], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[23], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[22], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[21], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[20], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[19], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[18], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[17], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[16], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[15], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[14], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[13], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[12], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[11], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[10], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[9], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[8], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[7], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[6], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[5], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[4], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[3], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[2], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[1], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_0[0] }),
		.i_lavmm_deskew_rdata_valid(x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_rdata_valid_1),
		.i_lavmm_deskew_waitreq(x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_deskew_waitreq_1),
		.i_lavmm_emac_rdata({ pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1] }),
		.i_lavmm_emac_rdata_valid(pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1]),
		.i_lavmm_emac_waitreq(n2_0),
		.i_lavmm_epcs_rdata({ x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[31], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[30], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[29], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[28], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[27], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[26], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[25], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[24], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[23], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[22], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[21], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[20], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[19], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[18], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[17], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[16], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[15], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[14], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[13], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[12], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[11], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[10], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[9], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[8], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[7], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[6], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[5], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[4], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[3], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[2], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[1], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_0[0] }),
		.i_lavmm_epcs_rdata_valid(x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_rdata_valid_1),
		.i_lavmm_epcs_waitreq(x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_epcs_waitreq_1),
		.i_lavmm_fec_rdata({ x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[31], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[30], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[29], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[28], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[27], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[26], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[25], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[24], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[23], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[22], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[21], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[20], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[19], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[18], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[17], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[16], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[15], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[14], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[13], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[12], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[11], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[10], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[9], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[8], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[7], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[6], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[5], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[4], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[3], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[2], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[1], x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_0[0] }),
		.i_lavmm_fec_rdata_valid(x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_rdata_valid_1),
		.i_lavmm_fec_waitreq(x_std_sm_hssi_eth_lavmm_dec_0__i_lavmm_fec_waitreq_1),
		.i_lavmm_ptp_rdata({ pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1] }),
		.i_lavmm_ptp_rdata_valid(pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1]),
		.i_lavmm_ptp_waitreq(n2_0),
		.i_lavmm_read(o_ss_ch3_lavmm_ethe_read_0),
		.i_lavmm_rstn(o_ss_ch3_lavmm_ethe_rstn_0),
		.i_lavmm_ux_rdata({ o_ch2_lavmm_rdata_1[31], o_ch2_lavmm_rdata_1[30], o_ch2_lavmm_rdata_1[29], o_ch2_lavmm_rdata_1[28], o_ch2_lavmm_rdata_1[27], o_ch2_lavmm_rdata_1[26], o_ch2_lavmm_rdata_1[25], o_ch2_lavmm_rdata_1[24], o_ch2_lavmm_rdata_1[23], o_ch2_lavmm_rdata_1[22], o_ch2_lavmm_rdata_1[21], o_ch2_lavmm_rdata_1[20], o_ch2_lavmm_rdata_1[19], o_ch2_lavmm_rdata_1[18], o_ch2_lavmm_rdata_1[17], o_ch2_lavmm_rdata_1[16], o_ch2_lavmm_rdata_1[15], o_ch2_lavmm_rdata_1[14], o_ch2_lavmm_rdata_1[13], o_ch2_lavmm_rdata_1[12], o_ch2_lavmm_rdata_1[11], o_ch2_lavmm_rdata_1[10], o_ch2_lavmm_rdata_1[9], o_ch2_lavmm_rdata_1[8], o_ch2_lavmm_rdata_1[7], o_ch2_lavmm_rdata_1[6], o_ch2_lavmm_rdata_1[5], o_ch2_lavmm_rdata_1[4], o_ch2_lavmm_rdata_1[3], o_ch2_lavmm_rdata_1[2], o_ch2_lavmm_rdata_1[1], o_ch2_lavmm_rdata_1[0] }),
		.i_lavmm_ux_rdata_valid(o_ch2_lavmm_rdata_valid_1),
		.i_lavmm_ux_waitreq(o_ch2_lavmm_waitreq_1),
		.i_lavmm_wdata({ o_ss_ch3_lavmm_ethe_wdata_0[31], o_ss_ch3_lavmm_ethe_wdata_0[30], o_ss_ch3_lavmm_ethe_wdata_0[29], o_ss_ch3_lavmm_ethe_wdata_0[28], o_ss_ch3_lavmm_ethe_wdata_0[27], o_ss_ch3_lavmm_ethe_wdata_0[26], o_ss_ch3_lavmm_ethe_wdata_0[25], o_ss_ch3_lavmm_ethe_wdata_0[24], o_ss_ch3_lavmm_ethe_wdata_0[23], o_ss_ch3_lavmm_ethe_wdata_0[22], o_ss_ch3_lavmm_ethe_wdata_0[21], o_ss_ch3_lavmm_ethe_wdata_0[20], o_ss_ch3_lavmm_ethe_wdata_0[19], o_ss_ch3_lavmm_ethe_wdata_0[18], o_ss_ch3_lavmm_ethe_wdata_0[17], o_ss_ch3_lavmm_ethe_wdata_0[16], o_ss_ch3_lavmm_ethe_wdata_0[15], o_ss_ch3_lavmm_ethe_wdata_0[14], o_ss_ch3_lavmm_ethe_wdata_0[13], o_ss_ch3_lavmm_ethe_wdata_0[12], o_ss_ch3_lavmm_ethe_wdata_0[11], o_ss_ch3_lavmm_ethe_wdata_0[10], o_ss_ch3_lavmm_ethe_wdata_0[9], o_ss_ch3_lavmm_ethe_wdata_0[8], o_ss_ch3_lavmm_ethe_wdata_0[7], o_ss_ch3_lavmm_ethe_wdata_0[6], o_ss_ch3_lavmm_ethe_wdata_0[5], o_ss_ch3_lavmm_ethe_wdata_0[4], o_ss_ch3_lavmm_ethe_wdata_0[3], o_ss_ch3_lavmm_ethe_wdata_0[2], o_ss_ch3_lavmm_ethe_wdata_0[1], o_ss_ch3_lavmm_ethe_wdata_0[0] }),
		.i_lavmm_write(o_ss_ch3_lavmm_ethe_write_0),
		.i_lavmm_xcvrif_rdata({ o_ch2_lavmm_xcvrif_rdata_0[31], o_ch2_lavmm_xcvrif_rdata_0[30], o_ch2_lavmm_xcvrif_rdata_0[29], o_ch2_lavmm_xcvrif_rdata_0[28], o_ch2_lavmm_xcvrif_rdata_0[27], o_ch2_lavmm_xcvrif_rdata_0[26], o_ch2_lavmm_xcvrif_rdata_0[25], o_ch2_lavmm_xcvrif_rdata_0[24], o_ch2_lavmm_xcvrif_rdata_0[23], o_ch2_lavmm_xcvrif_rdata_0[22], o_ch2_lavmm_xcvrif_rdata_0[21], o_ch2_lavmm_xcvrif_rdata_0[20], o_ch2_lavmm_xcvrif_rdata_0[19], o_ch2_lavmm_xcvrif_rdata_0[18], o_ch2_lavmm_xcvrif_rdata_0[17], o_ch2_lavmm_xcvrif_rdata_0[16], o_ch2_lavmm_xcvrif_rdata_0[15], o_ch2_lavmm_xcvrif_rdata_0[14], o_ch2_lavmm_xcvrif_rdata_0[13], o_ch2_lavmm_xcvrif_rdata_0[12], o_ch2_lavmm_xcvrif_rdata_0[11], o_ch2_lavmm_xcvrif_rdata_0[10], o_ch2_lavmm_xcvrif_rdata_0[9], o_ch2_lavmm_xcvrif_rdata_0[8], o_ch2_lavmm_xcvrif_rdata_0[7], o_ch2_lavmm_xcvrif_rdata_0[6], o_ch2_lavmm_xcvrif_rdata_0[5], o_ch2_lavmm_xcvrif_rdata_0[4], o_ch2_lavmm_xcvrif_rdata_0[3], o_ch2_lavmm_xcvrif_rdata_0[2], o_ch2_lavmm_xcvrif_rdata_0[1], o_ch2_lavmm_xcvrif_rdata_0[0] }),
		.i_lavmm_xcvrif_rdata_valid(o_ch2_lavmm_xcvrif_rdata_valid_0),
		.i_lavmm_xcvrif_waitreq(o_ch2_lavmm_xcvrif_waitreq_0),
		.o_lavmm_deskew_addr({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[19], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[18], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[17], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[16], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[15], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[14], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[13], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[12], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[11], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[10], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[9], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[8], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[7], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[6], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[5], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[4], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_addr_0[0] }),
		.o_lavmm_deskew_be({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_be_0[0] }),
		.o_lavmm_deskew_clk(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_clk_1),
		.o_lavmm_deskew_read(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_read_1),
		.o_lavmm_deskew_rstn(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_rstn_1),
		.o_lavmm_deskew_wdata({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[31], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[30], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[29], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[28], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[27], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[26], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[25], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[24], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[23], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[22], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[21], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[20], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[19], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[18], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[17], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[16], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[15], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[14], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[13], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[12], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[11], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[10], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[9], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[8], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[7], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[6], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[5], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[4], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_wdata_0[0] }),
		.o_lavmm_deskew_write(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_deskew_write_1),
		.o_lavmm_emac_addr({ tmp, tmp_1, tmp_2, tmp_3, tmp_4, tmp_5, tmp_6, tmp_7, tmp_8, tmp_9, tmp_10, tmp_11, tmp_12, tmp_13, tmp_14, tmp_15, tmp_16, tmp_17, tmp_18, tmp_19 }),
		.o_lavmm_emac_be({ tmp_20, tmp_21, tmp_22, tmp_23 }),
		.o_lavmm_emac_clk(tmp_24),
		.o_lavmm_emac_read(tmp_25),
		.o_lavmm_emac_rstn(tmp_26),
		.o_lavmm_emac_wdata({ tmp_27, tmp_28, tmp_29, tmp_30, tmp_31, tmp_32, tmp_33, tmp_34, tmp_35, tmp_36, tmp_37, tmp_38, tmp_39, tmp_40, tmp_41, tmp_42, tmp_43, tmp_44, tmp_45, tmp_46, tmp_47, tmp_48, tmp_49, tmp_50, tmp_51, tmp_52, tmp_53, tmp_54, tmp_55, tmp_56, tmp_57, tmp_58 }),
		.o_lavmm_emac_write(tmp_59),
		.o_lavmm_epcs_addr({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[19], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[18], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[17], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[16], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[15], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[14], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[13], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[12], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[11], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[10], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[9], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[8], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[7], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[6], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[5], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[4], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_addr_0[0] }),
		.o_lavmm_epcs_be({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_be_0[0] }),
		.o_lavmm_epcs_clk(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_clk_1),
		.o_lavmm_epcs_read(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_read_1),
		.o_lavmm_epcs_rstn(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_rstn_1),
		.o_lavmm_epcs_wdata({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[31], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[30], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[29], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[28], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[27], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[26], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[25], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[24], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[23], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[22], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[21], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[20], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[19], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[18], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[17], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[16], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[15], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[14], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[13], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[12], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[11], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[10], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[9], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[8], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[7], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[6], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[5], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[4], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_wdata_0[0] }),
		.o_lavmm_epcs_write(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_epcs_write_1),
		.o_lavmm_fec_addr({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[19], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[18], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[17], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[16], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[15], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[14], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[13], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[12], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[11], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[10], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[9], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[8], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[7], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[6], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[5], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[4], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_addr_0[0] }),
		.o_lavmm_fec_be({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_be_0[0] }),
		.o_lavmm_fec_clk(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_clk_1),
		.o_lavmm_fec_read(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_read_1),
		.o_lavmm_fec_rstn(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_rstn_1),
		.o_lavmm_fec_wdata({ x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[31], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[30], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[29], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[28], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[27], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[26], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[25], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[24], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[23], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[22], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[21], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[20], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[19], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[18], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[17], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[16], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[15], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[14], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[13], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[12], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[11], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[10], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[9], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[8], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[7], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[6], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[5], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[4], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[3], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[2], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[1], x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_wdata_0[0] }),
		.o_lavmm_fec_write(x_std_sm_hssi_eth_lavmm_dec_0__o_lavmm_fec_write_1),
		.o_lavmm_ptp_addr({ tmp_60, tmp_61, tmp_62, tmp_63, tmp_64, tmp_65, tmp_66, tmp_67, tmp_68, tmp_69, tmp_70, tmp_71, tmp_72, tmp_73, tmp_74, tmp_75, tmp_76, tmp_77, tmp_78, tmp_79 }),
		.o_lavmm_ptp_be({ tmp_80, tmp_81, tmp_82, tmp_83 }),
		.o_lavmm_ptp_clk(tmp_84),
		.o_lavmm_ptp_read(tmp_85),
		.o_lavmm_ptp_rstn(tmp_86),
		.o_lavmm_ptp_wdata({ tmp_87, tmp_88, tmp_89, tmp_90, tmp_91, tmp_92, tmp_93, tmp_94, tmp_95, tmp_96, tmp_97, tmp_98, tmp_99, tmp_100, tmp_101, tmp_102, tmp_103, tmp_104, tmp_105, tmp_106, tmp_107, tmp_108, tmp_109, tmp_110, tmp_111, tmp_112, tmp_113, tmp_114, tmp_115, tmp_116, tmp_117, tmp_118 }),
		.o_lavmm_ptp_write(tmp_119),
		.o_lavmm_rdata({ pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[31], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[30], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[29], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[28], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[27], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[26], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[25], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[24], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[23], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[22], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[21], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[20], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[19], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[18], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[17], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[16], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[15], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[14], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[13], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[12], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[11], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[10], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[9], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[8], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[7], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[6], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[5], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[4], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[3], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[2], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[1], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[0] }),
		.o_lavmm_rdata_valid(pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_valid_0),
		.o_lavmm_ux_addr({ o_ch3_lavmm_ux_addr_0[19], o_ch3_lavmm_ux_addr_0[18], o_ch3_lavmm_ux_addr_0[17], o_ch3_lavmm_ux_addr_0[16], o_ch3_lavmm_ux_addr_0[15], o_ch3_lavmm_ux_addr_0[14], o_ch3_lavmm_ux_addr_0[13], o_ch3_lavmm_ux_addr_0[12], o_ch3_lavmm_ux_addr_0[11], o_ch3_lavmm_ux_addr_0[10], o_ch3_lavmm_ux_addr_0[9], o_ch3_lavmm_ux_addr_0[8], o_ch3_lavmm_ux_addr_0[7], o_ch3_lavmm_ux_addr_0[6], o_ch3_lavmm_ux_addr_0[5], o_ch3_lavmm_ux_addr_0[4], o_ch3_lavmm_ux_addr_0[3], o_ch3_lavmm_ux_addr_0[2], o_ch3_lavmm_ux_addr_0[1], o_ch3_lavmm_ux_addr_0[0] }),
		.o_lavmm_ux_be({ o_ch3_lavmm_ux_be_0[3], o_ch3_lavmm_ux_be_0[2], o_ch3_lavmm_ux_be_0[1], o_ch3_lavmm_ux_be_0[0] }),
		.o_lavmm_ux_clk(o_ch3_lavmm_ux_clk_0),
		.o_lavmm_ux_read(o_ch3_lavmm_ux_read_0),
		.o_lavmm_ux_rstn(o_ch3_lavmm_ux_rstn_0),
		.o_lavmm_ux_wdata({ o_ch3_lavmm_ux_wdata_0[31], o_ch3_lavmm_ux_wdata_0[30], o_ch3_lavmm_ux_wdata_0[29], o_ch3_lavmm_ux_wdata_0[28], o_ch3_lavmm_ux_wdata_0[27], o_ch3_lavmm_ux_wdata_0[26], o_ch3_lavmm_ux_wdata_0[25], o_ch3_lavmm_ux_wdata_0[24], o_ch3_lavmm_ux_wdata_0[23], o_ch3_lavmm_ux_wdata_0[22], o_ch3_lavmm_ux_wdata_0[21], o_ch3_lavmm_ux_wdata_0[20], o_ch3_lavmm_ux_wdata_0[19], o_ch3_lavmm_ux_wdata_0[18], o_ch3_lavmm_ux_wdata_0[17], o_ch3_lavmm_ux_wdata_0[16], o_ch3_lavmm_ux_wdata_0[15], o_ch3_lavmm_ux_wdata_0[14], o_ch3_lavmm_ux_wdata_0[13], o_ch3_lavmm_ux_wdata_0[12], o_ch3_lavmm_ux_wdata_0[11], o_ch3_lavmm_ux_wdata_0[10], o_ch3_lavmm_ux_wdata_0[9], o_ch3_lavmm_ux_wdata_0[8], o_ch3_lavmm_ux_wdata_0[7], o_ch3_lavmm_ux_wdata_0[6], o_ch3_lavmm_ux_wdata_0[5], o_ch3_lavmm_ux_wdata_0[4], o_ch3_lavmm_ux_wdata_0[3], o_ch3_lavmm_ux_wdata_0[2], o_ch3_lavmm_ux_wdata_0[1], o_ch3_lavmm_ux_wdata_0[0] }),
		.o_lavmm_ux_write(o_ch3_lavmm_ux_write_0),
		.o_lavmm_waitreq(pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_waitreq_0),
		.o_lavmm_xcvrif_addr({ eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[19], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[18], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[17], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[16], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[15], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[14], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[13], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[12], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[11], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[10], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[9], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[8], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[7], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[6], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[5], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[4], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[3], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[2], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[1], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[0] }),
		.o_lavmm_xcvrif_be({ eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[3], eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[2], eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[1], eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[0] }),
		.o_lavmm_xcvrif_clk(eth_lavmm_dec_u3__o_lavmm_xcvrif_clk_0),
		.o_lavmm_xcvrif_read(eth_lavmm_dec_u3__o_lavmm_xcvrif_read_0),
		.o_lavmm_xcvrif_rstn(eth_lavmm_dec_u3__o_lavmm_xcvrif_rstn_0),
		.o_lavmm_xcvrif_wdata({ eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[31], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[30], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[29], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[28], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[27], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[26], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[25], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[24], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[23], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[22], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[21], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[20], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[19], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[18], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[17], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[16], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[15], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[14], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[13], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[12], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[11], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[10], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[9], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[8], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[7], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[6], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[5], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[4], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[3], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[2], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[1], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[0] }),
		.o_lavmm_xcvrif_write(eth_lavmm_dec_u3__o_lavmm_xcvrif_write_0)
	);

	tennm_sm_hssi_pld_chnl_dp #(
		.dr_enabled(x_std_sm_hssi_pld_chnl_dp_0__dr_enabled),
		.duplex_mode(x_std_sm_hssi_pld_chnl_dp_0__duplex_mode),
		.pld_channel_identifier(x_std_sm_hssi_pld_chnl_dp_0__pld_channel_identifier),
		.rx_clkout1_divider(x_std_sm_hssi_pld_chnl_dp_0__rx_clkout1_divider),
		.rx_clkout2_divider(x_std_sm_hssi_pld_chnl_dp_0__rx_clkout2_divider),
		.rx_en(x_std_sm_hssi_pld_chnl_dp_0__rx_en),
		.rx_fifo_mode(x_std_sm_hssi_pld_chnl_dp_0__rx_fifo_mode),
		.rx_fifo_width(x_std_sm_hssi_pld_chnl_dp_0__rx_fifo_width),
		.rx_fifo_wr_clk_hz(x_std_sm_hssi_pld_chnl_dp_0__rx_fifo_wr_clk_hz),
		.rx_user1_clk_dynamic_mux(x_std_sm_hssi_pld_chnl_dp_0__rx_user1_clk_dynamic_mux),
		.rx_user2_clk_dynamic_mux(x_std_sm_hssi_pld_chnl_dp_0__rx_user2_clk_dynamic_mux),
		.sup_mode(x_std_sm_hssi_pld_chnl_dp_0__sup_mode),
		.tx_clkout1_divider(x_std_sm_hssi_pld_chnl_dp_0__tx_clkout1_divider),
		.tx_clkout2_divider(x_std_sm_hssi_pld_chnl_dp_0__tx_clkout2_divider),
		.tx_en(x_std_sm_hssi_pld_chnl_dp_0__tx_en),
		.tx_fifo_mode(x_std_sm_hssi_pld_chnl_dp_0__tx_fifo_mode),
		.tx_fifo_rd_clk_hz(x_std_sm_hssi_pld_chnl_dp_0__tx_fifo_rd_clk_hz),
		.tx_fifo_width(x_std_sm_hssi_pld_chnl_dp_0__tx_fifo_width),
		.tx_user1_clk_dynamic_mux(x_std_sm_hssi_pld_chnl_dp_0__tx_user1_clk_dynamic_mux),
		.tx_user2_clk_dynamic_mux(x_std_sm_hssi_pld_chnl_dp_0__tx_user2_clk_dynamic_mux),
		.vc_rx_pldif_wm_en(x_std_sm_hssi_pld_chnl_dp_0__vc_rx_pldif_wm_en)
	) x_std_sm_hssi_pld_chnl_dp_0 (
		.i_hio_det_lat_rx_dl_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_dl_clk_1),
		.i_hio_det_lat_rx_mux_select(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_mux_select_1),
		.i_hio_det_lat_rx_sclk_flop(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_flop_1),
		.i_hio_det_lat_rx_sclk_gen_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_sclk_gen_clk_1),
		.i_hio_det_lat_rx_trig_flop(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_rx_trig_flop_1),
		.i_hio_det_lat_sampling_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_sampling_clk_1),
		.i_hio_det_lat_tx_dl_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_dl_clk_1),
		.i_hio_det_lat_tx_mux_select(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_mux_select_1),
		.i_hio_det_lat_tx_sclk_flop(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_flop_1),
		.i_hio_det_lat_tx_sclk_gen_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_sclk_gen_clk_1),
		.i_hio_det_lat_tx_trig_flop(x_std_sm_hssi_pld_chnl_dp_0__i_hio_det_lat_tx_trig_flop_1),
		.i_hio_ehip_rx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_rx_rst_n_1),
		.i_hio_ehip_signal_ok(x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_signal_ok_1),
		.i_hio_ehip_tx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_ehip_tx_rst_n_1),
		.i_hio_lavmm_addr({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_addr_0[0] }),
		.i_hio_lavmm_be({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_be_0[0] }),
		.i_hio_lavmm_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_clk_1),
		.i_hio_lavmm_read(x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_read_1),
		.i_hio_lavmm_rstn(x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_rstn_1),
		.i_hio_lavmm_wdata({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[31], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[30], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[29], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[28], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[27], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[26], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[25], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[24], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[23], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[22], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[21], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_wdata_0[0] }),
		.i_hio_lavmm_write(x_std_sm_hssi_pld_chnl_dp_0__i_hio_lavmm_write_1),
		.i_hio_pld_reset_clk_row(x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_reset_clk_row_1),
		.i_hio_pld_rx_clk_in_row_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_rx_clk_in_row_clk_1),
		.i_hio_pld_tx_clk_in_row_clk(x_std_sm_hssi_pld_chnl_dp_0__i_hio_pld_tx_clk_in_row_clk_1),
		.i_hio_ptp_rst_n(quartus_i_dft_hssi_scan_mode_0),
		.i_hio_rst_pld_adapter_rx_pld_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_rx_pld_rst_n_1),
		.i_hio_rst_pld_adapter_tx_pld_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_adapter_tx_pld_rst_n_1),
		.i_hio_rst_pld_clrhip(quartus_i_dft_hssi_scan_mode_0),
		.i_hio_rst_pld_clrpcs(quartus_i_dft_hssi_scan_mode_0),
		.i_hio_rst_pld_perstn(quartus_i_dft_hssi_scan_mode_0),
		.i_hio_rst_pld_ready(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_pld_ready_1),
		.i_hio_rst_ux_rx_pma_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_pma_rst_n_1),
		.i_hio_rst_ux_rx_sfrz(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_rx_sfrz_1),
		.i_hio_rst_ux_tx_pma_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rst_ux_tx_pma_rst_n_1),
		.i_hio_rstfec_fec_csr_ret(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_csr_ret_1),
		.i_hio_rstfec_fec_rx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_rx_rst_n_1),
		.i_hio_rstfec_fec_tx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_fec_tx_rst_n_1),
		.i_hio_rstfec_rx_fec_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_rx_fec_sfrz_n_1),
		.i_hio_rstfec_tx_fec_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstfec_tx_fec_sfrz_n_1),
		.i_hio_rstxcvrif_rx_xcvrif_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_rx_xcvrif_sfrz_n_1),
		.i_hio_rstxcvrif_tx_xcvrif_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_tx_xcvrif_sfrz_n_1),
		.i_hio_rstxcvrif_xcvrif_rx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_rx_rst_n_1),
		.i_hio_rstxcvrif_xcvrif_signal_ok(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_signal_ok_1),
		.i_hio_rstxcvrif_xcvrif_tx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rstxcvrif_xcvrif_tx_rst_n_1),
		.i_hio_rxdata_fifo_rd_en(x_std_sm_hssi_pld_chnl_dp_0__i_hio_rxdata_fifo_rd_en_1),
		.i_hio_sfreeze_2_r03f_rx_mac_srfz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_2_r03f_rx_mac_srfz_n_1),
		.i_hio_sfreeze_3_c2f_tx_deskew_srfz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_sfreeze_3_c2f_tx_deskew_srfz_n_1),
		.i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__i_hio_t03f_sfreeze_1_tx_pcs_sfrz_n_1),
		.i_hio_txdata({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[79], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[78], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[77], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[76], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[75], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[74], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[73], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[72], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[71], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[70], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[69], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[68], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[67], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[66], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[65], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[64], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[63], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[62], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[61], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[60], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[59], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[58], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[57], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[56], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[55], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[54], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[53], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[52], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[51], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[50], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[49], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[48], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[47], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[46], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[45], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[44], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[43], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[42], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[41], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[40], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[39], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[38], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[37], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[36], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[35], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[34], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[33], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[32], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[31], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[30], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[29], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[28], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[27], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[26], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[25], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[24], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[23], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[22], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[21], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_0[0] }),
		.i_hio_txdata_async({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[99], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[98], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[97], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[96], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[95], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[94], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[93], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[92], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[91], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[90], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[89], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[88], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[87], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[86], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[85], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[84], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[83], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[82], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[81], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[80], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[79], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[78], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[77], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[76], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[75], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[74], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[73], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[72], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[71], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[70], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[69], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[68], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[67], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[66], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[65], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[64], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[63], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[62], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[61], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[60], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[59], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[58], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[57], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[56], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[55], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[54], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[53], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[52], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[51], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[50], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[49], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[48], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[47], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[46], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[45], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[44], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[43], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[42], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[41], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[40], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[39], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[38], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[37], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[36], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[35], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[34], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[33], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[32], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[31], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[30], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[29], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[28], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[27], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[26], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[25], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[24], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[23], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[22], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[21], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_async_0[0] }),
		.i_hio_txdata_direct({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_direct_0[0] }),
		.i_hio_txdata_extra({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_extra_0[0] }),
		.i_hio_txdata_fifo_wr_en(x_std_sm_hssi_pld_chnl_dp_0__i_hio_txdata_fifo_wr_en_1),
		.i_hio_uxquad_async({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[79], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[78], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[77], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[76], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[75], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[74], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[73], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[72], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[71], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[70], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[69], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[68], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[67], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[66], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[65], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[64], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[63], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[62], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[61], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[60], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[59], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[58], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[57], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[56], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[55], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[54], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[53], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[52], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[51], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[50], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[49], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[48], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[47], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[46], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[45], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[44], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[43], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[42], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[41], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[40], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[39], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[38], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[37], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[36], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[35], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[34], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[33], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[32], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[31], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[30], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[29], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[28], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[27], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[26], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[25], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[24], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[23], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[22], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[21], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_0[0] }),
		.i_hio_uxquad_async_pcie_mux({ x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[79], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[78], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[77], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[76], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[75], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[74], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[73], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[72], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[71], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[70], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[69], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[68], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[67], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[66], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[65], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[64], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[63], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[62], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[61], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[60], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[59], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[58], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[57], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[56], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[55], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[54], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[53], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[52], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[51], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[50], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[49], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[48], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[47], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[46], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[45], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[44], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[43], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[42], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[41], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[40], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[39], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[38], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[37], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[36], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[35], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[34], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[33], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[32], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[31], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[30], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[29], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[28], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[27], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[26], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[25], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[24], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[23], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[22], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[21], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_hio_uxquad_async_pcie_mux_0[0] }),
		.i_ss_det_lat_rx_async_pulse(o_ft_eth_rx_async_pulse_ch2_1),
		.i_ss_det_lat_tx_async_pulse(o_ft_eth_tx_async_pulse_ch2_1),
		.i_ss_eth_dkw_rx_async({ x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_async_0[0] }),
		.i_ss_eth_dkw_rx_direct(x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_dkw_rx_direct_1),
		.i_ss_eth_fec_rx_async({ x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_async_0[0] }),
		.i_ss_eth_fec_rx_direct(x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_fec_rx_direct_1),
		.i_ss_eth_mac_rx_async({ pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1], pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1] }),
		.i_ss_eth_mac_rx_direct(pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1]),
		.i_ss_eth_pcs_rx_async({ x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_async_0[0] }),
		.i_ss_eth_pcs_rx_direct(x_std_sm_hssi_pld_chnl_dp_0__i_ss_eth_pcs_rx_direct_1),
		.i_ss_eth_xcvrif_rx_async({ o_ch2_eth_xcvrif_rx_async_1[13], o_ch2_eth_xcvrif_rx_async_1[12], o_ch2_eth_xcvrif_rx_async_1[11], o_ch2_eth_xcvrif_rx_async_1[10], o_ch2_eth_xcvrif_rx_async_1[9], o_ch2_eth_xcvrif_rx_async_1[8], o_ch2_eth_xcvrif_rx_async_1[7], o_ch2_eth_xcvrif_rx_async_1[6], o_ch2_eth_xcvrif_rx_async_1[5], o_ch2_eth_xcvrif_rx_async_1[4], o_ch2_eth_xcvrif_rx_async_1[3], o_ch2_eth_xcvrif_rx_async_1[2], o_ch2_eth_xcvrif_rx_async_1[1], o_ch2_eth_xcvrif_rx_async_1[0] }),
		.i_ss_eth_xcvrif_rx_direct(o_ch2_eth_xcvrif_rx_direct_1),
		.i_ss_lavmm_ethe_rdata({ pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[31], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[30], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[29], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[28], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[27], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[26], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[25], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[24], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[23], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[22], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[21], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[20], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[19], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[18], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[17], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[16], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[15], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[14], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[13], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[12], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[11], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[10], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[9], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[8], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[7], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[6], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[5], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[4], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[3], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[2], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[1], pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_0[0] }),
		.i_ss_lavmm_ethe_rdata_valid(pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_rdata_valid_0),
		.i_ss_lavmm_ethe_waitreq(pld_chnl_dp_wr_u3__i_ss_lavmm_ethe_waitreq_0),
		.i_ss_lavmm_pcie_rdata({ o_ch2_lavmm_pcie_rdata_1[31], o_ch2_lavmm_pcie_rdata_1[30], o_ch2_lavmm_pcie_rdata_1[29], o_ch2_lavmm_pcie_rdata_1[28], o_ch2_lavmm_pcie_rdata_1[27], o_ch2_lavmm_pcie_rdata_1[26], o_ch2_lavmm_pcie_rdata_1[25], o_ch2_lavmm_pcie_rdata_1[24], o_ch2_lavmm_pcie_rdata_1[23], o_ch2_lavmm_pcie_rdata_1[22], o_ch2_lavmm_pcie_rdata_1[21], o_ch2_lavmm_pcie_rdata_1[20], o_ch2_lavmm_pcie_rdata_1[19], o_ch2_lavmm_pcie_rdata_1[18], o_ch2_lavmm_pcie_rdata_1[17], o_ch2_lavmm_pcie_rdata_1[16], o_ch2_lavmm_pcie_rdata_1[15], o_ch2_lavmm_pcie_rdata_1[14], o_ch2_lavmm_pcie_rdata_1[13], o_ch2_lavmm_pcie_rdata_1[12], o_ch2_lavmm_pcie_rdata_1[11], o_ch2_lavmm_pcie_rdata_1[10], o_ch2_lavmm_pcie_rdata_1[9], o_ch2_lavmm_pcie_rdata_1[8], o_ch2_lavmm_pcie_rdata_1[7], o_ch2_lavmm_pcie_rdata_1[6], o_ch2_lavmm_pcie_rdata_1[5], o_ch2_lavmm_pcie_rdata_1[4], o_ch2_lavmm_pcie_rdata_1[3], o_ch2_lavmm_pcie_rdata_1[2], o_ch2_lavmm_pcie_rdata_1[1], o_ch2_lavmm_pcie_rdata_1[0] }),
		.i_ss_lavmm_pcie_rdata_valid(o_ch2_lavmm_pcie_rdata_valid_1),
		.i_ss_lavmm_pcie_waitreq(o_ch2_lavmm_pcie_waitreq_1),
		.i_ss_pcie_ctrl_rx_async({ quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0 }),
		.i_ss_pcie_ctrl_rx_direct({ quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0, quartus_i_dft_hssi_scan_mode_0 }),
		.i_ss_rst_flux0_cpi_cmn_busy(o_ch3_rst_flux0_cpi_cmn_busy_2),
		.i_ss_rst_oflux_rx_srds_rdy(o_ch3_rst_oflux_rx_srds_rdy_2),
		.i_ss_rst_ux_all_synthlockstatus(o_ch3_rst_ux_all_synthlockstatus_2),
		.i_ss_rst_ux_octl_pcs_rxstatus(o_ch3_rst_ux_octl_pcs_rxstatus_2),
		.i_ss_rst_ux_octl_pcs_txstatus(o_ch3_rst_ux_octl_pcs_txstatus_2),
		.i_ss_rst_ux_rxcdrlock2data(o_ch3_rst_ux_rxcdrlock2data_2),
		.i_ss_rst_ux_rxcdrlockstatus(o_ch3_rst_ux_rxcdrlockstatus_2),
		.i_ss_rstepcs_rx_pcs_fully_aligned(x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstepcs_rx_pcs_fully_aligned_1),
		.i_ss_rstfec_fec_rx_rdy_n(x_std_sm_hssi_pld_chnl_dp_0__i_ss_rstfec_fec_rx_rdy_n_1),
		.i_ss_rx_fifo_clk(x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_clk_1),
		.i_ss_rx_fifo_data({ x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[79], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[78], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[77], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[76], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[75], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[74], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[73], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[72], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[71], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[70], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[69], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[68], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[67], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[66], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[65], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[64], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[63], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[62], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[61], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[60], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[59], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[58], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[57], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[56], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[55], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[54], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[53], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[52], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[51], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[50], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[49], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[48], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[47], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[46], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[45], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[44], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[43], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[42], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[41], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[40], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[39], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[38], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[37], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[36], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[35], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[34], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[33], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[32], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[31], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[30], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[29], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[28], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[27], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[26], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[25], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[24], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[23], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[22], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[21], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[20], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[19], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[18], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[17], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[16], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[15], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[14], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[13], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[12], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[11], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[10], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[9], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[8], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[7], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[6], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[5], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[4], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[3], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[2], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[1], x_std_sm_hssi_pld_chnl_dp_0__i_ss_rx_fifo_data_0[0] }),
		.i_ss_tx_fifo_clk(x_std_sm_hssi_pld_chnl_dp_0__i_ss_tx_fifo_clk_1),
		.i_ss_user_rx_clk1_clk(x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk1_clk_1),
		.i_ss_user_rx_clk2_clk(x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_rx_clk2_clk_1),
		.i_ss_user_tx_clk1_clk(x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk1_clk_1),
		.i_ss_user_tx_clk2_clk(x_std_sm_hssi_pld_chnl_dp_0__i_ss_user_tx_clk2_clk_1),
		.i_ss_uxquad_async({ o_ss_async_pldif_ch2_1[49], o_ss_async_pldif_ch2_1[48], o_ss_async_pldif_ch2_1[47], o_ss_async_pldif_ch2_1[46], o_ss_async_pldif_ch2_1[45], o_ss_async_pldif_ch2_1[44], o_ss_async_pldif_ch2_1[43], o_ss_async_pldif_ch2_1[42], o_ss_async_pldif_ch2_1[41], o_ss_async_pldif_ch2_1[40], o_ss_async_pldif_ch2_1[39], o_ss_async_pldif_ch2_1[38], o_ss_async_pldif_ch2_1[37], o_ss_async_pldif_ch2_1[36], o_ss_async_pldif_ch2_1[35], o_ss_async_pldif_ch2_1[34], o_ss_async_pldif_ch2_1[33], o_ss_async_pldif_ch2_1[32], o_ss_async_pldif_ch2_1[31], o_ss_async_pldif_ch2_1[30], o_ss_async_pldif_ch2_1[29], o_ss_async_pldif_ch2_1[28], o_ss_async_pldif_ch2_1[27], o_ss_async_pldif_ch2_1[26], o_ss_async_pldif_ch2_1[25], o_ss_async_pldif_ch2_1[24], o_ss_async_pldif_ch2_1[23], o_ss_async_pldif_ch2_1[22], o_ss_async_pldif_ch2_1[21], o_ss_async_pldif_ch2_1[20], o_ss_async_pldif_ch2_1[19], o_ss_async_pldif_ch2_1[18], o_ss_async_pldif_ch2_1[17], o_ss_async_pldif_ch2_1[16], o_ss_async_pldif_ch2_1[15], o_ss_async_pldif_ch2_1[14], o_ss_async_pldif_ch2_1[13], o_ss_async_pldif_ch2_1[12], o_ss_async_pldif_ch2_1[11], o_ss_async_pldif_ch2_1[10], o_ss_async_pldif_ch2_1[9], o_ss_async_pldif_ch2_1[8], o_ss_async_pldif_ch2_1[7], o_ss_async_pldif_ch2_1[6], o_ss_async_pldif_ch2_1[5], o_ss_async_pldif_ch2_1[4], o_ss_async_pldif_ch2_1[3], o_ss_async_pldif_ch2_1[2], o_ss_async_pldif_ch2_1[1], o_ss_async_pldif_ch2_1[0] }),
		.i_ss_xcvrif_rx_latency_pulse(o_rx_latency_ch2_pulse_0),
		.i_ss_xcvrif_tx_latency_pulse(o_tx_latency_ch2_pulse_0),
		.i_ux_chnl_refclk_mux(x_std_sm_hssi_pld_chnl_dp_0__i_ux_chnl_refclk_mux_1),
		.i_ux_tx_ch_ptr_smpl(quartus_i_dft_hssi_scan_mode_0),
		.k_user_rx_clk1_c0c1c2_sel({ x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0[2], x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0[1], x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk1_c0c1c2_sel_0[0] }),
		.k_user_rx_clk2_c0c1c2_sel({ x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0[2], x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0[1], x_std_sm_hssi_pld_chnl_dp_0__k_user_rx_clk2_c0c1c2_sel_0[0] }),
		.k_user_tx_clk1_c0c1c2_sel({ x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0[2], x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0[1], x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk1_c0c1c2_sel_0[0] }),
		.k_user_tx_clk2_c0c1c2_sel({ x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0[2], x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0[1], x_std_sm_hssi_pld_chnl_dp_0__k_user_tx_clk2_c0c1c2_sel_0[0] }),
		.o_hio_det_lat_rx_async_dl_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_dl_sync_1),
		.o_hio_det_lat_rx_async_pulse(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_pulse_1),
		.o_hio_det_lat_rx_async_sample_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_async_sample_sync_1),
		.o_hio_det_lat_rx_sclk_sample_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_sclk_sample_sync_1),
		.o_hio_det_lat_rx_trig_sample_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_rx_trig_sample_sync_1),
		.o_hio_det_lat_tx_async_dl_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_dl_sync_1),
		.o_hio_det_lat_tx_async_pulse(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_pulse_1),
		.o_hio_det_lat_tx_async_sample_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_async_sample_sync_1),
		.o_hio_det_lat_tx_sclk_sample_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_sclk_sample_sync_1),
		.o_hio_det_lat_tx_trig_sample_sync(x_std_sm_hssi_pld_chnl_dp_0__o_hio_det_lat_tx_trig_sample_sync_1),
		.o_hio_lavmm_rdata({ x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[31], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[30], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[29], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[28], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[27], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[26], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[25], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[24], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[23], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[22], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[21], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[20], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[19], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[18], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[17], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[16], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[15], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[14], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[13], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[12], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[11], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[10], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_0[0] }),
		.o_hio_lavmm_rdata_valid(x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_rdata_valid_1),
		.o_hio_lavmm_waitreq(x_std_sm_hssi_pld_chnl_dp_0__o_hio_lavmm_waitreq_1),
		.o_hio_rst_flux0_cpi_cmn_busy(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_flux0_cpi_cmn_busy_1),
		.o_hio_rst_oflux_rx_srds_rdy(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_oflux_rx_srds_rdy_1),
		.o_hio_rst_ux_all_synthlockstatus(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_all_synthlockstatus_1),
		.o_hio_rst_ux_octl_pcs_rxstatus(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_rxstatus_1),
		.o_hio_rst_ux_octl_pcs_txstatus(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_octl_pcs_txstatus_1),
		.o_hio_rst_ux_rxcdrlock2data(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlock2data_1),
		.o_hio_rst_ux_rxcdrlockstatus(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rst_ux_rxcdrlockstatus_1),
		.o_hio_rstepcs_rx_pcs_fully_aligned(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstepcs_rx_pcs_fully_aligned_1),
		.o_hio_rstfec_fec_rx_rdy_n(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rstfec_fec_rx_rdy_n_1),
		.o_hio_rxdata({ x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[79], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[78], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[77], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[76], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[75], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[74], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[73], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[72], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[71], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[70], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[69], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[68], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[67], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[66], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[65], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[64], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[63], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[62], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[61], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[60], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[59], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[58], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[57], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[56], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[55], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[54], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[53], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[52], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[51], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[50], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[49], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[48], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[47], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[46], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[45], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[44], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[43], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[42], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[41], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[40], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[39], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[38], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[37], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[36], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[35], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[34], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[33], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[32], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[31], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[30], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[29], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[28], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[27], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[26], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[25], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[24], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[23], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[22], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[21], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[20], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[19], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[18], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[17], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[16], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[15], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[14], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[13], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[12], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[11], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[10], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_0[0] }),
		.o_hio_rxdata_async({ x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[99], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[98], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[97], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[96], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[95], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[94], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[93], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[92], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[91], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[90], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[89], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[88], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[87], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[86], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[85], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[84], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[83], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[82], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[81], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[80], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[79], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[78], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[77], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[76], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[75], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[74], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[73], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[72], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[71], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[70], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[69], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[68], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[67], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[66], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[65], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[64], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[63], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[62], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[61], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[60], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[59], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[58], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[57], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[56], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[55], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[54], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[53], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[52], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[51], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[50], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[49], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[48], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[47], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[46], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[45], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[44], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[43], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[42], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[41], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[40], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[39], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[38], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[37], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[36], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[35], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[34], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[33], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[32], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[31], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[30], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[29], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[28], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[27], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[26], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[25], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[24], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[23], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[22], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[21], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[20], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[19], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[18], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[17], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[16], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[15], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[14], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[13], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[12], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[11], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[10], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_async_0[0] }),
		.o_hio_rxdata_direct({ x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_direct_0[0] }),
		.o_hio_rxdata_extra({ x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_extra_0[0] }),
		.o_hio_rxdata_fifo_rd_empty(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_empty_1),
		.o_hio_rxdata_fifo_rd_full(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_full_1),
		.o_hio_rxdata_fifo_rd_pempty(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pempty_1),
		.o_hio_rxdata_fifo_rd_pfull(x_std_sm_hssi_pld_chnl_dp_0__o_hio_rxdata_fifo_rd_pfull_1),
		.o_hio_txdata_fifo_wr_empty(x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_empty_1),
		.o_hio_txdata_fifo_wr_full(x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_full_1),
		.o_hio_txdata_fifo_wr_pempty(x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pempty_1),
		.o_hio_txdata_fifo_wr_pfull(x_std_sm_hssi_pld_chnl_dp_0__o_hio_txdata_fifo_wr_pfull_1),
		.o_hio_user_rx_clk1_clk(x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk1_clk_1),
		.o_hio_user_rx_clk2_clk(x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_rx_clk2_clk_1),
		.o_hio_user_tx_clk1_clk(x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk1_clk_1),
		.o_hio_user_tx_clk2_clk(x_std_sm_hssi_pld_chnl_dp_0__o_hio_user_tx_clk2_clk_1),
		.o_hio_ux_chnl_refclk_mux(x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_chnl_refclk_mux_1),
		.o_hio_ux_tx_ch_ptr_smpl(x_std_sm_hssi_pld_chnl_dp_0__o_hio_ux_tx_ch_ptr_smpl_1),
		.o_hio_uxquad_async({ x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[49], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[48], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[47], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[46], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[45], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[44], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[43], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[42], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[41], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[40], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[39], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[38], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[37], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[36], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[35], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[34], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[33], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[32], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[31], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[30], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[29], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[28], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[27], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[26], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[25], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[24], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[23], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[22], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[21], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[20], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[19], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[18], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[17], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[16], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[15], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[14], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[13], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[12], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[11], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[10], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_hio_uxquad_async_0[0] }),
		.o_hio_xcvrif_rx_latency_pulse(x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_rx_latency_pulse_1),
		.o_hio_xcvrif_tx_latency_pulse(x_std_sm_hssi_pld_chnl_dp_0__o_hio_xcvrif_tx_latency_pulse_1),
		.o_ss_det_lat_rx_sclk_clk(mac_pcs_fec_top_u0__o_ux_sclk_rx_ch2_0),
		.o_ss_det_lat_rx_sclk_sync(mac_pcs_fec_top_u0__o_ft_ux_rx_sclk_sync_ch2_0),
		.o_ss_det_lat_tx_sclk_clk(mac_pcs_fec_top_u0__o_ux_sclk_tx_ch2_0),
		.o_ss_det_lat_tx_sclk_sync(mac_pcs_fec_top_u0__o_ft_ux_tx_sclk_sync_ch2_0),
		.o_ss_ehip_rx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_rx_rst_n_1),
		.o_ss_ehip_signal_ok(x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_signal_ok_1),
		.o_ss_ehip_tx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_ehip_tx_rst_n_1),
		.o_ss_eth_dkw_tx_async({ x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_async_0[0] }),
		.o_ss_eth_dkw_tx_direct(x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_dkw_tx_direct_1),
		.o_ss_eth_fec_tx_async({ x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_async_0[0] }),
		.o_ss_eth_fec_tx_direct(x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_fec_tx_direct_1),
		.o_ss_eth_mac_tx_async({ tmp_120, tmp_121, tmp_122, tmp_123, tmp_124, tmp_125, tmp_126, tmp_127, tmp_128, tmp_129, tmp_130, tmp_131, tmp_132, tmp_133 }),
		.o_ss_eth_mac_tx_direct(tmp_134),
		.o_ss_eth_pcs_tx_async({ x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_async_0[0] }),
		.o_ss_eth_pcs_tx_direct(x_std_sm_hssi_pld_chnl_dp_0__o_ss_eth_pcs_tx_direct_1),
		.o_ss_eth_xcvrif_tx_async({ o_ss_ch3_eth_xcvrif_tx_async_0[6], o_ss_ch3_eth_xcvrif_tx_async_0[5], o_ss_ch3_eth_xcvrif_tx_async_0[4], o_ss_ch3_eth_xcvrif_tx_async_0[3], o_ss_ch3_eth_xcvrif_tx_async_0[2], o_ss_ch3_eth_xcvrif_tx_async_0[1], o_ss_ch3_eth_xcvrif_tx_async_0[0] }),
		.o_ss_eth_xcvrif_tx_direct(o_ss_ch3_eth_xcvrif_tx_direct_0),
		.o_ss_lavmm_ethe_addr({ o_ss_ch3_lavmm_ethe_addr_0[19], o_ss_ch3_lavmm_ethe_addr_0[18], o_ss_ch3_lavmm_ethe_addr_0[17], o_ss_ch3_lavmm_ethe_addr_0[16], o_ss_ch3_lavmm_ethe_addr_0[15], o_ss_ch3_lavmm_ethe_addr_0[14], o_ss_ch3_lavmm_ethe_addr_0[13], o_ss_ch3_lavmm_ethe_addr_0[12], o_ss_ch3_lavmm_ethe_addr_0[11], o_ss_ch3_lavmm_ethe_addr_0[10], o_ss_ch3_lavmm_ethe_addr_0[9], o_ss_ch3_lavmm_ethe_addr_0[8], o_ss_ch3_lavmm_ethe_addr_0[7], o_ss_ch3_lavmm_ethe_addr_0[6], o_ss_ch3_lavmm_ethe_addr_0[5], o_ss_ch3_lavmm_ethe_addr_0[4], o_ss_ch3_lavmm_ethe_addr_0[3], o_ss_ch3_lavmm_ethe_addr_0[2], o_ss_ch3_lavmm_ethe_addr_0[1], o_ss_ch3_lavmm_ethe_addr_0[0] }),
		.o_ss_lavmm_ethe_be({ o_ss_ch3_lavmm_ethe_be_0[3], o_ss_ch3_lavmm_ethe_be_0[2], o_ss_ch3_lavmm_ethe_be_0[1], o_ss_ch3_lavmm_ethe_be_0[0] }),
		.o_ss_lavmm_ethe_clk(o_ss_ch3_lavmm_ethe_clk_0),
		.o_ss_lavmm_ethe_read(o_ss_ch3_lavmm_ethe_read_0),
		.o_ss_lavmm_ethe_rstn(o_ss_ch3_lavmm_ethe_rstn_0),
		.o_ss_lavmm_ethe_wdata({ o_ss_ch3_lavmm_ethe_wdata_0[31], o_ss_ch3_lavmm_ethe_wdata_0[30], o_ss_ch3_lavmm_ethe_wdata_0[29], o_ss_ch3_lavmm_ethe_wdata_0[28], o_ss_ch3_lavmm_ethe_wdata_0[27], o_ss_ch3_lavmm_ethe_wdata_0[26], o_ss_ch3_lavmm_ethe_wdata_0[25], o_ss_ch3_lavmm_ethe_wdata_0[24], o_ss_ch3_lavmm_ethe_wdata_0[23], o_ss_ch3_lavmm_ethe_wdata_0[22], o_ss_ch3_lavmm_ethe_wdata_0[21], o_ss_ch3_lavmm_ethe_wdata_0[20], o_ss_ch3_lavmm_ethe_wdata_0[19], o_ss_ch3_lavmm_ethe_wdata_0[18], o_ss_ch3_lavmm_ethe_wdata_0[17], o_ss_ch3_lavmm_ethe_wdata_0[16], o_ss_ch3_lavmm_ethe_wdata_0[15], o_ss_ch3_lavmm_ethe_wdata_0[14], o_ss_ch3_lavmm_ethe_wdata_0[13], o_ss_ch3_lavmm_ethe_wdata_0[12], o_ss_ch3_lavmm_ethe_wdata_0[11], o_ss_ch3_lavmm_ethe_wdata_0[10], o_ss_ch3_lavmm_ethe_wdata_0[9], o_ss_ch3_lavmm_ethe_wdata_0[8], o_ss_ch3_lavmm_ethe_wdata_0[7], o_ss_ch3_lavmm_ethe_wdata_0[6], o_ss_ch3_lavmm_ethe_wdata_0[5], o_ss_ch3_lavmm_ethe_wdata_0[4], o_ss_ch3_lavmm_ethe_wdata_0[3], o_ss_ch3_lavmm_ethe_wdata_0[2], o_ss_ch3_lavmm_ethe_wdata_0[1], o_ss_ch3_lavmm_ethe_wdata_0[0] }),
		.o_ss_lavmm_ethe_write(o_ss_ch3_lavmm_ethe_write_0),
		.o_ss_lavmm_pcie_addr({ o_ss_ch3_lavmm_pcie_addr_0[16], o_ss_ch3_lavmm_pcie_addr_0[15], o_ss_ch3_lavmm_pcie_addr_0[14], o_ss_ch3_lavmm_pcie_addr_0[13], o_ss_ch3_lavmm_pcie_addr_0[12], o_ss_ch3_lavmm_pcie_addr_0[11], o_ss_ch3_lavmm_pcie_addr_0[10], o_ss_ch3_lavmm_pcie_addr_0[9], o_ss_ch3_lavmm_pcie_addr_0[8], o_ss_ch3_lavmm_pcie_addr_0[7], o_ss_ch3_lavmm_pcie_addr_0[6], o_ss_ch3_lavmm_pcie_addr_0[5], o_ss_ch3_lavmm_pcie_addr_0[4], o_ss_ch3_lavmm_pcie_addr_0[3], o_ss_ch3_lavmm_pcie_addr_0[2], o_ss_ch3_lavmm_pcie_addr_0[1], o_ss_ch3_lavmm_pcie_addr_0[0] }),
		.o_ss_lavmm_pcie_be({ o_ss_ch3_lavmm_pcie_be_0[3], o_ss_ch3_lavmm_pcie_be_0[2], o_ss_ch3_lavmm_pcie_be_0[1], o_ss_ch3_lavmm_pcie_be_0[0] }),
		.o_ss_lavmm_pcie_clk(o_ss_ch3_lavmm_pcie_clk_0),
		.o_ss_lavmm_pcie_read(o_ss_ch3_lavmm_pcie_read_0),
		.o_ss_lavmm_pcie_rstn(o_ss_ch3_lavmm_pcie_rstn_0),
		.o_ss_lavmm_pcie_wdata({ o_ss_ch3_lavmm_pcie_wdata_0[31], o_ss_ch3_lavmm_pcie_wdata_0[30], o_ss_ch3_lavmm_pcie_wdata_0[29], o_ss_ch3_lavmm_pcie_wdata_0[28], o_ss_ch3_lavmm_pcie_wdata_0[27], o_ss_ch3_lavmm_pcie_wdata_0[26], o_ss_ch3_lavmm_pcie_wdata_0[25], o_ss_ch3_lavmm_pcie_wdata_0[24], o_ss_ch3_lavmm_pcie_wdata_0[23], o_ss_ch3_lavmm_pcie_wdata_0[22], o_ss_ch3_lavmm_pcie_wdata_0[21], o_ss_ch3_lavmm_pcie_wdata_0[20], o_ss_ch3_lavmm_pcie_wdata_0[19], o_ss_ch3_lavmm_pcie_wdata_0[18], o_ss_ch3_lavmm_pcie_wdata_0[17], o_ss_ch3_lavmm_pcie_wdata_0[16], o_ss_ch3_lavmm_pcie_wdata_0[15], o_ss_ch3_lavmm_pcie_wdata_0[14], o_ss_ch3_lavmm_pcie_wdata_0[13], o_ss_ch3_lavmm_pcie_wdata_0[12], o_ss_ch3_lavmm_pcie_wdata_0[11], o_ss_ch3_lavmm_pcie_wdata_0[10], o_ss_ch3_lavmm_pcie_wdata_0[9], o_ss_ch3_lavmm_pcie_wdata_0[8], o_ss_ch3_lavmm_pcie_wdata_0[7], o_ss_ch3_lavmm_pcie_wdata_0[6], o_ss_ch3_lavmm_pcie_wdata_0[5], o_ss_ch3_lavmm_pcie_wdata_0[4], o_ss_ch3_lavmm_pcie_wdata_0[3], o_ss_ch3_lavmm_pcie_wdata_0[2], o_ss_ch3_lavmm_pcie_wdata_0[1], o_ss_ch3_lavmm_pcie_wdata_0[0] }),
		.o_ss_lavmm_pcie_write(o_ss_ch3_lavmm_pcie_write_0),
		.o_ss_pcie_ctrl_tx_async({ tmp_135, tmp_136, tmp_137, tmp_138, tmp_139, tmp_140, tmp_141, tmp_142, tmp_143, tmp_144, tmp_145, tmp_146, tmp_147, tmp_148, tmp_149, tmp_150, tmp_151, tmp_152, tmp_153, tmp_154, tmp_155, tmp_156, tmp_157, tmp_158, tmp_159, tmp_160, tmp_161, tmp_162, tmp_163, tmp_164, tmp_165, tmp_166, tmp_167, tmp_168, tmp_169, tmp_170, tmp_171, tmp_172, tmp_173, tmp_174, tmp_175, tmp_176, tmp_177, tmp_178, tmp_179, tmp_180, tmp_181, tmp_182, tmp_183, tmp_184, tmp_185, tmp_186, tmp_187, tmp_188, tmp_189, tmp_190, tmp_191, tmp_192, tmp_193, tmp_194, tmp_195, tmp_196, tmp_197, tmp_198, tmp_199, tmp_200, tmp_201, tmp_202, tmp_203, tmp_204, tmp_205, tmp_206, tmp_207, tmp_208, tmp_209, tmp_210, tmp_211, tmp_212, tmp_213, tmp_214, tmp_215, tmp_216, tmp_217, tmp_218, tmp_219, tmp_220, tmp_221, tmp_222 }),
		.o_ss_pcie_ctrl_tx_direct({ tmp_223, tmp_224, tmp_225, tmp_226, tmp_227, tmp_228, tmp_229, tmp_230 }),
		.o_ss_pcie_rst_pld_clrhip(tmp_231),
		.o_ss_pcie_rst_pld_clrpcs(tmp_232),
		.o_ss_pcie_rst_pld_perstn(tmp_233),
		.o_ss_ptp_rst_n(tmp_234),
		.o_ss_rst_pld_adapter_deskew_rx_pld_rst_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_rx_pld_rst_n_1),
		.o_ss_rst_pld_adapter_deskew_tx_pld_rst_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_adapter_deskew_tx_pld_rst_n_1),
		.o_ss_rst_pld_ready(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rst_pld_ready_1),
		.o_ss_rst_ux_rx_pma_rst_n(pcie_top_x4_u0__o_ft_ch3_rst_ux_rx_pma_rst_n_0),
		.o_ss_rst_ux_rx_sfrz(pcie_top_x4_u0__o_ft_ch3_rst_ux_rx_sfrz_0),
		.o_ss_rst_ux_tx_pma_rst_n(pcie_top_x4_u0__o_ft_ch3_rst_ux_tx_pma_rst_n_0),
		.o_ss_rstfec_fec_csr_ret(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_csr_ret_1),
		.o_ss_rstfec_fec_rx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_rx_rst_n_1),
		.o_ss_rstfec_fec_tx_rst_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_fec_tx_rst_n_1),
		.o_ss_rstfec_rx_fec_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_rx_fec_sfrz_n_1),
		.o_ss_rstfec_tx_fec_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_rstfec_tx_fec_sfrz_n_1),
		.o_ss_rstxcvrif_rx_xcvrif_sfrz_n(o_ss_ch3_rstxcvrif_rx_reset_sfreeze_xcvrif_0),
		.o_ss_rstxcvrif_tx_xcvrif_sfrz_n(o_ss_ch3_rstxcvrif_tx_reset_sfreeze_xcvrif_0),
		.o_ss_rstxcvrif_xcvrif_rx_rst_n(o_ss_ch3_rstxcvrif_e4_lphy_rx_rst_n_0),
		.o_ss_rstxcvrif_xcvrif_signal_ok(o_ss_ch3_rstxcvrif_lphy_signal_ok_0),
		.o_ss_rstxcvrif_xcvrif_tx_rst_n(o_ch2_rstxcvrif_tx_rst_n_0),
		.o_ss_sfreeze_2_r03f_rx_mac_srfz_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_2_r03f_rx_mac_srfz_n_1),
		.o_ss_sfreeze_3_c2f_tx_deskew_srfz_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_sfreeze_3_c2f_tx_deskew_srfz_n_1),
		.o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n(x_std_sm_hssi_pld_chnl_dp_0__o_ss_t03f_sfreeze_1_tx_pcs_sfrz_n_1),
		.o_ss_tx_fifo_data({ x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[79], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[78], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[77], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[76], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[75], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[74], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[73], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[72], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[71], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[70], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[69], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[68], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[67], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[66], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[65], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[64], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[63], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[62], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[61], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[60], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[59], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[58], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[57], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[56], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[55], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[54], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[53], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[52], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[51], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[50], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[49], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[48], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[47], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[46], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[45], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[44], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[43], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[42], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[41], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[40], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[39], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[38], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[37], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[36], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[35], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[34], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[33], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[32], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[31], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[30], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[29], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[28], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[27], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[26], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[25], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[24], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[23], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[22], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[21], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[20], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[19], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[18], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[17], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[16], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[15], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[14], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[13], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[12], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[11], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[10], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[9], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[8], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[7], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[6], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[5], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[4], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[3], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[2], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[1], x_std_sm_hssi_pld_chnl_dp_0__o_ss_tx_fifo_data_0[0] }),
		.o_ss_uxquad_async({ ux_quad_u0__i_ss_async_pldif_ch2_0[79], ux_quad_u0__i_ss_async_pldif_ch2_0[78], ux_quad_u0__i_ss_async_pldif_ch2_0[77], ux_quad_u0__i_ss_async_pldif_ch2_0[76], ux_quad_u0__i_ss_async_pldif_ch2_0[75], ux_quad_u0__i_ss_async_pldif_ch2_0[74], ux_quad_u0__i_ss_async_pldif_ch2_0[73], ux_quad_u0__i_ss_async_pldif_ch2_0[72], ux_quad_u0__i_ss_async_pldif_ch2_0[71], ux_quad_u0__i_ss_async_pldif_ch2_0[70], ux_quad_u0__i_ss_async_pldif_ch2_0[69], ux_quad_u0__i_ss_async_pldif_ch2_0[68], ux_quad_u0__i_ss_async_pldif_ch2_0[67], ux_quad_u0__i_ss_async_pldif_ch2_0[66], ux_quad_u0__i_ss_async_pldif_ch2_0[65], ux_quad_u0__i_ss_async_pldif_ch2_0[64], ux_quad_u0__i_ss_async_pldif_ch2_0[63], ux_quad_u0__i_ss_async_pldif_ch2_0[62], ux_quad_u0__i_ss_async_pldif_ch2_0[61], ux_quad_u0__i_ss_async_pldif_ch2_0[60], ux_quad_u0__i_ss_async_pldif_ch2_0[59], ux_quad_u0__i_ss_async_pldif_ch2_0[58], ux_quad_u0__i_ss_async_pldif_ch2_0[57], ux_quad_u0__i_ss_async_pldif_ch2_0[56], ux_quad_u0__i_ss_async_pldif_ch2_0[55], ux_quad_u0__i_ss_async_pldif_ch2_0[54], ux_quad_u0__i_ss_async_pldif_ch2_0[53], ux_quad_u0__i_ss_async_pldif_ch2_0[52], ux_quad_u0__i_ss_async_pldif_ch2_0[51], ux_quad_u0__i_ss_async_pldif_ch2_0[50], ux_quad_u0__i_ss_async_pldif_ch2_0[49], ux_quad_u0__i_ss_async_pldif_ch2_0[48], ux_quad_u0__i_ss_async_pldif_ch2_0[47], ux_quad_u0__i_ss_async_pldif_ch2_0[46], ux_quad_u0__i_ss_async_pldif_ch2_0[45], ux_quad_u0__i_ss_async_pldif_ch2_0[44], ux_quad_u0__i_ss_async_pldif_ch2_0[43], ux_quad_u0__i_ss_async_pldif_ch2_0[42], ux_quad_u0__i_ss_async_pldif_ch2_0[41], ux_quad_u0__i_ss_async_pldif_ch2_0[40], ux_quad_u0__i_ss_async_pldif_ch2_0[39], ux_quad_u0__i_ss_async_pldif_ch2_0[38], ux_quad_u0__i_ss_async_pldif_ch2_0[37], ux_quad_u0__i_ss_async_pldif_ch2_0[36], ux_quad_u0__i_ss_async_pldif_ch2_0[35], ux_quad_u0__i_ss_async_pldif_ch2_0[34], ux_quad_u0__i_ss_async_pldif_ch2_0[33], ux_quad_u0__i_ss_async_pldif_ch2_0[32], ux_quad_u0__i_ss_async_pldif_ch2_0[31], ux_quad_u0__i_ss_async_pldif_ch2_0[30], ux_quad_u0__i_ss_async_pldif_ch2_0[29], ux_quad_u0__i_ss_async_pldif_ch2_0[28], ux_quad_u0__i_ss_async_pldif_ch2_0[27], ux_quad_u0__i_ss_async_pldif_ch2_0[26], ux_quad_u0__i_ss_async_pldif_ch2_0[25], ux_quad_u0__i_ss_async_pldif_ch2_0[24], ux_quad_u0__i_ss_async_pldif_ch2_0[23], ux_quad_u0__i_ss_async_pldif_ch2_0[22], ux_quad_u0__i_ss_async_pldif_ch2_0[21], ux_quad_u0__i_ss_async_pldif_ch2_0[20], ux_quad_u0__i_ss_async_pldif_ch2_0[19], ux_quad_u0__i_ss_async_pldif_ch2_0[18], ux_quad_u0__i_ss_async_pldif_ch2_0[17], ux_quad_u0__i_ss_async_pldif_ch2_0[16], ux_quad_u0__i_ss_async_pldif_ch2_0[15], ux_quad_u0__i_ss_async_pldif_ch2_0[14], ux_quad_u0__i_ss_async_pldif_ch2_0[13], ux_quad_u0__i_ss_async_pldif_ch2_0[12], ux_quad_u0__i_ss_async_pldif_ch2_0[11], ux_quad_u0__i_ss_async_pldif_ch2_0[10], ux_quad_u0__i_ss_async_pldif_ch2_0[9], ux_quad_u0__i_ss_async_pldif_ch2_0[8], ux_quad_u0__i_ss_async_pldif_ch2_0[7], ux_quad_u0__i_ss_async_pldif_ch2_0[6], ux_quad_u0__i_ss_async_pldif_ch2_0[5], ux_quad_u0__i_ss_async_pldif_ch2_0[4], ux_quad_u0__i_ss_async_pldif_ch2_0[3], ux_quad_u0__i_ss_async_pldif_ch2_0[2], ux_quad_u0__i_ss_async_pldif_ch2_0[1], ux_quad_u0__i_ss_async_pldif_ch2_0[0] }),
		.o_ss_uxquad_async_pcie_mux({ ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[79], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[78], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[77], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[76], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[75], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[74], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[73], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[72], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[71], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[70], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[69], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[68], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[67], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[66], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[65], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[64], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[63], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[62], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[61], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[60], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[59], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[58], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[57], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[56], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[55], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[54], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[53], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[52], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[51], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[50], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[49], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[48], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[47], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[46], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[45], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[44], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[43], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[42], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[41], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[40], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[39], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[38], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[37], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[36], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[35], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[34], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[33], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[32], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[31], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[30], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[29], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[28], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[27], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[26], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[25], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[24], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[23], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[22], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[21], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[20], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[19], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[18], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[17], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[16], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[15], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[14], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[13], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[12], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[11], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[10], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[9], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[8], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[7], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[6], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[5], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[4], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[3], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[2], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[1], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[0] })
	);

	tennm_sm_xcvrif_1ch #(
		.dr_enabled(x_std_sm_xcvrif_1ch_0__dr_enabled),
		.duplex_mode(x_std_sm_xcvrif_1ch_0__duplex_mode),
		.eth_rx_clk_hz(x_std_sm_xcvrif_1ch_0__eth_rx_clk_hz),
		.eth_tx_clk_hz(x_std_sm_xcvrif_1ch_0__eth_tx_clk_hz),
		.loopback_mode(x_std_sm_xcvrif_1ch_0__loopback_mode),
		.rx_bond_size(x_std_sm_xcvrif_1ch_0__rx_bond_size),
		.rx_bonding_mode(x_std_sm_xcvrif_1ch_0__rx_bonding_mode),
		.rx_dl_enable(x_std_sm_xcvrif_1ch_0__rx_dl_enable),
		.rx_en(x_std_sm_xcvrif_1ch_0__rx_en),
		.rx_fifo_mode(x_std_sm_xcvrif_1ch_0__rx_fifo_mode),
		.rx_fifo_rd_en_dynamic_mux(x_std_sm_xcvrif_1ch_0__rx_fifo_rd_en_dynamic_mux),
		.rx_gb_width(x_std_sm_xcvrif_1ch_0__rx_gb_width),
		.rx_word_clk_dynamic_mux(x_std_sm_xcvrif_1ch_0__rx_word_clk_dynamic_mux),
		.sim_mode(x_std_sm_xcvrif_1ch_0__sim_mode),
		.sup_mode(x_std_sm_xcvrif_1ch_0__sup_mode),
		.tx_bond_size(x_std_sm_xcvrif_1ch_0__tx_bond_size),
		.tx_bonding_mode(x_std_sm_xcvrif_1ch_0__tx_bonding_mode),
		.tx_dl_enable(x_std_sm_xcvrif_1ch_0__tx_dl_enable),
		.tx_dynamic_mux(x_std_sm_xcvrif_1ch_0__tx_dynamic_mux),
		.tx_en(x_std_sm_xcvrif_1ch_0__tx_en),
		.tx_fifo_mode(x_std_sm_xcvrif_1ch_0__tx_fifo_mode),
		.tx_fifo_rd_en_dynamic_mux(x_std_sm_xcvrif_1ch_0__tx_fifo_rd_en_dynamic_mux),
		.tx_gb_width(x_std_sm_xcvrif_1ch_0__tx_gb_width),
		.tx_rst_dynamic_mux(x_std_sm_xcvrif_1ch_0__tx_rst_dynamic_mux),
		.tx_word_clk_dynamic_mux(x_std_sm_xcvrif_1ch_0__tx_word_clk_dynamic_mux),
		.xcvr_rxword_clk_hz(x_std_sm_xcvrif_1ch_0__xcvr_rxword_clk_hz),
		.xcvr_txword_clk_hz(x_std_sm_xcvrif_1ch_0__xcvr_txword_clk_hz)
	) x_std_sm_xcvrif_1ch_0 (
		.i_ch_eth_xcvrif_tx_async({ o_ss_ch3_eth_xcvrif_tx_async_0[6], o_ss_ch3_eth_xcvrif_tx_async_0[5], o_ss_ch3_eth_xcvrif_tx_async_0[4], o_ss_ch3_eth_xcvrif_tx_async_0[3], o_ss_ch3_eth_xcvrif_tx_async_0[2], o_ss_ch3_eth_xcvrif_tx_async_0[1], o_ss_ch3_eth_xcvrif_tx_async_0[0] }),
		.i_ch_eth_xcvrif_tx_direct(o_ss_ch3_eth_xcvrif_tx_direct_0),
		.i_ch_lavmm_xcvrif_addr({ eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[19], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[18], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[17], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[16], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[15], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[14], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[13], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[12], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[11], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[10], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[9], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[8], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[7], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[6], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[5], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[4], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[3], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[2], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[1], eth_lavmm_dec_u3__o_lavmm_xcvrif_addr_0[0] }),
		.i_ch_lavmm_xcvrif_be({ eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[3], eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[2], eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[1], eth_lavmm_dec_u3__o_lavmm_xcvrif_be_0[0] }),
		.i_ch_lavmm_xcvrif_clk(eth_lavmm_dec_u3__o_lavmm_xcvrif_clk_0),
		.i_ch_lavmm_xcvrif_read(eth_lavmm_dec_u3__o_lavmm_xcvrif_read_0),
		.i_ch_lavmm_xcvrif_rstn(eth_lavmm_dec_u3__o_lavmm_xcvrif_rstn_0),
		.i_ch_lavmm_xcvrif_wdata({ eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[31], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[30], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[29], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[28], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[27], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[26], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[25], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[24], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[23], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[22], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[21], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[20], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[19], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[18], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[17], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[16], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[15], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[14], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[13], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[12], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[11], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[10], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[9], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[8], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[7], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[6], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[5], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[4], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[3], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[2], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[1], eth_lavmm_dec_u3__o_lavmm_xcvrif_wdata_0[0] }),
		.i_ch_lavmm_xcvrif_write(eth_lavmm_dec_u3__o_lavmm_xcvrif_write_0),
		.i_ch_xcvrif_rx_fifo_rd_en(o_ch_xcvrif_rx_fifo_rd_en_2),
		.i_ch_xcvrif_tx_fifo_rd_en(o_ch_xcvrif_tx_fifo_rd_en_2),
		.i_eth_rx_ch_clk(o_eth_rx_ch2_clk_4),
		.i_eth_tx_ch_clk(o_eth_tx_ch2_clk_4),
		.i_pld_rx_lat_sclk_ch(mac_pcs_fec_top_u0__o_ux_sclk_rx_ch2_0),
		.i_pld_tx_lat_sclk_ch(mac_pcs_fec_top_u0__o_ux_sclk_tx_ch2_0),
		.i_rstxcvrif_rx_xcvrif_sfrz_n(o_ss_ch3_rstxcvrif_rx_reset_sfreeze_xcvrif_0),
		.i_rstxcvrif_tx_xcvrif_sfrz_n(o_ss_ch3_rstxcvrif_tx_reset_sfreeze_xcvrif_0),
		.i_rstxcvrif_xcvrif_rx_rst_n(o_ss_ch3_rstxcvrif_e4_lphy_rx_rst_n_0),
		.i_rstxcvrif_xcvrif_signal_ok(o_ss_ch3_rstxcvrif_lphy_signal_ok_0),
		.i_rstxcvrif_xcvrif_tx_rd_rst_n(xcvrif_tx_rd_rst_mux_u2__o_ch_xcvrif_tx_rst_n_0),
		.i_rstxcvrif_xcvrif_tx_rst_n(o_ch2_rstxcvrif_tx_rst_n_0),
		.i_rstxcvrif_xcvrif_tx_wr_rst_n(xcvrif_tx_rst_mux_u2__o_ch_xcvrif_tx_rst_n_0),
		.i_rx_dl_bit(o_rx_dl_ch2_bit_1),
		.i_ux_rx_ch_data({ o_eth_rx_data_2[31], o_eth_rx_data_2[30], o_eth_rx_data_2[29], o_eth_rx_data_2[28], o_eth_rx_data_2[27], o_eth_rx_data_2[26], o_eth_rx_data_2[25], o_eth_rx_data_2[24], o_eth_rx_data_2[23], o_eth_rx_data_2[22], o_eth_rx_data_2[21], o_eth_rx_data_2[20], o_eth_rx_data_2[19], o_eth_rx_data_2[18], o_eth_rx_data_2[17], o_eth_rx_data_2[16], o_eth_rx_data_2[15], o_eth_rx_data_2[14], o_eth_rx_data_2[13], o_eth_rx_data_2[12], o_eth_rx_data_2[11], o_eth_rx_data_2[10], o_eth_rx_data_2[9], o_eth_rx_data_2[8], o_eth_rx_data_2[7], o_eth_rx_data_2[6], o_eth_rx_data_2[5], o_eth_rx_data_2[4], o_eth_rx_data_2[3], o_eth_rx_data_2[2], o_eth_rx_data_2[1], o_eth_rx_data_2[0] }),
		.i_xcvr_rx_ch_clk(o_xcvr_rxword_ch_clk_2),
		.i_xcvr_tx_ch_clk(o_xcvr_txword_ch_clk_2),
		.i_xcvrif_tx_mux_data({ x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[42], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[41], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[40], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[39], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[38], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[37], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[36], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[35], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[34], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[33], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[32], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[31], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[30], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[29], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[28], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[27], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[26], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[25], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[24], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[23], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[22], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[21], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[20], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[19], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[18], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[17], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[16], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[15], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[14], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[13], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[12], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[11], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[10], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[9], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[8], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[7], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[6], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[5], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[4], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[3], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[2], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[1], x_std_sm_xcvrif_1ch_0__i_xcvrif_tx_mux_data_0[0] }),
		.o_ch_eth_xcvrif_rx_async({ o_ch2_eth_xcvrif_rx_async_1[13], o_ch2_eth_xcvrif_rx_async_1[12], o_ch2_eth_xcvrif_rx_async_1[11], o_ch2_eth_xcvrif_rx_async_1[10], o_ch2_eth_xcvrif_rx_async_1[9], o_ch2_eth_xcvrif_rx_async_1[8], o_ch2_eth_xcvrif_rx_async_1[7], o_ch2_eth_xcvrif_rx_async_1[6], o_ch2_eth_xcvrif_rx_async_1[5], o_ch2_eth_xcvrif_rx_async_1[4], o_ch2_eth_xcvrif_rx_async_1[3], o_ch2_eth_xcvrif_rx_async_1[2], o_ch2_eth_xcvrif_rx_async_1[1], o_ch2_eth_xcvrif_rx_async_1[0] }),
		.o_ch_eth_xcvrif_rx_direct(o_ch2_eth_xcvrif_rx_direct_1),
		.o_ch_lavmm_xcvrif_rdata({ o_ch2_lavmm_xcvrif_rdata_0[31], o_ch2_lavmm_xcvrif_rdata_0[30], o_ch2_lavmm_xcvrif_rdata_0[29], o_ch2_lavmm_xcvrif_rdata_0[28], o_ch2_lavmm_xcvrif_rdata_0[27], o_ch2_lavmm_xcvrif_rdata_0[26], o_ch2_lavmm_xcvrif_rdata_0[25], o_ch2_lavmm_xcvrif_rdata_0[24], o_ch2_lavmm_xcvrif_rdata_0[23], o_ch2_lavmm_xcvrif_rdata_0[22], o_ch2_lavmm_xcvrif_rdata_0[21], o_ch2_lavmm_xcvrif_rdata_0[20], o_ch2_lavmm_xcvrif_rdata_0[19], o_ch2_lavmm_xcvrif_rdata_0[18], o_ch2_lavmm_xcvrif_rdata_0[17], o_ch2_lavmm_xcvrif_rdata_0[16], o_ch2_lavmm_xcvrif_rdata_0[15], o_ch2_lavmm_xcvrif_rdata_0[14], o_ch2_lavmm_xcvrif_rdata_0[13], o_ch2_lavmm_xcvrif_rdata_0[12], o_ch2_lavmm_xcvrif_rdata_0[11], o_ch2_lavmm_xcvrif_rdata_0[10], o_ch2_lavmm_xcvrif_rdata_0[9], o_ch2_lavmm_xcvrif_rdata_0[8], o_ch2_lavmm_xcvrif_rdata_0[7], o_ch2_lavmm_xcvrif_rdata_0[6], o_ch2_lavmm_xcvrif_rdata_0[5], o_ch2_lavmm_xcvrif_rdata_0[4], o_ch2_lavmm_xcvrif_rdata_0[3], o_ch2_lavmm_xcvrif_rdata_0[2], o_ch2_lavmm_xcvrif_rdata_0[1], o_ch2_lavmm_xcvrif_rdata_0[0] }),
		.o_ch_lavmm_xcvrif_rdata_valid(o_ch2_lavmm_xcvrif_rdata_valid_0),
		.o_ch_lavmm_xcvrif_waitreq(o_ch2_lavmm_xcvrif_waitreq_0),
		.o_ch_xcvrif_rx_fifo_rd_en(o_ch2_xcvrif_rx_fifo_rd_en_0),
		.o_ch_xcvrif_tx_fifo_rd_en(o_ch2_xcvrif_tx_fifo_rd_en_0),
		.o_pma_rx_sf(x_std_sm_xcvrif_1ch_0__o_pma_rx_sf_1),
		.o_rx_data({ x_std_sm_xcvrif_1ch_0__o_rx_data_0[42], x_std_sm_xcvrif_1ch_0__o_rx_data_0[41], x_std_sm_xcvrif_1ch_0__o_rx_data_0[40], x_std_sm_xcvrif_1ch_0__o_rx_data_0[39], x_std_sm_xcvrif_1ch_0__o_rx_data_0[38], x_std_sm_xcvrif_1ch_0__o_rx_data_0[37], x_std_sm_xcvrif_1ch_0__o_rx_data_0[36], x_std_sm_xcvrif_1ch_0__o_rx_data_0[35], x_std_sm_xcvrif_1ch_0__o_rx_data_0[34], x_std_sm_xcvrif_1ch_0__o_rx_data_0[33], x_std_sm_xcvrif_1ch_0__o_rx_data_0[32], x_std_sm_xcvrif_1ch_0__o_rx_data_0[31], x_std_sm_xcvrif_1ch_0__o_rx_data_0[30], x_std_sm_xcvrif_1ch_0__o_rx_data_0[29], x_std_sm_xcvrif_1ch_0__o_rx_data_0[28], x_std_sm_xcvrif_1ch_0__o_rx_data_0[27], x_std_sm_xcvrif_1ch_0__o_rx_data_0[26], x_std_sm_xcvrif_1ch_0__o_rx_data_0[25], x_std_sm_xcvrif_1ch_0__o_rx_data_0[24], x_std_sm_xcvrif_1ch_0__o_rx_data_0[23], x_std_sm_xcvrif_1ch_0__o_rx_data_0[22], x_std_sm_xcvrif_1ch_0__o_rx_data_0[21], x_std_sm_xcvrif_1ch_0__o_rx_data_0[20], x_std_sm_xcvrif_1ch_0__o_rx_data_0[19], x_std_sm_xcvrif_1ch_0__o_rx_data_0[18], x_std_sm_xcvrif_1ch_0__o_rx_data_0[17], x_std_sm_xcvrif_1ch_0__o_rx_data_0[16], x_std_sm_xcvrif_1ch_0__o_rx_data_0[15], x_std_sm_xcvrif_1ch_0__o_rx_data_0[14], x_std_sm_xcvrif_1ch_0__o_rx_data_0[13], x_std_sm_xcvrif_1ch_0__o_rx_data_0[12], x_std_sm_xcvrif_1ch_0__o_rx_data_0[11], x_std_sm_xcvrif_1ch_0__o_rx_data_0[10], x_std_sm_xcvrif_1ch_0__o_rx_data_0[9], x_std_sm_xcvrif_1ch_0__o_rx_data_0[8], x_std_sm_xcvrif_1ch_0__o_rx_data_0[7], x_std_sm_xcvrif_1ch_0__o_rx_data_0[6], x_std_sm_xcvrif_1ch_0__o_rx_data_0[5], x_std_sm_xcvrif_1ch_0__o_rx_data_0[4], x_std_sm_xcvrif_1ch_0__o_rx_data_0[3], x_std_sm_xcvrif_1ch_0__o_rx_data_0[2], x_std_sm_xcvrif_1ch_0__o_rx_data_0[1], x_std_sm_xcvrif_1ch_0__o_rx_data_0[0] }),
		.o_rx_fifo_en_sel({ rx_fifo_en_sel_ch2_0[2], rx_fifo_en_sel_ch2_0[1], rx_fifo_en_sel_ch2_0[0] }),
		.o_rx_latency_pulse(o_rx_latency_ch2_pulse_0),
		.o_rx_xcvr_wordclk_sel({ xcvrif_1ch_u2__o_rx_xcvr_wordclk_sel_0[1], xcvrif_1ch_u2__o_rx_xcvr_wordclk_sel_0[0] }),
		.o_tx_dl_bit(o_tx_dl_ch2_bit_0),
		.o_tx_latency_pulse(o_tx_latency_ch2_pulse_0),
		.o_tx_rst_rd_sync_rst_n(o_ch2_tx_rst_rd_sync_rst_n_0),
		.o_tx_rst_source_sel({ xcvrif_1ch_u2__o_tx_rst_source_sel_0[2], xcvrif_1ch_u2__o_tx_rst_source_sel_0[1], xcvrif_1ch_u2__o_tx_rst_source_sel_0[0] }),
		.o_tx_rst_wr_sync_rst_n(o_ch2_tx_rst_wr_sync_rst_n_0),
		.o_tx_source_sel({ x_std_sm_xcvrif_1ch_0__o_tx_source_sel_0[1], x_std_sm_xcvrif_1ch_0__o_tx_source_sel_0[0] }),
		.o_tx_xcvr_wordclk_sel({ x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0[2], x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0[1], x_std_sm_xcvrif_1ch_0__o_tx_xcvr_wordclk_sel_0[0] }),
		.o_ux_tx_ch_data({ o_ux_tx_ch2_data_1[31], o_ux_tx_ch2_data_1[30], o_ux_tx_ch2_data_1[29], o_ux_tx_ch2_data_1[28], o_ux_tx_ch2_data_1[27], o_ux_tx_ch2_data_1[26], o_ux_tx_ch2_data_1[25], o_ux_tx_ch2_data_1[24], o_ux_tx_ch2_data_1[23], o_ux_tx_ch2_data_1[22], o_ux_tx_ch2_data_1[21], o_ux_tx_ch2_data_1[20], o_ux_tx_ch2_data_1[19], o_ux_tx_ch2_data_1[18], o_ux_tx_ch2_data_1[17], o_ux_tx_ch2_data_1[16], o_ux_tx_ch2_data_1[15], o_ux_tx_ch2_data_1[14], o_ux_tx_ch2_data_1[13], o_ux_tx_ch2_data_1[12], o_ux_tx_ch2_data_1[11], o_ux_tx_ch2_data_1[10], o_ux_tx_ch2_data_1[9], o_ux_tx_ch2_data_1[8], o_ux_tx_ch2_data_1[7], o_ux_tx_ch2_data_1[6], o_ux_tx_ch2_data_1[5], o_ux_tx_ch2_data_1[4], o_ux_tx_ch2_data_1[3], o_ux_tx_ch2_data_1[2], o_ux_tx_ch2_data_1[1], o_ux_tx_ch2_data_1[0] }),
		.o_ux_tx_ch_sync_data({ o_ux_tx_ch2_sync_data_1[6], o_ux_tx_ch2_sync_data_1[5], o_ux_tx_ch2_sync_data_1[4], o_ux_tx_ch2_sync_data_1[3], o_ux_tx_ch2_sync_data_1[2], o_ux_tx_ch2_sync_data_1[1], o_ux_tx_ch2_sync_data_1[0] })
	);

	tennm_sm_xcvrif_tx_rst_mux_module x_dynMux_sm_xcvrif_tx_rst_mux_1 (
		.i_x1(o_ch2_tx_rst_wr_sync_rst_n_0),
		.i_x2(),
		.i_x4(),
		.i_x6_bot(s3000_51_1__hssi_rstn_vcc_hssi__rst_n),
		.i_x6_top(),
		.i_x8_bot(s3000_51_1__hssi_rstn_vcc_hssi__rst_n),
		.i_x8_top(),
		.k_sel({ xcvrif_1ch_u2__o_tx_rst_source_sel_0[2], xcvrif_1ch_u2__o_tx_rst_source_sel_0[1], xcvrif_1ch_u2__o_tx_rst_source_sel_0[0] }),
		.o_ch_xcvrif_tx_rst_n(xcvrif_tx_rst_mux_u2__o_ch_xcvrif_tx_rst_n_0)
	);

	tennm_sm_xcvrif_tx_rst_mux_module x_dynMux_sm_xcvrif_tx_rst_mux_0 (
		.i_x1(o_ch2_tx_rst_rd_sync_rst_n_0),
		.i_x2(),
		.i_x4(),
		.i_x6_bot(s4708_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit),
		.i_x6_top(),
		.i_x8_bot(s4708_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit),
		.i_x8_top(),
		.k_sel({ xcvrif_1ch_u2__o_tx_rst_source_sel_0[2], xcvrif_1ch_u2__o_tx_rst_source_sel_0[1], xcvrif_1ch_u2__o_tx_rst_source_sel_0[0] }),
		.o_ch_xcvrif_tx_rst_n(xcvrif_tx_rd_rst_mux_u2__o_ch_xcvrif_tx_rst_n_0)
	);

	tennm_sm_hssi_pcie_pcs_lane #(
		.hps_clkmux(x_std_sm_hssi_pcie_pcs_lane_0__hps_clkmux),
		.hpsrx_mux(x_std_sm_hssi_pcie_pcs_lane_0__hpsrx_mux),
		.hpstx_demux(x_std_sm_hssi_pcie_pcs_lane_0__hpstx_demux),
		.pcie_pcs_mode(x_std_sm_hssi_pcie_pcs_lane_0__pcie_pcs_mode),
		.pclk_clk_hz(x_std_sm_hssi_pcie_pcs_lane_0__pclk_clk_hz),
		.sris_enable(x_std_sm_hssi_pcie_pcs_lane_0__sris_enable)
	) x_std_sm_hssi_pcie_pcs_lane_0 (
		.i_lavmm_pcie_addr({ o_ss_ch3_lavmm_pcie_addr_0[16], o_ss_ch3_lavmm_pcie_addr_0[15], o_ss_ch3_lavmm_pcie_addr_0[14], o_ss_ch3_lavmm_pcie_addr_0[13], o_ss_ch3_lavmm_pcie_addr_0[12], o_ss_ch3_lavmm_pcie_addr_0[11], o_ss_ch3_lavmm_pcie_addr_0[10], o_ss_ch3_lavmm_pcie_addr_0[9], o_ss_ch3_lavmm_pcie_addr_0[8], o_ss_ch3_lavmm_pcie_addr_0[7], o_ss_ch3_lavmm_pcie_addr_0[6], o_ss_ch3_lavmm_pcie_addr_0[5], o_ss_ch3_lavmm_pcie_addr_0[4], o_ss_ch3_lavmm_pcie_addr_0[3], o_ss_ch3_lavmm_pcie_addr_0[2], o_ss_ch3_lavmm_pcie_addr_0[1], o_ss_ch3_lavmm_pcie_addr_0[0] }),
		.i_lavmm_pcie_be({ o_ss_ch3_lavmm_pcie_be_0[3], o_ss_ch3_lavmm_pcie_be_0[2], o_ss_ch3_lavmm_pcie_be_0[1], o_ss_ch3_lavmm_pcie_be_0[0] }),
		.i_lavmm_pcie_clk(o_ss_ch3_lavmm_pcie_clk_0),
		.i_lavmm_pcie_read(o_ss_ch3_lavmm_pcie_read_0),
		.i_lavmm_pcie_rstn(o_ss_ch3_lavmm_pcie_rstn_0),
		.i_lavmm_pcie_wdata({ o_ss_ch3_lavmm_pcie_wdata_0[31], o_ss_ch3_lavmm_pcie_wdata_0[30], o_ss_ch3_lavmm_pcie_wdata_0[29], o_ss_ch3_lavmm_pcie_wdata_0[28], o_ss_ch3_lavmm_pcie_wdata_0[27], o_ss_ch3_lavmm_pcie_wdata_0[26], o_ss_ch3_lavmm_pcie_wdata_0[25], o_ss_ch3_lavmm_pcie_wdata_0[24], o_ss_ch3_lavmm_pcie_wdata_0[23], o_ss_ch3_lavmm_pcie_wdata_0[22], o_ss_ch3_lavmm_pcie_wdata_0[21], o_ss_ch3_lavmm_pcie_wdata_0[20], o_ss_ch3_lavmm_pcie_wdata_0[19], o_ss_ch3_lavmm_pcie_wdata_0[18], o_ss_ch3_lavmm_pcie_wdata_0[17], o_ss_ch3_lavmm_pcie_wdata_0[16], o_ss_ch3_lavmm_pcie_wdata_0[15], o_ss_ch3_lavmm_pcie_wdata_0[14], o_ss_ch3_lavmm_pcie_wdata_0[13], o_ss_ch3_lavmm_pcie_wdata_0[12], o_ss_ch3_lavmm_pcie_wdata_0[11], o_ss_ch3_lavmm_pcie_wdata_0[10], o_ss_ch3_lavmm_pcie_wdata_0[9], o_ss_ch3_lavmm_pcie_wdata_0[8], o_ss_ch3_lavmm_pcie_wdata_0[7], o_ss_ch3_lavmm_pcie_wdata_0[6], o_ss_ch3_lavmm_pcie_wdata_0[5], o_ss_ch3_lavmm_pcie_wdata_0[4], o_ss_ch3_lavmm_pcie_wdata_0[3], o_ss_ch3_lavmm_pcie_wdata_0[2], o_ss_ch3_lavmm_pcie_wdata_0[1], o_ss_ch3_lavmm_pcie_wdata_0[0] }),
		.i_lavmm_pcie_write(o_ss_ch3_lavmm_pcie_write_0),
		.i_pcie_rxword_clk(o_ux_pcie_rxword_clk_2),
		.i_pcie_txword_clk(o_ux_pcie_txword_clk_2),
		.i_pcs_pclk(x_std_sm_hssi_pcie_pcs_lane_0__i_pcs_pclk_1),
		.i_pcs_pipe_rstn(pcie_pcs_rst_mux_u2__o_rstn_0),
		.i_txpipe_asyncpowerchangeack(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_asyncpowerchangeack_1),
		.i_txpipe_blockaligncontrol(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_blockaligncontrol_1),
		.i_txpipe_cfg_hw_auto_sp_dis(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_cfg_hw_auto_sp_dis_1),
		.i_txpipe_dirchange(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_dirchange_1),
		.i_txpipe_ebuf_mode(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_ebuf_mode_1),
		.i_txpipe_encodedecodebypass(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_encodedecodebypass_1),
		.i_txpipe_fs({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[5], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[4], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_fs_0[0] }),
		.i_txpipe_getlocalpresetcoefficients(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_getlocalpresetcoefficients_1),
		.i_txpipe_invalidrequest(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_invalidrequest_1),
		.i_txpipe_lf({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[5], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[4], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lf_0[0] }),
		.i_txpipe_localpresetindex({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[4], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_localpresetindex_0[0] }),
		.i_txpipe_lowpin_nt(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_lowpin_nt_1),
		.i_txpipe_m2p_bus({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[7], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[6], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[5], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[4], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_m2p_bus_0[0] }),
		.i_txpipe_pclk_rate({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclk_rate_0[0] }),
		.i_txpipe_pclkchangeack(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_pclkchangeack_1),
		.i_txpipe_phy_mode_nt({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_phy_mode_nt_0[0] }),
		.i_txpipe_powerdown({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_powerdown_0[0] }),
		.i_txpipe_rate({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rate_0[0] }),
		.i_txpipe_rxelecidle_disable_a(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxelecidle_disable_a_1),
		.i_txpipe_rxeqclr(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqclr_1),
		.i_txpipe_rxeqeval(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqeval_1),
		.i_txpipe_rxeqinprogress(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqinprogress_1),
		.i_txpipe_rxeqtraining(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxeqtraining_1),
		.i_txpipe_rxpolarity(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpolarity_1),
		.i_txpipe_rxpresethint({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxpresethint_0[0] }),
		.i_txpipe_rxstandby(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxstandby_1),
		.i_txpipe_rxtermination(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_rxtermination_1),
		.i_txpipe_srisenable(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_srisenable_1),
		.i_txpipe_txcmnmode_disable_a(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcmnmode_disable_a_1),
		.i_txpipe_txcompliance(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txcompliance_1),
		.i_txpipe_txdata({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[39], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[38], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[37], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[36], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[35], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[34], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[33], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[32], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[31], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[30], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[29], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[28], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[27], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[26], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[25], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[24], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[23], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[22], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[21], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[20], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[19], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[18], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[17], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[16], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[15], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[14], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[13], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[12], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[11], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[10], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[9], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[8], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[7], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[6], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[5], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[4], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata_0[0] }),
		.i_txpipe_txdatak({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak_0[0] }),
		.i_txpipe_txdatavalid(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatavalid_1),
		.i_txpipe_txdeemph({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[17], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[16], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[15], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[14], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[13], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[12], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[11], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[10], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[9], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[8], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[7], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[6], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[5], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[4], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph_0[0] }),
		.i_txpipe_txdtctrx_lb(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdtctrx_lb_1),
		.i_txpipe_txelecidle(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txelecidle_1),
		.i_txpipe_txmargin({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txmargin_0[0] }),
		.i_txpipe_txoneszeros(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txoneszeros_1),
		.i_txpipe_txstartblock(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txstartblock_1),
		.i_txpipe_txswing(x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txswing_1),
		.i_txpipe_txsyncheader({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[3], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txsyncheader_0[0] }),
		.i_txpipe_width({ x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0[2], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0[1], x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_width_0[0] }),
		.i_uxq_rxcdrlock2dataa(o_ch3_rst_ux_rxcdrlock2data_2),
		.i_uxq_rxeq_best_eye_vala({ o_pcie_ch2_rxeq_best_eye_vala_1[13], o_pcie_ch2_rxeq_best_eye_vala_1[12], o_pcie_ch2_rxeq_best_eye_vala_1[11], o_pcie_ch2_rxeq_best_eye_vala_1[10], o_pcie_ch2_rxeq_best_eye_vala_1[9], o_pcie_ch2_rxeq_best_eye_vala_1[8], o_pcie_ch2_rxeq_best_eye_vala_1[7], o_pcie_ch2_rxeq_best_eye_vala_1[6], o_pcie_ch2_rxeq_best_eye_vala_1[5], o_pcie_ch2_rxeq_best_eye_vala_1[4], o_pcie_ch2_rxeq_best_eye_vala_1[3], o_pcie_ch2_rxeq_best_eye_vala_1[2], o_pcie_ch2_rxeq_best_eye_vala_1[1], o_pcie_ch2_rxeq_best_eye_vala_1[0] }),
		.i_uxq_rxeq_donea(o_pcie_ch2_rxeq_donea_1),
		.i_uxq_rxmargin_nacka(o_pcie_ch2_rxmargin_nacka_1),
		.i_uxq_rxmargin_status_gray_a({ o_pcie_ch2_rxmargin_status_gray_a_1[1], o_pcie_ch2_rxmargin_status_gray_a_1[0] }),
		.i_uxq_rxmargin_statusa(o_pcie_ch2_rxmargin_statusa_1),
		.i_uxq_rxsignaldetect_lfpsa(o_pcie_ch2_rxsignaldetect_lfpsa_1),
		.i_uxq_rxsignaldetecta(o_pcie_ch2_rxsignaldetecta_1),
		.i_uxq_rxstatusa(o_ch3_rst_ux_octl_pcs_rxstatus_2),
		.i_uxq_rxword({ o_pcie_rx_data_2[39], o_pcie_rx_data_2[38], o_pcie_rx_data_2[37], o_pcie_rx_data_2[36], o_pcie_rx_data_2[35], o_pcie_rx_data_2[34], o_pcie_rx_data_2[33], o_pcie_rx_data_2[32], o_pcie_rx_data_2[31], o_pcie_rx_data_2[30], o_pcie_rx_data_2[29], o_pcie_rx_data_2[28], o_pcie_rx_data_2[27], o_pcie_rx_data_2[26], o_pcie_rx_data_2[25], o_pcie_rx_data_2[24], o_pcie_rx_data_2[23], o_pcie_rx_data_2[22], o_pcie_rx_data_2[21], o_pcie_rx_data_2[20], o_pcie_rx_data_2[19], o_pcie_rx_data_2[18], o_pcie_rx_data_2[17], o_pcie_rx_data_2[16], o_pcie_rx_data_2[15], o_pcie_rx_data_2[14], o_pcie_rx_data_2[13], o_pcie_rx_data_2[12], o_pcie_rx_data_2[11], o_pcie_rx_data_2[10], o_pcie_rx_data_2[9], o_pcie_rx_data_2[8], o_pcie_rx_data_2[7], o_pcie_rx_data_2[6], o_pcie_rx_data_2[5], o_pcie_rx_data_2[4], o_pcie_rx_data_2[3], o_pcie_rx_data_2[2], o_pcie_rx_data_2[1], o_pcie_rx_data_2[0] }),
		.i_uxq_synthlcfast_postdiv(o_pcie_ch2_synthlcfast_postdiv_1),
		.i_uxq_synthlcmed_postdiv(o_pcie_ch2_synthlcmed_postdiv_1),
		.i_uxq_synthlcslow_postdiv(o_pcie_ch2_synthlcslow_postdiv_1),
		.i_uxq_txdetectrx_acka(o_pcie_ch2_txdetectrx_acka_1),
		.i_uxq_txdetectrx_statct(o_pcie_ch2_txdetectrx_statct_1),
		.i_uxq_txstatusa(o_ch3_rst_ux_octl_pcs_txstatus_2),
		.o_lavmm_pcie_rdata({ o_ch2_lavmm_pcie_rdata_1[31], o_ch2_lavmm_pcie_rdata_1[30], o_ch2_lavmm_pcie_rdata_1[29], o_ch2_lavmm_pcie_rdata_1[28], o_ch2_lavmm_pcie_rdata_1[27], o_ch2_lavmm_pcie_rdata_1[26], o_ch2_lavmm_pcie_rdata_1[25], o_ch2_lavmm_pcie_rdata_1[24], o_ch2_lavmm_pcie_rdata_1[23], o_ch2_lavmm_pcie_rdata_1[22], o_ch2_lavmm_pcie_rdata_1[21], o_ch2_lavmm_pcie_rdata_1[20], o_ch2_lavmm_pcie_rdata_1[19], o_ch2_lavmm_pcie_rdata_1[18], o_ch2_lavmm_pcie_rdata_1[17], o_ch2_lavmm_pcie_rdata_1[16], o_ch2_lavmm_pcie_rdata_1[15], o_ch2_lavmm_pcie_rdata_1[14], o_ch2_lavmm_pcie_rdata_1[13], o_ch2_lavmm_pcie_rdata_1[12], o_ch2_lavmm_pcie_rdata_1[11], o_ch2_lavmm_pcie_rdata_1[10], o_ch2_lavmm_pcie_rdata_1[9], o_ch2_lavmm_pcie_rdata_1[8], o_ch2_lavmm_pcie_rdata_1[7], o_ch2_lavmm_pcie_rdata_1[6], o_ch2_lavmm_pcie_rdata_1[5], o_ch2_lavmm_pcie_rdata_1[4], o_ch2_lavmm_pcie_rdata_1[3], o_ch2_lavmm_pcie_rdata_1[2], o_ch2_lavmm_pcie_rdata_1[1], o_ch2_lavmm_pcie_rdata_1[0] }),
		.o_lavmm_pcie_rdata_valid(o_ch2_lavmm_pcie_rdata_valid_1),
		.o_lavmm_pcie_waitreq(o_ch2_lavmm_pcie_waitreq_1),
		.o_pcs_pclk(x_std_sm_hssi_pcie_pcs_lane_0__o_pcs_pclk_1),
		.o_pcs_pipe_rstn(o_local_pcs2_pipe_rstn_1),
		.o_rxpipe_dirfeedback({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_dirfeedback_0[0] }),
		.o_rxpipe_linkevaluationfeedbackfiguremerit({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[7], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[6], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_linkevaluationfeedbackfiguremerit_0[0] }),
		.o_rxpipe_localfs({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localfs_0[0] }),
		.o_rxpipe_locallf({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_locallf_0[0] }),
		.o_rxpipe_localtxcoefficientsvalid(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxcoefficientsvalid_1),
		.o_rxpipe_localtxpresetcoefficients({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[17], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[16], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[15], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[14], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[13], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[12], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[11], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[10], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[9], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[8], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[7], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[6], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_localtxpresetcoefficients_0[0] }),
		.o_rxpipe_p2m_bus({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[7], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[6], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_p2m_bus_0[0] }),
		.o_rxpipe_pclkchangeok(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_pclkchangeok_1),
		.o_rxpipe_phystatus(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_phystatus_1),
		.o_rxpipe_rxdata({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[39], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[38], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[37], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[36], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[35], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[34], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[33], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[32], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[31], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[30], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[29], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[28], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[27], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[26], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[25], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[24], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[23], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[22], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[21], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[20], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[19], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[18], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[17], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[16], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[15], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[14], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[13], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[12], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[11], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[10], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[9], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[8], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[7], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[6], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[5], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[4], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata_0[0] }),
		.o_rxpipe_rxdatak({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak_0[0] }),
		.o_rxpipe_rxdatavalid(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatavalid_1),
		.o_rxpipe_rxelecidlea(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxelecidlea_1),
		.o_rxpipe_rxstandbystatus(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstandbystatus_1),
		.o_rxpipe_rxstartblock(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstartblock_0[0]),
		.o_rxpipe_rxstatus({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxstatus_0[0] }),
		.o_rxpipe_rxsyncheader({ x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[3], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[2], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[1], x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxsyncheader_0[0] }),
		.o_rxpipe_rxvalid(x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxvalid_1),
		.o_ux_ock_pma_clk(o_ux2_ock_pma_clk_1),
		.o_uxq_lfps_ennt(o_uxq2_lfps_ennt_0),
		.o_uxq_pcie_l1ctrla({ o_uxq2_pcie_l1ctrla_0[1], o_uxq2_pcie_l1ctrla_0[0] }),
		.o_uxq_pma_cmn_ctrl(o_uxq2_pma_cmn_ctrl_0),
		.o_uxq_pma_ctrl(o_uxq2_pma_ctrl_0),
		.o_uxq_rst_pcs_rx_b_a(o_uxq2_rst_pcs_rx_b_a_0),
		.o_uxq_rst_pcs_tx_b_a(o_uxq2_rst_pcs_tx_b_a_0),
		.o_uxq_rxeiosdetectstata(o_uxq2_rxeiosdetectstata_0),
		.o_uxq_rxeq_precal_code_selnt({ o_uxq2_rxeq_precal_code_selnt_0[2], o_uxq2_rxeq_precal_code_selnt_0[1], o_uxq2_rxeq_precal_code_selnt_0[0] }),
		.o_uxq_rxeq_starta(o_uxq2_rxeq_starta_0),
		.o_uxq_rxeq_static_ena(o_uxq2_rxeq_static_ena_0),
		.o_uxq_rxmargin_direction_nt(o_uxq2_rxmargin_direction_nt_0),
		.o_uxq_rxmargin_mode_nt(o_uxq2_rxmargin_mode_nt_0),
		.o_uxq_rxmargin_offset_change_a(o_uxq2_rxmargin_offset_change_a_0),
		.o_uxq_rxmargin_offset_nt({ o_uxq2_rxmargin_offset_nt_0[6], o_uxq2_rxmargin_offset_nt_0[5], o_uxq2_rxmargin_offset_nt_0[4], o_uxq2_rxmargin_offset_nt_0[3], o_uxq2_rxmargin_offset_nt_0[2], o_uxq2_rxmargin_offset_nt_0[1], o_uxq2_rxmargin_offset_nt_0[0] }),
		.o_uxq_rxmargin_start_a(o_uxq2_rxmargin_start_a_0),
		.o_uxq_rxpstate({ o_uxq2_rxpstate_0[2], o_uxq2_rxpstate_0[1], o_uxq2_rxpstate_0[0] }),
		.o_uxq_rxrate({ o_uxq2_rxrate_0[3], o_uxq2_rxrate_0[2], o_uxq2_rxrate_0[1], o_uxq2_rxrate_0[0] }),
		.o_uxq_rxterm_hiz_ena(o_uxq2_rxterm_hiz_ena_0),
		.o_uxq_rxwidth({ o_uxq2_rxwidth_0[2], o_uxq2_rxwidth_0[1], o_uxq2_rxwidth_0[0] }),
		.o_uxq_tstbus_lane(o_uxq2_tstbus_lane_0),
		.o_uxq_txbeacona(o_uxq2_txbeacona_0),
		.o_uxq_txclkdivrate({ o_uxq2_txclkdivrate_0[2], o_uxq2_txclkdivrate_0[1], o_uxq2_txclkdivrate_0[0] }),
		.o_uxq_txdetectrx_reqa(o_uxq2_txdetectrx_reqa_0),
		.o_uxq_txdrv_levn({ o_uxq2_txdrv_levn_0[5], o_uxq2_txdrv_levn_0[4], o_uxq2_txdrv_levn_0[3], o_uxq2_txdrv_levn_0[2], o_uxq2_txdrv_levn_0[1], o_uxq2_txdrv_levn_0[0] }),
		.o_uxq_txdrv_levnm1({ o_uxq2_txdrv_levnm1_0[4], o_uxq2_txdrv_levnm1_0[3], o_uxq2_txdrv_levnm1_0[2], o_uxq2_txdrv_levnm1_0[1], o_uxq2_txdrv_levnm1_0[0] }),
		.o_uxq_txdrv_levnm2({ o_uxq2_txdrv_levnm2_0[2], o_uxq2_txdrv_levnm2_0[1], o_uxq2_txdrv_levnm2_0[0] }),
		.o_uxq_txdrv_levnp1({ o_uxq2_txdrv_levnp1_0[4], o_uxq2_txdrv_levnp1_0[3], o_uxq2_txdrv_levnp1_0[2], o_uxq2_txdrv_levnp1_0[1], o_uxq2_txdrv_levnp1_0[0] }),
		.o_uxq_txdrv_slew({ o_uxq2_txdrv_slew_0[3], o_uxq2_txdrv_slew_0[2], o_uxq2_txdrv_slew_0[1], o_uxq2_txdrv_slew_0[0] }),
		.o_uxq_txelecidle({ o_uxq2_txelecidle_0[3], o_uxq2_txelecidle_0[2], o_uxq2_txelecidle_0[1], o_uxq2_txelecidle_0[0] }),
		.o_uxq_txpstate({ o_uxq2_txpstate_0[2], o_uxq2_txpstate_0[1], o_uxq2_txpstate_0[0] }),
		.o_uxq_txrate({ o_uxq2_txrate_0[3], o_uxq2_txrate_0[2], o_uxq2_txrate_0[1], o_uxq2_txrate_0[0] }),
		.o_uxq_txwidth({ o_uxq2_txwidth_0[2], o_uxq2_txwidth_0[1], o_uxq2_txwidth_0[0] }),
		.o_uxq_txword({ o_uxq2_txword_0[39], o_uxq2_txword_0[38], o_uxq2_txword_0[37], o_uxq2_txword_0[36], o_uxq2_txword_0[35], o_uxq2_txword_0[34], o_uxq2_txword_0[33], o_uxq2_txword_0[32], o_uxq2_txword_0[31], o_uxq2_txword_0[30], o_uxq2_txword_0[29], o_uxq2_txword_0[28], o_uxq2_txword_0[27], o_uxq2_txword_0[26], o_uxq2_txword_0[25], o_uxq2_txword_0[24], o_uxq2_txword_0[23], o_uxq2_txword_0[22], o_uxq2_txword_0[21], o_uxq2_txword_0[20], o_uxq2_txword_0[19], o_uxq2_txword_0[18], o_uxq2_txword_0[17], o_uxq2_txword_0[16], o_uxq2_txword_0[15], o_uxq2_txword_0[14], o_uxq2_txword_0[13], o_uxq2_txword_0[12], o_uxq2_txword_0[11], o_uxq2_txword_0[10], o_uxq2_txword_0[9], o_uxq2_txword_0[8], o_uxq2_txword_0[7], o_uxq2_txword_0[6], o_uxq2_txword_0[5], o_uxq2_txword_0[4], o_uxq2_txword_0[3], o_uxq2_txword_0[2], o_uxq2_txword_0[1], o_uxq2_txword_0[0] })
	);

	tennm_sm_hssi_pcie_pcs_rst_mux #(
		.sel(x_mux_sm_hssi_pcie_pcs_rst_mux_0__sel)
	) x_mux_sm_hssi_pcie_pcs_rst_mux_0 (
		.i_hps_rst_rstn(x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_hps_rst_rstn_1),
		.i_same_quad_pcs_rst_rstn(x_mux_sm_hssi_pcie_pcs_rst_mux_0__i_same_quad_pcs_rst_rstn_1),
		.i_unused_rstn(n1_3),
		.i_upper_quad_pcs_rst_rstn(n1_3),
		.o_rstn(pcie_pcs_rst_mux_u2__o_rstn_0)
	);

	tennm_ipfluxtop_global_mem_wrap x_std_ipfluxtop_global_mem_wrap_0 (
		.car_cpu_bresetn(car_cpu_bresetn_1),
		.car_cpu_clk(car_cpu_clk_1),
		.iflux_mem_dram0checkdata({ iflux_mem_DRam0CheckData_0[19], iflux_mem_DRam0CheckData_0[18], iflux_mem_DRam0CheckData_0[17], iflux_mem_DRam0CheckData_0[16], iflux_mem_DRam0CheckData_0[15], iflux_mem_DRam0CheckData_0[14], iflux_mem_DRam0CheckData_0[13], iflux_mem_DRam0CheckData_0[12], iflux_mem_DRam0CheckData_0[11], iflux_mem_DRam0CheckData_0[10], iflux_mem_DRam0CheckData_0[9], iflux_mem_DRam0CheckData_0[8], iflux_mem_DRam0CheckData_0[7], iflux_mem_DRam0CheckData_0[6], iflux_mem_DRam0CheckData_0[5], iflux_mem_DRam0CheckData_0[4], iflux_mem_DRam0CheckData_0[3], iflux_mem_DRam0CheckData_0[2], iflux_mem_DRam0CheckData_0[1], iflux_mem_DRam0CheckData_0[0] }),
		.iflux_mem_dram0data({ iflux_mem_DRam0Data_0[31], iflux_mem_DRam0Data_0[30], iflux_mem_DRam0Data_0[29], iflux_mem_DRam0Data_0[28], iflux_mem_DRam0Data_0[27], iflux_mem_DRam0Data_0[26], iflux_mem_DRam0Data_0[25], iflux_mem_DRam0Data_0[24], iflux_mem_DRam0Data_0[23], iflux_mem_DRam0Data_0[22], iflux_mem_DRam0Data_0[21], iflux_mem_DRam0Data_0[20], iflux_mem_DRam0Data_0[19], iflux_mem_DRam0Data_0[18], iflux_mem_DRam0Data_0[17], iflux_mem_DRam0Data_0[16], iflux_mem_DRam0Data_0[15], iflux_mem_DRam0Data_0[14], iflux_mem_DRam0Data_0[13], iflux_mem_DRam0Data_0[12], iflux_mem_DRam0Data_0[11], iflux_mem_DRam0Data_0[10], iflux_mem_DRam0Data_0[9], iflux_mem_DRam0Data_0[8], iflux_mem_DRam0Data_0[7], iflux_mem_DRam0Data_0[6], iflux_mem_DRam0Data_0[5], iflux_mem_DRam0Data_0[4], iflux_mem_DRam0Data_0[3], iflux_mem_DRam0Data_0[2], iflux_mem_DRam0Data_0[1], iflux_mem_DRam0Data_0[0] }),
		.iflux_mem_iram0checkdata({ iflux_mem_IRam0CheckData_0[6], iflux_mem_IRam0CheckData_0[5], iflux_mem_IRam0CheckData_0[4], iflux_mem_IRam0CheckData_0[3], iflux_mem_IRam0CheckData_0[2], iflux_mem_IRam0CheckData_0[1], iflux_mem_IRam0CheckData_0[0] }),
		.iflux_mem_iram0data({ iflux_mem_IRam0Data_0[31], iflux_mem_IRam0Data_0[30], iflux_mem_IRam0Data_0[29], iflux_mem_IRam0Data_0[28], iflux_mem_IRam0Data_0[27], iflux_mem_IRam0Data_0[26], iflux_mem_IRam0Data_0[25], iflux_mem_IRam0Data_0[24], iflux_mem_IRam0Data_0[23], iflux_mem_IRam0Data_0[22], iflux_mem_IRam0Data_0[21], iflux_mem_IRam0Data_0[20], iflux_mem_IRam0Data_0[19], iflux_mem_IRam0Data_0[18], iflux_mem_IRam0Data_0[17], iflux_mem_IRam0Data_0[16], iflux_mem_IRam0Data_0[15], iflux_mem_IRam0Data_0[14], iflux_mem_IRam0Data_0[13], iflux_mem_IRam0Data_0[12], iflux_mem_IRam0Data_0[11], iflux_mem_IRam0Data_0[10], iflux_mem_IRam0Data_0[9], iflux_mem_IRam0Data_0[8], iflux_mem_IRam0Data_0[7], iflux_mem_IRam0Data_0[6], iflux_mem_IRam0Data_0[5], iflux_mem_IRam0Data_0[4], iflux_mem_IRam0Data_0[3], iflux_mem_IRam0Data_0[2], iflux_mem_IRam0Data_0[1], iflux_mem_IRam0Data_0[0] }),
		.iflux_mem_qfifo_rd_data({ iflux_mem_qfifo_rd_data_0[31], iflux_mem_qfifo_rd_data_0[30], iflux_mem_qfifo_rd_data_0[29], iflux_mem_qfifo_rd_data_0[28], iflux_mem_qfifo_rd_data_0[27], iflux_mem_qfifo_rd_data_0[26], iflux_mem_qfifo_rd_data_0[25], iflux_mem_qfifo_rd_data_0[24], iflux_mem_qfifo_rd_data_0[23], iflux_mem_qfifo_rd_data_0[22], iflux_mem_qfifo_rd_data_0[21], iflux_mem_qfifo_rd_data_0[20], iflux_mem_qfifo_rd_data_0[19], iflux_mem_qfifo_rd_data_0[18], iflux_mem_qfifo_rd_data_0[17], iflux_mem_qfifo_rd_data_0[16], iflux_mem_qfifo_rd_data_0[15], iflux_mem_qfifo_rd_data_0[14], iflux_mem_qfifo_rd_data_0[13], iflux_mem_qfifo_rd_data_0[12], iflux_mem_qfifo_rd_data_0[11], iflux_mem_qfifo_rd_data_0[10], iflux_mem_qfifo_rd_data_0[9], iflux_mem_qfifo_rd_data_0[8], iflux_mem_qfifo_rd_data_0[7], iflux_mem_qfifo_rd_data_0[6], iflux_mem_qfifo_rd_data_0[5], iflux_mem_qfifo_rd_data_0[4], iflux_mem_qfifo_rd_data_0[3], iflux_mem_qfifo_rd_data_0[2], iflux_mem_qfifo_rd_data_0[1], iflux_mem_qfifo_rd_data_0[0] }),
		.iflux_mem_tracememdata({ iflux_mem_TraceMemData_0[31], iflux_mem_TraceMemData_0[30], iflux_mem_TraceMemData_0[29], iflux_mem_TraceMemData_0[28], iflux_mem_TraceMemData_0[27], iflux_mem_TraceMemData_0[26], iflux_mem_TraceMemData_0[25], iflux_mem_TraceMemData_0[24], iflux_mem_TraceMemData_0[23], iflux_mem_TraceMemData_0[22], iflux_mem_TraceMemData_0[21], iflux_mem_TraceMemData_0[20], iflux_mem_TraceMemData_0[19], iflux_mem_TraceMemData_0[18], iflux_mem_TraceMemData_0[17], iflux_mem_TraceMemData_0[16], iflux_mem_TraceMemData_0[15], iflux_mem_TraceMemData_0[14], iflux_mem_TraceMemData_0[13], iflux_mem_TraceMemData_0[12], iflux_mem_TraceMemData_0[11], iflux_mem_TraceMemData_0[10], iflux_mem_TraceMemData_0[9], iflux_mem_TraceMemData_0[8], iflux_mem_TraceMemData_0[7], iflux_mem_TraceMemData_0[6], iflux_mem_TraceMemData_0[5], iflux_mem_TraceMemData_0[4], iflux_mem_TraceMemData_0[3], iflux_mem_TraceMemData_0[2], iflux_mem_TraceMemData_0[1], iflux_mem_TraceMemData_0[0] }),
		.oflux_mem_dram0addr({ oflux_mem_DRam0Addr_1[15], oflux_mem_DRam0Addr_1[14], oflux_mem_DRam0Addr_1[13], oflux_mem_DRam0Addr_1[12], oflux_mem_DRam0Addr_1[11], oflux_mem_DRam0Addr_1[10], oflux_mem_DRam0Addr_1[9], oflux_mem_DRam0Addr_1[8], oflux_mem_DRam0Addr_1[7], oflux_mem_DRam0Addr_1[6], oflux_mem_DRam0Addr_1[5], oflux_mem_DRam0Addr_1[4], oflux_mem_DRam0Addr_1[3], oflux_mem_DRam0Addr_1[2] }),
		.oflux_mem_dram0byteen({ oflux_mem_DRam0ByteEn_1[3], oflux_mem_DRam0ByteEn_1[2], oflux_mem_DRam0ByteEn_1[1], oflux_mem_DRam0ByteEn_1[0] }),
		.oflux_mem_dram0checkwrdata({ oflux_mem_DRam0CheckWrData_1[19], oflux_mem_DRam0CheckWrData_1[18], oflux_mem_DRam0CheckWrData_1[17], oflux_mem_DRam0CheckWrData_1[16], oflux_mem_DRam0CheckWrData_1[15], oflux_mem_DRam0CheckWrData_1[14], oflux_mem_DRam0CheckWrData_1[13], oflux_mem_DRam0CheckWrData_1[12], oflux_mem_DRam0CheckWrData_1[11], oflux_mem_DRam0CheckWrData_1[10], oflux_mem_DRam0CheckWrData_1[9], oflux_mem_DRam0CheckWrData_1[8], oflux_mem_DRam0CheckWrData_1[7], oflux_mem_DRam0CheckWrData_1[6], oflux_mem_DRam0CheckWrData_1[5], oflux_mem_DRam0CheckWrData_1[4], oflux_mem_DRam0CheckWrData_1[3], oflux_mem_DRam0CheckWrData_1[2], oflux_mem_DRam0CheckWrData_1[1], oflux_mem_DRam0CheckWrData_1[0] }),
		.oflux_mem_dram0en(oflux_mem_DRam0En_1),
		.oflux_mem_dram0wr(oflux_mem_DRam0Wr_1),
		.oflux_mem_dram0wrdata({ oflux_mem_DRam0WrData_1[31], oflux_mem_DRam0WrData_1[30], oflux_mem_DRam0WrData_1[29], oflux_mem_DRam0WrData_1[28], oflux_mem_DRam0WrData_1[27], oflux_mem_DRam0WrData_1[26], oflux_mem_DRam0WrData_1[25], oflux_mem_DRam0WrData_1[24], oflux_mem_DRam0WrData_1[23], oflux_mem_DRam0WrData_1[22], oflux_mem_DRam0WrData_1[21], oflux_mem_DRam0WrData_1[20], oflux_mem_DRam0WrData_1[19], oflux_mem_DRam0WrData_1[18], oflux_mem_DRam0WrData_1[17], oflux_mem_DRam0WrData_1[16], oflux_mem_DRam0WrData_1[15], oflux_mem_DRam0WrData_1[14], oflux_mem_DRam0WrData_1[13], oflux_mem_DRam0WrData_1[12], oflux_mem_DRam0WrData_1[11], oflux_mem_DRam0WrData_1[10], oflux_mem_DRam0WrData_1[9], oflux_mem_DRam0WrData_1[8], oflux_mem_DRam0WrData_1[7], oflux_mem_DRam0WrData_1[6], oflux_mem_DRam0WrData_1[5], oflux_mem_DRam0WrData_1[4], oflux_mem_DRam0WrData_1[3], oflux_mem_DRam0WrData_1[2], oflux_mem_DRam0WrData_1[1], oflux_mem_DRam0WrData_1[0] }),
		.oflux_mem_iram0addr({ oflux_mem_IRam0Addr_1[16], oflux_mem_IRam0Addr_1[15], oflux_mem_IRam0Addr_1[14], oflux_mem_IRam0Addr_1[13], oflux_mem_IRam0Addr_1[12], oflux_mem_IRam0Addr_1[11], oflux_mem_IRam0Addr_1[10], oflux_mem_IRam0Addr_1[9], oflux_mem_IRam0Addr_1[8], oflux_mem_IRam0Addr_1[7], oflux_mem_IRam0Addr_1[6], oflux_mem_IRam0Addr_1[5], oflux_mem_IRam0Addr_1[4], oflux_mem_IRam0Addr_1[3], oflux_mem_IRam0Addr_1[2] }),
		.oflux_mem_iram0checkwrdata({ oflux_mem_IRam0CheckWrData_1[6], oflux_mem_IRam0CheckWrData_1[5], oflux_mem_IRam0CheckWrData_1[4], oflux_mem_IRam0CheckWrData_1[3], oflux_mem_IRam0CheckWrData_1[2], oflux_mem_IRam0CheckWrData_1[1], oflux_mem_IRam0CheckWrData_1[0] }),
		.oflux_mem_iram0en(oflux_mem_IRam0En_1),
		.oflux_mem_iram0wr(oflux_mem_IRam0Wr_1),
		.oflux_mem_iram0wrdata({ oflux_mem_IRam0WrData_1[31], oflux_mem_IRam0WrData_1[30], oflux_mem_IRam0WrData_1[29], oflux_mem_IRam0WrData_1[28], oflux_mem_IRam0WrData_1[27], oflux_mem_IRam0WrData_1[26], oflux_mem_IRam0WrData_1[25], oflux_mem_IRam0WrData_1[24], oflux_mem_IRam0WrData_1[23], oflux_mem_IRam0WrData_1[22], oflux_mem_IRam0WrData_1[21], oflux_mem_IRam0WrData_1[20], oflux_mem_IRam0WrData_1[19], oflux_mem_IRam0WrData_1[18], oflux_mem_IRam0WrData_1[17], oflux_mem_IRam0WrData_1[16], oflux_mem_IRam0WrData_1[15], oflux_mem_IRam0WrData_1[14], oflux_mem_IRam0WrData_1[13], oflux_mem_IRam0WrData_1[12], oflux_mem_IRam0WrData_1[11], oflux_mem_IRam0WrData_1[10], oflux_mem_IRam0WrData_1[9], oflux_mem_IRam0WrData_1[8], oflux_mem_IRam0WrData_1[7], oflux_mem_IRam0WrData_1[6], oflux_mem_IRam0WrData_1[5], oflux_mem_IRam0WrData_1[4], oflux_mem_IRam0WrData_1[3], oflux_mem_IRam0WrData_1[2], oflux_mem_IRam0WrData_1[1], oflux_mem_IRam0WrData_1[0] }),
		.oflux_mem_qfifo_rd_addr({ oflux_mem_qfifo_rd_addr_1[8], oflux_mem_qfifo_rd_addr_1[7], oflux_mem_qfifo_rd_addr_1[6], oflux_mem_qfifo_rd_addr_1[5], oflux_mem_qfifo_rd_addr_1[4], oflux_mem_qfifo_rd_addr_1[3], oflux_mem_qfifo_rd_addr_1[2], oflux_mem_qfifo_rd_addr_1[1], oflux_mem_qfifo_rd_addr_1[0] }),
		.oflux_mem_qfifo_rd_en(oflux_mem_qfifo_rd_en_1),
		.oflux_mem_qfifo_wr_addr({ oflux_mem_qfifo_wr_addr_1[8], oflux_mem_qfifo_wr_addr_1[7], oflux_mem_qfifo_wr_addr_1[6], oflux_mem_qfifo_wr_addr_1[5], oflux_mem_qfifo_wr_addr_1[4], oflux_mem_qfifo_wr_addr_1[3], oflux_mem_qfifo_wr_addr_1[2], oflux_mem_qfifo_wr_addr_1[1], oflux_mem_qfifo_wr_addr_1[0] }),
		.oflux_mem_qfifo_wr_data({ oflux_mem_qfifo_wr_data_1[31], oflux_mem_qfifo_wr_data_1[30], oflux_mem_qfifo_wr_data_1[29], oflux_mem_qfifo_wr_data_1[28], oflux_mem_qfifo_wr_data_1[27], oflux_mem_qfifo_wr_data_1[26], oflux_mem_qfifo_wr_data_1[25], oflux_mem_qfifo_wr_data_1[24], oflux_mem_qfifo_wr_data_1[23], oflux_mem_qfifo_wr_data_1[22], oflux_mem_qfifo_wr_data_1[21], oflux_mem_qfifo_wr_data_1[20], oflux_mem_qfifo_wr_data_1[19], oflux_mem_qfifo_wr_data_1[18], oflux_mem_qfifo_wr_data_1[17], oflux_mem_qfifo_wr_data_1[16], oflux_mem_qfifo_wr_data_1[15], oflux_mem_qfifo_wr_data_1[14], oflux_mem_qfifo_wr_data_1[13], oflux_mem_qfifo_wr_data_1[12], oflux_mem_qfifo_wr_data_1[11], oflux_mem_qfifo_wr_data_1[10], oflux_mem_qfifo_wr_data_1[9], oflux_mem_qfifo_wr_data_1[8], oflux_mem_qfifo_wr_data_1[7], oflux_mem_qfifo_wr_data_1[6], oflux_mem_qfifo_wr_data_1[5], oflux_mem_qfifo_wr_data_1[4], oflux_mem_qfifo_wr_data_1[3], oflux_mem_qfifo_wr_data_1[2], oflux_mem_qfifo_wr_data_1[1], oflux_mem_qfifo_wr_data_1[0] }),
		.oflux_mem_qfifo_wr_en(oflux_mem_qfifo_wr_en_1),
		.oflux_mem_tracememaddr({ oflux_mem_TraceMemAddr_1[8], oflux_mem_TraceMemAddr_1[7], oflux_mem_TraceMemAddr_1[6], oflux_mem_TraceMemAddr_1[5], oflux_mem_TraceMemAddr_1[4], oflux_mem_TraceMemAddr_1[3], oflux_mem_TraceMemAddr_1[2], oflux_mem_TraceMemAddr_1[1], oflux_mem_TraceMemAddr_1[0] }),
		.oflux_mem_tracememen(oflux_mem_TraceMemEn_1),
		.oflux_mem_tracememwr(oflux_mem_TraceMemWr_1),
		.oflux_mem_tracememwrdata({ oflux_mem_TraceMemWrData_1[31], oflux_mem_TraceMemWrData_1[30], oflux_mem_TraceMemWrData_1[29], oflux_mem_TraceMemWrData_1[28], oflux_mem_TraceMemWrData_1[27], oflux_mem_TraceMemWrData_1[26], oflux_mem_TraceMemWrData_1[25], oflux_mem_TraceMemWrData_1[24], oflux_mem_TraceMemWrData_1[23], oflux_mem_TraceMemWrData_1[22], oflux_mem_TraceMemWrData_1[21], oflux_mem_TraceMemWrData_1[20], oflux_mem_TraceMemWrData_1[19], oflux_mem_TraceMemWrData_1[18], oflux_mem_TraceMemWrData_1[17], oflux_mem_TraceMemWrData_1[16], oflux_mem_TraceMemWrData_1[15], oflux_mem_TraceMemWrData_1[14], oflux_mem_TraceMemWrData_1[13], oflux_mem_TraceMemWrData_1[12], oflux_mem_TraceMemWrData_1[11], oflux_mem_TraceMemWrData_1[10], oflux_mem_TraceMemWrData_1[9], oflux_mem_TraceMemWrData_1[8], oflux_mem_TraceMemWrData_1[7], oflux_mem_TraceMemWrData_1[6], oflux_mem_TraceMemWrData_1[5], oflux_mem_TraceMemWrData_1[4], oflux_mem_TraceMemWrData_1[3], oflux_mem_TraceMemWrData_1[2], oflux_mem_TraceMemWrData_1[1], oflux_mem_TraceMemWrData_1[0] })
	);

	tennm_sm_flux_ingress #(
		.clkrx_refclk_cssm_fw_control(x_std_sm_flux_ingress_0__clkrx_refclk_cssm_fw_control),
		.clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_flux_ingress_0__clkrx_refclk_sector_specifies_refclk_ready),
		.dr_enabled(x_std_sm_flux_ingress_0__dr_enabled),
		.flux_mode(x_std_sm_flux_ingress_0__flux_mode),
		.local_refclk_cssm_fw_control(x_std_sm_flux_ingress_0__local_refclk_cssm_fw_control),
		.local_refclk_sector_specifies_refclk_ready(x_std_sm_flux_ingress_0__local_refclk_sector_specifies_refclk_ready),
		.rx_dl_enable(x_std_sm_flux_ingress_0__rx_dl_enable),
		.rx_dl_rx_lat_bit_for_async(x_std_sm_flux_ingress_0__rx_dl_rx_lat_bit_for_async),
		.rx_dl_rxbit_cntr_pma(x_std_sm_flux_ingress_0__rx_dl_rxbit_cntr_pma),
		.rx_dl_rxbit_rollover(x_std_sm_flux_ingress_0__rx_dl_rxbit_rollover),
		.rx_fec_type_used(x_std_sm_flux_ingress_0__rx_fec_type_used),
		.rx_protocol_hint(x_std_sm_flux_ingress_0__rx_protocol_hint),
		.rx_sim_mode(x_std_sm_flux_ingress_0__rx_sim_mode),
		.rx_user1_clk_mux_dynamic_sel(x_std_sm_flux_ingress_0__rx_user1_clk_mux_dynamic_sel),
		.rx_user2_clk_mux_dynamic_sel(x_std_sm_flux_ingress_0__rx_user2_clk_mux_dynamic_sel),
		.sequencer_reg_en(x_std_sm_flux_ingress_0__sequencer_reg_en),
		.tx_bond_size(x_std_sm_flux_ingress_0__tx_bond_size),
		.tx_dl_enable(x_std_sm_flux_ingress_0__tx_dl_enable),
		.tx_sim_mode(x_std_sm_flux_ingress_0__tx_sim_mode),
		.tx_user1_clk_mux_dynamic_sel(x_std_sm_flux_ingress_0__tx_user1_clk_mux_dynamic_sel),
		.tx_user2_clk_mux_dynamic_sel(x_std_sm_flux_ingress_0__tx_user2_clk_mux_dynamic_sel)
	) x_std_sm_flux_ingress_0 (
		.i_dat_pcs_measlatbit(ux_toolbox_u0__o_dat_pcs_measlatbit_ch2_0),
		.i_dpma_refclk(o_ux_dpma_clk_2),
		.i_flux_cpi_int(oflux_cpi_int_1),
		.i_flux_int(oflux_int2_1),
		.i_flux_srds_rdy(oflux_srds_rdy2_1),
		.i_ft_rx_async_pulse_ch(ux_toolbox_u0__o_ft_rx_async_pulse_ch2_0),
		.i_ft_rx_sclk_sync_ch(mac_pcs_fec_top_u0__o_ft_ux_rx_sclk_sync_ch2_0),
		.i_ft_tx_async_pulse_ch(ux_toolbox_u0__o_ft_tx_async_pulse_ch2_0),
		.i_ft_tx_sclk_sync_ch(mac_pcs_fec_top_u0__o_ft_ux_tx_sclk_sync_ch2_0),
		.i_ick_pcs_txword(o_pcs_txword_2),
		.i_ick_sclk_rx(mac_pcs_fec_top_u0__o_ux_sclk_rx_ch2_0),
		.i_ick_sclk_tx(mac_pcs_fec_top_u0__o_ux_sclk_tx_ch2_0),
		.i_ictl_pcs_txenable_a(ux_toolbox_u0__o_ictl_pcs_txenable_ch2_a_0),
		.i_lavmm_addr({ o_ch3_lavmm_ux_addr_0[19], o_ch3_lavmm_ux_addr_0[18], o_ch3_lavmm_ux_addr_0[17], o_ch3_lavmm_ux_addr_0[16], o_ch3_lavmm_ux_addr_0[15], o_ch3_lavmm_ux_addr_0[14], o_ch3_lavmm_ux_addr_0[13], o_ch3_lavmm_ux_addr_0[12], o_ch3_lavmm_ux_addr_0[11], o_ch3_lavmm_ux_addr_0[10], o_ch3_lavmm_ux_addr_0[9], o_ch3_lavmm_ux_addr_0[8], o_ch3_lavmm_ux_addr_0[7], o_ch3_lavmm_ux_addr_0[6], o_ch3_lavmm_ux_addr_0[5], o_ch3_lavmm_ux_addr_0[4], o_ch3_lavmm_ux_addr_0[3], o_ch3_lavmm_ux_addr_0[2], o_ch3_lavmm_ux_addr_0[1], o_ch3_lavmm_ux_addr_0[0] }),
		.i_lavmm_be({ o_ch3_lavmm_ux_be_0[3], o_ch3_lavmm_ux_be_0[2], o_ch3_lavmm_ux_be_0[1], o_ch3_lavmm_ux_be_0[0] }),
		.i_lavmm_clk(o_ch3_lavmm_ux_clk_0),
		.i_lavmm_rdata({ flux_ingress_u2__i_lavmm_rdata_0[31], flux_ingress_u2__i_lavmm_rdata_0[30], flux_ingress_u2__i_lavmm_rdata_0[29], flux_ingress_u2__i_lavmm_rdata_0[28], flux_ingress_u2__i_lavmm_rdata_0[27], flux_ingress_u2__i_lavmm_rdata_0[26], flux_ingress_u2__i_lavmm_rdata_0[25], flux_ingress_u2__i_lavmm_rdata_0[24], flux_ingress_u2__i_lavmm_rdata_0[23], flux_ingress_u2__i_lavmm_rdata_0[22], flux_ingress_u2__i_lavmm_rdata_0[21], flux_ingress_u2__i_lavmm_rdata_0[20], flux_ingress_u2__i_lavmm_rdata_0[19], flux_ingress_u2__i_lavmm_rdata_0[18], flux_ingress_u2__i_lavmm_rdata_0[17], flux_ingress_u2__i_lavmm_rdata_0[16], flux_ingress_u2__i_lavmm_rdata_0[15], flux_ingress_u2__i_lavmm_rdata_0[14], flux_ingress_u2__i_lavmm_rdata_0[13], flux_ingress_u2__i_lavmm_rdata_0[12], flux_ingress_u2__i_lavmm_rdata_0[11], flux_ingress_u2__i_lavmm_rdata_0[10], flux_ingress_u2__i_lavmm_rdata_0[9], flux_ingress_u2__i_lavmm_rdata_0[8], flux_ingress_u2__i_lavmm_rdata_0[7], flux_ingress_u2__i_lavmm_rdata_0[6], flux_ingress_u2__i_lavmm_rdata_0[5], flux_ingress_u2__i_lavmm_rdata_0[4], flux_ingress_u2__i_lavmm_rdata_0[3], flux_ingress_u2__i_lavmm_rdata_0[2], flux_ingress_u2__i_lavmm_rdata_0[1], flux_ingress_u2__i_lavmm_rdata_0[0] }),
		.i_lavmm_rdata_valid(flux_ingress_u2__i_lavmm_rdata_valid_0),
		.i_lavmm_read(o_ch3_lavmm_ux_read_0),
		.i_lavmm_rstn(o_ch3_lavmm_ux_rstn_0),
		.i_lavmm_waitreq(flux_ingress_u2__i_lavmm_waitreq_0),
		.i_lavmm_wdata({ o_ch3_lavmm_ux_wdata_0[31], o_ch3_lavmm_ux_wdata_0[30], o_ch3_lavmm_ux_wdata_0[29], o_ch3_lavmm_ux_wdata_0[28], o_ch3_lavmm_ux_wdata_0[27], o_ch3_lavmm_ux_wdata_0[26], o_ch3_lavmm_ux_wdata_0[25], o_ch3_lavmm_ux_wdata_0[24], o_ch3_lavmm_ux_wdata_0[23], o_ch3_lavmm_ux_wdata_0[22], o_ch3_lavmm_ux_wdata_0[21], o_ch3_lavmm_ux_wdata_0[20], o_ch3_lavmm_ux_wdata_0[19], o_ch3_lavmm_ux_wdata_0[18], o_ch3_lavmm_ux_wdata_0[17], o_ch3_lavmm_ux_wdata_0[16], o_ch3_lavmm_ux_wdata_0[15], o_ch3_lavmm_ux_wdata_0[14], o_ch3_lavmm_ux_wdata_0[13], o_ch3_lavmm_ux_wdata_0[12], o_ch3_lavmm_ux_wdata_0[11], o_ch3_lavmm_ux_wdata_0[10], o_ch3_lavmm_ux_wdata_0[9], o_ch3_lavmm_ux_wdata_0[8], o_ch3_lavmm_ux_wdata_0[7], o_ch3_lavmm_ux_wdata_0[6], o_ch3_lavmm_ux_wdata_0[5], o_ch3_lavmm_ux_wdata_0[4], o_ch3_lavmm_ux_wdata_0[3], o_ch3_lavmm_ux_wdata_0[2], o_ch3_lavmm_ux_wdata_0[1], o_ch3_lavmm_ux_wdata_0[0] }),
		.i_lavmm_write(o_ch3_lavmm_ux_write_0),
		.i_lfps_ennt(o_uxq2_lfps_ennt_0),
		.i_ock_pcs_txword(oflux_srds_tx_clk_lane2_1),
		.i_oflux_octl_pcs_txptr_smpl_lane(oflux_octl_pcs_txptr_smpl_lane2_1),
		.i_pcie_l1ctrla({ o_uxq2_pcie_l1ctrla_0[1], o_uxq2_pcie_l1ctrla_0[0] }),
		.i_pcie_pcs_rx_rst(o_uxq2_rst_pcs_rx_b_a_0),
		.i_pcie_pcs_tx_rst(o_uxq2_rst_pcs_tx_b_a_0),
		.i_pcs_pipe_rstn(o_local_pcs2_pipe_rstn_1),
		.i_pcs_rxpostdiv(oflux_srds_rx_divn_clk_lane2_1),
		.i_pcs_rxword(oflux_srds_rx_clk_lane2_1),
		.i_pma_cmn_ctrl(o_uxq2_pma_cmn_ctrl_0),
		.i_pma_ctrl(o_uxq2_pma_ctrl_0),
		.i_rst_pld_ux_rx_pma_rst_n(pcie_top_x4_u0__o_ft_ch3_rst_ux_rx_pma_rst_n_0),
		.i_rst_pld_ux_tx_pma_rst_n(pcie_top_x4_u0__o_ft_ch3_rst_ux_tx_pma_rst_n_0),
		.i_rst_ux_rx_sfrz(pcie_top_x4_u0__o_ft_ch3_rst_ux_rx_sfrz_0),
		.i_rx_data({ oflux_pcs_rxword_lane2_1[79], oflux_pcs_rxword_lane2_1[78], oflux_pcs_rxword_lane2_1[77], oflux_pcs_rxword_lane2_1[76], oflux_pcs_rxword_lane2_1[75], oflux_pcs_rxword_lane2_1[74], oflux_pcs_rxword_lane2_1[73], oflux_pcs_rxword_lane2_1[72], oflux_pcs_rxword_lane2_1[71], oflux_pcs_rxword_lane2_1[70], oflux_pcs_rxword_lane2_1[69], oflux_pcs_rxword_lane2_1[68], oflux_pcs_rxword_lane2_1[67], oflux_pcs_rxword_lane2_1[66], oflux_pcs_rxword_lane2_1[65], oflux_pcs_rxword_lane2_1[64], oflux_pcs_rxword_lane2_1[63], oflux_pcs_rxword_lane2_1[62], oflux_pcs_rxword_lane2_1[61], oflux_pcs_rxword_lane2_1[60], oflux_pcs_rxword_lane2_1[59], oflux_pcs_rxword_lane2_1[58], oflux_pcs_rxword_lane2_1[57], oflux_pcs_rxword_lane2_1[56], oflux_pcs_rxword_lane2_1[55], oflux_pcs_rxword_lane2_1[54], oflux_pcs_rxword_lane2_1[53], oflux_pcs_rxword_lane2_1[52], oflux_pcs_rxword_lane2_1[51], oflux_pcs_rxword_lane2_1[50], oflux_pcs_rxword_lane2_1[49], oflux_pcs_rxword_lane2_1[48], oflux_pcs_rxword_lane2_1[47], oflux_pcs_rxword_lane2_1[46], oflux_pcs_rxword_lane2_1[45], oflux_pcs_rxword_lane2_1[44], oflux_pcs_rxword_lane2_1[43], oflux_pcs_rxword_lane2_1[42], oflux_pcs_rxword_lane2_1[41], oflux_pcs_rxword_lane2_1[40], oflux_pcs_rxword_lane2_1[39], oflux_pcs_rxword_lane2_1[38], oflux_pcs_rxword_lane2_1[37], oflux_pcs_rxword_lane2_1[36], oflux_pcs_rxword_lane2_1[35], oflux_pcs_rxword_lane2_1[34], oflux_pcs_rxword_lane2_1[33], oflux_pcs_rxword_lane2_1[32], oflux_pcs_rxword_lane2_1[31], oflux_pcs_rxword_lane2_1[30], oflux_pcs_rxword_lane2_1[29], oflux_pcs_rxword_lane2_1[28], oflux_pcs_rxword_lane2_1[27], oflux_pcs_rxword_lane2_1[26], oflux_pcs_rxword_lane2_1[25], oflux_pcs_rxword_lane2_1[24], oflux_pcs_rxword_lane2_1[23], oflux_pcs_rxword_lane2_1[22], oflux_pcs_rxword_lane2_1[21], oflux_pcs_rxword_lane2_1[20], oflux_pcs_rxword_lane2_1[19], oflux_pcs_rxword_lane2_1[18], oflux_pcs_rxword_lane2_1[17], oflux_pcs_rxword_lane2_1[16], oflux_pcs_rxword_lane2_1[15], oflux_pcs_rxword_lane2_1[14], oflux_pcs_rxword_lane2_1[13], oflux_pcs_rxword_lane2_1[12], oflux_pcs_rxword_lane2_1[11], oflux_pcs_rxword_lane2_1[10], oflux_pcs_rxword_lane2_1[9], oflux_pcs_rxword_lane2_1[8], oflux_pcs_rxword_lane2_1[7], oflux_pcs_rxword_lane2_1[6], oflux_pcs_rxword_lane2_1[5], oflux_pcs_rxword_lane2_1[4], oflux_pcs_rxword_lane2_1[3], oflux_pcs_rxword_lane2_1[2], oflux_pcs_rxword_lane2_1[1], oflux_pcs_rxword_lane2_1[0] }),
		.i_rx_dl_ch_bit(flux_ingress_u2__i_rx_dl_ch_bit_0),
		.i_rxeiosdetectstata(o_uxq2_rxeiosdetectstata_0),
		.i_rxeq_precal_code_selnt({ o_uxq2_rxeq_precal_code_selnt_0[2], o_uxq2_rxeq_precal_code_selnt_0[1], o_uxq2_rxeq_precal_code_selnt_0[0] }),
		.i_rxeq_starta(o_uxq2_rxeq_starta_0),
		.i_rxeq_static_ena(o_uxq2_rxeq_static_ena_0),
		.i_rxmargin_direction_nt(o_uxq2_rxmargin_direction_nt_0),
		.i_rxmargin_mode_nt(o_uxq2_rxmargin_mode_nt_0),
		.i_rxmargin_offset_change_a(o_uxq2_rxmargin_offset_change_a_0),
		.i_rxmargin_offset_nt({ o_uxq2_rxmargin_offset_nt_0[6], o_uxq2_rxmargin_offset_nt_0[5], o_uxq2_rxmargin_offset_nt_0[4], o_uxq2_rxmargin_offset_nt_0[3], o_uxq2_rxmargin_offset_nt_0[2], o_uxq2_rxmargin_offset_nt_0[1], o_uxq2_rxmargin_offset_nt_0[0] }),
		.i_rxmargin_start_a(o_uxq2_rxmargin_start_a_0),
		.i_rxpstate({ o_uxq2_rxpstate_0[2], o_uxq2_rxpstate_0[1], o_uxq2_rxpstate_0[0] }),
		.i_rxrate({ o_uxq2_rxrate_0[3], o_uxq2_rxrate_0[2], o_uxq2_rxrate_0[1], o_uxq2_rxrate_0[0] }),
		.i_rxterm_hiz_ena(o_uxq2_rxterm_hiz_ena_0),
		.i_rxwidth({ o_uxq2_rxwidth_0[2], o_uxq2_rxwidth_0[1], o_uxq2_rxwidth_0[0] }),
		.i_sm_flux_egress({ oflux_egress_direct_lane2_1[256], oflux_egress_direct_lane2_1[255], oflux_egress_direct_lane2_1[254], oflux_egress_direct_lane2_1[253], oflux_egress_direct_lane2_1[252], oflux_egress_direct_lane2_1[251], oflux_egress_direct_lane2_1[250], oflux_egress_direct_lane2_1[249], oflux_egress_direct_lane2_1[248], oflux_egress_direct_lane2_1[247], oflux_egress_direct_lane2_1[246], oflux_egress_direct_lane2_1[245], oflux_egress_direct_lane2_1[244], oflux_egress_direct_lane2_1[243], oflux_egress_direct_lane2_1[242], oflux_egress_direct_lane2_1[241], oflux_egress_direct_lane2_1[240], oflux_egress_direct_lane2_1[239], oflux_egress_direct_lane2_1[238], oflux_egress_direct_lane2_1[237], oflux_egress_direct_lane2_1[236], oflux_egress_direct_lane2_1[235], oflux_egress_direct_lane2_1[234], oflux_egress_direct_lane2_1[233], oflux_egress_direct_lane2_1[232], oflux_egress_direct_lane2_1[231], oflux_egress_direct_lane2_1[230], oflux_egress_direct_lane2_1[229], oflux_egress_direct_lane2_1[228], oflux_egress_direct_lane2_1[227], oflux_egress_direct_lane2_1[226], oflux_egress_direct_lane2_1[225], oflux_egress_direct_lane2_1[224], oflux_egress_direct_lane2_1[223], oflux_egress_direct_lane2_1[222], oflux_egress_direct_lane2_1[221], oflux_egress_direct_lane2_1[220], oflux_egress_direct_lane2_1[219], oflux_egress_direct_lane2_1[218], oflux_egress_direct_lane2_1[217], oflux_egress_direct_lane2_1[216], oflux_egress_direct_lane2_1[215], oflux_egress_direct_lane2_1[214], oflux_egress_direct_lane2_1[213], oflux_egress_direct_lane2_1[212], oflux_egress_direct_lane2_1[211], oflux_egress_direct_lane2_1[210], oflux_egress_direct_lane2_1[209], oflux_egress_direct_lane2_1[208], oflux_egress_direct_lane2_1[207], oflux_egress_direct_lane2_1[206], oflux_egress_direct_lane2_1[205], oflux_egress_direct_lane2_1[204], oflux_egress_direct_lane2_1[203], oflux_egress_direct_lane2_1[202], oflux_egress_direct_lane2_1[201], oflux_egress_direct_lane2_1[200], oflux_egress_direct_lane2_1[199], oflux_egress_direct_lane2_1[198], oflux_egress_direct_lane2_1[197], oflux_egress_direct_lane2_1[196], oflux_egress_direct_lane2_1[195], oflux_egress_direct_lane2_1[194], oflux_egress_direct_lane2_1[193], oflux_egress_direct_lane2_1[192], oflux_egress_direct_lane2_1[191], oflux_egress_direct_lane2_1[190], oflux_egress_direct_lane2_1[189], oflux_egress_direct_lane2_1[188], oflux_egress_direct_lane2_1[187], oflux_egress_direct_lane2_1[186], oflux_egress_direct_lane2_1[185], oflux_egress_direct_lane2_1[184], oflux_egress_direct_lane2_1[183], oflux_egress_direct_lane2_1[182], oflux_egress_direct_lane2_1[181], oflux_egress_direct_lane2_1[180], oflux_egress_direct_lane2_1[179], oflux_egress_direct_lane2_1[178], oflux_egress_direct_lane2_1[177], oflux_egress_direct_lane2_1[176], oflux_egress_direct_lane2_1[175], oflux_egress_direct_lane2_1[174], oflux_egress_direct_lane2_1[173], oflux_egress_direct_lane2_1[172], oflux_egress_direct_lane2_1[171], oflux_egress_direct_lane2_1[170], oflux_egress_direct_lane2_1[169], oflux_egress_direct_lane2_1[168], oflux_egress_direct_lane2_1[167], oflux_egress_direct_lane2_1[166], oflux_egress_direct_lane2_1[165], oflux_egress_direct_lane2_1[164], oflux_egress_direct_lane2_1[163], oflux_egress_direct_lane2_1[162], oflux_egress_direct_lane2_1[161], oflux_egress_direct_lane2_1[160], oflux_egress_direct_lane2_1[159], oflux_egress_direct_lane2_1[158], oflux_egress_direct_lane2_1[157], oflux_egress_direct_lane2_1[156], oflux_egress_direct_lane2_1[155], oflux_egress_direct_lane2_1[154], oflux_egress_direct_lane2_1[153], oflux_egress_direct_lane2_1[152], oflux_egress_direct_lane2_1[151], oflux_egress_direct_lane2_1[150], oflux_egress_direct_lane2_1[149], oflux_egress_direct_lane2_1[148], oflux_egress_direct_lane2_1[147], oflux_egress_direct_lane2_1[146], oflux_egress_direct_lane2_1[145], oflux_egress_direct_lane2_1[144], oflux_egress_direct_lane2_1[143], oflux_egress_direct_lane2_1[142], oflux_egress_direct_lane2_1[141], oflux_egress_direct_lane2_1[140], oflux_egress_direct_lane2_1[139], oflux_egress_direct_lane2_1[138], oflux_egress_direct_lane2_1[137], oflux_egress_direct_lane2_1[136], oflux_egress_direct_lane2_1[135], oflux_egress_direct_lane2_1[134], oflux_egress_direct_lane2_1[133], oflux_egress_direct_lane2_1[132], oflux_egress_direct_lane2_1[131], oflux_egress_direct_lane2_1[130], oflux_egress_direct_lane2_1[129], oflux_egress_direct_lane2_1[128], oflux_egress_direct_lane2_1[127], oflux_egress_direct_lane2_1[126], oflux_egress_direct_lane2_1[125], oflux_egress_direct_lane2_1[124], oflux_egress_direct_lane2_1[123], oflux_egress_direct_lane2_1[122], oflux_egress_direct_lane2_1[121], oflux_egress_direct_lane2_1[120], oflux_egress_direct_lane2_1[119], oflux_egress_direct_lane2_1[118], oflux_egress_direct_lane2_1[117], oflux_egress_direct_lane2_1[116], oflux_egress_direct_lane2_1[115], oflux_egress_direct_lane2_1[114], oflux_egress_direct_lane2_1[113], oflux_egress_direct_lane2_1[112], oflux_egress_direct_lane2_1[111], oflux_egress_direct_lane2_1[110], oflux_egress_direct_lane2_1[109], oflux_egress_direct_lane2_1[108], oflux_egress_direct_lane2_1[107], oflux_egress_direct_lane2_1[106], oflux_egress_direct_lane2_1[105], oflux_egress_direct_lane2_1[104], oflux_egress_direct_lane2_1[103], oflux_egress_direct_lane2_1[102], oflux_egress_direct_lane2_1[101], oflux_egress_direct_lane2_1[100], oflux_egress_direct_lane2_1[99], oflux_egress_direct_lane2_1[98], oflux_egress_direct_lane2_1[97], oflux_egress_direct_lane2_1[96], oflux_egress_direct_lane2_1[95], oflux_egress_direct_lane2_1[94], oflux_egress_direct_lane2_1[93], oflux_egress_direct_lane2_1[92], oflux_egress_direct_lane2_1[91], oflux_egress_direct_lane2_1[90], oflux_egress_direct_lane2_1[89], oflux_egress_direct_lane2_1[88], oflux_egress_direct_lane2_1[87], oflux_egress_direct_lane2_1[86], oflux_egress_direct_lane2_1[85], oflux_egress_direct_lane2_1[84], oflux_egress_direct_lane2_1[83], oflux_egress_direct_lane2_1[82], oflux_egress_direct_lane2_1[81], oflux_egress_direct_lane2_1[80], oflux_egress_direct_lane2_1[79], oflux_egress_direct_lane2_1[78], oflux_egress_direct_lane2_1[77], oflux_egress_direct_lane2_1[76], oflux_egress_direct_lane2_1[75], oflux_egress_direct_lane2_1[74], oflux_egress_direct_lane2_1[73], oflux_egress_direct_lane2_1[72], oflux_egress_direct_lane2_1[71], oflux_egress_direct_lane2_1[70], oflux_egress_direct_lane2_1[69], oflux_egress_direct_lane2_1[68], oflux_egress_direct_lane2_1[67], oflux_egress_direct_lane2_1[66], oflux_egress_direct_lane2_1[65], oflux_egress_direct_lane2_1[64], oflux_egress_direct_lane2_1[63], oflux_egress_direct_lane2_1[62], oflux_egress_direct_lane2_1[61], oflux_egress_direct_lane2_1[60], oflux_egress_direct_lane2_1[59], oflux_egress_direct_lane2_1[58], oflux_egress_direct_lane2_1[57], oflux_egress_direct_lane2_1[56], oflux_egress_direct_lane2_1[55], oflux_egress_direct_lane2_1[54], oflux_egress_direct_lane2_1[53], oflux_egress_direct_lane2_1[52], oflux_egress_direct_lane2_1[51], oflux_egress_direct_lane2_1[50], oflux_egress_direct_lane2_1[49], oflux_egress_direct_lane2_1[48], oflux_egress_direct_lane2_1[47], oflux_egress_direct_lane2_1[46], oflux_egress_direct_lane2_1[45], oflux_egress_direct_lane2_1[44], oflux_egress_direct_lane2_1[43], oflux_egress_direct_lane2_1[42], oflux_egress_direct_lane2_1[41], oflux_egress_direct_lane2_1[40], oflux_egress_direct_lane2_1[39], oflux_egress_direct_lane2_1[38], oflux_egress_direct_lane2_1[37], oflux_egress_direct_lane2_1[36], oflux_egress_direct_lane2_1[35], oflux_egress_direct_lane2_1[34], oflux_egress_direct_lane2_1[33], oflux_egress_direct_lane2_1[32], oflux_egress_direct_lane2_1[31], oflux_egress_direct_lane2_1[30], oflux_egress_direct_lane2_1[29], oflux_egress_direct_lane2_1[28], oflux_egress_direct_lane2_1[27], oflux_egress_direct_lane2_1[26], oflux_egress_direct_lane2_1[25], oflux_egress_direct_lane2_1[24], oflux_egress_direct_lane2_1[23], oflux_egress_direct_lane2_1[22], oflux_egress_direct_lane2_1[21], oflux_egress_direct_lane2_1[20], oflux_egress_direct_lane2_1[19], oflux_egress_direct_lane2_1[18], oflux_egress_direct_lane2_1[17], oflux_egress_direct_lane2_1[16], oflux_egress_direct_lane2_1[15], oflux_egress_direct_lane2_1[14], oflux_egress_direct_lane2_1[13], oflux_egress_direct_lane2_1[12], oflux_egress_direct_lane2_1[11], oflux_egress_direct_lane2_1[10], oflux_egress_direct_lane2_1[9], oflux_egress_direct_lane2_1[8], oflux_egress_direct_lane2_1[7], oflux_egress_direct_lane2_1[6], oflux_egress_direct_lane2_1[5], oflux_egress_direct_lane2_1[4], oflux_egress_direct_lane2_1[3], oflux_egress_direct_lane2_1[2], oflux_egress_direct_lane2_1[1], oflux_egress_direct_lane2_1[0] }),
		.i_ss_async_pldif({ ux_quad_u0__i_ss_async_pldif_ch2_0[79], ux_quad_u0__i_ss_async_pldif_ch2_0[78], ux_quad_u0__i_ss_async_pldif_ch2_0[77], ux_quad_u0__i_ss_async_pldif_ch2_0[76], ux_quad_u0__i_ss_async_pldif_ch2_0[75], ux_quad_u0__i_ss_async_pldif_ch2_0[74], ux_quad_u0__i_ss_async_pldif_ch2_0[73], ux_quad_u0__i_ss_async_pldif_ch2_0[72], ux_quad_u0__i_ss_async_pldif_ch2_0[71], ux_quad_u0__i_ss_async_pldif_ch2_0[70], ux_quad_u0__i_ss_async_pldif_ch2_0[69], ux_quad_u0__i_ss_async_pldif_ch2_0[68], ux_quad_u0__i_ss_async_pldif_ch2_0[67], ux_quad_u0__i_ss_async_pldif_ch2_0[66], ux_quad_u0__i_ss_async_pldif_ch2_0[65], ux_quad_u0__i_ss_async_pldif_ch2_0[64], ux_quad_u0__i_ss_async_pldif_ch2_0[63], ux_quad_u0__i_ss_async_pldif_ch2_0[62], ux_quad_u0__i_ss_async_pldif_ch2_0[61], ux_quad_u0__i_ss_async_pldif_ch2_0[60], ux_quad_u0__i_ss_async_pldif_ch2_0[59], ux_quad_u0__i_ss_async_pldif_ch2_0[58], ux_quad_u0__i_ss_async_pldif_ch2_0[57], ux_quad_u0__i_ss_async_pldif_ch2_0[56], ux_quad_u0__i_ss_async_pldif_ch2_0[55], ux_quad_u0__i_ss_async_pldif_ch2_0[54], ux_quad_u0__i_ss_async_pldif_ch2_0[53], ux_quad_u0__i_ss_async_pldif_ch2_0[52], ux_quad_u0__i_ss_async_pldif_ch2_0[51], ux_quad_u0__i_ss_async_pldif_ch2_0[50], ux_quad_u0__i_ss_async_pldif_ch2_0[49], ux_quad_u0__i_ss_async_pldif_ch2_0[48], ux_quad_u0__i_ss_async_pldif_ch2_0[47], ux_quad_u0__i_ss_async_pldif_ch2_0[46], ux_quad_u0__i_ss_async_pldif_ch2_0[45], ux_quad_u0__i_ss_async_pldif_ch2_0[44], ux_quad_u0__i_ss_async_pldif_ch2_0[43], ux_quad_u0__i_ss_async_pldif_ch2_0[42], ux_quad_u0__i_ss_async_pldif_ch2_0[41], ux_quad_u0__i_ss_async_pldif_ch2_0[40], ux_quad_u0__i_ss_async_pldif_ch2_0[39], ux_quad_u0__i_ss_async_pldif_ch2_0[38], ux_quad_u0__i_ss_async_pldif_ch2_0[37], ux_quad_u0__i_ss_async_pldif_ch2_0[36], ux_quad_u0__i_ss_async_pldif_ch2_0[35], ux_quad_u0__i_ss_async_pldif_ch2_0[34], ux_quad_u0__i_ss_async_pldif_ch2_0[33], ux_quad_u0__i_ss_async_pldif_ch2_0[32], ux_quad_u0__i_ss_async_pldif_ch2_0[31], ux_quad_u0__i_ss_async_pldif_ch2_0[30], ux_quad_u0__i_ss_async_pldif_ch2_0[29], ux_quad_u0__i_ss_async_pldif_ch2_0[28], ux_quad_u0__i_ss_async_pldif_ch2_0[27], ux_quad_u0__i_ss_async_pldif_ch2_0[26], ux_quad_u0__i_ss_async_pldif_ch2_0[25], ux_quad_u0__i_ss_async_pldif_ch2_0[24], ux_quad_u0__i_ss_async_pldif_ch2_0[23], ux_quad_u0__i_ss_async_pldif_ch2_0[22], ux_quad_u0__i_ss_async_pldif_ch2_0[21], ux_quad_u0__i_ss_async_pldif_ch2_0[20], ux_quad_u0__i_ss_async_pldif_ch2_0[19], ux_quad_u0__i_ss_async_pldif_ch2_0[18], ux_quad_u0__i_ss_async_pldif_ch2_0[17], ux_quad_u0__i_ss_async_pldif_ch2_0[16], ux_quad_u0__i_ss_async_pldif_ch2_0[15], ux_quad_u0__i_ss_async_pldif_ch2_0[14], ux_quad_u0__i_ss_async_pldif_ch2_0[13], ux_quad_u0__i_ss_async_pldif_ch2_0[12], ux_quad_u0__i_ss_async_pldif_ch2_0[11], ux_quad_u0__i_ss_async_pldif_ch2_0[10], ux_quad_u0__i_ss_async_pldif_ch2_0[9], ux_quad_u0__i_ss_async_pldif_ch2_0[8], ux_quad_u0__i_ss_async_pldif_ch2_0[7], ux_quad_u0__i_ss_async_pldif_ch2_0[6], ux_quad_u0__i_ss_async_pldif_ch2_0[5], ux_quad_u0__i_ss_async_pldif_ch2_0[4], ux_quad_u0__i_ss_async_pldif_ch2_0[3], ux_quad_u0__i_ss_async_pldif_ch2_0[2], ux_quad_u0__i_ss_async_pldif_ch2_0[1], ux_quad_u0__i_ss_async_pldif_ch2_0[0] }),
		.i_ss_async_pldif_pcie_mux({ ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[79], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[78], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[77], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[76], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[75], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[74], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[73], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[72], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[71], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[70], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[69], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[68], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[67], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[66], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[65], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[64], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[63], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[62], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[61], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[60], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[59], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[58], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[57], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[56], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[55], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[54], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[53], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[52], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[51], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[50], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[49], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[48], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[47], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[46], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[45], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[44], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[43], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[42], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[41], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[40], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[39], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[38], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[37], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[36], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[35], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[34], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[33], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[32], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[31], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[30], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[29], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[28], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[27], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[26], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[25], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[24], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[23], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[22], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[21], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[20], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[19], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[18], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[17], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[16], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[15], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[14], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[13], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[12], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[11], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[10], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[9], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[8], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[7], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[6], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[5], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[4], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[3], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[2], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[1], ux_quad_u0__i_ss_async_pldif_pcie_mux_ch2_0[0] }),
		.i_sync_cfg_data({ ux_toolbox_u0__o_sync_cfg_data_ch2_0[124], ux_toolbox_u0__o_sync_cfg_data_ch2_0[123], ux_toolbox_u0__o_sync_cfg_data_ch2_0[122], ux_toolbox_u0__o_sync_cfg_data_ch2_0[121], ux_toolbox_u0__o_sync_cfg_data_ch2_0[120], ux_toolbox_u0__o_sync_cfg_data_ch2_0[119], ux_toolbox_u0__o_sync_cfg_data_ch2_0[118], ux_toolbox_u0__o_sync_cfg_data_ch2_0[117], ux_toolbox_u0__o_sync_cfg_data_ch2_0[116], ux_toolbox_u0__o_sync_cfg_data_ch2_0[115], ux_toolbox_u0__o_sync_cfg_data_ch2_0[114], ux_toolbox_u0__o_sync_cfg_data_ch2_0[113], ux_toolbox_u0__o_sync_cfg_data_ch2_0[112], ux_toolbox_u0__o_sync_cfg_data_ch2_0[111], ux_toolbox_u0__o_sync_cfg_data_ch2_0[110], ux_toolbox_u0__o_sync_cfg_data_ch2_0[109], ux_toolbox_u0__o_sync_cfg_data_ch2_0[108], ux_toolbox_u0__o_sync_cfg_data_ch2_0[107], ux_toolbox_u0__o_sync_cfg_data_ch2_0[106], ux_toolbox_u0__o_sync_cfg_data_ch2_0[105], ux_toolbox_u0__o_sync_cfg_data_ch2_0[104], ux_toolbox_u0__o_sync_cfg_data_ch2_0[103], ux_toolbox_u0__o_sync_cfg_data_ch2_0[102], ux_toolbox_u0__o_sync_cfg_data_ch2_0[101], ux_toolbox_u0__o_sync_cfg_data_ch2_0[100], ux_toolbox_u0__o_sync_cfg_data_ch2_0[99], ux_toolbox_u0__o_sync_cfg_data_ch2_0[98], ux_toolbox_u0__o_sync_cfg_data_ch2_0[97], ux_toolbox_u0__o_sync_cfg_data_ch2_0[96], ux_toolbox_u0__o_sync_cfg_data_ch2_0[95], ux_toolbox_u0__o_sync_cfg_data_ch2_0[94], ux_toolbox_u0__o_sync_cfg_data_ch2_0[93], ux_toolbox_u0__o_sync_cfg_data_ch2_0[92], ux_toolbox_u0__o_sync_cfg_data_ch2_0[91], ux_toolbox_u0__o_sync_cfg_data_ch2_0[90], ux_toolbox_u0__o_sync_cfg_data_ch2_0[89], ux_toolbox_u0__o_sync_cfg_data_ch2_0[88], ux_toolbox_u0__o_sync_cfg_data_ch2_0[87], ux_toolbox_u0__o_sync_cfg_data_ch2_0[86], ux_toolbox_u0__o_sync_cfg_data_ch2_0[85], ux_toolbox_u0__o_sync_cfg_data_ch2_0[84], ux_toolbox_u0__o_sync_cfg_data_ch2_0[83], ux_toolbox_u0__o_sync_cfg_data_ch2_0[82], ux_toolbox_u0__o_sync_cfg_data_ch2_0[81], ux_toolbox_u0__o_sync_cfg_data_ch2_0[80], ux_toolbox_u0__o_sync_cfg_data_ch2_0[79], ux_toolbox_u0__o_sync_cfg_data_ch2_0[78], ux_toolbox_u0__o_sync_cfg_data_ch2_0[77], ux_toolbox_u0__o_sync_cfg_data_ch2_0[76], ux_toolbox_u0__o_sync_cfg_data_ch2_0[75], ux_toolbox_u0__o_sync_cfg_data_ch2_0[74], ux_toolbox_u0__o_sync_cfg_data_ch2_0[73], ux_toolbox_u0__o_sync_cfg_data_ch2_0[72], ux_toolbox_u0__o_sync_cfg_data_ch2_0[71], ux_toolbox_u0__o_sync_cfg_data_ch2_0[70], ux_toolbox_u0__o_sync_cfg_data_ch2_0[69], ux_toolbox_u0__o_sync_cfg_data_ch2_0[68], ux_toolbox_u0__o_sync_cfg_data_ch2_0[67], ux_toolbox_u0__o_sync_cfg_data_ch2_0[66], ux_toolbox_u0__o_sync_cfg_data_ch2_0[65], ux_toolbox_u0__o_sync_cfg_data_ch2_0[64], ux_toolbox_u0__o_sync_cfg_data_ch2_0[63], ux_toolbox_u0__o_sync_cfg_data_ch2_0[62], ux_toolbox_u0__o_sync_cfg_data_ch2_0[61], ux_toolbox_u0__o_sync_cfg_data_ch2_0[60], ux_toolbox_u0__o_sync_cfg_data_ch2_0[59], ux_toolbox_u0__o_sync_cfg_data_ch2_0[58], ux_toolbox_u0__o_sync_cfg_data_ch2_0[57], ux_toolbox_u0__o_sync_cfg_data_ch2_0[56], ux_toolbox_u0__o_sync_cfg_data_ch2_0[55], ux_toolbox_u0__o_sync_cfg_data_ch2_0[54], ux_toolbox_u0__o_sync_cfg_data_ch2_0[53], ux_toolbox_u0__o_sync_cfg_data_ch2_0[52], ux_toolbox_u0__o_sync_cfg_data_ch2_0[51], ux_toolbox_u0__o_sync_cfg_data_ch2_0[50], ux_toolbox_u0__o_sync_cfg_data_ch2_0[49], ux_toolbox_u0__o_sync_cfg_data_ch2_0[48], ux_toolbox_u0__o_sync_cfg_data_ch2_0[47], ux_toolbox_u0__o_sync_cfg_data_ch2_0[46], ux_toolbox_u0__o_sync_cfg_data_ch2_0[45], ux_toolbox_u0__o_sync_cfg_data_ch2_0[44], ux_toolbox_u0__o_sync_cfg_data_ch2_0[43], ux_toolbox_u0__o_sync_cfg_data_ch2_0[42], ux_toolbox_u0__o_sync_cfg_data_ch2_0[41], ux_toolbox_u0__o_sync_cfg_data_ch2_0[40], ux_toolbox_u0__o_sync_cfg_data_ch2_0[39], ux_toolbox_u0__o_sync_cfg_data_ch2_0[38], ux_toolbox_u0__o_sync_cfg_data_ch2_0[37], ux_toolbox_u0__o_sync_cfg_data_ch2_0[36], ux_toolbox_u0__o_sync_cfg_data_ch2_0[35], ux_toolbox_u0__o_sync_cfg_data_ch2_0[34], ux_toolbox_u0__o_sync_cfg_data_ch2_0[33], ux_toolbox_u0__o_sync_cfg_data_ch2_0[32], ux_toolbox_u0__o_sync_cfg_data_ch2_0[31], ux_toolbox_u0__o_sync_cfg_data_ch2_0[30], ux_toolbox_u0__o_sync_cfg_data_ch2_0[29], ux_toolbox_u0__o_sync_cfg_data_ch2_0[28], ux_toolbox_u0__o_sync_cfg_data_ch2_0[27], ux_toolbox_u0__o_sync_cfg_data_ch2_0[26], ux_toolbox_u0__o_sync_cfg_data_ch2_0[25], ux_toolbox_u0__o_sync_cfg_data_ch2_0[24], ux_toolbox_u0__o_sync_cfg_data_ch2_0[23], ux_toolbox_u0__o_sync_cfg_data_ch2_0[22], ux_toolbox_u0__o_sync_cfg_data_ch2_0[21], ux_toolbox_u0__o_sync_cfg_data_ch2_0[20], ux_toolbox_u0__o_sync_cfg_data_ch2_0[19], ux_toolbox_u0__o_sync_cfg_data_ch2_0[18], ux_toolbox_u0__o_sync_cfg_data_ch2_0[17], ux_toolbox_u0__o_sync_cfg_data_ch2_0[16], ux_toolbox_u0__o_sync_cfg_data_ch2_0[15], ux_toolbox_u0__o_sync_cfg_data_ch2_0[14], ux_toolbox_u0__o_sync_cfg_data_ch2_0[13], ux_toolbox_u0__o_sync_cfg_data_ch2_0[12], ux_toolbox_u0__o_sync_cfg_data_ch2_0[11], ux_toolbox_u0__o_sync_cfg_data_ch2_0[10], ux_toolbox_u0__o_sync_cfg_data_ch2_0[9], ux_toolbox_u0__o_sync_cfg_data_ch2_0[8], ux_toolbox_u0__o_sync_cfg_data_ch2_0[7], ux_toolbox_u0__o_sync_cfg_data_ch2_0[6], ux_toolbox_u0__o_sync_cfg_data_ch2_0[5], ux_toolbox_u0__o_sync_cfg_data_ch2_0[4], ux_toolbox_u0__o_sync_cfg_data_ch2_0[3], ux_toolbox_u0__o_sync_cfg_data_ch2_0[2], ux_toolbox_u0__o_sync_cfg_data_ch2_0[1], ux_toolbox_u0__o_sync_cfg_data_ch2_0[0] }),
		.i_sync_common_control({ ux_toolbox_u0__o_sync_common_control_ch2_0[4], ux_toolbox_u0__o_sync_common_control_ch2_0[3], ux_toolbox_u0__o_sync_common_control_ch2_0[2], ux_toolbox_u0__o_sync_common_control_ch2_0[1], ux_toolbox_u0__o_sync_common_control_ch2_0[0] }),
		.i_sync_interface_control({ ux_toolbox_u0__o_sync_interface_control_ch2_0[249], ux_toolbox_u0__o_sync_interface_control_ch2_0[248], ux_toolbox_u0__o_sync_interface_control_ch2_0[247], ux_toolbox_u0__o_sync_interface_control_ch2_0[246], ux_toolbox_u0__o_sync_interface_control_ch2_0[245], ux_toolbox_u0__o_sync_interface_control_ch2_0[244], ux_toolbox_u0__o_sync_interface_control_ch2_0[243], ux_toolbox_u0__o_sync_interface_control_ch2_0[242], ux_toolbox_u0__o_sync_interface_control_ch2_0[241], ux_toolbox_u0__o_sync_interface_control_ch2_0[240], ux_toolbox_u0__o_sync_interface_control_ch2_0[239], ux_toolbox_u0__o_sync_interface_control_ch2_0[238], ux_toolbox_u0__o_sync_interface_control_ch2_0[237], ux_toolbox_u0__o_sync_interface_control_ch2_0[236], ux_toolbox_u0__o_sync_interface_control_ch2_0[235], ux_toolbox_u0__o_sync_interface_control_ch2_0[234], ux_toolbox_u0__o_sync_interface_control_ch2_0[233], ux_toolbox_u0__o_sync_interface_control_ch2_0[232], ux_toolbox_u0__o_sync_interface_control_ch2_0[231], ux_toolbox_u0__o_sync_interface_control_ch2_0[230], ux_toolbox_u0__o_sync_interface_control_ch2_0[229], ux_toolbox_u0__o_sync_interface_control_ch2_0[228], ux_toolbox_u0__o_sync_interface_control_ch2_0[227], ux_toolbox_u0__o_sync_interface_control_ch2_0[226], ux_toolbox_u0__o_sync_interface_control_ch2_0[225], ux_toolbox_u0__o_sync_interface_control_ch2_0[224], ux_toolbox_u0__o_sync_interface_control_ch2_0[223], ux_toolbox_u0__o_sync_interface_control_ch2_0[222], ux_toolbox_u0__o_sync_interface_control_ch2_0[221], ux_toolbox_u0__o_sync_interface_control_ch2_0[220], ux_toolbox_u0__o_sync_interface_control_ch2_0[219], ux_toolbox_u0__o_sync_interface_control_ch2_0[218], ux_toolbox_u0__o_sync_interface_control_ch2_0[217], ux_toolbox_u0__o_sync_interface_control_ch2_0[216], ux_toolbox_u0__o_sync_interface_control_ch2_0[215], ux_toolbox_u0__o_sync_interface_control_ch2_0[214], ux_toolbox_u0__o_sync_interface_control_ch2_0[213], ux_toolbox_u0__o_sync_interface_control_ch2_0[212], ux_toolbox_u0__o_sync_interface_control_ch2_0[211], ux_toolbox_u0__o_sync_interface_control_ch2_0[210], ux_toolbox_u0__o_sync_interface_control_ch2_0[209], ux_toolbox_u0__o_sync_interface_control_ch2_0[208], ux_toolbox_u0__o_sync_interface_control_ch2_0[207], ux_toolbox_u0__o_sync_interface_control_ch2_0[206], ux_toolbox_u0__o_sync_interface_control_ch2_0[205], ux_toolbox_u0__o_sync_interface_control_ch2_0[204], ux_toolbox_u0__o_sync_interface_control_ch2_0[203], ux_toolbox_u0__o_sync_interface_control_ch2_0[202], ux_toolbox_u0__o_sync_interface_control_ch2_0[201], ux_toolbox_u0__o_sync_interface_control_ch2_0[200], ux_toolbox_u0__o_sync_interface_control_ch2_0[199], ux_toolbox_u0__o_sync_interface_control_ch2_0[198], ux_toolbox_u0__o_sync_interface_control_ch2_0[197], ux_toolbox_u0__o_sync_interface_control_ch2_0[196], ux_toolbox_u0__o_sync_interface_control_ch2_0[195], ux_toolbox_u0__o_sync_interface_control_ch2_0[194], ux_toolbox_u0__o_sync_interface_control_ch2_0[193], ux_toolbox_u0__o_sync_interface_control_ch2_0[192], ux_toolbox_u0__o_sync_interface_control_ch2_0[191], ux_toolbox_u0__o_sync_interface_control_ch2_0[190], ux_toolbox_u0__o_sync_interface_control_ch2_0[189], ux_toolbox_u0__o_sync_interface_control_ch2_0[188], ux_toolbox_u0__o_sync_interface_control_ch2_0[187], ux_toolbox_u0__o_sync_interface_control_ch2_0[186], ux_toolbox_u0__o_sync_interface_control_ch2_0[185], ux_toolbox_u0__o_sync_interface_control_ch2_0[184], ux_toolbox_u0__o_sync_interface_control_ch2_0[183], ux_toolbox_u0__o_sync_interface_control_ch2_0[182], ux_toolbox_u0__o_sync_interface_control_ch2_0[181], ux_toolbox_u0__o_sync_interface_control_ch2_0[180], ux_toolbox_u0__o_sync_interface_control_ch2_0[179], ux_toolbox_u0__o_sync_interface_control_ch2_0[178], ux_toolbox_u0__o_sync_interface_control_ch2_0[177], ux_toolbox_u0__o_sync_interface_control_ch2_0[176], ux_toolbox_u0__o_sync_interface_control_ch2_0[175], ux_toolbox_u0__o_sync_interface_control_ch2_0[174], ux_toolbox_u0__o_sync_interface_control_ch2_0[173], ux_toolbox_u0__o_sync_interface_control_ch2_0[172], ux_toolbox_u0__o_sync_interface_control_ch2_0[171], ux_toolbox_u0__o_sync_interface_control_ch2_0[170], ux_toolbox_u0__o_sync_interface_control_ch2_0[169], ux_toolbox_u0__o_sync_interface_control_ch2_0[168], ux_toolbox_u0__o_sync_interface_control_ch2_0[167], ux_toolbox_u0__o_sync_interface_control_ch2_0[166], ux_toolbox_u0__o_sync_interface_control_ch2_0[165], ux_toolbox_u0__o_sync_interface_control_ch2_0[164], ux_toolbox_u0__o_sync_interface_control_ch2_0[163], ux_toolbox_u0__o_sync_interface_control_ch2_0[162], ux_toolbox_u0__o_sync_interface_control_ch2_0[161], ux_toolbox_u0__o_sync_interface_control_ch2_0[160], ux_toolbox_u0__o_sync_interface_control_ch2_0[159], ux_toolbox_u0__o_sync_interface_control_ch2_0[158], ux_toolbox_u0__o_sync_interface_control_ch2_0[157], ux_toolbox_u0__o_sync_interface_control_ch2_0[156], ux_toolbox_u0__o_sync_interface_control_ch2_0[155], ux_toolbox_u0__o_sync_interface_control_ch2_0[154], ux_toolbox_u0__o_sync_interface_control_ch2_0[153], ux_toolbox_u0__o_sync_interface_control_ch2_0[152], ux_toolbox_u0__o_sync_interface_control_ch2_0[151], ux_toolbox_u0__o_sync_interface_control_ch2_0[150], ux_toolbox_u0__o_sync_interface_control_ch2_0[149], ux_toolbox_u0__o_sync_interface_control_ch2_0[148], ux_toolbox_u0__o_sync_interface_control_ch2_0[147], ux_toolbox_u0__o_sync_interface_control_ch2_0[146], ux_toolbox_u0__o_sync_interface_control_ch2_0[145], ux_toolbox_u0__o_sync_interface_control_ch2_0[144], ux_toolbox_u0__o_sync_interface_control_ch2_0[143], ux_toolbox_u0__o_sync_interface_control_ch2_0[142], ux_toolbox_u0__o_sync_interface_control_ch2_0[141], ux_toolbox_u0__o_sync_interface_control_ch2_0[140], ux_toolbox_u0__o_sync_interface_control_ch2_0[139], ux_toolbox_u0__o_sync_interface_control_ch2_0[138], ux_toolbox_u0__o_sync_interface_control_ch2_0[137], ux_toolbox_u0__o_sync_interface_control_ch2_0[136], ux_toolbox_u0__o_sync_interface_control_ch2_0[135], ux_toolbox_u0__o_sync_interface_control_ch2_0[134], ux_toolbox_u0__o_sync_interface_control_ch2_0[133], ux_toolbox_u0__o_sync_interface_control_ch2_0[132], ux_toolbox_u0__o_sync_interface_control_ch2_0[131], ux_toolbox_u0__o_sync_interface_control_ch2_0[130], ux_toolbox_u0__o_sync_interface_control_ch2_0[129], ux_toolbox_u0__o_sync_interface_control_ch2_0[128], ux_toolbox_u0__o_sync_interface_control_ch2_0[127], ux_toolbox_u0__o_sync_interface_control_ch2_0[126], ux_toolbox_u0__o_sync_interface_control_ch2_0[125], ux_toolbox_u0__o_sync_interface_control_ch2_0[124], ux_toolbox_u0__o_sync_interface_control_ch2_0[123], ux_toolbox_u0__o_sync_interface_control_ch2_0[122], ux_toolbox_u0__o_sync_interface_control_ch2_0[121], ux_toolbox_u0__o_sync_interface_control_ch2_0[120], ux_toolbox_u0__o_sync_interface_control_ch2_0[119], ux_toolbox_u0__o_sync_interface_control_ch2_0[118], ux_toolbox_u0__o_sync_interface_control_ch2_0[117], ux_toolbox_u0__o_sync_interface_control_ch2_0[116], ux_toolbox_u0__o_sync_interface_control_ch2_0[115], ux_toolbox_u0__o_sync_interface_control_ch2_0[114], ux_toolbox_u0__o_sync_interface_control_ch2_0[113], ux_toolbox_u0__o_sync_interface_control_ch2_0[112], ux_toolbox_u0__o_sync_interface_control_ch2_0[111], ux_toolbox_u0__o_sync_interface_control_ch2_0[110], ux_toolbox_u0__o_sync_interface_control_ch2_0[109], ux_toolbox_u0__o_sync_interface_control_ch2_0[108], ux_toolbox_u0__o_sync_interface_control_ch2_0[107], ux_toolbox_u0__o_sync_interface_control_ch2_0[106], ux_toolbox_u0__o_sync_interface_control_ch2_0[105], ux_toolbox_u0__o_sync_interface_control_ch2_0[104], ux_toolbox_u0__o_sync_interface_control_ch2_0[103], ux_toolbox_u0__o_sync_interface_control_ch2_0[102], ux_toolbox_u0__o_sync_interface_control_ch2_0[101], ux_toolbox_u0__o_sync_interface_control_ch2_0[100], ux_toolbox_u0__o_sync_interface_control_ch2_0[99], ux_toolbox_u0__o_sync_interface_control_ch2_0[98], ux_toolbox_u0__o_sync_interface_control_ch2_0[97], ux_toolbox_u0__o_sync_interface_control_ch2_0[96], ux_toolbox_u0__o_sync_interface_control_ch2_0[95], ux_toolbox_u0__o_sync_interface_control_ch2_0[94], ux_toolbox_u0__o_sync_interface_control_ch2_0[93], ux_toolbox_u0__o_sync_interface_control_ch2_0[92], ux_toolbox_u0__o_sync_interface_control_ch2_0[91], ux_toolbox_u0__o_sync_interface_control_ch2_0[90], ux_toolbox_u0__o_sync_interface_control_ch2_0[89], ux_toolbox_u0__o_sync_interface_control_ch2_0[88], ux_toolbox_u0__o_sync_interface_control_ch2_0[87], ux_toolbox_u0__o_sync_interface_control_ch2_0[86], ux_toolbox_u0__o_sync_interface_control_ch2_0[85], ux_toolbox_u0__o_sync_interface_control_ch2_0[84], ux_toolbox_u0__o_sync_interface_control_ch2_0[83], ux_toolbox_u0__o_sync_interface_control_ch2_0[82], ux_toolbox_u0__o_sync_interface_control_ch2_0[81], ux_toolbox_u0__o_sync_interface_control_ch2_0[80], ux_toolbox_u0__o_sync_interface_control_ch2_0[79], ux_toolbox_u0__o_sync_interface_control_ch2_0[78], ux_toolbox_u0__o_sync_interface_control_ch2_0[77], ux_toolbox_u0__o_sync_interface_control_ch2_0[76], ux_toolbox_u0__o_sync_interface_control_ch2_0[75], ux_toolbox_u0__o_sync_interface_control_ch2_0[74], ux_toolbox_u0__o_sync_interface_control_ch2_0[73], ux_toolbox_u0__o_sync_interface_control_ch2_0[72], ux_toolbox_u0__o_sync_interface_control_ch2_0[71], ux_toolbox_u0__o_sync_interface_control_ch2_0[70], ux_toolbox_u0__o_sync_interface_control_ch2_0[69], ux_toolbox_u0__o_sync_interface_control_ch2_0[68], ux_toolbox_u0__o_sync_interface_control_ch2_0[67], ux_toolbox_u0__o_sync_interface_control_ch2_0[66], ux_toolbox_u0__o_sync_interface_control_ch2_0[65], ux_toolbox_u0__o_sync_interface_control_ch2_0[64], ux_toolbox_u0__o_sync_interface_control_ch2_0[63], ux_toolbox_u0__o_sync_interface_control_ch2_0[62], ux_toolbox_u0__o_sync_interface_control_ch2_0[61], ux_toolbox_u0__o_sync_interface_control_ch2_0[60], ux_toolbox_u0__o_sync_interface_control_ch2_0[59], ux_toolbox_u0__o_sync_interface_control_ch2_0[58], ux_toolbox_u0__o_sync_interface_control_ch2_0[57], ux_toolbox_u0__o_sync_interface_control_ch2_0[56], ux_toolbox_u0__o_sync_interface_control_ch2_0[55], ux_toolbox_u0__o_sync_interface_control_ch2_0[54], ux_toolbox_u0__o_sync_interface_control_ch2_0[53], ux_toolbox_u0__o_sync_interface_control_ch2_0[52], ux_toolbox_u0__o_sync_interface_control_ch2_0[51], ux_toolbox_u0__o_sync_interface_control_ch2_0[50], ux_toolbox_u0__o_sync_interface_control_ch2_0[49], ux_toolbox_u0__o_sync_interface_control_ch2_0[48], ux_toolbox_u0__o_sync_interface_control_ch2_0[47], ux_toolbox_u0__o_sync_interface_control_ch2_0[46], ux_toolbox_u0__o_sync_interface_control_ch2_0[45], ux_toolbox_u0__o_sync_interface_control_ch2_0[44], ux_toolbox_u0__o_sync_interface_control_ch2_0[43], ux_toolbox_u0__o_sync_interface_control_ch2_0[42], ux_toolbox_u0__o_sync_interface_control_ch2_0[41], ux_toolbox_u0__o_sync_interface_control_ch2_0[40], ux_toolbox_u0__o_sync_interface_control_ch2_0[39], ux_toolbox_u0__o_sync_interface_control_ch2_0[38], ux_toolbox_u0__o_sync_interface_control_ch2_0[37], ux_toolbox_u0__o_sync_interface_control_ch2_0[36], ux_toolbox_u0__o_sync_interface_control_ch2_0[35], ux_toolbox_u0__o_sync_interface_control_ch2_0[34], ux_toolbox_u0__o_sync_interface_control_ch2_0[33], ux_toolbox_u0__o_sync_interface_control_ch2_0[32], ux_toolbox_u0__o_sync_interface_control_ch2_0[31], ux_toolbox_u0__o_sync_interface_control_ch2_0[30], ux_toolbox_u0__o_sync_interface_control_ch2_0[29], ux_toolbox_u0__o_sync_interface_control_ch2_0[28], ux_toolbox_u0__o_sync_interface_control_ch2_0[27], ux_toolbox_u0__o_sync_interface_control_ch2_0[26], ux_toolbox_u0__o_sync_interface_control_ch2_0[25], ux_toolbox_u0__o_sync_interface_control_ch2_0[24], ux_toolbox_u0__o_sync_interface_control_ch2_0[23], ux_toolbox_u0__o_sync_interface_control_ch2_0[22], ux_toolbox_u0__o_sync_interface_control_ch2_0[21], ux_toolbox_u0__o_sync_interface_control_ch2_0[20], ux_toolbox_u0__o_sync_interface_control_ch2_0[19], ux_toolbox_u0__o_sync_interface_control_ch2_0[18], ux_toolbox_u0__o_sync_interface_control_ch2_0[17], ux_toolbox_u0__o_sync_interface_control_ch2_0[16], ux_toolbox_u0__o_sync_interface_control_ch2_0[15], ux_toolbox_u0__o_sync_interface_control_ch2_0[14], ux_toolbox_u0__o_sync_interface_control_ch2_0[13], ux_toolbox_u0__o_sync_interface_control_ch2_0[12], ux_toolbox_u0__o_sync_interface_control_ch2_0[11], ux_toolbox_u0__o_sync_interface_control_ch2_0[10], ux_toolbox_u0__o_sync_interface_control_ch2_0[9], ux_toolbox_u0__o_sync_interface_control_ch2_0[8], ux_toolbox_u0__o_sync_interface_control_ch2_0[7], ux_toolbox_u0__o_sync_interface_control_ch2_0[6], ux_toolbox_u0__o_sync_interface_control_ch2_0[5], ux_toolbox_u0__o_sync_interface_control_ch2_0[4], ux_toolbox_u0__o_sync_interface_control_ch2_0[3], ux_toolbox_u0__o_sync_interface_control_ch2_0[2], ux_toolbox_u0__o_sync_interface_control_ch2_0[1], ux_toolbox_u0__o_sync_interface_control_ch2_0[0] }),
		.i_tstbus_lane(o_uxq2_tstbus_lane_0),
		.i_tx_data({ o_tx_data_2[39], o_tx_data_2[38], o_tx_data_2[37], o_tx_data_2[36], o_tx_data_2[35], o_tx_data_2[34], o_tx_data_2[33], o_tx_data_2[32], o_tx_data_2[31], o_tx_data_2[30], o_tx_data_2[29], o_tx_data_2[28], o_tx_data_2[27], o_tx_data_2[26], o_tx_data_2[25], o_tx_data_2[24], o_tx_data_2[23], o_tx_data_2[22], o_tx_data_2[21], o_tx_data_2[20], o_tx_data_2[19], o_tx_data_2[18], o_tx_data_2[17], o_tx_data_2[16], o_tx_data_2[15], o_tx_data_2[14], o_tx_data_2[13], o_tx_data_2[12], o_tx_data_2[11], o_tx_data_2[10], o_tx_data_2[9], o_tx_data_2[8], o_tx_data_2[7], o_tx_data_2[6], o_tx_data_2[5], o_tx_data_2[4], o_tx_data_2[3], o_tx_data_2[2], o_tx_data_2[1], o_tx_data_2[0] }),
		.i_tx_dl_ch_bit(o_tx_dl_ch2_bit_0),
		.i_txbeacona(o_uxq2_txbeacona_0),
		.i_txclkdivrate({ o_uxq2_txclkdivrate_0[2], o_uxq2_txclkdivrate_0[1], o_uxq2_txclkdivrate_0[0] }),
		.i_txdetectrx_reqa(o_uxq2_txdetectrx_reqa_0),
		.i_txdrv_levn({ o_uxq2_txdrv_levn_0[5], o_uxq2_txdrv_levn_0[4], o_uxq2_txdrv_levn_0[3], o_uxq2_txdrv_levn_0[2], o_uxq2_txdrv_levn_0[1], o_uxq2_txdrv_levn_0[0] }),
		.i_txdrv_levnm1({ o_uxq2_txdrv_levnm1_0[4], o_uxq2_txdrv_levnm1_0[3], o_uxq2_txdrv_levnm1_0[2], o_uxq2_txdrv_levnm1_0[1], o_uxq2_txdrv_levnm1_0[0] }),
		.i_txdrv_levnm2({ o_uxq2_txdrv_levnm2_0[2], o_uxq2_txdrv_levnm2_0[1], o_uxq2_txdrv_levnm2_0[0] }),
		.i_txdrv_levnp1({ o_uxq2_txdrv_levnp1_0[4], o_uxq2_txdrv_levnp1_0[3], o_uxq2_txdrv_levnp1_0[2], o_uxq2_txdrv_levnp1_0[1], o_uxq2_txdrv_levnp1_0[0] }),
		.i_txdrv_slew({ o_uxq2_txdrv_slew_0[3], o_uxq2_txdrv_slew_0[2], o_uxq2_txdrv_slew_0[1], o_uxq2_txdrv_slew_0[0] }),
		.i_txelecidle({ o_uxq2_txelecidle_0[3], o_uxq2_txelecidle_0[2], o_uxq2_txelecidle_0[1], o_uxq2_txelecidle_0[0] }),
		.i_txpstate({ o_uxq2_txpstate_0[2], o_uxq2_txpstate_0[1], o_uxq2_txpstate_0[0] }),
		.i_txrate({ o_uxq2_txrate_0[3], o_uxq2_txrate_0[2], o_uxq2_txrate_0[1], o_uxq2_txrate_0[0] }),
		.i_txwidth({ o_uxq2_txwidth_0[2], o_uxq2_txwidth_0[1], o_uxq2_txwidth_0[0] }),
		.i_ux_rxuser1_sel({ ux_toolbox_u0__o_ux2_rxuser1_sel_0[1], ux_toolbox_u0__o_ux2_rxuser1_sel_0[0] }),
		.i_ux_rxuser2_sel({ ux_toolbox_u0__o_ux2_rxuser2_sel_0[1], ux_toolbox_u0__o_ux2_rxuser2_sel_0[0] }),
		.i_ux_tx_sync_data({ o_ux_tx_ch2_sync_data_1[6], o_ux_tx_ch2_sync_data_1[5], o_ux_tx_ch2_sync_data_1[4], o_ux_tx_ch2_sync_data_1[3], o_ux_tx_ch2_sync_data_1[2], o_ux_tx_ch2_sync_data_1[1], o_ux_tx_ch2_sync_data_1[0] }),
		.i_ux_txuser1_sel({ ux_toolbox_u0__o_ux2_txuser1_sel_0[1], ux_toolbox_u0__o_ux2_txuser1_sel_0[0] }),
		.i_ux_txuser2_sel({ ux_toolbox_u0__o_ux2_txuser2_sel_0[1], ux_toolbox_u0__o_ux2_txuser2_sel_0[0] }),
		.o_dat_pcs_measlatrndtripbit(flux_ingress_u2__o_dat_pcs_measlatrndtripbit_0),
		.o_ft_rx_async_pulse_ch(o_ft_eth_rx_async_pulse_ch2_1),
		.o_ft_rx_sclk_sync_ch(flux_ingress_u2__o_ft_rx_sclk_sync_ch_0),
		.o_ft_tx_async_pulse_ch(o_ft_eth_tx_async_pulse_ch2_1),
		.o_ft_tx_sclk_sync_ch(flux_ingress_u2__o_ft_tx_sclk_sync_ch_0),
		.o_ick_pcs_txword(o_pcs_txword_ch2_0),
		.o_ick_sclk_rx(flux_ingress_u2__o_ick_sclk_rx_0),
		.o_ick_sclk_tx(o_ick_sclk_tx_ch2_0),
		.o_lavmm_addr({ flux_ingress_u2__o_lavmm_addr_0[19], flux_ingress_u2__o_lavmm_addr_0[18], flux_ingress_u2__o_lavmm_addr_0[17], flux_ingress_u2__o_lavmm_addr_0[16], flux_ingress_u2__o_lavmm_addr_0[15], flux_ingress_u2__o_lavmm_addr_0[14], flux_ingress_u2__o_lavmm_addr_0[13], flux_ingress_u2__o_lavmm_addr_0[12], flux_ingress_u2__o_lavmm_addr_0[11], flux_ingress_u2__o_lavmm_addr_0[10], flux_ingress_u2__o_lavmm_addr_0[9], flux_ingress_u2__o_lavmm_addr_0[8], flux_ingress_u2__o_lavmm_addr_0[7], flux_ingress_u2__o_lavmm_addr_0[6], flux_ingress_u2__o_lavmm_addr_0[5], flux_ingress_u2__o_lavmm_addr_0[4], flux_ingress_u2__o_lavmm_addr_0[3], flux_ingress_u2__o_lavmm_addr_0[2], flux_ingress_u2__o_lavmm_addr_0[1], flux_ingress_u2__o_lavmm_addr_0[0] }),
		.o_lavmm_be({ flux_ingress_u2__o_lavmm_be_0[3], flux_ingress_u2__o_lavmm_be_0[2], flux_ingress_u2__o_lavmm_be_0[1], flux_ingress_u2__o_lavmm_be_0[0] }),
		.o_lavmm_clk(flux_ingress_u2__o_lavmm_clk_0),
		.o_lavmm_rdata({ o_ch2_lavmm_rdata_1[31], o_ch2_lavmm_rdata_1[30], o_ch2_lavmm_rdata_1[29], o_ch2_lavmm_rdata_1[28], o_ch2_lavmm_rdata_1[27], o_ch2_lavmm_rdata_1[26], o_ch2_lavmm_rdata_1[25], o_ch2_lavmm_rdata_1[24], o_ch2_lavmm_rdata_1[23], o_ch2_lavmm_rdata_1[22], o_ch2_lavmm_rdata_1[21], o_ch2_lavmm_rdata_1[20], o_ch2_lavmm_rdata_1[19], o_ch2_lavmm_rdata_1[18], o_ch2_lavmm_rdata_1[17], o_ch2_lavmm_rdata_1[16], o_ch2_lavmm_rdata_1[15], o_ch2_lavmm_rdata_1[14], o_ch2_lavmm_rdata_1[13], o_ch2_lavmm_rdata_1[12], o_ch2_lavmm_rdata_1[11], o_ch2_lavmm_rdata_1[10], o_ch2_lavmm_rdata_1[9], o_ch2_lavmm_rdata_1[8], o_ch2_lavmm_rdata_1[7], o_ch2_lavmm_rdata_1[6], o_ch2_lavmm_rdata_1[5], o_ch2_lavmm_rdata_1[4], o_ch2_lavmm_rdata_1[3], o_ch2_lavmm_rdata_1[2], o_ch2_lavmm_rdata_1[1], o_ch2_lavmm_rdata_1[0] }),
		.o_lavmm_rdata_valid(o_ch2_lavmm_rdata_valid_1),
		.o_lavmm_read(flux_ingress_u2__o_lavmm_read_0),
		.o_lavmm_rstn(flux_ingress_u2__o_lavmm_rstn_0),
		.o_lavmm_waitreq(o_ch2_lavmm_waitreq_1),
		.o_lavmm_wdata({ flux_ingress_u2__o_lavmm_wdata_0[31], flux_ingress_u2__o_lavmm_wdata_0[30], flux_ingress_u2__o_lavmm_wdata_0[29], flux_ingress_u2__o_lavmm_wdata_0[28], flux_ingress_u2__o_lavmm_wdata_0[27], flux_ingress_u2__o_lavmm_wdata_0[26], flux_ingress_u2__o_lavmm_wdata_0[25], flux_ingress_u2__o_lavmm_wdata_0[24], flux_ingress_u2__o_lavmm_wdata_0[23], flux_ingress_u2__o_lavmm_wdata_0[22], flux_ingress_u2__o_lavmm_wdata_0[21], flux_ingress_u2__o_lavmm_wdata_0[20], flux_ingress_u2__o_lavmm_wdata_0[19], flux_ingress_u2__o_lavmm_wdata_0[18], flux_ingress_u2__o_lavmm_wdata_0[17], flux_ingress_u2__o_lavmm_wdata_0[16], flux_ingress_u2__o_lavmm_wdata_0[15], flux_ingress_u2__o_lavmm_wdata_0[14], flux_ingress_u2__o_lavmm_wdata_0[13], flux_ingress_u2__o_lavmm_wdata_0[12], flux_ingress_u2__o_lavmm_wdata_0[11], flux_ingress_u2__o_lavmm_wdata_0[10], flux_ingress_u2__o_lavmm_wdata_0[9], flux_ingress_u2__o_lavmm_wdata_0[8], flux_ingress_u2__o_lavmm_wdata_0[7], flux_ingress_u2__o_lavmm_wdata_0[6], flux_ingress_u2__o_lavmm_wdata_0[5], flux_ingress_u2__o_lavmm_wdata_0[4], flux_ingress_u2__o_lavmm_wdata_0[3], flux_ingress_u2__o_lavmm_wdata_0[2], flux_ingress_u2__o_lavmm_wdata_0[1], flux_ingress_u2__o_lavmm_wdata_0[0] }),
		.o_lavmm_write(flux_ingress_u2__o_lavmm_write_0),
		.o_ock_pcs_cdrfbclk(x_std_sm_flux_ingress_0__o_ock_pcs_cdrfbclk_1),
		.o_ock_pcs_ref(x_std_sm_flux_ingress_0__o_ock_pcs_ref_1),
		.o_ock_pcs_txword(flux_ingress_u2__o_ock_pcs_txword_0),
		.o_octl_pcs_txstatus_a(flux_ingress_u2__o_octl_pcs_txstatus_a_0),
		.o_pcs_rxpostdiv(flux_ingress_u2__o_pcs_rxpostdiv_0),
		.o_pcs_rxword(flux_ingress_u2__o_pcs_rxword_0),
		.o_rst_flux0_cpi_cmn_busy(o_ch3_rst_flux0_cpi_cmn_busy_2),
		.o_rst_oflux_rx_srds_rdy(o_ch3_rst_oflux_rx_srds_rdy_2),
		.o_rst_ux_all_synthlockstatus(o_ch3_rst_ux_all_synthlockstatus_2),
		.o_rst_ux_rx_pma_rst_n(flux_ingress_u2__o_rst_ux_rx_pma_rst_n_0),
		.o_rst_ux_rxcdrlockstatus(o_ch3_rst_ux_rxcdrlockstatus_2),
		.o_rst_ux_tx_pma_rst_n(flux_ingress_u2__o_rst_ux_tx_pma_rst_n_0),
		.o_rx_data({ flux_mux_wrapper_u2__i_rx_data_0[39], flux_mux_wrapper_u2__i_rx_data_0[38], flux_mux_wrapper_u2__i_rx_data_0[37], flux_mux_wrapper_u2__i_rx_data_0[36], flux_mux_wrapper_u2__i_rx_data_0[35], flux_mux_wrapper_u2__i_rx_data_0[34], flux_mux_wrapper_u2__i_rx_data_0[33], flux_mux_wrapper_u2__i_rx_data_0[32], flux_mux_wrapper_u2__i_rx_data_0[31], flux_mux_wrapper_u2__i_rx_data_0[30], flux_mux_wrapper_u2__i_rx_data_0[29], flux_mux_wrapper_u2__i_rx_data_0[28], flux_mux_wrapper_u2__i_rx_data_0[27], flux_mux_wrapper_u2__i_rx_data_0[26], flux_mux_wrapper_u2__i_rx_data_0[25], flux_mux_wrapper_u2__i_rx_data_0[24], flux_mux_wrapper_u2__i_rx_data_0[23], flux_mux_wrapper_u2__i_rx_data_0[22], flux_mux_wrapper_u2__i_rx_data_0[21], flux_mux_wrapper_u2__i_rx_data_0[20], flux_mux_wrapper_u2__i_rx_data_0[19], flux_mux_wrapper_u2__i_rx_data_0[18], flux_mux_wrapper_u2__i_rx_data_0[17], flux_mux_wrapper_u2__i_rx_data_0[16], flux_mux_wrapper_u2__i_rx_data_0[15], flux_mux_wrapper_u2__i_rx_data_0[14], flux_mux_wrapper_u2__i_rx_data_0[13], flux_mux_wrapper_u2__i_rx_data_0[12], flux_mux_wrapper_u2__i_rx_data_0[11], flux_mux_wrapper_u2__i_rx_data_0[10], flux_mux_wrapper_u2__i_rx_data_0[9], flux_mux_wrapper_u2__i_rx_data_0[8], flux_mux_wrapper_u2__i_rx_data_0[7], flux_mux_wrapper_u2__i_rx_data_0[6], flux_mux_wrapper_u2__i_rx_data_0[5], flux_mux_wrapper_u2__i_rx_data_0[4], flux_mux_wrapper_u2__i_rx_data_0[3], flux_mux_wrapper_u2__i_rx_data_0[2], flux_mux_wrapper_u2__i_rx_data_0[1], flux_mux_wrapper_u2__i_rx_data_0[0] }),
		.o_rx_dl_ch_bit(o_rx_dl_ch2_bit_1),
		.o_rxcdrlock2dataa(o_ch3_rst_ux_rxcdrlock2data_2),
		.o_rxeq_best_eye_vala({ o_pcie_ch2_rxeq_best_eye_vala_1[13], o_pcie_ch2_rxeq_best_eye_vala_1[12], o_pcie_ch2_rxeq_best_eye_vala_1[11], o_pcie_ch2_rxeq_best_eye_vala_1[10], o_pcie_ch2_rxeq_best_eye_vala_1[9], o_pcie_ch2_rxeq_best_eye_vala_1[8], o_pcie_ch2_rxeq_best_eye_vala_1[7], o_pcie_ch2_rxeq_best_eye_vala_1[6], o_pcie_ch2_rxeq_best_eye_vala_1[5], o_pcie_ch2_rxeq_best_eye_vala_1[4], o_pcie_ch2_rxeq_best_eye_vala_1[3], o_pcie_ch2_rxeq_best_eye_vala_1[2], o_pcie_ch2_rxeq_best_eye_vala_1[1], o_pcie_ch2_rxeq_best_eye_vala_1[0] }),
		.o_rxeq_donea(o_pcie_ch2_rxeq_donea_1),
		.o_rxmargin_nacka(o_pcie_ch2_rxmargin_nacka_1),
		.o_rxmargin_status_gray({ o_pcie_ch2_rxmargin_status_gray_a_1[1], o_pcie_ch2_rxmargin_status_gray_a_1[0] }),
		.o_rxmargin_statusa(o_pcie_ch2_rxmargin_statusa_1),
		.o_rxsignaldetect_lfpsa(o_pcie_ch2_rxsignaldetect_lfpsa_1),
		.o_rxsignaldetecta(o_pcie_ch2_rxsignaldetecta_1),
		.o_rxstatusa(o_ch3_rst_ux_octl_pcs_rxstatus_2),
		.o_sclk_return_sel_rx(flux_ingress_u2__o_sclk_return_sel_rx_0),
		.o_sclk_return_sel_tx(flux_ingress_u2__o_sclk_return_sel_tx_0),
		//.o_sm_flux_ingress({ tmp_235, tmp_236, tmp_237, tmp_238, tmp_239, tmp_240, tmp_241, tmp_242, tmp_243, tmp_244, tmp_245, tmp_246, tmp_247, tmp_248, tmp_249, tmp_250, tmp_251, tmp_252, tmp_253, tmp_254, tmp_255, tmp_256, tmp_257, tmp_258, tmp_259, tmp_260, tmp_261, tmp_262, tmp_263, tmp_264, tmp_265, tmp_266, tmp_267, tmp_268, tmp_269, tmp_270, tmp_271, tmp_272, tmp_273, tmp_274, tmp_275, tmp_276, tmp_277, tmp_278, tmp_279, tmp_280, tmp_281, tmp_282, tmp_283, tmp_284, tmp_285, tmp_286, tmp_287, tmp_288, tmp_289, tmp_290, tmp_291, tmp_292, tmp_293, tmp_294, tmp_295, tmp_296, tmp_297, tmp_298, tmp_299, tmp_300, tmp_301, tmp_302, tmp_303, tmp_304, tmp_305, tmp_306, tmp_307, tmp_308, tmp_309, tmp_310, tmp_311, tmp_312, tmp_313, tmp_314, tmp_315, tmp_316, tmp_317, tmp_318, tmp_319, tmp_320, tmp_321, tmp_322, tmp_323, tmp_324, tmp_325, tmp_326, tmp_327, tmp_328, tmp_329, tmp_330, tmp_331, tmp_332, tmp_333, tmp_334, tmp_335, tmp_336, tmp_337, tmp_338, tmp_339, tmp_340, tmp_341, tmp_342, tmp_343, tmp_344, tmp_345, tmp_346, tmp_347, tmp_348, tmp_349, tmp_350, tmp_351, tmp_352, tmp_353, tmp_354, tmp_355, tmp_356, tmp_357, tmp_358, tmp_359, tmp_360, tmp_361, tmp_362, tmp_363, tmp_364, tmp_365, tmp_366, tmp_367, tmp_368, tmp_369, tmp_370, tmp_371, tmp_372, tmp_373, tmp_374, tmp_375, tmp_376, tmp_377, tmp_378, tmp_379, tmp_380, tmp_381, tmp_382, tmp_383, tmp_384, tmp_385, tmp_386, tmp_387, tmp_388, tmp_389, tmp_390, tmp_391, tmp_392, tmp_393, tmp_394, tmp_395, tmp_396, tmp_397, tmp_398, tmp_399, tmp_400, tmp_401, tmp_402, tmp_403, tmp_404, tmp_405, tmp_406, tmp_407, tmp_408, tmp_409, tmp_410, tmp_411, tmp_412, tmp_413, tmp_414, tmp_415, tmp_416, tmp_417, tmp_418, tmp_419, tmp_420, tmp_421, tmp_422, tmp_423, tmp_424, tmp_425, tmp_426, tmp_427, tmp_428, tmp_429, tmp_430, tmp_431, tmp_432, tmp_433, tmp_434, tmp_435, tmp_436, tmp_437, tmp_438, tmp_439, tmp_440, tmp_441, tmp_442, tmp_443, tmp_444, tmp_445, tmp_446, tmp_447, tmp_448, tmp_449, tmp_450, tmp_451, tmp_452, tmp_453, tmp_454, tmp_455, tmp_456, tmp_457, tmp_458, tmp_459, tmp_460, tmp_461, tmp_462, tmp_463, tmp_464, tmp_465, tmp_466, tmp_467, tmp_468, tmp_469, tmp_470, tmp_471, tmp_472, tmp_473, tmp_474, tmp_475, tmp_476, tmp_477, tmp_478, tmp_479, tmp_480, tmp_481, tmp_482, tmp_483, tmp_484, tmp_485, tmp_486, tmp_487, tmp_488, tmp_489, tmp_490, tmp_491, tmp_492, tmp_493, tmp_494, tmp_495, tmp_496, tmp_497, tmp_498, tmp_499, tmp_500, tmp_501, tmp_502, tmp_503, tmp_504, tmp_505, tmp_506, tmp_507, tmp_508, tmp_509, tmp_510, tmp_511, tmp_512, tmp_513, tmp_514, tmp_515, tmp_516, tmp_517, tmp_518, tmp_519, tmp_520, tmp_521, tmp_522, tmp_523, tmp_524, tmp_525, tmp_526, tmp_527, tmp_528, tmp_529, tmp_530, tmp_531, tmp_532, tmp_533, tmp_534, tmp_535, tmp_536, tmp_537, tmp_538, tmp_539, tmp_540, tmp_541, tmp_542, tmp_543, tmp_544, tmp_545, tmp_546, tmp_547, tmp_548, tmp_549, tmp_550, tmp_551, tmp_552, tmp_553, tmp_554 }),
		.o_sm_flux_ingress({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[307], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[306], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[305], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[304], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[303], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[302], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[301], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[300], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[299], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[298], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[297], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[296], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[295], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[294], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[293], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[292], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[291], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[290], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[289], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[288], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[287], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[286], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[285], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[284], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[283], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[282], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[281], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[98], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[97], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[96], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[95], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[94], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[93], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[92], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[91], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[90], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[89], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[88], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[87], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[86], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[0] }),
		.o_ss_async_pldif({ o_ss_async_pldif_ch2_1[49], o_ss_async_pldif_ch2_1[48], o_ss_async_pldif_ch2_1[47], o_ss_async_pldif_ch2_1[46], o_ss_async_pldif_ch2_1[45], o_ss_async_pldif_ch2_1[44], o_ss_async_pldif_ch2_1[43], o_ss_async_pldif_ch2_1[42], o_ss_async_pldif_ch2_1[41], o_ss_async_pldif_ch2_1[40], o_ss_async_pldif_ch2_1[39], o_ss_async_pldif_ch2_1[38], o_ss_async_pldif_ch2_1[37], o_ss_async_pldif_ch2_1[36], o_ss_async_pldif_ch2_1[35], o_ss_async_pldif_ch2_1[34], o_ss_async_pldif_ch2_1[33], o_ss_async_pldif_ch2_1[32], o_ss_async_pldif_ch2_1[31], o_ss_async_pldif_ch2_1[30], o_ss_async_pldif_ch2_1[29], o_ss_async_pldif_ch2_1[28], o_ss_async_pldif_ch2_1[27], o_ss_async_pldif_ch2_1[26], o_ss_async_pldif_ch2_1[25], o_ss_async_pldif_ch2_1[24], o_ss_async_pldif_ch2_1[23], o_ss_async_pldif_ch2_1[22], o_ss_async_pldif_ch2_1[21], o_ss_async_pldif_ch2_1[20], o_ss_async_pldif_ch2_1[19], o_ss_async_pldif_ch2_1[18], o_ss_async_pldif_ch2_1[17], o_ss_async_pldif_ch2_1[16], o_ss_async_pldif_ch2_1[15], o_ss_async_pldif_ch2_1[14], o_ss_async_pldif_ch2_1[13], o_ss_async_pldif_ch2_1[12], o_ss_async_pldif_ch2_1[11], o_ss_async_pldif_ch2_1[10], o_ss_async_pldif_ch2_1[9], o_ss_async_pldif_ch2_1[8], o_ss_async_pldif_ch2_1[7], o_ss_async_pldif_ch2_1[6], o_ss_async_pldif_ch2_1[5], o_ss_async_pldif_ch2_1[4], o_ss_async_pldif_ch2_1[3], o_ss_async_pldif_ch2_1[2], o_ss_async_pldif_ch2_1[1], o_ss_async_pldif_ch2_1[0] }),
		.o_synthlcfast_postdiv(o_pcie_ch2_synthlcfast_postdiv_1),
		.o_synthlcmed_postdiv(o_pcie_ch2_synthlcmed_postdiv_1),
		.o_synthlcslow_postdiv(o_pcie_ch2_synthlcslow_postdiv_1),
		.o_tx_data({ o_flux_pcs_txword_lane2_0[79], o_flux_pcs_txword_lane2_0[78], o_flux_pcs_txword_lane2_0[77], o_flux_pcs_txword_lane2_0[76], o_flux_pcs_txword_lane2_0[75], o_flux_pcs_txword_lane2_0[74], o_flux_pcs_txword_lane2_0[73], o_flux_pcs_txword_lane2_0[72], o_flux_pcs_txword_lane2_0[71], o_flux_pcs_txword_lane2_0[70], o_flux_pcs_txword_lane2_0[69], o_flux_pcs_txword_lane2_0[68], o_flux_pcs_txword_lane2_0[67], o_flux_pcs_txword_lane2_0[66], o_flux_pcs_txword_lane2_0[65], o_flux_pcs_txword_lane2_0[64], o_flux_pcs_txword_lane2_0[63], o_flux_pcs_txword_lane2_0[62], o_flux_pcs_txword_lane2_0[61], o_flux_pcs_txword_lane2_0[60], o_flux_pcs_txword_lane2_0[59], o_flux_pcs_txword_lane2_0[58], o_flux_pcs_txword_lane2_0[57], o_flux_pcs_txword_lane2_0[56], o_flux_pcs_txword_lane2_0[55], o_flux_pcs_txword_lane2_0[54], o_flux_pcs_txword_lane2_0[53], o_flux_pcs_txword_lane2_0[52], o_flux_pcs_txword_lane2_0[51], o_flux_pcs_txword_lane2_0[50], o_flux_pcs_txword_lane2_0[49], o_flux_pcs_txword_lane2_0[48], o_flux_pcs_txword_lane2_0[47], o_flux_pcs_txword_lane2_0[46], o_flux_pcs_txword_lane2_0[45], o_flux_pcs_txword_lane2_0[44], o_flux_pcs_txword_lane2_0[43], o_flux_pcs_txword_lane2_0[42], o_flux_pcs_txword_lane2_0[41], o_flux_pcs_txword_lane2_0[40], o_flux_pcs_txword_lane2_0[39], o_flux_pcs_txword_lane2_0[38], o_flux_pcs_txword_lane2_0[37], o_flux_pcs_txword_lane2_0[36], o_flux_pcs_txword_lane2_0[35], o_flux_pcs_txword_lane2_0[34], o_flux_pcs_txword_lane2_0[33], o_flux_pcs_txword_lane2_0[32], o_flux_pcs_txword_lane2_0[31], o_flux_pcs_txword_lane2_0[30], o_flux_pcs_txword_lane2_0[29], o_flux_pcs_txword_lane2_0[28], o_flux_pcs_txword_lane2_0[27], o_flux_pcs_txword_lane2_0[26], o_flux_pcs_txword_lane2_0[25], o_flux_pcs_txword_lane2_0[24], o_flux_pcs_txword_lane2_0[23], o_flux_pcs_txword_lane2_0[22], o_flux_pcs_txword_lane2_0[21], o_flux_pcs_txword_lane2_0[20], o_flux_pcs_txword_lane2_0[19], o_flux_pcs_txword_lane2_0[18], o_flux_pcs_txword_lane2_0[17], o_flux_pcs_txword_lane2_0[16], o_flux_pcs_txword_lane2_0[15], o_flux_pcs_txword_lane2_0[14], o_flux_pcs_txword_lane2_0[13], o_flux_pcs_txword_lane2_0[12], o_flux_pcs_txword_lane2_0[11], o_flux_pcs_txword_lane2_0[10], o_flux_pcs_txword_lane2_0[9], o_flux_pcs_txword_lane2_0[8], o_flux_pcs_txword_lane2_0[7], o_flux_pcs_txword_lane2_0[6], o_flux_pcs_txword_lane2_0[5], o_flux_pcs_txword_lane2_0[4], o_flux_pcs_txword_lane2_0[3], o_flux_pcs_txword_lane2_0[2], o_flux_pcs_txword_lane2_0[1], o_flux_pcs_txword_lane2_0[0] }),
		.o_tx_dl_ch_bit(ux_toolbox_u0__i_tx_dl_ch2_bit_0),
		.o_txdetectrx_acka(o_pcie_ch2_txdetectrx_acka_1),
		.o_txdetectrx_statct(o_pcie_ch2_txdetectrx_statct_1),
		.o_txstatusa(o_ch3_rst_ux_octl_pcs_txstatus_2),
		.o_ux_rxuser1_sel({ flux_ingress_u2__o_ux_rxuser1_sel_0[1], flux_ingress_u2__o_ux_rxuser1_sel_0[0] }),
		.o_ux_rxuser2_sel({ flux_ingress_u2__o_ux_rxuser2_sel_0[1], flux_ingress_u2__o_ux_rxuser2_sel_0[0] }),
		.o_ux_tx_ch_ptr_smpl(tmp_555),
		.o_ux_txlc_clk(flux_ingress_u2__o_ux_txlc_clk_0),
		.o_ux_txuser1_sel({ flux_ingress_u2__o_ux_txuser1_sel_0[1], flux_ingress_u2__o_ux_txuser1_sel_0[0] }),
		.o_ux_txuser2_sel({ flux_ingress_u2__o_ux_txuser2_sel_0[1], flux_ingress_u2__o_ux_txuser2_sel_0[0] }),
		.o_quartus_connection_to_serdes(o_quartus_connection_to_serdes_lane2_0),
		.i_quartus_flux_s_to_ingress(o_flux_sclk_mux_0)
	);

	tennm_sm_ux_toolbox #(
		.ch0_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_cssm_fw_control),
		.ch0_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch0_clkrx_refclk_sector_specifies_refclk_ready),
		.ch0_dr_enabled(x_std_sm_ux_toolbox_0__ch0_dr_enabled),
		.ch0_flux_mode(x_std_sm_ux_toolbox_0__ch0_flux_mode),
		.ch0_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch0_lc_postdiv_sel),
		.ch0_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch0_local_refclk_cssm_fw_control),
		.ch0_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch0_local_refclk_sector_specifies_refclk_ready),
		.ch0_loopback_mode(x_std_sm_ux_toolbox_0__ch0_loopback_mode),
		.ch0_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch0_rst_mux_static_sel),
		.ch0_rx_dl_enable(x_std_sm_ux_toolbox_0__ch0_rx_dl_enable),
		.ch0_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch0_rx_dl_rx_lat_bit_for_async),
		.ch0_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_cntr_pma),
		.ch0_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch0_rx_dl_rxbit_rollover),
		.ch0_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch0_rx_fec_type_used),
		.ch0_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch0_rx_preloaded_hardware_configs),
		.ch0_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch0_rx_protocol_hint),
		.ch0_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_rx_user1_clk_mux_dynamic_sel),
		.ch0_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_rx_user2_clk_mux_dynamic_sel),
		.ch0_rx_width(x_std_sm_ux_toolbox_0__ch0_rx_width),
		.ch0_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch0_sequencer_reg_en),
		.ch0_tx_bond_size(x_std_sm_ux_toolbox_0__ch0_tx_bond_size),
		.ch0_tx_bonding_category(x_std_sm_ux_toolbox_0__ch0_tx_bonding_category),
		.ch0_tx_dl_enable(x_std_sm_ux_toolbox_0__ch0_tx_dl_enable),
		.ch0_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch0_tx_preloaded_hardware_configs),
		.ch0_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_tx_user1_clk_mux_dynamic_sel),
		.ch0_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch0_tx_user2_clk_mux_dynamic_sel),
		.ch1_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_cssm_fw_control),
		.ch1_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch1_clkrx_refclk_sector_specifies_refclk_ready),
		.ch1_dr_enabled(x_std_sm_ux_toolbox_0__ch1_dr_enabled),
		.ch1_flux_mode(x_std_sm_ux_toolbox_0__ch1_flux_mode),
		.ch1_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch1_lc_postdiv_sel),
		.ch1_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch1_local_refclk_cssm_fw_control),
		.ch1_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch1_local_refclk_sector_specifies_refclk_ready),
		.ch1_loopback_mode(x_std_sm_ux_toolbox_0__ch1_loopback_mode),
		.ch1_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch1_rst_mux_static_sel),
		.ch1_rx_dl_enable(x_std_sm_ux_toolbox_0__ch1_rx_dl_enable),
		.ch1_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch1_rx_dl_rx_lat_bit_for_async),
		.ch1_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_cntr_pma),
		.ch1_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch1_rx_dl_rxbit_rollover),
		.ch1_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch1_rx_fec_type_used),
		.ch1_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch1_rx_preloaded_hardware_configs),
		.ch1_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch1_rx_protocol_hint),
		.ch1_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_rx_user1_clk_mux_dynamic_sel),
		.ch1_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_rx_user2_clk_mux_dynamic_sel),
		.ch1_rx_width(x_std_sm_ux_toolbox_0__ch1_rx_width),
		.ch1_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch1_sequencer_reg_en),
		.ch1_tx_bond_size(x_std_sm_ux_toolbox_0__ch1_tx_bond_size),
		.ch1_tx_bonding_category(x_std_sm_ux_toolbox_0__ch1_tx_bonding_category),
		.ch1_tx_dl_enable(x_std_sm_ux_toolbox_0__ch1_tx_dl_enable),
		.ch1_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch1_tx_preloaded_hardware_configs),
		.ch1_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_tx_user1_clk_mux_dynamic_sel),
		.ch1_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch1_tx_user2_clk_mux_dynamic_sel),
		.ch2_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_cssm_fw_control),
		.ch2_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch2_clkrx_refclk_sector_specifies_refclk_ready),
		.ch2_dr_enabled(x_std_sm_ux_toolbox_0__ch2_dr_enabled),
		.ch2_flux_mode(x_std_sm_ux_toolbox_0__ch2_flux_mode),
		.ch2_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch2_lc_postdiv_sel),
		.ch2_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch2_local_refclk_cssm_fw_control),
		.ch2_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch2_local_refclk_sector_specifies_refclk_ready),
		.ch2_loopback_mode(x_std_sm_ux_toolbox_0__ch2_loopback_mode),
		.ch2_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch2_rst_mux_static_sel),
		.ch2_rx_dl_enable(x_std_sm_ux_toolbox_0__ch2_rx_dl_enable),
		.ch2_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch2_rx_dl_rx_lat_bit_for_async),
		.ch2_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_cntr_pma),
		.ch2_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch2_rx_dl_rxbit_rollover),
		.ch2_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch2_rx_fec_type_used),
		.ch2_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch2_rx_preloaded_hardware_configs),
		.ch2_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch2_rx_protocol_hint),
		.ch2_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_rx_user1_clk_mux_dynamic_sel),
		.ch2_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_rx_user2_clk_mux_dynamic_sel),
		.ch2_rx_width(x_std_sm_ux_toolbox_0__ch2_rx_width),
		.ch2_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch2_sequencer_reg_en),
		.ch2_tx_bond_size(x_std_sm_ux_toolbox_0__ch2_tx_bond_size),
		.ch2_tx_bonding_category(x_std_sm_ux_toolbox_0__ch2_tx_bonding_category),
		.ch2_tx_dl_enable(x_std_sm_ux_toolbox_0__ch2_tx_dl_enable),
		.ch2_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch2_tx_preloaded_hardware_configs),
		.ch2_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_tx_user1_clk_mux_dynamic_sel),
		.ch2_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch2_tx_user2_clk_mux_dynamic_sel),
		.ch3_clkrx_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_cssm_fw_control),
		.ch3_clkrx_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch3_clkrx_refclk_sector_specifies_refclk_ready),
		.ch3_dr_enabled(x_std_sm_ux_toolbox_0__ch3_dr_enabled),
		.ch3_flux_mode(x_std_sm_ux_toolbox_0__ch3_flux_mode),
		.ch3_lc_postdiv_sel(x_std_sm_ux_toolbox_0__ch3_lc_postdiv_sel),
		.ch3_local_refclk_cssm_fw_control(x_std_sm_ux_toolbox_0__ch3_local_refclk_cssm_fw_control),
		.ch3_local_refclk_sector_specifies_refclk_ready(x_std_sm_ux_toolbox_0__ch3_local_refclk_sector_specifies_refclk_ready),
		.ch3_loopback_mode(x_std_sm_ux_toolbox_0__ch3_loopback_mode),
		.ch3_rst_mux_static_sel(x_std_sm_ux_toolbox_0__ch3_rst_mux_static_sel),
		.ch3_rx_dl_enable(x_std_sm_ux_toolbox_0__ch3_rx_dl_enable),
		.ch3_rx_dl_rx_lat_bit_for_async(x_std_sm_ux_toolbox_0__ch3_rx_dl_rx_lat_bit_for_async),
		.ch3_rx_dl_rxbit_cntr_pma(x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_cntr_pma),
		.ch3_rx_dl_rxbit_rollover(x_std_sm_ux_toolbox_0__ch3_rx_dl_rxbit_rollover),
		.ch3_rx_fec_type_used(x_std_sm_ux_toolbox_0__ch3_rx_fec_type_used),
		.ch3_rx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch3_rx_preloaded_hardware_configs),
		.ch3_rx_protocol_hint(x_std_sm_ux_toolbox_0__ch3_rx_protocol_hint),
		.ch3_rx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_rx_user1_clk_mux_dynamic_sel),
		.ch3_rx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_rx_user2_clk_mux_dynamic_sel),
		.ch3_rx_width(x_std_sm_ux_toolbox_0__ch3_rx_width),
		.ch3_sequencer_reg_en(x_std_sm_ux_toolbox_0__ch3_sequencer_reg_en),
		.ch3_tx_bond_size(x_std_sm_ux_toolbox_0__ch3_tx_bond_size),
		.ch3_tx_bonding_category(x_std_sm_ux_toolbox_0__ch3_tx_bonding_category),
		.ch3_tx_dl_enable(x_std_sm_ux_toolbox_0__ch3_tx_dl_enable),
		.ch3_tx_preloaded_hardware_configs(x_std_sm_ux_toolbox_0__ch3_tx_preloaded_hardware_configs),
		.ch3_tx_user1_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_tx_user1_clk_mux_dynamic_sel),
		.ch3_tx_user2_clk_mux_dynamic_sel(x_std_sm_ux_toolbox_0__ch3_tx_user2_clk_mux_dynamic_sel)
	) x_std_sm_ux_toolbox_0 (
		.i_ch0_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch0_lavmm_addr_0[0] }),
		.i_ch0_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch0_lavmm_be_0[0] }),
		.i_ch0_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch0_lavmm_clk_1),
		.i_ch0_lavmm_read(x_std_sm_ux_toolbox_0__i_ch0_lavmm_read_1),
		.i_ch0_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch0_lavmm_rstn_1),
		.i_ch0_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch0_lavmm_wdata_0[0] }),
		.i_ch0_lavmm_write(x_std_sm_ux_toolbox_0__i_ch0_lavmm_write_1),
		.i_ch1_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch1_lavmm_addr_0[0] }),
		.i_ch1_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch1_lavmm_be_0[0] }),
		.i_ch1_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch1_lavmm_clk_1),
		.i_ch1_lavmm_read(x_std_sm_ux_toolbox_0__i_ch1_lavmm_read_1),
		.i_ch1_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch1_lavmm_rstn_1),
		.i_ch1_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch1_lavmm_wdata_0[0] }),
		.i_ch1_lavmm_write(x_std_sm_ux_toolbox_0__i_ch1_lavmm_write_1),
		.i_ch2_lavmm_addr({ flux_ingress_u2__o_lavmm_addr_0[19], flux_ingress_u2__o_lavmm_addr_0[18], flux_ingress_u2__o_lavmm_addr_0[17], flux_ingress_u2__o_lavmm_addr_0[16], flux_ingress_u2__o_lavmm_addr_0[15], flux_ingress_u2__o_lavmm_addr_0[14], flux_ingress_u2__o_lavmm_addr_0[13], flux_ingress_u2__o_lavmm_addr_0[12], flux_ingress_u2__o_lavmm_addr_0[11], flux_ingress_u2__o_lavmm_addr_0[10], flux_ingress_u2__o_lavmm_addr_0[9], flux_ingress_u2__o_lavmm_addr_0[8], flux_ingress_u2__o_lavmm_addr_0[7], flux_ingress_u2__o_lavmm_addr_0[6], flux_ingress_u2__o_lavmm_addr_0[5], flux_ingress_u2__o_lavmm_addr_0[4], flux_ingress_u2__o_lavmm_addr_0[3], flux_ingress_u2__o_lavmm_addr_0[2], flux_ingress_u2__o_lavmm_addr_0[1], flux_ingress_u2__o_lavmm_addr_0[0] }),
		.i_ch2_lavmm_be({ flux_ingress_u2__o_lavmm_be_0[3], flux_ingress_u2__o_lavmm_be_0[2], flux_ingress_u2__o_lavmm_be_0[1], flux_ingress_u2__o_lavmm_be_0[0] }),
		.i_ch2_lavmm_clk(flux_ingress_u2__o_lavmm_clk_0),
		.i_ch2_lavmm_read(flux_ingress_u2__o_lavmm_read_0),
		.i_ch2_lavmm_rstn(flux_ingress_u2__o_lavmm_rstn_0),
		.i_ch2_lavmm_wdata({ flux_ingress_u2__o_lavmm_wdata_0[31], flux_ingress_u2__o_lavmm_wdata_0[30], flux_ingress_u2__o_lavmm_wdata_0[29], flux_ingress_u2__o_lavmm_wdata_0[28], flux_ingress_u2__o_lavmm_wdata_0[27], flux_ingress_u2__o_lavmm_wdata_0[26], flux_ingress_u2__o_lavmm_wdata_0[25], flux_ingress_u2__o_lavmm_wdata_0[24], flux_ingress_u2__o_lavmm_wdata_0[23], flux_ingress_u2__o_lavmm_wdata_0[22], flux_ingress_u2__o_lavmm_wdata_0[21], flux_ingress_u2__o_lavmm_wdata_0[20], flux_ingress_u2__o_lavmm_wdata_0[19], flux_ingress_u2__o_lavmm_wdata_0[18], flux_ingress_u2__o_lavmm_wdata_0[17], flux_ingress_u2__o_lavmm_wdata_0[16], flux_ingress_u2__o_lavmm_wdata_0[15], flux_ingress_u2__o_lavmm_wdata_0[14], flux_ingress_u2__o_lavmm_wdata_0[13], flux_ingress_u2__o_lavmm_wdata_0[12], flux_ingress_u2__o_lavmm_wdata_0[11], flux_ingress_u2__o_lavmm_wdata_0[10], flux_ingress_u2__o_lavmm_wdata_0[9], flux_ingress_u2__o_lavmm_wdata_0[8], flux_ingress_u2__o_lavmm_wdata_0[7], flux_ingress_u2__o_lavmm_wdata_0[6], flux_ingress_u2__o_lavmm_wdata_0[5], flux_ingress_u2__o_lavmm_wdata_0[4], flux_ingress_u2__o_lavmm_wdata_0[3], flux_ingress_u2__o_lavmm_wdata_0[2], flux_ingress_u2__o_lavmm_wdata_0[1], flux_ingress_u2__o_lavmm_wdata_0[0] }),
		.i_ch2_lavmm_write(flux_ingress_u2__o_lavmm_write_0),
		.i_ch3_lavmm_addr({ x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[19], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[18], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[17], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[16], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[15], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[14], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[13], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[12], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[11], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[10], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[9], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[8], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[7], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[6], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[5], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[4], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[3], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[2], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[1], x_std_sm_ux_toolbox_0__i_ch3_lavmm_addr_0[0] }),
		.i_ch3_lavmm_be({ x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[3], x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[2], x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[1], x_std_sm_ux_toolbox_0__i_ch3_lavmm_be_0[0] }),
		.i_ch3_lavmm_clk(x_std_sm_ux_toolbox_0__i_ch3_lavmm_clk_1),
		.i_ch3_lavmm_read(x_std_sm_ux_toolbox_0__i_ch3_lavmm_read_1),
		.i_ch3_lavmm_rstn(x_std_sm_ux_toolbox_0__i_ch3_lavmm_rstn_1),
		.i_ch3_lavmm_wdata({ x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[31], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[30], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[29], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[28], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[27], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[26], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[25], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[24], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[23], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[22], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[21], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[20], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[19], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[18], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[17], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[16], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[15], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[14], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[13], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[12], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[11], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[10], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[9], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[8], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[7], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[6], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[5], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[4], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[3], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[2], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[1], x_std_sm_ux_toolbox_0__i_ch3_lavmm_wdata_0[0] }),
		.i_ch3_lavmm_write(x_std_sm_ux_toolbox_0__i_ch3_lavmm_write_1),
		.i_dat_pcs_measlatrndtripbit_ch0(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch0_1),
		.i_dat_pcs_measlatrndtripbit_ch1(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch1_1),
		.i_dat_pcs_measlatrndtripbit_ch2(flux_ingress_u2__o_dat_pcs_measlatrndtripbit_0),
		.i_dat_pcs_measlatrndtripbit_ch3(x_std_sm_ux_toolbox_0__i_dat_pcs_measlatrndtripbit_ch3_1),
		.i_flux_apb_prdata({ oflux_ext_pcs_prdata_1[31], oflux_ext_pcs_prdata_1[30], oflux_ext_pcs_prdata_1[29], oflux_ext_pcs_prdata_1[28], oflux_ext_pcs_prdata_1[27], oflux_ext_pcs_prdata_1[26], oflux_ext_pcs_prdata_1[25], oflux_ext_pcs_prdata_1[24], oflux_ext_pcs_prdata_1[23], oflux_ext_pcs_prdata_1[22], oflux_ext_pcs_prdata_1[21], oflux_ext_pcs_prdata_1[20], oflux_ext_pcs_prdata_1[19], oflux_ext_pcs_prdata_1[18], oflux_ext_pcs_prdata_1[17], oflux_ext_pcs_prdata_1[16], oflux_ext_pcs_prdata_1[15], oflux_ext_pcs_prdata_1[14], oflux_ext_pcs_prdata_1[13], oflux_ext_pcs_prdata_1[12], oflux_ext_pcs_prdata_1[11], oflux_ext_pcs_prdata_1[10], oflux_ext_pcs_prdata_1[9], oflux_ext_pcs_prdata_1[8], oflux_ext_pcs_prdata_1[7], oflux_ext_pcs_prdata_1[6], oflux_ext_pcs_prdata_1[5], oflux_ext_pcs_prdata_1[4], oflux_ext_pcs_prdata_1[3], oflux_ext_pcs_prdata_1[2], oflux_ext_pcs_prdata_1[1], oflux_ext_pcs_prdata_1[0] }),
		.i_flux_apb_pready(oflux_ext_pcs_pready_1),
		.i_flux_apb_pslverr(oflux_ext_pcs_pslverr_1),
		.i_ft_rx_sclk_sync_ch0(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch0_1),
		.i_ft_rx_sclk_sync_ch1(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch1_1),
		.i_ft_rx_sclk_sync_ch2(flux_ingress_u2__o_ft_rx_sclk_sync_ch_0),
		.i_ft_rx_sclk_sync_ch3(x_std_sm_ux_toolbox_0__i_ft_rx_sclk_sync_ch3_1),
		.i_ft_tx_sclk_sync_ch0(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch0_1),
		.i_ft_tx_sclk_sync_ch1(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch1_1),
		.i_ft_tx_sclk_sync_ch2(flux_ingress_u2__o_ft_tx_sclk_sync_ch_0),
		.i_ft_tx_sclk_sync_ch3(x_std_sm_ux_toolbox_0__i_ft_tx_sclk_sync_ch3_1),
		.i_ick_sclk_rx_ch0(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch0_1),
		.i_ick_sclk_rx_ch1(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch1_1),
		.i_ick_sclk_rx_ch2(flux_ingress_u2__o_ick_sclk_rx_0),
		.i_ick_sclk_rx_ch3(x_std_sm_ux_toolbox_0__i_ick_sclk_rx_ch3_1),
		.i_octl_pcs_txstatus_ch0_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch0_a_1),
		.i_octl_pcs_txstatus_ch1_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch1_a_1),
		.i_octl_pcs_txstatus_ch2_a(flux_ingress_u2__o_octl_pcs_txstatus_a_0),
		.i_octl_pcs_txstatus_ch3_a(x_std_sm_ux_toolbox_0__i_octl_pcs_txstatus_ch3_a_1),
		.i_oflux_cpi_int(oflux_cpi_int_1),
		.i_oflux_int0(oflux_int0_1),
		.i_oflux_int1(oflux_int1_1),
		.i_oflux_int2(oflux_int2_1),
		.i_oflux_int3(oflux_int3_1),
		.i_oflux_srds_rdy0(oflux_srds_rdy0_1),
		.i_oflux_srds_rdy1(oflux_srds_rdy1_1),
		.i_oflux_srds_rdy2(oflux_srds_rdy2_1),
		.i_oflux_srds_rdy3(oflux_srds_rdy3_1),
		.i_pcs_ick_txword_ch0(o_pcs_txword_ch0_0),
		.i_pcs_ick_txword_ch1(o_pcs_txword_ch1_0),
		.i_pcs_ick_txword_ch2(o_pcs_txword_ch2_0),
		.i_pcs_ick_txword_ch3(o_pcs_txword_ch3_0),
		.i_pcs_rxword_ch0(oflux_srds_rx_clk_lane0_1),
		.i_pcs_rxword_ch1(oflux_srds_rx_clk_lane1_1),
		.i_pcs_rxword_ch2(oflux_srds_rx_clk_lane2_1),
		.i_pcs_rxword_ch3(oflux_srds_rx_clk_lane3_1),
		.i_q2q_xcvrrc_ux_ux__txstatus_rc_ux({ x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[3], x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[2], x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[1], x_std_sm_ux_toolbox_0__i_q2q_xcvrrc_ux_ux__txstatus_rc_ux_0[0] }),
		.i_rst_ux_rx_pma_rst_n_ch0(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch0_1),
		.i_rst_ux_rx_pma_rst_n_ch1(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch1_1),
		.i_rst_ux_rx_pma_rst_n_ch2(flux_ingress_u2__o_rst_ux_rx_pma_rst_n_0),
		.i_rst_ux_rx_pma_rst_n_ch3(x_std_sm_ux_toolbox_0__i_rst_ux_rx_pma_rst_n_ch3_1),
		.i_rst_ux_tx_pma_rst_n_ch0(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch0_1),
		.i_rst_ux_tx_pma_rst_n_ch1(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch1_1),
		.i_rst_ux_tx_pma_rst_n_ch2(flux_ingress_u2__o_rst_ux_tx_pma_rst_n_0),
		.i_rst_ux_tx_pma_rst_n_ch3(x_std_sm_ux_toolbox_0__i_rst_ux_tx_pma_rst_n_ch3_1),
		.i_sclk_return_sel_rx_ch0(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch0_1),
		.i_sclk_return_sel_rx_ch1(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch1_1),
		.i_sclk_return_sel_rx_ch2(flux_ingress_u2__o_sclk_return_sel_rx_0),
		.i_sclk_return_sel_rx_ch3(x_std_sm_ux_toolbox_0__i_sclk_return_sel_rx_ch3_1),
		.i_sclk_return_sel_tx_ch0(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch0_1),
		.i_sclk_return_sel_tx_ch1(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch1_1),
		.i_sclk_return_sel_tx_ch2(flux_ingress_u2__o_sclk_return_sel_tx_0),
		.i_sclk_return_sel_tx_ch3(x_std_sm_ux_toolbox_0__i_sclk_return_sel_tx_ch3_1),
		.i_tx_dl_ch0_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch0_bit_1),
		.i_tx_dl_ch1_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch1_bit_1),
		.i_tx_dl_ch2_bit(ux_toolbox_u0__i_tx_dl_ch2_bit_0),
		.i_tx_dl_ch3_bit(x_std_sm_ux_toolbox_0__i_tx_dl_ch3_bit_1),
		.o_ch0_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_0[0] }),
		.o_ch0_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch0_lavmm_rdata_valid_1),
		.o_ch0_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch0_lavmm_waitreq_1),
		.o_ch1_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_0[0] }),
		.o_ch1_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch1_lavmm_rdata_valid_1),
		.o_ch1_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch1_lavmm_waitreq_1),
		.o_ch2_lavmm_rdata({ flux_ingress_u2__i_lavmm_rdata_0[31], flux_ingress_u2__i_lavmm_rdata_0[30], flux_ingress_u2__i_lavmm_rdata_0[29], flux_ingress_u2__i_lavmm_rdata_0[28], flux_ingress_u2__i_lavmm_rdata_0[27], flux_ingress_u2__i_lavmm_rdata_0[26], flux_ingress_u2__i_lavmm_rdata_0[25], flux_ingress_u2__i_lavmm_rdata_0[24], flux_ingress_u2__i_lavmm_rdata_0[23], flux_ingress_u2__i_lavmm_rdata_0[22], flux_ingress_u2__i_lavmm_rdata_0[21], flux_ingress_u2__i_lavmm_rdata_0[20], flux_ingress_u2__i_lavmm_rdata_0[19], flux_ingress_u2__i_lavmm_rdata_0[18], flux_ingress_u2__i_lavmm_rdata_0[17], flux_ingress_u2__i_lavmm_rdata_0[16], flux_ingress_u2__i_lavmm_rdata_0[15], flux_ingress_u2__i_lavmm_rdata_0[14], flux_ingress_u2__i_lavmm_rdata_0[13], flux_ingress_u2__i_lavmm_rdata_0[12], flux_ingress_u2__i_lavmm_rdata_0[11], flux_ingress_u2__i_lavmm_rdata_0[10], flux_ingress_u2__i_lavmm_rdata_0[9], flux_ingress_u2__i_lavmm_rdata_0[8], flux_ingress_u2__i_lavmm_rdata_0[7], flux_ingress_u2__i_lavmm_rdata_0[6], flux_ingress_u2__i_lavmm_rdata_0[5], flux_ingress_u2__i_lavmm_rdata_0[4], flux_ingress_u2__i_lavmm_rdata_0[3], flux_ingress_u2__i_lavmm_rdata_0[2], flux_ingress_u2__i_lavmm_rdata_0[1], flux_ingress_u2__i_lavmm_rdata_0[0] }),
		.o_ch2_lavmm_rdata_valid(flux_ingress_u2__i_lavmm_rdata_valid_0),
		.o_ch2_lavmm_waitreq(flux_ingress_u2__i_lavmm_waitreq_0),
		.o_ch3_lavmm_rdata({ x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[31], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[30], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[29], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[28], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[27], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[26], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[25], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[24], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[23], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[22], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[21], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[20], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[19], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[18], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[17], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[16], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[15], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[14], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[13], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[12], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[11], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[10], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[9], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[8], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[7], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[6], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[5], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[4], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[3], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[2], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[1], x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_0[0] }),
		.o_ch3_lavmm_rdata_valid(x_std_sm_ux_toolbox_0__o_ch3_lavmm_rdata_valid_1),
		.o_ch3_lavmm_waitreq(x_std_sm_ux_toolbox_0__o_ch3_lavmm_waitreq_1),
		.o_dat_pcs_measlatbit_ch0(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch0_1),
		.o_dat_pcs_measlatbit_ch1(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch1_1),
		.o_dat_pcs_measlatbit_ch2(ux_toolbox_u0__o_dat_pcs_measlatbit_ch2_0),
		.o_dat_pcs_measlatbit_ch3(x_std_sm_ux_toolbox_0__o_dat_pcs_measlatbit_ch3_1),
		.o_flux_apb_clk(o_flux_apb_clk_0),
		.o_flux_apb_paddr({ o_flux_apb_paddr_0[31], o_flux_apb_paddr_0[30], o_flux_apb_paddr_0[29], o_flux_apb_paddr_0[28], o_flux_apb_paddr_0[27], o_flux_apb_paddr_0[26], o_flux_apb_paddr_0[25], o_flux_apb_paddr_0[24], o_flux_apb_paddr_0[23], o_flux_apb_paddr_0[22], o_flux_apb_paddr_0[21], o_flux_apb_paddr_0[20], o_flux_apb_paddr_0[19], o_flux_apb_paddr_0[18], o_flux_apb_paddr_0[17], o_flux_apb_paddr_0[16], o_flux_apb_paddr_0[15], o_flux_apb_paddr_0[14], o_flux_apb_paddr_0[13], o_flux_apb_paddr_0[12], o_flux_apb_paddr_0[11], o_flux_apb_paddr_0[10], o_flux_apb_paddr_0[9], o_flux_apb_paddr_0[8], o_flux_apb_paddr_0[7], o_flux_apb_paddr_0[6], o_flux_apb_paddr_0[5], o_flux_apb_paddr_0[4], o_flux_apb_paddr_0[3], o_flux_apb_paddr_0[2], o_flux_apb_paddr_0[1], o_flux_apb_paddr_0[0] }),
		.o_flux_apb_penable(o_flux_apb_penable_0),
		.o_flux_apb_pprot({ o_flux_apb_pprot_0[2], o_flux_apb_pprot_0[1], o_flux_apb_pprot_0[0] }),
		.o_flux_apb_psel(o_flux_apb_psel_0),
		.o_flux_apb_pstrb({ o_flux_apb_pstrb_0[3], o_flux_apb_pstrb_0[2], o_flux_apb_pstrb_0[1], o_flux_apb_pstrb_0[0] }),
		.o_flux_apb_pwdata({ o_flux_apb_pwdata_0[31], o_flux_apb_pwdata_0[30], o_flux_apb_pwdata_0[29], o_flux_apb_pwdata_0[28], o_flux_apb_pwdata_0[27], o_flux_apb_pwdata_0[26], o_flux_apb_pwdata_0[25], o_flux_apb_pwdata_0[24], o_flux_apb_pwdata_0[23], o_flux_apb_pwdata_0[22], o_flux_apb_pwdata_0[21], o_flux_apb_pwdata_0[20], o_flux_apb_pwdata_0[19], o_flux_apb_pwdata_0[18], o_flux_apb_pwdata_0[17], o_flux_apb_pwdata_0[16], o_flux_apb_pwdata_0[15], o_flux_apb_pwdata_0[14], o_flux_apb_pwdata_0[13], o_flux_apb_pwdata_0[12], o_flux_apb_pwdata_0[11], o_flux_apb_pwdata_0[10], o_flux_apb_pwdata_0[9], o_flux_apb_pwdata_0[8], o_flux_apb_pwdata_0[7], o_flux_apb_pwdata_0[6], o_flux_apb_pwdata_0[5], o_flux_apb_pwdata_0[4], o_flux_apb_pwdata_0[3], o_flux_apb_pwdata_0[2], o_flux_apb_pwdata_0[1], o_flux_apb_pwdata_0[0] }),
		.o_flux_apb_pwrite(o_flux_apb_pwrite_0),
		.o_flux_apb_rst_n(o_flux_apb_rst_n_0),
		.o_ft_rx_async_pulse_ch0(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch0_1),
		.o_ft_rx_async_pulse_ch1(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch1_1),
		.o_ft_rx_async_pulse_ch2(ux_toolbox_u0__o_ft_rx_async_pulse_ch2_0),
		.o_ft_rx_async_pulse_ch3(x_std_sm_ux_toolbox_0__o_ft_rx_async_pulse_ch3_1),
		.o_ft_tx_async_pulse_ch0(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch0_1),
		.o_ft_tx_async_pulse_ch1(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch1_1),
		.o_ft_tx_async_pulse_ch2(ux_toolbox_u0__o_ft_tx_async_pulse_ch2_0),
		.o_ft_tx_async_pulse_ch3(x_std_sm_ux_toolbox_0__o_ft_tx_async_pulse_ch3_1),
		.o_ictl_pcs_txenable_ch0_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch0_a_1),
		.o_ictl_pcs_txenable_ch1_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch1_a_1),
		.o_ictl_pcs_txenable_ch2_a(ux_toolbox_u0__o_ictl_pcs_txenable_ch2_a_0),
		.o_ictl_pcs_txenable_ch3_a(x_std_sm_ux_toolbox_0__o_ictl_pcs_txenable_ch3_a_1),
		.o_q2q_xcvrrc_ux_ux__txstatus_ux_rc({ x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[3], x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[2], x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[1], x_std_sm_ux_toolbox_0__o_q2q_xcvrrc_ux_ux__txstatus_ux_rc_0[0] }),
		.o_rx_dl_ch0_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch0_bit_1),
		.o_rx_dl_ch1_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch1_bit_1),
		.o_rx_dl_ch2_bit(flux_ingress_u2__i_rx_dl_ch_bit_0),
		.o_rx_dl_ch3_bit(x_std_sm_ux_toolbox_0__o_rx_dl_ch3_bit_1),
		.o_sync_cfg_data_ch0({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch0_0[0] }),
		.o_sync_cfg_data_ch1({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch1_0[0] }),
		.o_sync_cfg_data_ch2({ ux_toolbox_u0__o_sync_cfg_data_ch2_0[124], ux_toolbox_u0__o_sync_cfg_data_ch2_0[123], ux_toolbox_u0__o_sync_cfg_data_ch2_0[122], ux_toolbox_u0__o_sync_cfg_data_ch2_0[121], ux_toolbox_u0__o_sync_cfg_data_ch2_0[120], ux_toolbox_u0__o_sync_cfg_data_ch2_0[119], ux_toolbox_u0__o_sync_cfg_data_ch2_0[118], ux_toolbox_u0__o_sync_cfg_data_ch2_0[117], ux_toolbox_u0__o_sync_cfg_data_ch2_0[116], ux_toolbox_u0__o_sync_cfg_data_ch2_0[115], ux_toolbox_u0__o_sync_cfg_data_ch2_0[114], ux_toolbox_u0__o_sync_cfg_data_ch2_0[113], ux_toolbox_u0__o_sync_cfg_data_ch2_0[112], ux_toolbox_u0__o_sync_cfg_data_ch2_0[111], ux_toolbox_u0__o_sync_cfg_data_ch2_0[110], ux_toolbox_u0__o_sync_cfg_data_ch2_0[109], ux_toolbox_u0__o_sync_cfg_data_ch2_0[108], ux_toolbox_u0__o_sync_cfg_data_ch2_0[107], ux_toolbox_u0__o_sync_cfg_data_ch2_0[106], ux_toolbox_u0__o_sync_cfg_data_ch2_0[105], ux_toolbox_u0__o_sync_cfg_data_ch2_0[104], ux_toolbox_u0__o_sync_cfg_data_ch2_0[103], ux_toolbox_u0__o_sync_cfg_data_ch2_0[102], ux_toolbox_u0__o_sync_cfg_data_ch2_0[101], ux_toolbox_u0__o_sync_cfg_data_ch2_0[100], ux_toolbox_u0__o_sync_cfg_data_ch2_0[99], ux_toolbox_u0__o_sync_cfg_data_ch2_0[98], ux_toolbox_u0__o_sync_cfg_data_ch2_0[97], ux_toolbox_u0__o_sync_cfg_data_ch2_0[96], ux_toolbox_u0__o_sync_cfg_data_ch2_0[95], ux_toolbox_u0__o_sync_cfg_data_ch2_0[94], ux_toolbox_u0__o_sync_cfg_data_ch2_0[93], ux_toolbox_u0__o_sync_cfg_data_ch2_0[92], ux_toolbox_u0__o_sync_cfg_data_ch2_0[91], ux_toolbox_u0__o_sync_cfg_data_ch2_0[90], ux_toolbox_u0__o_sync_cfg_data_ch2_0[89], ux_toolbox_u0__o_sync_cfg_data_ch2_0[88], ux_toolbox_u0__o_sync_cfg_data_ch2_0[87], ux_toolbox_u0__o_sync_cfg_data_ch2_0[86], ux_toolbox_u0__o_sync_cfg_data_ch2_0[85], ux_toolbox_u0__o_sync_cfg_data_ch2_0[84], ux_toolbox_u0__o_sync_cfg_data_ch2_0[83], ux_toolbox_u0__o_sync_cfg_data_ch2_0[82], ux_toolbox_u0__o_sync_cfg_data_ch2_0[81], ux_toolbox_u0__o_sync_cfg_data_ch2_0[80], ux_toolbox_u0__o_sync_cfg_data_ch2_0[79], ux_toolbox_u0__o_sync_cfg_data_ch2_0[78], ux_toolbox_u0__o_sync_cfg_data_ch2_0[77], ux_toolbox_u0__o_sync_cfg_data_ch2_0[76], ux_toolbox_u0__o_sync_cfg_data_ch2_0[75], ux_toolbox_u0__o_sync_cfg_data_ch2_0[74], ux_toolbox_u0__o_sync_cfg_data_ch2_0[73], ux_toolbox_u0__o_sync_cfg_data_ch2_0[72], ux_toolbox_u0__o_sync_cfg_data_ch2_0[71], ux_toolbox_u0__o_sync_cfg_data_ch2_0[70], ux_toolbox_u0__o_sync_cfg_data_ch2_0[69], ux_toolbox_u0__o_sync_cfg_data_ch2_0[68], ux_toolbox_u0__o_sync_cfg_data_ch2_0[67], ux_toolbox_u0__o_sync_cfg_data_ch2_0[66], ux_toolbox_u0__o_sync_cfg_data_ch2_0[65], ux_toolbox_u0__o_sync_cfg_data_ch2_0[64], ux_toolbox_u0__o_sync_cfg_data_ch2_0[63], ux_toolbox_u0__o_sync_cfg_data_ch2_0[62], ux_toolbox_u0__o_sync_cfg_data_ch2_0[61], ux_toolbox_u0__o_sync_cfg_data_ch2_0[60], ux_toolbox_u0__o_sync_cfg_data_ch2_0[59], ux_toolbox_u0__o_sync_cfg_data_ch2_0[58], ux_toolbox_u0__o_sync_cfg_data_ch2_0[57], ux_toolbox_u0__o_sync_cfg_data_ch2_0[56], ux_toolbox_u0__o_sync_cfg_data_ch2_0[55], ux_toolbox_u0__o_sync_cfg_data_ch2_0[54], ux_toolbox_u0__o_sync_cfg_data_ch2_0[53], ux_toolbox_u0__o_sync_cfg_data_ch2_0[52], ux_toolbox_u0__o_sync_cfg_data_ch2_0[51], ux_toolbox_u0__o_sync_cfg_data_ch2_0[50], ux_toolbox_u0__o_sync_cfg_data_ch2_0[49], ux_toolbox_u0__o_sync_cfg_data_ch2_0[48], ux_toolbox_u0__o_sync_cfg_data_ch2_0[47], ux_toolbox_u0__o_sync_cfg_data_ch2_0[46], ux_toolbox_u0__o_sync_cfg_data_ch2_0[45], ux_toolbox_u0__o_sync_cfg_data_ch2_0[44], ux_toolbox_u0__o_sync_cfg_data_ch2_0[43], ux_toolbox_u0__o_sync_cfg_data_ch2_0[42], ux_toolbox_u0__o_sync_cfg_data_ch2_0[41], ux_toolbox_u0__o_sync_cfg_data_ch2_0[40], ux_toolbox_u0__o_sync_cfg_data_ch2_0[39], ux_toolbox_u0__o_sync_cfg_data_ch2_0[38], ux_toolbox_u0__o_sync_cfg_data_ch2_0[37], ux_toolbox_u0__o_sync_cfg_data_ch2_0[36], ux_toolbox_u0__o_sync_cfg_data_ch2_0[35], ux_toolbox_u0__o_sync_cfg_data_ch2_0[34], ux_toolbox_u0__o_sync_cfg_data_ch2_0[33], ux_toolbox_u0__o_sync_cfg_data_ch2_0[32], ux_toolbox_u0__o_sync_cfg_data_ch2_0[31], ux_toolbox_u0__o_sync_cfg_data_ch2_0[30], ux_toolbox_u0__o_sync_cfg_data_ch2_0[29], ux_toolbox_u0__o_sync_cfg_data_ch2_0[28], ux_toolbox_u0__o_sync_cfg_data_ch2_0[27], ux_toolbox_u0__o_sync_cfg_data_ch2_0[26], ux_toolbox_u0__o_sync_cfg_data_ch2_0[25], ux_toolbox_u0__o_sync_cfg_data_ch2_0[24], ux_toolbox_u0__o_sync_cfg_data_ch2_0[23], ux_toolbox_u0__o_sync_cfg_data_ch2_0[22], ux_toolbox_u0__o_sync_cfg_data_ch2_0[21], ux_toolbox_u0__o_sync_cfg_data_ch2_0[20], ux_toolbox_u0__o_sync_cfg_data_ch2_0[19], ux_toolbox_u0__o_sync_cfg_data_ch2_0[18], ux_toolbox_u0__o_sync_cfg_data_ch2_0[17], ux_toolbox_u0__o_sync_cfg_data_ch2_0[16], ux_toolbox_u0__o_sync_cfg_data_ch2_0[15], ux_toolbox_u0__o_sync_cfg_data_ch2_0[14], ux_toolbox_u0__o_sync_cfg_data_ch2_0[13], ux_toolbox_u0__o_sync_cfg_data_ch2_0[12], ux_toolbox_u0__o_sync_cfg_data_ch2_0[11], ux_toolbox_u0__o_sync_cfg_data_ch2_0[10], ux_toolbox_u0__o_sync_cfg_data_ch2_0[9], ux_toolbox_u0__o_sync_cfg_data_ch2_0[8], ux_toolbox_u0__o_sync_cfg_data_ch2_0[7], ux_toolbox_u0__o_sync_cfg_data_ch2_0[6], ux_toolbox_u0__o_sync_cfg_data_ch2_0[5], ux_toolbox_u0__o_sync_cfg_data_ch2_0[4], ux_toolbox_u0__o_sync_cfg_data_ch2_0[3], ux_toolbox_u0__o_sync_cfg_data_ch2_0[2], ux_toolbox_u0__o_sync_cfg_data_ch2_0[1], ux_toolbox_u0__o_sync_cfg_data_ch2_0[0] }),
		.o_sync_cfg_data_ch3({ x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[124], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[123], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[122], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[121], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[120], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[119], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[118], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[117], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[116], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[115], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[114], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[113], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[112], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[111], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[110], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[109], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[108], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[107], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[106], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[105], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[104], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[103], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[102], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[101], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[100], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[99], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[98], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[97], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[96], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[95], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[94], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[93], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[92], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[91], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[90], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[89], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[88], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[87], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[86], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[85], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[84], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[83], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[82], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[81], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[80], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[79], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[78], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[77], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[76], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[75], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[74], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[73], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[72], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[71], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[70], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[69], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[68], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[67], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[66], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[65], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[64], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[63], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[62], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[61], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[60], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[59], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[58], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[57], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[56], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[55], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[54], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[53], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[52], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[51], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[50], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[49], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[48], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[47], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[46], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[45], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[44], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[43], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[42], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[41], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[40], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[39], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[38], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[37], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[36], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[35], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[34], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[33], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[32], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[31], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[30], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[29], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[28], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[27], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[26], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[25], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[24], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[23], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[22], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[21], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[20], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[19], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[18], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[17], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[16], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[15], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[14], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[13], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[12], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[11], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[10], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[9], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[8], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[7], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[6], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[5], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[4], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[3], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[2], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[1], x_std_sm_ux_toolbox_0__o_sync_cfg_data_ch3_0[0] }),
		.o_sync_common_control_ch0({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch0_0[0] }),
		.o_sync_common_control_ch1({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch1_0[0] }),
		.o_sync_common_control_ch2({ ux_toolbox_u0__o_sync_common_control_ch2_0[4], ux_toolbox_u0__o_sync_common_control_ch2_0[3], ux_toolbox_u0__o_sync_common_control_ch2_0[2], ux_toolbox_u0__o_sync_common_control_ch2_0[1], ux_toolbox_u0__o_sync_common_control_ch2_0[0] }),
		.o_sync_common_control_ch3({ x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[4], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[3], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[2], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[1], x_std_sm_ux_toolbox_0__o_sync_common_control_ch3_0[0] }),
		.o_sync_interface_control_ch0({ x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[249], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[248], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[247], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[246], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[245], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[244], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[243], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[242], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[241], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[240], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[239], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[238], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[237], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[236], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[235], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[234], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[233], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[232], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[231], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[230], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[229], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[228], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[227], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[226], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[225], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[224], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[223], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[222], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[221], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[220], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[219], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[218], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[217], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[216], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[215], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[214], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[213], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[212], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[211], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[210], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[209], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[208], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[207], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[206], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[205], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[204], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[203], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[202], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[201], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[200], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[199], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[198], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[197], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[196], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[195], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[194], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[193], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[192], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[191], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[190], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[189], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[188], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[187], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[186], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[185], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[184], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[183], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[182], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[181], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[180], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[179], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[178], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[177], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[176], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[175], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[174], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[173], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[172], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[171], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[170], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[169], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[168], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[167], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[166], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[165], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[164], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[163], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[162], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[161], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[160], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[159], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[158], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[157], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[156], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[155], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[154], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[153], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[152], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[151], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[150], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[149], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[148], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[147], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[146], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[145], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[144], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[143], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[142], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[141], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[140], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[139], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[138], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[137], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[136], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[135], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[134], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[133], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[132], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[131], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[130], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[129], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[128], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[127], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[126], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[125], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[124], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[123], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch0_0[122], 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x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[121], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[120], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[119], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[118], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[117], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[116], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[115], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[114], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[113], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[112], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[111], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[110], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[109], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[108], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[107], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[106], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[105], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[104], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[103], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[102], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[101], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[100], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[99], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[98], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[97], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[96], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[95], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[94], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[93], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[92], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[91], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[90], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[89], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[88], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[87], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[86], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[85], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[84], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[83], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[82], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[81], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[80], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[79], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[78], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[77], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[76], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[75], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[74], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[73], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[72], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[71], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[70], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[69], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[68], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[67], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[66], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[65], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[64], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[63], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[62], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[61], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[60], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[59], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[58], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[57], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[56], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[55], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[54], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[53], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[52], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[51], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[50], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[49], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[48], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[47], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[46], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[45], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[44], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[43], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[42], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[41], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[40], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[39], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[38], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[37], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[36], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[35], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[34], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[33], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[32], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[31], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[30], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[29], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[28], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[27], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[26], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[25], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[24], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[23], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[22], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[21], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[20], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[19], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[18], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[17], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[16], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[15], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[14], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[13], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[12], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[11], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[10], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[9], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[8], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[7], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[6], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[5], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[4], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[3], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[2], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[1], x_std_sm_ux_toolbox_0__o_sync_interface_control_ch3_0[0] }),
		.o_ux0_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_rxuser1_sel_0[0] }),
		.o_ux0_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_rxuser2_sel_0[0] }),
		.o_ux0_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_txuser1_sel_0[0] }),
		.o_ux0_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux0_txuser2_sel_0[0] }),
		.o_ux1_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_rxuser1_sel_0[0] }),
		.o_ux1_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_rxuser2_sel_0[0] }),
		.o_ux1_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_txuser1_sel_0[0] }),
		.o_ux1_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux1_txuser2_sel_0[0] }),
		.o_ux2_rxuser1_sel({ ux_toolbox_u0__o_ux2_rxuser1_sel_0[1], ux_toolbox_u0__o_ux2_rxuser1_sel_0[0] }),
		.o_ux2_rxuser2_sel({ ux_toolbox_u0__o_ux2_rxuser2_sel_0[1], ux_toolbox_u0__o_ux2_rxuser2_sel_0[0] }),
		.o_ux2_txuser1_sel({ ux_toolbox_u0__o_ux2_txuser1_sel_0[1], ux_toolbox_u0__o_ux2_txuser1_sel_0[0] }),
		.o_ux2_txuser2_sel({ ux_toolbox_u0__o_ux2_txuser2_sel_0[1], ux_toolbox_u0__o_ux2_txuser2_sel_0[0] }),
		.o_ux3_rxuser1_sel({ x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_rxuser1_sel_0[0] }),
		.o_ux3_rxuser2_sel({ x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_rxuser2_sel_0[0] }),
		.o_ux3_txuser1_sel({ x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_txuser1_sel_0[0] }),
		.o_ux3_txuser2_sel({ x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[1], x_std_sm_ux_toolbox_0__o_ux3_txuser2_sel_0[0] })
	);

	tennm_sm_xcvrif_rx_ch_clk_mux #(
		.sel(x_mux_sm_xcvrif_rx_ch_clk_mux_0__sel)
	) x_mux_sm_xcvrif_rx_ch_clk_mux_0 (
		.i_ground_clk(pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1]),
		.i_rxword_clk(o_xcvr_rxword_ch_clk_2),
		.i_sys_clk(xcvrif_tx_esys_clk_mux_u0__o_esys_ch_clk_2),
		.o_eth_rx_ch_clk(o_eth_rx_ch2_clk_4)
	);

	tennm_sm_xcvrif_rx_word_clk_mux_module x_dynMux_sm_xcvrif_rx_word_clk_mux_0 (
		.i_ground_clk(pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1]),
		.i_rxword_clk(o_ux_eth_rxword_clk_2),
		.i_txword_clk(o_xcvr_txword_ch_clk_2),
		.k_sel({ xcvrif_1ch_u2__o_rx_xcvr_wordclk_sel_0[1], xcvrif_1ch_u2__o_rx_xcvr_wordclk_sel_0[0] }),
		.o_xcvr_rxword_ch_clk(o_xcvr_rxword_ch_clk_2)
	);

	tennm_sm_xcvrif_tx_ch_clk_mux #(
		.sel(x_mux_sm_xcvrif_tx_ch_clk_mux_0__sel)
	) x_mux_sm_xcvrif_tx_ch_clk_mux_0 (
		.i_ground_clk(pld_pwr_level_shifter_u0__o_dft_ptcb_eth_top_edt_channel_in_0[1]),
		.i_sys_clk(xcvrif_tx_esys_clk_mux_u0__o_esys_ch_clk_2),
		.i_txword_clk(o_xcvr_txword_ch_clk_2),
		.o_eth_tx_ch_clk(o_eth_tx_ch2_clk_4)
	);

	tennm_sm_xcvrif_rx_fifo_rd_en_mux_module x_dynMux_sm_xcvrif_rx_fifo_rd_en_mux_0 (
		.i_x1(o_ch2_xcvrif_rx_fifo_rd_en_0),
		.i_x2(),
		.i_x4(x_dynMux_sm_xcvrif_rx_fifo_rd_en_mux_0__i_x4_1),
		.i_x6_bot(n1_1),
		.i_x6_top(n1_1),
		.i_x8_bot(n1_1),
		.i_x8_top(n1_1),
		.k_sel({ rx_fifo_en_sel_ch2_0[2], rx_fifo_en_sel_ch2_0[1], rx_fifo_en_sel_ch2_0[0] }),
		.o_ch_xcvrif_rx_fifo_rd_en(o_ch_xcvrif_rx_fifo_rd_en_2)
	);

	tennm_sm_xcvrif_tx_fifo_rd_en_mux_module x_dynMux_sm_xcvrif_tx_fifo_rd_en_mux_0 (
		.i_x1(o_ch2_xcvrif_tx_fifo_rd_en_0),
		.i_x2(),
		.i_x4(),
		.i_x6_bot(s4706_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit),
		.i_x6_top(),
		.i_x8_bot(s4706_51_1__sm_hssi_user_bit_vcc_hssi__hssi_user_bit),
		.i_x8_top(),
		.k_sel({ xcvrif_1ch_u2__o_tx_rst_source_sel_0[2], xcvrif_1ch_u2__o_tx_rst_source_sel_0[1], xcvrif_1ch_u2__o_tx_rst_source_sel_0[0] }),
		.o_ch_xcvrif_tx_fifo_rd_en(o_ch_xcvrif_tx_fifo_rd_en_2)
	);

	tennm_sm_xcvrif_tx_word_clk_mux_module x_dynMux_sm_xcvrif_tx_word_clk_mux_0 (
		.i_ground_clk(n1_14),
		.i_x1(o_ux_eth_txword_clk_2),
		.i_x2(o_ux_eth_txword_clk_2),
		.i_x4(),
		.i_x6_bot(ux_quad_u0__o_ux0_top_eth_txword_clk_0),
		.i_x6_top(),
		.i_x8_bot(ux_quad_u0__o_ux0_top_eth_txword_clk_0),
		.i_x8_top(),
		.k_sel({ x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0[2], x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0[1], x_dynMux_sm_xcvrif_tx_word_clk_mux_0__k_sel_0[0] }),
		.o_xcvr_txword_ch_clk(o_xcvr_txword_ch_clk_2)
	);

	tennm_ipfluxtop_flux_core_shim_wrap #(
		.ch0_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_l_counter),
		.ch0_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_cdr_refclk_select),
		.ch0_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_flux_mode),
		.ch0_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_loopback_mode),
		.ch0_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_pcie_mode),
		.ch0_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_monitor_en),
		.ch0_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_prbs_pattern),
		.ch0_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_preloaded_hardware_configs),
		.ch0_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_sim_mode),
		.ch0_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_rx_width),
		.ch0_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_bonding_category),
		.ch0_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_l_counter),
		.ch0_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_pll_refclk_select),
		.ch0_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_gen_en),
		.ch0_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_prbs_pattern),
		.ch0_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_preloaded_hardware_configs),
		.ch0_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_sim_mode),
		.ch0_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_user_clk_only_mode),
		.ch0_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch0_tx_width),
		.ch1_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_l_counter),
		.ch1_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_cdr_refclk_select),
		.ch1_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_flux_mode),
		.ch1_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_loopback_mode),
		.ch1_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_pcie_mode),
		.ch1_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_monitor_en),
		.ch1_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_prbs_pattern),
		.ch1_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_preloaded_hardware_configs),
		.ch1_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_sim_mode),
		.ch1_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_rx_width),
		.ch1_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_bonding_category),
		.ch1_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_l_counter),
		.ch1_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_pll_refclk_select),
		.ch1_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_gen_en),
		.ch1_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_prbs_pattern),
		.ch1_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_preloaded_hardware_configs),
		.ch1_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_sim_mode),
		.ch1_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_user_clk_only_mode),
		.ch1_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch1_tx_width),
		.ch2_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_l_counter),
		.ch2_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_cdr_refclk_select),
		.ch2_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_flux_mode),
		.ch2_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_loopback_mode),
		.ch2_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_pcie_mode),
		.ch2_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_monitor_en),
		.ch2_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_prbs_pattern),
		.ch2_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_preloaded_hardware_configs),
		.ch2_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_sim_mode),
		.ch2_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_rx_width),
		.ch2_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_bonding_category),
		.ch2_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_l_counter),
		.ch2_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_pll_refclk_select),
		.ch2_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_gen_en),
		.ch2_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_prbs_pattern),
		.ch2_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_preloaded_hardware_configs),
		.ch2_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_sim_mode),
		.ch2_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_user_clk_only_mode),
		.ch2_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch2_tx_width),
		.ch3_cdr_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_l_counter),
		.ch3_cdr_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_cdr_refclk_select),
		.ch3_flux_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_flux_mode),
		.ch3_loopback_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_loopback_mode),
		.ch3_pcie_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_pcie_mode),
		.ch3_rx_prbs_monitor_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_monitor_en),
		.ch3_rx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_prbs_pattern),
		.ch3_rx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_preloaded_hardware_configs),
		.ch3_rx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_sim_mode),
		.ch3_rx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_rx_width),
		.ch3_tx_bonding_category(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_bonding_category),
		.ch3_tx_pll_l_counter(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_l_counter),
		.ch3_tx_pll_refclk_select(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_pll_refclk_select),
		.ch3_tx_prbs_gen_en(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_gen_en),
		.ch3_tx_prbs_pattern(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_prbs_pattern),
		.ch3_tx_preloaded_hardware_configs(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_preloaded_hardware_configs),
		.ch3_tx_sim_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_sim_mode),
		.ch3_tx_user_clk_only_mode(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_user_clk_only_mode),
		.ch3_tx_width(x_std_ipfluxtop_flux_core_shim_wrap_0__ch3_tx_width)
	) x_std_ipfluxtop_flux_core_shim_wrap_0 (
		.car_cpu_bresetn(car_cpu_bresetn_1),
		.car_cpu_clk(car_cpu_clk_1),
		.iflux_ext_car_apb_rstn(o_flux_apb_rst_n_0),
		.iflux_ext_ck_apb_clk(o_flux_apb_clk_0),
		.iflux_ext_cpu_fast_clk(o_flux_sclk_mux_0),
		.iflux_ext_pcs_paddr({ o_flux_apb_paddr_0[31], o_flux_apb_paddr_0[30], o_flux_apb_paddr_0[29], o_flux_apb_paddr_0[28], o_flux_apb_paddr_0[27], o_flux_apb_paddr_0[26], o_flux_apb_paddr_0[25], o_flux_apb_paddr_0[24], o_flux_apb_paddr_0[23], o_flux_apb_paddr_0[22], o_flux_apb_paddr_0[21], o_flux_apb_paddr_0[20], o_flux_apb_paddr_0[19], o_flux_apb_paddr_0[18], o_flux_apb_paddr_0[17], o_flux_apb_paddr_0[16], o_flux_apb_paddr_0[15], o_flux_apb_paddr_0[14], o_flux_apb_paddr_0[13], o_flux_apb_paddr_0[12], o_flux_apb_paddr_0[11], o_flux_apb_paddr_0[10], o_flux_apb_paddr_0[9], o_flux_apb_paddr_0[8], o_flux_apb_paddr_0[7], o_flux_apb_paddr_0[6], o_flux_apb_paddr_0[5], o_flux_apb_paddr_0[4], o_flux_apb_paddr_0[3], o_flux_apb_paddr_0[2], o_flux_apb_paddr_0[1], o_flux_apb_paddr_0[0] }),
		.iflux_ext_pcs_penable(o_flux_apb_penable_0),
		.iflux_ext_pcs_pprot({ o_flux_apb_pprot_0[2], o_flux_apb_pprot_0[1], o_flux_apb_pprot_0[0] }),
		.iflux_ext_pcs_psel(o_flux_apb_psel_0),
		.iflux_ext_pcs_pstrb({ o_flux_apb_pstrb_0[3], o_flux_apb_pstrb_0[2], o_flux_apb_pstrb_0[1], o_flux_apb_pstrb_0[0] }),
		.iflux_ext_pcs_pwdata({ o_flux_apb_pwdata_0[31], o_flux_apb_pwdata_0[30], o_flux_apb_pwdata_0[29], o_flux_apb_pwdata_0[28], o_flux_apb_pwdata_0[27], o_flux_apb_pwdata_0[26], o_flux_apb_pwdata_0[25], o_flux_apb_pwdata_0[24], o_flux_apb_pwdata_0[23], o_flux_apb_pwdata_0[22], o_flux_apb_pwdata_0[21], o_flux_apb_pwdata_0[20], o_flux_apb_pwdata_0[19], o_flux_apb_pwdata_0[18], o_flux_apb_pwdata_0[17], o_flux_apb_pwdata_0[16], o_flux_apb_pwdata_0[15], o_flux_apb_pwdata_0[14], o_flux_apb_pwdata_0[13], o_flux_apb_pwdata_0[12], o_flux_apb_pwdata_0[11], o_flux_apb_pwdata_0[10], o_flux_apb_pwdata_0[9], o_flux_apb_pwdata_0[8], o_flux_apb_pwdata_0[7], o_flux_apb_pwdata_0[6], o_flux_apb_pwdata_0[5], o_flux_apb_pwdata_0[4], o_flux_apb_pwdata_0[3], o_flux_apb_pwdata_0[2], o_flux_apb_pwdata_0[1], o_flux_apb_pwdata_0[0] }),
		.iflux_ext_pcs_pwrite(o_flux_apb_pwrite_0),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane0_1),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane1_1),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane2(o_ick_sclk_tx_ch2_0),
		.iflux_ick_pcs_txptr_smpl_clk_l0_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ick_pcs_txptr_smpl_clk_l0_lane3_1),
		.iflux_ingress_direct_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[307], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[306], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[305], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[304], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[303], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[302], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[301], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[300], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[299], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[298], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[297], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[296], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[295], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[294], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[293], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[292], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[291], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[290], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[289], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[288], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[287], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[286], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[285], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[284], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[283], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[282], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[281], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[280], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[279], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[278], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[277], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[276], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[275], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[274], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[273], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[272], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[271], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[270], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[269], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[268], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[267], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[266], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[265], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[264], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[263], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[262], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[261], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[260], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[259], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[258], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[257], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[255], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[254], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[253], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[252], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[251], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[250], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[249], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[248], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[247], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[246], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[245], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[244], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[243], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[242], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[231], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[230], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[229], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[228], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[227], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[226], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[225], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[224], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[223], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[222], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[221], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[220], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[219], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[218], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[217], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[216], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[215], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[214], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[213], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[212], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[211], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[210], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[209], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[208], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[207], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[206], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[205], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[204], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[203], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[202], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[201], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[200], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[199], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[198], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[197], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[196], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[195], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[194], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[193], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[192], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[191], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane0_0[190], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[98], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[97], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[96], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[95], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[94], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[93], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[92], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[91], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[90], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[89], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[88], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[87], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[86], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[73], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[34], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane1_0[0] }),
		.iflux_ingress_direct_lane2({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[307], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[306], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[305], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[304], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[303], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[302], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[301], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[300], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[299], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[298], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[297], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[296], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[295], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[294], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[293], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[292], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[291], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[290], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[289], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[288], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[287], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[286], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[285], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[284], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[283], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[282], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[281], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[280], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[279], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[278], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[277], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[276], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[275], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[274], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[273], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[272], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[271], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[270], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[269], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[268], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[267], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[266], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[265], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[264], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[263], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[262], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[261], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[260], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[259], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[258], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[257], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[255], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane2_0[0] }),
		.iflux_ingress_direct_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[319], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[318], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[317], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[316], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[315], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[314], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[313], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[312], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[311], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[310], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[309], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[308], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[307], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[306], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[305], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[304], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[303], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[302], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[301], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[300], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[299], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[298], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[297], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[296], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[295], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[294], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[293], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[292], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[291], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[290], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[289], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[288], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[287], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[286], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[285], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[284], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[283], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[282], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[281], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[280], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[279], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[278], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[277], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[276], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[275], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[274], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[273], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[272], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[271], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[270], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[269], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[268], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[267], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[266], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[265], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[264], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[263], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[262], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[261], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[260], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[259], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[258], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[257], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[255], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[231], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[230], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[229], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[228], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[227], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[226], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[225], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[224], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[223], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[222], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[221], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[220], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[219], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[218], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[217], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[216], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[215], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[214], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[213], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[212], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[211], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[210], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[209], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[208], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[207], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[206], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[205], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[204], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[203], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[202], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[201], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[200], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[199], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[198], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[197], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[196], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[195], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[194], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[193], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[192], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[191], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[190], 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x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[163], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[162], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[161], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[160], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[159], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[158], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[157], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[156], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[155], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[154], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[153], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[152], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[151], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[150], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[149], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[148], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[147], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[146], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[145], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[144], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[143], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[142], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[141], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[140], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[139], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[138], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[137], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[136], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[135], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[134], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[133], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[132], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[131], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[130], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[129], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[128], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[127], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[126], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[125], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[124], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[123], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[122], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[121], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[120], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[119], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[118], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[117], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[116], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[115], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[114], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[113], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[112], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[111], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[110], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[109], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[108], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[107], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[106], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[105], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[104], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[103], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[102], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[101], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[100], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[99], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[98], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[97], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[96], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[95], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[94], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[93], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[92], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[91], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[90], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[89], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[88], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[87], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[86], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_ingress_direct_lane3_0[0] }),
		.iflux_mem_dram0checkdata({ iflux_mem_DRam0CheckData_0[19], iflux_mem_DRam0CheckData_0[18], iflux_mem_DRam0CheckData_0[17], iflux_mem_DRam0CheckData_0[16], iflux_mem_DRam0CheckData_0[15], iflux_mem_DRam0CheckData_0[14], iflux_mem_DRam0CheckData_0[13], iflux_mem_DRam0CheckData_0[12], iflux_mem_DRam0CheckData_0[11], iflux_mem_DRam0CheckData_0[10], iflux_mem_DRam0CheckData_0[9], iflux_mem_DRam0CheckData_0[8], iflux_mem_DRam0CheckData_0[7], iflux_mem_DRam0CheckData_0[6], iflux_mem_DRam0CheckData_0[5], iflux_mem_DRam0CheckData_0[4], iflux_mem_DRam0CheckData_0[3], iflux_mem_DRam0CheckData_0[2], iflux_mem_DRam0CheckData_0[1], iflux_mem_DRam0CheckData_0[0] }),
		.iflux_mem_dram0data({ iflux_mem_DRam0Data_0[31], iflux_mem_DRam0Data_0[30], iflux_mem_DRam0Data_0[29], iflux_mem_DRam0Data_0[28], iflux_mem_DRam0Data_0[27], iflux_mem_DRam0Data_0[26], iflux_mem_DRam0Data_0[25], iflux_mem_DRam0Data_0[24], iflux_mem_DRam0Data_0[23], iflux_mem_DRam0Data_0[22], iflux_mem_DRam0Data_0[21], iflux_mem_DRam0Data_0[20], iflux_mem_DRam0Data_0[19], iflux_mem_DRam0Data_0[18], iflux_mem_DRam0Data_0[17], iflux_mem_DRam0Data_0[16], iflux_mem_DRam0Data_0[15], iflux_mem_DRam0Data_0[14], iflux_mem_DRam0Data_0[13], iflux_mem_DRam0Data_0[12], iflux_mem_DRam0Data_0[11], iflux_mem_DRam0Data_0[10], iflux_mem_DRam0Data_0[9], iflux_mem_DRam0Data_0[8], iflux_mem_DRam0Data_0[7], iflux_mem_DRam0Data_0[6], iflux_mem_DRam0Data_0[5], iflux_mem_DRam0Data_0[4], iflux_mem_DRam0Data_0[3], iflux_mem_DRam0Data_0[2], iflux_mem_DRam0Data_0[1], iflux_mem_DRam0Data_0[0] }),
		.iflux_mem_iram0checkdata({ iflux_mem_IRam0CheckData_0[6], iflux_mem_IRam0CheckData_0[5], iflux_mem_IRam0CheckData_0[4], iflux_mem_IRam0CheckData_0[3], iflux_mem_IRam0CheckData_0[2], iflux_mem_IRam0CheckData_0[1], iflux_mem_IRam0CheckData_0[0] }),
		.iflux_mem_iram0data({ iflux_mem_IRam0Data_0[31], iflux_mem_IRam0Data_0[30], iflux_mem_IRam0Data_0[29], iflux_mem_IRam0Data_0[28], iflux_mem_IRam0Data_0[27], iflux_mem_IRam0Data_0[26], iflux_mem_IRam0Data_0[25], iflux_mem_IRam0Data_0[24], iflux_mem_IRam0Data_0[23], iflux_mem_IRam0Data_0[22], iflux_mem_IRam0Data_0[21], iflux_mem_IRam0Data_0[20], iflux_mem_IRam0Data_0[19], iflux_mem_IRam0Data_0[18], iflux_mem_IRam0Data_0[17], iflux_mem_IRam0Data_0[16], iflux_mem_IRam0Data_0[15], iflux_mem_IRam0Data_0[14], iflux_mem_IRam0Data_0[13], iflux_mem_IRam0Data_0[12], iflux_mem_IRam0Data_0[11], iflux_mem_IRam0Data_0[10], iflux_mem_IRam0Data_0[9], iflux_mem_IRam0Data_0[8], iflux_mem_IRam0Data_0[7], iflux_mem_IRam0Data_0[6], iflux_mem_IRam0Data_0[5], iflux_mem_IRam0Data_0[4], iflux_mem_IRam0Data_0[3], iflux_mem_IRam0Data_0[2], iflux_mem_IRam0Data_0[1], iflux_mem_IRam0Data_0[0] }),
		.iflux_mem_qfifo_rd_data({ iflux_mem_qfifo_rd_data_0[31], iflux_mem_qfifo_rd_data_0[30], iflux_mem_qfifo_rd_data_0[29], iflux_mem_qfifo_rd_data_0[28], iflux_mem_qfifo_rd_data_0[27], iflux_mem_qfifo_rd_data_0[26], iflux_mem_qfifo_rd_data_0[25], iflux_mem_qfifo_rd_data_0[24], iflux_mem_qfifo_rd_data_0[23], iflux_mem_qfifo_rd_data_0[22], iflux_mem_qfifo_rd_data_0[21], iflux_mem_qfifo_rd_data_0[20], iflux_mem_qfifo_rd_data_0[19], iflux_mem_qfifo_rd_data_0[18], iflux_mem_qfifo_rd_data_0[17], iflux_mem_qfifo_rd_data_0[16], iflux_mem_qfifo_rd_data_0[15], iflux_mem_qfifo_rd_data_0[14], iflux_mem_qfifo_rd_data_0[13], iflux_mem_qfifo_rd_data_0[12], iflux_mem_qfifo_rd_data_0[11], iflux_mem_qfifo_rd_data_0[10], iflux_mem_qfifo_rd_data_0[9], iflux_mem_qfifo_rd_data_0[8], iflux_mem_qfifo_rd_data_0[7], iflux_mem_qfifo_rd_data_0[6], iflux_mem_qfifo_rd_data_0[5], iflux_mem_qfifo_rd_data_0[4], iflux_mem_qfifo_rd_data_0[3], iflux_mem_qfifo_rd_data_0[2], iflux_mem_qfifo_rd_data_0[1], iflux_mem_qfifo_rd_data_0[0] }),
		.iflux_mem_tracememdata({ iflux_mem_TraceMemData_0[31], iflux_mem_TraceMemData_0[30], iflux_mem_TraceMemData_0[29], iflux_mem_TraceMemData_0[28], iflux_mem_TraceMemData_0[27], iflux_mem_TraceMemData_0[26], iflux_mem_TraceMemData_0[25], iflux_mem_TraceMemData_0[24], iflux_mem_TraceMemData_0[23], iflux_mem_TraceMemData_0[22], iflux_mem_TraceMemData_0[21], iflux_mem_TraceMemData_0[20], iflux_mem_TraceMemData_0[19], iflux_mem_TraceMemData_0[18], iflux_mem_TraceMemData_0[17], iflux_mem_TraceMemData_0[16], iflux_mem_TraceMemData_0[15], iflux_mem_TraceMemData_0[14], iflux_mem_TraceMemData_0[13], iflux_mem_TraceMemData_0[12], iflux_mem_TraceMemData_0[11], iflux_mem_TraceMemData_0[10], iflux_mem_TraceMemData_0[9], iflux_mem_TraceMemData_0[8], iflux_mem_TraceMemData_0[7], iflux_mem_TraceMemData_0[6], iflux_mem_TraceMemData_0[5], iflux_mem_TraceMemData_0[4], iflux_mem_TraceMemData_0[3], iflux_mem_TraceMemData_0[2], iflux_mem_TraceMemData_0[1], iflux_mem_TraceMemData_0[0] }),
		.iflux_pcs_txword_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane0_0[0] }),
		.iflux_pcs_txword_lane1({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane1_0[0] }),
		.iflux_pcs_txword_lane2({ o_flux_pcs_txword_lane2_0[79], o_flux_pcs_txword_lane2_0[78], o_flux_pcs_txword_lane2_0[77], o_flux_pcs_txword_lane2_0[76], o_flux_pcs_txword_lane2_0[75], o_flux_pcs_txword_lane2_0[74], o_flux_pcs_txword_lane2_0[73], o_flux_pcs_txword_lane2_0[72], o_flux_pcs_txword_lane2_0[71], o_flux_pcs_txword_lane2_0[70], o_flux_pcs_txword_lane2_0[69], o_flux_pcs_txword_lane2_0[68], o_flux_pcs_txword_lane2_0[67], o_flux_pcs_txword_lane2_0[66], o_flux_pcs_txword_lane2_0[65], o_flux_pcs_txword_lane2_0[64], o_flux_pcs_txword_lane2_0[63], o_flux_pcs_txword_lane2_0[62], o_flux_pcs_txword_lane2_0[61], o_flux_pcs_txword_lane2_0[60], o_flux_pcs_txword_lane2_0[59], o_flux_pcs_txword_lane2_0[58], o_flux_pcs_txword_lane2_0[57], o_flux_pcs_txword_lane2_0[56], o_flux_pcs_txword_lane2_0[55], o_flux_pcs_txword_lane2_0[54], o_flux_pcs_txword_lane2_0[53], o_flux_pcs_txword_lane2_0[52], o_flux_pcs_txword_lane2_0[51], o_flux_pcs_txword_lane2_0[50], o_flux_pcs_txword_lane2_0[49], o_flux_pcs_txword_lane2_0[48], o_flux_pcs_txword_lane2_0[47], o_flux_pcs_txword_lane2_0[46], o_flux_pcs_txword_lane2_0[45], o_flux_pcs_txword_lane2_0[44], o_flux_pcs_txword_lane2_0[43], o_flux_pcs_txword_lane2_0[42], o_flux_pcs_txword_lane2_0[41], o_flux_pcs_txword_lane2_0[40], o_flux_pcs_txword_lane2_0[39], o_flux_pcs_txword_lane2_0[38], o_flux_pcs_txword_lane2_0[37], o_flux_pcs_txword_lane2_0[36], o_flux_pcs_txword_lane2_0[35], o_flux_pcs_txword_lane2_0[34], o_flux_pcs_txword_lane2_0[33], o_flux_pcs_txword_lane2_0[32], o_flux_pcs_txword_lane2_0[31], o_flux_pcs_txword_lane2_0[30], o_flux_pcs_txword_lane2_0[29], o_flux_pcs_txword_lane2_0[28], o_flux_pcs_txword_lane2_0[27], o_flux_pcs_txword_lane2_0[26], o_flux_pcs_txword_lane2_0[25], o_flux_pcs_txword_lane2_0[24], o_flux_pcs_txword_lane2_0[23], o_flux_pcs_txword_lane2_0[22], o_flux_pcs_txword_lane2_0[21], o_flux_pcs_txword_lane2_0[20], o_flux_pcs_txword_lane2_0[19], o_flux_pcs_txword_lane2_0[18], o_flux_pcs_txword_lane2_0[17], o_flux_pcs_txword_lane2_0[16], o_flux_pcs_txword_lane2_0[15], o_flux_pcs_txword_lane2_0[14], o_flux_pcs_txword_lane2_0[13], o_flux_pcs_txword_lane2_0[12], o_flux_pcs_txword_lane2_0[11], o_flux_pcs_txword_lane2_0[10], o_flux_pcs_txword_lane2_0[9], o_flux_pcs_txword_lane2_0[8], o_flux_pcs_txword_lane2_0[7], o_flux_pcs_txword_lane2_0[6], o_flux_pcs_txword_lane2_0[5], o_flux_pcs_txword_lane2_0[4], o_flux_pcs_txword_lane2_0[3], o_flux_pcs_txword_lane2_0[2], o_flux_pcs_txword_lane2_0[1], o_flux_pcs_txword_lane2_0[0] }),
		.iflux_pcs_txword_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__iflux_pcs_txword_lane3_0[0] }),
		.iflux_srds_tx_clk_lane0(o_pcs_txword_ch0_0),
		.iflux_srds_tx_clk_lane1(o_pcs_txword_ch1_0),
		.iflux_srds_tx_clk_lane2(o_pcs_txword_ch2_0),
		.iflux_srds_tx_clk_lane3(o_pcs_txword_ch3_0),
		.oflux_cpi_int(oflux_cpi_int_1),
		.oflux_egress_direct_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[255], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[254], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[253], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[252], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[251], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[250], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[249], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[248], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[247], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[246], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[245], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[244], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[243], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[242], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[231], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[230], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[229], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[228], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[227], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[226], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[225], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[224], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[223], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[222], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[221], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[220], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[219], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[218], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[217], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[216], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[215], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[214], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[213], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[212], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[211], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[210], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[209], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[208], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[207], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[206], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[205], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[204], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[203], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[202], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[201], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[200], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[199], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[198], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[197], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[196], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[195], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[194], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[193], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane0_0[192], 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x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane1_0[0] }),
		.oflux_egress_direct_lane2({ oflux_egress_direct_lane2_1[256], oflux_egress_direct_lane2_1[255], oflux_egress_direct_lane2_1[254], oflux_egress_direct_lane2_1[253], oflux_egress_direct_lane2_1[252], oflux_egress_direct_lane2_1[251], oflux_egress_direct_lane2_1[250], oflux_egress_direct_lane2_1[249], oflux_egress_direct_lane2_1[248], oflux_egress_direct_lane2_1[247], oflux_egress_direct_lane2_1[246], oflux_egress_direct_lane2_1[245], oflux_egress_direct_lane2_1[244], oflux_egress_direct_lane2_1[243], oflux_egress_direct_lane2_1[242], oflux_egress_direct_lane2_1[241], oflux_egress_direct_lane2_1[240], oflux_egress_direct_lane2_1[239], oflux_egress_direct_lane2_1[238], oflux_egress_direct_lane2_1[237], oflux_egress_direct_lane2_1[236], oflux_egress_direct_lane2_1[235], oflux_egress_direct_lane2_1[234], oflux_egress_direct_lane2_1[233], oflux_egress_direct_lane2_1[232], oflux_egress_direct_lane2_1[231], oflux_egress_direct_lane2_1[230], oflux_egress_direct_lane2_1[229], oflux_egress_direct_lane2_1[228], oflux_egress_direct_lane2_1[227], oflux_egress_direct_lane2_1[226], oflux_egress_direct_lane2_1[225], oflux_egress_direct_lane2_1[224], oflux_egress_direct_lane2_1[223], oflux_egress_direct_lane2_1[222], oflux_egress_direct_lane2_1[221], oflux_egress_direct_lane2_1[220], oflux_egress_direct_lane2_1[219], oflux_egress_direct_lane2_1[218], oflux_egress_direct_lane2_1[217], oflux_egress_direct_lane2_1[216], oflux_egress_direct_lane2_1[215], oflux_egress_direct_lane2_1[214], oflux_egress_direct_lane2_1[213], oflux_egress_direct_lane2_1[212], oflux_egress_direct_lane2_1[211], oflux_egress_direct_lane2_1[210], oflux_egress_direct_lane2_1[209], oflux_egress_direct_lane2_1[208], oflux_egress_direct_lane2_1[207], oflux_egress_direct_lane2_1[206], oflux_egress_direct_lane2_1[205], oflux_egress_direct_lane2_1[204], oflux_egress_direct_lane2_1[203], oflux_egress_direct_lane2_1[202], oflux_egress_direct_lane2_1[201], oflux_egress_direct_lane2_1[200], oflux_egress_direct_lane2_1[199], oflux_egress_direct_lane2_1[198], oflux_egress_direct_lane2_1[197], oflux_egress_direct_lane2_1[196], oflux_egress_direct_lane2_1[195], oflux_egress_direct_lane2_1[194], oflux_egress_direct_lane2_1[193], oflux_egress_direct_lane2_1[192], oflux_egress_direct_lane2_1[191], oflux_egress_direct_lane2_1[190], oflux_egress_direct_lane2_1[189], oflux_egress_direct_lane2_1[188], oflux_egress_direct_lane2_1[187], oflux_egress_direct_lane2_1[186], oflux_egress_direct_lane2_1[185], oflux_egress_direct_lane2_1[184], oflux_egress_direct_lane2_1[183], oflux_egress_direct_lane2_1[182], oflux_egress_direct_lane2_1[181], oflux_egress_direct_lane2_1[180], oflux_egress_direct_lane2_1[179], oflux_egress_direct_lane2_1[178], oflux_egress_direct_lane2_1[177], oflux_egress_direct_lane2_1[176], oflux_egress_direct_lane2_1[175], oflux_egress_direct_lane2_1[174], oflux_egress_direct_lane2_1[173], oflux_egress_direct_lane2_1[172], oflux_egress_direct_lane2_1[171], oflux_egress_direct_lane2_1[170], oflux_egress_direct_lane2_1[169], oflux_egress_direct_lane2_1[168], oflux_egress_direct_lane2_1[167], oflux_egress_direct_lane2_1[166], oflux_egress_direct_lane2_1[165], oflux_egress_direct_lane2_1[164], oflux_egress_direct_lane2_1[163], oflux_egress_direct_lane2_1[162], oflux_egress_direct_lane2_1[161], oflux_egress_direct_lane2_1[160], oflux_egress_direct_lane2_1[159], oflux_egress_direct_lane2_1[158], oflux_egress_direct_lane2_1[157], oflux_egress_direct_lane2_1[156], oflux_egress_direct_lane2_1[155], oflux_egress_direct_lane2_1[154], oflux_egress_direct_lane2_1[153], oflux_egress_direct_lane2_1[152], oflux_egress_direct_lane2_1[151], oflux_egress_direct_lane2_1[150], oflux_egress_direct_lane2_1[149], oflux_egress_direct_lane2_1[148], oflux_egress_direct_lane2_1[147], oflux_egress_direct_lane2_1[146], oflux_egress_direct_lane2_1[145], oflux_egress_direct_lane2_1[144], oflux_egress_direct_lane2_1[143], oflux_egress_direct_lane2_1[142], oflux_egress_direct_lane2_1[141], oflux_egress_direct_lane2_1[140], oflux_egress_direct_lane2_1[139], oflux_egress_direct_lane2_1[138], oflux_egress_direct_lane2_1[137], oflux_egress_direct_lane2_1[136], oflux_egress_direct_lane2_1[135], oflux_egress_direct_lane2_1[134], oflux_egress_direct_lane2_1[133], oflux_egress_direct_lane2_1[132], oflux_egress_direct_lane2_1[131], oflux_egress_direct_lane2_1[130], oflux_egress_direct_lane2_1[129], oflux_egress_direct_lane2_1[128], oflux_egress_direct_lane2_1[127], oflux_egress_direct_lane2_1[126], oflux_egress_direct_lane2_1[125], oflux_egress_direct_lane2_1[124], oflux_egress_direct_lane2_1[123], oflux_egress_direct_lane2_1[122], oflux_egress_direct_lane2_1[121], oflux_egress_direct_lane2_1[120], oflux_egress_direct_lane2_1[119], oflux_egress_direct_lane2_1[118], oflux_egress_direct_lane2_1[117], oflux_egress_direct_lane2_1[116], oflux_egress_direct_lane2_1[115], oflux_egress_direct_lane2_1[114], oflux_egress_direct_lane2_1[113], oflux_egress_direct_lane2_1[112], oflux_egress_direct_lane2_1[111], oflux_egress_direct_lane2_1[110], oflux_egress_direct_lane2_1[109], oflux_egress_direct_lane2_1[108], oflux_egress_direct_lane2_1[107], oflux_egress_direct_lane2_1[106], oflux_egress_direct_lane2_1[105], oflux_egress_direct_lane2_1[104], oflux_egress_direct_lane2_1[103], oflux_egress_direct_lane2_1[102], oflux_egress_direct_lane2_1[101], oflux_egress_direct_lane2_1[100], oflux_egress_direct_lane2_1[99], oflux_egress_direct_lane2_1[98], oflux_egress_direct_lane2_1[97], oflux_egress_direct_lane2_1[96], oflux_egress_direct_lane2_1[95], oflux_egress_direct_lane2_1[94], oflux_egress_direct_lane2_1[93], oflux_egress_direct_lane2_1[92], oflux_egress_direct_lane2_1[91], oflux_egress_direct_lane2_1[90], oflux_egress_direct_lane2_1[89], oflux_egress_direct_lane2_1[88], oflux_egress_direct_lane2_1[87], oflux_egress_direct_lane2_1[86], oflux_egress_direct_lane2_1[85], oflux_egress_direct_lane2_1[84], oflux_egress_direct_lane2_1[83], oflux_egress_direct_lane2_1[82], oflux_egress_direct_lane2_1[81], oflux_egress_direct_lane2_1[80], oflux_egress_direct_lane2_1[79], oflux_egress_direct_lane2_1[78], oflux_egress_direct_lane2_1[77], oflux_egress_direct_lane2_1[76], oflux_egress_direct_lane2_1[75], oflux_egress_direct_lane2_1[74], oflux_egress_direct_lane2_1[73], oflux_egress_direct_lane2_1[72], oflux_egress_direct_lane2_1[71], oflux_egress_direct_lane2_1[70], oflux_egress_direct_lane2_1[69], oflux_egress_direct_lane2_1[68], oflux_egress_direct_lane2_1[67], oflux_egress_direct_lane2_1[66], oflux_egress_direct_lane2_1[65], oflux_egress_direct_lane2_1[64], oflux_egress_direct_lane2_1[63], oflux_egress_direct_lane2_1[62], oflux_egress_direct_lane2_1[61], oflux_egress_direct_lane2_1[60], oflux_egress_direct_lane2_1[59], oflux_egress_direct_lane2_1[58], oflux_egress_direct_lane2_1[57], oflux_egress_direct_lane2_1[56], oflux_egress_direct_lane2_1[55], oflux_egress_direct_lane2_1[54], oflux_egress_direct_lane2_1[53], oflux_egress_direct_lane2_1[52], oflux_egress_direct_lane2_1[51], oflux_egress_direct_lane2_1[50], oflux_egress_direct_lane2_1[49], oflux_egress_direct_lane2_1[48], oflux_egress_direct_lane2_1[47], oflux_egress_direct_lane2_1[46], oflux_egress_direct_lane2_1[45], oflux_egress_direct_lane2_1[44], oflux_egress_direct_lane2_1[43], oflux_egress_direct_lane2_1[42], oflux_egress_direct_lane2_1[41], oflux_egress_direct_lane2_1[40], oflux_egress_direct_lane2_1[39], oflux_egress_direct_lane2_1[38], oflux_egress_direct_lane2_1[37], oflux_egress_direct_lane2_1[36], oflux_egress_direct_lane2_1[35], oflux_egress_direct_lane2_1[34], oflux_egress_direct_lane2_1[33], oflux_egress_direct_lane2_1[32], oflux_egress_direct_lane2_1[31], oflux_egress_direct_lane2_1[30], oflux_egress_direct_lane2_1[29], oflux_egress_direct_lane2_1[28], oflux_egress_direct_lane2_1[27], oflux_egress_direct_lane2_1[26], oflux_egress_direct_lane2_1[25], oflux_egress_direct_lane2_1[24], oflux_egress_direct_lane2_1[23], oflux_egress_direct_lane2_1[22], oflux_egress_direct_lane2_1[21], oflux_egress_direct_lane2_1[20], oflux_egress_direct_lane2_1[19], oflux_egress_direct_lane2_1[18], oflux_egress_direct_lane2_1[17], oflux_egress_direct_lane2_1[16], oflux_egress_direct_lane2_1[15], oflux_egress_direct_lane2_1[14], oflux_egress_direct_lane2_1[13], oflux_egress_direct_lane2_1[12], oflux_egress_direct_lane2_1[11], oflux_egress_direct_lane2_1[10], oflux_egress_direct_lane2_1[9], oflux_egress_direct_lane2_1[8], oflux_egress_direct_lane2_1[7], oflux_egress_direct_lane2_1[6], oflux_egress_direct_lane2_1[5], oflux_egress_direct_lane2_1[4], oflux_egress_direct_lane2_1[3], oflux_egress_direct_lane2_1[2], oflux_egress_direct_lane2_1[1], oflux_egress_direct_lane2_1[0] }),
		.oflux_egress_direct_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[256], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[255], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[254], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[253], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[252], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[251], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[250], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[249], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[248], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[247], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[246], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[245], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[244], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[243], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[242], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[241], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[240], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[239], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[238], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[237], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[236], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[235], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[234], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[233], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[232], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[231], 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x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_egress_direct_lane3_0[0] }),
		.oflux_ext_pcs_prdata({ oflux_ext_pcs_prdata_1[31], oflux_ext_pcs_prdata_1[30], oflux_ext_pcs_prdata_1[29], oflux_ext_pcs_prdata_1[28], oflux_ext_pcs_prdata_1[27], oflux_ext_pcs_prdata_1[26], oflux_ext_pcs_prdata_1[25], oflux_ext_pcs_prdata_1[24], oflux_ext_pcs_prdata_1[23], oflux_ext_pcs_prdata_1[22], oflux_ext_pcs_prdata_1[21], oflux_ext_pcs_prdata_1[20], oflux_ext_pcs_prdata_1[19], oflux_ext_pcs_prdata_1[18], oflux_ext_pcs_prdata_1[17], oflux_ext_pcs_prdata_1[16], oflux_ext_pcs_prdata_1[15], oflux_ext_pcs_prdata_1[14], oflux_ext_pcs_prdata_1[13], oflux_ext_pcs_prdata_1[12], oflux_ext_pcs_prdata_1[11], oflux_ext_pcs_prdata_1[10], oflux_ext_pcs_prdata_1[9], oflux_ext_pcs_prdata_1[8], oflux_ext_pcs_prdata_1[7], oflux_ext_pcs_prdata_1[6], oflux_ext_pcs_prdata_1[5], oflux_ext_pcs_prdata_1[4], oflux_ext_pcs_prdata_1[3], oflux_ext_pcs_prdata_1[2], oflux_ext_pcs_prdata_1[1], oflux_ext_pcs_prdata_1[0] }),
		.oflux_ext_pcs_pready(oflux_ext_pcs_pready_1),
		.oflux_ext_pcs_pslverr(oflux_ext_pcs_pslverr_1),
		.oflux_int0(oflux_int0_1),
		.oflux_int1(oflux_int1_1),
		.oflux_int2(oflux_int2_1),
		.oflux_int3(oflux_int3_1),
		.oflux_mem_dram0addr({ oflux_mem_DRam0Addr_1[15], oflux_mem_DRam0Addr_1[14], oflux_mem_DRam0Addr_1[13], oflux_mem_DRam0Addr_1[12], oflux_mem_DRam0Addr_1[11], oflux_mem_DRam0Addr_1[10], oflux_mem_DRam0Addr_1[9], oflux_mem_DRam0Addr_1[8], oflux_mem_DRam0Addr_1[7], oflux_mem_DRam0Addr_1[6], oflux_mem_DRam0Addr_1[5], oflux_mem_DRam0Addr_1[4], oflux_mem_DRam0Addr_1[3], oflux_mem_DRam0Addr_1[2] }),
		.oflux_mem_dram0byteen({ oflux_mem_DRam0ByteEn_1[3], oflux_mem_DRam0ByteEn_1[2], oflux_mem_DRam0ByteEn_1[1], oflux_mem_DRam0ByteEn_1[0] }),
		.oflux_mem_dram0checkwrdata({ oflux_mem_DRam0CheckWrData_1[19], oflux_mem_DRam0CheckWrData_1[18], oflux_mem_DRam0CheckWrData_1[17], oflux_mem_DRam0CheckWrData_1[16], oflux_mem_DRam0CheckWrData_1[15], oflux_mem_DRam0CheckWrData_1[14], oflux_mem_DRam0CheckWrData_1[13], oflux_mem_DRam0CheckWrData_1[12], oflux_mem_DRam0CheckWrData_1[11], oflux_mem_DRam0CheckWrData_1[10], oflux_mem_DRam0CheckWrData_1[9], oflux_mem_DRam0CheckWrData_1[8], oflux_mem_DRam0CheckWrData_1[7], oflux_mem_DRam0CheckWrData_1[6], oflux_mem_DRam0CheckWrData_1[5], oflux_mem_DRam0CheckWrData_1[4], oflux_mem_DRam0CheckWrData_1[3], oflux_mem_DRam0CheckWrData_1[2], oflux_mem_DRam0CheckWrData_1[1], oflux_mem_DRam0CheckWrData_1[0] }),
		.oflux_mem_dram0en(oflux_mem_DRam0En_1),
		.oflux_mem_dram0wr(oflux_mem_DRam0Wr_1),
		.oflux_mem_dram0wrdata({ oflux_mem_DRam0WrData_1[31], oflux_mem_DRam0WrData_1[30], oflux_mem_DRam0WrData_1[29], oflux_mem_DRam0WrData_1[28], oflux_mem_DRam0WrData_1[27], oflux_mem_DRam0WrData_1[26], oflux_mem_DRam0WrData_1[25], oflux_mem_DRam0WrData_1[24], oflux_mem_DRam0WrData_1[23], oflux_mem_DRam0WrData_1[22], oflux_mem_DRam0WrData_1[21], oflux_mem_DRam0WrData_1[20], oflux_mem_DRam0WrData_1[19], oflux_mem_DRam0WrData_1[18], oflux_mem_DRam0WrData_1[17], oflux_mem_DRam0WrData_1[16], oflux_mem_DRam0WrData_1[15], oflux_mem_DRam0WrData_1[14], oflux_mem_DRam0WrData_1[13], oflux_mem_DRam0WrData_1[12], oflux_mem_DRam0WrData_1[11], oflux_mem_DRam0WrData_1[10], oflux_mem_DRam0WrData_1[9], oflux_mem_DRam0WrData_1[8], oflux_mem_DRam0WrData_1[7], oflux_mem_DRam0WrData_1[6], oflux_mem_DRam0WrData_1[5], oflux_mem_DRam0WrData_1[4], oflux_mem_DRam0WrData_1[3], oflux_mem_DRam0WrData_1[2], oflux_mem_DRam0WrData_1[1], oflux_mem_DRam0WrData_1[0] }),
		.oflux_mem_iram0addr({ oflux_mem_IRam0Addr_1[16], oflux_mem_IRam0Addr_1[15], oflux_mem_IRam0Addr_1[14], oflux_mem_IRam0Addr_1[13], oflux_mem_IRam0Addr_1[12], oflux_mem_IRam0Addr_1[11], oflux_mem_IRam0Addr_1[10], oflux_mem_IRam0Addr_1[9], oflux_mem_IRam0Addr_1[8], oflux_mem_IRam0Addr_1[7], oflux_mem_IRam0Addr_1[6], oflux_mem_IRam0Addr_1[5], oflux_mem_IRam0Addr_1[4], oflux_mem_IRam0Addr_1[3], oflux_mem_IRam0Addr_1[2] }),
		.oflux_mem_iram0checkwrdata({ oflux_mem_IRam0CheckWrData_1[6], oflux_mem_IRam0CheckWrData_1[5], oflux_mem_IRam0CheckWrData_1[4], oflux_mem_IRam0CheckWrData_1[3], oflux_mem_IRam0CheckWrData_1[2], oflux_mem_IRam0CheckWrData_1[1], oflux_mem_IRam0CheckWrData_1[0] }),
		.oflux_mem_iram0en(oflux_mem_IRam0En_1),
		.oflux_mem_iram0wr(oflux_mem_IRam0Wr_1),
		.oflux_mem_iram0wrdata({ oflux_mem_IRam0WrData_1[31], oflux_mem_IRam0WrData_1[30], oflux_mem_IRam0WrData_1[29], oflux_mem_IRam0WrData_1[28], oflux_mem_IRam0WrData_1[27], oflux_mem_IRam0WrData_1[26], oflux_mem_IRam0WrData_1[25], oflux_mem_IRam0WrData_1[24], oflux_mem_IRam0WrData_1[23], oflux_mem_IRam0WrData_1[22], oflux_mem_IRam0WrData_1[21], oflux_mem_IRam0WrData_1[20], oflux_mem_IRam0WrData_1[19], oflux_mem_IRam0WrData_1[18], oflux_mem_IRam0WrData_1[17], oflux_mem_IRam0WrData_1[16], oflux_mem_IRam0WrData_1[15], oflux_mem_IRam0WrData_1[14], oflux_mem_IRam0WrData_1[13], oflux_mem_IRam0WrData_1[12], oflux_mem_IRam0WrData_1[11], oflux_mem_IRam0WrData_1[10], oflux_mem_IRam0WrData_1[9], oflux_mem_IRam0WrData_1[8], oflux_mem_IRam0WrData_1[7], oflux_mem_IRam0WrData_1[6], oflux_mem_IRam0WrData_1[5], oflux_mem_IRam0WrData_1[4], oflux_mem_IRam0WrData_1[3], oflux_mem_IRam0WrData_1[2], oflux_mem_IRam0WrData_1[1], oflux_mem_IRam0WrData_1[0] }),
		.oflux_mem_qfifo_rd_addr({ oflux_mem_qfifo_rd_addr_1[8], oflux_mem_qfifo_rd_addr_1[7], oflux_mem_qfifo_rd_addr_1[6], oflux_mem_qfifo_rd_addr_1[5], oflux_mem_qfifo_rd_addr_1[4], oflux_mem_qfifo_rd_addr_1[3], oflux_mem_qfifo_rd_addr_1[2], oflux_mem_qfifo_rd_addr_1[1], oflux_mem_qfifo_rd_addr_1[0] }),
		.oflux_mem_qfifo_rd_en(oflux_mem_qfifo_rd_en_1),
		.oflux_mem_qfifo_wr_addr({ oflux_mem_qfifo_wr_addr_1[8], oflux_mem_qfifo_wr_addr_1[7], oflux_mem_qfifo_wr_addr_1[6], oflux_mem_qfifo_wr_addr_1[5], oflux_mem_qfifo_wr_addr_1[4], oflux_mem_qfifo_wr_addr_1[3], oflux_mem_qfifo_wr_addr_1[2], oflux_mem_qfifo_wr_addr_1[1], oflux_mem_qfifo_wr_addr_1[0] }),
		.oflux_mem_qfifo_wr_data({ oflux_mem_qfifo_wr_data_1[31], oflux_mem_qfifo_wr_data_1[30], oflux_mem_qfifo_wr_data_1[29], oflux_mem_qfifo_wr_data_1[28], oflux_mem_qfifo_wr_data_1[27], oflux_mem_qfifo_wr_data_1[26], oflux_mem_qfifo_wr_data_1[25], oflux_mem_qfifo_wr_data_1[24], oflux_mem_qfifo_wr_data_1[23], oflux_mem_qfifo_wr_data_1[22], oflux_mem_qfifo_wr_data_1[21], oflux_mem_qfifo_wr_data_1[20], oflux_mem_qfifo_wr_data_1[19], oflux_mem_qfifo_wr_data_1[18], oflux_mem_qfifo_wr_data_1[17], oflux_mem_qfifo_wr_data_1[16], oflux_mem_qfifo_wr_data_1[15], oflux_mem_qfifo_wr_data_1[14], oflux_mem_qfifo_wr_data_1[13], oflux_mem_qfifo_wr_data_1[12], oflux_mem_qfifo_wr_data_1[11], oflux_mem_qfifo_wr_data_1[10], oflux_mem_qfifo_wr_data_1[9], oflux_mem_qfifo_wr_data_1[8], oflux_mem_qfifo_wr_data_1[7], oflux_mem_qfifo_wr_data_1[6], oflux_mem_qfifo_wr_data_1[5], oflux_mem_qfifo_wr_data_1[4], oflux_mem_qfifo_wr_data_1[3], oflux_mem_qfifo_wr_data_1[2], oflux_mem_qfifo_wr_data_1[1], oflux_mem_qfifo_wr_data_1[0] }),
		.oflux_mem_qfifo_wr_en(oflux_mem_qfifo_wr_en_1),
		.oflux_mem_tracememaddr({ oflux_mem_TraceMemAddr_1[8], oflux_mem_TraceMemAddr_1[7], oflux_mem_TraceMemAddr_1[6], oflux_mem_TraceMemAddr_1[5], oflux_mem_TraceMemAddr_1[4], oflux_mem_TraceMemAddr_1[3], oflux_mem_TraceMemAddr_1[2], oflux_mem_TraceMemAddr_1[1], oflux_mem_TraceMemAddr_1[0] }),
		.oflux_mem_tracememen(oflux_mem_TraceMemEn_1),
		.oflux_mem_tracememwr(oflux_mem_TraceMemWr_1),
		.oflux_mem_tracememwrdata({ oflux_mem_TraceMemWrData_1[31], oflux_mem_TraceMemWrData_1[30], oflux_mem_TraceMemWrData_1[29], oflux_mem_TraceMemWrData_1[28], oflux_mem_TraceMemWrData_1[27], oflux_mem_TraceMemWrData_1[26], oflux_mem_TraceMemWrData_1[25], oflux_mem_TraceMemWrData_1[24], oflux_mem_TraceMemWrData_1[23], oflux_mem_TraceMemWrData_1[22], oflux_mem_TraceMemWrData_1[21], oflux_mem_TraceMemWrData_1[20], oflux_mem_TraceMemWrData_1[19], oflux_mem_TraceMemWrData_1[18], oflux_mem_TraceMemWrData_1[17], oflux_mem_TraceMemWrData_1[16], oflux_mem_TraceMemWrData_1[15], oflux_mem_TraceMemWrData_1[14], oflux_mem_TraceMemWrData_1[13], oflux_mem_TraceMemWrData_1[12], oflux_mem_TraceMemWrData_1[11], oflux_mem_TraceMemWrData_1[10], oflux_mem_TraceMemWrData_1[9], oflux_mem_TraceMemWrData_1[8], oflux_mem_TraceMemWrData_1[7], oflux_mem_TraceMemWrData_1[6], oflux_mem_TraceMemWrData_1[5], oflux_mem_TraceMemWrData_1[4], oflux_mem_TraceMemWrData_1[3], oflux_mem_TraceMemWrData_1[2], oflux_mem_TraceMemWrData_1[1], oflux_mem_TraceMemWrData_1[0] }),
		.oflux_octl_pcs_txptr_smpl_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane0_1),
		.oflux_octl_pcs_txptr_smpl_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane1_1),
		.oflux_octl_pcs_txptr_smpl_lane2(oflux_octl_pcs_txptr_smpl_lane2_1),
		.oflux_octl_pcs_txptr_smpl_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_octl_pcs_txptr_smpl_lane3_1),
		.oflux_pcs_rxword_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane0_0[0] }),
		.oflux_pcs_rxword_lane1({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane1_0[0] }),
		.oflux_pcs_rxword_lane2({ oflux_pcs_rxword_lane2_1[79], oflux_pcs_rxword_lane2_1[78], oflux_pcs_rxword_lane2_1[77], oflux_pcs_rxword_lane2_1[76], oflux_pcs_rxword_lane2_1[75], oflux_pcs_rxword_lane2_1[74], oflux_pcs_rxword_lane2_1[73], oflux_pcs_rxword_lane2_1[72], oflux_pcs_rxword_lane2_1[71], oflux_pcs_rxword_lane2_1[70], oflux_pcs_rxword_lane2_1[69], oflux_pcs_rxword_lane2_1[68], oflux_pcs_rxword_lane2_1[67], oflux_pcs_rxword_lane2_1[66], oflux_pcs_rxword_lane2_1[65], oflux_pcs_rxword_lane2_1[64], oflux_pcs_rxword_lane2_1[63], oflux_pcs_rxword_lane2_1[62], oflux_pcs_rxword_lane2_1[61], oflux_pcs_rxword_lane2_1[60], oflux_pcs_rxword_lane2_1[59], oflux_pcs_rxword_lane2_1[58], oflux_pcs_rxword_lane2_1[57], oflux_pcs_rxword_lane2_1[56], oflux_pcs_rxword_lane2_1[55], oflux_pcs_rxword_lane2_1[54], oflux_pcs_rxword_lane2_1[53], oflux_pcs_rxword_lane2_1[52], oflux_pcs_rxword_lane2_1[51], oflux_pcs_rxword_lane2_1[50], oflux_pcs_rxword_lane2_1[49], oflux_pcs_rxword_lane2_1[48], oflux_pcs_rxword_lane2_1[47], oflux_pcs_rxword_lane2_1[46], oflux_pcs_rxword_lane2_1[45], oflux_pcs_rxword_lane2_1[44], oflux_pcs_rxword_lane2_1[43], oflux_pcs_rxword_lane2_1[42], oflux_pcs_rxword_lane2_1[41], oflux_pcs_rxword_lane2_1[40], oflux_pcs_rxword_lane2_1[39], oflux_pcs_rxword_lane2_1[38], oflux_pcs_rxword_lane2_1[37], oflux_pcs_rxword_lane2_1[36], oflux_pcs_rxword_lane2_1[35], oflux_pcs_rxword_lane2_1[34], oflux_pcs_rxword_lane2_1[33], oflux_pcs_rxword_lane2_1[32], oflux_pcs_rxword_lane2_1[31], oflux_pcs_rxword_lane2_1[30], oflux_pcs_rxword_lane2_1[29], oflux_pcs_rxword_lane2_1[28], oflux_pcs_rxword_lane2_1[27], oflux_pcs_rxword_lane2_1[26], oflux_pcs_rxword_lane2_1[25], oflux_pcs_rxword_lane2_1[24], oflux_pcs_rxword_lane2_1[23], oflux_pcs_rxword_lane2_1[22], oflux_pcs_rxword_lane2_1[21], oflux_pcs_rxword_lane2_1[20], oflux_pcs_rxword_lane2_1[19], oflux_pcs_rxword_lane2_1[18], oflux_pcs_rxword_lane2_1[17], oflux_pcs_rxword_lane2_1[16], oflux_pcs_rxword_lane2_1[15], oflux_pcs_rxword_lane2_1[14], oflux_pcs_rxword_lane2_1[13], oflux_pcs_rxword_lane2_1[12], oflux_pcs_rxword_lane2_1[11], oflux_pcs_rxword_lane2_1[10], oflux_pcs_rxword_lane2_1[9], oflux_pcs_rxword_lane2_1[8], oflux_pcs_rxword_lane2_1[7], oflux_pcs_rxword_lane2_1[6], oflux_pcs_rxword_lane2_1[5], oflux_pcs_rxword_lane2_1[4], oflux_pcs_rxword_lane2_1[3], oflux_pcs_rxword_lane2_1[2], oflux_pcs_rxword_lane2_1[1], oflux_pcs_rxword_lane2_1[0] }),
		.oflux_pcs_rxword_lane3({ x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_pcs_rxword_lane3_0[0] }),
		.oflux_srds_rdy0(oflux_srds_rdy0_1),
		.oflux_srds_rdy1(oflux_srds_rdy1_1),
		.oflux_srds_rdy2(oflux_srds_rdy2_1),
		.oflux_srds_rdy3(oflux_srds_rdy3_1),
		.oflux_srds_rx_clk_lane0(oflux_srds_rx_clk_lane0_1),
		.oflux_srds_rx_clk_lane1(oflux_srds_rx_clk_lane1_1),
		.oflux_srds_rx_clk_lane2(oflux_srds_rx_clk_lane2_1),
		.oflux_srds_rx_clk_lane3(oflux_srds_rx_clk_lane3_1),
		.oflux_srds_rx_divn_clk_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane0_1),
		.oflux_srds_rx_divn_clk_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane1_1),
		.oflux_srds_rx_divn_clk_lane2(oflux_srds_rx_divn_clk_lane2_1),
		.oflux_srds_rx_divn_clk_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_rx_divn_clk_lane3_1),
		.oflux_srds_tx_clk_lane0(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane0_1),
		.oflux_srds_tx_clk_lane1(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane1_1),
		.oflux_srds_tx_clk_lane2(oflux_srds_tx_clk_lane2_1),
		.oflux_srds_tx_clk_lane3(x_std_ipfluxtop_flux_core_shim_wrap_0__oflux_srds_tx_clk_lane3_1),
		.uxwrap_bus_in_lane0({ x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[767], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[766], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[765], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[764], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[763], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[762], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[761], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[760], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[759], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[758], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[757], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[756], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[755], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_in_lane0_0[754], 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		.uxwrap_bus_in_lane2({ uxwrap_bus_in_lane2_0[767], uxwrap_bus_in_lane2_0[766], uxwrap_bus_in_lane2_0[765], uxwrap_bus_in_lane2_0[764], uxwrap_bus_in_lane2_0[763], uxwrap_bus_in_lane2_0[762], uxwrap_bus_in_lane2_0[761], uxwrap_bus_in_lane2_0[760], uxwrap_bus_in_lane2_0[759], uxwrap_bus_in_lane2_0[758], uxwrap_bus_in_lane2_0[757], uxwrap_bus_in_lane2_0[756], uxwrap_bus_in_lane2_0[755], uxwrap_bus_in_lane2_0[754], uxwrap_bus_in_lane2_0[753], uxwrap_bus_in_lane2_0[752], uxwrap_bus_in_lane2_0[751], uxwrap_bus_in_lane2_0[750], uxwrap_bus_in_lane2_0[749], uxwrap_bus_in_lane2_0[748], uxwrap_bus_in_lane2_0[747], uxwrap_bus_in_lane2_0[746], uxwrap_bus_in_lane2_0[745], uxwrap_bus_in_lane2_0[744], uxwrap_bus_in_lane2_0[743], uxwrap_bus_in_lane2_0[742], uxwrap_bus_in_lane2_0[741], uxwrap_bus_in_lane2_0[740], uxwrap_bus_in_lane2_0[739], uxwrap_bus_in_lane2_0[738], uxwrap_bus_in_lane2_0[737], uxwrap_bus_in_lane2_0[736], uxwrap_bus_in_lane2_0[735], uxwrap_bus_in_lane2_0[734], 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x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane1_0[0] }),
		.uxwrap_bus_out_lane2({ uxwrap_bus_out_lane2_1[703], uxwrap_bus_out_lane2_1[702], uxwrap_bus_out_lane2_1[701], uxwrap_bus_out_lane2_1[700], uxwrap_bus_out_lane2_1[699], uxwrap_bus_out_lane2_1[698], uxwrap_bus_out_lane2_1[697], uxwrap_bus_out_lane2_1[696], uxwrap_bus_out_lane2_1[695], uxwrap_bus_out_lane2_1[694], uxwrap_bus_out_lane2_1[693], uxwrap_bus_out_lane2_1[692], uxwrap_bus_out_lane2_1[691], uxwrap_bus_out_lane2_1[690], uxwrap_bus_out_lane2_1[689], uxwrap_bus_out_lane2_1[688], uxwrap_bus_out_lane2_1[687], uxwrap_bus_out_lane2_1[686], uxwrap_bus_out_lane2_1[685], uxwrap_bus_out_lane2_1[684], uxwrap_bus_out_lane2_1[683], uxwrap_bus_out_lane2_1[682], uxwrap_bus_out_lane2_1[681], uxwrap_bus_out_lane2_1[680], uxwrap_bus_out_lane2_1[679], uxwrap_bus_out_lane2_1[678], uxwrap_bus_out_lane2_1[677], uxwrap_bus_out_lane2_1[676], uxwrap_bus_out_lane2_1[675], uxwrap_bus_out_lane2_1[674], uxwrap_bus_out_lane2_1[673], uxwrap_bus_out_lane2_1[672], uxwrap_bus_out_lane2_1[671], uxwrap_bus_out_lane2_1[670], uxwrap_bus_out_lane2_1[669], uxwrap_bus_out_lane2_1[668], uxwrap_bus_out_lane2_1[667], uxwrap_bus_out_lane2_1[666], uxwrap_bus_out_lane2_1[665], uxwrap_bus_out_lane2_1[664], uxwrap_bus_out_lane2_1[663], uxwrap_bus_out_lane2_1[662], uxwrap_bus_out_lane2_1[661], uxwrap_bus_out_lane2_1[660], uxwrap_bus_out_lane2_1[659], uxwrap_bus_out_lane2_1[658], uxwrap_bus_out_lane2_1[657], uxwrap_bus_out_lane2_1[656], uxwrap_bus_out_lane2_1[655], uxwrap_bus_out_lane2_1[654], uxwrap_bus_out_lane2_1[653], uxwrap_bus_out_lane2_1[652], uxwrap_bus_out_lane2_1[651], uxwrap_bus_out_lane2_1[650], uxwrap_bus_out_lane2_1[649], uxwrap_bus_out_lane2_1[648], uxwrap_bus_out_lane2_1[647], uxwrap_bus_out_lane2_1[646], uxwrap_bus_out_lane2_1[645], uxwrap_bus_out_lane2_1[644], uxwrap_bus_out_lane2_1[643], uxwrap_bus_out_lane2_1[642], uxwrap_bus_out_lane2_1[641], uxwrap_bus_out_lane2_1[640], uxwrap_bus_out_lane2_1[639], uxwrap_bus_out_lane2_1[638], uxwrap_bus_out_lane2_1[637], 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x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[115], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[114], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[113], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[112], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[111], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[110], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[109], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[108], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[107], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[106], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[105], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[104], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[103], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[102], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[101], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[100], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[99], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[98], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[97], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[96], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[95], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[94], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[93], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[92], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[91], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[90], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[89], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[88], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[87], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[86], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[85], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[84], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[83], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[82], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[81], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[80], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[79], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[78], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[77], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[76], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[75], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[74], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[73], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[72], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[71], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[70], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[69], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[68], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[67], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[66], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[65], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[64], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[63], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[62], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[61], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[60], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[59], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[58], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[57], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[56], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[55], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[54], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[53], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[52], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[51], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[50], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[49], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[48], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[47], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[46], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[45], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[44], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[43], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[42], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[41], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[40], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[39], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[38], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[37], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[36], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[35], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[34], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[33], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[32], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[31], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[30], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[29], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[28], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[27], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[26], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[25], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[24], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[23], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[22], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[21], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[20], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[19], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[18], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[17], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[16], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[15], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[14], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[13], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[12], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[11], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[10], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[9], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[8], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[7], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[6], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[5], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[4], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[3], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[2], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[1], x_std_ipfluxtop_flux_core_shim_wrap_0__uxwrap_bus_out_lane3_0[0] })
	);

	tennm_sm_flux_dpma_clk_mux #(
		.sel(x_mux_sm_flux_dpma_clk_mux_0__sel)
	) x_mux_sm_flux_dpma_clk_mux_0 (
		.i_cnoc_clk(flux_ingress_cnoc_clk_u0__o_cnoc_clk_2),
		.i_global_downward_syspll_c2_clk(x_mux_sm_flux_dpma_clk_mux_0__i_global_downward_syspll_c2_clk_1),
		.i_global_upward_syspll_c2_clk(x_mux_sm_flux_dpma_clk_mux_0__i_global_upward_syspll_c2_clk_1),
		.i_local_syspll_c2_clk(x_mux_sm_flux_dpma_clk_mux_0__i_local_syspll_c2_clk_1),
		.o_ux_dpma_clk(o_ux_dpma_clk_2)
	);

	tennm_sm_cnoc_clk x_std_sm_cnoc_clk_0 (
		.o_cnoc_clk(flux_ingress_cnoc_clk_u0__o_cnoc_clk_2)
	);

	tennm_sm_flux_rx_rxword_clk_demux #(
		.sel(x_decoder_sm_flux_rx_rxword_clk_demux_0__sel)
	) x_decoder_sm_flux_rx_rxword_clk_demux_0 (
		.i_ock_pcs_rxword(flux_ingress_u2__o_pcs_rxword_0),
		.o_eth_rxword_clk(o_ux_eth_rxword_clk_2),
		.o_pcie_rxword_clk(o_ux_pcie_rxword_clk_2)
	);

	tennm_sm_flux_rx_user_clk_mux_module x_dynMux_sm_flux_rx_user_clk_mux_0 (
		.i_ock_pcs_rxpostdiv(flux_ingress_u2__o_pcs_rxpostdiv_0),
		.i_ock_pcs_rxword(flux_ingress_u2__o_pcs_rxword_0),
		.i_sel({ flux_ingress_u2__o_ux_rxuser1_sel_0[1], flux_ingress_u2__o_ux_rxuser1_sel_0[0] }),
		.o_ux_rxuser_clk(x_dynMux_sm_flux_rx_user_clk_mux_0__o_ux_rxuser_clk_1)
	);

	tennm_sm_flux_rx_user_clk_mux_module x_dynMux_sm_flux_rx_user_clk_mux_1 (
		.i_ock_pcs_rxpostdiv(flux_ingress_u2__o_pcs_rxpostdiv_0),
		.i_ock_pcs_rxword(flux_ingress_u2__o_pcs_rxword_0),
		.i_sel({ flux_ingress_u2__o_ux_rxuser2_sel_0[1], flux_ingress_u2__o_ux_rxuser2_sel_0[0] }),
		.o_ux_rxuser_clk(x_dynMux_sm_flux_rx_user_clk_mux_1__o_ux_rxuser_clk_1)
	);

	tennm_sm_flux_tx_txword_clk_demux #(
		.sel(x_decoder_sm_flux_tx_txword_clk_demux_0__sel)
	) x_decoder_sm_flux_tx_txword_clk_demux_0 (
		.i_ock_pcs_txword(flux_ingress_u2__o_ock_pcs_txword_0),
		.o_eth_txword_clk(o_ux_eth_txword_clk_2),
		.o_pcie_txword_clk(o_ux_pcie_txword_clk_2)
	);

	tennm_sm_flux_tx_txword_clk_mux #(
		.sel(x_mux_sm_flux_tx_txword_clk_mux_0__sel)
	) x_mux_sm_flux_tx_txword_clk_mux_0 (
		.i_ux_ock_pma_clk(o_ux2_ock_pma_clk_1),
		.i_xcvr_txword_clk(o_xcvr_txword_ch_clk_2),
		.o_pcs_txword(o_pcs_txword_2)
	);

	tennm_sm_flux_tx_user_clk_mux_module x_dynMux_sm_flux_tx_user_clk_mux_0 (
		.i_ock_pcs_txword_clk(flux_ingress_u2__o_ock_pcs_txword_0),
		.i_sel({ flux_ingress_u2__o_ux_txuser1_sel_0[1], flux_ingress_u2__o_ux_txuser1_sel_0[0] }),
		.i_ux_txlc_clk(flux_ingress_u2__o_ux_txlc_clk_0),
		.o_ux_txuser_clk(x_dynMux_sm_flux_tx_user_clk_mux_0__o_ux_txuser_clk_1)
	);

	tennm_sm_flux_tx_user_clk_mux_module x_dynMux_sm_flux_tx_user_clk_mux_1 (
		.i_ock_pcs_txword_clk(flux_ingress_u2__o_ock_pcs_txword_0),
		.i_sel({ flux_ingress_u2__o_ux_txuser2_sel_0[1], flux_ingress_u2__o_ux_txuser2_sel_0[0] }),
		.i_ux_txlc_clk(flux_ingress_u2__o_ux_txlc_clk_0),
		.o_ux_txuser_clk(x_dynMux_sm_flux_tx_user_clk_mux_1__o_ux_txuser_clk_1)
	);

	tennm_sm_flux_rx_demux #(
		.sel(x_decoder_sm_flux_rx_demux_0__sel)
	) x_decoder_sm_flux_rx_demux_0 (
		.i_rx_data({ flux_mux_wrapper_u2__i_rx_data_0[39], flux_mux_wrapper_u2__i_rx_data_0[38], flux_mux_wrapper_u2__i_rx_data_0[37], flux_mux_wrapper_u2__i_rx_data_0[36], flux_mux_wrapper_u2__i_rx_data_0[35], flux_mux_wrapper_u2__i_rx_data_0[34], flux_mux_wrapper_u2__i_rx_data_0[33], flux_mux_wrapper_u2__i_rx_data_0[32], flux_mux_wrapper_u2__i_rx_data_0[31], flux_mux_wrapper_u2__i_rx_data_0[30], flux_mux_wrapper_u2__i_rx_data_0[29], flux_mux_wrapper_u2__i_rx_data_0[28], flux_mux_wrapper_u2__i_rx_data_0[27], flux_mux_wrapper_u2__i_rx_data_0[26], flux_mux_wrapper_u2__i_rx_data_0[25], flux_mux_wrapper_u2__i_rx_data_0[24], flux_mux_wrapper_u2__i_rx_data_0[23], flux_mux_wrapper_u2__i_rx_data_0[22], flux_mux_wrapper_u2__i_rx_data_0[21], flux_mux_wrapper_u2__i_rx_data_0[20], flux_mux_wrapper_u2__i_rx_data_0[19], flux_mux_wrapper_u2__i_rx_data_0[18], flux_mux_wrapper_u2__i_rx_data_0[17], flux_mux_wrapper_u2__i_rx_data_0[16], flux_mux_wrapper_u2__i_rx_data_0[15], flux_mux_wrapper_u2__i_rx_data_0[14], flux_mux_wrapper_u2__i_rx_data_0[13], flux_mux_wrapper_u2__i_rx_data_0[12], flux_mux_wrapper_u2__i_rx_data_0[11], flux_mux_wrapper_u2__i_rx_data_0[10], flux_mux_wrapper_u2__i_rx_data_0[9], flux_mux_wrapper_u2__i_rx_data_0[8], flux_mux_wrapper_u2__i_rx_data_0[7], flux_mux_wrapper_u2__i_rx_data_0[6], flux_mux_wrapper_u2__i_rx_data_0[5], flux_mux_wrapper_u2__i_rx_data_0[4], flux_mux_wrapper_u2__i_rx_data_0[3], flux_mux_wrapper_u2__i_rx_data_0[2], flux_mux_wrapper_u2__i_rx_data_0[1], flux_mux_wrapper_u2__i_rx_data_0[0] }),
		.o_pcie_pcs({ o_pcie_rx_data_2[39], o_pcie_rx_data_2[38], o_pcie_rx_data_2[37], o_pcie_rx_data_2[36], o_pcie_rx_data_2[35], o_pcie_rx_data_2[34], o_pcie_rx_data_2[33], o_pcie_rx_data_2[32], o_pcie_rx_data_2[31], o_pcie_rx_data_2[30], o_pcie_rx_data_2[29], o_pcie_rx_data_2[28], o_pcie_rx_data_2[27], o_pcie_rx_data_2[26], o_pcie_rx_data_2[25], o_pcie_rx_data_2[24], o_pcie_rx_data_2[23], o_pcie_rx_data_2[22], o_pcie_rx_data_2[21], o_pcie_rx_data_2[20], o_pcie_rx_data_2[19], o_pcie_rx_data_2[18], o_pcie_rx_data_2[17], o_pcie_rx_data_2[16], o_pcie_rx_data_2[15], o_pcie_rx_data_2[14], o_pcie_rx_data_2[13], o_pcie_rx_data_2[12], o_pcie_rx_data_2[11], o_pcie_rx_data_2[10], o_pcie_rx_data_2[9], o_pcie_rx_data_2[8], o_pcie_rx_data_2[7], o_pcie_rx_data_2[6], o_pcie_rx_data_2[5], o_pcie_rx_data_2[4], o_pcie_rx_data_2[3], o_pcie_rx_data_2[2], o_pcie_rx_data_2[1], o_pcie_rx_data_2[0] }),
		.o_xcvrif({ o_eth_rx_data_2[31], o_eth_rx_data_2[30], o_eth_rx_data_2[29], o_eth_rx_data_2[28], o_eth_rx_data_2[27], o_eth_rx_data_2[26], o_eth_rx_data_2[25], o_eth_rx_data_2[24], o_eth_rx_data_2[23], o_eth_rx_data_2[22], o_eth_rx_data_2[21], o_eth_rx_data_2[20], o_eth_rx_data_2[19], o_eth_rx_data_2[18], o_eth_rx_data_2[17], o_eth_rx_data_2[16], o_eth_rx_data_2[15], o_eth_rx_data_2[14], o_eth_rx_data_2[13], o_eth_rx_data_2[12], o_eth_rx_data_2[11], o_eth_rx_data_2[10], o_eth_rx_data_2[9], o_eth_rx_data_2[8], o_eth_rx_data_2[7], o_eth_rx_data_2[6], o_eth_rx_data_2[5], o_eth_rx_data_2[4], o_eth_rx_data_2[3], o_eth_rx_data_2[2], o_eth_rx_data_2[1], o_eth_rx_data_2[0] })
	);

	tennm_sm_flux_tx_mux #(
		.sel(x_mux_sm_flux_tx_mux_0__sel)
	) x_mux_sm_flux_tx_mux_0 (
		.i_pcie_pcs({ o_uxq2_txword_0[39], o_uxq2_txword_0[38], o_uxq2_txword_0[37], o_uxq2_txword_0[36], o_uxq2_txword_0[35], o_uxq2_txword_0[34], o_uxq2_txword_0[33], o_uxq2_txword_0[32], o_uxq2_txword_0[31], o_uxq2_txword_0[30], o_uxq2_txword_0[29], o_uxq2_txword_0[28], o_uxq2_txword_0[27], o_uxq2_txword_0[26], o_uxq2_txword_0[25], o_uxq2_txword_0[24], o_uxq2_txword_0[23], o_uxq2_txword_0[22], o_uxq2_txword_0[21], o_uxq2_txword_0[20], o_uxq2_txword_0[19], o_uxq2_txword_0[18], o_uxq2_txword_0[17], o_uxq2_txword_0[16], o_uxq2_txword_0[15], o_uxq2_txword_0[14], o_uxq2_txword_0[13], o_uxq2_txword_0[12], o_uxq2_txword_0[11], o_uxq2_txword_0[10], o_uxq2_txword_0[9], o_uxq2_txword_0[8], o_uxq2_txword_0[7], o_uxq2_txword_0[6], o_uxq2_txword_0[5], o_uxq2_txword_0[4], o_uxq2_txword_0[3], o_uxq2_txword_0[2], o_uxq2_txword_0[1], o_uxq2_txword_0[0] }),
		.i_xcvrif({ o_ux_tx_ch2_data_1[31], o_ux_tx_ch2_data_1[30], o_ux_tx_ch2_data_1[29], o_ux_tx_ch2_data_1[28], o_ux_tx_ch2_data_1[27], o_ux_tx_ch2_data_1[26], o_ux_tx_ch2_data_1[25], o_ux_tx_ch2_data_1[24], o_ux_tx_ch2_data_1[23], o_ux_tx_ch2_data_1[22], o_ux_tx_ch2_data_1[21], o_ux_tx_ch2_data_1[20], o_ux_tx_ch2_data_1[19], o_ux_tx_ch2_data_1[18], o_ux_tx_ch2_data_1[17], o_ux_tx_ch2_data_1[16], o_ux_tx_ch2_data_1[15], o_ux_tx_ch2_data_1[14], o_ux_tx_ch2_data_1[13], o_ux_tx_ch2_data_1[12], o_ux_tx_ch2_data_1[11], o_ux_tx_ch2_data_1[10], o_ux_tx_ch2_data_1[9], o_ux_tx_ch2_data_1[8], o_ux_tx_ch2_data_1[7], o_ux_tx_ch2_data_1[6], o_ux_tx_ch2_data_1[5], o_ux_tx_ch2_data_1[4], o_ux_tx_ch2_data_1[3], o_ux_tx_ch2_data_1[2], o_ux_tx_ch2_data_1[1], o_ux_tx_ch2_data_1[0] }),
		.o_tx_data({ o_tx_data_2[39], o_tx_data_2[38], o_tx_data_2[37], o_tx_data_2[36], o_tx_data_2[35], o_tx_data_2[34], o_tx_data_2[33], o_tx_data_2[32], o_tx_data_2[31], o_tx_data_2[30], o_tx_data_2[29], o_tx_data_2[28], o_tx_data_2[27], o_tx_data_2[26], o_tx_data_2[25], o_tx_data_2[24], o_tx_data_2[23], o_tx_data_2[22], o_tx_data_2[21], o_tx_data_2[20], o_tx_data_2[19], o_tx_data_2[18], o_tx_data_2[17], o_tx_data_2[16], o_tx_data_2[15], o_tx_data_2[14], o_tx_data_2[13], o_tx_data_2[12], o_tx_data_2[11], o_tx_data_2[10], o_tx_data_2[9], o_tx_data_2[8], o_tx_data_2[7], o_tx_data_2[6], o_tx_data_2[5], o_tx_data_2[4], o_tx_data_2[3], o_tx_data_2[2], o_tx_data_2[1], o_tx_data_2[0] })
	);

	tennm_ipfluxtop_uxtop_wrap #(
		.cdr_f_out_hz(x_std_ipfluxtop_uxtop_wrap_0__cdr_f_out_hz),
		.cdr_f_pfd_hz(x_std_ipfluxtop_uxtop_wrap_0__cdr_f_pfd_hz),
		.cdr_f_ref_hz(x_std_ipfluxtop_uxtop_wrap_0__cdr_f_ref_hz),
		.cdr_f_vco_hz(x_std_ipfluxtop_uxtop_wrap_0__cdr_f_vco_hz),
		.cdr_l_counter(x_std_ipfluxtop_uxtop_wrap_0__cdr_l_counter),
		.cdr_m_counter(x_std_ipfluxtop_uxtop_wrap_0__cdr_m_counter),
		.cdr_n_counter(x_std_ipfluxtop_uxtop_wrap_0__cdr_n_counter),
		.cdr_refclk_select(x_std_ipfluxtop_uxtop_wrap_0__cdr_refclk_select),
		.clk_debug_select_0_enable(x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_0_enable),
		.clk_debug_select_0_setting(x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_0_setting),
		.clk_debug_select_1_enable(x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_1_enable),
		.clk_debug_select_1_setting(x_std_ipfluxtop_uxtop_wrap_0__clk_debug_select_1_setting),
		.duplex_mode(x_std_ipfluxtop_uxtop_wrap_0__duplex_mode),
		.ick_tx_word_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__ick_tx_word_clk_hz),
		.lane_common_ref_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__lane_common_ref_clk_hz),
		.loopback_mode(x_std_ipfluxtop_uxtop_wrap_0__loopback_mode),
		.pcie_mode(x_std_ipfluxtop_uxtop_wrap_0__pcie_mode),
		.pcs_ref_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__pcs_ref_clk_hz),
		.rx_adaptation_mode(x_std_ipfluxtop_uxtop_wrap_0__rx_adaptation_mode),
		.rx_cdrdivout_en(x_std_ipfluxtop_uxtop_wrap_0__rx_cdrdivout_en),
		.rx_datarate_bps(x_std_ipfluxtop_uxtop_wrap_0__rx_datarate_bps),
		.rx_en(x_std_ipfluxtop_uxtop_wrap_0__rx_en),
		.rx_eq_dfe_tap_1(x_std_ipfluxtop_uxtop_wrap_0__rx_eq_dfe_tap_1),
		.rx_eq_hf_boost(x_std_ipfluxtop_uxtop_wrap_0__rx_eq_hf_boost),
		.rx_eq_vga_gain(x_std_ipfluxtop_uxtop_wrap_0__rx_eq_vga_gain),
		.rx_external_couple_type(x_std_ipfluxtop_uxtop_wrap_0__rx_external_couple_type),
		.rx_force_cdr_ltr(x_std_ipfluxtop_uxtop_wrap_0__rx_force_cdr_ltr),
		.rx_invert_pin(x_std_ipfluxtop_uxtop_wrap_0__rx_invert_pin),
		.rx_onchip_termination_setting(x_std_ipfluxtop_uxtop_wrap_0__rx_onchip_termination_setting),
		.rx_postdiv_clk_divider(x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_divider),
		.rx_postdiv_clk_en(x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_en),
		.rx_postdiv_clk_fractional_en(x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_fractional_en),
		.rx_postdiv_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__rx_postdiv_clk_hz),
		.rx_prbs_monitor_en(x_std_ipfluxtop_uxtop_wrap_0__rx_prbs_monitor_en),
		.rx_prbs_pattern(x_std_ipfluxtop_uxtop_wrap_0__rx_prbs_pattern),
		.rx_preloaded_hardware_configs(x_std_ipfluxtop_uxtop_wrap_0__rx_preloaded_hardware_configs),
		.rx_protocol_hint(x_std_ipfluxtop_uxtop_wrap_0__rx_protocol_hint),
		.rx_sim_mode(x_std_ipfluxtop_uxtop_wrap_0__rx_sim_mode),
		.rx_termination_mode(x_std_ipfluxtop_uxtop_wrap_0__rx_termination_mode),
		.rx_width(x_std_ipfluxtop_uxtop_wrap_0__rx_width),
		.rx_word_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__rx_word_clk_hz),
		.speed_grade(x_std_ipfluxtop_uxtop_wrap_0__speed_grade),
		.tx_bond_size(x_std_ipfluxtop_uxtop_wrap_0__tx_bond_size),
		.tx_bonding_category(x_std_ipfluxtop_uxtop_wrap_0__tx_bonding_category),
		.tx_datarate_bps(x_std_ipfluxtop_uxtop_wrap_0__tx_datarate_bps),
		.tx_en(x_std_ipfluxtop_uxtop_wrap_0__tx_en),
		.tx_eq_main_tap(x_std_ipfluxtop_uxtop_wrap_0__tx_eq_main_tap),
		.tx_eq_post_tap_1(x_std_ipfluxtop_uxtop_wrap_0__tx_eq_post_tap_1),
		.tx_eq_pre_tap_1(x_std_ipfluxtop_uxtop_wrap_0__tx_eq_pre_tap_1),
		.tx_eq_pre_tap_2(x_std_ipfluxtop_uxtop_wrap_0__tx_eq_pre_tap_2),
		.tx_invert_pin(x_std_ipfluxtop_uxtop_wrap_0__tx_invert_pin),
		.tx_master_pll_mode(x_std_ipfluxtop_uxtop_wrap_0__tx_master_pll_mode),
		.tx_pll_bw_sel(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_bw_sel),
		.tx_pll_f_out_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_out_hz),
		.tx_pll_f_pfd_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_pfd_hz),
		.tx_pll_f_ref_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_ref_hz),
		.tx_pll_f_vco_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_f_vco_hz),
		.tx_pll_fb_counter(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_fb_counter),
		.tx_pll_feed_forward_gain(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_feed_forward_gain),
		.tx_pll_k_counter(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_k_counter),
		.tx_pll_l_counter(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_l_counter),
		.tx_pll_m_counter(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_m_counter),
		.tx_pll_n_counter(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_n_counter),
		.tx_pll_postdiv_sel(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_postdiv_sel),
		.tx_pll_refclk_select(x_std_ipfluxtop_uxtop_wrap_0__tx_pll_refclk_select),
		.tx_postdiv_cdr_refclk_divider(x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_cdr_refclk_divider),
		.tx_postdiv_cdr_refclk_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_cdr_refclk_hz),
		.tx_postdiv_clk_divider(x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_divider),
		.tx_postdiv_clk_fractional_en(x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_fractional_en),
		.tx_postdiv_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_postdiv_clk_hz),
		.tx_prbs_gen_en(x_std_ipfluxtop_uxtop_wrap_0__tx_prbs_gen_en),
		.tx_prbs_pattern(x_std_ipfluxtop_uxtop_wrap_0__tx_prbs_pattern),
		.tx_preloaded_hardware_configs(x_std_ipfluxtop_uxtop_wrap_0__tx_preloaded_hardware_configs),
		.tx_protocol_hint(x_std_ipfluxtop_uxtop_wrap_0__tx_protocol_hint),
		.tx_sim_mode(x_std_ipfluxtop_uxtop_wrap_0__tx_sim_mode),
		.tx_spread_spectrum_en(x_std_ipfluxtop_uxtop_wrap_0__tx_spread_spectrum_en),
		.tx_synthdiv_out_divider(x_std_ipfluxtop_uxtop_wrap_0__tx_synthdiv_out_divider),
		.tx_synthdiv_out_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_synthdiv_out_hz),
		.tx_user_clk_only_mode(x_std_ipfluxtop_uxtop_wrap_0__tx_user_clk_only_mode),
		.tx_width(x_std_ipfluxtop_uxtop_wrap_0__tx_width),
		.tx_word_clk_hz(x_std_ipfluxtop_uxtop_wrap_0__tx_word_clk_hz),
		.usb_mode(x_std_ipfluxtop_uxtop_wrap_0__usb_mode)
	) x_std_ipfluxtop_uxtop_wrap_0 (
		.iflux_xia_rx_n_l0_ux(x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_n_l0_ux_1),
		.iflux_xia_rx_p_l0_ux(x_std_ipfluxtop_uxtop_wrap_0__iflux_xia_rx_p_l0_ux_1),
		.ioack_cdrdiv_left_ux_bidir_in(x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_in_1),
		.ioack_cdrdiv_left_ux_bidir_out(x_std_ipfluxtop_uxtop_wrap_0__ioack_cdrdiv_left_ux_bidir_out_1),
		.ioack_hsref_left_p_ux_bidir_in(x_std_ipfluxtop_uxtop_wrap_0__ioack_hsref_left_p_ux_bidir_in_1),
		.ioack_ref_left_p_ux_bidir_in({ x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[5], x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[4], x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[3], x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[2], x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[1], x_std_ipfluxtop_uxtop_wrap_0__ioack_ref_left_p_ux_bidir_in_0[0] }),
		.ioack_synthdiv1_left_ux_bidir_in(x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_in_1),
		.ioack_synthdiv1_left_ux_bidir_out(x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv1_left_ux_bidir_out_1),
		.ioack_synthdiv2_left_ux_bidir_in(x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_in_1),
		.ioack_synthdiv2_left_ux_bidir_out(x_std_ipfluxtop_uxtop_wrap_0__ioack_synthdiv2_left_ux_bidir_out_1),
		.oflux_xoa_tx_n_l0_ux(x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_n_l0_ux_1),
		.oflux_xoa_tx_p_l0_ux(x_std_ipfluxtop_uxtop_wrap_0__oflux_xoa_tx_p_l0_ux_1),
		.uxwrap_bus_in({ uxwrap_bus_in_lane2_0[767], uxwrap_bus_in_lane2_0[766], uxwrap_bus_in_lane2_0[765], uxwrap_bus_in_lane2_0[764], uxwrap_bus_in_lane2_0[763], uxwrap_bus_in_lane2_0[762], uxwrap_bus_in_lane2_0[761], uxwrap_bus_in_lane2_0[760], uxwrap_bus_in_lane2_0[759], uxwrap_bus_in_lane2_0[758], uxwrap_bus_in_lane2_0[757], uxwrap_bus_in_lane2_0[756], uxwrap_bus_in_lane2_0[755], uxwrap_bus_in_lane2_0[754], uxwrap_bus_in_lane2_0[753], uxwrap_bus_in_lane2_0[752], uxwrap_bus_in_lane2_0[751], uxwrap_bus_in_lane2_0[750], uxwrap_bus_in_lane2_0[749], uxwrap_bus_in_lane2_0[748], uxwrap_bus_in_lane2_0[747], uxwrap_bus_in_lane2_0[746], uxwrap_bus_in_lane2_0[745], uxwrap_bus_in_lane2_0[744], uxwrap_bus_in_lane2_0[743], uxwrap_bus_in_lane2_0[742], uxwrap_bus_in_lane2_0[741], uxwrap_bus_in_lane2_0[740], uxwrap_bus_in_lane2_0[739], uxwrap_bus_in_lane2_0[738], uxwrap_bus_in_lane2_0[737], uxwrap_bus_in_lane2_0[736], uxwrap_bus_in_lane2_0[735], uxwrap_bus_in_lane2_0[734], uxwrap_bus_in_lane2_0[733], uxwrap_bus_in_lane2_0[732], uxwrap_bus_in_lane2_0[731], uxwrap_bus_in_lane2_0[730], uxwrap_bus_in_lane2_0[729], uxwrap_bus_in_lane2_0[728], uxwrap_bus_in_lane2_0[727], uxwrap_bus_in_lane2_0[726], uxwrap_bus_in_lane2_0[725], uxwrap_bus_in_lane2_0[724], uxwrap_bus_in_lane2_0[723], uxwrap_bus_in_lane2_0[722], uxwrap_bus_in_lane2_0[721], uxwrap_bus_in_lane2_0[720], uxwrap_bus_in_lane2_0[719], uxwrap_bus_in_lane2_0[718], uxwrap_bus_in_lane2_0[717], uxwrap_bus_in_lane2_0[716], uxwrap_bus_in_lane2_0[715], uxwrap_bus_in_lane2_0[714], uxwrap_bus_in_lane2_0[713], uxwrap_bus_in_lane2_0[712], uxwrap_bus_in_lane2_0[711], uxwrap_bus_in_lane2_0[710], uxwrap_bus_in_lane2_0[709], uxwrap_bus_in_lane2_0[708], uxwrap_bus_in_lane2_0[707], uxwrap_bus_in_lane2_0[706], uxwrap_bus_in_lane2_0[705], uxwrap_bus_in_lane2_0[704], uxwrap_bus_in_lane2_0[703], uxwrap_bus_in_lane2_0[702], uxwrap_bus_in_lane2_0[701], uxwrap_bus_in_lane2_0[700], uxwrap_bus_in_lane2_0[699], uxwrap_bus_in_lane2_0[698], uxwrap_bus_in_lane2_0[697], uxwrap_bus_in_lane2_0[696], uxwrap_bus_in_lane2_0[695], uxwrap_bus_in_lane2_0[694], uxwrap_bus_in_lane2_0[693], uxwrap_bus_in_lane2_0[692], uxwrap_bus_in_lane2_0[691], uxwrap_bus_in_lane2_0[690], uxwrap_bus_in_lane2_0[689], uxwrap_bus_in_lane2_0[688], uxwrap_bus_in_lane2_0[687], uxwrap_bus_in_lane2_0[686], uxwrap_bus_in_lane2_0[685], uxwrap_bus_in_lane2_0[684], uxwrap_bus_in_lane2_0[683], uxwrap_bus_in_lane2_0[682], uxwrap_bus_in_lane2_0[681], uxwrap_bus_in_lane2_0[680], uxwrap_bus_in_lane2_0[679], uxwrap_bus_in_lane2_0[678], uxwrap_bus_in_lane2_0[677], uxwrap_bus_in_lane2_0[676], uxwrap_bus_in_lane2_0[675], uxwrap_bus_in_lane2_0[674], uxwrap_bus_in_lane2_0[673], uxwrap_bus_in_lane2_0[672], uxwrap_bus_in_lane2_0[671], uxwrap_bus_in_lane2_0[670], uxwrap_bus_in_lane2_0[669], uxwrap_bus_in_lane2_0[668], uxwrap_bus_in_lane2_0[667], uxwrap_bus_in_lane2_0[666], uxwrap_bus_in_lane2_0[665], uxwrap_bus_in_lane2_0[664], uxwrap_bus_in_lane2_0[663], uxwrap_bus_in_lane2_0[662], uxwrap_bus_in_lane2_0[661], uxwrap_bus_in_lane2_0[660], uxwrap_bus_in_lane2_0[659], uxwrap_bus_in_lane2_0[658], uxwrap_bus_in_lane2_0[657], uxwrap_bus_in_lane2_0[656], uxwrap_bus_in_lane2_0[655], uxwrap_bus_in_lane2_0[654], uxwrap_bus_in_lane2_0[653], uxwrap_bus_in_lane2_0[652], uxwrap_bus_in_lane2_0[651], uxwrap_bus_in_lane2_0[650], uxwrap_bus_in_lane2_0[649], uxwrap_bus_in_lane2_0[648], uxwrap_bus_in_lane2_0[647], uxwrap_bus_in_lane2_0[646], uxwrap_bus_in_lane2_0[645], uxwrap_bus_in_lane2_0[644], uxwrap_bus_in_lane2_0[643], uxwrap_bus_in_lane2_0[642], uxwrap_bus_in_lane2_0[641], uxwrap_bus_in_lane2_0[640], uxwrap_bus_in_lane2_0[639], uxwrap_bus_in_lane2_0[638], uxwrap_bus_in_lane2_0[637], uxwrap_bus_in_lane2_0[636], uxwrap_bus_in_lane2_0[635], uxwrap_bus_in_lane2_0[634], uxwrap_bus_in_lane2_0[633], uxwrap_bus_in_lane2_0[632], uxwrap_bus_in_lane2_0[631], uxwrap_bus_in_lane2_0[630], uxwrap_bus_in_lane2_0[629], uxwrap_bus_in_lane2_0[628], uxwrap_bus_in_lane2_0[627], uxwrap_bus_in_lane2_0[626], uxwrap_bus_in_lane2_0[625], uxwrap_bus_in_lane2_0[624], uxwrap_bus_in_lane2_0[623], uxwrap_bus_in_lane2_0[622], uxwrap_bus_in_lane2_0[621], uxwrap_bus_in_lane2_0[620], uxwrap_bus_in_lane2_0[619], uxwrap_bus_in_lane2_0[618], uxwrap_bus_in_lane2_0[617], uxwrap_bus_in_lane2_0[616], uxwrap_bus_in_lane2_0[615], uxwrap_bus_in_lane2_0[614], uxwrap_bus_in_lane2_0[613], uxwrap_bus_in_lane2_0[612], uxwrap_bus_in_lane2_0[611], uxwrap_bus_in_lane2_0[610], uxwrap_bus_in_lane2_0[609], uxwrap_bus_in_lane2_0[608], uxwrap_bus_in_lane2_0[607], uxwrap_bus_in_lane2_0[606], uxwrap_bus_in_lane2_0[605], uxwrap_bus_in_lane2_0[604], uxwrap_bus_in_lane2_0[603], uxwrap_bus_in_lane2_0[602], uxwrap_bus_in_lane2_0[601], uxwrap_bus_in_lane2_0[600], uxwrap_bus_in_lane2_0[599], uxwrap_bus_in_lane2_0[598], uxwrap_bus_in_lane2_0[597], uxwrap_bus_in_lane2_0[596], uxwrap_bus_in_lane2_0[595], uxwrap_bus_in_lane2_0[594], uxwrap_bus_in_lane2_0[593], uxwrap_bus_in_lane2_0[592], uxwrap_bus_in_lane2_0[591], uxwrap_bus_in_lane2_0[590], uxwrap_bus_in_lane2_0[589], uxwrap_bus_in_lane2_0[588], uxwrap_bus_in_lane2_0[587], uxwrap_bus_in_lane2_0[586], uxwrap_bus_in_lane2_0[585], uxwrap_bus_in_lane2_0[584], uxwrap_bus_in_lane2_0[583], uxwrap_bus_in_lane2_0[582], uxwrap_bus_in_lane2_0[581], uxwrap_bus_in_lane2_0[580], uxwrap_bus_in_lane2_0[579], uxwrap_bus_in_lane2_0[578], uxwrap_bus_in_lane2_0[577], uxwrap_bus_in_lane2_0[576], uxwrap_bus_in_lane2_0[575], uxwrap_bus_in_lane2_0[574], uxwrap_bus_in_lane2_0[573], uxwrap_bus_in_lane2_0[572], uxwrap_bus_in_lane2_0[571], uxwrap_bus_in_lane2_0[570], uxwrap_bus_in_lane2_0[569], uxwrap_bus_in_lane2_0[568], uxwrap_bus_in_lane2_0[567], uxwrap_bus_in_lane2_0[566], uxwrap_bus_in_lane2_0[565], uxwrap_bus_in_lane2_0[564], uxwrap_bus_in_lane2_0[563], uxwrap_bus_in_lane2_0[562], uxwrap_bus_in_lane2_0[561], uxwrap_bus_in_lane2_0[560], uxwrap_bus_in_lane2_0[559], uxwrap_bus_in_lane2_0[558], uxwrap_bus_in_lane2_0[557], uxwrap_bus_in_lane2_0[556], uxwrap_bus_in_lane2_0[555], uxwrap_bus_in_lane2_0[554], uxwrap_bus_in_lane2_0[553], uxwrap_bus_in_lane2_0[552], uxwrap_bus_in_lane2_0[551], uxwrap_bus_in_lane2_0[550], uxwrap_bus_in_lane2_0[549], uxwrap_bus_in_lane2_0[548], uxwrap_bus_in_lane2_0[547], uxwrap_bus_in_lane2_0[546], uxwrap_bus_in_lane2_0[545], uxwrap_bus_in_lane2_0[544], uxwrap_bus_in_lane2_0[543], uxwrap_bus_in_lane2_0[542], uxwrap_bus_in_lane2_0[541], uxwrap_bus_in_lane2_0[540], uxwrap_bus_in_lane2_0[539], uxwrap_bus_in_lane2_0[538], uxwrap_bus_in_lane2_0[537], uxwrap_bus_in_lane2_0[536], uxwrap_bus_in_lane2_0[535], uxwrap_bus_in_lane2_0[534], uxwrap_bus_in_lane2_0[533], uxwrap_bus_in_lane2_0[532], uxwrap_bus_in_lane2_0[531], uxwrap_bus_in_lane2_0[530], uxwrap_bus_in_lane2_0[529], uxwrap_bus_in_lane2_0[528], uxwrap_bus_in_lane2_0[527], uxwrap_bus_in_lane2_0[526], uxwrap_bus_in_lane2_0[525], uxwrap_bus_in_lane2_0[524], uxwrap_bus_in_lane2_0[523], uxwrap_bus_in_lane2_0[522], uxwrap_bus_in_lane2_0[521], uxwrap_bus_in_lane2_0[520], uxwrap_bus_in_lane2_0[519], uxwrap_bus_in_lane2_0[518], uxwrap_bus_in_lane2_0[517], uxwrap_bus_in_lane2_0[516], uxwrap_bus_in_lane2_0[515], uxwrap_bus_in_lane2_0[514], uxwrap_bus_in_lane2_0[513], uxwrap_bus_in_lane2_0[512], uxwrap_bus_in_lane2_0[511], uxwrap_bus_in_lane2_0[510], uxwrap_bus_in_lane2_0[509], uxwrap_bus_in_lane2_0[508], uxwrap_bus_in_lane2_0[507], uxwrap_bus_in_lane2_0[506], uxwrap_bus_in_lane2_0[505], uxwrap_bus_in_lane2_0[504], uxwrap_bus_in_lane2_0[503], uxwrap_bus_in_lane2_0[502], uxwrap_bus_in_lane2_0[501], uxwrap_bus_in_lane2_0[500], uxwrap_bus_in_lane2_0[499], uxwrap_bus_in_lane2_0[498], uxwrap_bus_in_lane2_0[497], uxwrap_bus_in_lane2_0[496], uxwrap_bus_in_lane2_0[495], uxwrap_bus_in_lane2_0[494], uxwrap_bus_in_lane2_0[493], uxwrap_bus_in_lane2_0[492], uxwrap_bus_in_lane2_0[491], uxwrap_bus_in_lane2_0[490], uxwrap_bus_in_lane2_0[489], uxwrap_bus_in_lane2_0[488], uxwrap_bus_in_lane2_0[487], uxwrap_bus_in_lane2_0[486], uxwrap_bus_in_lane2_0[485], uxwrap_bus_in_lane2_0[484], uxwrap_bus_in_lane2_0[483], uxwrap_bus_in_lane2_0[482], uxwrap_bus_in_lane2_0[481], uxwrap_bus_in_lane2_0[480], uxwrap_bus_in_lane2_0[479], uxwrap_bus_in_lane2_0[478], uxwrap_bus_in_lane2_0[477], uxwrap_bus_in_lane2_0[476], uxwrap_bus_in_lane2_0[475], uxwrap_bus_in_lane2_0[474], uxwrap_bus_in_lane2_0[473], uxwrap_bus_in_lane2_0[472], uxwrap_bus_in_lane2_0[471], uxwrap_bus_in_lane2_0[470], uxwrap_bus_in_lane2_0[469], uxwrap_bus_in_lane2_0[468], uxwrap_bus_in_lane2_0[467], uxwrap_bus_in_lane2_0[466], uxwrap_bus_in_lane2_0[465], uxwrap_bus_in_lane2_0[464], uxwrap_bus_in_lane2_0[463], uxwrap_bus_in_lane2_0[462], uxwrap_bus_in_lane2_0[461], uxwrap_bus_in_lane2_0[460], uxwrap_bus_in_lane2_0[459], uxwrap_bus_in_lane2_0[458], uxwrap_bus_in_lane2_0[457], uxwrap_bus_in_lane2_0[456], uxwrap_bus_in_lane2_0[455], uxwrap_bus_in_lane2_0[454], uxwrap_bus_in_lane2_0[453], uxwrap_bus_in_lane2_0[452], uxwrap_bus_in_lane2_0[451], uxwrap_bus_in_lane2_0[450], uxwrap_bus_in_lane2_0[449], uxwrap_bus_in_lane2_0[448], uxwrap_bus_in_lane2_0[447], uxwrap_bus_in_lane2_0[446], uxwrap_bus_in_lane2_0[445], uxwrap_bus_in_lane2_0[444], uxwrap_bus_in_lane2_0[443], uxwrap_bus_in_lane2_0[442], uxwrap_bus_in_lane2_0[441], uxwrap_bus_in_lane2_0[440], uxwrap_bus_in_lane2_0[439], uxwrap_bus_in_lane2_0[438], uxwrap_bus_in_lane2_0[437], uxwrap_bus_in_lane2_0[436], uxwrap_bus_in_lane2_0[435], uxwrap_bus_in_lane2_0[434], uxwrap_bus_in_lane2_0[433], uxwrap_bus_in_lane2_0[432], uxwrap_bus_in_lane2_0[431], uxwrap_bus_in_lane2_0[430], uxwrap_bus_in_lane2_0[429], uxwrap_bus_in_lane2_0[428], uxwrap_bus_in_lane2_0[427], uxwrap_bus_in_lane2_0[426], uxwrap_bus_in_lane2_0[425], uxwrap_bus_in_lane2_0[424], uxwrap_bus_in_lane2_0[423], uxwrap_bus_in_lane2_0[422], uxwrap_bus_in_lane2_0[421], uxwrap_bus_in_lane2_0[420], uxwrap_bus_in_lane2_0[419], uxwrap_bus_in_lane2_0[418], uxwrap_bus_in_lane2_0[417], uxwrap_bus_in_lane2_0[416], uxwrap_bus_in_lane2_0[415], uxwrap_bus_in_lane2_0[414], uxwrap_bus_in_lane2_0[413], uxwrap_bus_in_lane2_0[412], uxwrap_bus_in_lane2_0[411], uxwrap_bus_in_lane2_0[410], uxwrap_bus_in_lane2_0[409], uxwrap_bus_in_lane2_0[408], uxwrap_bus_in_lane2_0[407], uxwrap_bus_in_lane2_0[406], uxwrap_bus_in_lane2_0[405], uxwrap_bus_in_lane2_0[404], uxwrap_bus_in_lane2_0[403], uxwrap_bus_in_lane2_0[402], uxwrap_bus_in_lane2_0[401], uxwrap_bus_in_lane2_0[400], uxwrap_bus_in_lane2_0[399], uxwrap_bus_in_lane2_0[398], uxwrap_bus_in_lane2_0[397], uxwrap_bus_in_lane2_0[396], uxwrap_bus_in_lane2_0[395], uxwrap_bus_in_lane2_0[394], uxwrap_bus_in_lane2_0[393], uxwrap_bus_in_lane2_0[392], uxwrap_bus_in_lane2_0[391], uxwrap_bus_in_lane2_0[390], uxwrap_bus_in_lane2_0[389], uxwrap_bus_in_lane2_0[388], uxwrap_bus_in_lane2_0[387], uxwrap_bus_in_lane2_0[386], uxwrap_bus_in_lane2_0[385], uxwrap_bus_in_lane2_0[384], uxwrap_bus_in_lane2_0[383], uxwrap_bus_in_lane2_0[382], uxwrap_bus_in_lane2_0[381], uxwrap_bus_in_lane2_0[380], uxwrap_bus_in_lane2_0[379], uxwrap_bus_in_lane2_0[378], uxwrap_bus_in_lane2_0[377], uxwrap_bus_in_lane2_0[376], uxwrap_bus_in_lane2_0[375], uxwrap_bus_in_lane2_0[374], uxwrap_bus_in_lane2_0[373], uxwrap_bus_in_lane2_0[372], uxwrap_bus_in_lane2_0[371], uxwrap_bus_in_lane2_0[370], uxwrap_bus_in_lane2_0[369], uxwrap_bus_in_lane2_0[368], uxwrap_bus_in_lane2_0[367], uxwrap_bus_in_lane2_0[366], uxwrap_bus_in_lane2_0[365], uxwrap_bus_in_lane2_0[364], uxwrap_bus_in_lane2_0[363], uxwrap_bus_in_lane2_0[362], uxwrap_bus_in_lane2_0[361], uxwrap_bus_in_lane2_0[360], uxwrap_bus_in_lane2_0[359], uxwrap_bus_in_lane2_0[358], uxwrap_bus_in_lane2_0[357], uxwrap_bus_in_lane2_0[356], uxwrap_bus_in_lane2_0[355], uxwrap_bus_in_lane2_0[354], uxwrap_bus_in_lane2_0[353], uxwrap_bus_in_lane2_0[352], uxwrap_bus_in_lane2_0[351], uxwrap_bus_in_lane2_0[350], uxwrap_bus_in_lane2_0[349], uxwrap_bus_in_lane2_0[348], uxwrap_bus_in_lane2_0[347], uxwrap_bus_in_lane2_0[346], uxwrap_bus_in_lane2_0[345], uxwrap_bus_in_lane2_0[344], uxwrap_bus_in_lane2_0[343], uxwrap_bus_in_lane2_0[342], uxwrap_bus_in_lane2_0[341], uxwrap_bus_in_lane2_0[340], uxwrap_bus_in_lane2_0[339], uxwrap_bus_in_lane2_0[338], uxwrap_bus_in_lane2_0[337], uxwrap_bus_in_lane2_0[336], uxwrap_bus_in_lane2_0[335], uxwrap_bus_in_lane2_0[334], uxwrap_bus_in_lane2_0[333], uxwrap_bus_in_lane2_0[332], uxwrap_bus_in_lane2_0[331], uxwrap_bus_in_lane2_0[330], uxwrap_bus_in_lane2_0[329], uxwrap_bus_in_lane2_0[328], uxwrap_bus_in_lane2_0[327], uxwrap_bus_in_lane2_0[326], uxwrap_bus_in_lane2_0[325], uxwrap_bus_in_lane2_0[324], uxwrap_bus_in_lane2_0[323], uxwrap_bus_in_lane2_0[322], uxwrap_bus_in_lane2_0[321], uxwrap_bus_in_lane2_0[320], uxwrap_bus_in_lane2_0[319], uxwrap_bus_in_lane2_0[318], uxwrap_bus_in_lane2_0[317], uxwrap_bus_in_lane2_0[316], uxwrap_bus_in_lane2_0[315], uxwrap_bus_in_lane2_0[314], uxwrap_bus_in_lane2_0[313], uxwrap_bus_in_lane2_0[312], uxwrap_bus_in_lane2_0[311], uxwrap_bus_in_lane2_0[310], uxwrap_bus_in_lane2_0[309], uxwrap_bus_in_lane2_0[308], uxwrap_bus_in_lane2_0[307], uxwrap_bus_in_lane2_0[306], uxwrap_bus_in_lane2_0[305], uxwrap_bus_in_lane2_0[304], uxwrap_bus_in_lane2_0[303], uxwrap_bus_in_lane2_0[302], uxwrap_bus_in_lane2_0[301], uxwrap_bus_in_lane2_0[300], uxwrap_bus_in_lane2_0[299], uxwrap_bus_in_lane2_0[298], uxwrap_bus_in_lane2_0[297], uxwrap_bus_in_lane2_0[296], uxwrap_bus_in_lane2_0[295], uxwrap_bus_in_lane2_0[294], uxwrap_bus_in_lane2_0[293], uxwrap_bus_in_lane2_0[292], uxwrap_bus_in_lane2_0[291], uxwrap_bus_in_lane2_0[290], uxwrap_bus_in_lane2_0[289], uxwrap_bus_in_lane2_0[288], uxwrap_bus_in_lane2_0[287], uxwrap_bus_in_lane2_0[286], uxwrap_bus_in_lane2_0[285], uxwrap_bus_in_lane2_0[284], uxwrap_bus_in_lane2_0[283], uxwrap_bus_in_lane2_0[282], uxwrap_bus_in_lane2_0[281], uxwrap_bus_in_lane2_0[280], uxwrap_bus_in_lane2_0[279], uxwrap_bus_in_lane2_0[278], uxwrap_bus_in_lane2_0[277], uxwrap_bus_in_lane2_0[276], uxwrap_bus_in_lane2_0[275], uxwrap_bus_in_lane2_0[274], uxwrap_bus_in_lane2_0[273], uxwrap_bus_in_lane2_0[272], uxwrap_bus_in_lane2_0[271], uxwrap_bus_in_lane2_0[270], uxwrap_bus_in_lane2_0[269], uxwrap_bus_in_lane2_0[268], uxwrap_bus_in_lane2_0[267], uxwrap_bus_in_lane2_0[266], uxwrap_bus_in_lane2_0[265], uxwrap_bus_in_lane2_0[264], uxwrap_bus_in_lane2_0[263], uxwrap_bus_in_lane2_0[262], uxwrap_bus_in_lane2_0[261], uxwrap_bus_in_lane2_0[260], uxwrap_bus_in_lane2_0[259], uxwrap_bus_in_lane2_0[258], uxwrap_bus_in_lane2_0[257], uxwrap_bus_in_lane2_0[256], uxwrap_bus_in_lane2_0[255], uxwrap_bus_in_lane2_0[254], uxwrap_bus_in_lane2_0[253], uxwrap_bus_in_lane2_0[252], uxwrap_bus_in_lane2_0[251], uxwrap_bus_in_lane2_0[250], uxwrap_bus_in_lane2_0[249], uxwrap_bus_in_lane2_0[248], uxwrap_bus_in_lane2_0[247], uxwrap_bus_in_lane2_0[246], uxwrap_bus_in_lane2_0[245], uxwrap_bus_in_lane2_0[244], uxwrap_bus_in_lane2_0[243], uxwrap_bus_in_lane2_0[242], uxwrap_bus_in_lane2_0[241], uxwrap_bus_in_lane2_0[240], uxwrap_bus_in_lane2_0[239], uxwrap_bus_in_lane2_0[238], uxwrap_bus_in_lane2_0[237], uxwrap_bus_in_lane2_0[236], uxwrap_bus_in_lane2_0[235], uxwrap_bus_in_lane2_0[234], uxwrap_bus_in_lane2_0[233], uxwrap_bus_in_lane2_0[232], uxwrap_bus_in_lane2_0[231], uxwrap_bus_in_lane2_0[230], uxwrap_bus_in_lane2_0[229], uxwrap_bus_in_lane2_0[228], uxwrap_bus_in_lane2_0[227], uxwrap_bus_in_lane2_0[226], uxwrap_bus_in_lane2_0[225], uxwrap_bus_in_lane2_0[224], uxwrap_bus_in_lane2_0[223], uxwrap_bus_in_lane2_0[222], uxwrap_bus_in_lane2_0[221], uxwrap_bus_in_lane2_0[220], uxwrap_bus_in_lane2_0[219], uxwrap_bus_in_lane2_0[218], uxwrap_bus_in_lane2_0[217], uxwrap_bus_in_lane2_0[216], uxwrap_bus_in_lane2_0[215], uxwrap_bus_in_lane2_0[214], uxwrap_bus_in_lane2_0[213], uxwrap_bus_in_lane2_0[212], uxwrap_bus_in_lane2_0[211], uxwrap_bus_in_lane2_0[210], uxwrap_bus_in_lane2_0[209], uxwrap_bus_in_lane2_0[208], uxwrap_bus_in_lane2_0[207], uxwrap_bus_in_lane2_0[206], uxwrap_bus_in_lane2_0[205], uxwrap_bus_in_lane2_0[204], uxwrap_bus_in_lane2_0[203], uxwrap_bus_in_lane2_0[202], uxwrap_bus_in_lane2_0[201], uxwrap_bus_in_lane2_0[200], uxwrap_bus_in_lane2_0[199], uxwrap_bus_in_lane2_0[198], uxwrap_bus_in_lane2_0[197], uxwrap_bus_in_lane2_0[196], uxwrap_bus_in_lane2_0[195], uxwrap_bus_in_lane2_0[194], uxwrap_bus_in_lane2_0[193], uxwrap_bus_in_lane2_0[192], uxwrap_bus_in_lane2_0[191], uxwrap_bus_in_lane2_0[190], uxwrap_bus_in_lane2_0[189], uxwrap_bus_in_lane2_0[188], uxwrap_bus_in_lane2_0[187], uxwrap_bus_in_lane2_0[186], uxwrap_bus_in_lane2_0[185], uxwrap_bus_in_lane2_0[184], uxwrap_bus_in_lane2_0[183], uxwrap_bus_in_lane2_0[182], uxwrap_bus_in_lane2_0[181], uxwrap_bus_in_lane2_0[180], uxwrap_bus_in_lane2_0[179], uxwrap_bus_in_lane2_0[178], uxwrap_bus_in_lane2_0[177], uxwrap_bus_in_lane2_0[176], uxwrap_bus_in_lane2_0[175], uxwrap_bus_in_lane2_0[174], uxwrap_bus_in_lane2_0[173], uxwrap_bus_in_lane2_0[172], uxwrap_bus_in_lane2_0[171], uxwrap_bus_in_lane2_0[170], uxwrap_bus_in_lane2_0[169], uxwrap_bus_in_lane2_0[168], uxwrap_bus_in_lane2_0[167], uxwrap_bus_in_lane2_0[166], uxwrap_bus_in_lane2_0[165], uxwrap_bus_in_lane2_0[164], uxwrap_bus_in_lane2_0[163], uxwrap_bus_in_lane2_0[162], uxwrap_bus_in_lane2_0[161], uxwrap_bus_in_lane2_0[160], uxwrap_bus_in_lane2_0[159], uxwrap_bus_in_lane2_0[158], uxwrap_bus_in_lane2_0[157], uxwrap_bus_in_lane2_0[156], uxwrap_bus_in_lane2_0[155], uxwrap_bus_in_lane2_0[154], uxwrap_bus_in_lane2_0[153], uxwrap_bus_in_lane2_0[152], uxwrap_bus_in_lane2_0[151], uxwrap_bus_in_lane2_0[150], uxwrap_bus_in_lane2_0[149], uxwrap_bus_in_lane2_0[148], uxwrap_bus_in_lane2_0[147], uxwrap_bus_in_lane2_0[146], uxwrap_bus_in_lane2_0[145], uxwrap_bus_in_lane2_0[144], uxwrap_bus_in_lane2_0[143], uxwrap_bus_in_lane2_0[142], uxwrap_bus_in_lane2_0[141], uxwrap_bus_in_lane2_0[140], uxwrap_bus_in_lane2_0[139], uxwrap_bus_in_lane2_0[138], uxwrap_bus_in_lane2_0[137], uxwrap_bus_in_lane2_0[136], uxwrap_bus_in_lane2_0[135], uxwrap_bus_in_lane2_0[134], uxwrap_bus_in_lane2_0[133], uxwrap_bus_in_lane2_0[132], uxwrap_bus_in_lane2_0[131], uxwrap_bus_in_lane2_0[130], uxwrap_bus_in_lane2_0[129], uxwrap_bus_in_lane2_0[128], uxwrap_bus_in_lane2_0[127], uxwrap_bus_in_lane2_0[126], uxwrap_bus_in_lane2_0[125], uxwrap_bus_in_lane2_0[124], uxwrap_bus_in_lane2_0[123], uxwrap_bus_in_lane2_0[122], uxwrap_bus_in_lane2_0[121], uxwrap_bus_in_lane2_0[120], uxwrap_bus_in_lane2_0[119], uxwrap_bus_in_lane2_0[118], uxwrap_bus_in_lane2_0[117], uxwrap_bus_in_lane2_0[116], uxwrap_bus_in_lane2_0[115], uxwrap_bus_in_lane2_0[114], uxwrap_bus_in_lane2_0[113], uxwrap_bus_in_lane2_0[112], uxwrap_bus_in_lane2_0[111], uxwrap_bus_in_lane2_0[110], uxwrap_bus_in_lane2_0[109], uxwrap_bus_in_lane2_0[108], uxwrap_bus_in_lane2_0[107], uxwrap_bus_in_lane2_0[106], uxwrap_bus_in_lane2_0[105], uxwrap_bus_in_lane2_0[104], uxwrap_bus_in_lane2_0[103], uxwrap_bus_in_lane2_0[102], uxwrap_bus_in_lane2_0[101], uxwrap_bus_in_lane2_0[100], uxwrap_bus_in_lane2_0[99], uxwrap_bus_in_lane2_0[98], uxwrap_bus_in_lane2_0[97], uxwrap_bus_in_lane2_0[96], uxwrap_bus_in_lane2_0[95], uxwrap_bus_in_lane2_0[94], uxwrap_bus_in_lane2_0[93], uxwrap_bus_in_lane2_0[92], uxwrap_bus_in_lane2_0[91], uxwrap_bus_in_lane2_0[90], uxwrap_bus_in_lane2_0[89], uxwrap_bus_in_lane2_0[88], uxwrap_bus_in_lane2_0[87], uxwrap_bus_in_lane2_0[86], uxwrap_bus_in_lane2_0[85], uxwrap_bus_in_lane2_0[84], uxwrap_bus_in_lane2_0[83], uxwrap_bus_in_lane2_0[82], uxwrap_bus_in_lane2_0[81], uxwrap_bus_in_lane2_0[80], uxwrap_bus_in_lane2_0[79], uxwrap_bus_in_lane2_0[78], uxwrap_bus_in_lane2_0[77], uxwrap_bus_in_lane2_0[76], uxwrap_bus_in_lane2_0[75], uxwrap_bus_in_lane2_0[74], uxwrap_bus_in_lane2_0[73], uxwrap_bus_in_lane2_0[72], uxwrap_bus_in_lane2_0[71], uxwrap_bus_in_lane2_0[70], uxwrap_bus_in_lane2_0[69], uxwrap_bus_in_lane2_0[68], uxwrap_bus_in_lane2_0[67], uxwrap_bus_in_lane2_0[66], uxwrap_bus_in_lane2_0[65], uxwrap_bus_in_lane2_0[64], uxwrap_bus_in_lane2_0[63], uxwrap_bus_in_lane2_0[62], uxwrap_bus_in_lane2_0[61], uxwrap_bus_in_lane2_0[60], uxwrap_bus_in_lane2_0[59], uxwrap_bus_in_lane2_0[58], uxwrap_bus_in_lane2_0[57], uxwrap_bus_in_lane2_0[56], uxwrap_bus_in_lane2_0[55], uxwrap_bus_in_lane2_0[54], uxwrap_bus_in_lane2_0[53], uxwrap_bus_in_lane2_0[52], uxwrap_bus_in_lane2_0[51], uxwrap_bus_in_lane2_0[50], uxwrap_bus_in_lane2_0[49], uxwrap_bus_in_lane2_0[48], uxwrap_bus_in_lane2_0[47], uxwrap_bus_in_lane2_0[46], uxwrap_bus_in_lane2_0[45], uxwrap_bus_in_lane2_0[44], uxwrap_bus_in_lane2_0[43], uxwrap_bus_in_lane2_0[42], uxwrap_bus_in_lane2_0[41], uxwrap_bus_in_lane2_0[40], uxwrap_bus_in_lane2_0[39], uxwrap_bus_in_lane2_0[38], uxwrap_bus_in_lane2_0[37], uxwrap_bus_in_lane2_0[36], uxwrap_bus_in_lane2_0[35], uxwrap_bus_in_lane2_0[34], uxwrap_bus_in_lane2_0[33], uxwrap_bus_in_lane2_0[32], uxwrap_bus_in_lane2_0[31], uxwrap_bus_in_lane2_0[30], uxwrap_bus_in_lane2_0[29], uxwrap_bus_in_lane2_0[28], uxwrap_bus_in_lane2_0[27], uxwrap_bus_in_lane2_0[26], uxwrap_bus_in_lane2_0[25], uxwrap_bus_in_lane2_0[24], uxwrap_bus_in_lane2_0[23], uxwrap_bus_in_lane2_0[22], uxwrap_bus_in_lane2_0[21], uxwrap_bus_in_lane2_0[20], uxwrap_bus_in_lane2_0[19], uxwrap_bus_in_lane2_0[18], uxwrap_bus_in_lane2_0[17], uxwrap_bus_in_lane2_0[16], uxwrap_bus_in_lane2_0[15], uxwrap_bus_in_lane2_0[14], uxwrap_bus_in_lane2_0[13], uxwrap_bus_in_lane2_0[12], uxwrap_bus_in_lane2_0[11], uxwrap_bus_in_lane2_0[10], uxwrap_bus_in_lane2_0[9], uxwrap_bus_in_lane2_0[8], uxwrap_bus_in_lane2_0[7], uxwrap_bus_in_lane2_0[6], uxwrap_bus_in_lane2_0[5], uxwrap_bus_in_lane2_0[4], uxwrap_bus_in_lane2_0[3], uxwrap_bus_in_lane2_0[2], uxwrap_bus_in_lane2_0[1], uxwrap_bus_in_lane2_0[0] }),
		.uxwrap_bus_out({ uxwrap_bus_out_lane2_1[703], uxwrap_bus_out_lane2_1[702], uxwrap_bus_out_lane2_1[701], uxwrap_bus_out_lane2_1[700], uxwrap_bus_out_lane2_1[699], uxwrap_bus_out_lane2_1[698], uxwrap_bus_out_lane2_1[697], uxwrap_bus_out_lane2_1[696], uxwrap_bus_out_lane2_1[695], uxwrap_bus_out_lane2_1[694], uxwrap_bus_out_lane2_1[693], uxwrap_bus_out_lane2_1[692], uxwrap_bus_out_lane2_1[691], uxwrap_bus_out_lane2_1[690], uxwrap_bus_out_lane2_1[689], uxwrap_bus_out_lane2_1[688], uxwrap_bus_out_lane2_1[687], uxwrap_bus_out_lane2_1[686], uxwrap_bus_out_lane2_1[685], uxwrap_bus_out_lane2_1[684], uxwrap_bus_out_lane2_1[683], uxwrap_bus_out_lane2_1[682], uxwrap_bus_out_lane2_1[681], uxwrap_bus_out_lane2_1[680], uxwrap_bus_out_lane2_1[679], uxwrap_bus_out_lane2_1[678], uxwrap_bus_out_lane2_1[677], uxwrap_bus_out_lane2_1[676], uxwrap_bus_out_lane2_1[675], uxwrap_bus_out_lane2_1[674], uxwrap_bus_out_lane2_1[673], uxwrap_bus_out_lane2_1[672], uxwrap_bus_out_lane2_1[671], uxwrap_bus_out_lane2_1[670], uxwrap_bus_out_lane2_1[669], uxwrap_bus_out_lane2_1[668], uxwrap_bus_out_lane2_1[667], uxwrap_bus_out_lane2_1[666], uxwrap_bus_out_lane2_1[665], uxwrap_bus_out_lane2_1[664], uxwrap_bus_out_lane2_1[663], uxwrap_bus_out_lane2_1[662], uxwrap_bus_out_lane2_1[661], uxwrap_bus_out_lane2_1[660], uxwrap_bus_out_lane2_1[659], uxwrap_bus_out_lane2_1[658], uxwrap_bus_out_lane2_1[657], uxwrap_bus_out_lane2_1[656], uxwrap_bus_out_lane2_1[655], uxwrap_bus_out_lane2_1[654], uxwrap_bus_out_lane2_1[653], uxwrap_bus_out_lane2_1[652], uxwrap_bus_out_lane2_1[651], uxwrap_bus_out_lane2_1[650], uxwrap_bus_out_lane2_1[649], uxwrap_bus_out_lane2_1[648], uxwrap_bus_out_lane2_1[647], uxwrap_bus_out_lane2_1[646], uxwrap_bus_out_lane2_1[645], uxwrap_bus_out_lane2_1[644], uxwrap_bus_out_lane2_1[643], uxwrap_bus_out_lane2_1[642], uxwrap_bus_out_lane2_1[641], uxwrap_bus_out_lane2_1[640], uxwrap_bus_out_lane2_1[639], uxwrap_bus_out_lane2_1[638], uxwrap_bus_out_lane2_1[637], uxwrap_bus_out_lane2_1[636], uxwrap_bus_out_lane2_1[635], uxwrap_bus_out_lane2_1[634], uxwrap_bus_out_lane2_1[633], uxwrap_bus_out_lane2_1[632], uxwrap_bus_out_lane2_1[631], uxwrap_bus_out_lane2_1[630], uxwrap_bus_out_lane2_1[629], uxwrap_bus_out_lane2_1[628], uxwrap_bus_out_lane2_1[627], uxwrap_bus_out_lane2_1[626], uxwrap_bus_out_lane2_1[625], uxwrap_bus_out_lane2_1[624], uxwrap_bus_out_lane2_1[623], uxwrap_bus_out_lane2_1[622], uxwrap_bus_out_lane2_1[621], uxwrap_bus_out_lane2_1[620], uxwrap_bus_out_lane2_1[619], uxwrap_bus_out_lane2_1[618], uxwrap_bus_out_lane2_1[617], uxwrap_bus_out_lane2_1[616], uxwrap_bus_out_lane2_1[615], uxwrap_bus_out_lane2_1[614], uxwrap_bus_out_lane2_1[613], uxwrap_bus_out_lane2_1[612], uxwrap_bus_out_lane2_1[611], uxwrap_bus_out_lane2_1[610], uxwrap_bus_out_lane2_1[609], uxwrap_bus_out_lane2_1[608], uxwrap_bus_out_lane2_1[607], uxwrap_bus_out_lane2_1[606], uxwrap_bus_out_lane2_1[605], uxwrap_bus_out_lane2_1[604], uxwrap_bus_out_lane2_1[603], uxwrap_bus_out_lane2_1[602], uxwrap_bus_out_lane2_1[601], uxwrap_bus_out_lane2_1[600], uxwrap_bus_out_lane2_1[599], uxwrap_bus_out_lane2_1[598], uxwrap_bus_out_lane2_1[597], uxwrap_bus_out_lane2_1[596], uxwrap_bus_out_lane2_1[595], uxwrap_bus_out_lane2_1[594], uxwrap_bus_out_lane2_1[593], uxwrap_bus_out_lane2_1[592], uxwrap_bus_out_lane2_1[591], uxwrap_bus_out_lane2_1[590], uxwrap_bus_out_lane2_1[589], uxwrap_bus_out_lane2_1[588], uxwrap_bus_out_lane2_1[587], uxwrap_bus_out_lane2_1[586], uxwrap_bus_out_lane2_1[585], uxwrap_bus_out_lane2_1[584], uxwrap_bus_out_lane2_1[583], uxwrap_bus_out_lane2_1[582], uxwrap_bus_out_lane2_1[581], uxwrap_bus_out_lane2_1[580], uxwrap_bus_out_lane2_1[579], uxwrap_bus_out_lane2_1[578], uxwrap_bus_out_lane2_1[577], uxwrap_bus_out_lane2_1[576], uxwrap_bus_out_lane2_1[575], uxwrap_bus_out_lane2_1[574], uxwrap_bus_out_lane2_1[573], uxwrap_bus_out_lane2_1[572], uxwrap_bus_out_lane2_1[571], uxwrap_bus_out_lane2_1[570], uxwrap_bus_out_lane2_1[569], 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uxwrap_bus_out_lane2_1[126], uxwrap_bus_out_lane2_1[125], uxwrap_bus_out_lane2_1[124], uxwrap_bus_out_lane2_1[123], uxwrap_bus_out_lane2_1[122], uxwrap_bus_out_lane2_1[121], uxwrap_bus_out_lane2_1[120], uxwrap_bus_out_lane2_1[119], uxwrap_bus_out_lane2_1[118], uxwrap_bus_out_lane2_1[117], uxwrap_bus_out_lane2_1[116], uxwrap_bus_out_lane2_1[115], uxwrap_bus_out_lane2_1[114], uxwrap_bus_out_lane2_1[113], uxwrap_bus_out_lane2_1[112], uxwrap_bus_out_lane2_1[111], uxwrap_bus_out_lane2_1[110], uxwrap_bus_out_lane2_1[109], uxwrap_bus_out_lane2_1[108], uxwrap_bus_out_lane2_1[107], uxwrap_bus_out_lane2_1[106], uxwrap_bus_out_lane2_1[105], uxwrap_bus_out_lane2_1[104], uxwrap_bus_out_lane2_1[103], uxwrap_bus_out_lane2_1[102], uxwrap_bus_out_lane2_1[101], uxwrap_bus_out_lane2_1[100], uxwrap_bus_out_lane2_1[99], uxwrap_bus_out_lane2_1[98], uxwrap_bus_out_lane2_1[97], uxwrap_bus_out_lane2_1[96], uxwrap_bus_out_lane2_1[95], uxwrap_bus_out_lane2_1[94], uxwrap_bus_out_lane2_1[93], uxwrap_bus_out_lane2_1[92], uxwrap_bus_out_lane2_1[91], uxwrap_bus_out_lane2_1[90], uxwrap_bus_out_lane2_1[89], uxwrap_bus_out_lane2_1[88], uxwrap_bus_out_lane2_1[87], uxwrap_bus_out_lane2_1[86], uxwrap_bus_out_lane2_1[85], uxwrap_bus_out_lane2_1[84], uxwrap_bus_out_lane2_1[83], uxwrap_bus_out_lane2_1[82], uxwrap_bus_out_lane2_1[81], uxwrap_bus_out_lane2_1[80], uxwrap_bus_out_lane2_1[79], uxwrap_bus_out_lane2_1[78], uxwrap_bus_out_lane2_1[77], uxwrap_bus_out_lane2_1[76], uxwrap_bus_out_lane2_1[75], uxwrap_bus_out_lane2_1[74], uxwrap_bus_out_lane2_1[73], uxwrap_bus_out_lane2_1[72], uxwrap_bus_out_lane2_1[71], uxwrap_bus_out_lane2_1[70], uxwrap_bus_out_lane2_1[69], uxwrap_bus_out_lane2_1[68], uxwrap_bus_out_lane2_1[67], uxwrap_bus_out_lane2_1[66], uxwrap_bus_out_lane2_1[65], uxwrap_bus_out_lane2_1[64], uxwrap_bus_out_lane2_1[63], uxwrap_bus_out_lane2_1[62], uxwrap_bus_out_lane2_1[61], uxwrap_bus_out_lane2_1[60], uxwrap_bus_out_lane2_1[59], uxwrap_bus_out_lane2_1[58], uxwrap_bus_out_lane2_1[57], uxwrap_bus_out_lane2_1[56], uxwrap_bus_out_lane2_1[55], uxwrap_bus_out_lane2_1[54], uxwrap_bus_out_lane2_1[53], uxwrap_bus_out_lane2_1[52], uxwrap_bus_out_lane2_1[51], uxwrap_bus_out_lane2_1[50], uxwrap_bus_out_lane2_1[49], uxwrap_bus_out_lane2_1[48], uxwrap_bus_out_lane2_1[47], uxwrap_bus_out_lane2_1[46], uxwrap_bus_out_lane2_1[45], uxwrap_bus_out_lane2_1[44], uxwrap_bus_out_lane2_1[43], uxwrap_bus_out_lane2_1[42], uxwrap_bus_out_lane2_1[41], uxwrap_bus_out_lane2_1[40], uxwrap_bus_out_lane2_1[39], uxwrap_bus_out_lane2_1[38], uxwrap_bus_out_lane2_1[37], uxwrap_bus_out_lane2_1[36], uxwrap_bus_out_lane2_1[35], uxwrap_bus_out_lane2_1[34], uxwrap_bus_out_lane2_1[33], uxwrap_bus_out_lane2_1[32], uxwrap_bus_out_lane2_1[31], uxwrap_bus_out_lane2_1[30], uxwrap_bus_out_lane2_1[29], uxwrap_bus_out_lane2_1[28], uxwrap_bus_out_lane2_1[27], uxwrap_bus_out_lane2_1[26], uxwrap_bus_out_lane2_1[25], uxwrap_bus_out_lane2_1[24], uxwrap_bus_out_lane2_1[23], uxwrap_bus_out_lane2_1[22], uxwrap_bus_out_lane2_1[21], uxwrap_bus_out_lane2_1[20], uxwrap_bus_out_lane2_1[19], uxwrap_bus_out_lane2_1[18], uxwrap_bus_out_lane2_1[17], uxwrap_bus_out_lane2_1[16], uxwrap_bus_out_lane2_1[15], uxwrap_bus_out_lane2_1[14], uxwrap_bus_out_lane2_1[13], uxwrap_bus_out_lane2_1[12], uxwrap_bus_out_lane2_1[11], uxwrap_bus_out_lane2_1[10], uxwrap_bus_out_lane2_1[9], uxwrap_bus_out_lane2_1[8], uxwrap_bus_out_lane2_1[7], uxwrap_bus_out_lane2_1[6], uxwrap_bus_out_lane2_1[5], uxwrap_bus_out_lane2_1[4], uxwrap_bus_out_lane2_1[3], uxwrap_bus_out_lane2_1[2], uxwrap_bus_out_lane2_1[1], uxwrap_bus_out_lane2_1[0] }),
		.quartus_connection_to_serdes(o_quartus_connection_to_serdes_lane2_0)
	);

endmodule
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mr8jg6yVyp+1vCTSmm9okNGk/MFlI0RPgpclK5sJLh1jVstZniZ9YOfmN88MxbRZ2R9n6JUN5qUH1ePxKsetzz1WYna7MjmI3bbnOOrj9bgeBmNZMK5blGJcG/5l8YpGARVzlg+qL5wBUfY239yiLMLlxcFQsSMeUV3CxQOjMGuwK0UNiTu9YQpoIvBUadaVlUJYD0/eo11RyVMEsbtlFdUm+sT9khX6udL1+1bFfkTursm/Jjayfv6x3vM7z1h72Ws1Ib0/7VaKyxiTDwBly0xaV0OiUwJw6UEBVH5gFofjxpui2K+0Bu6eJxOmZqh4mXe3vJup9wd4Od9RbRcuLbdAxS5P7nQ91bXFp0OE6taKgnUVj+PDKplbSZDDWMAQA8lipDsIYlJptU68tKH1nXH6K6f2DUjA6y5O/QerI63k5tXcN50GuQtq9xu7E4p0PAKUxgxLRFN5JWylf5KwaYD2wfM4RgtZzSUBv9+a3UgRsq1XNUVgym1xZ55tTSMmyoN+g0zmSIupxoU/QyK2grC6j5avWYdnEDRPG2x/Di0bSOglNm+YI3tfFtQ5fznNkUTuIYY6lTWJjLvWrybyo/zoTxQBAKYc7vgY1jUWrUAm4qxSChPLQ53jnF1dFtsthOErCgougzLtmouIqx73J/PVlZMMbJyaYkS9GhRQuRFWCtQrFk4MNhcz5TpyyTLYL8QIOr49FSjHYOwYun0HfxdP2E4I3QqPXljxahDrkmPuf4VU6ghuxVsZ8YJXPEWN+IEyDKphTb/Wmq7fifWFWQv22IU4zb+QaH3JZORQ4C6tlm98UH/h3alY6ySzvuBdf9sF+CUPxvDp12hEpk1Qc6s0gSwqc8LHGugX8mjRBMj6DNDV6yOycI/jZy5Ian9Cy0NaIgyOafk0r6KvOq/gBc+QHeDpbbCfboSbM7kIjIDCLtVFxOYGY7myA3aEXnlNHUZPhnE+rhQB+aNXErcYF07cYNeoDfpbKUOQsuNG2WPAYphVr9A90Fnf3aHKFKbZ"
`endif