module Pll_Audio (
  input wire clk,        
  output reg out         
   
);

  reg [25:0] counter;     

  always @(posedge clk) begin
    if (counter == 25'd0) begin
      out <= ~out;         
    end

    
    if (counter == 25'd1920000) begin
      counter <= 25'd0;
    end else begin
      counter <= counter + 1;  
    end
  end


endmodule