// agilex_hps_intel_agilex_5_soc_300_7k7syei.v

// This file was auto-generated from intel_soc_sundancemesa_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module agilex_hps_intel_agilex_5_soc_300_7k7syei (
		output wire         h2f_reset_reset,                        //                h2f_reset.reset,         Active high reset from the HPS Reset Manager.
		input  wire         hps2fpga_axi_clock_clk,                 //       hps2fpga_axi_clock.clk,           Clock from a single source in the FPGA.
		input  wire         hps2fpga_axi_reset_reset,               //       hps2fpga_axi_reset.reset,         Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   hps2fpga_awid,                          //                 hps2fpga.awid,          Identification tag for a write transaction.
		output wire [37:0]  hps2fpga_awaddr,                        //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [7:0]   hps2fpga_awlen,                         //                         .awlen,         The exact number of data transfers in a write transaction.
		output wire [2:0]   hps2fpga_awsize,                        //                         .awsize,        The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   hps2fpga_awburst,                       //                         .awburst,       Indicates how address changes between each transfer in a write transaction.
		output wire         hps2fpga_awlock,                        //                         .awlock,        Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   hps2fpga_awcache,                       //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_awprot,                        //                         .awprot,        Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         hps2fpga_awvalid,                       //                         .awvalid,       Indicates that the write address channel signals are valid.
		input  wire         hps2fpga_awready,                       //                         .awready,       Indicates that a transfer on the write address channel can be accepted.
		output wire [127:0] hps2fpga_wdata,                         //                         .wdata,         Write data.
		output wire [15:0]  hps2fpga_wstrb,                         //                         .wstrb,         Write strobes, indicate which byte lanes hold valid data.
		output wire         hps2fpga_wlast,                         //                         .wlast,         User-defined extension for the write data channel.
		output wire         hps2fpga_wvalid,                        //                         .wvalid,        Indicates that the write data channel signals are valid.
		input  wire         hps2fpga_wready,                        //                         .wready,        Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   hps2fpga_bid,                           //                         .bid,           Transaction identifier for the write response.
		input  wire [1:0]   hps2fpga_bresp,                         //                         .bresp,         Write response, indicates the status of a write transaction.
		input  wire         hps2fpga_bvalid,                        //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire         hps2fpga_bready,                        //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   hps2fpga_arid,                          //                         .arid,          Transaction identifier for the read transaction.
		output wire [37:0]  hps2fpga_araddr,                        //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [7:0]   hps2fpga_arlen,                         //                         .arlen,         The exact number of data transfers in a read transaction.
		output wire [2:0]   hps2fpga_arsize,                        //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   hps2fpga_arburst,                       //                         .arburst,       Indicates how address changes between each transfer in a read transaction.
		output wire         hps2fpga_arlock,                        //                         .arlock,        Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   hps2fpga_arcache,                       //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   hps2fpga_arprot,                        //                         .arprot,        Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         hps2fpga_arvalid,                       //                         .arvalid,       Indicates that the read address channel signals are valid.
		input  wire         hps2fpga_arready,                       //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   hps2fpga_rid,                           //                         .rid,           Identification tag for read data and response.
		input  wire [127:0] hps2fpga_rdata,                         //                         .rdata,         Read data.
		input  wire [1:0]   hps2fpga_rresp,                         //                         .rresp,         Read response, indicates the status of a read transfer.
		input  wire         hps2fpga_rlast,                         //                         .rlast,         Indicates whether this is the last data transfer in a read transaction.
		input  wire         hps2fpga_rvalid,                        //                         .rvalid,        Indicates that the read data channel signals are valid.
		output wire         hps2fpga_rready,                        //                         .rready,        Indicates that a transfer on the read data channel can be accepted.
		input  wire         lwhps2fpga_axi_clock_clk,               //     lwhps2fpga_axi_clock.clk,           clock from a single source in the FPGA.
		input  wire         lwhps2fpga_axi_reset_reset,             //     lwhps2fpga_axi_reset.reset,         Async reset to the Bridge logic. This signal is active-HIGH.
		output wire [3:0]   lwhps2fpga_awid,                        //               lwhps2fpga.awid,          Identification tag for a write transaction.
		output wire [28:0]  lwhps2fpga_awaddr,                      //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [7:0]   lwhps2fpga_awlen,                       //                         .awlen,         The exact number of data transfers in a write transaction.
		output wire [2:0]   lwhps2fpga_awsize,                      //                         .awsize,        The number of bytes in each data transfer in a write transaction.
		output wire [1:0]   lwhps2fpga_awburst,                     //                         .awburst,       Indicates how address changes between each transfer in a write transaction.
		output wire         lwhps2fpga_awlock,                      //                         .awlock,        Provides information about the atomic characteristics of a write transaction.
		output wire [3:0]   lwhps2fpga_awcache,                     //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_awprot,                      //                         .awprot,        Protection attributes of a write transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_awvalid,                     //                         .awvalid,       Indicates that the write address channel signals are valid.
		input  wire         lwhps2fpga_awready,                     //                         .awready,       Indicates that a transfer on the write address channel can be accepted.
		output wire [31:0]  lwhps2fpga_wdata,                       //                         .wdata,         Write data.
		output wire [3:0]   lwhps2fpga_wstrb,                       //                         .wstrb,         Write strobes, indicate which byte lanes hold valid data.
		output wire         lwhps2fpga_wlast,                       //                         .wlast,         User-defined extension for the write data channel.
		output wire         lwhps2fpga_wvalid,                      //                         .wvalid,        Indicates that the write data channel signals are valid.
		input  wire         lwhps2fpga_wready,                      //                         .wready,        Indicates that a transfer on the write data channel can be accepted.
		input  wire [3:0]   lwhps2fpga_bid,                         //                         .bid,           Transaction identifier for the write response.
		input  wire [1:0]   lwhps2fpga_bresp,                       //                         .bresp,         Write response, indicates the status of a write transaction.
		input  wire         lwhps2fpga_bvalid,                      //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire         lwhps2fpga_bready,                      //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [3:0]   lwhps2fpga_arid,                        //                         .arid,          Transaction identifier for the read transaction.
		output wire [28:0]  lwhps2fpga_araddr,                      //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [7:0]   lwhps2fpga_arlen,                       //                         .arlen,         The exact number of data transfers in a read transaction.
		output wire [2:0]   lwhps2fpga_arsize,                      //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [1:0]   lwhps2fpga_arburst,                     //                         .arburst,       Indicates how address changes between each transfer in a read transaction.
		output wire         lwhps2fpga_arlock,                      //                         .arlock,        Provides information about the atomic characteristics of a read transaction.
		output wire [3:0]   lwhps2fpga_arcache,                     //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		output wire [2:0]   lwhps2fpga_arprot,                      //                         .arprot,        Protection attributes of a read transaction: privilege, security level, and access type.
		output wire         lwhps2fpga_arvalid,                     //                         .arvalid,       Indicates that the read address channel signals are valid.
		input  wire         lwhps2fpga_arready,                     //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [3:0]   lwhps2fpga_rid,                         //                         .rid,           Identification tag for read data and response.
		input  wire [31:0]  lwhps2fpga_rdata,                       //                         .rdata,         Read data.
		input  wire [1:0]   lwhps2fpga_rresp,                       //                         .rresp,         Read response, indicates the status of a read transfer.
		input  wire         lwhps2fpga_rlast,                       //                         .rlast,         Indicates whether this is the last data transfer in a read transaction.
		input  wire         lwhps2fpga_rvalid,                      //                         .rvalid,        Indicates that the read data channel signals are valid.
		output wire         lwhps2fpga_rready,                      //                         .rready,        Indicates that a transfer on the read data channel can be accepted.
		output wire         emac2_app_rst_reset_n,                  //            emac2_app_rst.reset_n,       EMAC2 application clock reset output.
		output wire         h2f_warm_reset_handshake_reset_req,     // h2f_warm_reset_handshake.reset_req,     HPS warm reset request. Identical to watchdog reset except this is asserted by SDM.
		input  wire         h2f_warm_reset_handshake_reset_ack,     //                         .reset_ack,     HPS warm reset acknowledge response to SDM. Should be asserted when all HPS soft logic is successfully in reset.
		input  wire         hps_io_hps_osc_clk,                     //                   hps_io.hps_osc_clk,   HPS input clock pin for EOSC reference clock.
		inout  wire         hps_io_sdmmc_data0,                     //                         .sdmmc_data0,   SDMMC data[0].
		inout  wire         hps_io_sdmmc_data1,                     //                         .sdmmc_data1,   SDMMC data[1].
		output wire         hps_io_sdmmc_cclk,                      //                         .sdmmc_cclk,    SDMMC output clock.
		inout  wire         hps_io_sdmmc_data2,                     //                         .sdmmc_data2,   SDMMC data[2].
		inout  wire         hps_io_sdmmc_data3,                     //                         .sdmmc_data3,   SDMMC data[3].
		inout  wire         hps_io_sdmmc_cmd,                       //                         .sdmmc_cmd,     SDMMC command.
		input  wire         hps_io_usb1_clk,                        //                         .usb1_clk,      ULPI PHY clock input.
		output wire         hps_io_usb1_stp,                        //                         .usb1_stp,      ULPI stop output control.
		input  wire         hps_io_usb1_dir,                        //                         .usb1_dir,      Data bus control.
		inout  wire         hps_io_usb1_data0,                      //                         .usb1_data0,    USB data[0].
		inout  wire         hps_io_usb1_data1,                      //                         .usb1_data1,    USB data[1].
		input  wire         hps_io_usb1_nxt,                        //                         .usb1_nxt,      ULPI next data control.
		inout  wire         hps_io_usb1_data2,                      //                         .usb1_data2,    USB data[2].
		inout  wire         hps_io_usb1_data3,                      //                         .usb1_data3,    USB data[3].
		inout  wire         hps_io_usb1_data4,                      //                         .usb1_data4,    USB data[4].
		inout  wire         hps_io_usb1_data5,                      //                         .usb1_data5,    USB data[5].
		inout  wire         hps_io_usb1_data6,                      //                         .usb1_data6,    USB data[6].
		inout  wire         hps_io_usb1_data7,                      //                         .usb1_data7,    USB data[7].
		output wire         hps_io_emac2_tx_clk,                    //                         .emac2_tx_clk,  EMAC2 transmit clock.
		output wire         hps_io_emac2_tx_ctl,                    //                         .emac2_tx_ctl,  EMAC2 transmit data enable.
		input  wire         hps_io_emac2_rx_clk,                    //                         .emac2_rx_clk,  EMAC2 receive clock.
		input  wire         hps_io_emac2_rx_ctl,                    //                         .emac2_rx_ctl,  EMAC2 receive data enable.
		output wire         hps_io_emac2_txd0,                      //                         .emac2_txd0,    EMAC2 transmit data[0].
		output wire         hps_io_emac2_txd1,                      //                         .emac2_txd1,    EMAC2 transmit data[1].
		input  wire         hps_io_emac2_rxd0,                      //                         .emac2_rxd0,    EMAC2 receive data[0].
		input  wire         hps_io_emac2_rxd1,                      //                         .emac2_rxd1,    EMAC2 receive data[1].
		output wire         hps_io_emac2_txd2,                      //                         .emac2_txd2,    EMAC2 transmit data[2].
		output wire         hps_io_emac2_txd3,                      //                         .emac2_txd3,    EMAC2 transmit data[3].
		input  wire         hps_io_emac2_rxd2,                      //                         .emac2_rxd2,    EMAC2 receive data[2].
		input  wire         hps_io_emac2_rxd3,                      //                         .emac2_rxd3,    EMAC2 receive data[3].
		inout  wire         hps_io_mdio2_mdio,                      //                         .mdio2_mdio,    EMAC2 MDIO data.
		output wire         hps_io_mdio2_mdc,                       //                         .mdio2_mdc,     EMAC2 MDIO clock.
		output wire         hps_io_uart0_tx,                        //                         .uart0_tx,      UART0 transmit data.
		input  wire         hps_io_uart0_rx,                        //                         .uart0_rx,      UART0 receive data.
		inout  wire         hps_io_i2c0_sda,                        //                         .i2c0_sda,      I2C0 serial data.
		inout  wire         hps_io_i2c0_scl,                        //                         .i2c0_scl,      I2C0 clock.
		inout  wire         hps_io_gpio0,                           //                         .gpio0,         GPIO0 IO0
		inout  wire         hps_io_gpio1,                           //                         .gpio1,         GPIO0 IO1
		inout  wire         hps_io_gpio8,                           //                         .gpio8,         GPIO0 IO8
		inout  wire         hps_io_gpio9,                           //                         .gpio9,         GPIO0 IO9
		inout  wire         hps_io_gpio10,                          //                         .gpio10,        GPIO0 IO10
		inout  wire         hps_io_gpio11,                          //                         .gpio11,        GPIO0 IO11
		inout  wire         hps_io_gpio28,                          //                         .gpio28,        GPIO1 IO4
		input  wire         usb31_io_vbus_det,                      //                 usb31_io.vbus_det,      VBUS detect.
		input  wire         usb31_io_flt_bar,                       //                         .flt_bar,       Connected to overcurrent input on USB3.1 controller.
		output wire [1:0]   usb31_io_usb_ctrl,                      //                         .usb_ctrl,      USB3.1 control output to connect to UMC.
		input  wire         usb31_io_usb31_id,                      //                         .usb31_id,      USB ID.
		input  wire [62:0]  fpga2hps_interrupt_irq,                 //       fpga2hps_interrupt.irq,           FPGA-to-HPS interrupts.
		input  wire         usb31_phy_pma_cpu_clk_clk,              //    usb31_phy_pma_cpu_clk.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_refclk_p_clk,                 //       usb31_phy_refclk_p.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_refclk_n_clk,                 //       usb31_phy_refclk_n.clk,           The connection made from "Reference and SystemPLL Clocks IP" to this pin will guide Quartus on properly setting clock network.
		input  wire         usb31_phy_rx_serial_n_i_rx_serial_n,    //    usb31_phy_rx_serial_n.i_rx_serial_n, Differential pair for RX serial data port. Historically was hidden; however now used in pam4 signal simulation model, hence needs to be connected by user.
		input  wire         usb31_phy_rx_serial_p_i_rx_serial_p,    //    usb31_phy_rx_serial_p.i_rx_serial_p, TX serial data port.
		output wire         usb31_phy_tx_serial_n_o_tx_serial_n,    //    usb31_phy_tx_serial_n.o_tx_serial_n, Differential pair for TX serial data port. Historically was hidden; however now used in pam4 signal simulation model, hence needs to be connected by user.
		output wire         usb31_phy_tx_serial_p_o_tx_serial_p,    //    usb31_phy_tx_serial_p.o_tx_serial_p, TX serial data port.
		input  wire         usb31_phy_reconfig_rst_reset,           //   usb31_phy_reconfig_rst.reset,         reconfig_reset
		input  wire         usb31_phy_reconfig_clk_clk,             //   usb31_phy_reconfig_clk.clk,           reconfig_clk
		input  wire [20:0]  usb31_phy_reconfig_slave_address,       // usb31_phy_reconfig_slave.address,       Address for Ethernet CSRs
		input  wire [3:0]   usb31_phy_reconfig_slave_byteenable,    //                         .byteenable,    Byte enable for read/write to Ethernet CSRs
		output wire         usb31_phy_reconfig_slave_readdatavalid, //                         .readdatavalid, Read data from Ethernet CSRs is valid
		input  wire         usb31_phy_reconfig_slave_read,          //                         .read,          Read command for Ethernet CSRs
		input  wire         usb31_phy_reconfig_slave_write,         //                         .write,         Write command for Ethernet CSRs
		output wire [31:0]  usb31_phy_reconfig_slave_readdata,      //                         .readdata,      Read data from reads to Ethernet CSRs
		input  wire [31:0]  usb31_phy_reconfig_slave_writedata,     //                         .writedata,     Data for writes to Ethernet CSRs
		output wire         usb31_phy_reconfig_slave_waitrequest,   //                         .waitrequest,   AVMM stall signal for operation on Ethernet CSRs
		input  wire         f2sdram_axi_clock_clk,                  //        f2sdram_axi_clock.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         f2sdram_axi_reset_reset,                //        f2sdram_axi_reset.reset,         Active high reset for f2sdram soft logic on FPGA. The actual bridge reset is driven by internal HPS Reset Manager.
		input  wire [31:0]  f2sdram_araddr,                         //                  f2sdram.araddr,        Address of the first transfer in a read transaction.
		input  wire [1:0]   f2sdram_arburst,                        //                         .arburst,       Burst type indicating how address changes between each transfer in a read transaction.
		input  wire [3:0]   f2sdram_arcache,                        //                         .arcache,       Indicates how a read transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_arid,                           //                         .arid,          Identification tag for a read transaction.
		input  wire [7:0]   f2sdram_arlen,                          //                         .arlen,         The exact number of data transfers in a read transaction.
		input  wire         f2sdram_arlock,                         //                         .arlock,        Provides info on atomic characteristics of a read transaction.
		input  wire [2:0]   f2sdram_arprot,                         //                         .arprot,        Protection attributes of a read transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_arqos,                          //                         .arqos,         Quality service identifier for a read transaction.
		output wire         f2sdram_arready,                        //                         .arready,       Indicates that a transfer on the read address channel can be accepted.
		input  wire [2:0]   f2sdram_arsize,                         //                         .arsize,        The number of bytes in each data transfer of a read transaction.
		input  wire         f2sdram_arvalid,                        //                         .arvalid,       Indicates the read address channel signals are valid.
		input  wire [31:0]  f2sdram_awaddr,                         //                         .awaddr,        The address of the first transfer in a write transaction.
		input  wire [1:0]   f2sdram_awburst,                        //                         .awburst,       Burst type indicating how address changes between each transfer in a write transaction.
		input  wire [3:0]   f2sdram_awcache,                        //                         .awcache,       Indicates how a write transaction is required to progress through a system.
		input  wire [4:0]   f2sdram_awid,                           //                         .awid,          Identification tag for a write transaction.
		input  wire [7:0]   f2sdram_awlen,                          //                         .awlen,         The exact number of data transfers in a write transaction.
		input  wire         f2sdram_awlock,                         //                         .awlock,        Provides info on atomic characteristics of a write transaction.
		input  wire [2:0]   f2sdram_awprot,                         //                         .awprot,        Protection attributes of a write transaction: privelege, security level, access type.
		input  wire [3:0]   f2sdram_awqos,                          //                         .awqos,         Quality of servide identifier for a write transaction.
		output wire         f2sdram_awready,                        //                         .awready,       Indicates that a transfer on the write channel address can be accepted.
		input  wire [2:0]   f2sdram_awsize,                         //                         .awsize,        The number of bytes in each data transfer of a write transaction.
		input  wire         f2sdram_awvalid,                        //                         .awvalid,       Indicates the write address channel signals are valid.
		output wire [4:0]   f2sdram_bid,                            //                         .bid,           Identification tag for a write response.
		input  wire         f2sdram_bready,                         //                         .bready,        Indicates that a transfer on the write response channel can be accepted.
		output wire [1:0]   f2sdram_bresp,                          //                         .bresp,         Write response indicating the status of a write transaction.
		output wire         f2sdram_bvalid,                         //                         .bvalid,        Indicates that the write response channel signals are valid.
		output wire [255:0] f2sdram_rdata,                          //                         .rdata,         Read data.
		output wire [4:0]   f2sdram_rid,                            //                         .rid,           Identification tag for read data and response.
		output wire         f2sdram_rlast,                          //                         .rlast,         Indicates the last data transfer in a read transaction.
		input  wire         f2sdram_rready,                         //                         .rready,        Indicates a transfer on the read data channel can be accepted.
		output wire [1:0]   f2sdram_rresp,                          //                         .rresp,         Read response indicating the status of a read transfer.
		output wire         f2sdram_rvalid,                         //                         .rvalid,        Indicates the read channel data channel signals are valid.
		input  wire [255:0] f2sdram_wdata,                          //                         .wdata,         Write data.
		input  wire         f2sdram_wlast,                          //                         .wlast,         Indicates the last data transfer in a write transaction.
		output wire         f2sdram_wready,                         //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		input  wire [31:0]  f2sdram_wstrb,                          //                         .wstrb,         Write strobes indicating which bye lanes hold valid data.
		input  wire         f2sdram_wvalid,                         //                         .wvalid,        Indicates the write channel data signals are valid.
		input  wire [7:0]   f2sdram_aruser,                         //                         .aruser,        Extension for the read address channel.
		input  wire [7:0]   f2sdram_awuser,                         //                         .awuser,        Extension for the write address channel.
		input  wire [7:0]   f2sdram_wuser,                          //                         .wuser,         Extension for the write data channel.
		output wire [7:0]   f2sdram_buser,                          //                         .buser,         Extension for the write response channel.
		input  wire [3:0]   f2sdram_arregion,                       //                         .arregion,      Region indicator for a read transaction.
		output wire [7:0]   f2sdram_ruser,                          //                         .ruser,         Extension for the read data channel.
		input  wire [3:0]   f2sdram_awregion,                       //                         .awregion,      Region indicator for a write transaction.
		input  wire         io96b0_csr_axi_clk_clk,                 //       io96b0_csr_axi_clk.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_csr_axi_rst_reset_n,             //       io96b0_csr_axi_rst.reset_n,       Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_csr_axi_arready,                 //           io96b0_csr_axi.arready,       Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_csr_axi_awready,                 //                         .awready,       Indicates a transfer on the write address channel can be accepted.
		input  wire [1:0]   io96b0_csr_axi_bresp,                   //                         .bresp,         Indicates status of write transaction.
		input  wire         io96b0_csr_axi_bvalid,                  //                         .bvalid,        Indicates write response channel signals are valid.
		input  wire [31:0]  io96b0_csr_axi_rdata,                   //                         .rdata,         Read data.
		input  wire [1:0]   io96b0_csr_axi_rresp,                   //                         .rresp,         Indicates status of read transaction.
		input  wire         io96b0_csr_axi_rvalid,                  //                         .rvalid,        Indicates read data channel signals are valid.
		input  wire         io96b0_csr_axi_wready,                  //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		output wire [31:0]  io96b0_csr_axi_araddr,                  //                         .araddr,        The address of the first transfer in a read transaction.
		output wire         io96b0_csr_axi_arvalid,                 //                         .arvalid,       Indicates read address channel signals are valid.
		output wire [31:0]  io96b0_csr_axi_awaddr,                  //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire         io96b0_csr_axi_awvalid,                 //                         .awvalid,       Indicates write address channel signals are valid.
		output wire         io96b0_csr_axi_bready,                  //                         .bready,        Indicates a transfer on the write response channel can be accepted.
		output wire         io96b0_csr_axi_rready,                  //                         .rready,        Indicates a transfer on the read data channel can be accepted.
		output wire [31:0]  io96b0_csr_axi_wdata,                   //                         .wdata,         Write data.
		output wire [3:0]   io96b0_csr_axi_wstrb,                   //                         .wstrb,         Write strobes indicating which bye lanes hold valid data.
		output wire         io96b0_csr_axi_wvalid,                  //                         .wvalid,        Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_csr_axi_arprot,                  //                         .arprot,        Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_csr_axi_awprot,                  //                         .awprot,        Placegolder AWPROT. Protection attributes not supported for this bridge.
		input  wire         io96b0_ch0_axi_clk_clk,                 //       io96b0_ch0_axi_clk.clk,           Clock source signal. Synchronous signals are sampled on the rising edge of this clock.
		input  wire         io96b0_ch0_axi_rst_reset_n,             //       io96b0_ch0_axi_rst.reset_n,       Required placeholder reset. The actual bridge reset is driven by HPS Reset Manager.
		input  wire         io96b0_ch0_axi_arready,                 //           io96b0_ch0_axi.arready,       Indicates a transfer on the read address channel can be accepted.
		input  wire         io96b0_ch0_axi_awready,                 //                         .awready,       Indicates a transfer on the write address channel can be accepted.
		input  wire [6:0]   io96b0_ch0_axi_bid,                     //                         .bid,           Identification tag for a write response.
		input  wire [1:0]   io96b0_ch0_axi_bresp,                   //                         .bresp,         Indicates the status of a write transaction.
		input  wire         io96b0_ch0_axi_bvalid,                  //                         .bvalid,        Indicates write response channel signals are valid.
		input  wire [255:0] io96b0_ch0_axi_rdata,                   //                         .rdata,         Read data.
		input  wire [6:0]   io96b0_ch0_axi_rid,                     //                         .rid,           Identification tag for read data and response.
		input  wire         io96b0_ch0_axi_rlast,                   //                         .rlast,         Indicates the last data transfer in a read transaction.
		input  wire [1:0]   io96b0_ch0_axi_rresp,                   //                         .rresp,         Indicates the status of a read transfer.
		input  wire [31:0]  io96b0_ch0_axi_ruser,                   //                         .ruser,         Extension of read data channel.
		input  wire         io96b0_ch0_axi_rvalid,                  //                         .rvalid,        Indicates read data channel signals are valid.
		input  wire         io96b0_ch0_axi_wready,                  //                         .wready,        Indicates a transfer on the write data channel can be accepted.
		output wire [43:0]  io96b0_ch0_axi_araddr,                  //                         .araddr,        The address of the first transfer in a read transaction.
		output wire [1:0]   io96b0_ch0_axi_arburst,                 //                         .arburst,       Burst type indicating how address changes between each transfer in a read transaction.
		output wire [6:0]   io96b0_ch0_axi_arid,                    //                         .arid,          Identification tag for a read transaction.
		output wire [7:0]   io96b0_ch0_axi_arlen,                   //                         .arlen,         Exact number of data transfers in a read transaction.
		output wire         io96b0_ch0_axi_arlock,                  //                         .arlock,        Provides info on atomic characteristics of a read transaction.
		output wire [3:0]   io96b0_ch0_axi_arqos,                   //                         .arqos,         Quality of service identifier for a read transaction.
		output wire [2:0]   io96b0_ch0_axi_arsize,                  //                         .arsize,        The number of bytes in each data transfer in a read transaction.
		output wire [13:0]  io96b0_ch0_axi_aruser,                  //                         .aruser,        Extension of read address channel.
		output wire         io96b0_ch0_axi_arvalid,                 //                         .arvalid,       Indicates read address channel signals are valid.
		output wire [43:0]  io96b0_ch0_axi_awaddr,                  //                         .awaddr,        The address of the first transfer in a write transaction.
		output wire [1:0]   io96b0_ch0_axi_awburst,                 //                         .awburst,       Burst type indicating how address changes between each transfer in a write transaction.
		output wire [6:0]   io96b0_ch0_axi_awid,                    //                         .awid,          Identification tag for a write transaction.
		output wire [7:0]   io96b0_ch0_axi_awlen,                   //                         .awlen,         Exact number of data transfers in a write transaction.
		output wire         io96b0_ch0_axi_awlock,                  //                         .awlock,        Provides info on atomic characteristics of a write transaction.
		output wire [3:0]   io96b0_ch0_axi_awqos,                   //                         .awqos,         Quality of service identifier for a write transaction.
		output wire [2:0]   io96b0_ch0_axi_awsize,                  //                         .awsize,        Number of bytes in each data transfer in a write transaction.
		output wire [13:0]  io96b0_ch0_axi_awuser,                  //                         .awuser,        Extension of write address channel.
		output wire         io96b0_ch0_axi_awvalid,                 //                         .awvalid,       Indicates write address channel signals are valid.
		output wire         io96b0_ch0_axi_bready,                  //                         .bready,        Indicates a transfer on write response channel can be accepted.
		output wire         io96b0_ch0_axi_rready,                  //                         .rready,        Indicates a transfer on read data channel can be accepted.
		output wire [255:0] io96b0_ch0_axi_wdata,                   //                         .wdata,         Write data.
		output wire         io96b0_ch0_axi_wlast,                   //                         .wlast,         Indicates the last data transfer in a write transaction.
		output wire [31:0]  io96b0_ch0_axi_wstrb,                   //                         .wstrb,         Write strobes indicating which byte lanes hold valid data.
		output wire [31:0]  io96b0_ch0_axi_wuser,                   //                         .wuser,         Extension of the write data channel.
		output wire         io96b0_ch0_axi_wvalid,                  //                         .wvalid,        Indicates write data channel signals are valid.
		output wire [2:0]   io96b0_ch0_axi_arprot,                  //                         .arprot,        Placeholder ARPROT. Protection attributes not supported for this bridge.
		output wire [2:0]   io96b0_ch0_axi_awprot                   //                         .awprot,        Placeholder AWPROT. Protection attributes not supported for this bridge.
	);

	wire    [1:0] sm_hps_hps_dmi0_interconnect_awburst;                               // sm_hps:hps2mpfe_dmi0_awburst -> sm_mpfe:hps2mpfe_dmi0_awburst
	wire    [7:0] sm_hps_hps_dmi0_interconnect_arlen;                                 // sm_hps:hps2mpfe_dmi0_arlen -> sm_mpfe:hps2mpfe_dmi0_arlen
	wire    [3:0] sm_hps_hps_dmi0_interconnect_arqos;                                 // sm_hps:hps2mpfe_dmi0_arqos -> sm_mpfe:hps2mpfe_dmi0_arqos
	wire    [7:0] sm_hps_hps_dmi0_interconnect_awuser;                                // sm_hps:hps2mpfe_dmi0_awuser -> sm_mpfe:hps2mpfe_dmi0_awuser
	wire          sm_hps_hps_dmi0_interconnect_wready;                                // sm_mpfe:hps2mpfe_dmi0_wready -> sm_hps:hps2mpfe_dmi0_wready
	wire   [31:0] sm_hps_hps_dmi0_interconnect_wstrb;                                 // sm_hps:hps2mpfe_dmi0_wstrb -> sm_mpfe:hps2mpfe_dmi0_wstrb
	wire    [9:0] sm_hps_hps_dmi0_interconnect_rid;                                   // sm_mpfe:hps2mpfe_dmi0_rid -> sm_hps:hps2mpfe_dmi0_rid
	wire          sm_hps_hps_dmi0_interconnect_rready;                                // sm_hps:hps2mpfe_dmi0_rready -> sm_mpfe:hps2mpfe_dmi0_rready
	wire    [7:0] sm_hps_hps_dmi0_interconnect_awlen;                                 // sm_hps:hps2mpfe_dmi0_awlen -> sm_mpfe:hps2mpfe_dmi0_awlen
	wire    [3:0] sm_hps_hps_dmi0_interconnect_awqos;                                 // sm_hps:hps2mpfe_dmi0_awqos -> sm_mpfe:hps2mpfe_dmi0_awqos
	wire    [3:0] sm_hps_hps_dmi0_interconnect_arcache;                               // sm_hps:hps2mpfe_dmi0_arcache -> sm_mpfe:hps2mpfe_dmi0_arcache
	wire   [43:0] sm_hps_hps_dmi0_interconnect_araddr;                                // sm_hps:hps2mpfe_dmi0_araddr -> sm_mpfe:hps2mpfe_dmi0_araddr
	wire          sm_hps_hps_dmi0_interconnect_wvalid;                                // sm_hps:hps2mpfe_dmi0_wvalid -> sm_mpfe:hps2mpfe_dmi0_wvalid
	wire    [2:0] sm_hps_hps_dmi0_interconnect_arprot;                                // sm_hps:hps2mpfe_dmi0_arprot -> sm_mpfe:hps2mpfe_dmi0_arprot
	wire          sm_hps_hps_dmi0_interconnect_arvalid;                               // sm_hps:hps2mpfe_dmi0_arvalid -> sm_mpfe:hps2mpfe_dmi0_arvalid
	wire    [2:0] sm_hps_hps_dmi0_interconnect_awprot;                                // sm_hps:hps2mpfe_dmi0_awprot -> sm_mpfe:hps2mpfe_dmi0_awprot
	wire  [255:0] sm_hps_hps_dmi0_interconnect_wdata;                                 // sm_hps:hps2mpfe_dmi0_wdata -> sm_mpfe:hps2mpfe_dmi0_wdata
	wire    [9:0] sm_hps_hps_dmi0_interconnect_arid;                                  // sm_hps:hps2mpfe_dmi0_arid -> sm_mpfe:hps2mpfe_dmi0_arid
	wire    [3:0] sm_hps_hps_dmi0_interconnect_awcache;                               // sm_hps:hps2mpfe_dmi0_awcache -> sm_mpfe:hps2mpfe_dmi0_awcache
	wire          sm_hps_hps_dmi0_interconnect_arlock;                                // sm_hps:hps2mpfe_dmi0_arlock -> sm_mpfe:hps2mpfe_dmi0_arlock
	wire          sm_hps_hps_dmi0_interconnect_awlock;                                // sm_hps:hps2mpfe_dmi0_awlock -> sm_mpfe:hps2mpfe_dmi0_awlock
	wire   [43:0] sm_hps_hps_dmi0_interconnect_awaddr;                                // sm_hps:hps2mpfe_dmi0_awaddr -> sm_mpfe:hps2mpfe_dmi0_awaddr
	wire          sm_hps_hps_dmi0_interconnect_arready;                               // sm_mpfe:hps2mpfe_dmi0_arready -> sm_hps:hps2mpfe_dmi0_arready
	wire    [1:0] sm_hps_hps_dmi0_interconnect_bresp;                                 // sm_mpfe:hps2mpfe_dmi0_bresp -> sm_hps:hps2mpfe_dmi0_bresp
	wire  [255:0] sm_hps_hps_dmi0_interconnect_rdata;                                 // sm_mpfe:hps2mpfe_dmi0_rdata -> sm_hps:hps2mpfe_dmi0_rdata
	wire    [1:0] sm_hps_hps_dmi0_interconnect_arburst;                               // sm_hps:hps2mpfe_dmi0_arburst -> sm_mpfe:hps2mpfe_dmi0_arburst
	wire          sm_hps_hps_dmi0_interconnect_awready;                               // sm_mpfe:hps2mpfe_dmi0_awready -> sm_hps:hps2mpfe_dmi0_awready
	wire    [2:0] sm_hps_hps_dmi0_interconnect_arsize;                                // sm_hps:hps2mpfe_dmi0_arsize -> sm_mpfe:hps2mpfe_dmi0_arsize
	wire          sm_hps_hps_dmi0_interconnect_bready;                                // sm_hps:hps2mpfe_dmi0_bready -> sm_mpfe:hps2mpfe_dmi0_bready
	wire          sm_hps_hps_dmi0_interconnect_rlast;                                 // sm_mpfe:hps2mpfe_dmi0_rlast -> sm_hps:hps2mpfe_dmi0_rlast
	wire          sm_hps_hps_dmi0_interconnect_wlast;                                 // sm_hps:hps2mpfe_dmi0_wlast -> sm_mpfe:hps2mpfe_dmi0_wlast
	wire    [1:0] sm_hps_hps_dmi0_interconnect_rresp;                                 // sm_mpfe:hps2mpfe_dmi0_rresp -> sm_hps:hps2mpfe_dmi0_rresp
	wire    [9:0] sm_hps_hps_dmi0_interconnect_awid;                                  // sm_hps:hps2mpfe_dmi0_awid -> sm_mpfe:hps2mpfe_dmi0_awid
	wire    [9:0] sm_hps_hps_dmi0_interconnect_bid;                                   // sm_mpfe:hps2mpfe_dmi0_bid -> sm_hps:hps2mpfe_dmi0_bid
	wire          sm_hps_hps_dmi0_interconnect_bvalid;                                // sm_mpfe:hps2mpfe_dmi0_bvalid -> sm_hps:hps2mpfe_dmi0_bvalid
	wire    [7:0] sm_hps_hps_dmi0_interconnect_aruser;                                // sm_hps:hps2mpfe_dmi0_aruser -> sm_mpfe:hps2mpfe_dmi0_aruser
	wire    [2:0] sm_hps_hps_dmi0_interconnect_awsize;                                // sm_hps:hps2mpfe_dmi0_awsize -> sm_mpfe:hps2mpfe_dmi0_awsize
	wire          sm_hps_hps_dmi0_interconnect_awvalid;                               // sm_hps:hps2mpfe_dmi0_awvalid -> sm_mpfe:hps2mpfe_dmi0_awvalid
	wire          sm_hps_hps_dmi0_interconnect_rvalid;                                // sm_mpfe:hps2mpfe_dmi0_rvalid -> sm_hps:hps2mpfe_dmi0_rvalid
	wire    [1:0] sm_hps_hps_dmi1_interconnect_awburst;                               // sm_hps:hps2mpfe_dmi1_awburst -> sm_mpfe:hps2mpfe_dmi1_awburst
	wire    [7:0] sm_hps_hps_dmi1_interconnect_arlen;                                 // sm_hps:hps2mpfe_dmi1_arlen -> sm_mpfe:hps2mpfe_dmi1_arlen
	wire    [3:0] sm_hps_hps_dmi1_interconnect_arqos;                                 // sm_hps:hps2mpfe_dmi1_arqos -> sm_mpfe:hps2mpfe_dmi1_arqos
	wire    [7:0] sm_hps_hps_dmi1_interconnect_awuser;                                // sm_hps:hps2mpfe_dmi1_awuser -> sm_mpfe:hps2mpfe_dmi1_awuser
	wire          sm_hps_hps_dmi1_interconnect_wready;                                // sm_mpfe:hps2mpfe_dmi1_wready -> sm_hps:hps2mpfe_dmi1_wready
	wire   [31:0] sm_hps_hps_dmi1_interconnect_wstrb;                                 // sm_hps:hps2mpfe_dmi1_wstrb -> sm_mpfe:hps2mpfe_dmi1_wstrb
	wire    [9:0] sm_hps_hps_dmi1_interconnect_rid;                                   // sm_mpfe:hps2mpfe_dmi1_rid -> sm_hps:hps2mpfe_dmi1_rid
	wire          sm_hps_hps_dmi1_interconnect_rready;                                // sm_hps:hps2mpfe_dmi1_rready -> sm_mpfe:hps2mpfe_dmi1_rready
	wire    [7:0] sm_hps_hps_dmi1_interconnect_awlen;                                 // sm_hps:hps2mpfe_dmi1_awlen -> sm_mpfe:hps2mpfe_dmi1_awlen
	wire    [3:0] sm_hps_hps_dmi1_interconnect_awqos;                                 // sm_hps:hps2mpfe_dmi1_awqos -> sm_mpfe:hps2mpfe_dmi1_awqos
	wire    [3:0] sm_hps_hps_dmi1_interconnect_arcache;                               // sm_hps:hps2mpfe_dmi1_arcache -> sm_mpfe:hps2mpfe_dmi1_arcache
	wire   [43:0] sm_hps_hps_dmi1_interconnect_araddr;                                // sm_hps:hps2mpfe_dmi1_araddr -> sm_mpfe:hps2mpfe_dmi1_araddr
	wire          sm_hps_hps_dmi1_interconnect_wvalid;                                // sm_hps:hps2mpfe_dmi1_wvalid -> sm_mpfe:hps2mpfe_dmi1_wvalid
	wire    [2:0] sm_hps_hps_dmi1_interconnect_arprot;                                // sm_hps:hps2mpfe_dmi1_arprot -> sm_mpfe:hps2mpfe_dmi1_arprot
	wire          sm_hps_hps_dmi1_interconnect_arvalid;                               // sm_hps:hps2mpfe_dmi1_arvalid -> sm_mpfe:hps2mpfe_dmi1_arvalid
	wire    [2:0] sm_hps_hps_dmi1_interconnect_awprot;                                // sm_hps:hps2mpfe_dmi1_awprot -> sm_mpfe:hps2mpfe_dmi1_awprot
	wire  [255:0] sm_hps_hps_dmi1_interconnect_wdata;                                 // sm_hps:hps2mpfe_dmi1_wdata -> sm_mpfe:hps2mpfe_dmi1_wdata
	wire    [9:0] sm_hps_hps_dmi1_interconnect_arid;                                  // sm_hps:hps2mpfe_dmi1_arid -> sm_mpfe:hps2mpfe_dmi1_arid
	wire    [3:0] sm_hps_hps_dmi1_interconnect_awcache;                               // sm_hps:hps2mpfe_dmi1_awcache -> sm_mpfe:hps2mpfe_dmi1_awcache
	wire          sm_hps_hps_dmi1_interconnect_arlock;                                // sm_hps:hps2mpfe_dmi1_arlock -> sm_mpfe:hps2mpfe_dmi1_arlock
	wire          sm_hps_hps_dmi1_interconnect_awlock;                                // sm_hps:hps2mpfe_dmi1_awlock -> sm_mpfe:hps2mpfe_dmi1_awlock
	wire   [43:0] sm_hps_hps_dmi1_interconnect_awaddr;                                // sm_hps:hps2mpfe_dmi1_awaddr -> sm_mpfe:hps2mpfe_dmi1_awaddr
	wire          sm_hps_hps_dmi1_interconnect_arready;                               // sm_mpfe:hps2mpfe_dmi1_arready -> sm_hps:hps2mpfe_dmi1_arready
	wire    [1:0] sm_hps_hps_dmi1_interconnect_bresp;                                 // sm_mpfe:hps2mpfe_dmi1_bresp -> sm_hps:hps2mpfe_dmi1_bresp
	wire  [255:0] sm_hps_hps_dmi1_interconnect_rdata;                                 // sm_mpfe:hps2mpfe_dmi1_rdata -> sm_hps:hps2mpfe_dmi1_rdata
	wire    [1:0] sm_hps_hps_dmi1_interconnect_arburst;                               // sm_hps:hps2mpfe_dmi1_arburst -> sm_mpfe:hps2mpfe_dmi1_arburst
	wire          sm_hps_hps_dmi1_interconnect_awready;                               // sm_mpfe:hps2mpfe_dmi1_awready -> sm_hps:hps2mpfe_dmi1_awready
	wire    [2:0] sm_hps_hps_dmi1_interconnect_arsize;                                // sm_hps:hps2mpfe_dmi1_arsize -> sm_mpfe:hps2mpfe_dmi1_arsize
	wire          sm_hps_hps_dmi1_interconnect_bready;                                // sm_hps:hps2mpfe_dmi1_bready -> sm_mpfe:hps2mpfe_dmi1_bready
	wire          sm_hps_hps_dmi1_interconnect_rlast;                                 // sm_mpfe:hps2mpfe_dmi1_rlast -> sm_hps:hps2mpfe_dmi1_rlast
	wire          sm_hps_hps_dmi1_interconnect_wlast;                                 // sm_hps:hps2mpfe_dmi1_wlast -> sm_mpfe:hps2mpfe_dmi1_wlast
	wire    [1:0] sm_hps_hps_dmi1_interconnect_rresp;                                 // sm_mpfe:hps2mpfe_dmi1_rresp -> sm_hps:hps2mpfe_dmi1_rresp
	wire    [9:0] sm_hps_hps_dmi1_interconnect_awid;                                  // sm_hps:hps2mpfe_dmi1_awid -> sm_mpfe:hps2mpfe_dmi1_awid
	wire    [9:0] sm_hps_hps_dmi1_interconnect_bid;                                   // sm_mpfe:hps2mpfe_dmi1_bid -> sm_hps:hps2mpfe_dmi1_bid
	wire          sm_hps_hps_dmi1_interconnect_bvalid;                                // sm_mpfe:hps2mpfe_dmi1_bvalid -> sm_hps:hps2mpfe_dmi1_bvalid
	wire    [7:0] sm_hps_hps_dmi1_interconnect_aruser;                                // sm_hps:hps2mpfe_dmi1_aruser -> sm_mpfe:hps2mpfe_dmi1_aruser
	wire    [2:0] sm_hps_hps_dmi1_interconnect_awsize;                                // sm_hps:hps2mpfe_dmi1_awsize -> sm_mpfe:hps2mpfe_dmi1_awsize
	wire          sm_hps_hps_dmi1_interconnect_awvalid;                               // sm_hps:hps2mpfe_dmi1_awvalid -> sm_mpfe:hps2mpfe_dmi1_awvalid
	wire          sm_hps_hps_dmi1_interconnect_rvalid;                                // sm_mpfe:hps2mpfe_dmi1_rvalid -> sm_hps:hps2mpfe_dmi1_rvalid
	wire          sm_hps_hps_ccu_interconnect_clk_clk;                                // sm_hps:hps2mpfe_ccu_clk -> sm_mpfe:hps2mpfe_ccu_clk
	wire          sm_hps_hps_ccu_interconnect_rst_reset;                              // sm_hps:hps2mpfe_ccu_rst -> sm_mpfe:hps2mpfe_ccu_rst
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_awburst;                             // sm_hps:hps2mpfe_csr_awburst -> sm_mpfe:hps2mpfe_csr_awburst
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_arlen;                               // sm_hps:hps2mpfe_csr_arlen -> sm_mpfe:hps2mpfe_csr_arlen
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_awuser;                              // sm_hps:hps2mpfe_csr_awuser -> sm_mpfe:hps2mpfe_csr_awuser
	wire          sm_hps_hps_s2mpfe_interconnect_wready;                              // sm_mpfe:hps2mpfe_csr_wready -> sm_hps:hps2mpfe_csr_wready
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_wstrb;                               // sm_hps:hps2mpfe_csr_wstrb -> sm_mpfe:hps2mpfe_csr_wstrb
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_rid;                                 // sm_mpfe:hps2mpfe_csr_rid -> sm_hps:hps2mpfe_csr_rid
	wire          sm_hps_hps_s2mpfe_interconnect_rready;                              // sm_hps:hps2mpfe_csr_rready -> sm_mpfe:hps2mpfe_csr_rready
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_awlen;                               // sm_hps:hps2mpfe_csr_awlen -> sm_mpfe:hps2mpfe_csr_awlen
	wire    [3:0] sm_hps_hps_s2mpfe_interconnect_arcache;                             // sm_hps:hps2mpfe_csr_arcache -> sm_mpfe:hps2mpfe_csr_arcache
	wire   [43:0] sm_hps_hps_s2mpfe_interconnect_araddr;                              // sm_hps:hps2mpfe_csr_araddr -> sm_mpfe:hps2mpfe_csr_araddr
	wire          sm_hps_hps_s2mpfe_interconnect_wvalid;                              // sm_hps:hps2mpfe_csr_wvalid -> sm_mpfe:hps2mpfe_csr_wvalid
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_arprot;                              // sm_hps:hps2mpfe_csr_arprot -> sm_mpfe:hps2mpfe_csr_arprot
	wire          sm_hps_hps_s2mpfe_interconnect_arvalid;                             // sm_hps:hps2mpfe_csr_arvalid -> sm_mpfe:hps2mpfe_csr_arvalid
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_awprot;                              // sm_hps:hps2mpfe_csr_awprot -> sm_mpfe:hps2mpfe_csr_awprot
	wire   [63:0] sm_hps_hps_s2mpfe_interconnect_wdata;                               // sm_hps:hps2mpfe_csr_wdata -> sm_mpfe:hps2mpfe_csr_wdata
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_arid;                                // sm_hps:hps2mpfe_csr_arid -> sm_mpfe:hps2mpfe_csr_arid
	wire    [3:0] sm_hps_hps_s2mpfe_interconnect_awcache;                             // sm_hps:hps2mpfe_csr_awcache -> sm_mpfe:hps2mpfe_csr_awcache
	wire          sm_hps_hps_s2mpfe_interconnect_arlock;                              // sm_hps:hps2mpfe_csr_arlock -> sm_mpfe:hps2mpfe_csr_arlock
	wire          sm_hps_hps_s2mpfe_interconnect_awlock;                              // sm_hps:hps2mpfe_csr_awlock -> sm_mpfe:hps2mpfe_csr_awlock
	wire   [43:0] sm_hps_hps_s2mpfe_interconnect_awaddr;                              // sm_hps:hps2mpfe_csr_awaddr -> sm_mpfe:hps2mpfe_csr_awaddr
	wire          sm_hps_hps_s2mpfe_interconnect_arready;                             // sm_mpfe:hps2mpfe_csr_arready -> sm_hps:hps2mpfe_csr_arready
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_bresp;                               // sm_mpfe:hps2mpfe_csr_bresp -> sm_hps:hps2mpfe_csr_bresp
	wire   [63:0] sm_hps_hps_s2mpfe_interconnect_rdata;                               // sm_mpfe:hps2mpfe_csr_rdata -> sm_hps:hps2mpfe_csr_rdata
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_arburst;                             // sm_hps:hps2mpfe_csr_arburst -> sm_mpfe:hps2mpfe_csr_arburst
	wire          sm_hps_hps_s2mpfe_interconnect_awready;                             // sm_mpfe:hps2mpfe_csr_awready -> sm_hps:hps2mpfe_csr_awready
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_arsize;                              // sm_hps:hps2mpfe_csr_arsize -> sm_mpfe:hps2mpfe_csr_arsize
	wire          sm_hps_hps_s2mpfe_interconnect_bready;                              // sm_hps:hps2mpfe_csr_bready -> sm_mpfe:hps2mpfe_csr_bready
	wire          sm_hps_hps_s2mpfe_interconnect_rlast;                               // sm_mpfe:hps2mpfe_csr_rlast -> sm_hps:hps2mpfe_csr_rlast
	wire          sm_hps_hps_s2mpfe_interconnect_wlast;                               // sm_hps:hps2mpfe_csr_wlast -> sm_mpfe:hps2mpfe_csr_wlast
	wire    [1:0] sm_hps_hps_s2mpfe_interconnect_rresp;                               // sm_mpfe:hps2mpfe_csr_rresp -> sm_hps:hps2mpfe_csr_rresp
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_awid;                                // sm_hps:hps2mpfe_csr_awid -> sm_mpfe:hps2mpfe_csr_awid
	wire    [9:0] sm_hps_hps_s2mpfe_interconnect_bid;                                 // sm_mpfe:hps2mpfe_csr_bid -> sm_hps:hps2mpfe_csr_bid
	wire          sm_hps_hps_s2mpfe_interconnect_bvalid;                              // sm_mpfe:hps2mpfe_csr_bvalid -> sm_hps:hps2mpfe_csr_bvalid
	wire    [7:0] sm_hps_hps_s2mpfe_interconnect_aruser;                              // sm_hps:hps2mpfe_csr_aruser -> sm_mpfe:hps2mpfe_csr_aruser
	wire    [2:0] sm_hps_hps_s2mpfe_interconnect_awsize;                              // sm_hps:hps2mpfe_csr_awsize -> sm_mpfe:hps2mpfe_csr_awsize
	wire          sm_hps_hps_s2mpfe_interconnect_awvalid;                             // sm_hps:hps2mpfe_csr_awvalid -> sm_mpfe:hps2mpfe_csr_awvalid
	wire          sm_hps_hps_s2mpfe_interconnect_rvalid;                              // sm_mpfe:hps2mpfe_csr_rvalid -> sm_hps:hps2mpfe_csr_rvalid
	wire          sm_mpfe_sdram2hps_interconnect_tbu_ras;                             // sm_mpfe:sdram_tbu_ras_irpt -> sm_hps:fpga2sdram_tbu_ras_irpt
	wire          sm_mpfe_sdram2hps_interconnect_ack;                                 // sm_mpfe:sdram_bridge_ack -> sm_hps:fpga2sdram_bridge_ack
	wire          sm_hps_hps2sdram_interconnect_reset_n;                              // sm_hps:fpga2sdram_bridge_rst_n -> sm_mpfe:sdram_bridge_rst_n
	wire          sm_mpfe_sdram2hps_interconnect_tbu_pmu;                             // sm_mpfe:sdram_tbu_pmu_irpt -> sm_hps:fpga2sdram_tbu_pmu_irpt
	wire          sm_hps_hps2sdram_interconnect_req;                                  // sm_hps:fpga2sdram_bridge_req -> sm_mpfe:sdram_bridge_req
	wire          sm_usb31_phy_o_usb31_pipe_clk_clk;                                  // sm_usb31_phy:o_usb31_pipe_clk -> sm_hps:usb31_pipe_pclk
	wire          sm_usb31_phy_o_usb31_pipe_rxvalid_o_usb31_pipe_rxvalid;             // sm_usb31_phy:o_usb31_pipe_RxValid -> sm_hps:usb31_pipe_RxValid
	wire   [15:0] sm_usb31_phy_o_usb31_pipe_rxdata_o_usb31_pipe_rxdata;               // sm_usb31_phy:o_usb31_pipe_RxData -> sm_hps:usb31_pipe_RxData
	wire    [1:0] sm_usb31_phy_o_usb31_pipe_rxdatak_o_usb31_pipe_rxdatak;             // sm_usb31_phy:o_usb31_pipe_RxDataK -> sm_hps:usb31_pipe_RxDataK
	wire          sm_usb31_phy_o_usb31_pipe_phystatus_o_usb31_pipe_phystatus;         // sm_usb31_phy:o_usb31_pipe_PhyStatus -> sm_hps:usb31_pipe_PhyStatus
	wire          sm_usb31_phy_o_usb31_pipe_rxelecidle_o_usb31_pipe_rxelecidle;       // sm_usb31_phy:o_usb31_pipe_RxElecidle -> sm_hps:usb31_pipe_RxElecIdle
	wire    [2:0] sm_usb31_phy_o_usb31_pipe_rxstatus_o_usb31_pipe_rxstatus;           // sm_usb31_phy:o_usb31_pipe_Rxstatus -> sm_hps:usb31_pipe_RxStatus
	wire          sm_hps_usb31_rst_interconnect_i_usb31_pipe_reset_n;                 // sm_hps:usb31_pipe_reset_n -> sm_usb31_phy:i_usb31_pipe_reset_n
	wire   [15:0] sm_hps_usb31_txdata_interconnect_i_usb31_pipe_txdata;               // sm_hps:usb31_pipe_TxData -> sm_usb31_phy:i_usb31_pipe_TxData
	wire    [1:0] sm_hps_usb31_txdatak_interconnect_i_usb31_pipe_txdatak;             // sm_hps:usb31_pipe_TxDataK -> sm_usb31_phy:i_usb31_pipe_TxDataK
	wire          sm_hps_usb31_rxeqtrain_interconnect_i_usb31_pipe_rxeqtrain;         // sm_hps:usb31_pipe_RxEqTrain -> sm_usb31_phy:i_usb31_pipe_RxEqTrain
	wire          sm_hps_usb31_elasbuf_interconnect_i_usb31_pipe_elasbuffermode;      // sm_hps:usb31_pipe_ElasBufferMode -> sm_usb31_phy:i_usb31_pipe_ElasBufferMode
	wire          sm_hps_usb31_loopback_interconnect_i_usb31_pipe_txdetectrxloopback; // sm_hps:usb31_pipe_TxDetectRxLoopbk -> sm_usb31_phy:i_usb31_pipe_TxDetectRxLoopback
	wire          sm_hps_usb31_txelecidle_interconnect_i_usb31_pipe_txelecidle;       // sm_hps:usb31_pipe_TxElecIdle -> sm_usb31_phy:i_usb31_pipe_TxElecidle
	wire          sm_hps_usb31_rxpolarity_interconnect_i_usb31_pipe_rxpolarity;       // sm_hps:usb31_pipe_RxPolarity -> sm_usb31_phy:i_usb31_pipe_RxPolarity
	wire    [3:0] sm_hps_usb31_pwrdown_interconnect_i_usb31_pipe_powerdown;           // sm_hps:usb31_pipe_PowerDown -> sm_usb31_phy:i_usb31_pipe_PowerDown
	wire    [1:0] sm_hps_usb31_piperate_interconnect_i_usb31_pipe_txdeemphasis;       // sm_hps:usb31_pipe_Rate -> sm_usb31_phy:i_usb31_pipe_TxDeEmphasis
	wire          sm_hps_usb31_rxterm_interconnect_i_usb31_pipe_rxtermination;        // sm_hps:usb31_pipe_RxTermination -> sm_usb31_phy:i_usb31_pipe_RxTermination
	wire          sm_hps_usb31_txoneszeros_interconnect_i_usb31_pipe_txoneszeros;     // sm_hps:usb31_pipe_TxOnesZeros -> sm_usb31_phy:i_usb31_pipe_TxOnesZeros

	agilex_hps_intel_sundancemesa_hps_100_pcn6ita sm_hps (
		.h2f_reset                   (h2f_reset_reset),                                                    //  output,    width = 1,                      h2f_reset.reset
		.hps2fpga_clk                (hps2fpga_axi_clock_clk),                                             //   input,    width = 1,             hps2fpga_axi_clock.clk
		.hps2fpga_rst                (hps2fpga_axi_reset_reset),                                           //   input,    width = 1,             hps2fpga_axi_reset.reset
		.hps2fpga_awid               (hps2fpga_awid),                                                      //  output,    width = 4,                       hps2fpga.awid
		.hps2fpga_awaddr             (hps2fpga_awaddr),                                                    //  output,   width = 38,                               .awaddr
		.hps2fpga_awlen              (hps2fpga_awlen),                                                     //  output,    width = 8,                               .awlen
		.hps2fpga_awsize             (hps2fpga_awsize),                                                    //  output,    width = 3,                               .awsize
		.hps2fpga_awburst            (hps2fpga_awburst),                                                   //  output,    width = 2,                               .awburst
		.hps2fpga_awlock             (hps2fpga_awlock),                                                    //  output,    width = 1,                               .awlock
		.hps2fpga_awcache            (hps2fpga_awcache),                                                   //  output,    width = 4,                               .awcache
		.hps2fpga_awprot             (hps2fpga_awprot),                                                    //  output,    width = 3,                               .awprot
		.hps2fpga_awvalid            (hps2fpga_awvalid),                                                   //  output,    width = 1,                               .awvalid
		.hps2fpga_awready            (hps2fpga_awready),                                                   //   input,    width = 1,                               .awready
		.hps2fpga_wdata              (hps2fpga_wdata),                                                     //  output,  width = 128,                               .wdata
		.hps2fpga_wstrb              (hps2fpga_wstrb),                                                     //  output,   width = 16,                               .wstrb
		.hps2fpga_wlast              (hps2fpga_wlast),                                                     //  output,    width = 1,                               .wlast
		.hps2fpga_wvalid             (hps2fpga_wvalid),                                                    //  output,    width = 1,                               .wvalid
		.hps2fpga_wready             (hps2fpga_wready),                                                    //   input,    width = 1,                               .wready
		.hps2fpga_bid                (hps2fpga_bid),                                                       //   input,    width = 4,                               .bid
		.hps2fpga_bresp              (hps2fpga_bresp),                                                     //   input,    width = 2,                               .bresp
		.hps2fpga_bvalid             (hps2fpga_bvalid),                                                    //   input,    width = 1,                               .bvalid
		.hps2fpga_bready             (hps2fpga_bready),                                                    //  output,    width = 1,                               .bready
		.hps2fpga_arid               (hps2fpga_arid),                                                      //  output,    width = 4,                               .arid
		.hps2fpga_araddr             (hps2fpga_araddr),                                                    //  output,   width = 38,                               .araddr
		.hps2fpga_arlen              (hps2fpga_arlen),                                                     //  output,    width = 8,                               .arlen
		.hps2fpga_arsize             (hps2fpga_arsize),                                                    //  output,    width = 3,                               .arsize
		.hps2fpga_arburst            (hps2fpga_arburst),                                                   //  output,    width = 2,                               .arburst
		.hps2fpga_arlock             (hps2fpga_arlock),                                                    //  output,    width = 1,                               .arlock
		.hps2fpga_arcache            (hps2fpga_arcache),                                                   //  output,    width = 4,                               .arcache
		.hps2fpga_arprot             (hps2fpga_arprot),                                                    //  output,    width = 3,                               .arprot
		.hps2fpga_arvalid            (hps2fpga_arvalid),                                                   //  output,    width = 1,                               .arvalid
		.hps2fpga_arready            (hps2fpga_arready),                                                   //   input,    width = 1,                               .arready
		.hps2fpga_rid                (hps2fpga_rid),                                                       //   input,    width = 4,                               .rid
		.hps2fpga_rdata              (hps2fpga_rdata),                                                     //   input,  width = 128,                               .rdata
		.hps2fpga_rresp              (hps2fpga_rresp),                                                     //   input,    width = 2,                               .rresp
		.hps2fpga_rlast              (hps2fpga_rlast),                                                     //   input,    width = 1,                               .rlast
		.hps2fpga_rvalid             (hps2fpga_rvalid),                                                    //   input,    width = 1,                               .rvalid
		.hps2fpga_rready             (hps2fpga_rready),                                                    //  output,    width = 1,                               .rready
		.lwhps2fpga_clk              (lwhps2fpga_axi_clock_clk),                                           //   input,    width = 1,           lwhps2fpga_axi_clock.clk
		.lwhps2fpga_rst              (lwhps2fpga_axi_reset_reset),                                         //   input,    width = 1,           lwhps2fpga_axi_reset.reset
		.lwhps2fpga_awid             (lwhps2fpga_awid),                                                    //  output,    width = 4,                     lwhps2fpga.awid
		.lwhps2fpga_awaddr           (lwhps2fpga_awaddr),                                                  //  output,   width = 29,                               .awaddr
		.lwhps2fpga_awlen            (lwhps2fpga_awlen),                                                   //  output,    width = 8,                               .awlen
		.lwhps2fpga_awsize           (lwhps2fpga_awsize),                                                  //  output,    width = 3,                               .awsize
		.lwhps2fpga_awburst          (lwhps2fpga_awburst),                                                 //  output,    width = 2,                               .awburst
		.lwhps2fpga_awlock           (lwhps2fpga_awlock),                                                  //  output,    width = 1,                               .awlock
		.lwhps2fpga_awcache          (lwhps2fpga_awcache),                                                 //  output,    width = 4,                               .awcache
		.lwhps2fpga_awprot           (lwhps2fpga_awprot),                                                  //  output,    width = 3,                               .awprot
		.lwhps2fpga_awvalid          (lwhps2fpga_awvalid),                                                 //  output,    width = 1,                               .awvalid
		.lwhps2fpga_awready          (lwhps2fpga_awready),                                                 //   input,    width = 1,                               .awready
		.lwhps2fpga_wdata            (lwhps2fpga_wdata),                                                   //  output,   width = 32,                               .wdata
		.lwhps2fpga_wstrb            (lwhps2fpga_wstrb),                                                   //  output,    width = 4,                               .wstrb
		.lwhps2fpga_wlast            (lwhps2fpga_wlast),                                                   //  output,    width = 1,                               .wlast
		.lwhps2fpga_wvalid           (lwhps2fpga_wvalid),                                                  //  output,    width = 1,                               .wvalid
		.lwhps2fpga_wready           (lwhps2fpga_wready),                                                  //   input,    width = 1,                               .wready
		.lwhps2fpga_bid              (lwhps2fpga_bid),                                                     //   input,    width = 4,                               .bid
		.lwhps2fpga_bresp            (lwhps2fpga_bresp),                                                   //   input,    width = 2,                               .bresp
		.lwhps2fpga_bvalid           (lwhps2fpga_bvalid),                                                  //   input,    width = 1,                               .bvalid
		.lwhps2fpga_bready           (lwhps2fpga_bready),                                                  //  output,    width = 1,                               .bready
		.lwhps2fpga_arid             (lwhps2fpga_arid),                                                    //  output,    width = 4,                               .arid
		.lwhps2fpga_araddr           (lwhps2fpga_araddr),                                                  //  output,   width = 29,                               .araddr
		.lwhps2fpga_arlen            (lwhps2fpga_arlen),                                                   //  output,    width = 8,                               .arlen
		.lwhps2fpga_arsize           (lwhps2fpga_arsize),                                                  //  output,    width = 3,                               .arsize
		.lwhps2fpga_arburst          (lwhps2fpga_arburst),                                                 //  output,    width = 2,                               .arburst
		.lwhps2fpga_arlock           (lwhps2fpga_arlock),                                                  //  output,    width = 1,                               .arlock
		.lwhps2fpga_arcache          (lwhps2fpga_arcache),                                                 //  output,    width = 4,                               .arcache
		.lwhps2fpga_arprot           (lwhps2fpga_arprot),                                                  //  output,    width = 3,                               .arprot
		.lwhps2fpga_arvalid          (lwhps2fpga_arvalid),                                                 //  output,    width = 1,                               .arvalid
		.lwhps2fpga_arready          (lwhps2fpga_arready),                                                 //   input,    width = 1,                               .arready
		.lwhps2fpga_rid              (lwhps2fpga_rid),                                                     //   input,    width = 4,                               .rid
		.lwhps2fpga_rdata            (lwhps2fpga_rdata),                                                   //   input,   width = 32,                               .rdata
		.lwhps2fpga_rresp            (lwhps2fpga_rresp),                                                   //   input,    width = 2,                               .rresp
		.lwhps2fpga_rlast            (lwhps2fpga_rlast),                                                   //   input,    width = 1,                               .rlast
		.lwhps2fpga_rvalid           (lwhps2fpga_rvalid),                                                  //   input,    width = 1,                               .rvalid
		.lwhps2fpga_rready           (lwhps2fpga_rready),                                                  //  output,    width = 1,                               .rready
		.emac2_rst_clk_app_n_o       (emac2_app_rst_reset_n),                                              //  output,    width = 1,                  emac2_app_rst.reset_n
		.h2f_pending_rst_req_n       (h2f_warm_reset_handshake_reset_req),                                 //  output,    width = 1,       h2f_warm_reset_handshake.reset_req
		.f2h_pending_rst_ack_n       (h2f_warm_reset_handshake_reset_ack),                                 //   input,    width = 1,                               .reset_ack
		.hps_osc_clk                 (hps_io_hps_osc_clk),                                                 //   input,    width = 1,                         hps_io.hps_osc_clk
		.sdmmc_data0                 (hps_io_sdmmc_data0),                                                 //   inout,    width = 1,                               .sdmmc_data0
		.sdmmc_data1                 (hps_io_sdmmc_data1),                                                 //   inout,    width = 1,                               .sdmmc_data1
		.sdmmc_cclk                  (hps_io_sdmmc_cclk),                                                  //  output,    width = 1,                               .sdmmc_cclk
		.sdmmc_data2                 (hps_io_sdmmc_data2),                                                 //   inout,    width = 1,                               .sdmmc_data2
		.sdmmc_data3                 (hps_io_sdmmc_data3),                                                 //   inout,    width = 1,                               .sdmmc_data3
		.sdmmc_cmd                   (hps_io_sdmmc_cmd),                                                   //   inout,    width = 1,                               .sdmmc_cmd
		.usb1_clk                    (hps_io_usb1_clk),                                                    //   input,    width = 1,                               .usb1_clk
		.usb1_stp                    (hps_io_usb1_stp),                                                    //  output,    width = 1,                               .usb1_stp
		.usb1_dir                    (hps_io_usb1_dir),                                                    //   input,    width = 1,                               .usb1_dir
		.usb1_data0                  (hps_io_usb1_data0),                                                  //   inout,    width = 1,                               .usb1_data0
		.usb1_data1                  (hps_io_usb1_data1),                                                  //   inout,    width = 1,                               .usb1_data1
		.usb1_nxt                    (hps_io_usb1_nxt),                                                    //   input,    width = 1,                               .usb1_nxt
		.usb1_data2                  (hps_io_usb1_data2),                                                  //   inout,    width = 1,                               .usb1_data2
		.usb1_data3                  (hps_io_usb1_data3),                                                  //   inout,    width = 1,                               .usb1_data3
		.usb1_data4                  (hps_io_usb1_data4),                                                  //   inout,    width = 1,                               .usb1_data4
		.usb1_data5                  (hps_io_usb1_data5),                                                  //   inout,    width = 1,                               .usb1_data5
		.usb1_data6                  (hps_io_usb1_data6),                                                  //   inout,    width = 1,                               .usb1_data6
		.usb1_data7                  (hps_io_usb1_data7),                                                  //   inout,    width = 1,                               .usb1_data7
		.emac2_tx_clk                (hps_io_emac2_tx_clk),                                                //  output,    width = 1,                               .emac2_tx_clk
		.emac2_tx_ctl                (hps_io_emac2_tx_ctl),                                                //  output,    width = 1,                               .emac2_tx_ctl
		.emac2_rx_clk                (hps_io_emac2_rx_clk),                                                //   input,    width = 1,                               .emac2_rx_clk
		.emac2_rx_ctl                (hps_io_emac2_rx_ctl),                                                //   input,    width = 1,                               .emac2_rx_ctl
		.emac2_txd0                  (hps_io_emac2_txd0),                                                  //  output,    width = 1,                               .emac2_txd0
		.emac2_txd1                  (hps_io_emac2_txd1),                                                  //  output,    width = 1,                               .emac2_txd1
		.emac2_rxd0                  (hps_io_emac2_rxd0),                                                  //   input,    width = 1,                               .emac2_rxd0
		.emac2_rxd1                  (hps_io_emac2_rxd1),                                                  //   input,    width = 1,                               .emac2_rxd1
		.emac2_txd2                  (hps_io_emac2_txd2),                                                  //  output,    width = 1,                               .emac2_txd2
		.emac2_txd3                  (hps_io_emac2_txd3),                                                  //  output,    width = 1,                               .emac2_txd3
		.emac2_rxd2                  (hps_io_emac2_rxd2),                                                  //   input,    width = 1,                               .emac2_rxd2
		.emac2_rxd3                  (hps_io_emac2_rxd3),                                                  //   input,    width = 1,                               .emac2_rxd3
		.mdio2_mdio                  (hps_io_mdio2_mdio),                                                  //   inout,    width = 1,                               .mdio2_mdio
		.mdio2_mdc                   (hps_io_mdio2_mdc),                                                   //  output,    width = 1,                               .mdio2_mdc
		.uart0_io_tx                 (hps_io_uart0_tx),                                                    //  output,    width = 1,                               .uart0_tx
		.uart0_io_rx                 (hps_io_uart0_rx),                                                    //   input,    width = 1,                               .uart0_rx
		.i2c0_sda                    (hps_io_i2c0_sda),                                                    //   inout,    width = 1,                               .i2c0_sda
		.i2c0_scl                    (hps_io_i2c0_scl),                                                    //   inout,    width = 1,                               .i2c0_scl
		.gpio0                       (hps_io_gpio0),                                                       //   inout,    width = 1,                               .gpio0
		.gpio1                       (hps_io_gpio1),                                                       //   inout,    width = 1,                               .gpio1
		.gpio8                       (hps_io_gpio8),                                                       //   inout,    width = 1,                               .gpio8
		.gpio9                       (hps_io_gpio9),                                                       //   inout,    width = 1,                               .gpio9
		.gpio10                      (hps_io_gpio10),                                                      //   inout,    width = 1,                               .gpio10
		.gpio11                      (hps_io_gpio11),                                                      //   inout,    width = 1,                               .gpio11
		.gpio28                      (hps_io_gpio28),                                                      //   inout,    width = 1,                               .gpio28
		.usb1_usb31_vbus_det         (usb31_io_vbus_det),                                                  //   input,    width = 1,                       usb31_io.vbus_det
		.usb1_usb31_flt_bar          (usb31_io_flt_bar),                                                   //   input,    width = 1,                               .flt_bar
		.usb1_usb31_usb_ctrl         (usb31_io_usb_ctrl),                                                  //  output,    width = 2,                               .usb_ctrl
		.usb1_usb31_id               (usb31_io_usb31_id),                                                  //   input,    width = 1,                               .usb31_id
		.usb31_pipe_pclk             (sm_usb31_phy_o_usb31_pipe_clk_clk),                                  //   input,    width = 1,         usb31_clk_interconnect.clk
		.usb31_pipe_RxValid          (sm_usb31_phy_o_usb31_pipe_rxvalid_o_usb31_pipe_rxvalid),             //   input,    width = 1,     usb31_rxvalid_interconnect.o_usb31_pipe_RxValid
		.usb31_pipe_RxData           (sm_usb31_phy_o_usb31_pipe_rxdata_o_usb31_pipe_rxdata),               //   input,   width = 16,      usb31_rxdata_interconnect.o_usb31_pipe_RxData
		.usb31_pipe_RxDataK          (sm_usb31_phy_o_usb31_pipe_rxdatak_o_usb31_pipe_rxdatak),             //   input,    width = 2,     usb31_rxdatak_interconnect.o_usb31_pipe_RxDataK
		.usb31_pipe_PhyStatus        (sm_usb31_phy_o_usb31_pipe_phystatus_o_usb31_pipe_phystatus),         //   input,    width = 1,   usb31_phystatus_interconnect.o_usb31_pipe_PhyStatus
		.usb31_pipe_RxElecIdle       (sm_usb31_phy_o_usb31_pipe_rxelecidle_o_usb31_pipe_rxelecidle),       //   input,    width = 1,  usb31_rxelecidle_interconnect.o_usb31_pipe_RxElecidle
		.usb31_pipe_RxStatus         (sm_usb31_phy_o_usb31_pipe_rxstatus_o_usb31_pipe_rxstatus),           //   input,    width = 3,    usb31_rxstatus_interconnect.o_usb31_pipe_Rxstatus
		.usb31_pipe_reset_n          (sm_hps_usb31_rst_interconnect_i_usb31_pipe_reset_n),                 //  output,    width = 1,         usb31_rst_interconnect.i_usb31_pipe_reset_n
		.usb31_pipe_TxData           (sm_hps_usb31_txdata_interconnect_i_usb31_pipe_txdata),               //  output,   width = 16,      usb31_txdata_interconnect.i_usb31_pipe_TxData
		.usb31_pipe_TxDataK          (sm_hps_usb31_txdatak_interconnect_i_usb31_pipe_txdatak),             //  output,    width = 2,     usb31_txdatak_interconnect.i_usb31_pipe_TxDataK
		.usb31_pipe_RxEqTrain        (sm_hps_usb31_rxeqtrain_interconnect_i_usb31_pipe_rxeqtrain),         //  output,    width = 1,   usb31_rxeqtrain_interconnect.i_usb31_pipe_RxEqTrain
		.usb31_pipe_ElasBufferMode   (sm_hps_usb31_elasbuf_interconnect_i_usb31_pipe_elasbuffermode),      //  output,    width = 1,     usb31_elasbuf_interconnect.i_usb31_pipe_ElasBufferMode
		.usb31_pipe_TxDetectRxLoopbk (sm_hps_usb31_loopback_interconnect_i_usb31_pipe_txdetectrxloopback), //  output,    width = 1,    usb31_loopback_interconnect.i_usb31_pipe_TxDetectRxLoopback
		.usb31_pipe_TxElecIdle       (sm_hps_usb31_txelecidle_interconnect_i_usb31_pipe_txelecidle),       //  output,    width = 1,  usb31_txelecidle_interconnect.i_usb31_pipe_TxElecidle
		.usb31_pipe_RxPolarity       (sm_hps_usb31_rxpolarity_interconnect_i_usb31_pipe_rxpolarity),       //  output,    width = 1,  usb31_rxpolarity_interconnect.i_usb31_pipe_RxPolarity
		.usb31_pipe_PowerDown        (sm_hps_usb31_pwrdown_interconnect_i_usb31_pipe_powerdown),           //  output,    width = 4,     usb31_pwrdown_interconnect.i_usb31_pipe_PowerDown
		.usb31_pipe_Rate             (sm_hps_usb31_piperate_interconnect_i_usb31_pipe_txdeemphasis),       //  output,    width = 2,    usb31_piperate_interconnect.i_usb31_pipe_TxDeEmphasis
		.usb31_pipe_RxTermination    (sm_hps_usb31_rxterm_interconnect_i_usb31_pipe_rxtermination),        //  output,    width = 1,      usb31_rxterm_interconnect.i_usb31_pipe_RxTermination
		.usb31_pipe_TxOnesZeros      (sm_hps_usb31_txoneszeros_interconnect_i_usb31_pipe_txoneszeros),     //  output,    width = 1, usb31_txoneszeros_interconnect.i_usb31_pipe_TxOnesZeros
		.hps2mpfe_ccu_clk            (sm_hps_hps_ccu_interconnect_clk_clk),                                //  output,    width = 1,       hps_ccu_interconnect_clk.clk
		.hps2mpfe_ccu_rst            (sm_hps_hps_ccu_interconnect_rst_reset),                              //  output,    width = 1,       hps_ccu_interconnect_rst.reset
		.hps2mpfe_dmi0_araddr        (sm_hps_hps_dmi0_interconnect_araddr),                                //  output,   width = 44,          hps_dmi0_interconnect.araddr
		.hps2mpfe_dmi0_arburst       (sm_hps_hps_dmi0_interconnect_arburst),                               //  output,    width = 2,                               .arburst
		.hps2mpfe_dmi0_arcache       (sm_hps_hps_dmi0_interconnect_arcache),                               //  output,    width = 4,                               .arcache
		.hps2mpfe_dmi0_arid          (sm_hps_hps_dmi0_interconnect_arid),                                  //  output,   width = 10,                               .arid
		.hps2mpfe_dmi0_arlen         (sm_hps_hps_dmi0_interconnect_arlen),                                 //  output,    width = 8,                               .arlen
		.hps2mpfe_dmi0_arlock        (sm_hps_hps_dmi0_interconnect_arlock),                                //  output,    width = 1,                               .arlock
		.hps2mpfe_dmi0_arprot        (sm_hps_hps_dmi0_interconnect_arprot),                                //  output,    width = 3,                               .arprot
		.hps2mpfe_dmi0_arqos         (sm_hps_hps_dmi0_interconnect_arqos),                                 //  output,    width = 4,                               .arqos
		.hps2mpfe_dmi0_arready       (sm_hps_hps_dmi0_interconnect_arready),                               //   input,    width = 1,                               .arready
		.hps2mpfe_dmi0_arsize        (sm_hps_hps_dmi0_interconnect_arsize),                                //  output,    width = 3,                               .arsize
		.hps2mpfe_dmi0_aruser        (sm_hps_hps_dmi0_interconnect_aruser),                                //  output,    width = 8,                               .aruser
		.hps2mpfe_dmi0_arvalid       (sm_hps_hps_dmi0_interconnect_arvalid),                               //  output,    width = 1,                               .arvalid
		.hps2mpfe_dmi0_awaddr        (sm_hps_hps_dmi0_interconnect_awaddr),                                //  output,   width = 44,                               .awaddr
		.hps2mpfe_dmi0_awburst       (sm_hps_hps_dmi0_interconnect_awburst),                               //  output,    width = 2,                               .awburst
		.hps2mpfe_dmi0_awcache       (sm_hps_hps_dmi0_interconnect_awcache),                               //  output,    width = 4,                               .awcache
		.hps2mpfe_dmi0_awid          (sm_hps_hps_dmi0_interconnect_awid),                                  //  output,   width = 10,                               .awid
		.hps2mpfe_dmi0_awlen         (sm_hps_hps_dmi0_interconnect_awlen),                                 //  output,    width = 8,                               .awlen
		.hps2mpfe_dmi0_awlock        (sm_hps_hps_dmi0_interconnect_awlock),                                //  output,    width = 1,                               .awlock
		.hps2mpfe_dmi0_awprot        (sm_hps_hps_dmi0_interconnect_awprot),                                //  output,    width = 3,                               .awprot
		.hps2mpfe_dmi0_awqos         (sm_hps_hps_dmi0_interconnect_awqos),                                 //  output,    width = 4,                               .awqos
		.hps2mpfe_dmi0_awready       (sm_hps_hps_dmi0_interconnect_awready),                               //   input,    width = 1,                               .awready
		.hps2mpfe_dmi0_awsize        (sm_hps_hps_dmi0_interconnect_awsize),                                //  output,    width = 3,                               .awsize
		.hps2mpfe_dmi0_awuser        (sm_hps_hps_dmi0_interconnect_awuser),                                //  output,    width = 8,                               .awuser
		.hps2mpfe_dmi0_awvalid       (sm_hps_hps_dmi0_interconnect_awvalid),                               //  output,    width = 1,                               .awvalid
		.hps2mpfe_dmi0_bid           (sm_hps_hps_dmi0_interconnect_bid),                                   //   input,   width = 10,                               .bid
		.hps2mpfe_dmi0_bready        (sm_hps_hps_dmi0_interconnect_bready),                                //  output,    width = 1,                               .bready
		.hps2mpfe_dmi0_bresp         (sm_hps_hps_dmi0_interconnect_bresp),                                 //   input,    width = 2,                               .bresp
		.hps2mpfe_dmi0_bvalid        (sm_hps_hps_dmi0_interconnect_bvalid),                                //   input,    width = 1,                               .bvalid
		.hps2mpfe_dmi0_rdata         (sm_hps_hps_dmi0_interconnect_rdata),                                 //   input,  width = 256,                               .rdata
		.hps2mpfe_dmi0_rid           (sm_hps_hps_dmi0_interconnect_rid),                                   //   input,   width = 10,                               .rid
		.hps2mpfe_dmi0_rlast         (sm_hps_hps_dmi0_interconnect_rlast),                                 //   input,    width = 1,                               .rlast
		.hps2mpfe_dmi0_rready        (sm_hps_hps_dmi0_interconnect_rready),                                //  output,    width = 1,                               .rready
		.hps2mpfe_dmi0_rresp         (sm_hps_hps_dmi0_interconnect_rresp),                                 //   input,    width = 2,                               .rresp
		.hps2mpfe_dmi0_rvalid        (sm_hps_hps_dmi0_interconnect_rvalid),                                //   input,    width = 1,                               .rvalid
		.hps2mpfe_dmi0_wdata         (sm_hps_hps_dmi0_interconnect_wdata),                                 //  output,  width = 256,                               .wdata
		.hps2mpfe_dmi0_wlast         (sm_hps_hps_dmi0_interconnect_wlast),                                 //  output,    width = 1,                               .wlast
		.hps2mpfe_dmi0_wready        (sm_hps_hps_dmi0_interconnect_wready),                                //   input,    width = 1,                               .wready
		.hps2mpfe_dmi0_wstrb         (sm_hps_hps_dmi0_interconnect_wstrb),                                 //  output,   width = 32,                               .wstrb
		.hps2mpfe_dmi0_wvalid        (sm_hps_hps_dmi0_interconnect_wvalid),                                //  output,    width = 1,                               .wvalid
		.hps2mpfe_dmi1_araddr        (sm_hps_hps_dmi1_interconnect_araddr),                                //  output,   width = 44,          hps_dmi1_interconnect.araddr
		.hps2mpfe_dmi1_arburst       (sm_hps_hps_dmi1_interconnect_arburst),                               //  output,    width = 2,                               .arburst
		.hps2mpfe_dmi1_arcache       (sm_hps_hps_dmi1_interconnect_arcache),                               //  output,    width = 4,                               .arcache
		.hps2mpfe_dmi1_arid          (sm_hps_hps_dmi1_interconnect_arid),                                  //  output,   width = 10,                               .arid
		.hps2mpfe_dmi1_arlen         (sm_hps_hps_dmi1_interconnect_arlen),                                 //  output,    width = 8,                               .arlen
		.hps2mpfe_dmi1_arlock        (sm_hps_hps_dmi1_interconnect_arlock),                                //  output,    width = 1,                               .arlock
		.hps2mpfe_dmi1_arprot        (sm_hps_hps_dmi1_interconnect_arprot),                                //  output,    width = 3,                               .arprot
		.hps2mpfe_dmi1_arqos         (sm_hps_hps_dmi1_interconnect_arqos),                                 //  output,    width = 4,                               .arqos
		.hps2mpfe_dmi1_arready       (sm_hps_hps_dmi1_interconnect_arready),                               //   input,    width = 1,                               .arready
		.hps2mpfe_dmi1_arsize        (sm_hps_hps_dmi1_interconnect_arsize),                                //  output,    width = 3,                               .arsize
		.hps2mpfe_dmi1_aruser        (sm_hps_hps_dmi1_interconnect_aruser),                                //  output,    width = 8,                               .aruser
		.hps2mpfe_dmi1_arvalid       (sm_hps_hps_dmi1_interconnect_arvalid),                               //  output,    width = 1,                               .arvalid
		.hps2mpfe_dmi1_awaddr        (sm_hps_hps_dmi1_interconnect_awaddr),                                //  output,   width = 44,                               .awaddr
		.hps2mpfe_dmi1_awburst       (sm_hps_hps_dmi1_interconnect_awburst),                               //  output,    width = 2,                               .awburst
		.hps2mpfe_dmi1_awcache       (sm_hps_hps_dmi1_interconnect_awcache),                               //  output,    width = 4,                               .awcache
		.hps2mpfe_dmi1_awid          (sm_hps_hps_dmi1_interconnect_awid),                                  //  output,   width = 10,                               .awid
		.hps2mpfe_dmi1_awlen         (sm_hps_hps_dmi1_interconnect_awlen),                                 //  output,    width = 8,                               .awlen
		.hps2mpfe_dmi1_awlock        (sm_hps_hps_dmi1_interconnect_awlock),                                //  output,    width = 1,                               .awlock
		.hps2mpfe_dmi1_awprot        (sm_hps_hps_dmi1_interconnect_awprot),                                //  output,    width = 3,                               .awprot
		.hps2mpfe_dmi1_awqos         (sm_hps_hps_dmi1_interconnect_awqos),                                 //  output,    width = 4,                               .awqos
		.hps2mpfe_dmi1_awready       (sm_hps_hps_dmi1_interconnect_awready),                               //   input,    width = 1,                               .awready
		.hps2mpfe_dmi1_awsize        (sm_hps_hps_dmi1_interconnect_awsize),                                //  output,    width = 3,                               .awsize
		.hps2mpfe_dmi1_awuser        (sm_hps_hps_dmi1_interconnect_awuser),                                //  output,    width = 8,                               .awuser
		.hps2mpfe_dmi1_awvalid       (sm_hps_hps_dmi1_interconnect_awvalid),                               //  output,    width = 1,                               .awvalid
		.hps2mpfe_dmi1_bid           (sm_hps_hps_dmi1_interconnect_bid),                                   //   input,   width = 10,                               .bid
		.hps2mpfe_dmi1_bready        (sm_hps_hps_dmi1_interconnect_bready),                                //  output,    width = 1,                               .bready
		.hps2mpfe_dmi1_bresp         (sm_hps_hps_dmi1_interconnect_bresp),                                 //   input,    width = 2,                               .bresp
		.hps2mpfe_dmi1_bvalid        (sm_hps_hps_dmi1_interconnect_bvalid),                                //   input,    width = 1,                               .bvalid
		.hps2mpfe_dmi1_rdata         (sm_hps_hps_dmi1_interconnect_rdata),                                 //   input,  width = 256,                               .rdata
		.hps2mpfe_dmi1_rid           (sm_hps_hps_dmi1_interconnect_rid),                                   //   input,   width = 10,                               .rid
		.hps2mpfe_dmi1_rlast         (sm_hps_hps_dmi1_interconnect_rlast),                                 //   input,    width = 1,                               .rlast
		.hps2mpfe_dmi1_rready        (sm_hps_hps_dmi1_interconnect_rready),                                //  output,    width = 1,                               .rready
		.hps2mpfe_dmi1_rresp         (sm_hps_hps_dmi1_interconnect_rresp),                                 //   input,    width = 2,                               .rresp
		.hps2mpfe_dmi1_rvalid        (sm_hps_hps_dmi1_interconnect_rvalid),                                //   input,    width = 1,                               .rvalid
		.hps2mpfe_dmi1_wdata         (sm_hps_hps_dmi1_interconnect_wdata),                                 //  output,  width = 256,                               .wdata
		.hps2mpfe_dmi1_wlast         (sm_hps_hps_dmi1_interconnect_wlast),                                 //  output,    width = 1,                               .wlast
		.hps2mpfe_dmi1_wready        (sm_hps_hps_dmi1_interconnect_wready),                                //   input,    width = 1,                               .wready
		.hps2mpfe_dmi1_wstrb         (sm_hps_hps_dmi1_interconnect_wstrb),                                 //  output,   width = 32,                               .wstrb
		.hps2mpfe_dmi1_wvalid        (sm_hps_hps_dmi1_interconnect_wvalid),                                //  output,    width = 1,                               .wvalid
		.hps2mpfe_csr_araddr         (sm_hps_hps_s2mpfe_interconnect_araddr),                              //  output,   width = 44,        hps_s2mpfe_interconnect.araddr
		.hps2mpfe_csr_arburst        (sm_hps_hps_s2mpfe_interconnect_arburst),                             //  output,    width = 2,                               .arburst
		.hps2mpfe_csr_arcache        (sm_hps_hps_s2mpfe_interconnect_arcache),                             //  output,    width = 4,                               .arcache
		.hps2mpfe_csr_arid           (sm_hps_hps_s2mpfe_interconnect_arid),                                //  output,   width = 10,                               .arid
		.hps2mpfe_csr_arlen          (sm_hps_hps_s2mpfe_interconnect_arlen),                               //  output,    width = 8,                               .arlen
		.hps2mpfe_csr_arlock         (sm_hps_hps_s2mpfe_interconnect_arlock),                              //  output,    width = 1,                               .arlock
		.hps2mpfe_csr_arprot         (sm_hps_hps_s2mpfe_interconnect_arprot),                              //  output,    width = 3,                               .arprot
		.hps2mpfe_csr_arready        (sm_hps_hps_s2mpfe_interconnect_arready),                             //   input,    width = 1,                               .arready
		.hps2mpfe_csr_arsize         (sm_hps_hps_s2mpfe_interconnect_arsize),                              //  output,    width = 3,                               .arsize
		.hps2mpfe_csr_aruser         (sm_hps_hps_s2mpfe_interconnect_aruser),                              //  output,    width = 8,                               .aruser
		.hps2mpfe_csr_arvalid        (sm_hps_hps_s2mpfe_interconnect_arvalid),                             //  output,    width = 1,                               .arvalid
		.hps2mpfe_csr_awaddr         (sm_hps_hps_s2mpfe_interconnect_awaddr),                              //  output,   width = 44,                               .awaddr
		.hps2mpfe_csr_awburst        (sm_hps_hps_s2mpfe_interconnect_awburst),                             //  output,    width = 2,                               .awburst
		.hps2mpfe_csr_awcache        (sm_hps_hps_s2mpfe_interconnect_awcache),                             //  output,    width = 4,                               .awcache
		.hps2mpfe_csr_awid           (sm_hps_hps_s2mpfe_interconnect_awid),                                //  output,   width = 10,                               .awid
		.hps2mpfe_csr_awlen          (sm_hps_hps_s2mpfe_interconnect_awlen),                               //  output,    width = 8,                               .awlen
		.hps2mpfe_csr_awlock         (sm_hps_hps_s2mpfe_interconnect_awlock),                              //  output,    width = 1,                               .awlock
		.hps2mpfe_csr_awprot         (sm_hps_hps_s2mpfe_interconnect_awprot),                              //  output,    width = 3,                               .awprot
		.hps2mpfe_csr_awready        (sm_hps_hps_s2mpfe_interconnect_awready),                             //   input,    width = 1,                               .awready
		.hps2mpfe_csr_awsize         (sm_hps_hps_s2mpfe_interconnect_awsize),                              //  output,    width = 3,                               .awsize
		.hps2mpfe_csr_awuser         (sm_hps_hps_s2mpfe_interconnect_awuser),                              //  output,    width = 8,                               .awuser
		.hps2mpfe_csr_awvalid        (sm_hps_hps_s2mpfe_interconnect_awvalid),                             //  output,    width = 1,                               .awvalid
		.hps2mpfe_csr_bid            (sm_hps_hps_s2mpfe_interconnect_bid),                                 //   input,   width = 10,                               .bid
		.hps2mpfe_csr_bready         (sm_hps_hps_s2mpfe_interconnect_bready),                              //  output,    width = 1,                               .bready
		.hps2mpfe_csr_bresp          (sm_hps_hps_s2mpfe_interconnect_bresp),                               //   input,    width = 2,                               .bresp
		.hps2mpfe_csr_bvalid         (sm_hps_hps_s2mpfe_interconnect_bvalid),                              //   input,    width = 1,                               .bvalid
		.hps2mpfe_csr_rdata          (sm_hps_hps_s2mpfe_interconnect_rdata),                               //   input,   width = 64,                               .rdata
		.hps2mpfe_csr_rid            (sm_hps_hps_s2mpfe_interconnect_rid),                                 //   input,   width = 10,                               .rid
		.hps2mpfe_csr_rlast          (sm_hps_hps_s2mpfe_interconnect_rlast),                               //   input,    width = 1,                               .rlast
		.hps2mpfe_csr_rready         (sm_hps_hps_s2mpfe_interconnect_rready),                              //  output,    width = 1,                               .rready
		.hps2mpfe_csr_rresp          (sm_hps_hps_s2mpfe_interconnect_rresp),                               //   input,    width = 2,                               .rresp
		.hps2mpfe_csr_rvalid         (sm_hps_hps_s2mpfe_interconnect_rvalid),                              //   input,    width = 1,                               .rvalid
		.hps2mpfe_csr_wdata          (sm_hps_hps_s2mpfe_interconnect_wdata),                               //  output,   width = 64,                               .wdata
		.hps2mpfe_csr_wlast          (sm_hps_hps_s2mpfe_interconnect_wlast),                               //  output,    width = 1,                               .wlast
		.hps2mpfe_csr_wready         (sm_hps_hps_s2mpfe_interconnect_wready),                              //   input,    width = 1,                               .wready
		.hps2mpfe_csr_wstrb          (sm_hps_hps_s2mpfe_interconnect_wstrb),                               //  output,    width = 8,                               .wstrb
		.hps2mpfe_csr_wvalid         (sm_hps_hps_s2mpfe_interconnect_wvalid),                              //  output,    width = 1,                               .wvalid
		.fpga2sdram_bridge_rst_n     (sm_hps_hps2sdram_interconnect_reset_n),                              //  output,    width = 1,         hps2sdram_interconnect.reset_n
		.fpga2sdram_bridge_ack       (sm_mpfe_sdram2hps_interconnect_ack),                                 //   input,    width = 1,                               .ack
		.fpga2sdram_bridge_req       (sm_hps_hps2sdram_interconnect_req),                                  //  output,    width = 1,                               .req
		.fpga2sdram_tbu_pmu_irpt     (sm_mpfe_sdram2hps_interconnect_tbu_pmu),                             //   input,    width = 1,                               .tbu_pmu
		.fpga2sdram_tbu_ras_irpt     (sm_mpfe_sdram2hps_interconnect_tbu_ras),                             //   input,    width = 1,                               .tbu_ras
		.f2h_fpga_irq63              (fpga2hps_interrupt_irq),                                             //   input,   width = 63,             fpga2hps_interrupt.irq
		.h2emif_interconnect_axi_rst ()                                                                    //  output,    width = 1,    h2emif_interconnect_axi_rst.reset_n
	);

	agilex_hps_intel_usbphy_gts_100_mk4aksi sm_usb31_phy (
		.i_pma_cpu_clk                   (usb31_phy_pma_cpu_clk_clk),                                          //   input,   width = 1,                   i_pma_cpu_clk.clk
		.i_refclk_p                      (usb31_phy_refclk_p_clk),                                             //   input,   width = 1,                      i_refclk_p.clk
		.i_refclk_n                      (usb31_phy_refclk_n_clk),                                             //   input,   width = 1,                      i_refclk_n.clk
		.i_rx_serial_n                   (usb31_phy_rx_serial_n_i_rx_serial_n),                                //   input,   width = 1,                   i_rx_serial_n.i_rx_serial_n
		.i_rx_serial_p                   (usb31_phy_rx_serial_p_i_rx_serial_p),                                //   input,   width = 1,                   i_rx_serial_p.i_rx_serial_p
		.o_tx_serial_n                   (usb31_phy_tx_serial_n_o_tx_serial_n),                                //  output,   width = 1,                   o_tx_serial_n.o_tx_serial_n
		.o_tx_serial_p                   (usb31_phy_tx_serial_p_o_tx_serial_p),                                //  output,   width = 1,                   o_tx_serial_p.o_tx_serial_p
		.o_usb31_pipe_clk                (sm_usb31_phy_o_usb31_pipe_clk_clk),                                  //  output,   width = 1,                o_usb31_pipe_clk.clk
		.i_usb31_pipe_reset_n            (sm_hps_usb31_rst_interconnect_i_usb31_pipe_reset_n),                 //   input,   width = 1,            i_usb31_pipe_reset_n.i_usb31_pipe_reset_n
		.i_usb31_pipe_PowerDown          (sm_hps_usb31_pwrdown_interconnect_i_usb31_pipe_powerdown),           //   input,   width = 4,          i_usb31_pipe_PowerDown.i_usb31_pipe_PowerDown
		.i_usb31_pipe_ElasBufferMode     (sm_hps_usb31_elasbuf_interconnect_i_usb31_pipe_elasbuffermode),      //   input,   width = 1,     i_usb31_pipe_ElasBufferMode.i_usb31_pipe_ElasBufferMode
		.i_usb31_pipe_Rate               (),                                                                   //   input,   width = 3,               i_usb31_pipe_Rate.i_usb31_pipe_Rate
		.i_usb31_pipe_TxDetectRxLoopback (sm_hps_usb31_loopback_interconnect_i_usb31_pipe_txdetectrxloopback), //   input,   width = 1, i_usb31_pipe_TxDetectRxLoopback.i_usb31_pipe_TxDetectRxLoopback
		.i_usb31_pipe_TxElecidle         (sm_hps_usb31_txelecidle_interconnect_i_usb31_pipe_txelecidle),       //   input,   width = 1,         i_usb31_pipe_TxElecidle.i_usb31_pipe_TxElecidle
		.i_usb31_pipe_TxOnesZeros        (sm_hps_usb31_txoneszeros_interconnect_i_usb31_pipe_txoneszeros),     //   input,   width = 1,        i_usb31_pipe_TxOnesZeros.i_usb31_pipe_TxOnesZeros
		.i_usb31_pipe_RxTermination      (sm_hps_usb31_rxterm_interconnect_i_usb31_pipe_rxtermination),        //   input,   width = 1,      i_usb31_pipe_RxTermination.i_usb31_pipe_RxTermination
		.i_usb31_pipe_RxEqTrain          (sm_hps_usb31_rxeqtrain_interconnect_i_usb31_pipe_rxeqtrain),         //   input,   width = 1,          i_usb31_pipe_RxEqTrain.i_usb31_pipe_RxEqTrain
		.i_usb31_pipe_RxPolarity         (sm_hps_usb31_rxpolarity_interconnect_i_usb31_pipe_rxpolarity),       //   input,   width = 1,         i_usb31_pipe_RxPolarity.i_usb31_pipe_RxPolarity
		.i_usb31_pipe_TxDeEmphasis       (sm_hps_usb31_piperate_interconnect_i_usb31_pipe_txdeemphasis),       //   input,   width = 2,       i_usb31_pipe_TxDeEmphasis.i_usb31_pipe_TxDeEmphasis
		.o_usb31_pipe_PhyStatus          (sm_usb31_phy_o_usb31_pipe_phystatus_o_usb31_pipe_phystatus),         //  output,   width = 1,          o_usb31_pipe_PhyStatus.o_usb31_pipe_PhyStatus
		.o_usb31_pipe_RxElecidle         (sm_usb31_phy_o_usb31_pipe_rxelecidle_o_usb31_pipe_rxelecidle),       //  output,   width = 1,         o_usb31_pipe_RxElecidle.o_usb31_pipe_RxElecidle
		.o_usb31_pipe_Rxstatus           (sm_usb31_phy_o_usb31_pipe_rxstatus_o_usb31_pipe_rxstatus),           //  output,   width = 3,           o_usb31_pipe_Rxstatus.o_usb31_pipe_Rxstatus
		.o_usb31_pipe_RxData             (sm_usb31_phy_o_usb31_pipe_rxdata_o_usb31_pipe_rxdata),               //  output,  width = 16,             o_usb31_pipe_RxData.o_usb31_pipe_RxData
		.o_usb31_pipe_RxDataK            (sm_usb31_phy_o_usb31_pipe_rxdatak_o_usb31_pipe_rxdatak),             //  output,   width = 2,            o_usb31_pipe_RxDataK.o_usb31_pipe_RxDataK
		.o_usb31_pipe_RxValid            (sm_usb31_phy_o_usb31_pipe_rxvalid_o_usb31_pipe_rxvalid),             //  output,   width = 1,            o_usb31_pipe_RxValid.o_usb31_pipe_RxValid
		.i_usb31_pipe_TxData             (sm_hps_usb31_txdata_interconnect_i_usb31_pipe_txdata),               //   input,  width = 16,             i_usb31_pipe_TxData.i_usb31_pipe_TxData
		.i_usb31_pipe_TxDataK            (sm_hps_usb31_txdatak_interconnect_i_usb31_pipe_txdatak),             //   input,   width = 2,            i_usb31_pipe_TxDataK.i_usb31_pipe_TxDataK
		.i_reconfig_reset                (usb31_phy_reconfig_rst_reset),                                       //   input,   width = 1,                i_reconfig_reset.reset
		.i_reconfig_clk                  (usb31_phy_reconfig_clk_clk),                                         //   input,   width = 1,                  i_reconfig_clk.clk
		.i_reconfig_address              (usb31_phy_reconfig_slave_address),                                   //   input,  width = 21,                  reconfig_slave.address
		.i_reconfig_byteenable           (usb31_phy_reconfig_slave_byteenable),                                //   input,   width = 4,                                .byteenable
		.o_reconfig_readdatavalid        (usb31_phy_reconfig_slave_readdatavalid),                             //  output,   width = 1,                                .readdatavalid
		.i_reconfig_read                 (usb31_phy_reconfig_slave_read),                                      //   input,   width = 1,                                .read
		.i_reconfig_write                (usb31_phy_reconfig_slave_write),                                     //   input,   width = 1,                                .write
		.o_reconfig_readdata             (usb31_phy_reconfig_slave_readdata),                                  //  output,  width = 32,                                .readdata
		.i_reconfig_writedata            (usb31_phy_reconfig_slave_writedata),                                 //   input,  width = 32,                                .writedata
		.o_reconfig_waitrequest          (usb31_phy_reconfig_slave_waitrequest)                                //  output,   width = 1,                                .waitrequest
	);

	agilex_hps_intel_sundancemesa_mpfe_100_za3cssq sm_mpfe (
		.f2sdram_clk           (f2sdram_axi_clock_clk),                  //   input,    width = 1,         f2sdram_axi_clock.clk
		.f2sdram_rst           (f2sdram_axi_reset_reset),                //   input,    width = 1,         f2sdram_axi_reset.reset
		.f2sdram_araddr        (f2sdram_araddr),                         //   input,   width = 32,                   f2sdram.araddr
		.f2sdram_arburst       (f2sdram_arburst),                        //   input,    width = 2,                          .arburst
		.f2sdram_arcache       (f2sdram_arcache),                        //   input,    width = 4,                          .arcache
		.f2sdram_arid          (f2sdram_arid),                           //   input,    width = 5,                          .arid
		.f2sdram_arlen         (f2sdram_arlen),                          //   input,    width = 8,                          .arlen
		.f2sdram_arlock        (f2sdram_arlock),                         //   input,    width = 1,                          .arlock
		.f2sdram_arprot        (f2sdram_arprot),                         //   input,    width = 3,                          .arprot
		.f2sdram_arqos         (f2sdram_arqos),                          //   input,    width = 4,                          .arqos
		.f2sdram_arready       (f2sdram_arready),                        //  output,    width = 1,                          .arready
		.f2sdram_arsize        (f2sdram_arsize),                         //   input,    width = 3,                          .arsize
		.f2sdram_arvalid       (f2sdram_arvalid),                        //   input,    width = 1,                          .arvalid
		.f2sdram_awaddr        (f2sdram_awaddr),                         //   input,   width = 32,                          .awaddr
		.f2sdram_awburst       (f2sdram_awburst),                        //   input,    width = 2,                          .awburst
		.f2sdram_awcache       (f2sdram_awcache),                        //   input,    width = 4,                          .awcache
		.f2sdram_awid          (f2sdram_awid),                           //   input,    width = 5,                          .awid
		.f2sdram_awlen         (f2sdram_awlen),                          //   input,    width = 8,                          .awlen
		.f2sdram_awlock        (f2sdram_awlock),                         //   input,    width = 1,                          .awlock
		.f2sdram_awprot        (f2sdram_awprot),                         //   input,    width = 3,                          .awprot
		.f2sdram_awqos         (f2sdram_awqos),                          //   input,    width = 4,                          .awqos
		.f2sdram_awready       (f2sdram_awready),                        //  output,    width = 1,                          .awready
		.f2sdram_awsize        (f2sdram_awsize),                         //   input,    width = 3,                          .awsize
		.f2sdram_awvalid       (f2sdram_awvalid),                        //   input,    width = 1,                          .awvalid
		.f2sdram_bid           (f2sdram_bid),                            //  output,    width = 5,                          .bid
		.f2sdram_bready        (f2sdram_bready),                         //   input,    width = 1,                          .bready
		.f2sdram_bresp         (f2sdram_bresp),                          //  output,    width = 2,                          .bresp
		.f2sdram_bvalid        (f2sdram_bvalid),                         //  output,    width = 1,                          .bvalid
		.f2sdram_rdata         (f2sdram_rdata),                          //  output,  width = 256,                          .rdata
		.f2sdram_rid           (f2sdram_rid),                            //  output,    width = 5,                          .rid
		.f2sdram_rlast         (f2sdram_rlast),                          //  output,    width = 1,                          .rlast
		.f2sdram_rready        (f2sdram_rready),                         //   input,    width = 1,                          .rready
		.f2sdram_rresp         (f2sdram_rresp),                          //  output,    width = 2,                          .rresp
		.f2sdram_rvalid        (f2sdram_rvalid),                         //  output,    width = 1,                          .rvalid
		.f2sdram_wdata         (f2sdram_wdata),                          //   input,  width = 256,                          .wdata
		.f2sdram_wlast         (f2sdram_wlast),                          //   input,    width = 1,                          .wlast
		.f2sdram_wready        (f2sdram_wready),                         //  output,    width = 1,                          .wready
		.f2sdram_wstrb         (f2sdram_wstrb),                          //   input,   width = 32,                          .wstrb
		.f2sdram_wvalid        (f2sdram_wvalid),                         //   input,    width = 1,                          .wvalid
		.f2sdram_aruser        (f2sdram_aruser),                         //   input,    width = 8,                          .aruser
		.f2sdram_awuser        (f2sdram_awuser),                         //   input,    width = 8,                          .awuser
		.f2sdram_wuser         (f2sdram_wuser),                          //   input,    width = 8,                          .wuser
		.f2sdram_buser         (f2sdram_buser),                          //  output,    width = 8,                          .buser
		.f2sdram_arregion      (f2sdram_arregion),                       //   input,    width = 4,                          .arregion
		.f2sdram_ruser         (f2sdram_ruser),                          //  output,    width = 8,                          .ruser
		.f2sdram_awregion      (f2sdram_awregion),                       //   input,    width = 4,                          .awregion
		.sdram_bridge_rst_n    (sm_hps_hps2sdram_interconnect_reset_n),  //   input,    width = 1,    sdram2hps_interconnect.reset_n
		.sdram_bridge_ack      (sm_mpfe_sdram2hps_interconnect_ack),     //  output,    width = 1,                          .ack
		.sdram_bridge_req      (sm_hps_hps2sdram_interconnect_req),      //   input,    width = 1,                          .req
		.sdram_tbu_pmu_irpt    (sm_mpfe_sdram2hps_interconnect_tbu_pmu), //  output,    width = 1,                          .tbu_pmu
		.sdram_tbu_ras_irpt    (sm_mpfe_sdram2hps_interconnect_tbu_ras), //  output,    width = 1,                          .tbu_ras
		.emif_csr_axi_clk      (io96b0_csr_axi_clk_clk),                 //   input,    width = 1,        io96b0_csr_axi_clk.clk
		.emif_csr_axi_rst      (io96b0_csr_axi_rst_reset_n),             //   input,    width = 1,        io96b0_csr_axi_rst.reset_n
		.emif_mem_cfg_arready  (io96b0_csr_axi_arready),                 //   input,    width = 1,            io96b0_csr_axi.arready
		.emif_mem_cfg_awready  (io96b0_csr_axi_awready),                 //   input,    width = 1,                          .awready
		.emif_mem_cfg_bresp    (io96b0_csr_axi_bresp),                   //   input,    width = 2,                          .bresp
		.emif_mem_cfg_bvalid   (io96b0_csr_axi_bvalid),                  //   input,    width = 1,                          .bvalid
		.emif_mem_cfg_rdata    (io96b0_csr_axi_rdata),                   //   input,   width = 32,                          .rdata
		.emif_mem_cfg_rresp    (io96b0_csr_axi_rresp),                   //   input,    width = 2,                          .rresp
		.emif_mem_cfg_rvalid   (io96b0_csr_axi_rvalid),                  //   input,    width = 1,                          .rvalid
		.emif_mem_cfg_wready   (io96b0_csr_axi_wready),                  //   input,    width = 1,                          .wready
		.emif_mem_cfg_araddr   (io96b0_csr_axi_araddr),                  //  output,   width = 32,                          .araddr
		.emif_mem_cfg_arvalid  (io96b0_csr_axi_arvalid),                 //  output,    width = 1,                          .arvalid
		.emif_mem_cfg_awaddr   (io96b0_csr_axi_awaddr),                  //  output,   width = 32,                          .awaddr
		.emif_mem_cfg_awvalid  (io96b0_csr_axi_awvalid),                 //  output,    width = 1,                          .awvalid
		.emif_mem_cfg_bready   (io96b0_csr_axi_bready),                  //  output,    width = 1,                          .bready
		.emif_mem_cfg_rready   (io96b0_csr_axi_rready),                  //  output,    width = 1,                          .rready
		.emif_mem_cfg_wdata    (io96b0_csr_axi_wdata),                   //  output,   width = 32,                          .wdata
		.emif_mem_cfg_wstrb    (io96b0_csr_axi_wstrb),                   //  output,    width = 4,                          .wstrb
		.emif_mem_cfg_wvalid   (io96b0_csr_axi_wvalid),                  //  output,    width = 1,                          .wvalid
		.emif_mem_cfg_arprot   (io96b0_csr_axi_arprot),                  //  output,    width = 3,                          .arprot
		.emif_mem_cfg_awprot   (io96b0_csr_axi_awprot),                  //  output,    width = 3,                          .awprot
		.emif_ch0_axi_clk      (io96b0_ch0_axi_clk_clk),                 //   input,    width = 1,        io96b0_ch0_axi_clk.clk
		.emif_ch0_axi_rst      (io96b0_ch0_axi_rst_reset_n),             //   input,    width = 1,        io96b0_ch0_axi_rst.reset_n
		.emif0_arready         (io96b0_ch0_axi_arready),                 //   input,    width = 1,            io96b0_ch0_axi.arready
		.emif0_awready         (io96b0_ch0_axi_awready),                 //   input,    width = 1,                          .awready
		.emif0_bid             (io96b0_ch0_axi_bid),                     //   input,    width = 7,                          .bid
		.emif0_bresp           (io96b0_ch0_axi_bresp),                   //   input,    width = 2,                          .bresp
		.emif0_bvalid          (io96b0_ch0_axi_bvalid),                  //   input,    width = 1,                          .bvalid
		.emif0_rdata           (io96b0_ch0_axi_rdata),                   //   input,  width = 256,                          .rdata
		.emif0_rid             (io96b0_ch0_axi_rid),                     //   input,    width = 7,                          .rid
		.emif0_rlast           (io96b0_ch0_axi_rlast),                   //   input,    width = 1,                          .rlast
		.emif0_rresp           (io96b0_ch0_axi_rresp),                   //   input,    width = 2,                          .rresp
		.emif0_ruser           (io96b0_ch0_axi_ruser),                   //   input,   width = 32,                          .ruser
		.emif0_rvalid          (io96b0_ch0_axi_rvalid),                  //   input,    width = 1,                          .rvalid
		.emif0_wready          (io96b0_ch0_axi_wready),                  //   input,    width = 1,                          .wready
		.emif0_araddr          (io96b0_ch0_axi_araddr),                  //  output,   width = 44,                          .araddr
		.emif0_arburst         (io96b0_ch0_axi_arburst),                 //  output,    width = 2,                          .arburst
		.emif0_arid            (io96b0_ch0_axi_arid),                    //  output,    width = 7,                          .arid
		.emif0_arlen           (io96b0_ch0_axi_arlen),                   //  output,    width = 8,                          .arlen
		.emif0_arlock          (io96b0_ch0_axi_arlock),                  //  output,    width = 1,                          .arlock
		.emif0_arqos           (io96b0_ch0_axi_arqos),                   //  output,    width = 4,                          .arqos
		.emif0_arsize          (io96b0_ch0_axi_arsize),                  //  output,    width = 3,                          .arsize
		.emif0_aruser          (io96b0_ch0_axi_aruser),                  //  output,   width = 14,                          .aruser
		.emif0_arvalid         (io96b0_ch0_axi_arvalid),                 //  output,    width = 1,                          .arvalid
		.emif0_awaddr          (io96b0_ch0_axi_awaddr),                  //  output,   width = 44,                          .awaddr
		.emif0_awburst         (io96b0_ch0_axi_awburst),                 //  output,    width = 2,                          .awburst
		.emif0_awid            (io96b0_ch0_axi_awid),                    //  output,    width = 7,                          .awid
		.emif0_awlen           (io96b0_ch0_axi_awlen),                   //  output,    width = 8,                          .awlen
		.emif0_awlock          (io96b0_ch0_axi_awlock),                  //  output,    width = 1,                          .awlock
		.emif0_awqos           (io96b0_ch0_axi_awqos),                   //  output,    width = 4,                          .awqos
		.emif0_awsize          (io96b0_ch0_axi_awsize),                  //  output,    width = 3,                          .awsize
		.emif0_awuser          (io96b0_ch0_axi_awuser),                  //  output,   width = 14,                          .awuser
		.emif0_awvalid         (io96b0_ch0_axi_awvalid),                 //  output,    width = 1,                          .awvalid
		.emif0_bready          (io96b0_ch0_axi_bready),                  //  output,    width = 1,                          .bready
		.emif0_rready          (io96b0_ch0_axi_rready),                  //  output,    width = 1,                          .rready
		.emif0_wdata           (io96b0_ch0_axi_wdata),                   //  output,  width = 256,                          .wdata
		.emif0_wlast           (io96b0_ch0_axi_wlast),                   //  output,    width = 1,                          .wlast
		.emif0_wstrb           (io96b0_ch0_axi_wstrb),                   //  output,   width = 32,                          .wstrb
		.emif0_wuser           (io96b0_ch0_axi_wuser),                   //  output,   width = 32,                          .wuser
		.emif0_wvalid          (io96b0_ch0_axi_wvalid),                  //  output,    width = 1,                          .wvalid
		.emif0_arprot          (io96b0_ch0_axi_arprot),                  //  output,    width = 3,                          .arprot
		.emif0_awprot          (io96b0_ch0_axi_awprot),                  //  output,    width = 3,                          .awprot
		.hps2mpfe_ccu_clk      (sm_hps_hps_ccu_interconnect_clk_clk),    //   input,    width = 1, mpfe_ccu_interconnect_clk.clk
		.hps2mpfe_ccu_rst      (sm_hps_hps_ccu_interconnect_rst_reset),  //   input,    width = 1, mpfe_ccu_interconnect_rst.reset
		.hps2mpfe_dmi0_araddr  (sm_hps_hps_dmi0_interconnect_araddr),    //   input,   width = 44,    mpfe_dmi0_interconnect.araddr
		.hps2mpfe_dmi0_arburst (sm_hps_hps_dmi0_interconnect_arburst),   //   input,    width = 2,                          .arburst
		.hps2mpfe_dmi0_arcache (sm_hps_hps_dmi0_interconnect_arcache),   //   input,    width = 4,                          .arcache
		.hps2mpfe_dmi0_arid    (sm_hps_hps_dmi0_interconnect_arid),      //   input,   width = 10,                          .arid
		.hps2mpfe_dmi0_arlen   (sm_hps_hps_dmi0_interconnect_arlen),     //   input,    width = 8,                          .arlen
		.hps2mpfe_dmi0_arlock  (sm_hps_hps_dmi0_interconnect_arlock),    //   input,    width = 1,                          .arlock
		.hps2mpfe_dmi0_arprot  (sm_hps_hps_dmi0_interconnect_arprot),    //   input,    width = 3,                          .arprot
		.hps2mpfe_dmi0_arqos   (sm_hps_hps_dmi0_interconnect_arqos),     //   input,    width = 4,                          .arqos
		.hps2mpfe_dmi0_arready (sm_hps_hps_dmi0_interconnect_arready),   //  output,    width = 1,                          .arready
		.hps2mpfe_dmi0_arsize  (sm_hps_hps_dmi0_interconnect_arsize),    //   input,    width = 3,                          .arsize
		.hps2mpfe_dmi0_aruser  (sm_hps_hps_dmi0_interconnect_aruser),    //   input,    width = 8,                          .aruser
		.hps2mpfe_dmi0_arvalid (sm_hps_hps_dmi0_interconnect_arvalid),   //   input,    width = 1,                          .arvalid
		.hps2mpfe_dmi0_awaddr  (sm_hps_hps_dmi0_interconnect_awaddr),    //   input,   width = 44,                          .awaddr
		.hps2mpfe_dmi0_awburst (sm_hps_hps_dmi0_interconnect_awburst),   //   input,    width = 2,                          .awburst
		.hps2mpfe_dmi0_awcache (sm_hps_hps_dmi0_interconnect_awcache),   //   input,    width = 4,                          .awcache
		.hps2mpfe_dmi0_awid    (sm_hps_hps_dmi0_interconnect_awid),      //   input,   width = 10,                          .awid
		.hps2mpfe_dmi0_awlen   (sm_hps_hps_dmi0_interconnect_awlen),     //   input,    width = 8,                          .awlen
		.hps2mpfe_dmi0_awlock  (sm_hps_hps_dmi0_interconnect_awlock),    //   input,    width = 1,                          .awlock
		.hps2mpfe_dmi0_awprot  (sm_hps_hps_dmi0_interconnect_awprot),    //   input,    width = 3,                          .awprot
		.hps2mpfe_dmi0_awqos   (sm_hps_hps_dmi0_interconnect_awqos),     //   input,    width = 4,                          .awqos
		.hps2mpfe_dmi0_awready (sm_hps_hps_dmi0_interconnect_awready),   //  output,    width = 1,                          .awready
		.hps2mpfe_dmi0_awsize  (sm_hps_hps_dmi0_interconnect_awsize),    //   input,    width = 3,                          .awsize
		.hps2mpfe_dmi0_awuser  (sm_hps_hps_dmi0_interconnect_awuser),    //   input,    width = 8,                          .awuser
		.hps2mpfe_dmi0_awvalid (sm_hps_hps_dmi0_interconnect_awvalid),   //   input,    width = 1,                          .awvalid
		.hps2mpfe_dmi0_bid     (sm_hps_hps_dmi0_interconnect_bid),       //  output,   width = 10,                          .bid
		.hps2mpfe_dmi0_bready  (sm_hps_hps_dmi0_interconnect_bready),    //   input,    width = 1,                          .bready
		.hps2mpfe_dmi0_bresp   (sm_hps_hps_dmi0_interconnect_bresp),     //  output,    width = 2,                          .bresp
		.hps2mpfe_dmi0_bvalid  (sm_hps_hps_dmi0_interconnect_bvalid),    //  output,    width = 1,                          .bvalid
		.hps2mpfe_dmi0_rdata   (sm_hps_hps_dmi0_interconnect_rdata),     //  output,  width = 256,                          .rdata
		.hps2mpfe_dmi0_rid     (sm_hps_hps_dmi0_interconnect_rid),       //  output,   width = 10,                          .rid
		.hps2mpfe_dmi0_rlast   (sm_hps_hps_dmi0_interconnect_rlast),     //  output,    width = 1,                          .rlast
		.hps2mpfe_dmi0_rready  (sm_hps_hps_dmi0_interconnect_rready),    //   input,    width = 1,                          .rready
		.hps2mpfe_dmi0_rresp   (sm_hps_hps_dmi0_interconnect_rresp),     //  output,    width = 2,                          .rresp
		.hps2mpfe_dmi0_rvalid  (sm_hps_hps_dmi0_interconnect_rvalid),    //  output,    width = 1,                          .rvalid
		.hps2mpfe_dmi0_wdata   (sm_hps_hps_dmi0_interconnect_wdata),     //   input,  width = 256,                          .wdata
		.hps2mpfe_dmi0_wlast   (sm_hps_hps_dmi0_interconnect_wlast),     //   input,    width = 1,                          .wlast
		.hps2mpfe_dmi0_wready  (sm_hps_hps_dmi0_interconnect_wready),    //  output,    width = 1,                          .wready
		.hps2mpfe_dmi0_wstrb   (sm_hps_hps_dmi0_interconnect_wstrb),     //   input,   width = 32,                          .wstrb
		.hps2mpfe_dmi0_wvalid  (sm_hps_hps_dmi0_interconnect_wvalid),    //   input,    width = 1,                          .wvalid
		.hps2mpfe_dmi1_araddr  (sm_hps_hps_dmi1_interconnect_araddr),    //   input,   width = 44,    mpfe_dmi1_interconnect.araddr
		.hps2mpfe_dmi1_arburst (sm_hps_hps_dmi1_interconnect_arburst),   //   input,    width = 2,                          .arburst
		.hps2mpfe_dmi1_arcache (sm_hps_hps_dmi1_interconnect_arcache),   //   input,    width = 4,                          .arcache
		.hps2mpfe_dmi1_arid    (sm_hps_hps_dmi1_interconnect_arid),      //   input,   width = 10,                          .arid
		.hps2mpfe_dmi1_arlen   (sm_hps_hps_dmi1_interconnect_arlen),     //   input,    width = 8,                          .arlen
		.hps2mpfe_dmi1_arlock  (sm_hps_hps_dmi1_interconnect_arlock),    //   input,    width = 1,                          .arlock
		.hps2mpfe_dmi1_arprot  (sm_hps_hps_dmi1_interconnect_arprot),    //   input,    width = 3,                          .arprot
		.hps2mpfe_dmi1_arqos   (sm_hps_hps_dmi1_interconnect_arqos),     //   input,    width = 4,                          .arqos
		.hps2mpfe_dmi1_arready (sm_hps_hps_dmi1_interconnect_arready),   //  output,    width = 1,                          .arready
		.hps2mpfe_dmi1_arsize  (sm_hps_hps_dmi1_interconnect_arsize),    //   input,    width = 3,                          .arsize
		.hps2mpfe_dmi1_aruser  (sm_hps_hps_dmi1_interconnect_aruser),    //   input,    width = 8,                          .aruser
		.hps2mpfe_dmi1_arvalid (sm_hps_hps_dmi1_interconnect_arvalid),   //   input,    width = 1,                          .arvalid
		.hps2mpfe_dmi1_awaddr  (sm_hps_hps_dmi1_interconnect_awaddr),    //   input,   width = 44,                          .awaddr
		.hps2mpfe_dmi1_awburst (sm_hps_hps_dmi1_interconnect_awburst),   //   input,    width = 2,                          .awburst
		.hps2mpfe_dmi1_awcache (sm_hps_hps_dmi1_interconnect_awcache),   //   input,    width = 4,                          .awcache
		.hps2mpfe_dmi1_awid    (sm_hps_hps_dmi1_interconnect_awid),      //   input,   width = 10,                          .awid
		.hps2mpfe_dmi1_awlen   (sm_hps_hps_dmi1_interconnect_awlen),     //   input,    width = 8,                          .awlen
		.hps2mpfe_dmi1_awlock  (sm_hps_hps_dmi1_interconnect_awlock),    //   input,    width = 1,                          .awlock
		.hps2mpfe_dmi1_awprot  (sm_hps_hps_dmi1_interconnect_awprot),    //   input,    width = 3,                          .awprot
		.hps2mpfe_dmi1_awqos   (sm_hps_hps_dmi1_interconnect_awqos),     //   input,    width = 4,                          .awqos
		.hps2mpfe_dmi1_awready (sm_hps_hps_dmi1_interconnect_awready),   //  output,    width = 1,                          .awready
		.hps2mpfe_dmi1_awsize  (sm_hps_hps_dmi1_interconnect_awsize),    //   input,    width = 3,                          .awsize
		.hps2mpfe_dmi1_awuser  (sm_hps_hps_dmi1_interconnect_awuser),    //   input,    width = 8,                          .awuser
		.hps2mpfe_dmi1_awvalid (sm_hps_hps_dmi1_interconnect_awvalid),   //   input,    width = 1,                          .awvalid
		.hps2mpfe_dmi1_bid     (sm_hps_hps_dmi1_interconnect_bid),       //  output,   width = 10,                          .bid
		.hps2mpfe_dmi1_bready  (sm_hps_hps_dmi1_interconnect_bready),    //   input,    width = 1,                          .bready
		.hps2mpfe_dmi1_bresp   (sm_hps_hps_dmi1_interconnect_bresp),     //  output,    width = 2,                          .bresp
		.hps2mpfe_dmi1_bvalid  (sm_hps_hps_dmi1_interconnect_bvalid),    //  output,    width = 1,                          .bvalid
		.hps2mpfe_dmi1_rdata   (sm_hps_hps_dmi1_interconnect_rdata),     //  output,  width = 256,                          .rdata
		.hps2mpfe_dmi1_rid     (sm_hps_hps_dmi1_interconnect_rid),       //  output,   width = 10,                          .rid
		.hps2mpfe_dmi1_rlast   (sm_hps_hps_dmi1_interconnect_rlast),     //  output,    width = 1,                          .rlast
		.hps2mpfe_dmi1_rready  (sm_hps_hps_dmi1_interconnect_rready),    //   input,    width = 1,                          .rready
		.hps2mpfe_dmi1_rresp   (sm_hps_hps_dmi1_interconnect_rresp),     //  output,    width = 2,                          .rresp
		.hps2mpfe_dmi1_rvalid  (sm_hps_hps_dmi1_interconnect_rvalid),    //  output,    width = 1,                          .rvalid
		.hps2mpfe_dmi1_wdata   (sm_hps_hps_dmi1_interconnect_wdata),     //   input,  width = 256,                          .wdata
		.hps2mpfe_dmi1_wlast   (sm_hps_hps_dmi1_interconnect_wlast),     //   input,    width = 1,                          .wlast
		.hps2mpfe_dmi1_wready  (sm_hps_hps_dmi1_interconnect_wready),    //  output,    width = 1,                          .wready
		.hps2mpfe_dmi1_wstrb   (sm_hps_hps_dmi1_interconnect_wstrb),     //   input,   width = 32,                          .wstrb
		.hps2mpfe_dmi1_wvalid  (sm_hps_hps_dmi1_interconnect_wvalid),    //   input,    width = 1,                          .wvalid
		.hps2mpfe_csr_araddr   (sm_hps_hps_s2mpfe_interconnect_araddr),  //   input,   width = 44,  mpfe_s2mpfe_interconnect.araddr
		.hps2mpfe_csr_arburst  (sm_hps_hps_s2mpfe_interconnect_arburst), //   input,    width = 2,                          .arburst
		.hps2mpfe_csr_arcache  (sm_hps_hps_s2mpfe_interconnect_arcache), //   input,    width = 4,                          .arcache
		.hps2mpfe_csr_arid     (sm_hps_hps_s2mpfe_interconnect_arid),    //   input,   width = 10,                          .arid
		.hps2mpfe_csr_arlen    (sm_hps_hps_s2mpfe_interconnect_arlen),   //   input,    width = 8,                          .arlen
		.hps2mpfe_csr_arlock   (sm_hps_hps_s2mpfe_interconnect_arlock),  //   input,    width = 1,                          .arlock
		.hps2mpfe_csr_arprot   (sm_hps_hps_s2mpfe_interconnect_arprot),  //   input,    width = 3,                          .arprot
		.hps2mpfe_csr_arready  (sm_hps_hps_s2mpfe_interconnect_arready), //  output,    width = 1,                          .arready
		.hps2mpfe_csr_arsize   (sm_hps_hps_s2mpfe_interconnect_arsize),  //   input,    width = 3,                          .arsize
		.hps2mpfe_csr_aruser   (sm_hps_hps_s2mpfe_interconnect_aruser),  //   input,    width = 8,                          .aruser
		.hps2mpfe_csr_arvalid  (sm_hps_hps_s2mpfe_interconnect_arvalid), //   input,    width = 1,                          .arvalid
		.hps2mpfe_csr_awaddr   (sm_hps_hps_s2mpfe_interconnect_awaddr),  //   input,   width = 44,                          .awaddr
		.hps2mpfe_csr_awburst  (sm_hps_hps_s2mpfe_interconnect_awburst), //   input,    width = 2,                          .awburst
		.hps2mpfe_csr_awcache  (sm_hps_hps_s2mpfe_interconnect_awcache), //   input,    width = 4,                          .awcache
		.hps2mpfe_csr_awid     (sm_hps_hps_s2mpfe_interconnect_awid),    //   input,   width = 10,                          .awid
		.hps2mpfe_csr_awlen    (sm_hps_hps_s2mpfe_interconnect_awlen),   //   input,    width = 8,                          .awlen
		.hps2mpfe_csr_awlock   (sm_hps_hps_s2mpfe_interconnect_awlock),  //   input,    width = 1,                          .awlock
		.hps2mpfe_csr_awprot   (sm_hps_hps_s2mpfe_interconnect_awprot),  //   input,    width = 3,                          .awprot
		.hps2mpfe_csr_awready  (sm_hps_hps_s2mpfe_interconnect_awready), //  output,    width = 1,                          .awready
		.hps2mpfe_csr_awsize   (sm_hps_hps_s2mpfe_interconnect_awsize),  //   input,    width = 3,                          .awsize
		.hps2mpfe_csr_awuser   (sm_hps_hps_s2mpfe_interconnect_awuser),  //   input,    width = 8,                          .awuser
		.hps2mpfe_csr_awvalid  (sm_hps_hps_s2mpfe_interconnect_awvalid), //   input,    width = 1,                          .awvalid
		.hps2mpfe_csr_bid      (sm_hps_hps_s2mpfe_interconnect_bid),     //  output,   width = 10,                          .bid
		.hps2mpfe_csr_bready   (sm_hps_hps_s2mpfe_interconnect_bready),  //   input,    width = 1,                          .bready
		.hps2mpfe_csr_bresp    (sm_hps_hps_s2mpfe_interconnect_bresp),   //  output,    width = 2,                          .bresp
		.hps2mpfe_csr_bvalid   (sm_hps_hps_s2mpfe_interconnect_bvalid),  //  output,    width = 1,                          .bvalid
		.hps2mpfe_csr_rdata    (sm_hps_hps_s2mpfe_interconnect_rdata),   //  output,   width = 64,                          .rdata
		.hps2mpfe_csr_rid      (sm_hps_hps_s2mpfe_interconnect_rid),     //  output,   width = 10,                          .rid
		.hps2mpfe_csr_rlast    (sm_hps_hps_s2mpfe_interconnect_rlast),   //  output,    width = 1,                          .rlast
		.hps2mpfe_csr_rready   (sm_hps_hps_s2mpfe_interconnect_rready),  //   input,    width = 1,                          .rready
		.hps2mpfe_csr_rresp    (sm_hps_hps_s2mpfe_interconnect_rresp),   //  output,    width = 2,                          .rresp
		.hps2mpfe_csr_rvalid   (sm_hps_hps_s2mpfe_interconnect_rvalid),  //  output,    width = 1,                          .rvalid
		.hps2mpfe_csr_wdata    (sm_hps_hps_s2mpfe_interconnect_wdata),   //   input,   width = 64,                          .wdata
		.hps2mpfe_csr_wlast    (sm_hps_hps_s2mpfe_interconnect_wlast),   //   input,    width = 1,                          .wlast
		.hps2mpfe_csr_wready   (sm_hps_hps_s2mpfe_interconnect_wready),  //  output,    width = 1,                          .wready
		.hps2mpfe_csr_wstrb    (sm_hps_hps_s2mpfe_interconnect_wstrb),   //   input,    width = 8,                          .wstrb
		.hps2mpfe_csr_wvalid   (sm_hps_hps_s2mpfe_interconnect_wvalid)   //   input,    width = 1,                          .wvalid
	);

endmodule
