module emif_hps_emif_ph2_cal_arch_fp_410_r3ed27y #(
   parameter NUM_CALBUS_PERIPHS                                 = 0,
   parameter NUM_CALBUS_PLLS                                    = 0,
   parameter PORT_M_AXIL_ENABLE                                 = 0,
   parameter PORT_AXIL_ADDRESS_WIDTH                            = 0
) (
   output logic [1341:0]   periph_calbus_0,
   input  logic [1314:0]   periph_calbus_readdata_0,
   input  logic [32767:0]  periph_calbus_param_table_0,
   output logic [1341:0]   periph_calbus_1,
   input  logic [1314:0]   periph_calbus_readdata_1,
   input  logic [32767:0]  periph_calbus_param_table_1,
   output logic [57:0]     pll_calbus_0,
   input  logic [31:0]     pll_calbus_readdata_0,
   output logic [57:0]     pll_calbus_1,
   input  logic [31:0]     pll_calbus_readdata_1,
   output logic [57:0]     pll_calbus_2,
   input  logic [31:0]     pll_calbus_readdata_2,
   input  logic            s0_axi4lite_clk,
   input  logic            s0_axi4lite_rst_n,
   input  logic [26:0]     s0_axi4lite_awaddr,
   input  logic            s0_axi4lite_awvalid,
   output logic            s0_axi4lite_awready,
   input  logic [31:0]     s0_axi4lite_wdata,
   input  logic [3:0]      s0_axi4lite_wstrb,
   input  logic            s0_axi4lite_wvalid,
   output logic            s0_axi4lite_wready,
   output logic [1:0]      s0_axi4lite_bresp,
   output logic            s0_axi4lite_bvalid,
   input  logic            s0_axi4lite_bready,
   input  logic [26:0]     s0_axi4lite_araddr,
   input  logic            s0_axi4lite_arvalid,
   output logic            s0_axi4lite_arready,
   output logic [31:0]     s0_axi4lite_rdata,
   output logic [1:0]      s0_axi4lite_rresp,
   output logic            s0_axi4lite_rvalid,
   input  logic            s0_axi4lite_rready,
   input  logic [2:0]      s0_axi4lite_awprot,
   input  logic [2:0]      s0_axi4lite_arprot,
   output logic [26:0]     m0_axi4lite_awaddr,
   output logic            m0_axi4lite_awvalid,
   input  logic            m0_axi4lite_awready,
   output logic [31:0]     m0_axi4lite_wdata,
   output logic [3:0]      m0_axi4lite_wstrb,
   output logic            m0_axi4lite_wvalid,
   input  logic            m0_axi4lite_wready,
   input  logic [1:0]      m0_axi4lite_bresp,
   input  logic            m0_axi4lite_bvalid,
   output logic            m0_axi4lite_bready,
   output logic [26:0]     m0_axi4lite_araddr,
   output logic            m0_axi4lite_arvalid,
   input  logic            m0_axi4lite_arready,
   input  logic [31:0]     m0_axi4lite_rdata,
   input  logic [1:0]      m0_axi4lite_rresp,
   input  logic            m0_axi4lite_rvalid,
   output logic            m0_axi4lite_rready,
   output logic [2:0]      m0_axi4lite_awprot,
   output logic [2:0]      m0_axi4lite_arprot,
   output logic            s0_noc_axi4lite_clk,
   output logic            s0_noc_axi4lite_rst_n,
   input  logic [26:0]     s0_noc_axi4lite_awaddr,
   input  logic            s0_noc_axi4lite_awvalid,
   output logic            s0_noc_axi4lite_awready,
   input  logic [31:0]     s0_noc_axi4lite_wdata,
   input  logic [3:0]      s0_noc_axi4lite_wstrb,
   input  logic            s0_noc_axi4lite_wvalid,
   output logic            s0_noc_axi4lite_wready,
   output logic [1:0]      s0_noc_axi4lite_bresp,
   output logic            s0_noc_axi4lite_bvalid,
   input  logic            s0_noc_axi4lite_bready,
   input  logic [26:0]     s0_noc_axi4lite_araddr,
   input  logic            s0_noc_axi4lite_arvalid,
   output logic            s0_noc_axi4lite_arready,
   output logic [31:0]     s0_noc_axi4lite_rdata,
   output logic [1:0]      s0_noc_axi4lite_rresp,
   output logic            s0_noc_axi4lite_rvalid,
   input  logic            s0_noc_axi4lite_rready,
   input  logic [2:0]      s0_noc_axi4lite_awprot,
   input  logic [2:0]      s0_noc_axi4lite_arprot,
   input  logic            tniul_rst_n,
   input  logic [7:0]      ls_to_cal,
   output logic [7:0]      ls_from_cal,
   input  logic            fbr_c2f_rst_n
);
   timeunit 1ns;
   timeprecision 1ps;

   emif_hps_emif_ph2_cal_arch_fp_410_r3ed27y_cal_arch_fp_top # (
      .NUM_CALBUS_PERIPHS (NUM_CALBUS_PERIPHS),
      .NUM_CALBUS_PLLS (NUM_CALBUS_PLLS),
      .PORT_M_AXIL_ENABLE (PORT_M_AXIL_ENABLE),
      .PORT_AXIL_ADDRESS_WIDTH (PORT_AXIL_ADDRESS_WIDTH)
   ) emif_hps_emif_ph2_cal_arch_fp_410_r3ed27y_cal_arch_fp_inst (
      .periph_calbus_0 (periph_calbus_0),
      .periph_calbus_readdata_0 (periph_calbus_readdata_0),
      .periph_calbus_param_table_0 (periph_calbus_param_table_0),
      .periph_calbus_1 (periph_calbus_1),
      .periph_calbus_readdata_1 (periph_calbus_readdata_1),
      .periph_calbus_param_table_1 (periph_calbus_param_table_1),
      .pll_calbus_0 (pll_calbus_0),
      .pll_calbus_readdata_0 (pll_calbus_readdata_0),
      .pll_calbus_1 (pll_calbus_1),
      .pll_calbus_readdata_1 (pll_calbus_readdata_1),
      .pll_calbus_2 (pll_calbus_2),
      .pll_calbus_readdata_2 (pll_calbus_readdata_2),
      .s0_axi4lite_clk (s0_axi4lite_clk),
      .s0_axi4lite_rst_n (s0_axi4lite_rst_n),
      .s0_axi4lite_awaddr (s0_axi4lite_awaddr),
      .s0_axi4lite_awvalid (s0_axi4lite_awvalid),
      .s0_axi4lite_awready (s0_axi4lite_awready),
      .s0_axi4lite_wdata (s0_axi4lite_wdata),
      .s0_axi4lite_wstrb (s0_axi4lite_wstrb),
      .s0_axi4lite_wvalid (s0_axi4lite_wvalid),
      .s0_axi4lite_wready (s0_axi4lite_wready),
      .s0_axi4lite_bresp (s0_axi4lite_bresp),
      .s0_axi4lite_bvalid (s0_axi4lite_bvalid),
      .s0_axi4lite_bready (s0_axi4lite_bready),
      .s0_axi4lite_araddr (s0_axi4lite_araddr),
      .s0_axi4lite_arvalid (s0_axi4lite_arvalid),
      .s0_axi4lite_arready (s0_axi4lite_arready),
      .s0_axi4lite_rdata (s0_axi4lite_rdata),
      .s0_axi4lite_rresp (s0_axi4lite_rresp),
      .s0_axi4lite_rvalid (s0_axi4lite_rvalid),
      .s0_axi4lite_rready (s0_axi4lite_rready),
      .s0_axi4lite_awprot (s0_axi4lite_awprot),
      .s0_axi4lite_arprot (s0_axi4lite_arprot),
      .m0_axi4lite_awaddr (m0_axi4lite_awaddr),
      .m0_axi4lite_awvalid (m0_axi4lite_awvalid),
      .m0_axi4lite_awready (m0_axi4lite_awready),
      .m0_axi4lite_wdata (m0_axi4lite_wdata),
      .m0_axi4lite_wstrb (m0_axi4lite_wstrb),
      .m0_axi4lite_wvalid (m0_axi4lite_wvalid),
      .m0_axi4lite_wready (m0_axi4lite_wready),
      .m0_axi4lite_bresp (m0_axi4lite_bresp),
      .m0_axi4lite_bvalid (m0_axi4lite_bvalid),
      .m0_axi4lite_bready (m0_axi4lite_bready),
      .m0_axi4lite_araddr (m0_axi4lite_araddr),
      .m0_axi4lite_arvalid (m0_axi4lite_arvalid),
      .m0_axi4lite_arready (m0_axi4lite_arready),
      .m0_axi4lite_rdata (m0_axi4lite_rdata),
      .m0_axi4lite_rresp (m0_axi4lite_rresp),
      .m0_axi4lite_rvalid (m0_axi4lite_rvalid),
      .m0_axi4lite_rready (m0_axi4lite_rready),
      .m0_axi4lite_awprot (m0_axi4lite_awprot),
      .m0_axi4lite_arprot (m0_axi4lite_arprot),
      .s0_noc_axi4lite_clk (s0_noc_axi4lite_clk),
      .s0_noc_axi4lite_rst_n (s0_noc_axi4lite_rst_n),
      .s0_noc_axi4lite_awaddr (s0_noc_axi4lite_awaddr),
      .s0_noc_axi4lite_awvalid (s0_noc_axi4lite_awvalid),
      .s0_noc_axi4lite_awready (s0_noc_axi4lite_awready),
      .s0_noc_axi4lite_wdata (s0_noc_axi4lite_wdata),
      .s0_noc_axi4lite_wstrb (s0_noc_axi4lite_wstrb),
      .s0_noc_axi4lite_wvalid (s0_noc_axi4lite_wvalid),
      .s0_noc_axi4lite_wready (s0_noc_axi4lite_wready),
      .s0_noc_axi4lite_bresp (s0_noc_axi4lite_bresp),
      .s0_noc_axi4lite_bvalid (s0_noc_axi4lite_bvalid),
      .s0_noc_axi4lite_bready (s0_noc_axi4lite_bready),
      .s0_noc_axi4lite_araddr (s0_noc_axi4lite_araddr),
      .s0_noc_axi4lite_arvalid (s0_noc_axi4lite_arvalid),
      .s0_noc_axi4lite_arready (s0_noc_axi4lite_arready),
      .s0_noc_axi4lite_rdata (s0_noc_axi4lite_rdata),
      .s0_noc_axi4lite_rresp (s0_noc_axi4lite_rresp),
      .s0_noc_axi4lite_rvalid (s0_noc_axi4lite_rvalid),
      .s0_noc_axi4lite_rready (s0_noc_axi4lite_rready),
      .s0_noc_axi4lite_awprot (s0_noc_axi4lite_awprot),
      .s0_noc_axi4lite_arprot (s0_noc_axi4lite_arprot),
      .tniul_rst_n (tniul_rst_n),
      .ls_to_cal (ls_to_cal),
      .ls_from_cal (ls_from_cal),
      .fbr_c2f_rst_n (fbr_c2f_rst_n)
   );
endmodule
