// qsys_top_altera_mm_interconnect_1920_jt5szha.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module qsys_top_altera_mm_interconnect_1920_jt5szha (
		input  wire [31:0]  subsys_debug_fpga_m_master_address,                //               subsys_debug_fpga_m_master.address
		output wire         subsys_debug_fpga_m_master_waitrequest,            //                                         .waitrequest
		input  wire [3:0]   subsys_debug_fpga_m_master_byteenable,             //                                         .byteenable
		input  wire         subsys_debug_fpga_m_master_read,                   //                                         .read
		output wire [31:0]  subsys_debug_fpga_m_master_readdata,               //                                         .readdata
		output wire         subsys_debug_fpga_m_master_readdatavalid,          //                                         .readdatavalid
		input  wire         subsys_debug_fpga_m_master_write,                  //                                         .write
		input  wire [31:0]  subsys_debug_fpga_m_master_writedata,              //                                         .writedata
		input  wire [3:0]   subsys_hps_hps2fpga_awid,                          //                      subsys_hps_hps2fpga.awid
		input  wire [37:0]  subsys_hps_hps2fpga_awaddr,                        //                                         .awaddr
		input  wire [7:0]   subsys_hps_hps2fpga_awlen,                         //                                         .awlen
		input  wire [2:0]   subsys_hps_hps2fpga_awsize,                        //                                         .awsize
		input  wire [1:0]   subsys_hps_hps2fpga_awburst,                       //                                         .awburst
		input  wire [0:0]   subsys_hps_hps2fpga_awlock,                        //                                         .awlock
		input  wire [3:0]   subsys_hps_hps2fpga_awcache,                       //                                         .awcache
		input  wire [2:0]   subsys_hps_hps2fpga_awprot,                        //                                         .awprot
		input  wire         subsys_hps_hps2fpga_awvalid,                       //                                         .awvalid
		output wire         subsys_hps_hps2fpga_awready,                       //                                         .awready
		input  wire [127:0] subsys_hps_hps2fpga_wdata,                         //                                         .wdata
		input  wire [15:0]  subsys_hps_hps2fpga_wstrb,                         //                                         .wstrb
		input  wire         subsys_hps_hps2fpga_wlast,                         //                                         .wlast
		input  wire         subsys_hps_hps2fpga_wvalid,                        //                                         .wvalid
		output wire         subsys_hps_hps2fpga_wready,                        //                                         .wready
		output wire [3:0]   subsys_hps_hps2fpga_bid,                           //                                         .bid
		output wire [1:0]   subsys_hps_hps2fpga_bresp,                         //                                         .bresp
		output wire         subsys_hps_hps2fpga_bvalid,                        //                                         .bvalid
		input  wire         subsys_hps_hps2fpga_bready,                        //                                         .bready
		input  wire [3:0]   subsys_hps_hps2fpga_arid,                          //                                         .arid
		input  wire [37:0]  subsys_hps_hps2fpga_araddr,                        //                                         .araddr
		input  wire [7:0]   subsys_hps_hps2fpga_arlen,                         //                                         .arlen
		input  wire [2:0]   subsys_hps_hps2fpga_arsize,                        //                                         .arsize
		input  wire [1:0]   subsys_hps_hps2fpga_arburst,                       //                                         .arburst
		input  wire [0:0]   subsys_hps_hps2fpga_arlock,                        //                                         .arlock
		input  wire [3:0]   subsys_hps_hps2fpga_arcache,                       //                                         .arcache
		input  wire [2:0]   subsys_hps_hps2fpga_arprot,                        //                                         .arprot
		input  wire         subsys_hps_hps2fpga_arvalid,                       //                                         .arvalid
		output wire         subsys_hps_hps2fpga_arready,                       //                                         .arready
		output wire [3:0]   subsys_hps_hps2fpga_rid,                           //                                         .rid
		output wire [127:0] subsys_hps_hps2fpga_rdata,                         //                                         .rdata
		output wire [1:0]   subsys_hps_hps2fpga_rresp,                         //                                         .rresp
		output wire         subsys_hps_hps2fpga_rlast,                         //                                         .rlast
		output wire         subsys_hps_hps2fpga_rvalid,                        //                                         .rvalid
		input  wire         subsys_hps_hps2fpga_rready,                        //                                         .rready
		input  wire [3:0]   subsys_hps_lwhps2fpga_awid,                        //                    subsys_hps_lwhps2fpga.awid
		input  wire [28:0]  subsys_hps_lwhps2fpga_awaddr,                      //                                         .awaddr
		input  wire [7:0]   subsys_hps_lwhps2fpga_awlen,                       //                                         .awlen
		input  wire [2:0]   subsys_hps_lwhps2fpga_awsize,                      //                                         .awsize
		input  wire [1:0]   subsys_hps_lwhps2fpga_awburst,                     //                                         .awburst
		input  wire [0:0]   subsys_hps_lwhps2fpga_awlock,                      //                                         .awlock
		input  wire [3:0]   subsys_hps_lwhps2fpga_awcache,                     //                                         .awcache
		input  wire [2:0]   subsys_hps_lwhps2fpga_awprot,                      //                                         .awprot
		input  wire         subsys_hps_lwhps2fpga_awvalid,                     //                                         .awvalid
		output wire         subsys_hps_lwhps2fpga_awready,                     //                                         .awready
		input  wire [31:0]  subsys_hps_lwhps2fpga_wdata,                       //                                         .wdata
		input  wire [3:0]   subsys_hps_lwhps2fpga_wstrb,                       //                                         .wstrb
		input  wire         subsys_hps_lwhps2fpga_wlast,                       //                                         .wlast
		input  wire         subsys_hps_lwhps2fpga_wvalid,                      //                                         .wvalid
		output wire         subsys_hps_lwhps2fpga_wready,                      //                                         .wready
		output wire [3:0]   subsys_hps_lwhps2fpga_bid,                         //                                         .bid
		output wire [1:0]   subsys_hps_lwhps2fpga_bresp,                       //                                         .bresp
		output wire         subsys_hps_lwhps2fpga_bvalid,                      //                                         .bvalid
		input  wire         subsys_hps_lwhps2fpga_bready,                      //                                         .bready
		input  wire [3:0]   subsys_hps_lwhps2fpga_arid,                        //                                         .arid
		input  wire [28:0]  subsys_hps_lwhps2fpga_araddr,                      //                                         .araddr
		input  wire [7:0]   subsys_hps_lwhps2fpga_arlen,                       //                                         .arlen
		input  wire [2:0]   subsys_hps_lwhps2fpga_arsize,                      //                                         .arsize
		input  wire [1:0]   subsys_hps_lwhps2fpga_arburst,                     //                                         .arburst
		input  wire [0:0]   subsys_hps_lwhps2fpga_arlock,                      //                                         .arlock
		input  wire [3:0]   subsys_hps_lwhps2fpga_arcache,                     //                                         .arcache
		input  wire [2:0]   subsys_hps_lwhps2fpga_arprot,                      //                                         .arprot
		input  wire         subsys_hps_lwhps2fpga_arvalid,                     //                                         .arvalid
		output wire         subsys_hps_lwhps2fpga_arready,                     //                                         .arready
		output wire [3:0]   subsys_hps_lwhps2fpga_rid,                         //                                         .rid
		output wire [31:0]  subsys_hps_lwhps2fpga_rdata,                       //                                         .rdata
		output wire [1:0]   subsys_hps_lwhps2fpga_rresp,                       //                                         .rresp
		output wire         subsys_hps_lwhps2fpga_rlast,                       //                                         .rlast
		output wire         subsys_hps_lwhps2fpga_rvalid,                      //                                         .rvalid
		input  wire         subsys_hps_lwhps2fpga_rready,                      //                                         .rready
		output wire [9:0]   ocm_axi_s1_awid,                                   //                               ocm_axi_s1.awid
		output wire [17:0]  ocm_axi_s1_awaddr,                                 //                                         .awaddr
		output wire [7:0]   ocm_axi_s1_awlen,                                  //                                         .awlen
		output wire [2:0]   ocm_axi_s1_awsize,                                 //                                         .awsize
		output wire [1:0]   ocm_axi_s1_awburst,                                //                                         .awburst
		output wire         ocm_axi_s1_awvalid,                                //                                         .awvalid
		input  wire         ocm_axi_s1_awready,                                //                                         .awready
		output wire [127:0] ocm_axi_s1_wdata,                                  //                                         .wdata
		output wire [15:0]  ocm_axi_s1_wstrb,                                  //                                         .wstrb
		output wire         ocm_axi_s1_wlast,                                  //                                         .wlast
		output wire         ocm_axi_s1_wvalid,                                 //                                         .wvalid
		input  wire         ocm_axi_s1_wready,                                 //                                         .wready
		input  wire [9:0]   ocm_axi_s1_bid,                                    //                                         .bid
		input  wire [1:0]   ocm_axi_s1_bresp,                                  //                                         .bresp
		input  wire         ocm_axi_s1_bvalid,                                 //                                         .bvalid
		output wire         ocm_axi_s1_bready,                                 //                                         .bready
		output wire [9:0]   ocm_axi_s1_arid,                                   //                                         .arid
		output wire [17:0]  ocm_axi_s1_araddr,                                 //                                         .araddr
		output wire [7:0]   ocm_axi_s1_arlen,                                  //                                         .arlen
		output wire [2:0]   ocm_axi_s1_arsize,                                 //                                         .arsize
		output wire [1:0]   ocm_axi_s1_arburst,                                //                                         .arburst
		output wire         ocm_axi_s1_arvalid,                                //                                         .arvalid
		input  wire         ocm_axi_s1_arready,                                //                                         .arready
		input  wire [9:0]   ocm_axi_s1_rid,                                    //                                         .rid
		input  wire [127:0] ocm_axi_s1_rdata,                                  //                                         .rdata
		input  wire [1:0]   ocm_axi_s1_rresp,                                  //                                         .rresp
		input  wire         ocm_axi_s1_rlast,                                  //                                         .rlast
		input  wire         ocm_axi_s1_rvalid,                                 //                                         .rvalid
		output wire         ocm_axi_s1_rready,                                 //                                         .rready
		output wire [20:0]  subsys_hps_usb31_phy_reconfig_slave_address,       //      subsys_hps_usb31_phy_reconfig_slave.address
		output wire         subsys_hps_usb31_phy_reconfig_slave_write,         //                                         .write
		output wire         subsys_hps_usb31_phy_reconfig_slave_read,          //                                         .read
		input  wire [31:0]  subsys_hps_usb31_phy_reconfig_slave_readdata,      //                                         .readdata
		output wire [31:0]  subsys_hps_usb31_phy_reconfig_slave_writedata,     //                                         .writedata
		output wire [3:0]   subsys_hps_usb31_phy_reconfig_slave_byteenable,    //                                         .byteenable
		input  wire         subsys_hps_usb31_phy_reconfig_slave_readdatavalid, //                                         .readdatavalid
		input  wire         subsys_hps_usb31_phy_reconfig_slave_waitrequest,   //                                         .waitrequest
		output wire [16:0]  subsys_periph_pb_cpu_0_s0_address,                 //                subsys_periph_pb_cpu_0_s0.address
		output wire         subsys_periph_pb_cpu_0_s0_write,                   //                                         .write
		output wire         subsys_periph_pb_cpu_0_s0_read,                    //                                         .read
		input  wire [31:0]  subsys_periph_pb_cpu_0_s0_readdata,                //                                         .readdata
		output wire [31:0]  subsys_periph_pb_cpu_0_s0_writedata,               //                                         .writedata
		output wire [0:0]   subsys_periph_pb_cpu_0_s0_burstcount,              //                                         .burstcount
		output wire [3:0]   subsys_periph_pb_cpu_0_s0_byteenable,              //                                         .byteenable
		input  wire         subsys_periph_pb_cpu_0_s0_readdatavalid,           //                                         .readdatavalid
		input  wire         subsys_periph_pb_cpu_0_s0_waitrequest,             //                                         .waitrequest
		output wire         subsys_periph_pb_cpu_0_s0_debugaccess,             //                                         .debugaccess
		input  wire         subsys_debug_reset_reset_bridge_in_reset_reset,    // subsys_debug_reset_reset_bridge_in_reset.reset,        Reset Input
		input  wire         ocm_reset1_reset_bridge_in_reset_reset,            //         ocm_reset1_reset_bridge_in_reset.reset,        Reset Input
		input  wire         clk_100_out_clk_clk                                //                          clk_100_out_clk.clk,          Clock Input
	);

	wire          subsys_debug_fpga_m_master_translator_avalon_universal_master_0_waitrequest;     // subsys_debug_fpga_m_master_agent:av_waitrequest -> subsys_debug_fpga_m_master_translator:uav_waitrequest
	wire   [31:0] subsys_debug_fpga_m_master_translator_avalon_universal_master_0_readdata;        // subsys_debug_fpga_m_master_agent:av_readdata -> subsys_debug_fpga_m_master_translator:uav_readdata
	wire          subsys_debug_fpga_m_master_translator_avalon_universal_master_0_debugaccess;     // subsys_debug_fpga_m_master_translator:uav_debugaccess -> subsys_debug_fpga_m_master_agent:av_debugaccess
	wire   [37:0] subsys_debug_fpga_m_master_translator_avalon_universal_master_0_address;         // subsys_debug_fpga_m_master_translator:uav_address -> subsys_debug_fpga_m_master_agent:av_address
	wire          subsys_debug_fpga_m_master_translator_avalon_universal_master_0_read;            // subsys_debug_fpga_m_master_translator:uav_read -> subsys_debug_fpga_m_master_agent:av_read
	wire    [3:0] subsys_debug_fpga_m_master_translator_avalon_universal_master_0_byteenable;      // subsys_debug_fpga_m_master_translator:uav_byteenable -> subsys_debug_fpga_m_master_agent:av_byteenable
	wire          subsys_debug_fpga_m_master_translator_avalon_universal_master_0_readdatavalid;   // subsys_debug_fpga_m_master_agent:av_readdatavalid -> subsys_debug_fpga_m_master_translator:uav_readdatavalid
	wire          subsys_debug_fpga_m_master_translator_avalon_universal_master_0_lock;            // subsys_debug_fpga_m_master_translator:uav_lock -> subsys_debug_fpga_m_master_agent:av_lock
	wire          subsys_debug_fpga_m_master_translator_avalon_universal_master_0_write;           // subsys_debug_fpga_m_master_translator:uav_write -> subsys_debug_fpga_m_master_agent:av_write
	wire   [31:0] subsys_debug_fpga_m_master_translator_avalon_universal_master_0_writedata;       // subsys_debug_fpga_m_master_translator:uav_writedata -> subsys_debug_fpga_m_master_agent:av_writedata
	wire    [2:0] subsys_debug_fpga_m_master_translator_avalon_universal_master_0_burstcount;      // subsys_debug_fpga_m_master_translator:uav_burstcount -> subsys_debug_fpga_m_master_agent:av_burstcount
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_ruser;                                         // subsys_hps_hps2fpga_agent:ruser -> subsys_hps_hps2fpga_translator:m0_ruser
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_wuser;                                         // subsys_hps_hps2fpga_translator:m0_wuser -> subsys_hps_hps2fpga_agent:wuser
	wire    [1:0] subsys_hps_hps2fpga_translator_m0_awburst;                                       // subsys_hps_hps2fpga_translator:m0_awburst -> subsys_hps_hps2fpga_agent:awburst
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_arregion;                                      // subsys_hps_hps2fpga_translator:m0_arregion -> subsys_hps_hps2fpga_agent:arregion
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_awuser;                                        // subsys_hps_hps2fpga_translator:m0_awuser -> subsys_hps_hps2fpga_agent:awuser
	wire    [7:0] subsys_hps_hps2fpga_translator_m0_arlen;                                         // subsys_hps_hps2fpga_translator:m0_arlen -> subsys_hps_hps2fpga_agent:arlen
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_arqos;                                         // subsys_hps_hps2fpga_translator:m0_arqos -> subsys_hps_hps2fpga_agent:arqos
	wire   [15:0] subsys_hps_hps2fpga_translator_m0_wstrb;                                         // subsys_hps_hps2fpga_translator:m0_wstrb -> subsys_hps_hps2fpga_agent:wstrb
	wire          subsys_hps_hps2fpga_translator_m0_wready;                                        // subsys_hps_hps2fpga_agent:wready -> subsys_hps_hps2fpga_translator:m0_wready
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_rid;                                           // subsys_hps_hps2fpga_agent:rid -> subsys_hps_hps2fpga_translator:m0_rid
	wire          subsys_hps_hps2fpga_translator_m0_rready;                                        // subsys_hps_hps2fpga_translator:m0_rready -> subsys_hps_hps2fpga_agent:rready
	wire    [7:0] subsys_hps_hps2fpga_translator_m0_awlen;                                         // subsys_hps_hps2fpga_translator:m0_awlen -> subsys_hps_hps2fpga_agent:awlen
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_awqos;                                         // subsys_hps_hps2fpga_translator:m0_awqos -> subsys_hps_hps2fpga_agent:awqos
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_arcache;                                       // subsys_hps_hps2fpga_translator:m0_arcache -> subsys_hps_hps2fpga_agent:arcache
	wire          subsys_hps_hps2fpga_translator_m0_wvalid;                                        // subsys_hps_hps2fpga_translator:m0_wvalid -> subsys_hps_hps2fpga_agent:wvalid
	wire   [37:0] subsys_hps_hps2fpga_translator_m0_araddr;                                        // subsys_hps_hps2fpga_translator:m0_araddr -> subsys_hps_hps2fpga_agent:araddr
	wire    [2:0] subsys_hps_hps2fpga_translator_m0_arprot;                                        // subsys_hps_hps2fpga_translator:m0_arprot -> subsys_hps_hps2fpga_agent:arprot
	wire    [2:0] subsys_hps_hps2fpga_translator_m0_awprot;                                        // subsys_hps_hps2fpga_translator:m0_awprot -> subsys_hps_hps2fpga_agent:awprot
	wire  [127:0] subsys_hps_hps2fpga_translator_m0_wdata;                                         // subsys_hps_hps2fpga_translator:m0_wdata -> subsys_hps_hps2fpga_agent:wdata
	wire          subsys_hps_hps2fpga_translator_m0_arvalid;                                       // subsys_hps_hps2fpga_translator:m0_arvalid -> subsys_hps_hps2fpga_agent:arvalid
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_awcache;                                       // subsys_hps_hps2fpga_translator:m0_awcache -> subsys_hps_hps2fpga_agent:awcache
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_arid;                                          // subsys_hps_hps2fpga_translator:m0_arid -> subsys_hps_hps2fpga_agent:arid
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_arlock;                                        // subsys_hps_hps2fpga_translator:m0_arlock -> subsys_hps_hps2fpga_agent:arlock
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_awlock;                                        // subsys_hps_hps2fpga_translator:m0_awlock -> subsys_hps_hps2fpga_agent:awlock
	wire   [37:0] subsys_hps_hps2fpga_translator_m0_awaddr;                                        // subsys_hps_hps2fpga_translator:m0_awaddr -> subsys_hps_hps2fpga_agent:awaddr
	wire    [1:0] subsys_hps_hps2fpga_translator_m0_bresp;                                         // subsys_hps_hps2fpga_agent:bresp -> subsys_hps_hps2fpga_translator:m0_bresp
	wire          subsys_hps_hps2fpga_translator_m0_arready;                                       // subsys_hps_hps2fpga_agent:arready -> subsys_hps_hps2fpga_translator:m0_arready
	wire  [127:0] subsys_hps_hps2fpga_translator_m0_rdata;                                         // subsys_hps_hps2fpga_agent:rdata -> subsys_hps_hps2fpga_translator:m0_rdata
	wire          subsys_hps_hps2fpga_translator_m0_awready;                                       // subsys_hps_hps2fpga_agent:awready -> subsys_hps_hps2fpga_translator:m0_awready
	wire    [1:0] subsys_hps_hps2fpga_translator_m0_arburst;                                       // subsys_hps_hps2fpga_translator:m0_arburst -> subsys_hps_hps2fpga_agent:arburst
	wire    [2:0] subsys_hps_hps2fpga_translator_m0_arsize;                                        // subsys_hps_hps2fpga_translator:m0_arsize -> subsys_hps_hps2fpga_agent:arsize
	wire          subsys_hps_hps2fpga_translator_m0_bready;                                        // subsys_hps_hps2fpga_translator:m0_bready -> subsys_hps_hps2fpga_agent:bready
	wire          subsys_hps_hps2fpga_translator_m0_rlast;                                         // subsys_hps_hps2fpga_agent:rlast -> subsys_hps_hps2fpga_translator:m0_rlast
	wire          subsys_hps_hps2fpga_translator_m0_wlast;                                         // subsys_hps_hps2fpga_translator:m0_wlast -> subsys_hps_hps2fpga_agent:wlast
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_awregion;                                      // subsys_hps_hps2fpga_translator:m0_awregion -> subsys_hps_hps2fpga_agent:awregion
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_buser;                                         // subsys_hps_hps2fpga_agent:buser -> subsys_hps_hps2fpga_translator:m0_buser
	wire    [1:0] subsys_hps_hps2fpga_translator_m0_rresp;                                         // subsys_hps_hps2fpga_agent:rresp -> subsys_hps_hps2fpga_translator:m0_rresp
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_awid;                                          // subsys_hps_hps2fpga_translator:m0_awid -> subsys_hps_hps2fpga_agent:awid
	wire    [3:0] subsys_hps_hps2fpga_translator_m0_bid;                                           // subsys_hps_hps2fpga_agent:bid -> subsys_hps_hps2fpga_translator:m0_bid
	wire          subsys_hps_hps2fpga_translator_m0_bvalid;                                        // subsys_hps_hps2fpga_agent:bvalid -> subsys_hps_hps2fpga_translator:m0_bvalid
	wire    [2:0] subsys_hps_hps2fpga_translator_m0_awsize;                                        // subsys_hps_hps2fpga_translator:m0_awsize -> subsys_hps_hps2fpga_agent:awsize
	wire          subsys_hps_hps2fpga_translator_m0_awvalid;                                       // subsys_hps_hps2fpga_translator:m0_awvalid -> subsys_hps_hps2fpga_agent:awvalid
	wire    [0:0] subsys_hps_hps2fpga_translator_m0_aruser;                                        // subsys_hps_hps2fpga_translator:m0_aruser -> subsys_hps_hps2fpga_agent:aruser
	wire          subsys_hps_hps2fpga_translator_m0_rvalid;                                        // subsys_hps_hps2fpga_agent:rvalid -> subsys_hps_hps2fpga_translator:m0_rvalid
	wire          rsp_mux_001_src_valid;                                                           // rsp_mux_001:src_valid -> subsys_hps_hps2fpga_agent:write_rp_valid
	wire  [265:0] rsp_mux_001_src_data;                                                            // rsp_mux_001:src_data -> subsys_hps_hps2fpga_agent:write_rp_data
	wire          rsp_mux_001_src_ready;                                                           // subsys_hps_hps2fpga_agent:write_rp_ready -> rsp_mux_001:src_ready
	wire    [4:0] rsp_mux_001_src_channel;                                                         // rsp_mux_001:src_channel -> subsys_hps_hps2fpga_agent:write_rp_channel
	wire          rsp_mux_001_src_startofpacket;                                                   // rsp_mux_001:src_startofpacket -> subsys_hps_hps2fpga_agent:write_rp_startofpacket
	wire          rsp_mux_001_src_endofpacket;                                                     // rsp_mux_001:src_endofpacket -> subsys_hps_hps2fpga_agent:write_rp_endofpacket
	wire          rsp_mux_002_src_valid;                                                           // rsp_mux_002:src_valid -> subsys_hps_hps2fpga_agent:read_rp_valid
	wire  [265:0] rsp_mux_002_src_data;                                                            // rsp_mux_002:src_data -> subsys_hps_hps2fpga_agent:read_rp_data
	wire          rsp_mux_002_src_ready;                                                           // subsys_hps_hps2fpga_agent:read_rp_ready -> rsp_mux_002:src_ready
	wire    [4:0] rsp_mux_002_src_channel;                                                         // rsp_mux_002:src_channel -> subsys_hps_hps2fpga_agent:read_rp_channel
	wire          rsp_mux_002_src_startofpacket;                                                   // rsp_mux_002:src_startofpacket -> subsys_hps_hps2fpga_agent:read_rp_startofpacket
	wire          rsp_mux_002_src_endofpacket;                                                     // rsp_mux_002:src_endofpacket -> subsys_hps_hps2fpga_agent:read_rp_endofpacket
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_ruser;                                       // subsys_hps_lwhps2fpga_agent:ruser -> subsys_hps_lwhps2fpga_translator:m0_ruser
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_wuser;                                       // subsys_hps_lwhps2fpga_translator:m0_wuser -> subsys_hps_lwhps2fpga_agent:wuser
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_awburst;                                     // subsys_hps_lwhps2fpga_translator:m0_awburst -> subsys_hps_lwhps2fpga_agent:awburst
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arregion;                                    // subsys_hps_lwhps2fpga_translator:m0_arregion -> subsys_hps_lwhps2fpga_agent:arregion
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_awuser;                                      // subsys_hps_lwhps2fpga_translator:m0_awuser -> subsys_hps_lwhps2fpga_agent:awuser
	wire    [7:0] subsys_hps_lwhps2fpga_translator_m0_arlen;                                       // subsys_hps_lwhps2fpga_translator:m0_arlen -> subsys_hps_lwhps2fpga_agent:arlen
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arqos;                                       // subsys_hps_lwhps2fpga_translator:m0_arqos -> subsys_hps_lwhps2fpga_agent:arqos
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_wstrb;                                       // subsys_hps_lwhps2fpga_translator:m0_wstrb -> subsys_hps_lwhps2fpga_agent:wstrb
	wire          subsys_hps_lwhps2fpga_translator_m0_wready;                                      // subsys_hps_lwhps2fpga_agent:wready -> subsys_hps_lwhps2fpga_translator:m0_wready
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_rid;                                         // subsys_hps_lwhps2fpga_agent:rid -> subsys_hps_lwhps2fpga_translator:m0_rid
	wire          subsys_hps_lwhps2fpga_translator_m0_rready;                                      // subsys_hps_lwhps2fpga_translator:m0_rready -> subsys_hps_lwhps2fpga_agent:rready
	wire    [7:0] subsys_hps_lwhps2fpga_translator_m0_awlen;                                       // subsys_hps_lwhps2fpga_translator:m0_awlen -> subsys_hps_lwhps2fpga_agent:awlen
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awqos;                                       // subsys_hps_lwhps2fpga_translator:m0_awqos -> subsys_hps_lwhps2fpga_agent:awqos
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arcache;                                     // subsys_hps_lwhps2fpga_translator:m0_arcache -> subsys_hps_lwhps2fpga_agent:arcache
	wire          subsys_hps_lwhps2fpga_translator_m0_wvalid;                                      // subsys_hps_lwhps2fpga_translator:m0_wvalid -> subsys_hps_lwhps2fpga_agent:wvalid
	wire   [28:0] subsys_hps_lwhps2fpga_translator_m0_araddr;                                      // subsys_hps_lwhps2fpga_translator:m0_araddr -> subsys_hps_lwhps2fpga_agent:araddr
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_arprot;                                      // subsys_hps_lwhps2fpga_translator:m0_arprot -> subsys_hps_lwhps2fpga_agent:arprot
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_awprot;                                      // subsys_hps_lwhps2fpga_translator:m0_awprot -> subsys_hps_lwhps2fpga_agent:awprot
	wire   [31:0] subsys_hps_lwhps2fpga_translator_m0_wdata;                                       // subsys_hps_lwhps2fpga_translator:m0_wdata -> subsys_hps_lwhps2fpga_agent:wdata
	wire          subsys_hps_lwhps2fpga_translator_m0_arvalid;                                     // subsys_hps_lwhps2fpga_translator:m0_arvalid -> subsys_hps_lwhps2fpga_agent:arvalid
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awcache;                                     // subsys_hps_lwhps2fpga_translator:m0_awcache -> subsys_hps_lwhps2fpga_agent:awcache
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_arid;                                        // subsys_hps_lwhps2fpga_translator:m0_arid -> subsys_hps_lwhps2fpga_agent:arid
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_arlock;                                      // subsys_hps_lwhps2fpga_translator:m0_arlock -> subsys_hps_lwhps2fpga_agent:arlock
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_awlock;                                      // subsys_hps_lwhps2fpga_translator:m0_awlock -> subsys_hps_lwhps2fpga_agent:awlock
	wire   [28:0] subsys_hps_lwhps2fpga_translator_m0_awaddr;                                      // subsys_hps_lwhps2fpga_translator:m0_awaddr -> subsys_hps_lwhps2fpga_agent:awaddr
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_bresp;                                       // subsys_hps_lwhps2fpga_agent:bresp -> subsys_hps_lwhps2fpga_translator:m0_bresp
	wire          subsys_hps_lwhps2fpga_translator_m0_arready;                                     // subsys_hps_lwhps2fpga_agent:arready -> subsys_hps_lwhps2fpga_translator:m0_arready
	wire   [31:0] subsys_hps_lwhps2fpga_translator_m0_rdata;                                       // subsys_hps_lwhps2fpga_agent:rdata -> subsys_hps_lwhps2fpga_translator:m0_rdata
	wire          subsys_hps_lwhps2fpga_translator_m0_awready;                                     // subsys_hps_lwhps2fpga_agent:awready -> subsys_hps_lwhps2fpga_translator:m0_awready
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_arburst;                                     // subsys_hps_lwhps2fpga_translator:m0_arburst -> subsys_hps_lwhps2fpga_agent:arburst
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_arsize;                                      // subsys_hps_lwhps2fpga_translator:m0_arsize -> subsys_hps_lwhps2fpga_agent:arsize
	wire          subsys_hps_lwhps2fpga_translator_m0_bready;                                      // subsys_hps_lwhps2fpga_translator:m0_bready -> subsys_hps_lwhps2fpga_agent:bready
	wire          subsys_hps_lwhps2fpga_translator_m0_rlast;                                       // subsys_hps_lwhps2fpga_agent:rlast -> subsys_hps_lwhps2fpga_translator:m0_rlast
	wire          subsys_hps_lwhps2fpga_translator_m0_wlast;                                       // subsys_hps_lwhps2fpga_translator:m0_wlast -> subsys_hps_lwhps2fpga_agent:wlast
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awregion;                                    // subsys_hps_lwhps2fpga_translator:m0_awregion -> subsys_hps_lwhps2fpga_agent:awregion
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_buser;                                       // subsys_hps_lwhps2fpga_agent:buser -> subsys_hps_lwhps2fpga_translator:m0_buser
	wire    [1:0] subsys_hps_lwhps2fpga_translator_m0_rresp;                                       // subsys_hps_lwhps2fpga_agent:rresp -> subsys_hps_lwhps2fpga_translator:m0_rresp
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_awid;                                        // subsys_hps_lwhps2fpga_translator:m0_awid -> subsys_hps_lwhps2fpga_agent:awid
	wire    [3:0] subsys_hps_lwhps2fpga_translator_m0_bid;                                         // subsys_hps_lwhps2fpga_agent:bid -> subsys_hps_lwhps2fpga_translator:m0_bid
	wire          subsys_hps_lwhps2fpga_translator_m0_bvalid;                                      // subsys_hps_lwhps2fpga_agent:bvalid -> subsys_hps_lwhps2fpga_translator:m0_bvalid
	wire    [2:0] subsys_hps_lwhps2fpga_translator_m0_awsize;                                      // subsys_hps_lwhps2fpga_translator:m0_awsize -> subsys_hps_lwhps2fpga_agent:awsize
	wire          subsys_hps_lwhps2fpga_translator_m0_awvalid;                                     // subsys_hps_lwhps2fpga_translator:m0_awvalid -> subsys_hps_lwhps2fpga_agent:awvalid
	wire    [0:0] subsys_hps_lwhps2fpga_translator_m0_aruser;                                      // subsys_hps_lwhps2fpga_translator:m0_aruser -> subsys_hps_lwhps2fpga_agent:aruser
	wire          subsys_hps_lwhps2fpga_translator_m0_rvalid;                                      // subsys_hps_lwhps2fpga_agent:rvalid -> subsys_hps_lwhps2fpga_translator:m0_rvalid
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_ruser;                                        // ocm_axi_s1_translator:s0_ruser -> ocm_axi_s1_agent:ruser
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_wuser;                                        // ocm_axi_s1_agent:wuser -> ocm_axi_s1_translator:s0_wuser
	wire    [1:0] ocm_axi_s1_agent_altera_axi_master_awburst;                                      // ocm_axi_s1_agent:awburst -> ocm_axi_s1_translator:s0_awburst
	wire    [3:0] ocm_axi_s1_agent_altera_axi_master_arregion;                                     // ocm_axi_s1_agent:arregion -> ocm_axi_s1_translator:s0_arregion
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_awuser;                                       // ocm_axi_s1_agent:awuser -> ocm_axi_s1_translator:s0_awuser
	wire    [7:0] ocm_axi_s1_agent_altera_axi_master_arlen;                                        // ocm_axi_s1_agent:arlen -> ocm_axi_s1_translator:s0_arlen
	wire    [3:0] ocm_axi_s1_agent_altera_axi_master_arqos;                                        // ocm_axi_s1_agent:arqos -> ocm_axi_s1_translator:s0_arqos
	wire   [15:0] ocm_axi_s1_agent_altera_axi_master_wstrb;                                        // ocm_axi_s1_agent:wstrb -> ocm_axi_s1_translator:s0_wstrb
	wire          ocm_axi_s1_agent_altera_axi_master_wready;                                       // ocm_axi_s1_translator:s0_wready -> ocm_axi_s1_agent:wready
	wire    [9:0] ocm_axi_s1_agent_altera_axi_master_rid;                                          // ocm_axi_s1_translator:s0_rid -> ocm_axi_s1_agent:rid
	wire          ocm_axi_s1_agent_altera_axi_master_rready;                                       // ocm_axi_s1_agent:rready -> ocm_axi_s1_translator:s0_rready
	wire    [7:0] ocm_axi_s1_agent_altera_axi_master_awlen;                                        // ocm_axi_s1_agent:awlen -> ocm_axi_s1_translator:s0_awlen
	wire    [3:0] ocm_axi_s1_agent_altera_axi_master_awqos;                                        // ocm_axi_s1_agent:awqos -> ocm_axi_s1_translator:s0_awqos
	wire    [3:0] ocm_axi_s1_agent_altera_axi_master_arcache;                                      // ocm_axi_s1_agent:arcache -> ocm_axi_s1_translator:s0_arcache
	wire          ocm_axi_s1_agent_altera_axi_master_wvalid;                                       // ocm_axi_s1_agent:wvalid -> ocm_axi_s1_translator:s0_wvalid
	wire   [17:0] ocm_axi_s1_agent_altera_axi_master_araddr;                                       // ocm_axi_s1_agent:araddr -> ocm_axi_s1_translator:s0_araddr
	wire    [2:0] ocm_axi_s1_agent_altera_axi_master_arprot;                                       // ocm_axi_s1_agent:arprot -> ocm_axi_s1_translator:s0_arprot
	wire    [2:0] ocm_axi_s1_agent_altera_axi_master_awprot;                                       // ocm_axi_s1_agent:awprot -> ocm_axi_s1_translator:s0_awprot
	wire  [127:0] ocm_axi_s1_agent_altera_axi_master_wdata;                                        // ocm_axi_s1_agent:wdata -> ocm_axi_s1_translator:s0_wdata
	wire          ocm_axi_s1_agent_altera_axi_master_arvalid;                                      // ocm_axi_s1_agent:arvalid -> ocm_axi_s1_translator:s0_arvalid
	wire    [3:0] ocm_axi_s1_agent_altera_axi_master_awcache;                                      // ocm_axi_s1_agent:awcache -> ocm_axi_s1_translator:s0_awcache
	wire    [9:0] ocm_axi_s1_agent_altera_axi_master_arid;                                         // ocm_axi_s1_agent:arid -> ocm_axi_s1_translator:s0_arid
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_arlock;                                       // ocm_axi_s1_agent:arlock -> ocm_axi_s1_translator:s0_arlock
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_awlock;                                       // ocm_axi_s1_agent:awlock -> ocm_axi_s1_translator:s0_awlock
	wire   [17:0] ocm_axi_s1_agent_altera_axi_master_awaddr;                                       // ocm_axi_s1_agent:awaddr -> ocm_axi_s1_translator:s0_awaddr
	wire    [1:0] ocm_axi_s1_agent_altera_axi_master_bresp;                                        // ocm_axi_s1_translator:s0_bresp -> ocm_axi_s1_agent:bresp
	wire          ocm_axi_s1_agent_altera_axi_master_arready;                                      // ocm_axi_s1_translator:s0_arready -> ocm_axi_s1_agent:arready
	wire  [127:0] ocm_axi_s1_agent_altera_axi_master_rdata;                                        // ocm_axi_s1_translator:s0_rdata -> ocm_axi_s1_agent:rdata
	wire          ocm_axi_s1_agent_altera_axi_master_awready;                                      // ocm_axi_s1_translator:s0_awready -> ocm_axi_s1_agent:awready
	wire    [1:0] ocm_axi_s1_agent_altera_axi_master_arburst;                                      // ocm_axi_s1_agent:arburst -> ocm_axi_s1_translator:s0_arburst
	wire    [2:0] ocm_axi_s1_agent_altera_axi_master_arsize;                                       // ocm_axi_s1_agent:arsize -> ocm_axi_s1_translator:s0_arsize
	wire          ocm_axi_s1_agent_altera_axi_master_bready;                                       // ocm_axi_s1_agent:bready -> ocm_axi_s1_translator:s0_bready
	wire          ocm_axi_s1_agent_altera_axi_master_rlast;                                        // ocm_axi_s1_translator:s0_rlast -> ocm_axi_s1_agent:rlast
	wire          ocm_axi_s1_agent_altera_axi_master_wlast;                                        // ocm_axi_s1_agent:wlast -> ocm_axi_s1_translator:s0_wlast
	wire    [3:0] ocm_axi_s1_agent_altera_axi_master_awregion;                                     // ocm_axi_s1_agent:awregion -> ocm_axi_s1_translator:s0_awregion
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_buser;                                        // ocm_axi_s1_translator:s0_buser -> ocm_axi_s1_agent:buser
	wire    [1:0] ocm_axi_s1_agent_altera_axi_master_rresp;                                        // ocm_axi_s1_translator:s0_rresp -> ocm_axi_s1_agent:rresp
	wire    [9:0] ocm_axi_s1_agent_altera_axi_master_awid;                                         // ocm_axi_s1_agent:awid -> ocm_axi_s1_translator:s0_awid
	wire    [9:0] ocm_axi_s1_agent_altera_axi_master_bid;                                          // ocm_axi_s1_translator:s0_bid -> ocm_axi_s1_agent:bid
	wire          ocm_axi_s1_agent_altera_axi_master_bvalid;                                       // ocm_axi_s1_translator:s0_bvalid -> ocm_axi_s1_agent:bvalid
	wire    [2:0] ocm_axi_s1_agent_altera_axi_master_awsize;                                       // ocm_axi_s1_agent:awsize -> ocm_axi_s1_translator:s0_awsize
	wire          ocm_axi_s1_agent_altera_axi_master_awvalid;                                      // ocm_axi_s1_agent:awvalid -> ocm_axi_s1_translator:s0_awvalid
	wire    [0:0] ocm_axi_s1_agent_altera_axi_master_aruser;                                       // ocm_axi_s1_agent:aruser -> ocm_axi_s1_translator:s0_aruser
	wire          ocm_axi_s1_agent_altera_axi_master_rvalid;                                       // ocm_axi_s1_translator:s0_rvalid -> ocm_axi_s1_agent:rvalid
	wire   [31:0] subsys_hps_usb31_phy_reconfig_slave_agent_m0_readdata;                           // subsys_hps_usb31_phy_reconfig_slave_translator:uav_readdata -> subsys_hps_usb31_phy_reconfig_slave_agent:m0_readdata
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_m0_waitrequest;                        // subsys_hps_usb31_phy_reconfig_slave_translator:uav_waitrequest -> subsys_hps_usb31_phy_reconfig_slave_agent:m0_waitrequest
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_m0_debugaccess;                        // subsys_hps_usb31_phy_reconfig_slave_agent:m0_debugaccess -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_debugaccess
	wire   [37:0] subsys_hps_usb31_phy_reconfig_slave_agent_m0_address;                            // subsys_hps_usb31_phy_reconfig_slave_agent:m0_address -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_address
	wire    [3:0] subsys_hps_usb31_phy_reconfig_slave_agent_m0_byteenable;                         // subsys_hps_usb31_phy_reconfig_slave_agent:m0_byteenable -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_byteenable
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_m0_read;                               // subsys_hps_usb31_phy_reconfig_slave_agent:m0_read -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_read
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_m0_readdatavalid;                      // subsys_hps_usb31_phy_reconfig_slave_translator:uav_readdatavalid -> subsys_hps_usb31_phy_reconfig_slave_agent:m0_readdatavalid
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_m0_lock;                               // subsys_hps_usb31_phy_reconfig_slave_agent:m0_lock -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_lock
	wire   [31:0] subsys_hps_usb31_phy_reconfig_slave_agent_m0_writedata;                          // subsys_hps_usb31_phy_reconfig_slave_agent:m0_writedata -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_writedata
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_m0_write;                              // subsys_hps_usb31_phy_reconfig_slave_agent:m0_write -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_write
	wire    [2:0] subsys_hps_usb31_phy_reconfig_slave_agent_m0_burstcount;                         // subsys_hps_usb31_phy_reconfig_slave_agent:m0_burstcount -> subsys_hps_usb31_phy_reconfig_slave_translator:uav_burstcount
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_valid;                       // subsys_hps_usb31_phy_reconfig_slave_agent:rf_source_valid -> subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:in_valid
	wire  [158:0] subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_data;                        // subsys_hps_usb31_phy_reconfig_slave_agent:rf_source_data -> subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:in_data
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_ready;                       // subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:in_ready -> subsys_hps_usb31_phy_reconfig_slave_agent:rf_source_ready
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_startofpacket;               // subsys_hps_usb31_phy_reconfig_slave_agent:rf_source_startofpacket -> subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:in_startofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_endofpacket;                 // subsys_hps_usb31_phy_reconfig_slave_agent:rf_source_endofpacket -> subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:in_endofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_valid;                    // subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:out_valid -> subsys_hps_usb31_phy_reconfig_slave_agent:rf_sink_valid
	wire  [158:0] subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_data;                     // subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:out_data -> subsys_hps_usb31_phy_reconfig_slave_agent:rf_sink_data
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_ready;                    // subsys_hps_usb31_phy_reconfig_slave_agent:rf_sink_ready -> subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:out_ready
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_startofpacket;            // subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:out_startofpacket -> subsys_hps_usb31_phy_reconfig_slave_agent:rf_sink_startofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_endofpacket;              // subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo:out_endofpacket -> subsys_hps_usb31_phy_reconfig_slave_agent:rf_sink_endofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_valid;                  // subsys_hps_usb31_phy_reconfig_slave_agent:rdata_fifo_src_valid -> subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo:in_valid
	wire   [33:0] subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_data;                   // subsys_hps_usb31_phy_reconfig_slave_agent:rdata_fifo_src_data -> subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo:in_data
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_ready;                  // subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo:in_ready -> subsys_hps_usb31_phy_reconfig_slave_agent:rdata_fifo_src_ready
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_valid;                  // subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo:out_valid -> subsys_hps_usb31_phy_reconfig_slave_agent:rdata_fifo_sink_valid
	wire   [33:0] subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_data;                   // subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo:out_data -> subsys_hps_usb31_phy_reconfig_slave_agent:rdata_fifo_sink_data
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_ready;                  // subsys_hps_usb31_phy_reconfig_slave_agent:rdata_fifo_sink_ready -> subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo:out_ready
	wire   [31:0] subsys_periph_pb_cpu_0_s0_agent_m0_readdata;                                     // subsys_periph_pb_cpu_0_s0_translator:uav_readdata -> subsys_periph_pb_cpu_0_s0_agent:m0_readdata
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_waitrequest;                                  // subsys_periph_pb_cpu_0_s0_translator:uav_waitrequest -> subsys_periph_pb_cpu_0_s0_agent:m0_waitrequest
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_debugaccess;                                  // subsys_periph_pb_cpu_0_s0_agent:m0_debugaccess -> subsys_periph_pb_cpu_0_s0_translator:uav_debugaccess
	wire   [37:0] subsys_periph_pb_cpu_0_s0_agent_m0_address;                                      // subsys_periph_pb_cpu_0_s0_agent:m0_address -> subsys_periph_pb_cpu_0_s0_translator:uav_address
	wire    [3:0] subsys_periph_pb_cpu_0_s0_agent_m0_byteenable;                                   // subsys_periph_pb_cpu_0_s0_agent:m0_byteenable -> subsys_periph_pb_cpu_0_s0_translator:uav_byteenable
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_read;                                         // subsys_periph_pb_cpu_0_s0_agent:m0_read -> subsys_periph_pb_cpu_0_s0_translator:uav_read
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_readdatavalid;                                // subsys_periph_pb_cpu_0_s0_translator:uav_readdatavalid -> subsys_periph_pb_cpu_0_s0_agent:m0_readdatavalid
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_lock;                                         // subsys_periph_pb_cpu_0_s0_agent:m0_lock -> subsys_periph_pb_cpu_0_s0_translator:uav_lock
	wire   [31:0] subsys_periph_pb_cpu_0_s0_agent_m0_writedata;                                    // subsys_periph_pb_cpu_0_s0_agent:m0_writedata -> subsys_periph_pb_cpu_0_s0_translator:uav_writedata
	wire          subsys_periph_pb_cpu_0_s0_agent_m0_write;                                        // subsys_periph_pb_cpu_0_s0_agent:m0_write -> subsys_periph_pb_cpu_0_s0_translator:uav_write
	wire    [2:0] subsys_periph_pb_cpu_0_s0_agent_m0_burstcount;                                   // subsys_periph_pb_cpu_0_s0_agent:m0_burstcount -> subsys_periph_pb_cpu_0_s0_translator:uav_burstcount
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_valid;                                 // subsys_periph_pb_cpu_0_s0_agent:rf_source_valid -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_valid
	wire  [158:0] subsys_periph_pb_cpu_0_s0_agent_rf_source_data;                                  // subsys_periph_pb_cpu_0_s0_agent:rf_source_data -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_ready;                                 // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_ready -> subsys_periph_pb_cpu_0_s0_agent:rf_source_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_startofpacket;                         // subsys_periph_pb_cpu_0_s0_agent:rf_source_startofpacket -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rf_source_endofpacket;                           // subsys_periph_pb_cpu_0_s0_agent:rf_source_endofpacket -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:in_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_valid;                              // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_valid -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_valid
	wire  [158:0] subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_data;                               // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_data -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_ready;                              // subsys_periph_pb_cpu_0_s0_agent:rf_sink_ready -> subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_startofpacket;                      // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_startofpacket -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_endofpacket;                        // subsys_periph_pb_cpu_0_s0_agent_rsp_fifo:out_endofpacket -> subsys_periph_pb_cpu_0_s0_agent:rf_sink_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_valid;                            // subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_src_valid -> subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:in_valid
	wire   [33:0] subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_data;                             // subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_src_data -> subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:in_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_ready;                            // subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:in_ready -> subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_src_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_valid;                            // subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:out_valid -> subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_sink_valid
	wire   [33:0] subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_data;                             // subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:out_data -> subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_sink_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_ready;                            // subsys_periph_pb_cpu_0_s0_agent:rdata_fifo_sink_ready -> subsys_periph_pb_cpu_0_s0_agent_rdata_fifo:out_ready
	wire          subsys_debug_fpga_m_master_agent_cp_valid;                                       // subsys_debug_fpga_m_master_agent:cp_valid -> router:sink_valid
	wire  [157:0] subsys_debug_fpga_m_master_agent_cp_data;                                        // subsys_debug_fpga_m_master_agent:cp_data -> router:sink_data
	wire          subsys_debug_fpga_m_master_agent_cp_ready;                                       // router:sink_ready -> subsys_debug_fpga_m_master_agent:cp_ready
	wire          subsys_debug_fpga_m_master_agent_cp_startofpacket;                               // subsys_debug_fpga_m_master_agent:cp_startofpacket -> router:sink_startofpacket
	wire          subsys_debug_fpga_m_master_agent_cp_endofpacket;                                 // subsys_debug_fpga_m_master_agent:cp_endofpacket -> router:sink_endofpacket
	wire          subsys_hps_hps2fpga_agent_write_cp_valid;                                        // subsys_hps_hps2fpga_agent:write_cp_valid -> router_001:sink_valid
	wire  [265:0] subsys_hps_hps2fpga_agent_write_cp_data;                                         // subsys_hps_hps2fpga_agent:write_cp_data -> router_001:sink_data
	wire          subsys_hps_hps2fpga_agent_write_cp_ready;                                        // router_001:sink_ready -> subsys_hps_hps2fpga_agent:write_cp_ready
	wire          subsys_hps_hps2fpga_agent_write_cp_startofpacket;                                // subsys_hps_hps2fpga_agent:write_cp_startofpacket -> router_001:sink_startofpacket
	wire          subsys_hps_hps2fpga_agent_write_cp_endofpacket;                                  // subsys_hps_hps2fpga_agent:write_cp_endofpacket -> router_001:sink_endofpacket
	wire          router_001_src_valid;                                                            // router_001:src_valid -> cmd_demux_001:sink_valid
	wire  [265:0] router_001_src_data;                                                             // router_001:src_data -> cmd_demux_001:sink_data
	wire          router_001_src_ready;                                                            // cmd_demux_001:sink_ready -> router_001:src_ready
	wire    [4:0] router_001_src_channel;                                                          // router_001:src_channel -> cmd_demux_001:sink_channel
	wire          router_001_src_startofpacket;                                                    // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
	wire          router_001_src_endofpacket;                                                      // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
	wire          subsys_hps_hps2fpga_agent_read_cp_valid;                                         // subsys_hps_hps2fpga_agent:read_cp_valid -> router_002:sink_valid
	wire  [265:0] subsys_hps_hps2fpga_agent_read_cp_data;                                          // subsys_hps_hps2fpga_agent:read_cp_data -> router_002:sink_data
	wire          subsys_hps_hps2fpga_agent_read_cp_ready;                                         // router_002:sink_ready -> subsys_hps_hps2fpga_agent:read_cp_ready
	wire          subsys_hps_hps2fpga_agent_read_cp_startofpacket;                                 // subsys_hps_hps2fpga_agent:read_cp_startofpacket -> router_002:sink_startofpacket
	wire          subsys_hps_hps2fpga_agent_read_cp_endofpacket;                                   // subsys_hps_hps2fpga_agent:read_cp_endofpacket -> router_002:sink_endofpacket
	wire          router_002_src_valid;                                                            // router_002:src_valid -> cmd_demux_002:sink_valid
	wire  [265:0] router_002_src_data;                                                             // router_002:src_data -> cmd_demux_002:sink_data
	wire          router_002_src_ready;                                                            // cmd_demux_002:sink_ready -> router_002:src_ready
	wire    [4:0] router_002_src_channel;                                                          // router_002:src_channel -> cmd_demux_002:sink_channel
	wire          router_002_src_startofpacket;                                                    // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
	wire          router_002_src_endofpacket;                                                      // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
	wire          subsys_hps_lwhps2fpga_agent_write_cp_valid;                                      // subsys_hps_lwhps2fpga_agent:write_cp_valid -> router_003:sink_valid
	wire  [157:0] subsys_hps_lwhps2fpga_agent_write_cp_data;                                       // subsys_hps_lwhps2fpga_agent:write_cp_data -> router_003:sink_data
	wire          subsys_hps_lwhps2fpga_agent_write_cp_ready;                                      // router_003:sink_ready -> subsys_hps_lwhps2fpga_agent:write_cp_ready
	wire          subsys_hps_lwhps2fpga_agent_write_cp_startofpacket;                              // subsys_hps_lwhps2fpga_agent:write_cp_startofpacket -> router_003:sink_startofpacket
	wire          subsys_hps_lwhps2fpga_agent_write_cp_endofpacket;                                // subsys_hps_lwhps2fpga_agent:write_cp_endofpacket -> router_003:sink_endofpacket
	wire          subsys_hps_lwhps2fpga_agent_read_cp_valid;                                       // subsys_hps_lwhps2fpga_agent:read_cp_valid -> router_004:sink_valid
	wire  [157:0] subsys_hps_lwhps2fpga_agent_read_cp_data;                                        // subsys_hps_lwhps2fpga_agent:read_cp_data -> router_004:sink_data
	wire          subsys_hps_lwhps2fpga_agent_read_cp_ready;                                       // router_004:sink_ready -> subsys_hps_lwhps2fpga_agent:read_cp_ready
	wire          subsys_hps_lwhps2fpga_agent_read_cp_startofpacket;                               // subsys_hps_lwhps2fpga_agent:read_cp_startofpacket -> router_004:sink_startofpacket
	wire          subsys_hps_lwhps2fpga_agent_read_cp_endofpacket;                                 // subsys_hps_lwhps2fpga_agent:read_cp_endofpacket -> router_004:sink_endofpacket
	wire          router_005_src_valid;                                                            // router_005:src_valid -> rsp_demux:sink_valid
	wire  [265:0] router_005_src_data;                                                             // router_005:src_data -> rsp_demux:sink_data
	wire          router_005_src_ready;                                                            // rsp_demux:sink_ready -> router_005:src_ready
	wire    [4:0] router_005_src_channel;                                                          // router_005:src_channel -> rsp_demux:sink_channel
	wire          router_005_src_startofpacket;                                                    // router_005:src_startofpacket -> rsp_demux:sink_startofpacket
	wire          router_005_src_endofpacket;                                                      // router_005:src_endofpacket -> rsp_demux:sink_endofpacket
	wire          router_006_src_valid;                                                            // router_006:src_valid -> rsp_demux_001:sink_valid
	wire  [265:0] router_006_src_data;                                                             // router_006:src_data -> rsp_demux_001:sink_data
	wire          router_006_src_ready;                                                            // rsp_demux_001:sink_ready -> router_006:src_ready
	wire    [4:0] router_006_src_channel;                                                          // router_006:src_channel -> rsp_demux_001:sink_channel
	wire          router_006_src_startofpacket;                                                    // router_006:src_startofpacket -> rsp_demux_001:sink_startofpacket
	wire          router_006_src_endofpacket;                                                      // router_006:src_endofpacket -> rsp_demux_001:sink_endofpacket
	wire          router_007_src_valid;                                                            // router_007:src_valid -> rsp_demux_002:sink_valid
	wire  [157:0] router_007_src_data;                                                             // router_007:src_data -> rsp_demux_002:sink_data
	wire          router_007_src_ready;                                                            // rsp_demux_002:sink_ready -> router_007:src_ready
	wire    [4:0] router_007_src_channel;                                                          // router_007:src_channel -> rsp_demux_002:sink_channel
	wire          router_007_src_startofpacket;                                                    // router_007:src_startofpacket -> rsp_demux_002:sink_startofpacket
	wire          router_007_src_endofpacket;                                                      // router_007:src_endofpacket -> rsp_demux_002:sink_endofpacket
	wire          router_008_src_valid;                                                            // router_008:src_valid -> rsp_demux_003:sink_valid
	wire  [157:0] router_008_src_data;                                                             // router_008:src_data -> rsp_demux_003:sink_data
	wire          router_008_src_ready;                                                            // rsp_demux_003:sink_ready -> router_008:src_ready
	wire    [4:0] router_008_src_channel;                                                          // router_008:src_channel -> rsp_demux_003:sink_channel
	wire          router_008_src_startofpacket;                                                    // router_008:src_startofpacket -> rsp_demux_003:sink_startofpacket
	wire          router_008_src_endofpacket;                                                      // router_008:src_endofpacket -> rsp_demux_003:sink_endofpacket
	wire          router_src_valid;                                                                // router:src_valid -> subsys_debug_fpga_m_master_limiter:cmd_sink_valid
	wire  [157:0] router_src_data;                                                                 // router:src_data -> subsys_debug_fpga_m_master_limiter:cmd_sink_data
	wire          router_src_ready;                                                                // subsys_debug_fpga_m_master_limiter:cmd_sink_ready -> router:src_ready
	wire    [4:0] router_src_channel;                                                              // router:src_channel -> subsys_debug_fpga_m_master_limiter:cmd_sink_channel
	wire          router_src_startofpacket;                                                        // router:src_startofpacket -> subsys_debug_fpga_m_master_limiter:cmd_sink_startofpacket
	wire          router_src_endofpacket;                                                          // router:src_endofpacket -> subsys_debug_fpga_m_master_limiter:cmd_sink_endofpacket
	wire          subsys_debug_fpga_m_master_limiter_rsp_src_valid;                                // subsys_debug_fpga_m_master_limiter:rsp_src_valid -> subsys_debug_fpga_m_master_agent:rp_valid
	wire  [157:0] subsys_debug_fpga_m_master_limiter_rsp_src_data;                                 // subsys_debug_fpga_m_master_limiter:rsp_src_data -> subsys_debug_fpga_m_master_agent:rp_data
	wire          subsys_debug_fpga_m_master_limiter_rsp_src_ready;                                // subsys_debug_fpga_m_master_agent:rp_ready -> subsys_debug_fpga_m_master_limiter:rsp_src_ready
	wire    [4:0] subsys_debug_fpga_m_master_limiter_rsp_src_channel;                              // subsys_debug_fpga_m_master_limiter:rsp_src_channel -> subsys_debug_fpga_m_master_agent:rp_channel
	wire          subsys_debug_fpga_m_master_limiter_rsp_src_startofpacket;                        // subsys_debug_fpga_m_master_limiter:rsp_src_startofpacket -> subsys_debug_fpga_m_master_agent:rp_startofpacket
	wire          subsys_debug_fpga_m_master_limiter_rsp_src_endofpacket;                          // subsys_debug_fpga_m_master_limiter:rsp_src_endofpacket -> subsys_debug_fpga_m_master_agent:rp_endofpacket
	wire          router_003_src_valid;                                                            // router_003:src_valid -> subsys_hps_lwhps2fpga_wr_limiter:cmd_sink_valid
	wire  [157:0] router_003_src_data;                                                             // router_003:src_data -> subsys_hps_lwhps2fpga_wr_limiter:cmd_sink_data
	wire          router_003_src_ready;                                                            // subsys_hps_lwhps2fpga_wr_limiter:cmd_sink_ready -> router_003:src_ready
	wire    [4:0] router_003_src_channel;                                                          // router_003:src_channel -> subsys_hps_lwhps2fpga_wr_limiter:cmd_sink_channel
	wire          router_003_src_startofpacket;                                                    // router_003:src_startofpacket -> subsys_hps_lwhps2fpga_wr_limiter:cmd_sink_startofpacket
	wire          router_003_src_endofpacket;                                                      // router_003:src_endofpacket -> subsys_hps_lwhps2fpga_wr_limiter:cmd_sink_endofpacket
	wire          subsys_hps_lwhps2fpga_wr_limiter_rsp_src_valid;                                  // subsys_hps_lwhps2fpga_wr_limiter:rsp_src_valid -> subsys_hps_lwhps2fpga_agent:write_rp_valid
	wire  [157:0] subsys_hps_lwhps2fpga_wr_limiter_rsp_src_data;                                   // subsys_hps_lwhps2fpga_wr_limiter:rsp_src_data -> subsys_hps_lwhps2fpga_agent:write_rp_data
	wire          subsys_hps_lwhps2fpga_wr_limiter_rsp_src_ready;                                  // subsys_hps_lwhps2fpga_agent:write_rp_ready -> subsys_hps_lwhps2fpga_wr_limiter:rsp_src_ready
	wire    [4:0] subsys_hps_lwhps2fpga_wr_limiter_rsp_src_channel;                                // subsys_hps_lwhps2fpga_wr_limiter:rsp_src_channel -> subsys_hps_lwhps2fpga_agent:write_rp_channel
	wire          subsys_hps_lwhps2fpga_wr_limiter_rsp_src_startofpacket;                          // subsys_hps_lwhps2fpga_wr_limiter:rsp_src_startofpacket -> subsys_hps_lwhps2fpga_agent:write_rp_startofpacket
	wire          subsys_hps_lwhps2fpga_wr_limiter_rsp_src_endofpacket;                            // subsys_hps_lwhps2fpga_wr_limiter:rsp_src_endofpacket -> subsys_hps_lwhps2fpga_agent:write_rp_endofpacket
	wire          router_004_src_valid;                                                            // router_004:src_valid -> subsys_hps_lwhps2fpga_rd_limiter:cmd_sink_valid
	wire  [157:0] router_004_src_data;                                                             // router_004:src_data -> subsys_hps_lwhps2fpga_rd_limiter:cmd_sink_data
	wire          router_004_src_ready;                                                            // subsys_hps_lwhps2fpga_rd_limiter:cmd_sink_ready -> router_004:src_ready
	wire    [4:0] router_004_src_channel;                                                          // router_004:src_channel -> subsys_hps_lwhps2fpga_rd_limiter:cmd_sink_channel
	wire          router_004_src_startofpacket;                                                    // router_004:src_startofpacket -> subsys_hps_lwhps2fpga_rd_limiter:cmd_sink_startofpacket
	wire          router_004_src_endofpacket;                                                      // router_004:src_endofpacket -> subsys_hps_lwhps2fpga_rd_limiter:cmd_sink_endofpacket
	wire          subsys_hps_lwhps2fpga_rd_limiter_rsp_src_valid;                                  // subsys_hps_lwhps2fpga_rd_limiter:rsp_src_valid -> subsys_hps_lwhps2fpga_agent:read_rp_valid
	wire  [157:0] subsys_hps_lwhps2fpga_rd_limiter_rsp_src_data;                                   // subsys_hps_lwhps2fpga_rd_limiter:rsp_src_data -> subsys_hps_lwhps2fpga_agent:read_rp_data
	wire          subsys_hps_lwhps2fpga_rd_limiter_rsp_src_ready;                                  // subsys_hps_lwhps2fpga_agent:read_rp_ready -> subsys_hps_lwhps2fpga_rd_limiter:rsp_src_ready
	wire    [4:0] subsys_hps_lwhps2fpga_rd_limiter_rsp_src_channel;                                // subsys_hps_lwhps2fpga_rd_limiter:rsp_src_channel -> subsys_hps_lwhps2fpga_agent:read_rp_channel
	wire          subsys_hps_lwhps2fpga_rd_limiter_rsp_src_startofpacket;                          // subsys_hps_lwhps2fpga_rd_limiter:rsp_src_startofpacket -> subsys_hps_lwhps2fpga_agent:read_rp_startofpacket
	wire          subsys_hps_lwhps2fpga_rd_limiter_rsp_src_endofpacket;                            // subsys_hps_lwhps2fpga_rd_limiter:rsp_src_endofpacket -> subsys_hps_lwhps2fpga_agent:read_rp_endofpacket
	wire          cmd_mux_002_src_valid;                                                           // cmd_mux_002:src_valid -> subsys_hps_usb31_phy_reconfig_slave_burst_adapter:sink0_valid
	wire  [157:0] cmd_mux_002_src_data;                                                            // cmd_mux_002:src_data -> subsys_hps_usb31_phy_reconfig_slave_burst_adapter:sink0_data
	wire          cmd_mux_002_src_ready;                                                           // subsys_hps_usb31_phy_reconfig_slave_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
	wire    [4:0] cmd_mux_002_src_channel;                                                         // cmd_mux_002:src_channel -> subsys_hps_usb31_phy_reconfig_slave_burst_adapter:sink0_channel
	wire          cmd_mux_002_src_startofpacket;                                                   // cmd_mux_002:src_startofpacket -> subsys_hps_usb31_phy_reconfig_slave_burst_adapter:sink0_startofpacket
	wire          cmd_mux_002_src_endofpacket;                                                     // cmd_mux_002:src_endofpacket -> subsys_hps_usb31_phy_reconfig_slave_burst_adapter:sink0_endofpacket
	wire          cmd_mux_003_src_valid;                                                           // cmd_mux_003:src_valid -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_valid
	wire  [157:0] cmd_mux_003_src_data;                                                            // cmd_mux_003:src_data -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_data
	wire          cmd_mux_003_src_ready;                                                           // subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
	wire    [4:0] cmd_mux_003_src_channel;                                                         // cmd_mux_003:src_channel -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_channel
	wire          cmd_mux_003_src_startofpacket;                                                   // cmd_mux_003:src_startofpacket -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_startofpacket
	wire          cmd_mux_003_src_endofpacket;                                                     // cmd_mux_003:src_endofpacket -> subsys_periph_pb_cpu_0_s0_burst_adapter:sink0_endofpacket
	wire          cmd_demux_src0_valid;                                                            // cmd_demux:src0_valid -> subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:in_valid
	wire  [157:0] cmd_demux_src0_data;                                                             // cmd_demux:src0_data -> subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:in_data
	wire          cmd_demux_src0_ready;                                                            // subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:in_ready -> cmd_demux:src0_ready
	wire    [4:0] cmd_demux_src0_channel;                                                          // cmd_demux:src0_channel -> subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:in_channel
	wire          cmd_demux_src0_startofpacket;                                                    // cmd_demux:src0_startofpacket -> subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_src0_endofpacket;                                                      // cmd_demux:src0_endofpacket -> subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:in_endofpacket
	wire          cmd_demux_src1_valid;                                                            // cmd_demux:src1_valid -> subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:in_valid
	wire  [157:0] cmd_demux_src1_data;                                                             // cmd_demux:src1_data -> subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:in_data
	wire          cmd_demux_src1_ready;                                                            // subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:in_ready -> cmd_demux:src1_ready
	wire    [4:0] cmd_demux_src1_channel;                                                          // cmd_demux:src1_channel -> subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:in_channel
	wire          cmd_demux_src1_startofpacket;                                                    // cmd_demux:src1_startofpacket -> subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:in_startofpacket
	wire          cmd_demux_src1_endofpacket;                                                      // cmd_demux:src1_endofpacket -> subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:in_endofpacket
	wire          rsp_demux_src0_valid;                                                            // rsp_demux:src0_valid -> ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_valid
	wire  [265:0] rsp_demux_src0_data;                                                             // rsp_demux:src0_data -> ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_data
	wire          rsp_demux_src0_ready;                                                            // ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_ready -> rsp_demux:src0_ready
	wire    [4:0] rsp_demux_src0_channel;                                                          // rsp_demux:src0_channel -> ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_channel
	wire          rsp_demux_src0_startofpacket;                                                    // rsp_demux:src0_startofpacket -> ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_src0_endofpacket;                                                      // rsp_demux:src0_endofpacket -> ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_endofpacket
	wire          rsp_demux_001_src0_valid;                                                        // rsp_demux_001:src0_valid -> ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_valid
	wire  [265:0] rsp_demux_001_src0_data;                                                         // rsp_demux_001:src0_data -> ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_data
	wire          rsp_demux_001_src0_ready;                                                        // ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_ready -> rsp_demux_001:src0_ready
	wire    [4:0] rsp_demux_001_src0_channel;                                                      // rsp_demux_001:src0_channel -> ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_channel
	wire          rsp_demux_001_src0_startofpacket;                                                // rsp_demux_001:src0_startofpacket -> ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_startofpacket
	wire          rsp_demux_001_src0_endofpacket;                                                  // rsp_demux_001:src0_endofpacket -> ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:in_endofpacket
	wire    [0:0] subsys_debug_fpga_m_master_limiter_cmd_src_valid;                                // subsys_debug_fpga_m_master_limiter:cmd_src_valid -> limiter_pipeline:in_valid
	wire  [157:0] subsys_debug_fpga_m_master_limiter_cmd_src_data;                                 // subsys_debug_fpga_m_master_limiter:cmd_src_data -> limiter_pipeline:in_data
	wire          subsys_debug_fpga_m_master_limiter_cmd_src_ready;                                // limiter_pipeline:in_ready -> subsys_debug_fpga_m_master_limiter:cmd_src_ready
	wire    [4:0] subsys_debug_fpga_m_master_limiter_cmd_src_channel;                              // subsys_debug_fpga_m_master_limiter:cmd_src_channel -> limiter_pipeline:in_channel
	wire          subsys_debug_fpga_m_master_limiter_cmd_src_startofpacket;                        // subsys_debug_fpga_m_master_limiter:cmd_src_startofpacket -> limiter_pipeline:in_startofpacket
	wire          subsys_debug_fpga_m_master_limiter_cmd_src_endofpacket;                          // subsys_debug_fpga_m_master_limiter:cmd_src_endofpacket -> limiter_pipeline:in_endofpacket
	wire          limiter_pipeline_source0_valid;                                                  // limiter_pipeline:out_valid -> cmd_demux:sink_valid
	wire  [157:0] limiter_pipeline_source0_data;                                                   // limiter_pipeline:out_data -> cmd_demux:sink_data
	wire          limiter_pipeline_source0_ready;                                                  // cmd_demux:sink_ready -> limiter_pipeline:out_ready
	wire    [4:0] limiter_pipeline_source0_channel;                                                // limiter_pipeline:out_channel -> cmd_demux:sink_channel
	wire          limiter_pipeline_source0_startofpacket;                                          // limiter_pipeline:out_startofpacket -> cmd_demux:sink_startofpacket
	wire          limiter_pipeline_source0_endofpacket;                                            // limiter_pipeline:out_endofpacket -> cmd_demux:sink_endofpacket
	wire          rsp_mux_src_valid;                                                               // rsp_mux:src_valid -> limiter_pipeline_001:in_valid
	wire  [157:0] rsp_mux_src_data;                                                                // rsp_mux:src_data -> limiter_pipeline_001:in_data
	wire          rsp_mux_src_ready;                                                               // limiter_pipeline_001:in_ready -> rsp_mux:src_ready
	wire    [4:0] rsp_mux_src_channel;                                                             // rsp_mux:src_channel -> limiter_pipeline_001:in_channel
	wire          rsp_mux_src_startofpacket;                                                       // rsp_mux:src_startofpacket -> limiter_pipeline_001:in_startofpacket
	wire          rsp_mux_src_endofpacket;                                                         // rsp_mux:src_endofpacket -> limiter_pipeline_001:in_endofpacket
	wire          limiter_pipeline_001_source0_valid;                                              // limiter_pipeline_001:out_valid -> subsys_debug_fpga_m_master_limiter:rsp_sink_valid
	wire  [157:0] limiter_pipeline_001_source0_data;                                               // limiter_pipeline_001:out_data -> subsys_debug_fpga_m_master_limiter:rsp_sink_data
	wire          limiter_pipeline_001_source0_ready;                                              // subsys_debug_fpga_m_master_limiter:rsp_sink_ready -> limiter_pipeline_001:out_ready
	wire    [4:0] limiter_pipeline_001_source0_channel;                                            // limiter_pipeline_001:out_channel -> subsys_debug_fpga_m_master_limiter:rsp_sink_channel
	wire          limiter_pipeline_001_source0_startofpacket;                                      // limiter_pipeline_001:out_startofpacket -> subsys_debug_fpga_m_master_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_001_source0_endofpacket;                                        // limiter_pipeline_001:out_endofpacket -> subsys_debug_fpga_m_master_limiter:rsp_sink_endofpacket
	wire    [0:0] subsys_hps_lwhps2fpga_wr_limiter_cmd_src_valid;                                  // subsys_hps_lwhps2fpga_wr_limiter:cmd_src_valid -> limiter_pipeline_002:in_valid
	wire  [157:0] subsys_hps_lwhps2fpga_wr_limiter_cmd_src_data;                                   // subsys_hps_lwhps2fpga_wr_limiter:cmd_src_data -> limiter_pipeline_002:in_data
	wire          subsys_hps_lwhps2fpga_wr_limiter_cmd_src_ready;                                  // limiter_pipeline_002:in_ready -> subsys_hps_lwhps2fpga_wr_limiter:cmd_src_ready
	wire    [4:0] subsys_hps_lwhps2fpga_wr_limiter_cmd_src_channel;                                // subsys_hps_lwhps2fpga_wr_limiter:cmd_src_channel -> limiter_pipeline_002:in_channel
	wire          subsys_hps_lwhps2fpga_wr_limiter_cmd_src_startofpacket;                          // subsys_hps_lwhps2fpga_wr_limiter:cmd_src_startofpacket -> limiter_pipeline_002:in_startofpacket
	wire          subsys_hps_lwhps2fpga_wr_limiter_cmd_src_endofpacket;                            // subsys_hps_lwhps2fpga_wr_limiter:cmd_src_endofpacket -> limiter_pipeline_002:in_endofpacket
	wire          limiter_pipeline_002_source0_valid;                                              // limiter_pipeline_002:out_valid -> cmd_demux_003:sink_valid
	wire  [157:0] limiter_pipeline_002_source0_data;                                               // limiter_pipeline_002:out_data -> cmd_demux_003:sink_data
	wire          limiter_pipeline_002_source0_ready;                                              // cmd_demux_003:sink_ready -> limiter_pipeline_002:out_ready
	wire    [4:0] limiter_pipeline_002_source0_channel;                                            // limiter_pipeline_002:out_channel -> cmd_demux_003:sink_channel
	wire          limiter_pipeline_002_source0_startofpacket;                                      // limiter_pipeline_002:out_startofpacket -> cmd_demux_003:sink_startofpacket
	wire          limiter_pipeline_002_source0_endofpacket;                                        // limiter_pipeline_002:out_endofpacket -> cmd_demux_003:sink_endofpacket
	wire          rsp_mux_003_src_valid;                                                           // rsp_mux_003:src_valid -> limiter_pipeline_003:in_valid
	wire  [157:0] rsp_mux_003_src_data;                                                            // rsp_mux_003:src_data -> limiter_pipeline_003:in_data
	wire          rsp_mux_003_src_ready;                                                           // limiter_pipeline_003:in_ready -> rsp_mux_003:src_ready
	wire    [4:0] rsp_mux_003_src_channel;                                                         // rsp_mux_003:src_channel -> limiter_pipeline_003:in_channel
	wire          rsp_mux_003_src_startofpacket;                                                   // rsp_mux_003:src_startofpacket -> limiter_pipeline_003:in_startofpacket
	wire          rsp_mux_003_src_endofpacket;                                                     // rsp_mux_003:src_endofpacket -> limiter_pipeline_003:in_endofpacket
	wire          limiter_pipeline_003_source0_valid;                                              // limiter_pipeline_003:out_valid -> subsys_hps_lwhps2fpga_wr_limiter:rsp_sink_valid
	wire  [157:0] limiter_pipeline_003_source0_data;                                               // limiter_pipeline_003:out_data -> subsys_hps_lwhps2fpga_wr_limiter:rsp_sink_data
	wire          limiter_pipeline_003_source0_ready;                                              // subsys_hps_lwhps2fpga_wr_limiter:rsp_sink_ready -> limiter_pipeline_003:out_ready
	wire    [4:0] limiter_pipeline_003_source0_channel;                                            // limiter_pipeline_003:out_channel -> subsys_hps_lwhps2fpga_wr_limiter:rsp_sink_channel
	wire          limiter_pipeline_003_source0_startofpacket;                                      // limiter_pipeline_003:out_startofpacket -> subsys_hps_lwhps2fpga_wr_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_003_source0_endofpacket;                                        // limiter_pipeline_003:out_endofpacket -> subsys_hps_lwhps2fpga_wr_limiter:rsp_sink_endofpacket
	wire    [0:0] subsys_hps_lwhps2fpga_rd_limiter_cmd_src_valid;                                  // subsys_hps_lwhps2fpga_rd_limiter:cmd_src_valid -> limiter_pipeline_004:in_valid
	wire  [157:0] subsys_hps_lwhps2fpga_rd_limiter_cmd_src_data;                                   // subsys_hps_lwhps2fpga_rd_limiter:cmd_src_data -> limiter_pipeline_004:in_data
	wire          subsys_hps_lwhps2fpga_rd_limiter_cmd_src_ready;                                  // limiter_pipeline_004:in_ready -> subsys_hps_lwhps2fpga_rd_limiter:cmd_src_ready
	wire    [4:0] subsys_hps_lwhps2fpga_rd_limiter_cmd_src_channel;                                // subsys_hps_lwhps2fpga_rd_limiter:cmd_src_channel -> limiter_pipeline_004:in_channel
	wire          subsys_hps_lwhps2fpga_rd_limiter_cmd_src_startofpacket;                          // subsys_hps_lwhps2fpga_rd_limiter:cmd_src_startofpacket -> limiter_pipeline_004:in_startofpacket
	wire          subsys_hps_lwhps2fpga_rd_limiter_cmd_src_endofpacket;                            // subsys_hps_lwhps2fpga_rd_limiter:cmd_src_endofpacket -> limiter_pipeline_004:in_endofpacket
	wire          limiter_pipeline_004_source0_valid;                                              // limiter_pipeline_004:out_valid -> cmd_demux_004:sink_valid
	wire  [157:0] limiter_pipeline_004_source0_data;                                               // limiter_pipeline_004:out_data -> cmd_demux_004:sink_data
	wire          limiter_pipeline_004_source0_ready;                                              // cmd_demux_004:sink_ready -> limiter_pipeline_004:out_ready
	wire    [4:0] limiter_pipeline_004_source0_channel;                                            // limiter_pipeline_004:out_channel -> cmd_demux_004:sink_channel
	wire          limiter_pipeline_004_source0_startofpacket;                                      // limiter_pipeline_004:out_startofpacket -> cmd_demux_004:sink_startofpacket
	wire          limiter_pipeline_004_source0_endofpacket;                                        // limiter_pipeline_004:out_endofpacket -> cmd_demux_004:sink_endofpacket
	wire          rsp_mux_004_src_valid;                                                           // rsp_mux_004:src_valid -> limiter_pipeline_005:in_valid
	wire  [157:0] rsp_mux_004_src_data;                                                            // rsp_mux_004:src_data -> limiter_pipeline_005:in_data
	wire          rsp_mux_004_src_ready;                                                           // limiter_pipeline_005:in_ready -> rsp_mux_004:src_ready
	wire    [4:0] rsp_mux_004_src_channel;                                                         // rsp_mux_004:src_channel -> limiter_pipeline_005:in_channel
	wire          rsp_mux_004_src_startofpacket;                                                   // rsp_mux_004:src_startofpacket -> limiter_pipeline_005:in_startofpacket
	wire          rsp_mux_004_src_endofpacket;                                                     // rsp_mux_004:src_endofpacket -> limiter_pipeline_005:in_endofpacket
	wire          limiter_pipeline_005_source0_valid;                                              // limiter_pipeline_005:out_valid -> subsys_hps_lwhps2fpga_rd_limiter:rsp_sink_valid
	wire  [157:0] limiter_pipeline_005_source0_data;                                               // limiter_pipeline_005:out_data -> subsys_hps_lwhps2fpga_rd_limiter:rsp_sink_data
	wire          limiter_pipeline_005_source0_ready;                                              // subsys_hps_lwhps2fpga_rd_limiter:rsp_sink_ready -> limiter_pipeline_005:out_ready
	wire    [4:0] limiter_pipeline_005_source0_channel;                                            // limiter_pipeline_005:out_channel -> subsys_hps_lwhps2fpga_rd_limiter:rsp_sink_channel
	wire          limiter_pipeline_005_source0_startofpacket;                                      // limiter_pipeline_005:out_startofpacket -> subsys_hps_lwhps2fpga_rd_limiter:rsp_sink_startofpacket
	wire          limiter_pipeline_005_source0_endofpacket;                                        // limiter_pipeline_005:out_endofpacket -> subsys_hps_lwhps2fpga_rd_limiter:rsp_sink_endofpacket
	wire          cmd_mux_src_valid;                                                               // cmd_mux:src_valid -> agent_pipeline:in_valid
	wire  [265:0] cmd_mux_src_data;                                                                // cmd_mux:src_data -> agent_pipeline:in_data
	wire          cmd_mux_src_ready;                                                               // agent_pipeline:in_ready -> cmd_mux:src_ready
	wire    [4:0] cmd_mux_src_channel;                                                             // cmd_mux:src_channel -> agent_pipeline:in_channel
	wire          cmd_mux_src_startofpacket;                                                       // cmd_mux:src_startofpacket -> agent_pipeline:in_startofpacket
	wire          cmd_mux_src_endofpacket;                                                         // cmd_mux:src_endofpacket -> agent_pipeline:in_endofpacket
	wire          agent_pipeline_source0_valid;                                                    // agent_pipeline:out_valid -> ocm_axi_s1_agent:write_cp_valid
	wire  [265:0] agent_pipeline_source0_data;                                                     // agent_pipeline:out_data -> ocm_axi_s1_agent:write_cp_data
	wire          agent_pipeline_source0_ready;                                                    // ocm_axi_s1_agent:write_cp_ready -> agent_pipeline:out_ready
	wire    [4:0] agent_pipeline_source0_channel;                                                  // agent_pipeline:out_channel -> ocm_axi_s1_agent:write_cp_channel
	wire          agent_pipeline_source0_startofpacket;                                            // agent_pipeline:out_startofpacket -> ocm_axi_s1_agent:write_cp_startofpacket
	wire          agent_pipeline_source0_endofpacket;                                              // agent_pipeline:out_endofpacket -> ocm_axi_s1_agent:write_cp_endofpacket
	wire          cmd_mux_001_src_valid;                                                           // cmd_mux_001:src_valid -> agent_pipeline_001:in_valid
	wire  [265:0] cmd_mux_001_src_data;                                                            // cmd_mux_001:src_data -> agent_pipeline_001:in_data
	wire          cmd_mux_001_src_ready;                                                           // agent_pipeline_001:in_ready -> cmd_mux_001:src_ready
	wire    [4:0] cmd_mux_001_src_channel;                                                         // cmd_mux_001:src_channel -> agent_pipeline_001:in_channel
	wire          cmd_mux_001_src_startofpacket;                                                   // cmd_mux_001:src_startofpacket -> agent_pipeline_001:in_startofpacket
	wire          cmd_mux_001_src_endofpacket;                                                     // cmd_mux_001:src_endofpacket -> agent_pipeline_001:in_endofpacket
	wire          agent_pipeline_001_source0_valid;                                                // agent_pipeline_001:out_valid -> ocm_axi_s1_agent:read_cp_valid
	wire  [265:0] agent_pipeline_001_source0_data;                                                 // agent_pipeline_001:out_data -> ocm_axi_s1_agent:read_cp_data
	wire          agent_pipeline_001_source0_ready;                                                // ocm_axi_s1_agent:read_cp_ready -> agent_pipeline_001:out_ready
	wire    [4:0] agent_pipeline_001_source0_channel;                                              // agent_pipeline_001:out_channel -> ocm_axi_s1_agent:read_cp_channel
	wire          agent_pipeline_001_source0_startofpacket;                                        // agent_pipeline_001:out_startofpacket -> ocm_axi_s1_agent:read_cp_startofpacket
	wire          agent_pipeline_001_source0_endofpacket;                                          // agent_pipeline_001:out_endofpacket -> ocm_axi_s1_agent:read_cp_endofpacket
	wire          ocm_axi_s1_agent_write_rp_valid;                                                 // ocm_axi_s1_agent:write_rp_valid -> agent_pipeline_002:in_valid
	wire  [265:0] ocm_axi_s1_agent_write_rp_data;                                                  // ocm_axi_s1_agent:write_rp_data -> agent_pipeline_002:in_data
	wire          ocm_axi_s1_agent_write_rp_ready;                                                 // agent_pipeline_002:in_ready -> ocm_axi_s1_agent:write_rp_ready
	wire          ocm_axi_s1_agent_write_rp_startofpacket;                                         // ocm_axi_s1_agent:write_rp_startofpacket -> agent_pipeline_002:in_startofpacket
	wire          ocm_axi_s1_agent_write_rp_endofpacket;                                           // ocm_axi_s1_agent:write_rp_endofpacket -> agent_pipeline_002:in_endofpacket
	wire          agent_pipeline_002_source0_valid;                                                // agent_pipeline_002:out_valid -> router_005:sink_valid
	wire  [265:0] agent_pipeline_002_source0_data;                                                 // agent_pipeline_002:out_data -> router_005:sink_data
	wire          agent_pipeline_002_source0_ready;                                                // router_005:sink_ready -> agent_pipeline_002:out_ready
	wire          agent_pipeline_002_source0_startofpacket;                                        // agent_pipeline_002:out_startofpacket -> router_005:sink_startofpacket
	wire          agent_pipeline_002_source0_endofpacket;                                          // agent_pipeline_002:out_endofpacket -> router_005:sink_endofpacket
	wire          ocm_axi_s1_agent_read_rp_valid;                                                  // ocm_axi_s1_agent:read_rp_valid -> agent_pipeline_003:in_valid
	wire  [265:0] ocm_axi_s1_agent_read_rp_data;                                                   // ocm_axi_s1_agent:read_rp_data -> agent_pipeline_003:in_data
	wire          ocm_axi_s1_agent_read_rp_ready;                                                  // agent_pipeline_003:in_ready -> ocm_axi_s1_agent:read_rp_ready
	wire          ocm_axi_s1_agent_read_rp_startofpacket;                                          // ocm_axi_s1_agent:read_rp_startofpacket -> agent_pipeline_003:in_startofpacket
	wire          ocm_axi_s1_agent_read_rp_endofpacket;                                            // ocm_axi_s1_agent:read_rp_endofpacket -> agent_pipeline_003:in_endofpacket
	wire          agent_pipeline_003_source0_valid;                                                // agent_pipeline_003:out_valid -> router_006:sink_valid
	wire  [265:0] agent_pipeline_003_source0_data;                                                 // agent_pipeline_003:out_data -> router_006:sink_data
	wire          agent_pipeline_003_source0_ready;                                                // router_006:sink_ready -> agent_pipeline_003:out_ready
	wire          agent_pipeline_003_source0_startofpacket;                                        // agent_pipeline_003:out_startofpacket -> router_006:sink_startofpacket
	wire          agent_pipeline_003_source0_endofpacket;                                          // agent_pipeline_003:out_endofpacket -> router_006:sink_endofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_valid;                 // subsys_hps_usb31_phy_reconfig_slave_burst_adapter:source0_valid -> agent_pipeline_004:in_valid
	wire  [157:0] subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_data;                  // subsys_hps_usb31_phy_reconfig_slave_burst_adapter:source0_data -> agent_pipeline_004:in_data
	wire          subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_ready;                 // agent_pipeline_004:in_ready -> subsys_hps_usb31_phy_reconfig_slave_burst_adapter:source0_ready
	wire    [4:0] subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_channel;               // subsys_hps_usb31_phy_reconfig_slave_burst_adapter:source0_channel -> agent_pipeline_004:in_channel
	wire          subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_startofpacket;         // subsys_hps_usb31_phy_reconfig_slave_burst_adapter:source0_startofpacket -> agent_pipeline_004:in_startofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_endofpacket;           // subsys_hps_usb31_phy_reconfig_slave_burst_adapter:source0_endofpacket -> agent_pipeline_004:in_endofpacket
	wire          agent_pipeline_004_source0_valid;                                                // agent_pipeline_004:out_valid -> subsys_hps_usb31_phy_reconfig_slave_agent:cp_valid
	wire  [157:0] agent_pipeline_004_source0_data;                                                 // agent_pipeline_004:out_data -> subsys_hps_usb31_phy_reconfig_slave_agent:cp_data
	wire          agent_pipeline_004_source0_ready;                                                // subsys_hps_usb31_phy_reconfig_slave_agent:cp_ready -> agent_pipeline_004:out_ready
	wire    [4:0] agent_pipeline_004_source0_channel;                                              // agent_pipeline_004:out_channel -> subsys_hps_usb31_phy_reconfig_slave_agent:cp_channel
	wire          agent_pipeline_004_source0_startofpacket;                                        // agent_pipeline_004:out_startofpacket -> subsys_hps_usb31_phy_reconfig_slave_agent:cp_startofpacket
	wire          agent_pipeline_004_source0_endofpacket;                                          // agent_pipeline_004:out_endofpacket -> subsys_hps_usb31_phy_reconfig_slave_agent:cp_endofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rp_valid;                              // subsys_hps_usb31_phy_reconfig_slave_agent:rp_valid -> agent_pipeline_005:in_valid
	wire  [157:0] subsys_hps_usb31_phy_reconfig_slave_agent_rp_data;                               // subsys_hps_usb31_phy_reconfig_slave_agent:rp_data -> agent_pipeline_005:in_data
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rp_ready;                              // agent_pipeline_005:in_ready -> subsys_hps_usb31_phy_reconfig_slave_agent:rp_ready
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rp_startofpacket;                      // subsys_hps_usb31_phy_reconfig_slave_agent:rp_startofpacket -> agent_pipeline_005:in_startofpacket
	wire          subsys_hps_usb31_phy_reconfig_slave_agent_rp_endofpacket;                        // subsys_hps_usb31_phy_reconfig_slave_agent:rp_endofpacket -> agent_pipeline_005:in_endofpacket
	wire          agent_pipeline_005_source0_valid;                                                // agent_pipeline_005:out_valid -> router_007:sink_valid
	wire  [157:0] agent_pipeline_005_source0_data;                                                 // agent_pipeline_005:out_data -> router_007:sink_data
	wire          agent_pipeline_005_source0_ready;                                                // router_007:sink_ready -> agent_pipeline_005:out_ready
	wire          agent_pipeline_005_source0_startofpacket;                                        // agent_pipeline_005:out_startofpacket -> router_007:sink_startofpacket
	wire          agent_pipeline_005_source0_endofpacket;                                          // agent_pipeline_005:out_endofpacket -> router_007:sink_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_valid;                           // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_valid -> agent_pipeline_006:in_valid
	wire  [157:0] subsys_periph_pb_cpu_0_s0_burst_adapter_source0_data;                            // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_data -> agent_pipeline_006:in_data
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_ready;                           // agent_pipeline_006:in_ready -> subsys_periph_pb_cpu_0_s0_burst_adapter:source0_ready
	wire    [4:0] subsys_periph_pb_cpu_0_s0_burst_adapter_source0_channel;                         // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_channel -> agent_pipeline_006:in_channel
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_startofpacket;                   // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_startofpacket -> agent_pipeline_006:in_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_burst_adapter_source0_endofpacket;                     // subsys_periph_pb_cpu_0_s0_burst_adapter:source0_endofpacket -> agent_pipeline_006:in_endofpacket
	wire          agent_pipeline_006_source0_valid;                                                // agent_pipeline_006:out_valid -> subsys_periph_pb_cpu_0_s0_agent:cp_valid
	wire  [157:0] agent_pipeline_006_source0_data;                                                 // agent_pipeline_006:out_data -> subsys_periph_pb_cpu_0_s0_agent:cp_data
	wire          agent_pipeline_006_source0_ready;                                                // subsys_periph_pb_cpu_0_s0_agent:cp_ready -> agent_pipeline_006:out_ready
	wire    [4:0] agent_pipeline_006_source0_channel;                                              // agent_pipeline_006:out_channel -> subsys_periph_pb_cpu_0_s0_agent:cp_channel
	wire          agent_pipeline_006_source0_startofpacket;                                        // agent_pipeline_006:out_startofpacket -> subsys_periph_pb_cpu_0_s0_agent:cp_startofpacket
	wire          agent_pipeline_006_source0_endofpacket;                                          // agent_pipeline_006:out_endofpacket -> subsys_periph_pb_cpu_0_s0_agent:cp_endofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_valid;                                        // subsys_periph_pb_cpu_0_s0_agent:rp_valid -> agent_pipeline_007:in_valid
	wire  [157:0] subsys_periph_pb_cpu_0_s0_agent_rp_data;                                         // subsys_periph_pb_cpu_0_s0_agent:rp_data -> agent_pipeline_007:in_data
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_ready;                                        // agent_pipeline_007:in_ready -> subsys_periph_pb_cpu_0_s0_agent:rp_ready
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_startofpacket;                                // subsys_periph_pb_cpu_0_s0_agent:rp_startofpacket -> agent_pipeline_007:in_startofpacket
	wire          subsys_periph_pb_cpu_0_s0_agent_rp_endofpacket;                                  // subsys_periph_pb_cpu_0_s0_agent:rp_endofpacket -> agent_pipeline_007:in_endofpacket
	wire          agent_pipeline_007_source0_valid;                                                // agent_pipeline_007:out_valid -> router_008:sink_valid
	wire  [157:0] agent_pipeline_007_source0_data;                                                 // agent_pipeline_007:out_data -> router_008:sink_data
	wire          agent_pipeline_007_source0_ready;                                                // router_008:sink_ready -> agent_pipeline_007:out_ready
	wire          agent_pipeline_007_source0_startofpacket;                                        // agent_pipeline_007:out_startofpacket -> router_008:sink_startofpacket
	wire          agent_pipeline_007_source0_endofpacket;                                          // agent_pipeline_007:out_endofpacket -> router_008:sink_endofpacket
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_valid;         // subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:out_valid -> mux_pipeline:in_valid
	wire  [265:0] subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_data;          // subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:out_data -> mux_pipeline:in_data
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_ready;         // mux_pipeline:in_ready -> subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:out_ready
	wire    [4:0] subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_channel;       // subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:out_channel -> mux_pipeline:in_channel
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_startofpacket; // subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:out_startofpacket -> mux_pipeline:in_startofpacket
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_endofpacket;   // subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter:out_endofpacket -> mux_pipeline:in_endofpacket
	wire          mux_pipeline_source0_valid;                                                      // mux_pipeline:out_valid -> cmd_mux:sink0_valid
	wire  [265:0] mux_pipeline_source0_data;                                                       // mux_pipeline:out_data -> cmd_mux:sink0_data
	wire          mux_pipeline_source0_ready;                                                      // cmd_mux:sink0_ready -> mux_pipeline:out_ready
	wire    [4:0] mux_pipeline_source0_channel;                                                    // mux_pipeline:out_channel -> cmd_mux:sink0_channel
	wire          mux_pipeline_source0_startofpacket;                                              // mux_pipeline:out_startofpacket -> cmd_mux:sink0_startofpacket
	wire          mux_pipeline_source0_endofpacket;                                                // mux_pipeline:out_endofpacket -> cmd_mux:sink0_endofpacket
	wire          cmd_demux_001_src0_valid;                                                        // cmd_demux_001:src0_valid -> mux_pipeline_001:in_valid
	wire  [265:0] cmd_demux_001_src0_data;                                                         // cmd_demux_001:src0_data -> mux_pipeline_001:in_data
	wire          cmd_demux_001_src0_ready;                                                        // mux_pipeline_001:in_ready -> cmd_demux_001:src0_ready
	wire    [4:0] cmd_demux_001_src0_channel;                                                      // cmd_demux_001:src0_channel -> mux_pipeline_001:in_channel
	wire          cmd_demux_001_src0_startofpacket;                                                // cmd_demux_001:src0_startofpacket -> mux_pipeline_001:in_startofpacket
	wire          cmd_demux_001_src0_endofpacket;                                                  // cmd_demux_001:src0_endofpacket -> mux_pipeline_001:in_endofpacket
	wire          mux_pipeline_001_source0_valid;                                                  // mux_pipeline_001:out_valid -> cmd_mux:sink1_valid
	wire  [265:0] mux_pipeline_001_source0_data;                                                   // mux_pipeline_001:out_data -> cmd_mux:sink1_data
	wire          mux_pipeline_001_source0_ready;                                                  // cmd_mux:sink1_ready -> mux_pipeline_001:out_ready
	wire    [4:0] mux_pipeline_001_source0_channel;                                                // mux_pipeline_001:out_channel -> cmd_mux:sink1_channel
	wire          mux_pipeline_001_source0_startofpacket;                                          // mux_pipeline_001:out_startofpacket -> cmd_mux:sink1_startofpacket
	wire          mux_pipeline_001_source0_endofpacket;                                            // mux_pipeline_001:out_endofpacket -> cmd_mux:sink1_endofpacket
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_valid;         // subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:out_valid -> mux_pipeline_002:in_valid
	wire  [265:0] subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_data;          // subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:out_data -> mux_pipeline_002:in_data
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_ready;         // mux_pipeline_002:in_ready -> subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:out_ready
	wire    [4:0] subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_channel;       // subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:out_channel -> mux_pipeline_002:in_channel
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_startofpacket; // subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:out_startofpacket -> mux_pipeline_002:in_startofpacket
	wire          subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_endofpacket;   // subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter:out_endofpacket -> mux_pipeline_002:in_endofpacket
	wire          mux_pipeline_002_source0_valid;                                                  // mux_pipeline_002:out_valid -> cmd_mux_001:sink0_valid
	wire  [265:0] mux_pipeline_002_source0_data;                                                   // mux_pipeline_002:out_data -> cmd_mux_001:sink0_data
	wire          mux_pipeline_002_source0_ready;                                                  // cmd_mux_001:sink0_ready -> mux_pipeline_002:out_ready
	wire    [4:0] mux_pipeline_002_source0_channel;                                                // mux_pipeline_002:out_channel -> cmd_mux_001:sink0_channel
	wire          mux_pipeline_002_source0_startofpacket;                                          // mux_pipeline_002:out_startofpacket -> cmd_mux_001:sink0_startofpacket
	wire          mux_pipeline_002_source0_endofpacket;                                            // mux_pipeline_002:out_endofpacket -> cmd_mux_001:sink0_endofpacket
	wire          cmd_demux_002_src0_valid;                                                        // cmd_demux_002:src0_valid -> mux_pipeline_003:in_valid
	wire  [265:0] cmd_demux_002_src0_data;                                                         // cmd_demux_002:src0_data -> mux_pipeline_003:in_data
	wire          cmd_demux_002_src0_ready;                                                        // mux_pipeline_003:in_ready -> cmd_demux_002:src0_ready
	wire    [4:0] cmd_demux_002_src0_channel;                                                      // cmd_demux_002:src0_channel -> mux_pipeline_003:in_channel
	wire          cmd_demux_002_src0_startofpacket;                                                // cmd_demux_002:src0_startofpacket -> mux_pipeline_003:in_startofpacket
	wire          cmd_demux_002_src0_endofpacket;                                                  // cmd_demux_002:src0_endofpacket -> mux_pipeline_003:in_endofpacket
	wire          mux_pipeline_003_source0_valid;                                                  // mux_pipeline_003:out_valid -> cmd_mux_001:sink1_valid
	wire  [265:0] mux_pipeline_003_source0_data;                                                   // mux_pipeline_003:out_data -> cmd_mux_001:sink1_data
	wire          mux_pipeline_003_source0_ready;                                                  // cmd_mux_001:sink1_ready -> mux_pipeline_003:out_ready
	wire    [4:0] mux_pipeline_003_source0_channel;                                                // mux_pipeline_003:out_channel -> cmd_mux_001:sink1_channel
	wire          mux_pipeline_003_source0_startofpacket;                                          // mux_pipeline_003:out_startofpacket -> cmd_mux_001:sink1_startofpacket
	wire          mux_pipeline_003_source0_endofpacket;                                            // mux_pipeline_003:out_endofpacket -> cmd_mux_001:sink1_endofpacket
	wire          cmd_demux_src2_valid;                                                            // cmd_demux:src2_valid -> mux_pipeline_004:in_valid
	wire  [157:0] cmd_demux_src2_data;                                                             // cmd_demux:src2_data -> mux_pipeline_004:in_data
	wire          cmd_demux_src2_ready;                                                            // mux_pipeline_004:in_ready -> cmd_demux:src2_ready
	wire    [4:0] cmd_demux_src2_channel;                                                          // cmd_demux:src2_channel -> mux_pipeline_004:in_channel
	wire          cmd_demux_src2_startofpacket;                                                    // cmd_demux:src2_startofpacket -> mux_pipeline_004:in_startofpacket
	wire          cmd_demux_src2_endofpacket;                                                      // cmd_demux:src2_endofpacket -> mux_pipeline_004:in_endofpacket
	wire          mux_pipeline_004_source0_valid;                                                  // mux_pipeline_004:out_valid -> cmd_mux_002:sink0_valid
	wire  [157:0] mux_pipeline_004_source0_data;                                                   // mux_pipeline_004:out_data -> cmd_mux_002:sink0_data
	wire          mux_pipeline_004_source0_ready;                                                  // cmd_mux_002:sink0_ready -> mux_pipeline_004:out_ready
	wire    [4:0] mux_pipeline_004_source0_channel;                                                // mux_pipeline_004:out_channel -> cmd_mux_002:sink0_channel
	wire          mux_pipeline_004_source0_startofpacket;                                          // mux_pipeline_004:out_startofpacket -> cmd_mux_002:sink0_startofpacket
	wire          mux_pipeline_004_source0_endofpacket;                                            // mux_pipeline_004:out_endofpacket -> cmd_mux_002:sink0_endofpacket
	wire          cmd_demux_003_src0_valid;                                                        // cmd_demux_003:src0_valid -> mux_pipeline_005:in_valid
	wire  [157:0] cmd_demux_003_src0_data;                                                         // cmd_demux_003:src0_data -> mux_pipeline_005:in_data
	wire          cmd_demux_003_src0_ready;                                                        // mux_pipeline_005:in_ready -> cmd_demux_003:src0_ready
	wire    [4:0] cmd_demux_003_src0_channel;                                                      // cmd_demux_003:src0_channel -> mux_pipeline_005:in_channel
	wire          cmd_demux_003_src0_startofpacket;                                                // cmd_demux_003:src0_startofpacket -> mux_pipeline_005:in_startofpacket
	wire          cmd_demux_003_src0_endofpacket;                                                  // cmd_demux_003:src0_endofpacket -> mux_pipeline_005:in_endofpacket
	wire          mux_pipeline_005_source0_valid;                                                  // mux_pipeline_005:out_valid -> cmd_mux_002:sink1_valid
	wire  [157:0] mux_pipeline_005_source0_data;                                                   // mux_pipeline_005:out_data -> cmd_mux_002:sink1_data
	wire          mux_pipeline_005_source0_ready;                                                  // cmd_mux_002:sink1_ready -> mux_pipeline_005:out_ready
	wire    [4:0] mux_pipeline_005_source0_channel;                                                // mux_pipeline_005:out_channel -> cmd_mux_002:sink1_channel
	wire          mux_pipeline_005_source0_startofpacket;                                          // mux_pipeline_005:out_startofpacket -> cmd_mux_002:sink1_startofpacket
	wire          mux_pipeline_005_source0_endofpacket;                                            // mux_pipeline_005:out_endofpacket -> cmd_mux_002:sink1_endofpacket
	wire          cmd_demux_004_src0_valid;                                                        // cmd_demux_004:src0_valid -> mux_pipeline_006:in_valid
	wire  [157:0] cmd_demux_004_src0_data;                                                         // cmd_demux_004:src0_data -> mux_pipeline_006:in_data
	wire          cmd_demux_004_src0_ready;                                                        // mux_pipeline_006:in_ready -> cmd_demux_004:src0_ready
	wire    [4:0] cmd_demux_004_src0_channel;                                                      // cmd_demux_004:src0_channel -> mux_pipeline_006:in_channel
	wire          cmd_demux_004_src0_startofpacket;                                                // cmd_demux_004:src0_startofpacket -> mux_pipeline_006:in_startofpacket
	wire          cmd_demux_004_src0_endofpacket;                                                  // cmd_demux_004:src0_endofpacket -> mux_pipeline_006:in_endofpacket
	wire          mux_pipeline_006_source0_valid;                                                  // mux_pipeline_006:out_valid -> cmd_mux_002:sink2_valid
	wire  [157:0] mux_pipeline_006_source0_data;                                                   // mux_pipeline_006:out_data -> cmd_mux_002:sink2_data
	wire          mux_pipeline_006_source0_ready;                                                  // cmd_mux_002:sink2_ready -> mux_pipeline_006:out_ready
	wire    [4:0] mux_pipeline_006_source0_channel;                                                // mux_pipeline_006:out_channel -> cmd_mux_002:sink2_channel
	wire          mux_pipeline_006_source0_startofpacket;                                          // mux_pipeline_006:out_startofpacket -> cmd_mux_002:sink2_startofpacket
	wire          mux_pipeline_006_source0_endofpacket;                                            // mux_pipeline_006:out_endofpacket -> cmd_mux_002:sink2_endofpacket
	wire          cmd_demux_003_src1_valid;                                                        // cmd_demux_003:src1_valid -> mux_pipeline_007:in_valid
	wire  [157:0] cmd_demux_003_src1_data;                                                         // cmd_demux_003:src1_data -> mux_pipeline_007:in_data
	wire          cmd_demux_003_src1_ready;                                                        // mux_pipeline_007:in_ready -> cmd_demux_003:src1_ready
	wire    [4:0] cmd_demux_003_src1_channel;                                                      // cmd_demux_003:src1_channel -> mux_pipeline_007:in_channel
	wire          cmd_demux_003_src1_startofpacket;                                                // cmd_demux_003:src1_startofpacket -> mux_pipeline_007:in_startofpacket
	wire          cmd_demux_003_src1_endofpacket;                                                  // cmd_demux_003:src1_endofpacket -> mux_pipeline_007:in_endofpacket
	wire          mux_pipeline_007_source0_valid;                                                  // mux_pipeline_007:out_valid -> cmd_mux_003:sink0_valid
	wire  [157:0] mux_pipeline_007_source0_data;                                                   // mux_pipeline_007:out_data -> cmd_mux_003:sink0_data
	wire          mux_pipeline_007_source0_ready;                                                  // cmd_mux_003:sink0_ready -> mux_pipeline_007:out_ready
	wire    [4:0] mux_pipeline_007_source0_channel;                                                // mux_pipeline_007:out_channel -> cmd_mux_003:sink0_channel
	wire          mux_pipeline_007_source0_startofpacket;                                          // mux_pipeline_007:out_startofpacket -> cmd_mux_003:sink0_startofpacket
	wire          mux_pipeline_007_source0_endofpacket;                                            // mux_pipeline_007:out_endofpacket -> cmd_mux_003:sink0_endofpacket
	wire          cmd_demux_004_src1_valid;                                                        // cmd_demux_004:src1_valid -> mux_pipeline_008:in_valid
	wire  [157:0] cmd_demux_004_src1_data;                                                         // cmd_demux_004:src1_data -> mux_pipeline_008:in_data
	wire          cmd_demux_004_src1_ready;                                                        // mux_pipeline_008:in_ready -> cmd_demux_004:src1_ready
	wire    [4:0] cmd_demux_004_src1_channel;                                                      // cmd_demux_004:src1_channel -> mux_pipeline_008:in_channel
	wire          cmd_demux_004_src1_startofpacket;                                                // cmd_demux_004:src1_startofpacket -> mux_pipeline_008:in_startofpacket
	wire          cmd_demux_004_src1_endofpacket;                                                  // cmd_demux_004:src1_endofpacket -> mux_pipeline_008:in_endofpacket
	wire          mux_pipeline_008_source0_valid;                                                  // mux_pipeline_008:out_valid -> cmd_mux_003:sink1_valid
	wire  [157:0] mux_pipeline_008_source0_data;                                                   // mux_pipeline_008:out_data -> cmd_mux_003:sink1_data
	wire          mux_pipeline_008_source0_ready;                                                  // cmd_mux_003:sink1_ready -> mux_pipeline_008:out_ready
	wire    [4:0] mux_pipeline_008_source0_channel;                                                // mux_pipeline_008:out_channel -> cmd_mux_003:sink1_channel
	wire          mux_pipeline_008_source0_startofpacket;                                          // mux_pipeline_008:out_startofpacket -> cmd_mux_003:sink1_startofpacket
	wire          mux_pipeline_008_source0_endofpacket;                                            // mux_pipeline_008:out_endofpacket -> cmd_mux_003:sink1_endofpacket
	wire          ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_valid;         // ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_valid -> mux_pipeline_009:in_valid
	wire  [157:0] ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_data;          // ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_data -> mux_pipeline_009:in_data
	wire          ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_ready;         // mux_pipeline_009:in_ready -> ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_ready
	wire    [4:0] ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_channel;       // ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_channel -> mux_pipeline_009:in_channel
	wire          ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_startofpacket; // ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_startofpacket -> mux_pipeline_009:in_startofpacket
	wire          ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_endofpacket;   // ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_endofpacket -> mux_pipeline_009:in_endofpacket
	wire          mux_pipeline_009_source0_valid;                                                  // mux_pipeline_009:out_valid -> rsp_mux:sink0_valid
	wire  [157:0] mux_pipeline_009_source0_data;                                                   // mux_pipeline_009:out_data -> rsp_mux:sink0_data
	wire          mux_pipeline_009_source0_ready;                                                  // rsp_mux:sink0_ready -> mux_pipeline_009:out_ready
	wire    [4:0] mux_pipeline_009_source0_channel;                                                // mux_pipeline_009:out_channel -> rsp_mux:sink0_channel
	wire          mux_pipeline_009_source0_startofpacket;                                          // mux_pipeline_009:out_startofpacket -> rsp_mux:sink0_startofpacket
	wire          mux_pipeline_009_source0_endofpacket;                                            // mux_pipeline_009:out_endofpacket -> rsp_mux:sink0_endofpacket
	wire          ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_valid;         // ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_valid -> mux_pipeline_010:in_valid
	wire  [157:0] ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_data;          // ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_data -> mux_pipeline_010:in_data
	wire          ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_ready;         // mux_pipeline_010:in_ready -> ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_ready
	wire    [4:0] ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_channel;       // ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_channel -> mux_pipeline_010:in_channel
	wire          ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_startofpacket; // ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_startofpacket -> mux_pipeline_010:in_startofpacket
	wire          ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_endofpacket;   // ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter:out_endofpacket -> mux_pipeline_010:in_endofpacket
	wire          mux_pipeline_010_source0_valid;                                                  // mux_pipeline_010:out_valid -> rsp_mux:sink1_valid
	wire  [157:0] mux_pipeline_010_source0_data;                                                   // mux_pipeline_010:out_data -> rsp_mux:sink1_data
	wire          mux_pipeline_010_source0_ready;                                                  // rsp_mux:sink1_ready -> mux_pipeline_010:out_ready
	wire    [4:0] mux_pipeline_010_source0_channel;                                                // mux_pipeline_010:out_channel -> rsp_mux:sink1_channel
	wire          mux_pipeline_010_source0_startofpacket;                                          // mux_pipeline_010:out_startofpacket -> rsp_mux:sink1_startofpacket
	wire          mux_pipeline_010_source0_endofpacket;                                            // mux_pipeline_010:out_endofpacket -> rsp_mux:sink1_endofpacket
	wire          rsp_demux_002_src0_valid;                                                        // rsp_demux_002:src0_valid -> mux_pipeline_011:in_valid
	wire  [157:0] rsp_demux_002_src0_data;                                                         // rsp_demux_002:src0_data -> mux_pipeline_011:in_data
	wire          rsp_demux_002_src0_ready;                                                        // mux_pipeline_011:in_ready -> rsp_demux_002:src0_ready
	wire    [4:0] rsp_demux_002_src0_channel;                                                      // rsp_demux_002:src0_channel -> mux_pipeline_011:in_channel
	wire          rsp_demux_002_src0_startofpacket;                                                // rsp_demux_002:src0_startofpacket -> mux_pipeline_011:in_startofpacket
	wire          rsp_demux_002_src0_endofpacket;                                                  // rsp_demux_002:src0_endofpacket -> mux_pipeline_011:in_endofpacket
	wire          mux_pipeline_011_source0_valid;                                                  // mux_pipeline_011:out_valid -> rsp_mux:sink2_valid
	wire  [157:0] mux_pipeline_011_source0_data;                                                   // mux_pipeline_011:out_data -> rsp_mux:sink2_data
	wire          mux_pipeline_011_source0_ready;                                                  // rsp_mux:sink2_ready -> mux_pipeline_011:out_ready
	wire    [4:0] mux_pipeline_011_source0_channel;                                                // mux_pipeline_011:out_channel -> rsp_mux:sink2_channel
	wire          mux_pipeline_011_source0_startofpacket;                                          // mux_pipeline_011:out_startofpacket -> rsp_mux:sink2_startofpacket
	wire          mux_pipeline_011_source0_endofpacket;                                            // mux_pipeline_011:out_endofpacket -> rsp_mux:sink2_endofpacket
	wire          rsp_demux_src1_valid;                                                            // rsp_demux:src1_valid -> mux_pipeline_012:in_valid
	wire  [265:0] rsp_demux_src1_data;                                                             // rsp_demux:src1_data -> mux_pipeline_012:in_data
	wire          rsp_demux_src1_ready;                                                            // mux_pipeline_012:in_ready -> rsp_demux:src1_ready
	wire    [4:0] rsp_demux_src1_channel;                                                          // rsp_demux:src1_channel -> mux_pipeline_012:in_channel
	wire          rsp_demux_src1_startofpacket;                                                    // rsp_demux:src1_startofpacket -> mux_pipeline_012:in_startofpacket
	wire          rsp_demux_src1_endofpacket;                                                      // rsp_demux:src1_endofpacket -> mux_pipeline_012:in_endofpacket
	wire          mux_pipeline_012_source0_valid;                                                  // mux_pipeline_012:out_valid -> rsp_mux_001:sink0_valid
	wire  [265:0] mux_pipeline_012_source0_data;                                                   // mux_pipeline_012:out_data -> rsp_mux_001:sink0_data
	wire          mux_pipeline_012_source0_ready;                                                  // rsp_mux_001:sink0_ready -> mux_pipeline_012:out_ready
	wire    [4:0] mux_pipeline_012_source0_channel;                                                // mux_pipeline_012:out_channel -> rsp_mux_001:sink0_channel
	wire          mux_pipeline_012_source0_startofpacket;                                          // mux_pipeline_012:out_startofpacket -> rsp_mux_001:sink0_startofpacket
	wire          mux_pipeline_012_source0_endofpacket;                                            // mux_pipeline_012:out_endofpacket -> rsp_mux_001:sink0_endofpacket
	wire          rsp_demux_001_src1_valid;                                                        // rsp_demux_001:src1_valid -> mux_pipeline_013:in_valid
	wire  [265:0] rsp_demux_001_src1_data;                                                         // rsp_demux_001:src1_data -> mux_pipeline_013:in_data
	wire          rsp_demux_001_src1_ready;                                                        // mux_pipeline_013:in_ready -> rsp_demux_001:src1_ready
	wire    [4:0] rsp_demux_001_src1_channel;                                                      // rsp_demux_001:src1_channel -> mux_pipeline_013:in_channel
	wire          rsp_demux_001_src1_startofpacket;                                                // rsp_demux_001:src1_startofpacket -> mux_pipeline_013:in_startofpacket
	wire          rsp_demux_001_src1_endofpacket;                                                  // rsp_demux_001:src1_endofpacket -> mux_pipeline_013:in_endofpacket
	wire          mux_pipeline_013_source0_valid;                                                  // mux_pipeline_013:out_valid -> rsp_mux_002:sink0_valid
	wire  [265:0] mux_pipeline_013_source0_data;                                                   // mux_pipeline_013:out_data -> rsp_mux_002:sink0_data
	wire          mux_pipeline_013_source0_ready;                                                  // rsp_mux_002:sink0_ready -> mux_pipeline_013:out_ready
	wire    [4:0] mux_pipeline_013_source0_channel;                                                // mux_pipeline_013:out_channel -> rsp_mux_002:sink0_channel
	wire          mux_pipeline_013_source0_startofpacket;                                          // mux_pipeline_013:out_startofpacket -> rsp_mux_002:sink0_startofpacket
	wire          mux_pipeline_013_source0_endofpacket;                                            // mux_pipeline_013:out_endofpacket -> rsp_mux_002:sink0_endofpacket
	wire          rsp_demux_002_src1_valid;                                                        // rsp_demux_002:src1_valid -> mux_pipeline_014:in_valid
	wire  [157:0] rsp_demux_002_src1_data;                                                         // rsp_demux_002:src1_data -> mux_pipeline_014:in_data
	wire          rsp_demux_002_src1_ready;                                                        // mux_pipeline_014:in_ready -> rsp_demux_002:src1_ready
	wire    [4:0] rsp_demux_002_src1_channel;                                                      // rsp_demux_002:src1_channel -> mux_pipeline_014:in_channel
	wire          rsp_demux_002_src1_startofpacket;                                                // rsp_demux_002:src1_startofpacket -> mux_pipeline_014:in_startofpacket
	wire          rsp_demux_002_src1_endofpacket;                                                  // rsp_demux_002:src1_endofpacket -> mux_pipeline_014:in_endofpacket
	wire          mux_pipeline_014_source0_valid;                                                  // mux_pipeline_014:out_valid -> rsp_mux_003:sink0_valid
	wire  [157:0] mux_pipeline_014_source0_data;                                                   // mux_pipeline_014:out_data -> rsp_mux_003:sink0_data
	wire          mux_pipeline_014_source0_ready;                                                  // rsp_mux_003:sink0_ready -> mux_pipeline_014:out_ready
	wire    [4:0] mux_pipeline_014_source0_channel;                                                // mux_pipeline_014:out_channel -> rsp_mux_003:sink0_channel
	wire          mux_pipeline_014_source0_startofpacket;                                          // mux_pipeline_014:out_startofpacket -> rsp_mux_003:sink0_startofpacket
	wire          mux_pipeline_014_source0_endofpacket;                                            // mux_pipeline_014:out_endofpacket -> rsp_mux_003:sink0_endofpacket
	wire          rsp_demux_003_src0_valid;                                                        // rsp_demux_003:src0_valid -> mux_pipeline_015:in_valid
	wire  [157:0] rsp_demux_003_src0_data;                                                         // rsp_demux_003:src0_data -> mux_pipeline_015:in_data
	wire          rsp_demux_003_src0_ready;                                                        // mux_pipeline_015:in_ready -> rsp_demux_003:src0_ready
	wire    [4:0] rsp_demux_003_src0_channel;                                                      // rsp_demux_003:src0_channel -> mux_pipeline_015:in_channel
	wire          rsp_demux_003_src0_startofpacket;                                                // rsp_demux_003:src0_startofpacket -> mux_pipeline_015:in_startofpacket
	wire          rsp_demux_003_src0_endofpacket;                                                  // rsp_demux_003:src0_endofpacket -> mux_pipeline_015:in_endofpacket
	wire          mux_pipeline_015_source0_valid;                                                  // mux_pipeline_015:out_valid -> rsp_mux_003:sink1_valid
	wire  [157:0] mux_pipeline_015_source0_data;                                                   // mux_pipeline_015:out_data -> rsp_mux_003:sink1_data
	wire          mux_pipeline_015_source0_ready;                                                  // rsp_mux_003:sink1_ready -> mux_pipeline_015:out_ready
	wire    [4:0] mux_pipeline_015_source0_channel;                                                // mux_pipeline_015:out_channel -> rsp_mux_003:sink1_channel
	wire          mux_pipeline_015_source0_startofpacket;                                          // mux_pipeline_015:out_startofpacket -> rsp_mux_003:sink1_startofpacket
	wire          mux_pipeline_015_source0_endofpacket;                                            // mux_pipeline_015:out_endofpacket -> rsp_mux_003:sink1_endofpacket
	wire          rsp_demux_002_src2_valid;                                                        // rsp_demux_002:src2_valid -> mux_pipeline_016:in_valid
	wire  [157:0] rsp_demux_002_src2_data;                                                         // rsp_demux_002:src2_data -> mux_pipeline_016:in_data
	wire          rsp_demux_002_src2_ready;                                                        // mux_pipeline_016:in_ready -> rsp_demux_002:src2_ready
	wire    [4:0] rsp_demux_002_src2_channel;                                                      // rsp_demux_002:src2_channel -> mux_pipeline_016:in_channel
	wire          rsp_demux_002_src2_startofpacket;                                                // rsp_demux_002:src2_startofpacket -> mux_pipeline_016:in_startofpacket
	wire          rsp_demux_002_src2_endofpacket;                                                  // rsp_demux_002:src2_endofpacket -> mux_pipeline_016:in_endofpacket
	wire          mux_pipeline_016_source0_valid;                                                  // mux_pipeline_016:out_valid -> rsp_mux_004:sink0_valid
	wire  [157:0] mux_pipeline_016_source0_data;                                                   // mux_pipeline_016:out_data -> rsp_mux_004:sink0_data
	wire          mux_pipeline_016_source0_ready;                                                  // rsp_mux_004:sink0_ready -> mux_pipeline_016:out_ready
	wire    [4:0] mux_pipeline_016_source0_channel;                                                // mux_pipeline_016:out_channel -> rsp_mux_004:sink0_channel
	wire          mux_pipeline_016_source0_startofpacket;                                          // mux_pipeline_016:out_startofpacket -> rsp_mux_004:sink0_startofpacket
	wire          mux_pipeline_016_source0_endofpacket;                                            // mux_pipeline_016:out_endofpacket -> rsp_mux_004:sink0_endofpacket
	wire          rsp_demux_003_src1_valid;                                                        // rsp_demux_003:src1_valid -> mux_pipeline_017:in_valid
	wire  [157:0] rsp_demux_003_src1_data;                                                         // rsp_demux_003:src1_data -> mux_pipeline_017:in_data
	wire          rsp_demux_003_src1_ready;                                                        // mux_pipeline_017:in_ready -> rsp_demux_003:src1_ready
	wire    [4:0] rsp_demux_003_src1_channel;                                                      // rsp_demux_003:src1_channel -> mux_pipeline_017:in_channel
	wire          rsp_demux_003_src1_startofpacket;                                                // rsp_demux_003:src1_startofpacket -> mux_pipeline_017:in_startofpacket
	wire          rsp_demux_003_src1_endofpacket;                                                  // rsp_demux_003:src1_endofpacket -> mux_pipeline_017:in_endofpacket
	wire          mux_pipeline_017_source0_valid;                                                  // mux_pipeline_017:out_valid -> rsp_mux_004:sink1_valid
	wire  [157:0] mux_pipeline_017_source0_data;                                                   // mux_pipeline_017:out_data -> rsp_mux_004:sink1_data
	wire          mux_pipeline_017_source0_ready;                                                  // rsp_mux_004:sink1_ready -> mux_pipeline_017:out_ready
	wire    [4:0] mux_pipeline_017_source0_channel;                                                // mux_pipeline_017:out_channel -> rsp_mux_004:sink1_channel
	wire          mux_pipeline_017_source0_startofpacket;                                          // mux_pipeline_017:out_startofpacket -> rsp_mux_004:sink1_startofpacket
	wire          mux_pipeline_017_source0_endofpacket;                                            // mux_pipeline_017:out_endofpacket -> rsp_mux_004:sink1_endofpacket

	qsys_top_altera_merlin_master_translator_192_lykd4la #(
		.AV_ADDRESS_W                (32),
		.AV_DATA_W                   (32),
		.AV_BURSTCOUNT_W             (1),
		.AV_BYTEENABLE_W             (4),
		.UAV_ADDRESS_W               (38),
		.UAV_BURSTCOUNT_W            (3),
		.USE_READ                    (1),
		.USE_WRITE                   (1),
		.USE_BEGINBURSTTRANSFER      (0),
		.USE_BEGINTRANSFER           (0),
		.USE_CHIPSELECT              (0),
		.USE_BURSTCOUNT              (0),
		.USE_READDATAVALID           (1),
		.USE_WAITREQUEST             (1),
		.USE_READRESPONSE            (0),
		.USE_WRITERESPONSE           (0),
		.AV_SYMBOLS_PER_WORD         (4),
		.AV_ADDRESS_SYMBOLS          (1),
		.AV_BURSTCOUNT_SYMBOLS       (0),
		.AV_CONSTANT_BURST_BEHAVIOR  (0),
		.UAV_CONSTANT_BURST_BEHAVIOR (0),
		.AV_LINEWRAPBURSTS           (0),
		.AV_REGISTERINCOMINGSIGNALS  (0),
		.SYNC_RESET                  (1),
		.WAITREQUEST_ALLOWANCE       (0),
		.USE_OUTPUTENABLE            (0)
	) subsys_debug_fpga_m_master_translator (
		.clk                    (clk_100_out_clk_clk),                                                           //   input,   width = 1,                       clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),                                //   input,   width = 1,                     reset.reset
		.uav_address            (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_address),       //  output,  width = 38, avalon_universal_master_0.address
		.uav_burstcount         (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_burstcount),    //  output,   width = 3,                          .burstcount
		.uav_read               (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_read),          //  output,   width = 1,                          .read
		.uav_write              (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_write),         //  output,   width = 1,                          .write
		.uav_waitrequest        (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_waitrequest),   //   input,   width = 1,                          .waitrequest
		.uav_readdatavalid      (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_readdatavalid), //   input,   width = 1,                          .readdatavalid
		.uav_byteenable         (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_byteenable),    //  output,   width = 4,                          .byteenable
		.uav_readdata           (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_readdata),      //   input,  width = 32,                          .readdata
		.uav_writedata          (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_writedata),     //  output,  width = 32,                          .writedata
		.uav_lock               (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_lock),          //  output,   width = 1,                          .lock
		.uav_debugaccess        (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_debugaccess),   //  output,   width = 1,                          .debugaccess
		.av_address             (subsys_debug_fpga_m_master_address),                                            //   input,  width = 32,      avalon_anti_master_0.address
		.av_waitrequest         (subsys_debug_fpga_m_master_waitrequest),                                        //  output,   width = 1,                          .waitrequest
		.av_byteenable          (subsys_debug_fpga_m_master_byteenable),                                         //   input,   width = 4,                          .byteenable
		.av_read                (subsys_debug_fpga_m_master_read),                                               //   input,   width = 1,                          .read
		.av_readdata            (subsys_debug_fpga_m_master_readdata),                                           //  output,  width = 32,                          .readdata
		.av_readdatavalid       (subsys_debug_fpga_m_master_readdatavalid),                                      //  output,   width = 1,                          .readdatavalid
		.av_write               (subsys_debug_fpga_m_master_write),                                              //   input,   width = 1,                          .write
		.av_writedata           (subsys_debug_fpga_m_master_writedata),                                          //   input,  width = 32,                          .writedata
		.av_burstcount          (1'b1),                                                                          // (terminated),                                        
		.av_beginbursttransfer  (1'b0),                                                                          // (terminated),                                        
		.av_begintransfer       (1'b0),                                                                          // (terminated),                                        
		.av_chipselect          (1'b0),                                                                          // (terminated),                                        
		.av_lock                (1'b0),                                                                          // (terminated),                                        
		.av_debugaccess         (1'b0),                                                                          // (terminated),                                        
		.uav_outputenable       (1'b0),                                                                          // (terminated),                                        
		.uav_clken              (),                                                                              // (terminated),                                        
		.av_clken               (1'b1),                                                                          // (terminated),                                        
		.uav_response           (2'b00),                                                                         // (terminated),                                        
		.av_response            (),                                                                              // (terminated),                                        
		.uav_writeresponsevalid (1'b0),                                                                          // (terminated),                                        
		.av_writeresponsevalid  ()                                                                               // (terminated),                                        
	);

	qsys_top_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (4),
		.DATA_WIDTH                        (128),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (4),
		.M0_ADDR_WIDTH                     (38),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (38),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) subsys_hps_hps2fpga_translator (
		.aclk              (clk_100_out_clk_clk),                             //   input,    width = 1,       clk.clk
		.aresetn           (~subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset_n
		.m0_awid           (subsys_hps_hps2fpga_translator_m0_awid),          //  output,    width = 4,        m0.awid
		.m0_awaddr         (subsys_hps_hps2fpga_translator_m0_awaddr),        //  output,   width = 38,          .awaddr
		.m0_awlen          (subsys_hps_hps2fpga_translator_m0_awlen),         //  output,    width = 8,          .awlen
		.m0_awsize         (subsys_hps_hps2fpga_translator_m0_awsize),        //  output,    width = 3,          .awsize
		.m0_awburst        (subsys_hps_hps2fpga_translator_m0_awburst),       //  output,    width = 2,          .awburst
		.m0_awlock         (subsys_hps_hps2fpga_translator_m0_awlock),        //  output,    width = 1,          .awlock
		.m0_awcache        (subsys_hps_hps2fpga_translator_m0_awcache),       //  output,    width = 4,          .awcache
		.m0_awprot         (subsys_hps_hps2fpga_translator_m0_awprot),        //  output,    width = 3,          .awprot
		.m0_awuser         (subsys_hps_hps2fpga_translator_m0_awuser),        //  output,    width = 1,          .awuser
		.m0_awqos          (subsys_hps_hps2fpga_translator_m0_awqos),         //  output,    width = 4,          .awqos
		.m0_awregion       (subsys_hps_hps2fpga_translator_m0_awregion),      //  output,    width = 4,          .awregion
		.m0_awvalid        (subsys_hps_hps2fpga_translator_m0_awvalid),       //  output,    width = 1,          .awvalid
		.m0_awready        (subsys_hps_hps2fpga_translator_m0_awready),       //   input,    width = 1,          .awready
		.m0_wdata          (subsys_hps_hps2fpga_translator_m0_wdata),         //  output,  width = 128,          .wdata
		.m0_wstrb          (subsys_hps_hps2fpga_translator_m0_wstrb),         //  output,   width = 16,          .wstrb
		.m0_wlast          (subsys_hps_hps2fpga_translator_m0_wlast),         //  output,    width = 1,          .wlast
		.m0_wvalid         (subsys_hps_hps2fpga_translator_m0_wvalid),        //  output,    width = 1,          .wvalid
		.m0_wuser          (subsys_hps_hps2fpga_translator_m0_wuser),         //  output,    width = 1,          .wuser
		.m0_wready         (subsys_hps_hps2fpga_translator_m0_wready),        //   input,    width = 1,          .wready
		.m0_bid            (subsys_hps_hps2fpga_translator_m0_bid),           //   input,    width = 4,          .bid
		.m0_bresp          (subsys_hps_hps2fpga_translator_m0_bresp),         //   input,    width = 2,          .bresp
		.m0_buser          (subsys_hps_hps2fpga_translator_m0_buser),         //   input,    width = 1,          .buser
		.m0_bvalid         (subsys_hps_hps2fpga_translator_m0_bvalid),        //   input,    width = 1,          .bvalid
		.m0_bready         (subsys_hps_hps2fpga_translator_m0_bready),        //  output,    width = 1,          .bready
		.m0_arid           (subsys_hps_hps2fpga_translator_m0_arid),          //  output,    width = 4,          .arid
		.m0_araddr         (subsys_hps_hps2fpga_translator_m0_araddr),        //  output,   width = 38,          .araddr
		.m0_arlen          (subsys_hps_hps2fpga_translator_m0_arlen),         //  output,    width = 8,          .arlen
		.m0_arsize         (subsys_hps_hps2fpga_translator_m0_arsize),        //  output,    width = 3,          .arsize
		.m0_arburst        (subsys_hps_hps2fpga_translator_m0_arburst),       //  output,    width = 2,          .arburst
		.m0_arlock         (subsys_hps_hps2fpga_translator_m0_arlock),        //  output,    width = 1,          .arlock
		.m0_arcache        (subsys_hps_hps2fpga_translator_m0_arcache),       //  output,    width = 4,          .arcache
		.m0_arprot         (subsys_hps_hps2fpga_translator_m0_arprot),        //  output,    width = 3,          .arprot
		.m0_aruser         (subsys_hps_hps2fpga_translator_m0_aruser),        //  output,    width = 1,          .aruser
		.m0_arqos          (subsys_hps_hps2fpga_translator_m0_arqos),         //  output,    width = 4,          .arqos
		.m0_arregion       (subsys_hps_hps2fpga_translator_m0_arregion),      //  output,    width = 4,          .arregion
		.m0_arvalid        (subsys_hps_hps2fpga_translator_m0_arvalid),       //  output,    width = 1,          .arvalid
		.m0_arready        (subsys_hps_hps2fpga_translator_m0_arready),       //   input,    width = 1,          .arready
		.m0_rid            (subsys_hps_hps2fpga_translator_m0_rid),           //   input,    width = 4,          .rid
		.m0_rdata          (subsys_hps_hps2fpga_translator_m0_rdata),         //   input,  width = 128,          .rdata
		.m0_rresp          (subsys_hps_hps2fpga_translator_m0_rresp),         //   input,    width = 2,          .rresp
		.m0_rlast          (subsys_hps_hps2fpga_translator_m0_rlast),         //   input,    width = 1,          .rlast
		.m0_rvalid         (subsys_hps_hps2fpga_translator_m0_rvalid),        //   input,    width = 1,          .rvalid
		.m0_rready         (subsys_hps_hps2fpga_translator_m0_rready),        //  output,    width = 1,          .rready
		.m0_ruser          (subsys_hps_hps2fpga_translator_m0_ruser),         //   input,    width = 1,          .ruser
		.s0_awid           (subsys_hps_hps2fpga_awid),                        //   input,    width = 4,        s0.awid
		.s0_awaddr         (subsys_hps_hps2fpga_awaddr),                      //   input,   width = 38,          .awaddr
		.s0_awlen          (subsys_hps_hps2fpga_awlen),                       //   input,    width = 8,          .awlen
		.s0_awsize         (subsys_hps_hps2fpga_awsize),                      //   input,    width = 3,          .awsize
		.s0_awburst        (subsys_hps_hps2fpga_awburst),                     //   input,    width = 2,          .awburst
		.s0_awlock         (subsys_hps_hps2fpga_awlock),                      //   input,    width = 1,          .awlock
		.s0_awcache        (subsys_hps_hps2fpga_awcache),                     //   input,    width = 4,          .awcache
		.s0_awprot         (subsys_hps_hps2fpga_awprot),                      //   input,    width = 3,          .awprot
		.s0_awvalid        (subsys_hps_hps2fpga_awvalid),                     //   input,    width = 1,          .awvalid
		.s0_awready        (subsys_hps_hps2fpga_awready),                     //  output,    width = 1,          .awready
		.s0_wdata          (subsys_hps_hps2fpga_wdata),                       //   input,  width = 128,          .wdata
		.s0_wstrb          (subsys_hps_hps2fpga_wstrb),                       //   input,   width = 16,          .wstrb
		.s0_wlast          (subsys_hps_hps2fpga_wlast),                       //   input,    width = 1,          .wlast
		.s0_wvalid         (subsys_hps_hps2fpga_wvalid),                      //   input,    width = 1,          .wvalid
		.s0_wready         (subsys_hps_hps2fpga_wready),                      //  output,    width = 1,          .wready
		.s0_bid            (subsys_hps_hps2fpga_bid),                         //  output,    width = 4,          .bid
		.s0_bresp          (subsys_hps_hps2fpga_bresp),                       //  output,    width = 2,          .bresp
		.s0_bvalid         (subsys_hps_hps2fpga_bvalid),                      //  output,    width = 1,          .bvalid
		.s0_bready         (subsys_hps_hps2fpga_bready),                      //   input,    width = 1,          .bready
		.s0_arid           (subsys_hps_hps2fpga_arid),                        //   input,    width = 4,          .arid
		.s0_araddr         (subsys_hps_hps2fpga_araddr),                      //   input,   width = 38,          .araddr
		.s0_arlen          (subsys_hps_hps2fpga_arlen),                       //   input,    width = 8,          .arlen
		.s0_arsize         (subsys_hps_hps2fpga_arsize),                      //   input,    width = 3,          .arsize
		.s0_arburst        (subsys_hps_hps2fpga_arburst),                     //   input,    width = 2,          .arburst
		.s0_arlock         (subsys_hps_hps2fpga_arlock),                      //   input,    width = 1,          .arlock
		.s0_arcache        (subsys_hps_hps2fpga_arcache),                     //   input,    width = 4,          .arcache
		.s0_arprot         (subsys_hps_hps2fpga_arprot),                      //   input,    width = 3,          .arprot
		.s0_arvalid        (subsys_hps_hps2fpga_arvalid),                     //   input,    width = 1,          .arvalid
		.s0_arready        (subsys_hps_hps2fpga_arready),                     //  output,    width = 1,          .arready
		.s0_rid            (subsys_hps_hps2fpga_rid),                         //  output,    width = 4,          .rid
		.s0_rdata          (subsys_hps_hps2fpga_rdata),                       //  output,  width = 128,          .rdata
		.s0_rresp          (subsys_hps_hps2fpga_rresp),                       //  output,    width = 2,          .rresp
		.s0_rlast          (subsys_hps_hps2fpga_rlast),                       //  output,    width = 1,          .rlast
		.s0_rvalid         (subsys_hps_hps2fpga_rvalid),                      //  output,    width = 1,          .rvalid
		.s0_rready         (subsys_hps_hps2fpga_rready),                      //   input,    width = 1,          .rready
		.m0_awuser_addrchk (),                                                // (terminated),                         
		.m0_awuser_sai     (),                                                // (terminated),                         
		.m0_wuser_datachk  (),                                                // (terminated),                         
		.m0_wuser_data     (),                                                // (terminated),                         
		.m0_wuser_poison   (),                                                // (terminated),                         
		.m0_aruser_addrchk (),                                                // (terminated),                         
		.m0_aruser_sai     (),                                                // (terminated),                         
		.m0_ruser_datachk  (16'b0000000000000000),                            // (terminated),                         
		.m0_ruser_data     (4'b0000),                                         // (terminated),                         
		.m0_ruser_poison   (2'b00),                                           // (terminated),                         
		.s0_awuser         (1'b0),                                            // (terminated),                         
		.s0_awuser_addrchk (4'b0000),                                         // (terminated),                         
		.s0_awuser_sai     (4'b0000),                                         // (terminated),                         
		.s0_awqos          (4'b0000),                                         // (terminated),                         
		.s0_awregion       (4'b0000),                                         // (terminated),                         
		.s0_wuser          (1'b0),                                            // (terminated),                         
		.s0_wuser_datachk  (16'b0000000000000000),                            // (terminated),                         
		.s0_wuser_data     (4'b0000),                                         // (terminated),                         
		.s0_wuser_poison   (2'b00),                                           // (terminated),                         
		.s0_buser          (),                                                // (terminated),                         
		.s0_aruser         (1'b0),                                            // (terminated),                         
		.s0_aruser_addrchk (4'b0000),                                         // (terminated),                         
		.s0_aruser_sai     (4'b0000),                                         // (terminated),                         
		.s0_arqos          (4'b0000),                                         // (terminated),                         
		.s0_arregion       (4'b0000),                                         // (terminated),                         
		.s0_ruser          (),                                                // (terminated),                         
		.s0_ruser_datachk  (),                                                // (terminated),                         
		.s0_ruser_data     (),                                                // (terminated),                         
		.s0_ruser_poison   (),                                                // (terminated),                         
		.s0_wid            (4'b0000),                                         // (terminated),                         
		.s0_ardomain       (2'b00),                                           // (terminated),                         
		.s0_arsnoop        (4'b0000),                                         // (terminated),                         
		.s0_arbar          (2'b00),                                           // (terminated),                         
		.s0_awdomain       (2'b00),                                           // (terminated),                         
		.s0_awsnoop        (3'b000),                                          // (terminated),                         
		.s0_awbar          (2'b00),                                           // (terminated),                         
		.s0_awunique       (1'b0),                                            // (terminated),                         
		.m0_wid            (),                                                // (terminated),                         
		.m0_ardomain       (),                                                // (terminated),                         
		.m0_arsnoop        (),                                                // (terminated),                         
		.m0_arbar          (),                                                // (terminated),                         
		.m0_awdomain       (),                                                // (terminated),                         
		.m0_awsnoop        (),                                                // (terminated),                         
		.m0_awbar          (),                                                // (terminated),                         
		.m0_awunique       ()                                                 // (terminated),                         
	);

	qsys_top_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (0),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (0),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (4),
		.DATA_WIDTH                        (32),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (4),
		.M0_ADDR_WIDTH                     (29),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (29),
		.USE_S0_AWUSER                     (0),
		.USE_S0_ARUSER                     (0),
		.USE_S0_WUSER                      (0),
		.USE_S0_RUSER                      (0),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) subsys_hps_lwhps2fpga_translator (
		.aclk              (clk_100_out_clk_clk),                             //   input,   width = 1,       clk.clk
		.aresetn           (~subsys_debug_reset_reset_bridge_in_reset_reset), //   input,   width = 1, clk_reset.reset_n
		.m0_awid           (subsys_hps_lwhps2fpga_translator_m0_awid),        //  output,   width = 4,        m0.awid
		.m0_awaddr         (subsys_hps_lwhps2fpga_translator_m0_awaddr),      //  output,  width = 29,          .awaddr
		.m0_awlen          (subsys_hps_lwhps2fpga_translator_m0_awlen),       //  output,   width = 8,          .awlen
		.m0_awsize         (subsys_hps_lwhps2fpga_translator_m0_awsize),      //  output,   width = 3,          .awsize
		.m0_awburst        (subsys_hps_lwhps2fpga_translator_m0_awburst),     //  output,   width = 2,          .awburst
		.m0_awlock         (subsys_hps_lwhps2fpga_translator_m0_awlock),      //  output,   width = 1,          .awlock
		.m0_awcache        (subsys_hps_lwhps2fpga_translator_m0_awcache),     //  output,   width = 4,          .awcache
		.m0_awprot         (subsys_hps_lwhps2fpga_translator_m0_awprot),      //  output,   width = 3,          .awprot
		.m0_awuser         (subsys_hps_lwhps2fpga_translator_m0_awuser),      //  output,   width = 1,          .awuser
		.m0_awqos          (subsys_hps_lwhps2fpga_translator_m0_awqos),       //  output,   width = 4,          .awqos
		.m0_awregion       (subsys_hps_lwhps2fpga_translator_m0_awregion),    //  output,   width = 4,          .awregion
		.m0_awvalid        (subsys_hps_lwhps2fpga_translator_m0_awvalid),     //  output,   width = 1,          .awvalid
		.m0_awready        (subsys_hps_lwhps2fpga_translator_m0_awready),     //   input,   width = 1,          .awready
		.m0_wdata          (subsys_hps_lwhps2fpga_translator_m0_wdata),       //  output,  width = 32,          .wdata
		.m0_wstrb          (subsys_hps_lwhps2fpga_translator_m0_wstrb),       //  output,   width = 4,          .wstrb
		.m0_wlast          (subsys_hps_lwhps2fpga_translator_m0_wlast),       //  output,   width = 1,          .wlast
		.m0_wvalid         (subsys_hps_lwhps2fpga_translator_m0_wvalid),      //  output,   width = 1,          .wvalid
		.m0_wuser          (subsys_hps_lwhps2fpga_translator_m0_wuser),       //  output,   width = 1,          .wuser
		.m0_wready         (subsys_hps_lwhps2fpga_translator_m0_wready),      //   input,   width = 1,          .wready
		.m0_bid            (subsys_hps_lwhps2fpga_translator_m0_bid),         //   input,   width = 4,          .bid
		.m0_bresp          (subsys_hps_lwhps2fpga_translator_m0_bresp),       //   input,   width = 2,          .bresp
		.m0_buser          (subsys_hps_lwhps2fpga_translator_m0_buser),       //   input,   width = 1,          .buser
		.m0_bvalid         (subsys_hps_lwhps2fpga_translator_m0_bvalid),      //   input,   width = 1,          .bvalid
		.m0_bready         (subsys_hps_lwhps2fpga_translator_m0_bready),      //  output,   width = 1,          .bready
		.m0_arid           (subsys_hps_lwhps2fpga_translator_m0_arid),        //  output,   width = 4,          .arid
		.m0_araddr         (subsys_hps_lwhps2fpga_translator_m0_araddr),      //  output,  width = 29,          .araddr
		.m0_arlen          (subsys_hps_lwhps2fpga_translator_m0_arlen),       //  output,   width = 8,          .arlen
		.m0_arsize         (subsys_hps_lwhps2fpga_translator_m0_arsize),      //  output,   width = 3,          .arsize
		.m0_arburst        (subsys_hps_lwhps2fpga_translator_m0_arburst),     //  output,   width = 2,          .arburst
		.m0_arlock         (subsys_hps_lwhps2fpga_translator_m0_arlock),      //  output,   width = 1,          .arlock
		.m0_arcache        (subsys_hps_lwhps2fpga_translator_m0_arcache),     //  output,   width = 4,          .arcache
		.m0_arprot         (subsys_hps_lwhps2fpga_translator_m0_arprot),      //  output,   width = 3,          .arprot
		.m0_aruser         (subsys_hps_lwhps2fpga_translator_m0_aruser),      //  output,   width = 1,          .aruser
		.m0_arqos          (subsys_hps_lwhps2fpga_translator_m0_arqos),       //  output,   width = 4,          .arqos
		.m0_arregion       (subsys_hps_lwhps2fpga_translator_m0_arregion),    //  output,   width = 4,          .arregion
		.m0_arvalid        (subsys_hps_lwhps2fpga_translator_m0_arvalid),     //  output,   width = 1,          .arvalid
		.m0_arready        (subsys_hps_lwhps2fpga_translator_m0_arready),     //   input,   width = 1,          .arready
		.m0_rid            (subsys_hps_lwhps2fpga_translator_m0_rid),         //   input,   width = 4,          .rid
		.m0_rdata          (subsys_hps_lwhps2fpga_translator_m0_rdata),       //   input,  width = 32,          .rdata
		.m0_rresp          (subsys_hps_lwhps2fpga_translator_m0_rresp),       //   input,   width = 2,          .rresp
		.m0_rlast          (subsys_hps_lwhps2fpga_translator_m0_rlast),       //   input,   width = 1,          .rlast
		.m0_rvalid         (subsys_hps_lwhps2fpga_translator_m0_rvalid),      //   input,   width = 1,          .rvalid
		.m0_rready         (subsys_hps_lwhps2fpga_translator_m0_rready),      //  output,   width = 1,          .rready
		.m0_ruser          (subsys_hps_lwhps2fpga_translator_m0_ruser),       //   input,   width = 1,          .ruser
		.s0_awid           (subsys_hps_lwhps2fpga_awid),                      //   input,   width = 4,        s0.awid
		.s0_awaddr         (subsys_hps_lwhps2fpga_awaddr),                    //   input,  width = 29,          .awaddr
		.s0_awlen          (subsys_hps_lwhps2fpga_awlen),                     //   input,   width = 8,          .awlen
		.s0_awsize         (subsys_hps_lwhps2fpga_awsize),                    //   input,   width = 3,          .awsize
		.s0_awburst        (subsys_hps_lwhps2fpga_awburst),                   //   input,   width = 2,          .awburst
		.s0_awlock         (subsys_hps_lwhps2fpga_awlock),                    //   input,   width = 1,          .awlock
		.s0_awcache        (subsys_hps_lwhps2fpga_awcache),                   //   input,   width = 4,          .awcache
		.s0_awprot         (subsys_hps_lwhps2fpga_awprot),                    //   input,   width = 3,          .awprot
		.s0_awvalid        (subsys_hps_lwhps2fpga_awvalid),                   //   input,   width = 1,          .awvalid
		.s0_awready        (subsys_hps_lwhps2fpga_awready),                   //  output,   width = 1,          .awready
		.s0_wdata          (subsys_hps_lwhps2fpga_wdata),                     //   input,  width = 32,          .wdata
		.s0_wstrb          (subsys_hps_lwhps2fpga_wstrb),                     //   input,   width = 4,          .wstrb
		.s0_wlast          (subsys_hps_lwhps2fpga_wlast),                     //   input,   width = 1,          .wlast
		.s0_wvalid         (subsys_hps_lwhps2fpga_wvalid),                    //   input,   width = 1,          .wvalid
		.s0_wready         (subsys_hps_lwhps2fpga_wready),                    //  output,   width = 1,          .wready
		.s0_bid            (subsys_hps_lwhps2fpga_bid),                       //  output,   width = 4,          .bid
		.s0_bresp          (subsys_hps_lwhps2fpga_bresp),                     //  output,   width = 2,          .bresp
		.s0_bvalid         (subsys_hps_lwhps2fpga_bvalid),                    //  output,   width = 1,          .bvalid
		.s0_bready         (subsys_hps_lwhps2fpga_bready),                    //   input,   width = 1,          .bready
		.s0_arid           (subsys_hps_lwhps2fpga_arid),                      //   input,   width = 4,          .arid
		.s0_araddr         (subsys_hps_lwhps2fpga_araddr),                    //   input,  width = 29,          .araddr
		.s0_arlen          (subsys_hps_lwhps2fpga_arlen),                     //   input,   width = 8,          .arlen
		.s0_arsize         (subsys_hps_lwhps2fpga_arsize),                    //   input,   width = 3,          .arsize
		.s0_arburst        (subsys_hps_lwhps2fpga_arburst),                   //   input,   width = 2,          .arburst
		.s0_arlock         (subsys_hps_lwhps2fpga_arlock),                    //   input,   width = 1,          .arlock
		.s0_arcache        (subsys_hps_lwhps2fpga_arcache),                   //   input,   width = 4,          .arcache
		.s0_arprot         (subsys_hps_lwhps2fpga_arprot),                    //   input,   width = 3,          .arprot
		.s0_arvalid        (subsys_hps_lwhps2fpga_arvalid),                   //   input,   width = 1,          .arvalid
		.s0_arready        (subsys_hps_lwhps2fpga_arready),                   //  output,   width = 1,          .arready
		.s0_rid            (subsys_hps_lwhps2fpga_rid),                       //  output,   width = 4,          .rid
		.s0_rdata          (subsys_hps_lwhps2fpga_rdata),                     //  output,  width = 32,          .rdata
		.s0_rresp          (subsys_hps_lwhps2fpga_rresp),                     //  output,   width = 2,          .rresp
		.s0_rlast          (subsys_hps_lwhps2fpga_rlast),                     //  output,   width = 1,          .rlast
		.s0_rvalid         (subsys_hps_lwhps2fpga_rvalid),                    //  output,   width = 1,          .rvalid
		.s0_rready         (subsys_hps_lwhps2fpga_rready),                    //   input,   width = 1,          .rready
		.m0_awuser_addrchk (),                                                // (terminated),                        
		.m0_awuser_sai     (),                                                // (terminated),                        
		.m0_wuser_datachk  (),                                                // (terminated),                        
		.m0_wuser_data     (),                                                // (terminated),                        
		.m0_wuser_poison   (),                                                // (terminated),                        
		.m0_aruser_addrchk (),                                                // (terminated),                        
		.m0_aruser_sai     (),                                                // (terminated),                        
		.m0_ruser_datachk  (4'b0000),                                         // (terminated),                        
		.m0_ruser_data     (4'b0000),                                         // (terminated),                        
		.m0_ruser_poison   (1'b0),                                            // (terminated),                        
		.s0_awuser         (1'b0),                                            // (terminated),                        
		.s0_awuser_addrchk (4'b0000),                                         // (terminated),                        
		.s0_awuser_sai     (4'b0000),                                         // (terminated),                        
		.s0_awqos          (4'b0000),                                         // (terminated),                        
		.s0_awregion       (4'b0000),                                         // (terminated),                        
		.s0_wuser          (1'b0),                                            // (terminated),                        
		.s0_wuser_datachk  (4'b0000),                                         // (terminated),                        
		.s0_wuser_data     (4'b0000),                                         // (terminated),                        
		.s0_wuser_poison   (1'b0),                                            // (terminated),                        
		.s0_buser          (),                                                // (terminated),                        
		.s0_aruser         (1'b0),                                            // (terminated),                        
		.s0_aruser_addrchk (4'b0000),                                         // (terminated),                        
		.s0_aruser_sai     (4'b0000),                                         // (terminated),                        
		.s0_arqos          (4'b0000),                                         // (terminated),                        
		.s0_arregion       (4'b0000),                                         // (terminated),                        
		.s0_ruser          (),                                                // (terminated),                        
		.s0_ruser_datachk  (),                                                // (terminated),                        
		.s0_ruser_data     (),                                                // (terminated),                        
		.s0_ruser_poison   (),                                                // (terminated),                        
		.s0_wid            (4'b0000),                                         // (terminated),                        
		.s0_ardomain       (2'b00),                                           // (terminated),                        
		.s0_arsnoop        (4'b0000),                                         // (terminated),                        
		.s0_arbar          (2'b00),                                           // (terminated),                        
		.s0_awdomain       (2'b00),                                           // (terminated),                        
		.s0_awsnoop        (3'b000),                                          // (terminated),                        
		.s0_awbar          (2'b00),                                           // (terminated),                        
		.s0_awunique       (1'b0),                                            // (terminated),                        
		.m0_wid            (),                                                // (terminated),                        
		.m0_ardomain       (),                                                // (terminated),                        
		.m0_arsnoop        (),                                                // (terminated),                        
		.m0_arbar          (),                                                // (terminated),                        
		.m0_awdomain       (),                                                // (terminated),                        
		.m0_awsnoop        (),                                                // (terminated),                        
		.m0_awbar          (),                                                // (terminated),                        
		.m0_awunique       ()                                                 // (terminated),                        
	);

	qsys_top_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (1),
		.USE_M0_AWREGION                   (0),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (0),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (0),
		.USE_M0_AWPROT                     (0),
		.USE_S0_AWQOS                      (1),
		.USE_M0_AWQOS                      (0),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (1),
		.USE_M0_ARREGION                   (0),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (0),
		.USE_M0_ARCACHE                    (0),
		.USE_M0_ARQOS                      (0),
		.USE_M0_ARPROT                     (0),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (1),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (10),
		.DATA_WIDTH                        (128),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (10),
		.M0_ADDR_WIDTH                     (18),
		.S0_WRITE_ADDR_USER_WIDTH          (1),
		.S0_READ_ADDR_USER_WIDTH           (1),
		.M0_WRITE_ADDR_USER_WIDTH          (1),
		.M0_READ_ADDR_USER_WIDTH           (1),
		.S0_WRITE_DATA_USER_WIDTH          (1),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (1),
		.M0_WRITE_DATA_USER_WIDTH          (1),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (1),
		.S0_ADDR_WIDTH                     (18),
		.USE_S0_AWUSER                     (1),
		.USE_S0_ARUSER                     (1),
		.USE_S0_WUSER                      (1),
		.USE_S0_RUSER                      (1),
		.USE_S0_BUSER                      (1),
		.USE_M0_AWUSER                     (0),
		.USE_M0_ARUSER                     (0),
		.USE_M0_WUSER                      (0),
		.USE_M0_RUSER                      (0),
		.USE_M0_BUSER                      (0),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) ocm_axi_s1_translator (
		.aclk              (clk_100_out_clk_clk),                             //   input,    width = 1,       clk.clk
		.aresetn           (~subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset_n
		.m0_awid           (ocm_axi_s1_awid),                                 //  output,   width = 10,        m0.awid
		.m0_awaddr         (ocm_axi_s1_awaddr),                               //  output,   width = 18,          .awaddr
		.m0_awlen          (ocm_axi_s1_awlen),                                //  output,    width = 8,          .awlen
		.m0_awsize         (ocm_axi_s1_awsize),                               //  output,    width = 3,          .awsize
		.m0_awburst        (ocm_axi_s1_awburst),                              //  output,    width = 2,          .awburst
		.m0_awvalid        (ocm_axi_s1_awvalid),                              //  output,    width = 1,          .awvalid
		.m0_awready        (ocm_axi_s1_awready),                              //   input,    width = 1,          .awready
		.m0_wdata          (ocm_axi_s1_wdata),                                //  output,  width = 128,          .wdata
		.m0_wstrb          (ocm_axi_s1_wstrb),                                //  output,   width = 16,          .wstrb
		.m0_wlast          (ocm_axi_s1_wlast),                                //  output,    width = 1,          .wlast
		.m0_wvalid         (ocm_axi_s1_wvalid),                               //  output,    width = 1,          .wvalid
		.m0_wready         (ocm_axi_s1_wready),                               //   input,    width = 1,          .wready
		.m0_bid            (ocm_axi_s1_bid),                                  //   input,   width = 10,          .bid
		.m0_bresp          (ocm_axi_s1_bresp),                                //   input,    width = 2,          .bresp
		.m0_bvalid         (ocm_axi_s1_bvalid),                               //   input,    width = 1,          .bvalid
		.m0_bready         (ocm_axi_s1_bready),                               //  output,    width = 1,          .bready
		.m0_arid           (ocm_axi_s1_arid),                                 //  output,   width = 10,          .arid
		.m0_araddr         (ocm_axi_s1_araddr),                               //  output,   width = 18,          .araddr
		.m0_arlen          (ocm_axi_s1_arlen),                                //  output,    width = 8,          .arlen
		.m0_arsize         (ocm_axi_s1_arsize),                               //  output,    width = 3,          .arsize
		.m0_arburst        (ocm_axi_s1_arburst),                              //  output,    width = 2,          .arburst
		.m0_arvalid        (ocm_axi_s1_arvalid),                              //  output,    width = 1,          .arvalid
		.m0_arready        (ocm_axi_s1_arready),                              //   input,    width = 1,          .arready
		.m0_rid            (ocm_axi_s1_rid),                                  //   input,   width = 10,          .rid
		.m0_rdata          (ocm_axi_s1_rdata),                                //   input,  width = 128,          .rdata
		.m0_rresp          (ocm_axi_s1_rresp),                                //   input,    width = 2,          .rresp
		.m0_rlast          (ocm_axi_s1_rlast),                                //   input,    width = 1,          .rlast
		.m0_rvalid         (ocm_axi_s1_rvalid),                               //   input,    width = 1,          .rvalid
		.m0_rready         (ocm_axi_s1_rready),                               //  output,    width = 1,          .rready
		.s0_awid           (ocm_axi_s1_agent_altera_axi_master_awid),         //   input,   width = 10,        s0.awid
		.s0_awaddr         (ocm_axi_s1_agent_altera_axi_master_awaddr),       //   input,   width = 18,          .awaddr
		.s0_awlen          (ocm_axi_s1_agent_altera_axi_master_awlen),        //   input,    width = 8,          .awlen
		.s0_awsize         (ocm_axi_s1_agent_altera_axi_master_awsize),       //   input,    width = 3,          .awsize
		.s0_awburst        (ocm_axi_s1_agent_altera_axi_master_awburst),      //   input,    width = 2,          .awburst
		.s0_awlock         (ocm_axi_s1_agent_altera_axi_master_awlock),       //   input,    width = 1,          .awlock
		.s0_awcache        (ocm_axi_s1_agent_altera_axi_master_awcache),      //   input,    width = 4,          .awcache
		.s0_awprot         (ocm_axi_s1_agent_altera_axi_master_awprot),       //   input,    width = 3,          .awprot
		.s0_awuser         (ocm_axi_s1_agent_altera_axi_master_awuser),       //   input,    width = 1,          .awuser
		.s0_awqos          (ocm_axi_s1_agent_altera_axi_master_awqos),        //   input,    width = 4,          .awqos
		.s0_awregion       (ocm_axi_s1_agent_altera_axi_master_awregion),     //   input,    width = 4,          .awregion
		.s0_awvalid        (ocm_axi_s1_agent_altera_axi_master_awvalid),      //   input,    width = 1,          .awvalid
		.s0_awready        (ocm_axi_s1_agent_altera_axi_master_awready),      //  output,    width = 1,          .awready
		.s0_wdata          (ocm_axi_s1_agent_altera_axi_master_wdata),        //   input,  width = 128,          .wdata
		.s0_wstrb          (ocm_axi_s1_agent_altera_axi_master_wstrb),        //   input,   width = 16,          .wstrb
		.s0_wlast          (ocm_axi_s1_agent_altera_axi_master_wlast),        //   input,    width = 1,          .wlast
		.s0_wvalid         (ocm_axi_s1_agent_altera_axi_master_wvalid),       //   input,    width = 1,          .wvalid
		.s0_wuser          (ocm_axi_s1_agent_altera_axi_master_wuser),        //   input,    width = 1,          .wuser
		.s0_wready         (ocm_axi_s1_agent_altera_axi_master_wready),       //  output,    width = 1,          .wready
		.s0_bid            (ocm_axi_s1_agent_altera_axi_master_bid),          //  output,   width = 10,          .bid
		.s0_bresp          (ocm_axi_s1_agent_altera_axi_master_bresp),        //  output,    width = 2,          .bresp
		.s0_buser          (ocm_axi_s1_agent_altera_axi_master_buser),        //  output,    width = 1,          .buser
		.s0_bvalid         (ocm_axi_s1_agent_altera_axi_master_bvalid),       //  output,    width = 1,          .bvalid
		.s0_bready         (ocm_axi_s1_agent_altera_axi_master_bready),       //   input,    width = 1,          .bready
		.s0_arid           (ocm_axi_s1_agent_altera_axi_master_arid),         //   input,   width = 10,          .arid
		.s0_araddr         (ocm_axi_s1_agent_altera_axi_master_araddr),       //   input,   width = 18,          .araddr
		.s0_arlen          (ocm_axi_s1_agent_altera_axi_master_arlen),        //   input,    width = 8,          .arlen
		.s0_arsize         (ocm_axi_s1_agent_altera_axi_master_arsize),       //   input,    width = 3,          .arsize
		.s0_arburst        (ocm_axi_s1_agent_altera_axi_master_arburst),      //   input,    width = 2,          .arburst
		.s0_arlock         (ocm_axi_s1_agent_altera_axi_master_arlock),       //   input,    width = 1,          .arlock
		.s0_arcache        (ocm_axi_s1_agent_altera_axi_master_arcache),      //   input,    width = 4,          .arcache
		.s0_arprot         (ocm_axi_s1_agent_altera_axi_master_arprot),       //   input,    width = 3,          .arprot
		.s0_aruser         (ocm_axi_s1_agent_altera_axi_master_aruser),       //   input,    width = 1,          .aruser
		.s0_arqos          (ocm_axi_s1_agent_altera_axi_master_arqos),        //   input,    width = 4,          .arqos
		.s0_arregion       (ocm_axi_s1_agent_altera_axi_master_arregion),     //   input,    width = 4,          .arregion
		.s0_arvalid        (ocm_axi_s1_agent_altera_axi_master_arvalid),      //   input,    width = 1,          .arvalid
		.s0_arready        (ocm_axi_s1_agent_altera_axi_master_arready),      //  output,    width = 1,          .arready
		.s0_rid            (ocm_axi_s1_agent_altera_axi_master_rid),          //  output,   width = 10,          .rid
		.s0_rdata          (ocm_axi_s1_agent_altera_axi_master_rdata),        //  output,  width = 128,          .rdata
		.s0_rresp          (ocm_axi_s1_agent_altera_axi_master_rresp),        //  output,    width = 2,          .rresp
		.s0_rlast          (ocm_axi_s1_agent_altera_axi_master_rlast),        //  output,    width = 1,          .rlast
		.s0_rvalid         (ocm_axi_s1_agent_altera_axi_master_rvalid),       //  output,    width = 1,          .rvalid
		.s0_rready         (ocm_axi_s1_agent_altera_axi_master_rready),       //   input,    width = 1,          .rready
		.s0_ruser          (ocm_axi_s1_agent_altera_axi_master_ruser),        //  output,    width = 1,          .ruser
		.m0_awlock         (),                                                // (terminated),                         
		.m0_awcache        (),                                                // (terminated),                         
		.m0_awprot         (),                                                // (terminated),                         
		.m0_awuser         (),                                                // (terminated),                         
		.m0_awuser_addrchk (),                                                // (terminated),                         
		.m0_awuser_sai     (),                                                // (terminated),                         
		.m0_awqos          (),                                                // (terminated),                         
		.m0_awregion       (),                                                // (terminated),                         
		.m0_wuser          (),                                                // (terminated),                         
		.m0_wuser_datachk  (),                                                // (terminated),                         
		.m0_wuser_data     (),                                                // (terminated),                         
		.m0_wuser_poison   (),                                                // (terminated),                         
		.m0_buser          (1'b0),                                            // (terminated),                         
		.m0_arlock         (),                                                // (terminated),                         
		.m0_arcache        (),                                                // (terminated),                         
		.m0_arprot         (),                                                // (terminated),                         
		.m0_aruser         (),                                                // (terminated),                         
		.m0_aruser_addrchk (),                                                // (terminated),                         
		.m0_aruser_sai     (),                                                // (terminated),                         
		.m0_arqos          (),                                                // (terminated),                         
		.m0_arregion       (),                                                // (terminated),                         
		.m0_ruser          (1'b0),                                            // (terminated),                         
		.m0_ruser_datachk  (16'b0000000000000000),                            // (terminated),                         
		.m0_ruser_data     (4'b0000),                                         // (terminated),                         
		.m0_ruser_poison   (2'b00),                                           // (terminated),                         
		.s0_awuser_addrchk (4'b0000),                                         // (terminated),                         
		.s0_awuser_sai     (4'b0000),                                         // (terminated),                         
		.s0_wuser_datachk  (16'b0000000000000000),                            // (terminated),                         
		.s0_wuser_data     (4'b0000),                                         // (terminated),                         
		.s0_wuser_poison   (2'b00),                                           // (terminated),                         
		.s0_aruser_addrchk (4'b0000),                                         // (terminated),                         
		.s0_aruser_sai     (4'b0000),                                         // (terminated),                         
		.s0_ruser_datachk  (),                                                // (terminated),                         
		.s0_ruser_data     (),                                                // (terminated),                         
		.s0_ruser_poison   (),                                                // (terminated),                         
		.s0_wid            (10'b0000000000),                                  // (terminated),                         
		.s0_ardomain       (2'b00),                                           // (terminated),                         
		.s0_arsnoop        (4'b0000),                                         // (terminated),                         
		.s0_arbar          (2'b00),                                           // (terminated),                         
		.s0_awdomain       (2'b00),                                           // (terminated),                         
		.s0_awsnoop        (3'b000),                                          // (terminated),                         
		.s0_awbar          (2'b00),                                           // (terminated),                         
		.s0_awunique       (1'b0),                                            // (terminated),                         
		.m0_wid            (),                                                // (terminated),                         
		.m0_ardomain       (),                                                // (terminated),                         
		.m0_arsnoop        (),                                                // (terminated),                         
		.m0_arbar          (),                                                // (terminated),                         
		.m0_awdomain       (),                                                // (terminated),                         
		.m0_awsnoop        (),                                                // (terminated),                         
		.m0_awbar          (),                                                // (terminated),                         
		.m0_awunique       ()                                                 // (terminated),                         
	);

	qsys_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (21),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (38),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (0),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (1),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) subsys_hps_usb31_phy_reconfig_slave_translator (
		.clk                    (clk_100_out_clk_clk),                                        //   input,   width = 1,                      clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),             //   input,   width = 1,                    reset.reset
		.uav_address            (subsys_hps_usb31_phy_reconfig_slave_agent_m0_address),       //   input,  width = 38, avalon_universal_slave_0.address
		.uav_burstcount         (subsys_hps_usb31_phy_reconfig_slave_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (subsys_hps_usb31_phy_reconfig_slave_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (subsys_hps_usb31_phy_reconfig_slave_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (subsys_hps_usb31_phy_reconfig_slave_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (subsys_hps_usb31_phy_reconfig_slave_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (subsys_hps_usb31_phy_reconfig_slave_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (subsys_hps_usb31_phy_reconfig_slave_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (subsys_hps_usb31_phy_reconfig_slave_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (subsys_hps_usb31_phy_reconfig_slave_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (subsys_hps_usb31_phy_reconfig_slave_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (subsys_hps_usb31_phy_reconfig_slave_address),                //  output,  width = 21,      avalon_anti_slave_0.address
		.av_write               (subsys_hps_usb31_phy_reconfig_slave_write),                  //  output,   width = 1,                         .write
		.av_read                (subsys_hps_usb31_phy_reconfig_slave_read),                   //  output,   width = 1,                         .read
		.av_readdata            (subsys_hps_usb31_phy_reconfig_slave_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (subsys_hps_usb31_phy_reconfig_slave_writedata),              //  output,  width = 32,                         .writedata
		.av_byteenable          (subsys_hps_usb31_phy_reconfig_slave_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (subsys_hps_usb31_phy_reconfig_slave_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (subsys_hps_usb31_phy_reconfig_slave_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_begintransfer       (),                                                           // (terminated),                                       
		.av_beginbursttransfer  (),                                                           // (terminated),                                       
		.av_burstcount          (),                                                           // (terminated),                                       
		.av_writebyteenable     (),                                                           // (terminated),                                       
		.av_lock                (),                                                           // (terminated),                                       
		.av_chipselect          (),                                                           // (terminated),                                       
		.av_clken               (),                                                           // (terminated),                                       
		.uav_clken              (1'b0),                                                       // (terminated),                                       
		.av_debugaccess         (),                                                           // (terminated),                                       
		.av_outputenable        (),                                                           // (terminated),                                       
		.uav_response           (),                                                           // (terminated),                                       
		.av_response            (2'b00),                                                      // (terminated),                                       
		.uav_writeresponsevalid (),                                                           // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                                        // (terminated),                                       
	);

	qsys_top_altera_merlin_slave_translator_191_x56fcki #(
		.AV_ADDRESS_W                   (17),
		.AV_DATA_W                      (32),
		.UAV_DATA_W                     (32),
		.AV_BURSTCOUNT_W                (1),
		.AV_BYTEENABLE_W                (4),
		.UAV_BYTEENABLE_W               (4),
		.UAV_ADDRESS_W                  (38),
		.UAV_BURSTCOUNT_W               (3),
		.AV_READLATENCY                 (0),
		.USE_READDATAVALID              (1),
		.USE_WAITREQUEST                (1),
		.USE_UAV_CLKEN                  (0),
		.USE_READRESPONSE               (0),
		.USE_WRITERESPONSE              (0),
		.AV_SYMBOLS_PER_WORD            (4),
		.AV_ADDRESS_SYMBOLS             (1),
		.AV_BURSTCOUNT_SYMBOLS          (0),
		.AV_CONSTANT_BURST_BEHAVIOR     (0),
		.UAV_CONSTANT_BURST_BEHAVIOR    (0),
		.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
		.CHIPSELECT_THROUGH_READLATENCY (0),
		.AV_READ_WAIT_CYCLES            (0),
		.AV_WRITE_WAIT_CYCLES           (0),
		.AV_SETUP_WAIT_CYCLES           (0),
		.AV_DATA_HOLD_CYCLES            (0),
		.WAITREQUEST_ALLOWANCE          (0),
		.SYNC_RESET                     (1)
	) subsys_periph_pb_cpu_0_s0_translator (
		.clk                    (clk_100_out_clk_clk),                              //   input,   width = 1,                      clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),   //   input,   width = 1,                    reset.reset
		.uav_address            (subsys_periph_pb_cpu_0_s0_agent_m0_address),       //   input,  width = 38, avalon_universal_slave_0.address
		.uav_burstcount         (subsys_periph_pb_cpu_0_s0_agent_m0_burstcount),    //   input,   width = 3,                         .burstcount
		.uav_read               (subsys_periph_pb_cpu_0_s0_agent_m0_read),          //   input,   width = 1,                         .read
		.uav_write              (subsys_periph_pb_cpu_0_s0_agent_m0_write),         //   input,   width = 1,                         .write
		.uav_waitrequest        (subsys_periph_pb_cpu_0_s0_agent_m0_waitrequest),   //  output,   width = 1,                         .waitrequest
		.uav_readdatavalid      (subsys_periph_pb_cpu_0_s0_agent_m0_readdatavalid), //  output,   width = 1,                         .readdatavalid
		.uav_byteenable         (subsys_periph_pb_cpu_0_s0_agent_m0_byteenable),    //   input,   width = 4,                         .byteenable
		.uav_readdata           (subsys_periph_pb_cpu_0_s0_agent_m0_readdata),      //  output,  width = 32,                         .readdata
		.uav_writedata          (subsys_periph_pb_cpu_0_s0_agent_m0_writedata),     //   input,  width = 32,                         .writedata
		.uav_lock               (subsys_periph_pb_cpu_0_s0_agent_m0_lock),          //   input,   width = 1,                         .lock
		.uav_debugaccess        (subsys_periph_pb_cpu_0_s0_agent_m0_debugaccess),   //   input,   width = 1,                         .debugaccess
		.av_address             (subsys_periph_pb_cpu_0_s0_address),                //  output,  width = 17,      avalon_anti_slave_0.address
		.av_write               (subsys_periph_pb_cpu_0_s0_write),                  //  output,   width = 1,                         .write
		.av_read                (subsys_periph_pb_cpu_0_s0_read),                   //  output,   width = 1,                         .read
		.av_readdata            (subsys_periph_pb_cpu_0_s0_readdata),               //   input,  width = 32,                         .readdata
		.av_writedata           (subsys_periph_pb_cpu_0_s0_writedata),              //  output,  width = 32,                         .writedata
		.av_burstcount          (subsys_periph_pb_cpu_0_s0_burstcount),             //  output,   width = 1,                         .burstcount
		.av_byteenable          (subsys_periph_pb_cpu_0_s0_byteenable),             //  output,   width = 4,                         .byteenable
		.av_readdatavalid       (subsys_periph_pb_cpu_0_s0_readdatavalid),          //   input,   width = 1,                         .readdatavalid
		.av_waitrequest         (subsys_periph_pb_cpu_0_s0_waitrequest),            //   input,   width = 1,                         .waitrequest
		.av_debugaccess         (subsys_periph_pb_cpu_0_s0_debugaccess),            //  output,   width = 1,                         .debugaccess
		.av_begintransfer       (),                                                 // (terminated),                                       
		.av_beginbursttransfer  (),                                                 // (terminated),                                       
		.av_writebyteenable     (),                                                 // (terminated),                                       
		.av_lock                (),                                                 // (terminated),                                       
		.av_chipselect          (),                                                 // (terminated),                                       
		.av_clken               (),                                                 // (terminated),                                       
		.uav_clken              (1'b0),                                             // (terminated),                                       
		.av_outputenable        (),                                                 // (terminated),                                       
		.uav_response           (),                                                 // (terminated),                                       
		.av_response            (2'b00),                                            // (terminated),                                       
		.uav_writeresponsevalid (),                                                 // (terminated),                                       
		.av_writeresponsevalid  (1'b0)                                              // (terminated),                                       
	);

	qsys_top_altera_merlin_master_agent_1922_fy3n5ti #(
		.PKT_WUNIQUE               (142),
		.PKT_DOMAIN_H              (141),
		.PKT_DOMAIN_L              (140),
		.PKT_SNOOP_H               (139),
		.PKT_SNOOP_L               (136),
		.PKT_BARRIER_H             (135),
		.PKT_BARRIER_L             (134),
		.PKT_ORI_BURST_SIZE_H      (133),
		.PKT_ORI_BURST_SIZE_L      (131),
		.PKT_RESPONSE_STATUS_H     (130),
		.PKT_RESPONSE_STATUS_L     (129),
		.PKT_QOS_H                 (113),
		.PKT_QOS_L                 (110),
		.PKT_DATA_SIDEBAND_H       (108),
		.PKT_DATA_SIDEBAND_L       (108),
		.PKT_ADDR_SIDEBAND_H       (107),
		.PKT_ADDR_SIDEBAND_L       (107),
		.PKT_BURST_TYPE_H          (106),
		.PKT_BURST_TYPE_L          (105),
		.PKT_CACHE_H               (128),
		.PKT_CACHE_L               (125),
		.PKT_THREAD_ID_H           (121),
		.PKT_THREAD_ID_L           (118),
		.PKT_BURST_SIZE_H          (104),
		.PKT_BURST_SIZE_L          (102),
		.PKT_TRANS_EXCLUSIVE       (79),
		.PKT_TRANS_LOCK            (78),
		.PKT_BEGIN_BURST           (109),
		.PKT_PROTECTION_H          (124),
		.PKT_PROTECTION_L          (122),
		.PKT_BURSTWRAP_H           (101),
		.PKT_BURSTWRAP_L           (93),
		.PKT_BYTE_CNT_H            (92),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (115),
		.PKT_SRC_ID_L              (114),
		.PKT_DEST_ID_H             (117),
		.PKT_DEST_ID_L             (116),
		.PKT_POISON_H              (143),
		.PKT_POISON_L              (143),
		.PKT_DATACHK_H             (144),
		.PKT_DATACHK_L             (144),
		.PKT_ADDRCHK_H             (147),
		.PKT_ADDRCHK_L             (146),
		.PKT_SAI_H                 (148),
		.PKT_SAI_L                 (148),
		.PKT_USER_DATA_H           (145),
		.PKT_USER_DATA_L           (145),
		.ST_DATA_W                 (158),
		.ST_CHANNEL_W              (5),
		.AV_BURSTCOUNT_W           (3),
		.SUPPRESS_0_BYTEEN_RSP     (1),
		.ID                        (0),
		.BURSTWRAP_VALUE           (511),
		.CACHE_VALUE               (0),
		.SECURE_ACCESS_BIT         (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.DOMAIN_VALUE              (3),
		.BARRIER_VALUE             (0),
		.SNOOP_VALUE               (0),
		.WUNIQUE_VALUE             (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.ROLE_BASED_USER           (0)
	) subsys_debug_fpga_m_master_agent (
		.clk                   (clk_100_out_clk_clk),                                                           //   input,    width = 1,       clk.clk
		.reset                 (subsys_debug_reset_reset_bridge_in_reset_reset),                                //   input,    width = 1, clk_reset.reset
		.av_address            (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_address),       //   input,   width = 38,        av.address
		.av_write              (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_write),         //   input,    width = 1,          .write
		.av_read               (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_read),          //   input,    width = 1,          .read
		.av_writedata          (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_writedata),     //   input,   width = 32,          .writedata
		.av_readdata           (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_readdata),      //  output,   width = 32,          .readdata
		.av_waitrequest        (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_waitrequest),   //  output,    width = 1,          .waitrequest
		.av_readdatavalid      (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_readdatavalid), //  output,    width = 1,          .readdatavalid
		.av_byteenable         (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_byteenable),    //   input,    width = 4,          .byteenable
		.av_burstcount         (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_burstcount),    //   input,    width = 3,          .burstcount
		.av_debugaccess        (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_debugaccess),   //   input,    width = 1,          .debugaccess
		.av_lock               (subsys_debug_fpga_m_master_translator_avalon_universal_master_0_lock),          //   input,    width = 1,          .lock
		.cp_valid              (subsys_debug_fpga_m_master_agent_cp_valid),                                     //  output,    width = 1,        cp.valid
		.cp_data               (subsys_debug_fpga_m_master_agent_cp_data),                                      //  output,  width = 158,          .data
		.cp_startofpacket      (subsys_debug_fpga_m_master_agent_cp_startofpacket),                             //  output,    width = 1,          .startofpacket
		.cp_endofpacket        (subsys_debug_fpga_m_master_agent_cp_endofpacket),                               //  output,    width = 1,          .endofpacket
		.cp_ready              (subsys_debug_fpga_m_master_agent_cp_ready),                                     //   input,    width = 1,          .ready
		.rp_valid              (subsys_debug_fpga_m_master_limiter_rsp_src_valid),                              //   input,    width = 1,        rp.valid
		.rp_data               (subsys_debug_fpga_m_master_limiter_rsp_src_data),                               //   input,  width = 158,          .data
		.rp_channel            (subsys_debug_fpga_m_master_limiter_rsp_src_channel),                            //   input,    width = 5,          .channel
		.rp_startofpacket      (subsys_debug_fpga_m_master_limiter_rsp_src_startofpacket),                      //   input,    width = 1,          .startofpacket
		.rp_endofpacket        (subsys_debug_fpga_m_master_limiter_rsp_src_endofpacket),                        //   input,    width = 1,          .endofpacket
		.rp_ready              (subsys_debug_fpga_m_master_limiter_rsp_src_ready),                              //  output,    width = 1,          .ready
		.av_response           (),                                                                              // (terminated),                         
		.av_writeresponsevalid ()                                                                               // (terminated),                         
	);

	qsys_top_altera_merlin_axi_master_ni_1980_4qd7sla #(
		.ID_WIDTH                  (4),
		.ADDR_WIDTH                (38),
		.RDATA_WIDTH               (128),
		.WDATA_WIDTH               (128),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (16),
		.READ_ISSUING_CAPABILITY   (16),
		.PKT_BEGIN_BURST           (217),
		.PKT_CACHE_H               (236),
		.PKT_CACHE_L               (233),
		.PKT_ADDR_SIDEBAND_H       (215),
		.PKT_ADDR_SIDEBAND_L       (215),
		.PKT_PROTECTION_H          (232),
		.PKT_PROTECTION_L          (230),
		.PKT_BURST_SIZE_H          (212),
		.PKT_BURST_SIZE_L          (210),
		.PKT_BURST_TYPE_H          (214),
		.PKT_BURST_TYPE_L          (213),
		.PKT_RESPONSE_STATUS_L     (237),
		.PKT_RESPONSE_STATUS_H     (238),
		.PKT_BURSTWRAP_H           (209),
		.PKT_BURSTWRAP_L           (201),
		.PKT_BYTE_CNT_H            (200),
		.PKT_BYTE_CNT_L            (188),
		.PKT_ADDR_H                (181),
		.PKT_ADDR_L                (144),
		.PKT_TRANS_EXCLUSIVE       (187),
		.PKT_TRANS_LOCK            (186),
		.PKT_TRANS_COMPRESSED_READ (182),
		.PKT_TRANS_POSTED          (183),
		.PKT_TRANS_WRITE           (184),
		.PKT_TRANS_READ            (185),
		.PKT_DATA_H                (127),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (143),
		.PKT_BYTEEN_L              (128),
		.PKT_SRC_ID_H              (223),
		.PKT_SRC_ID_L              (222),
		.PKT_DEST_ID_H             (225),
		.PKT_DEST_ID_L             (224),
		.PKT_THREAD_ID_H           (229),
		.PKT_THREAD_ID_L           (226),
		.PKT_QOS_L                 (218),
		.PKT_QOS_H                 (221),
		.PKT_ORI_BURST_SIZE_L      (239),
		.PKT_ORI_BURST_SIZE_H      (241),
		.PKT_DATA_SIDEBAND_H       (216),
		.PKT_DATA_SIDEBAND_L       (216),
		.PKT_DOMAIN_H              (249),
		.PKT_DOMAIN_L              (248),
		.PKT_SNOOP_H               (247),
		.PKT_SNOOP_L               (244),
		.PKT_BARRIER_H             (243),
		.PKT_BARRIER_L             (242),
		.PKT_WUNIQUE               (250),
		.PKT_EOP_OOO               (257),
		.PKT_SOP_OOO               (258),
		.PKT_POISON_H              (251),
		.PKT_POISON_L              (251),
		.PKT_DATACHK_H             (252),
		.PKT_DATACHK_L             (252),
		.PKT_ADDRCHK_H             (255),
		.PKT_ADDRCHK_L             (254),
		.PKT_SAI_H                 (256),
		.PKT_SAI_L                 (256),
		.PKT_USER_DATA_H           (253),
		.PKT_USER_DATA_L           (253),
		.ST_DATA_W                 (266),
		.ST_CHANNEL_W              (5),
		.ID                        (1),
		.SYNC_RESET                (1)
	) subsys_hps_hps2fpga_agent (
		.aclk                   (clk_100_out_clk_clk),                              //   input,    width = 1,              clk.clk
		.aresetn                (~subsys_debug_reset_reset_bridge_in_reset_reset),  //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (subsys_hps_hps2fpga_agent_write_cp_valid),         //  output,    width = 1,         write_cp.valid
		.write_cp_data          (subsys_hps_hps2fpga_agent_write_cp_data),          //  output,  width = 266,                 .data
		.write_cp_startofpacket (subsys_hps_hps2fpga_agent_write_cp_startofpacket), //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (subsys_hps_hps2fpga_agent_write_cp_endofpacket),   //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (subsys_hps_hps2fpga_agent_write_cp_ready),         //   input,    width = 1,                 .ready
		.write_rp_valid         (rsp_mux_001_src_valid),                            //   input,    width = 1,         write_rp.valid
		.write_rp_data          (rsp_mux_001_src_data),                             //   input,  width = 266,                 .data
		.write_rp_channel       (rsp_mux_001_src_channel),                          //   input,    width = 5,                 .channel
		.write_rp_startofpacket (rsp_mux_001_src_startofpacket),                    //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (rsp_mux_001_src_endofpacket),                      //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (rsp_mux_001_src_ready),                            //  output,    width = 1,                 .ready
		.read_cp_valid          (subsys_hps_hps2fpga_agent_read_cp_valid),          //  output,    width = 1,          read_cp.valid
		.read_cp_data           (subsys_hps_hps2fpga_agent_read_cp_data),           //  output,  width = 266,                 .data
		.read_cp_startofpacket  (subsys_hps_hps2fpga_agent_read_cp_startofpacket),  //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (subsys_hps_hps2fpga_agent_read_cp_endofpacket),    //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (subsys_hps_hps2fpga_agent_read_cp_ready),          //   input,    width = 1,                 .ready
		.read_rp_valid          (rsp_mux_002_src_valid),                            //   input,    width = 1,          read_rp.valid
		.read_rp_data           (rsp_mux_002_src_data),                             //   input,  width = 266,                 .data
		.read_rp_channel        (rsp_mux_002_src_channel),                          //   input,    width = 5,                 .channel
		.read_rp_startofpacket  (rsp_mux_002_src_startofpacket),                    //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (rsp_mux_002_src_endofpacket),                      //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (rsp_mux_002_src_ready),                            //  output,    width = 1,                 .ready
		.awid                   (subsys_hps_hps2fpga_translator_m0_awid),           //   input,    width = 4, altera_axi_slave.awid
		.awaddr                 (subsys_hps_hps2fpga_translator_m0_awaddr),         //   input,   width = 38,                 .awaddr
		.awlen                  (subsys_hps_hps2fpga_translator_m0_awlen),          //   input,    width = 8,                 .awlen
		.awsize                 (subsys_hps_hps2fpga_translator_m0_awsize),         //   input,    width = 3,                 .awsize
		.awburst                (subsys_hps_hps2fpga_translator_m0_awburst),        //   input,    width = 2,                 .awburst
		.awlock                 (subsys_hps_hps2fpga_translator_m0_awlock),         //   input,    width = 1,                 .awlock
		.awcache                (subsys_hps_hps2fpga_translator_m0_awcache),        //   input,    width = 4,                 .awcache
		.awprot                 (subsys_hps_hps2fpga_translator_m0_awprot),         //   input,    width = 3,                 .awprot
		.awuser                 (subsys_hps_hps2fpga_translator_m0_awuser),         //   input,    width = 1,                 .awuser
		.awqos                  (subsys_hps_hps2fpga_translator_m0_awqos),          //   input,    width = 4,                 .awqos
		.awregion               (subsys_hps_hps2fpga_translator_m0_awregion),       //   input,    width = 4,                 .awregion
		.awvalid                (subsys_hps_hps2fpga_translator_m0_awvalid),        //   input,    width = 1,                 .awvalid
		.awready                (subsys_hps_hps2fpga_translator_m0_awready),        //  output,    width = 1,                 .awready
		.wdata                  (subsys_hps_hps2fpga_translator_m0_wdata),          //   input,  width = 128,                 .wdata
		.wstrb                  (subsys_hps_hps2fpga_translator_m0_wstrb),          //   input,   width = 16,                 .wstrb
		.wlast                  (subsys_hps_hps2fpga_translator_m0_wlast),          //   input,    width = 1,                 .wlast
		.wvalid                 (subsys_hps_hps2fpga_translator_m0_wvalid),         //   input,    width = 1,                 .wvalid
		.wuser                  (subsys_hps_hps2fpga_translator_m0_wuser),          //   input,    width = 1,                 .wuser
		.wready                 (subsys_hps_hps2fpga_translator_m0_wready),         //  output,    width = 1,                 .wready
		.bid                    (subsys_hps_hps2fpga_translator_m0_bid),            //  output,    width = 4,                 .bid
		.bresp                  (subsys_hps_hps2fpga_translator_m0_bresp),          //  output,    width = 2,                 .bresp
		.buser                  (subsys_hps_hps2fpga_translator_m0_buser),          //  output,    width = 1,                 .buser
		.bvalid                 (subsys_hps_hps2fpga_translator_m0_bvalid),         //  output,    width = 1,                 .bvalid
		.bready                 (subsys_hps_hps2fpga_translator_m0_bready),         //   input,    width = 1,                 .bready
		.arid                   (subsys_hps_hps2fpga_translator_m0_arid),           //   input,    width = 4,                 .arid
		.araddr                 (subsys_hps_hps2fpga_translator_m0_araddr),         //   input,   width = 38,                 .araddr
		.arlen                  (subsys_hps_hps2fpga_translator_m0_arlen),          //   input,    width = 8,                 .arlen
		.arsize                 (subsys_hps_hps2fpga_translator_m0_arsize),         //   input,    width = 3,                 .arsize
		.arburst                (subsys_hps_hps2fpga_translator_m0_arburst),        //   input,    width = 2,                 .arburst
		.arlock                 (subsys_hps_hps2fpga_translator_m0_arlock),         //   input,    width = 1,                 .arlock
		.arcache                (subsys_hps_hps2fpga_translator_m0_arcache),        //   input,    width = 4,                 .arcache
		.arprot                 (subsys_hps_hps2fpga_translator_m0_arprot),         //   input,    width = 3,                 .arprot
		.aruser                 (subsys_hps_hps2fpga_translator_m0_aruser),         //   input,    width = 1,                 .aruser
		.arqos                  (subsys_hps_hps2fpga_translator_m0_arqos),          //   input,    width = 4,                 .arqos
		.arregion               (subsys_hps_hps2fpga_translator_m0_arregion),       //   input,    width = 4,                 .arregion
		.arvalid                (subsys_hps_hps2fpga_translator_m0_arvalid),        //   input,    width = 1,                 .arvalid
		.arready                (subsys_hps_hps2fpga_translator_m0_arready),        //  output,    width = 1,                 .arready
		.rid                    (subsys_hps_hps2fpga_translator_m0_rid),            //  output,    width = 4,                 .rid
		.rdata                  (subsys_hps_hps2fpga_translator_m0_rdata),          //  output,  width = 128,                 .rdata
		.rresp                  (subsys_hps_hps2fpga_translator_m0_rresp),          //  output,    width = 2,                 .rresp
		.rlast                  (subsys_hps_hps2fpga_translator_m0_rlast),          //  output,    width = 1,                 .rlast
		.rvalid                 (subsys_hps_hps2fpga_translator_m0_rvalid),         //  output,    width = 1,                 .rvalid
		.rready                 (subsys_hps_hps2fpga_translator_m0_rready),         //   input,    width = 1,                 .rready
		.ruser                  (subsys_hps_hps2fpga_translator_m0_ruser),          //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                             // (terminated),                                
		.awuser_sai             (1'b0),                                             // (terminated),                                
		.wuser_datachk          (16'b0000000000000000),                             // (terminated),                                
		.wuser_data             (1'b0),                                             // (terminated),                                
		.wuser_poison           (2'b00),                                            // (terminated),                                
		.aruser_addrchk         (1'b0),                                             // (terminated),                                
		.aruser_sai             (1'b0),                                             // (terminated),                                
		.ruser_datachk          (),                                                 // (terminated),                                
		.ruser_data             (),                                                 // (terminated),                                
		.ruser_poison           (),                                                 // (terminated),                                
		.wid                    (4'b0000),                                          // (terminated),                                
		.arsnoop                (4'b0000),                                          // (terminated),                                
		.ardomain               (2'b00),                                            // (terminated),                                
		.arbar                  (2'b00),                                            // (terminated),                                
		.awsnoop                (3'b000),                                           // (terminated),                                
		.awdomain               (2'b00),                                            // (terminated),                                
		.awbar                  (2'b00),                                            // (terminated),                                
		.awunique               (1'b0)                                              // (terminated),                                
	);

	qsys_top_altera_merlin_axi_master_ni_1980_4qd7sla #(
		.ID_WIDTH                  (4),
		.ADDR_WIDTH                (29),
		.RDATA_WIDTH               (32),
		.WDATA_WIDTH               (32),
		.ADDR_USER_WIDTH           (1),
		.DATA_USER_WIDTH           (1),
		.AXI_BURST_LENGTH_WIDTH    (8),
		.AXI_LOCK_WIDTH            (1),
		.SAI_WIDTH                 (1),
		.ADDRCHK_WIDTH             (1),
		.USER_DATA_WIDTH           (1),
		.USE_PKT_DATACHK           (0),
		.USE_PKT_ADDRCHK           (0),
		.AXI_VERSION               ("AXI4"),
		.ACE_LITE_SUPPORT          (0),
		.ROLE_BASED_USER           (0),
		.WRITE_ISSUING_CAPABILITY  (16),
		.READ_ISSUING_CAPABILITY   (16),
		.PKT_BEGIN_BURST           (109),
		.PKT_CACHE_H               (128),
		.PKT_CACHE_L               (125),
		.PKT_ADDR_SIDEBAND_H       (107),
		.PKT_ADDR_SIDEBAND_L       (107),
		.PKT_PROTECTION_H          (124),
		.PKT_PROTECTION_L          (122),
		.PKT_BURST_SIZE_H          (104),
		.PKT_BURST_SIZE_L          (102),
		.PKT_BURST_TYPE_H          (106),
		.PKT_BURST_TYPE_L          (105),
		.PKT_RESPONSE_STATUS_L     (129),
		.PKT_RESPONSE_STATUS_H     (130),
		.PKT_BURSTWRAP_H           (101),
		.PKT_BURSTWRAP_L           (93),
		.PKT_BYTE_CNT_H            (92),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_EXCLUSIVE       (79),
		.PKT_TRANS_LOCK            (78),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (115),
		.PKT_SRC_ID_L              (114),
		.PKT_DEST_ID_H             (117),
		.PKT_DEST_ID_L             (116),
		.PKT_THREAD_ID_H           (121),
		.PKT_THREAD_ID_L           (118),
		.PKT_QOS_L                 (110),
		.PKT_QOS_H                 (113),
		.PKT_ORI_BURST_SIZE_L      (131),
		.PKT_ORI_BURST_SIZE_H      (133),
		.PKT_DATA_SIDEBAND_H       (108),
		.PKT_DATA_SIDEBAND_L       (108),
		.PKT_DOMAIN_H              (141),
		.PKT_DOMAIN_L              (140),
		.PKT_SNOOP_H               (139),
		.PKT_SNOOP_L               (136),
		.PKT_BARRIER_H             (135),
		.PKT_BARRIER_L             (134),
		.PKT_WUNIQUE               (142),
		.PKT_EOP_OOO               (149),
		.PKT_SOP_OOO               (150),
		.PKT_POISON_H              (143),
		.PKT_POISON_L              (143),
		.PKT_DATACHK_H             (144),
		.PKT_DATACHK_L             (144),
		.PKT_ADDRCHK_H             (147),
		.PKT_ADDRCHK_L             (146),
		.PKT_SAI_H                 (148),
		.PKT_SAI_L                 (148),
		.PKT_USER_DATA_H           (145),
		.PKT_USER_DATA_L           (145),
		.ST_DATA_W                 (158),
		.ST_CHANNEL_W              (5),
		.ID                        (2),
		.SYNC_RESET                (1)
	) subsys_hps_lwhps2fpga_agent (
		.aclk                   (clk_100_out_clk_clk),                                    //   input,    width = 1,              clk.clk
		.aresetn                (~subsys_debug_reset_reset_bridge_in_reset_reset),        //   input,    width = 1,        clk_reset.reset_n
		.write_cp_valid         (subsys_hps_lwhps2fpga_agent_write_cp_valid),             //  output,    width = 1,         write_cp.valid
		.write_cp_data          (subsys_hps_lwhps2fpga_agent_write_cp_data),              //  output,  width = 158,                 .data
		.write_cp_startofpacket (subsys_hps_lwhps2fpga_agent_write_cp_startofpacket),     //  output,    width = 1,                 .startofpacket
		.write_cp_endofpacket   (subsys_hps_lwhps2fpga_agent_write_cp_endofpacket),       //  output,    width = 1,                 .endofpacket
		.write_cp_ready         (subsys_hps_lwhps2fpga_agent_write_cp_ready),             //   input,    width = 1,                 .ready
		.write_rp_valid         (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_valid),         //   input,    width = 1,         write_rp.valid
		.write_rp_data          (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_data),          //   input,  width = 158,                 .data
		.write_rp_channel       (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_channel),       //   input,    width = 5,                 .channel
		.write_rp_startofpacket (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_startofpacket), //   input,    width = 1,                 .startofpacket
		.write_rp_endofpacket   (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_endofpacket),   //   input,    width = 1,                 .endofpacket
		.write_rp_ready         (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_ready),         //  output,    width = 1,                 .ready
		.read_cp_valid          (subsys_hps_lwhps2fpga_agent_read_cp_valid),              //  output,    width = 1,          read_cp.valid
		.read_cp_data           (subsys_hps_lwhps2fpga_agent_read_cp_data),               //  output,  width = 158,                 .data
		.read_cp_startofpacket  (subsys_hps_lwhps2fpga_agent_read_cp_startofpacket),      //  output,    width = 1,                 .startofpacket
		.read_cp_endofpacket    (subsys_hps_lwhps2fpga_agent_read_cp_endofpacket),        //  output,    width = 1,                 .endofpacket
		.read_cp_ready          (subsys_hps_lwhps2fpga_agent_read_cp_ready),              //   input,    width = 1,                 .ready
		.read_rp_valid          (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_valid),         //   input,    width = 1,          read_rp.valid
		.read_rp_data           (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_data),          //   input,  width = 158,                 .data
		.read_rp_channel        (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_channel),       //   input,    width = 5,                 .channel
		.read_rp_startofpacket  (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_startofpacket), //   input,    width = 1,                 .startofpacket
		.read_rp_endofpacket    (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_endofpacket),   //   input,    width = 1,                 .endofpacket
		.read_rp_ready          (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_ready),         //  output,    width = 1,                 .ready
		.awid                   (subsys_hps_lwhps2fpga_translator_m0_awid),               //   input,    width = 4, altera_axi_slave.awid
		.awaddr                 (subsys_hps_lwhps2fpga_translator_m0_awaddr),             //   input,   width = 29,                 .awaddr
		.awlen                  (subsys_hps_lwhps2fpga_translator_m0_awlen),              //   input,    width = 8,                 .awlen
		.awsize                 (subsys_hps_lwhps2fpga_translator_m0_awsize),             //   input,    width = 3,                 .awsize
		.awburst                (subsys_hps_lwhps2fpga_translator_m0_awburst),            //   input,    width = 2,                 .awburst
		.awlock                 (subsys_hps_lwhps2fpga_translator_m0_awlock),             //   input,    width = 1,                 .awlock
		.awcache                (subsys_hps_lwhps2fpga_translator_m0_awcache),            //   input,    width = 4,                 .awcache
		.awprot                 (subsys_hps_lwhps2fpga_translator_m0_awprot),             //   input,    width = 3,                 .awprot
		.awuser                 (subsys_hps_lwhps2fpga_translator_m0_awuser),             //   input,    width = 1,                 .awuser
		.awqos                  (subsys_hps_lwhps2fpga_translator_m0_awqos),              //   input,    width = 4,                 .awqos
		.awregion               (subsys_hps_lwhps2fpga_translator_m0_awregion),           //   input,    width = 4,                 .awregion
		.awvalid                (subsys_hps_lwhps2fpga_translator_m0_awvalid),            //   input,    width = 1,                 .awvalid
		.awready                (subsys_hps_lwhps2fpga_translator_m0_awready),            //  output,    width = 1,                 .awready
		.wdata                  (subsys_hps_lwhps2fpga_translator_m0_wdata),              //   input,   width = 32,                 .wdata
		.wstrb                  (subsys_hps_lwhps2fpga_translator_m0_wstrb),              //   input,    width = 4,                 .wstrb
		.wlast                  (subsys_hps_lwhps2fpga_translator_m0_wlast),              //   input,    width = 1,                 .wlast
		.wvalid                 (subsys_hps_lwhps2fpga_translator_m0_wvalid),             //   input,    width = 1,                 .wvalid
		.wuser                  (subsys_hps_lwhps2fpga_translator_m0_wuser),              //   input,    width = 1,                 .wuser
		.wready                 (subsys_hps_lwhps2fpga_translator_m0_wready),             //  output,    width = 1,                 .wready
		.bid                    (subsys_hps_lwhps2fpga_translator_m0_bid),                //  output,    width = 4,                 .bid
		.bresp                  (subsys_hps_lwhps2fpga_translator_m0_bresp),              //  output,    width = 2,                 .bresp
		.buser                  (subsys_hps_lwhps2fpga_translator_m0_buser),              //  output,    width = 1,                 .buser
		.bvalid                 (subsys_hps_lwhps2fpga_translator_m0_bvalid),             //  output,    width = 1,                 .bvalid
		.bready                 (subsys_hps_lwhps2fpga_translator_m0_bready),             //   input,    width = 1,                 .bready
		.arid                   (subsys_hps_lwhps2fpga_translator_m0_arid),               //   input,    width = 4,                 .arid
		.araddr                 (subsys_hps_lwhps2fpga_translator_m0_araddr),             //   input,   width = 29,                 .araddr
		.arlen                  (subsys_hps_lwhps2fpga_translator_m0_arlen),              //   input,    width = 8,                 .arlen
		.arsize                 (subsys_hps_lwhps2fpga_translator_m0_arsize),             //   input,    width = 3,                 .arsize
		.arburst                (subsys_hps_lwhps2fpga_translator_m0_arburst),            //   input,    width = 2,                 .arburst
		.arlock                 (subsys_hps_lwhps2fpga_translator_m0_arlock),             //   input,    width = 1,                 .arlock
		.arcache                (subsys_hps_lwhps2fpga_translator_m0_arcache),            //   input,    width = 4,                 .arcache
		.arprot                 (subsys_hps_lwhps2fpga_translator_m0_arprot),             //   input,    width = 3,                 .arprot
		.aruser                 (subsys_hps_lwhps2fpga_translator_m0_aruser),             //   input,    width = 1,                 .aruser
		.arqos                  (subsys_hps_lwhps2fpga_translator_m0_arqos),              //   input,    width = 4,                 .arqos
		.arregion               (subsys_hps_lwhps2fpga_translator_m0_arregion),           //   input,    width = 4,                 .arregion
		.arvalid                (subsys_hps_lwhps2fpga_translator_m0_arvalid),            //   input,    width = 1,                 .arvalid
		.arready                (subsys_hps_lwhps2fpga_translator_m0_arready),            //  output,    width = 1,                 .arready
		.rid                    (subsys_hps_lwhps2fpga_translator_m0_rid),                //  output,    width = 4,                 .rid
		.rdata                  (subsys_hps_lwhps2fpga_translator_m0_rdata),              //  output,   width = 32,                 .rdata
		.rresp                  (subsys_hps_lwhps2fpga_translator_m0_rresp),              //  output,    width = 2,                 .rresp
		.rlast                  (subsys_hps_lwhps2fpga_translator_m0_rlast),              //  output,    width = 1,                 .rlast
		.rvalid                 (subsys_hps_lwhps2fpga_translator_m0_rvalid),             //  output,    width = 1,                 .rvalid
		.rready                 (subsys_hps_lwhps2fpga_translator_m0_rready),             //   input,    width = 1,                 .rready
		.ruser                  (subsys_hps_lwhps2fpga_translator_m0_ruser),              //  output,    width = 1,                 .ruser
		.awuser_addrchk         (1'b0),                                                   // (terminated),                                
		.awuser_sai             (1'b0),                                                   // (terminated),                                
		.wuser_datachk          (4'b0000),                                                // (terminated),                                
		.wuser_data             (1'b0),                                                   // (terminated),                                
		.wuser_poison           (1'b0),                                                   // (terminated),                                
		.aruser_addrchk         (1'b0),                                                   // (terminated),                                
		.aruser_sai             (1'b0),                                                   // (terminated),                                
		.ruser_datachk          (),                                                       // (terminated),                                
		.ruser_data             (),                                                       // (terminated),                                
		.ruser_poison           (),                                                       // (terminated),                                
		.wid                    (4'b0000),                                                // (terminated),                                
		.arsnoop                (4'b0000),                                                // (terminated),                                
		.ardomain               (2'b00),                                                  // (terminated),                                
		.arbar                  (2'b00),                                                  // (terminated),                                
		.awsnoop                (3'b000),                                                 // (terminated),                                
		.awdomain               (2'b00),                                                  // (terminated),                                
		.awbar                  (2'b00),                                                  // (terminated),                                
		.awunique               (1'b0)                                                    // (terminated),                                
	);

	qsys_top_altera_merlin_axi_slave_ni_1990_u4ur3ai #(
		.PKT_QOS_H                   (221),
		.PKT_QOS_L                   (218),
		.PKT_THREAD_ID_H             (229),
		.PKT_THREAD_ID_L             (226),
		.PKT_RESPONSE_STATUS_H       (238),
		.PKT_RESPONSE_STATUS_L       (237),
		.PKT_BEGIN_BURST             (217),
		.PKT_CACHE_H                 (236),
		.PKT_CACHE_L                 (233),
		.PKT_DATA_SIDEBAND_H         (216),
		.PKT_DATA_SIDEBAND_L         (216),
		.PKT_ADDR_SIDEBAND_H         (215),
		.PKT_ADDR_SIDEBAND_L         (215),
		.PKT_BURST_TYPE_H            (214),
		.PKT_BURST_TYPE_L            (213),
		.PKT_PROTECTION_H            (232),
		.PKT_PROTECTION_L            (230),
		.PKT_BURST_SIZE_H            (212),
		.PKT_BURST_SIZE_L            (210),
		.PKT_BURSTWRAP_H             (209),
		.PKT_BURSTWRAP_L             (201),
		.PKT_BYTE_CNT_H              (200),
		.PKT_BYTE_CNT_L              (188),
		.PKT_ADDR_H                  (181),
		.PKT_ADDR_L                  (144),
		.PKT_TRANS_EXCLUSIVE         (187),
		.PKT_TRANS_LOCK              (186),
		.PKT_TRANS_COMPRESSED_READ   (182),
		.PKT_TRANS_POSTED            (183),
		.PKT_TRANS_WRITE             (184),
		.PKT_TRANS_READ              (185),
		.PKT_DATA_H                  (127),
		.PKT_DATA_L                  (0),
		.PKT_BYTEEN_H                (143),
		.PKT_BYTEEN_L                (128),
		.PKT_SRC_ID_H                (223),
		.PKT_SRC_ID_L                (222),
		.PKT_DEST_ID_H               (225),
		.PKT_DEST_ID_L               (224),
		.PKT_ORI_BURST_SIZE_L        (239),
		.PKT_ORI_BURST_SIZE_H        (241),
		.PKT_DOMAIN_L                (248),
		.PKT_DOMAIN_H                (249),
		.PKT_SNOOP_L                 (244),
		.PKT_SNOOP_H                 (247),
		.PKT_BARRIER_L               (242),
		.PKT_BARRIER_H               (243),
		.PKT_WUNIQUE                 (250),
		.PKT_EOP_OOO                 (257),
		.PKT_SOP_OOO                 (258),
		.PKT_POISON_H                (251),
		.PKT_POISON_L                (251),
		.PKT_DATACHK_H               (252),
		.PKT_DATACHK_L               (252),
		.PKT_ADDRCHK_H               (255),
		.PKT_ADDRCHK_L               (254),
		.PKT_SAI_H                   (256),
		.PKT_SAI_L                   (256),
		.PKT_USER_DATA_H             (253),
		.PKT_USER_DATA_L             (253),
		.SAI_WIDTH                   (1),
		.ADDRCHK_WIDTH               (1),
		.USER_DATA_WIDTH             (1),
		.ADDR_USER_WIDTH             (1),
		.DATA_USER_WIDTH             (1),
		.ST_DATA_W                   (266),
		.ADDR_WIDTH                  (18),
		.RDATA_WIDTH                 (128),
		.WDATA_WIDTH                 (128),
		.ST_CHANNEL_W                (5),
		.AXI_SLAVE_ID_W              (10),
		.ACE_LITE_SUPPORT            (0),
		.PASS_ID_TO_SLAVE            (1),
		.AXI_VERSION                 ("AXI4"),
		.WRITE_ACCEPTANCE_CAPABILITY (1),
		.READ_ACCEPTANCE_CAPABILITY  (1),
		.USE_PKT_DATACHK             (0),
		.USE_PKT_ADDRCHK             (0),
		.SYNC_RESET                  (1),
		.USE_MEMORY_BLOCKS           (0),
		.ROLE_BASED_USER             (0),
		.ENABLE_OOO                  (0),
		.REORDER_BUFFER              (0)
	) ocm_axi_s1_agent (
		.aclk                   (clk_100_out_clk_clk),                             //   input,    width = 1,        clock_sink.clk
		.aresetn                (~subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1,        reset_sink.reset_n
		.read_cp_valid          (agent_pipeline_001_source0_valid),                //   input,    width = 1,           read_cp.valid
		.read_cp_ready          (agent_pipeline_001_source0_ready),                //  output,    width = 1,                  .ready
		.read_cp_data           (agent_pipeline_001_source0_data),                 //   input,  width = 266,                  .data
		.read_cp_channel        (agent_pipeline_001_source0_channel),              //   input,    width = 5,                  .channel
		.read_cp_startofpacket  (agent_pipeline_001_source0_startofpacket),        //   input,    width = 1,                  .startofpacket
		.read_cp_endofpacket    (agent_pipeline_001_source0_endofpacket),          //   input,    width = 1,                  .endofpacket
		.write_cp_ready         (agent_pipeline_source0_ready),                    //  output,    width = 1,          write_cp.ready
		.write_cp_valid         (agent_pipeline_source0_valid),                    //   input,    width = 1,                  .valid
		.write_cp_data          (agent_pipeline_source0_data),                     //   input,  width = 266,                  .data
		.write_cp_channel       (agent_pipeline_source0_channel),                  //   input,    width = 5,                  .channel
		.write_cp_startofpacket (agent_pipeline_source0_startofpacket),            //   input,    width = 1,                  .startofpacket
		.write_cp_endofpacket   (agent_pipeline_source0_endofpacket),              //   input,    width = 1,                  .endofpacket
		.read_rp_ready          (ocm_axi_s1_agent_read_rp_ready),                  //   input,    width = 1,           read_rp.ready
		.read_rp_valid          (ocm_axi_s1_agent_read_rp_valid),                  //  output,    width = 1,                  .valid
		.read_rp_data           (ocm_axi_s1_agent_read_rp_data),                   //  output,  width = 266,                  .data
		.read_rp_startofpacket  (ocm_axi_s1_agent_read_rp_startofpacket),          //  output,    width = 1,                  .startofpacket
		.read_rp_endofpacket    (ocm_axi_s1_agent_read_rp_endofpacket),            //  output,    width = 1,                  .endofpacket
		.write_rp_ready         (ocm_axi_s1_agent_write_rp_ready),                 //   input,    width = 1,          write_rp.ready
		.write_rp_valid         (ocm_axi_s1_agent_write_rp_valid),                 //  output,    width = 1,                  .valid
		.write_rp_data          (ocm_axi_s1_agent_write_rp_data),                  //  output,  width = 266,                  .data
		.write_rp_startofpacket (ocm_axi_s1_agent_write_rp_startofpacket),         //  output,    width = 1,                  .startofpacket
		.write_rp_endofpacket   (ocm_axi_s1_agent_write_rp_endofpacket),           //  output,    width = 1,                  .endofpacket
		.awid                   (ocm_axi_s1_agent_altera_axi_master_awid),         //  output,   width = 10, altera_axi_master.awid
		.awaddr                 (ocm_axi_s1_agent_altera_axi_master_awaddr),       //  output,   width = 18,                  .awaddr
		.awlen                  (ocm_axi_s1_agent_altera_axi_master_awlen),        //  output,    width = 8,                  .awlen
		.awsize                 (ocm_axi_s1_agent_altera_axi_master_awsize),       //  output,    width = 3,                  .awsize
		.awburst                (ocm_axi_s1_agent_altera_axi_master_awburst),      //  output,    width = 2,                  .awburst
		.awlock                 (ocm_axi_s1_agent_altera_axi_master_awlock),       //  output,    width = 1,                  .awlock
		.awcache                (ocm_axi_s1_agent_altera_axi_master_awcache),      //  output,    width = 4,                  .awcache
		.awprot                 (ocm_axi_s1_agent_altera_axi_master_awprot),       //  output,    width = 3,                  .awprot
		.awuser                 (ocm_axi_s1_agent_altera_axi_master_awuser),       //  output,    width = 1,                  .awuser
		.awvalid                (ocm_axi_s1_agent_altera_axi_master_awvalid),      //  output,    width = 1,                  .awvalid
		.awready                (ocm_axi_s1_agent_altera_axi_master_awready),      //   input,    width = 1,                  .awready
		.wdata                  (ocm_axi_s1_agent_altera_axi_master_wdata),        //  output,  width = 128,                  .wdata
		.wstrb                  (ocm_axi_s1_agent_altera_axi_master_wstrb),        //  output,   width = 16,                  .wstrb
		.wlast                  (ocm_axi_s1_agent_altera_axi_master_wlast),        //  output,    width = 1,                  .wlast
		.wvalid                 (ocm_axi_s1_agent_altera_axi_master_wvalid),       //  output,    width = 1,                  .wvalid
		.wready                 (ocm_axi_s1_agent_altera_axi_master_wready),       //   input,    width = 1,                  .wready
		.bid                    (ocm_axi_s1_agent_altera_axi_master_bid),          //   input,   width = 10,                  .bid
		.bresp                  (ocm_axi_s1_agent_altera_axi_master_bresp),        //   input,    width = 2,                  .bresp
		.bvalid                 (ocm_axi_s1_agent_altera_axi_master_bvalid),       //   input,    width = 1,                  .bvalid
		.bready                 (ocm_axi_s1_agent_altera_axi_master_bready),       //  output,    width = 1,                  .bready
		.arid                   (ocm_axi_s1_agent_altera_axi_master_arid),         //  output,   width = 10,                  .arid
		.araddr                 (ocm_axi_s1_agent_altera_axi_master_araddr),       //  output,   width = 18,                  .araddr
		.arlen                  (ocm_axi_s1_agent_altera_axi_master_arlen),        //  output,    width = 8,                  .arlen
		.arsize                 (ocm_axi_s1_agent_altera_axi_master_arsize),       //  output,    width = 3,                  .arsize
		.arburst                (ocm_axi_s1_agent_altera_axi_master_arburst),      //  output,    width = 2,                  .arburst
		.arlock                 (ocm_axi_s1_agent_altera_axi_master_arlock),       //  output,    width = 1,                  .arlock
		.arcache                (ocm_axi_s1_agent_altera_axi_master_arcache),      //  output,    width = 4,                  .arcache
		.arprot                 (ocm_axi_s1_agent_altera_axi_master_arprot),       //  output,    width = 3,                  .arprot
		.aruser                 (ocm_axi_s1_agent_altera_axi_master_aruser),       //  output,    width = 1,                  .aruser
		.arvalid                (ocm_axi_s1_agent_altera_axi_master_arvalid),      //  output,    width = 1,                  .arvalid
		.arready                (ocm_axi_s1_agent_altera_axi_master_arready),      //   input,    width = 1,                  .arready
		.rid                    (ocm_axi_s1_agent_altera_axi_master_rid),          //   input,   width = 10,                  .rid
		.rdata                  (ocm_axi_s1_agent_altera_axi_master_rdata),        //   input,  width = 128,                  .rdata
		.rresp                  (ocm_axi_s1_agent_altera_axi_master_rresp),        //   input,    width = 2,                  .rresp
		.rlast                  (ocm_axi_s1_agent_altera_axi_master_rlast),        //   input,    width = 1,                  .rlast
		.rvalid                 (ocm_axi_s1_agent_altera_axi_master_rvalid),       //   input,    width = 1,                  .rvalid
		.rready                 (ocm_axi_s1_agent_altera_axi_master_rready),       //  output,    width = 1,                  .rready
		.wuser                  (ocm_axi_s1_agent_altera_axi_master_wuser),        //  output,    width = 1,                  .wuser
		.awqos                  (ocm_axi_s1_agent_altera_axi_master_awqos),        //  output,    width = 4,                  .awqos
		.awregion               (ocm_axi_s1_agent_altera_axi_master_awregion),     //  output,    width = 4,                  .awregion
		.ruser                  (ocm_axi_s1_agent_altera_axi_master_ruser),        //   input,    width = 1,                  .ruser
		.buser                  (ocm_axi_s1_agent_altera_axi_master_buser),        //   input,    width = 1,                  .buser
		.arqos                  (ocm_axi_s1_agent_altera_axi_master_arqos),        //  output,    width = 4,                  .arqos
		.arregion               (ocm_axi_s1_agent_altera_axi_master_arregion),     //  output,    width = 4,                  .arregion
		.awuser_addrchk         (),                                                // (terminated),                                 
		.awuser_sai             (),                                                // (terminated),                                 
		.wuser_datachk          (),                                                // (terminated),                                 
		.wuser_data             (),                                                // (terminated),                                 
		.wuser_poison           (),                                                // (terminated),                                 
		.aruser_addrchk         (),                                                // (terminated),                                 
		.aruser_sai             (),                                                // (terminated),                                 
		.ruser_datachk          (16'b0000000000000000),                            // (terminated),                                 
		.ruser_data             (1'b0),                                            // (terminated),                                 
		.ruser_poison           (2'b00),                                           // (terminated),                                 
		.wid                    (),                                                // (terminated),                                 
		.arsnoop                (),                                                // (terminated),                                 
		.ardomain               (),                                                // (terminated),                                 
		.arbar                  (),                                                // (terminated),                                 
		.awsnoop                (),                                                // (terminated),                                 
		.awdomain               (),                                                // (terminated),                                 
		.awbar                  (),                                                // (terminated),                                 
		.awunique               ()                                                 // (terminated),                                 
	);

	qsys_top_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (133),
		.PKT_ORI_BURST_SIZE_L      (131),
		.PKT_RESPONSE_STATUS_H     (130),
		.PKT_RESPONSE_STATUS_L     (129),
		.PKT_BURST_SIZE_H          (104),
		.PKT_BURST_SIZE_L          (102),
		.PKT_TRANS_LOCK            (78),
		.PKT_BEGIN_BURST           (109),
		.PKT_PROTECTION_H          (124),
		.PKT_PROTECTION_L          (122),
		.PKT_BURSTWRAP_H           (101),
		.PKT_BURSTWRAP_L           (93),
		.PKT_BYTE_CNT_H            (92),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (115),
		.PKT_SRC_ID_L              (114),
		.PKT_DEST_ID_H             (117),
		.PKT_DEST_ID_L             (116),
		.PKT_POISON_H              (143),
		.PKT_POISON_L              (143),
		.PKT_DATACHK_H             (144),
		.PKT_DATACHK_L             (144),
		.PKT_SAI_H                 (148),
		.PKT_SAI_L                 (148),
		.PKT_ADDRCHK_H             (147),
		.PKT_ADDRCHK_L             (146),
		.PKT_USER_DATA_H           (145),
		.PKT_USER_DATA_L           (145),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (5),
		.ST_DATA_W                 (158),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) subsys_hps_usb31_phy_reconfig_slave_agent (
		.clk                     (clk_100_out_clk_clk),                                                  //   input,    width = 1,             clk.clk
		.reset                   (subsys_debug_reset_reset_bridge_in_reset_reset),                       //   input,    width = 1,       clk_reset.reset
		.m0_address              (subsys_hps_usb31_phy_reconfig_slave_agent_m0_address),                 //  output,   width = 38,              m0.address
		.m0_burstcount           (subsys_hps_usb31_phy_reconfig_slave_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (subsys_hps_usb31_phy_reconfig_slave_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (subsys_hps_usb31_phy_reconfig_slave_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (subsys_hps_usb31_phy_reconfig_slave_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (subsys_hps_usb31_phy_reconfig_slave_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (subsys_hps_usb31_phy_reconfig_slave_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (subsys_hps_usb31_phy_reconfig_slave_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (subsys_hps_usb31_phy_reconfig_slave_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (subsys_hps_usb31_phy_reconfig_slave_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (subsys_hps_usb31_phy_reconfig_slave_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (subsys_hps_usb31_phy_reconfig_slave_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (subsys_hps_usb31_phy_reconfig_slave_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (subsys_hps_usb31_phy_reconfig_slave_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (subsys_hps_usb31_phy_reconfig_slave_agent_rp_data),                    //  output,  width = 158,                .data
		.rp_startofpacket        (subsys_hps_usb31_phy_reconfig_slave_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_004_source0_ready),                                     //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_004_source0_valid),                                     //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_004_source0_data),                                      //   input,  width = 158,                .data
		.cp_startofpacket        (agent_pipeline_004_source0_startofpacket),                             //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_004_source0_endofpacket),                               //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_004_source0_channel),                                   //   input,    width = 5,                .channel
		.rf_sink_ready           (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_data),          //   input,  width = 159,                .data
		.rf_source_ready         (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_data),             //  output,  width = 159,                .data
		.rdata_fifo_sink_ready   (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                                // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                                 // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                                  // (terminated),                               
	);

	qsys_top_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (159),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo (
		.clk               (clk_100_out_clk_clk),                                                  //   input,    width = 1,       clk.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                               //   input,    width = 1, clk_reset.reset
		.in_data           (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_data),             //   input,  width = 159,        in.data
		.in_valid          (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_usb31_phy_reconfig_slave_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_data),          //  output,  width = 159,       out.data
		.out_valid         (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (subsys_hps_usb31_phy_reconfig_slave_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                                // (terminated),                         
		.csr_read          (1'b0),                                                                 // (terminated),                         
		.csr_write         (1'b0),                                                                 // (terminated),                         
		.csr_readdata      (),                                                                     // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                                 // (terminated),                         
		.almost_full_data  (),                                                                     // (terminated),                         
		.almost_empty_data (),                                                                     // (terminated),                         
		.in_empty          (1'b0),                                                                 // (terminated),                         
		.out_empty         (),                                                                     // (terminated),                         
		.in_error          (1'b0),                                                                 // (terminated),                         
		.out_error         (),                                                                     // (terminated),                         
		.in_channel        (1'b0),                                                                 // (terminated),                         
		.out_channel       ()                                                                      // (terminated),                         
	);

	qsys_top_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo (
		.clk               (clk_100_out_clk_clk),                                            //   input,   width = 1,       clk.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                         //   input,   width = 1, clk_reset.reset
		.in_data           (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (subsys_hps_usb31_phy_reconfig_slave_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                          // (terminated),                        
		.csr_read          (1'b0),                                                           // (terminated),                        
		.csr_write         (1'b0),                                                           // (terminated),                        
		.csr_readdata      (),                                                               // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                           // (terminated),                        
		.almost_full_data  (),                                                               // (terminated),                        
		.almost_empty_data (),                                                               // (terminated),                        
		.in_startofpacket  (1'b0),                                                           // (terminated),                        
		.in_endofpacket    (1'b0),                                                           // (terminated),                        
		.out_startofpacket (),                                                               // (terminated),                        
		.out_endofpacket   (),                                                               // (terminated),                        
		.in_empty          (1'b0),                                                           // (terminated),                        
		.out_empty         (),                                                               // (terminated),                        
		.in_error          (1'b0),                                                           // (terminated),                        
		.out_error         (),                                                               // (terminated),                        
		.in_channel        (1'b0),                                                           // (terminated),                        
		.out_channel       ()                                                                // (terminated),                        
	);

	qsys_top_altera_merlin_slave_agent_1921_b6r3djy #(
		.PKT_ORI_BURST_SIZE_H      (133),
		.PKT_ORI_BURST_SIZE_L      (131),
		.PKT_RESPONSE_STATUS_H     (130),
		.PKT_RESPONSE_STATUS_L     (129),
		.PKT_BURST_SIZE_H          (104),
		.PKT_BURST_SIZE_L          (102),
		.PKT_TRANS_LOCK            (78),
		.PKT_BEGIN_BURST           (109),
		.PKT_PROTECTION_H          (124),
		.PKT_PROTECTION_L          (122),
		.PKT_BURSTWRAP_H           (101),
		.PKT_BURSTWRAP_L           (93),
		.PKT_BYTE_CNT_H            (92),
		.PKT_BYTE_CNT_L            (80),
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_POSTED          (75),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.PKT_DATA_H                (31),
		.PKT_DATA_L                (0),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_SRC_ID_H              (115),
		.PKT_SRC_ID_L              (114),
		.PKT_DEST_ID_H             (117),
		.PKT_DEST_ID_L             (116),
		.PKT_POISON_H              (143),
		.PKT_POISON_L              (143),
		.PKT_DATACHK_H             (144),
		.PKT_DATACHK_L             (144),
		.PKT_SAI_H                 (148),
		.PKT_SAI_L                 (148),
		.PKT_ADDRCHK_H             (147),
		.PKT_ADDRCHK_L             (146),
		.PKT_USER_DATA_H           (145),
		.PKT_USER_DATA_L           (145),
		.PKT_SYMBOL_W              (8),
		.ST_CHANNEL_W              (5),
		.ST_DATA_W                 (158),
		.AVS_BURSTCOUNT_W          (3),
		.SUPPRESS_0_BYTEEN_CMD     (1),
		.USE_MEMORY_BLOCKS         (0),
		.PREVENT_FIFO_OVERFLOW     (1),
		.USE_READRESPONSE          (0),
		.USE_WRITERESPONSE         (0),
		.ECC_ENABLE                (0),
		.SYNC_RESET                (1),
		.USE_PKT_DATACHK           (0),
		.ROLE_BASED_USER           (0)
	) subsys_periph_pb_cpu_0_s0_agent (
		.clk                     (clk_100_out_clk_clk),                                        //   input,    width = 1,             clk.clk
		.reset                   (subsys_debug_reset_reset_bridge_in_reset_reset),             //   input,    width = 1,       clk_reset.reset
		.m0_address              (subsys_periph_pb_cpu_0_s0_agent_m0_address),                 //  output,   width = 38,              m0.address
		.m0_burstcount           (subsys_periph_pb_cpu_0_s0_agent_m0_burstcount),              //  output,    width = 3,                .burstcount
		.m0_byteenable           (subsys_periph_pb_cpu_0_s0_agent_m0_byteenable),              //  output,    width = 4,                .byteenable
		.m0_debugaccess          (subsys_periph_pb_cpu_0_s0_agent_m0_debugaccess),             //  output,    width = 1,                .debugaccess
		.m0_lock                 (subsys_periph_pb_cpu_0_s0_agent_m0_lock),                    //  output,    width = 1,                .lock
		.m0_readdata             (subsys_periph_pb_cpu_0_s0_agent_m0_readdata),                //   input,   width = 32,                .readdata
		.m0_readdatavalid        (subsys_periph_pb_cpu_0_s0_agent_m0_readdatavalid),           //   input,    width = 1,                .readdatavalid
		.m0_read                 (subsys_periph_pb_cpu_0_s0_agent_m0_read),                    //  output,    width = 1,                .read
		.m0_waitrequest          (subsys_periph_pb_cpu_0_s0_agent_m0_waitrequest),             //   input,    width = 1,                .waitrequest
		.m0_writedata            (subsys_periph_pb_cpu_0_s0_agent_m0_writedata),               //  output,   width = 32,                .writedata
		.m0_write                (subsys_periph_pb_cpu_0_s0_agent_m0_write),                   //  output,    width = 1,                .write
		.rp_endofpacket          (subsys_periph_pb_cpu_0_s0_agent_rp_endofpacket),             //  output,    width = 1,              rp.endofpacket
		.rp_ready                (subsys_periph_pb_cpu_0_s0_agent_rp_ready),                   //   input,    width = 1,                .ready
		.rp_valid                (subsys_periph_pb_cpu_0_s0_agent_rp_valid),                   //  output,    width = 1,                .valid
		.rp_data                 (subsys_periph_pb_cpu_0_s0_agent_rp_data),                    //  output,  width = 158,                .data
		.rp_startofpacket        (subsys_periph_pb_cpu_0_s0_agent_rp_startofpacket),           //  output,    width = 1,                .startofpacket
		.cp_ready                (agent_pipeline_006_source0_ready),                           //  output,    width = 1,              cp.ready
		.cp_valid                (agent_pipeline_006_source0_valid),                           //   input,    width = 1,                .valid
		.cp_data                 (agent_pipeline_006_source0_data),                            //   input,  width = 158,                .data
		.cp_startofpacket        (agent_pipeline_006_source0_startofpacket),                   //   input,    width = 1,                .startofpacket
		.cp_endofpacket          (agent_pipeline_006_source0_endofpacket),                     //   input,    width = 1,                .endofpacket
		.cp_channel              (agent_pipeline_006_source0_channel),                         //   input,    width = 5,                .channel
		.rf_sink_ready           (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_ready),         //  output,    width = 1,         rf_sink.ready
		.rf_sink_valid           (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_valid),         //   input,    width = 1,                .valid
		.rf_sink_startofpacket   (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_startofpacket), //   input,    width = 1,                .startofpacket
		.rf_sink_endofpacket     (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_endofpacket),   //   input,    width = 1,                .endofpacket
		.rf_sink_data            (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_data),          //   input,  width = 159,                .data
		.rf_source_ready         (subsys_periph_pb_cpu_0_s0_agent_rf_source_ready),            //   input,    width = 1,       rf_source.ready
		.rf_source_valid         (subsys_periph_pb_cpu_0_s0_agent_rf_source_valid),            //  output,    width = 1,                .valid
		.rf_source_startofpacket (subsys_periph_pb_cpu_0_s0_agent_rf_source_startofpacket),    //  output,    width = 1,                .startofpacket
		.rf_source_endofpacket   (subsys_periph_pb_cpu_0_s0_agent_rf_source_endofpacket),      //  output,    width = 1,                .endofpacket
		.rf_source_data          (subsys_periph_pb_cpu_0_s0_agent_rf_source_data),             //  output,  width = 159,                .data
		.rdata_fifo_sink_ready   (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_ready),       //  output,    width = 1, rdata_fifo_sink.ready
		.rdata_fifo_sink_valid   (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_valid),       //   input,    width = 1,                .valid
		.rdata_fifo_sink_data    (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_data),        //   input,   width = 34,                .data
		.rdata_fifo_src_ready    (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_ready),       //   input,    width = 1,  rdata_fifo_src.ready
		.rdata_fifo_src_valid    (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_valid),       //  output,    width = 1,                .valid
		.rdata_fifo_src_data     (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_data),        //  output,   width = 34,                .data
		.m0_response             (2'b00),                                                      // (terminated),                               
		.m0_writeresponsevalid   (1'b0),                                                       // (terminated),                               
		.rdata_fifo_sink_error   (1'b0)                                                        // (terminated),                               
	);

	qsys_top_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (159),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (1),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (1),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) subsys_periph_pb_cpu_0_s0_agent_rsp_fifo (
		.clk               (clk_100_out_clk_clk),                                        //   input,    width = 1,       clk.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                     //   input,    width = 1, clk_reset.reset
		.in_data           (subsys_periph_pb_cpu_0_s0_agent_rf_source_data),             //   input,  width = 159,        in.data
		.in_valid          (subsys_periph_pb_cpu_0_s0_agent_rf_source_valid),            //   input,    width = 1,          .valid
		.in_ready          (subsys_periph_pb_cpu_0_s0_agent_rf_source_ready),            //  output,    width = 1,          .ready
		.in_startofpacket  (subsys_periph_pb_cpu_0_s0_agent_rf_source_startofpacket),    //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_periph_pb_cpu_0_s0_agent_rf_source_endofpacket),      //   input,    width = 1,          .endofpacket
		.out_data          (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_data),          //  output,  width = 159,       out.data
		.out_valid         (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_valid),         //  output,    width = 1,          .valid
		.out_ready         (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_ready),         //   input,    width = 1,          .ready
		.out_startofpacket (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_out_endofpacket),   //  output,    width = 1,          .endofpacket
		.csr_address       (2'b00),                                                      // (terminated),                         
		.csr_read          (1'b0),                                                       // (terminated),                         
		.csr_write         (1'b0),                                                       // (terminated),                         
		.csr_readdata      (),                                                           // (terminated),                         
		.csr_writedata     (32'b00000000000000000000000000000000),                       // (terminated),                         
		.almost_full_data  (),                                                           // (terminated),                         
		.almost_empty_data (),                                                           // (terminated),                         
		.in_empty          (1'b0),                                                       // (terminated),                         
		.out_empty         (),                                                           // (terminated),                         
		.in_error          (1'b0),                                                       // (terminated),                         
		.out_error         (),                                                           // (terminated),                         
		.in_channel        (1'b0),                                                       // (terminated),                         
		.out_channel       ()                                                            // (terminated),                         
	);

	qsys_top_altera_avalon_sc_fifo_1932_w27kryi #(
		.SYMBOLS_PER_BEAT    (1),
		.BITS_PER_SYMBOL     (34),
		.FIFO_DEPTH          (2),
		.CHANNEL_WIDTH       (0),
		.ERROR_WIDTH         (0),
		.USE_PACKETS         (0),
		.USE_FILL_LEVEL      (0),
		.EMPTY_LATENCY       (0),
		.USE_MEMORY_BLOCKS   (0),
		.USE_STORE_FORWARD   (0),
		.USE_ALMOST_FULL_IF  (0),
		.USE_ALMOST_EMPTY_IF (0),
		.EMPTY_WIDTH         (1),
		.MEM_TYPE            ("M20K"),
		.SYNC_RESET          (1)
	) subsys_periph_pb_cpu_0_s0_agent_rdata_fifo (
		.clk               (clk_100_out_clk_clk),                                  //   input,   width = 1,       clk.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),               //   input,   width = 1, clk_reset.reset
		.in_data           (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_data),  //   input,  width = 34,        in.data
		.in_valid          (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_valid), //   input,   width = 1,          .valid
		.in_ready          (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_src_ready), //  output,   width = 1,          .ready
		.out_data          (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_data),  //  output,  width = 34,       out.data
		.out_valid         (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_valid), //  output,   width = 1,          .valid
		.out_ready         (subsys_periph_pb_cpu_0_s0_agent_rdata_fifo_out_ready), //   input,   width = 1,          .ready
		.csr_address       (2'b00),                                                // (terminated),                        
		.csr_read          (1'b0),                                                 // (terminated),                        
		.csr_write         (1'b0),                                                 // (terminated),                        
		.csr_readdata      (),                                                     // (terminated),                        
		.csr_writedata     (32'b00000000000000000000000000000000),                 // (terminated),                        
		.almost_full_data  (),                                                     // (terminated),                        
		.almost_empty_data (),                                                     // (terminated),                        
		.in_startofpacket  (1'b0),                                                 // (terminated),                        
		.in_endofpacket    (1'b0),                                                 // (terminated),                        
		.out_startofpacket (),                                                     // (terminated),                        
		.out_endofpacket   (),                                                     // (terminated),                        
		.in_empty          (1'b0),                                                 // (terminated),                        
		.out_empty         (),                                                     // (terminated),                        
		.in_error          (1'b0),                                                 // (terminated),                        
		.out_error         (),                                                     // (terminated),                        
		.in_channel        (1'b0),                                                 // (terminated),                        
		.out_channel       ()                                                      // (terminated),                        
	);

	qsys_top_altera_merlin_router_1921_fw7etti router (
		.sink_ready         (subsys_debug_fpga_m_master_agent_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_debug_fpga_m_master_agent_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (subsys_debug_fpga_m_master_agent_cp_data),          //   input,  width = 158,          .data
		.sink_startofpacket (subsys_debug_fpga_m_master_agent_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_debug_fpga_m_master_agent_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset),    //   input,    width = 1, clk_reset.reset
		.src_ready          (router_src_ready),                                  //   input,    width = 1,       src.ready
		.src_valid          (router_src_valid),                                  //  output,    width = 1,          .valid
		.src_data           (router_src_data),                                   //  output,  width = 158,          .data
		.src_channel        (router_src_channel),                                //  output,    width = 5,          .channel
		.src_startofpacket  (router_src_startofpacket),                          //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_src_endofpacket)                             //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_bija6bq router_001 (
		.sink_ready         (subsys_hps_hps2fpga_agent_write_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_hps_hps2fpga_agent_write_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (subsys_hps_hps2fpga_agent_write_cp_data),          //   input,  width = 266,          .data
		.sink_startofpacket (subsys_hps_hps2fpga_agent_write_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_hps2fpga_agent_write_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                              //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset),   //   input,    width = 1, clk_reset.reset
		.src_ready          (router_001_src_ready),                             //   input,    width = 1,       src.ready
		.src_valid          (router_001_src_valid),                             //  output,    width = 1,          .valid
		.src_data           (router_001_src_data),                              //  output,  width = 266,          .data
		.src_channel        (router_001_src_channel),                           //  output,    width = 5,          .channel
		.src_startofpacket  (router_001_src_startofpacket),                     //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_001_src_endofpacket)                        //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_figp5wa router_002 (
		.sink_ready         (subsys_hps_hps2fpga_agent_read_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_hps_hps2fpga_agent_read_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (subsys_hps_hps2fpga_agent_read_cp_data),          //   input,  width = 266,          .data
		.sink_startofpacket (subsys_hps_hps2fpga_agent_read_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_hps2fpga_agent_read_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                             //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset),  //   input,    width = 1, clk_reset.reset
		.src_ready          (router_002_src_ready),                            //   input,    width = 1,       src.ready
		.src_valid          (router_002_src_valid),                            //  output,    width = 1,          .valid
		.src_data           (router_002_src_data),                             //  output,  width = 266,          .data
		.src_channel        (router_002_src_channel),                          //  output,    width = 5,          .channel
		.src_startofpacket  (router_002_src_startofpacket),                    //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_002_src_endofpacket)                       //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_3lwbjsq router_003 (
		.sink_ready         (subsys_hps_lwhps2fpga_agent_write_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_hps_lwhps2fpga_agent_write_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (subsys_hps_lwhps2fpga_agent_write_cp_data),          //   input,  width = 158,          .data
		.sink_startofpacket (subsys_hps_lwhps2fpga_agent_write_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_lwhps2fpga_agent_write_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                                //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset),     //   input,    width = 1, clk_reset.reset
		.src_ready          (router_003_src_ready),                               //   input,    width = 1,       src.ready
		.src_valid          (router_003_src_valid),                               //  output,    width = 1,          .valid
		.src_data           (router_003_src_data),                                //  output,  width = 158,          .data
		.src_channel        (router_003_src_channel),                             //  output,    width = 5,          .channel
		.src_startofpacket  (router_003_src_startofpacket),                       //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_003_src_endofpacket)                          //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_3lwbjsq router_004 (
		.sink_ready         (subsys_hps_lwhps2fpga_agent_read_cp_ready),         //  output,    width = 1,      sink.ready
		.sink_valid         (subsys_hps_lwhps2fpga_agent_read_cp_valid),         //   input,    width = 1,          .valid
		.sink_data          (subsys_hps_lwhps2fpga_agent_read_cp_data),          //   input,  width = 158,          .data
		.sink_startofpacket (subsys_hps_lwhps2fpga_agent_read_cp_startofpacket), //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (subsys_hps_lwhps2fpga_agent_read_cp_endofpacket),   //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                               //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset),    //   input,    width = 1, clk_reset.reset
		.src_ready          (router_004_src_ready),                              //   input,    width = 1,       src.ready
		.src_valid          (router_004_src_valid),                              //  output,    width = 1,          .valid
		.src_data           (router_004_src_data),                               //  output,  width = 158,          .data
		.src_channel        (router_004_src_channel),                            //  output,    width = 5,          .channel
		.src_startofpacket  (router_004_src_startofpacket),                      //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_004_src_endofpacket)                         //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_vbhnnoa router_005 (
		.sink_ready         (agent_pipeline_002_source0_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_002_source0_valid),               //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_002_source0_data),                //   input,  width = 266,          .data
		.sink_startofpacket (agent_pipeline_002_source0_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_002_source0_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_005_src_ready),                           //   input,    width = 1,       src.ready
		.src_valid          (router_005_src_valid),                           //  output,    width = 1,          .valid
		.src_data           (router_005_src_data),                            //  output,  width = 266,          .data
		.src_channel        (router_005_src_channel),                         //  output,    width = 5,          .channel
		.src_startofpacket  (router_005_src_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_005_src_endofpacket)                      //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_3bzdlwi router_006 (
		.sink_ready         (agent_pipeline_003_source0_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_003_source0_valid),               //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_003_source0_data),                //   input,  width = 266,          .data
		.sink_startofpacket (agent_pipeline_003_source0_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_003_source0_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_006_src_ready),                           //   input,    width = 1,       src.ready
		.src_valid          (router_006_src_valid),                           //  output,    width = 1,          .valid
		.src_data           (router_006_src_data),                            //  output,  width = 266,          .data
		.src_channel        (router_006_src_channel),                         //  output,    width = 5,          .channel
		.src_startofpacket  (router_006_src_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_006_src_endofpacket)                      //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_bbfnzza router_007 (
		.sink_ready         (agent_pipeline_005_source0_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_005_source0_valid),               //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_005_source0_data),                //   input,  width = 158,          .data
		.sink_startofpacket (agent_pipeline_005_source0_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_005_source0_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_007_src_ready),                           //   input,    width = 1,       src.ready
		.src_valid          (router_007_src_valid),                           //  output,    width = 1,          .valid
		.src_data           (router_007_src_data),                            //  output,  width = 158,          .data
		.src_channel        (router_007_src_channel),                         //  output,    width = 5,          .channel
		.src_startofpacket  (router_007_src_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_007_src_endofpacket)                      //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_router_1921_uqxmhva router_008 (
		.sink_ready         (agent_pipeline_007_source0_ready),               //  output,    width = 1,      sink.ready
		.sink_valid         (agent_pipeline_007_source0_valid),               //   input,    width = 1,          .valid
		.sink_data          (agent_pipeline_007_source0_data),                //   input,  width = 158,          .data
		.sink_startofpacket (agent_pipeline_007_source0_startofpacket),       //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (agent_pipeline_007_source0_endofpacket),         //   input,    width = 1,          .endofpacket
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready          (router_008_src_ready),                           //   input,    width = 1,       src.ready
		.src_valid          (router_008_src_valid),                           //  output,    width = 1,          .valid
		.src_data           (router_008_src_data),                            //  output,  width = 158,          .data
		.src_channel        (router_008_src_channel),                         //  output,    width = 5,          .channel
		.src_startofpacket  (router_008_src_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src_endofpacket    (router_008_src_endofpacket)                      //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_traffic_limiter_1921_oarheta #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (117),
		.PKT_DEST_ID_L                        (116),
		.PKT_SRC_ID_H                         (115),
		.PKT_SRC_ID_L                         (114),
		.PKT_BYTE_CNT_H                       (92),
		.PKT_BYTE_CNT_L                       (80),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (75),
		.PKT_TRANS_WRITE                      (76),
		.PKT_TRANS_SEQ_H                      (157),
		.PKT_TRANS_SEQ_L                      (151),
		.MAX_OUTSTANDING_RESPONSES            (16),
		.PIPELINED                            (0),
		.ST_DATA_W                            (158),
		.ST_CHANNEL_W                         (5),
		.VALID_WIDTH                          (1),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (1),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) subsys_debug_fpga_m_master_limiter (
		.clk                    (clk_100_out_clk_clk),                                      //   input,    width = 1,       clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),           //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_src_ready),                                         //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_src_valid),                                         //   input,    width = 1,          .valid
		.cmd_sink_data          (router_src_data),                                          //   input,  width = 158,          .data
		.cmd_sink_channel       (router_src_channel),                                       //   input,    width = 5,          .channel
		.cmd_sink_startofpacket (router_src_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_src_endofpacket),                                   //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (subsys_debug_fpga_m_master_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (subsys_debug_fpga_m_master_limiter_cmd_src_data),          //  output,  width = 158,          .data
		.cmd_src_channel        (subsys_debug_fpga_m_master_limiter_cmd_src_channel),       //  output,    width = 5,          .channel
		.cmd_src_startofpacket  (subsys_debug_fpga_m_master_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (subsys_debug_fpga_m_master_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (subsys_debug_fpga_m_master_limiter_cmd_src_valid),         //  output,    width = 1,          .valid
		.rsp_sink_ready         (limiter_pipeline_001_source0_ready),                       //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_001_source0_valid),                       //   input,    width = 1,          .valid
		.rsp_sink_channel       (limiter_pipeline_001_source0_channel),                     //   input,    width = 5,          .channel
		.rsp_sink_data          (limiter_pipeline_001_source0_data),                        //   input,  width = 158,          .data
		.rsp_sink_startofpacket (limiter_pipeline_001_source0_startofpacket),               //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_001_source0_endofpacket),                 //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (subsys_debug_fpga_m_master_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (subsys_debug_fpga_m_master_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (subsys_debug_fpga_m_master_limiter_rsp_src_data),          //  output,  width = 158,          .data
		.rsp_src_channel        (subsys_debug_fpga_m_master_limiter_rsp_src_channel),       //  output,    width = 5,          .channel
		.rsp_src_startofpacket  (subsys_debug_fpga_m_master_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (subsys_debug_fpga_m_master_limiter_rsp_src_endofpacket)    //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_traffic_limiter_1921_oarheta #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (117),
		.PKT_DEST_ID_L                        (116),
		.PKT_SRC_ID_H                         (115),
		.PKT_SRC_ID_L                         (114),
		.PKT_BYTE_CNT_H                       (92),
		.PKT_BYTE_CNT_L                       (80),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (75),
		.PKT_TRANS_WRITE                      (76),
		.PKT_TRANS_SEQ_H                      (157),
		.PKT_TRANS_SEQ_L                      (151),
		.MAX_OUTSTANDING_RESPONSES            (16),
		.PIPELINED                            (0),
		.ST_DATA_W                            (158),
		.ST_CHANNEL_W                         (5),
		.VALID_WIDTH                          (1),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) subsys_hps_lwhps2fpga_wr_limiter (
		.clk                    (clk_100_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_003_src_ready),                                   //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_003_src_valid),                                   //   input,    width = 1,          .valid
		.cmd_sink_data          (router_003_src_data),                                    //   input,  width = 158,          .data
		.cmd_sink_channel       (router_003_src_channel),                                 //   input,    width = 5,          .channel
		.cmd_sink_startofpacket (router_003_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_003_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_data),          //  output,  width = 158,          .data
		.cmd_src_channel        (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_channel),       //  output,    width = 5,          .channel
		.cmd_src_startofpacket  (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_valid),         //  output,    width = 1,          .valid
		.rsp_sink_ready         (limiter_pipeline_003_source0_ready),                     //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_003_source0_valid),                     //   input,    width = 1,          .valid
		.rsp_sink_channel       (limiter_pipeline_003_source0_channel),                   //   input,    width = 5,          .channel
		.rsp_sink_data          (limiter_pipeline_003_source0_data),                      //   input,  width = 158,          .data
		.rsp_sink_startofpacket (limiter_pipeline_003_source0_startofpacket),             //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_003_source0_endofpacket),               //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_data),          //  output,  width = 158,          .data
		.rsp_src_channel        (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_channel),       //  output,    width = 5,          .channel
		.rsp_src_startofpacket  (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (subsys_hps_lwhps2fpga_wr_limiter_rsp_src_endofpacket)    //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_traffic_limiter_1921_oarheta #(
		.SYNC_RESET                           (1),
		.PKT_DEST_ID_H                        (117),
		.PKT_DEST_ID_L                        (116),
		.PKT_SRC_ID_H                         (115),
		.PKT_SRC_ID_L                         (114),
		.PKT_BYTE_CNT_H                       (92),
		.PKT_BYTE_CNT_L                       (80),
		.PKT_BYTEEN_H                         (35),
		.PKT_BYTEEN_L                         (32),
		.PKT_TRANS_POSTED                     (75),
		.PKT_TRANS_WRITE                      (76),
		.PKT_TRANS_SEQ_H                      (157),
		.PKT_TRANS_SEQ_L                      (151),
		.MAX_OUTSTANDING_RESPONSES            (16),
		.PIPELINED                            (0),
		.ST_DATA_W                            (158),
		.ST_CHANNEL_W                         (5),
		.VALID_WIDTH                          (1),
		.ENFORCE_ORDER                        (1),
		.PREVENT_HAZARDS                      (0),
		.SUPPORTS_POSTED_WRITES               (1),
		.SUPPORTS_NONPOSTED_WRITES            (0),
		.REORDER                              (0),
		.ENABLE_CONCURRENT_SUBORDINATE_ACCESS (0),
		.NO_REPEATED_IDS_BETWEEN_SUBORDINATES (0),
		.ENABLE_OOO                           (0)
	) subsys_hps_lwhps2fpga_rd_limiter (
		.clk                    (clk_100_out_clk_clk),                                    //   input,    width = 1,       clk.clk
		.reset                  (subsys_debug_reset_reset_bridge_in_reset_reset),         //   input,    width = 1, clk_reset.reset
		.cmd_sink_ready         (router_004_src_ready),                                   //  output,    width = 1,  cmd_sink.ready
		.cmd_sink_valid         (router_004_src_valid),                                   //   input,    width = 1,          .valid
		.cmd_sink_data          (router_004_src_data),                                    //   input,  width = 158,          .data
		.cmd_sink_channel       (router_004_src_channel),                                 //   input,    width = 5,          .channel
		.cmd_sink_startofpacket (router_004_src_startofpacket),                           //   input,    width = 1,          .startofpacket
		.cmd_sink_endofpacket   (router_004_src_endofpacket),                             //   input,    width = 1,          .endofpacket
		.cmd_src_ready          (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_ready),         //   input,    width = 1,   cmd_src.ready
		.cmd_src_data           (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_data),          //  output,  width = 158,          .data
		.cmd_src_channel        (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_channel),       //  output,    width = 5,          .channel
		.cmd_src_startofpacket  (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_startofpacket), //  output,    width = 1,          .startofpacket
		.cmd_src_endofpacket    (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_endofpacket),   //  output,    width = 1,          .endofpacket
		.cmd_src_valid          (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_valid),         //  output,    width = 1,          .valid
		.rsp_sink_ready         (limiter_pipeline_005_source0_ready),                     //  output,    width = 1,  rsp_sink.ready
		.rsp_sink_valid         (limiter_pipeline_005_source0_valid),                     //   input,    width = 1,          .valid
		.rsp_sink_channel       (limiter_pipeline_005_source0_channel),                   //   input,    width = 5,          .channel
		.rsp_sink_data          (limiter_pipeline_005_source0_data),                      //   input,  width = 158,          .data
		.rsp_sink_startofpacket (limiter_pipeline_005_source0_startofpacket),             //   input,    width = 1,          .startofpacket
		.rsp_sink_endofpacket   (limiter_pipeline_005_source0_endofpacket),               //   input,    width = 1,          .endofpacket
		.rsp_src_ready          (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_ready),         //   input,    width = 1,   rsp_src.ready
		.rsp_src_valid          (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_valid),         //  output,    width = 1,          .valid
		.rsp_src_data           (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_data),          //  output,  width = 158,          .data
		.rsp_src_channel        (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_channel),       //  output,    width = 5,          .channel
		.rsp_src_startofpacket  (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_startofpacket), //  output,    width = 1,          .startofpacket
		.rsp_src_endofpacket    (subsys_hps_lwhps2fpga_rd_limiter_rsp_src_endofpacket)    //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_burst_adapter_1932_4h72upy #(
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (109),
		.PKT_BYTE_CNT_H            (92),
		.PKT_BYTE_CNT_L            (80),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (104),
		.PKT_BURST_SIZE_L          (102),
		.PKT_BURST_TYPE_H          (106),
		.PKT_BURST_TYPE_L          (105),
		.PKT_BURSTWRAP_H           (101),
		.PKT_BURSTWRAP_L           (93),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (158),
		.ST_CHANNEL_W              (5),
		.OUT_BYTE_CNT_H            (82),
		.OUT_BURSTWRAP_H           (101),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("new"),
		.SYNC_RESET                (1)
	) subsys_hps_usb31_phy_reconfig_slave_burst_adapter (
		.clk                   (clk_100_out_clk_clk),                                                     //   input,    width = 1,       cr0.clk
		.reset                 (subsys_debug_reset_reset_bridge_in_reset_reset),                          //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_002_src_valid),                                                   //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_002_src_data),                                                    //   input,  width = 158,          .data
		.sink0_channel         (cmd_mux_002_src_channel),                                                 //   input,    width = 5,          .channel
		.sink0_startofpacket   (cmd_mux_002_src_startofpacket),                                           //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_002_src_endofpacket),                                             //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_002_src_ready),                                                   //  output,    width = 1,          .ready
		.source0_valid         (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_valid),         //  output,    width = 1,   source0.valid
		.source0_data          (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_data),          //  output,  width = 158,          .data
		.source0_channel       (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_channel),       //  output,    width = 5,          .channel
		.source0_startofpacket (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.source0_ready         (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_ready)          //   input,    width = 1,          .ready
	);

	qsys_top_altera_merlin_burst_adapter_1932_4h72upy #(
		.PKT_ADDR_H                (73),
		.PKT_ADDR_L                (36),
		.PKT_BEGIN_BURST           (109),
		.PKT_BYTE_CNT_H            (92),
		.PKT_BYTE_CNT_L            (80),
		.PKT_BYTEEN_H              (35),
		.PKT_BYTEEN_L              (32),
		.PKT_BURST_SIZE_H          (104),
		.PKT_BURST_SIZE_L          (102),
		.PKT_BURST_TYPE_H          (106),
		.PKT_BURST_TYPE_L          (105),
		.PKT_BURSTWRAP_H           (101),
		.PKT_BURSTWRAP_L           (93),
		.PKT_SAI_H                 (89),
		.PKT_SAI_L                 (89),
		.ROLE_BASED_USER           (0),
		.PKT_TRANS_COMPRESSED_READ (74),
		.PKT_TRANS_WRITE           (76),
		.PKT_TRANS_READ            (77),
		.OUT_NARROW_SIZE           (0),
		.IN_NARROW_SIZE            (1),
		.OUT_FIXED                 (0),
		.OUT_COMPLETE_WRAP         (0),
		.PKT_EOP_OOO               (89),
		.PKT_SOP_OOO               (90),
		.ENABLE_OOO                (0),
		.ST_DATA_W                 (158),
		.ST_CHANNEL_W              (5),
		.OUT_BYTE_CNT_H            (82),
		.OUT_BURSTWRAP_H           (101),
		.COMPRESSED_READ_SUPPORT   (1),
		.BYTEENABLE_SYNTHESIS      (1),
		.PIPE_INPUTS               (0),
		.NO_WRAP_SUPPORT           (0),
		.INCOMPLETE_WRAP_SUPPORT   (0),
		.BURSTWRAP_CONST_MASK      (0),
		.BURSTWRAP_CONST_VALUE     (0),
		.ADAPTER_VERSION           ("new"),
		.SYNC_RESET                (1)
	) subsys_periph_pb_cpu_0_s0_burst_adapter (
		.clk                   (clk_100_out_clk_clk),                                           //   input,    width = 1,       cr0.clk
		.reset                 (subsys_debug_reset_reset_bridge_in_reset_reset),                //   input,    width = 1, cr0_reset.reset
		.sink0_valid           (cmd_mux_003_src_valid),                                         //   input,    width = 1,     sink0.valid
		.sink0_data            (cmd_mux_003_src_data),                                          //   input,  width = 158,          .data
		.sink0_channel         (cmd_mux_003_src_channel),                                       //   input,    width = 5,          .channel
		.sink0_startofpacket   (cmd_mux_003_src_startofpacket),                                 //   input,    width = 1,          .startofpacket
		.sink0_endofpacket     (cmd_mux_003_src_endofpacket),                                   //   input,    width = 1,          .endofpacket
		.sink0_ready           (cmd_mux_003_src_ready),                                         //  output,    width = 1,          .ready
		.source0_valid         (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_valid),         //  output,    width = 1,   source0.valid
		.source0_data          (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_data),          //  output,  width = 158,          .data
		.source0_channel       (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_channel),       //  output,    width = 5,          .channel
		.source0_startofpacket (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.source0_endofpacket   (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.source0_ready         (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_ready)          //   input,    width = 1,          .ready
	);

	qsys_top_altera_merlin_demultiplexer_1921_tsd6raa cmd_demux (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (limiter_pipeline_source0_ready),                 //  output,    width = 1,      sink.ready
		.sink_channel       (limiter_pipeline_source0_channel),               //   input,    width = 5,          .channel
		.sink_data          (limiter_pipeline_source0_data),                  //   input,  width = 158,          .data
		.sink_startofpacket (limiter_pipeline_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (limiter_pipeline_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink_valid         (limiter_pipeline_source0_valid),                 //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_src0_ready),                           //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_src0_valid),                           //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_src0_data),                            //  output,  width = 158,          .data
		.src0_channel       (cmd_demux_src0_channel),                         //  output,    width = 5,          .channel
		.src0_startofpacket (cmd_demux_src0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_src0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_src1_ready),                           //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_src1_valid),                           //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_src1_data),                            //  output,  width = 158,          .data
		.src1_channel       (cmd_demux_src1_channel),                         //  output,    width = 5,          .channel
		.src1_startofpacket (cmd_demux_src1_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_src1_endofpacket),                     //  output,    width = 1,          .endofpacket
		.src2_ready         (cmd_demux_src2_ready),                           //   input,    width = 1,      src2.ready
		.src2_valid         (cmd_demux_src2_valid),                           //  output,    width = 1,          .valid
		.src2_data          (cmd_demux_src2_data),                            //  output,  width = 158,          .data
		.src2_channel       (cmd_demux_src2_channel),                         //  output,    width = 5,          .channel
		.src2_startofpacket (cmd_demux_src2_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (cmd_demux_src2_endofpacket)                      //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_p2eh26a cmd_demux_001 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_001_src_ready),                           //  output,    width = 1,      sink.ready
		.sink_channel       (router_001_src_channel),                         //   input,    width = 5,          .channel
		.sink_data          (router_001_src_data),                            //   input,  width = 266,          .data
		.sink_startofpacket (router_001_src_startofpacket),                   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_001_src_endofpacket),                     //   input,    width = 1,          .endofpacket
		.sink_valid         (router_001_src_valid),                           //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_001_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_001_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_001_src0_data),                        //  output,  width = 266,          .data
		.src0_channel       (cmd_demux_001_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (cmd_demux_001_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_001_src0_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_p2eh26a cmd_demux_002 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_002_src_ready),                           //  output,    width = 1,      sink.ready
		.sink_channel       (router_002_src_channel),                         //   input,    width = 5,          .channel
		.sink_data          (router_002_src_data),                            //   input,  width = 266,          .data
		.sink_startofpacket (router_002_src_startofpacket),                   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_002_src_endofpacket),                     //   input,    width = 1,          .endofpacket
		.sink_valid         (router_002_src_valid),                           //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_002_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_002_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_002_src0_data),                        //  output,  width = 266,          .data
		.src0_channel       (cmd_demux_002_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (cmd_demux_002_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_002_src0_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_rkazjqq cmd_demux_003 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (limiter_pipeline_002_source0_ready),             //  output,    width = 1,      sink.ready
		.sink_channel       (limiter_pipeline_002_source0_channel),           //   input,    width = 5,          .channel
		.sink_data          (limiter_pipeline_002_source0_data),              //   input,  width = 158,          .data
		.sink_startofpacket (limiter_pipeline_002_source0_startofpacket),     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (limiter_pipeline_002_source0_endofpacket),       //   input,    width = 1,          .endofpacket
		.sink_valid         (limiter_pipeline_002_source0_valid),             //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_003_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_003_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_003_src0_data),                        //  output,  width = 158,          .data
		.src0_channel       (cmd_demux_003_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (cmd_demux_003_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_003_src0_endofpacket),                 //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_003_src1_ready),                       //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_003_src1_valid),                       //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_003_src1_data),                        //  output,  width = 158,          .data
		.src1_channel       (cmd_demux_003_src1_channel),                     //  output,    width = 5,          .channel
		.src1_startofpacket (cmd_demux_003_src1_startofpacket),               //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_003_src1_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_rkazjqq cmd_demux_004 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (limiter_pipeline_004_source0_ready),             //  output,    width = 1,      sink.ready
		.sink_channel       (limiter_pipeline_004_source0_channel),           //   input,    width = 5,          .channel
		.sink_data          (limiter_pipeline_004_source0_data),              //   input,  width = 158,          .data
		.sink_startofpacket (limiter_pipeline_004_source0_startofpacket),     //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (limiter_pipeline_004_source0_endofpacket),       //   input,    width = 1,          .endofpacket
		.sink_valid         (limiter_pipeline_004_source0_valid),             //   input,    width = 1,          .valid
		.src0_ready         (cmd_demux_004_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (cmd_demux_004_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (cmd_demux_004_src0_data),                        //  output,  width = 158,          .data
		.src0_channel       (cmd_demux_004_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (cmd_demux_004_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (cmd_demux_004_src0_endofpacket),                 //  output,    width = 1,          .endofpacket
		.src1_ready         (cmd_demux_004_src1_ready),                       //   input,    width = 1,      src1.ready
		.src1_valid         (cmd_demux_004_src1_valid),                       //  output,    width = 1,          .valid
		.src1_data          (cmd_demux_004_src1_data),                        //  output,  width = 158,          .data
		.src1_channel       (cmd_demux_004_src1_channel),                     //  output,    width = 5,          .channel
		.src1_startofpacket (cmd_demux_004_src1_startofpacket),               //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (cmd_demux_004_src1_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_vcofnzi cmd_mux (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_src_ready),                              //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_src_valid),                              //  output,    width = 1,          .valid
		.src_data            (cmd_mux_src_data),                               //  output,  width = 266,          .data
		.src_channel         (cmd_mux_src_channel),                            //  output,    width = 5,          .channel
		.src_startofpacket   (cmd_mux_src_startofpacket),                      //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_src_endofpacket),                        //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_source0_ready),                     //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_source0_valid),                     //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_source0_channel),                   //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_source0_data),                      //   input,  width = 266,          .data
		.sink0_startofpacket (mux_pipeline_source0_startofpacket),             //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_source0_endofpacket),               //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_001_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_001_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_001_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_001_source0_data),                  //   input,  width = 266,          .data
		.sink1_startofpacket (mux_pipeline_001_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_001_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_vcofnzi cmd_mux_001 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_001_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_001_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (cmd_mux_001_src_data),                           //  output,  width = 266,          .data
		.src_channel         (cmd_mux_001_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (cmd_mux_001_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_001_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_002_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_002_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_002_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_002_source0_data),                  //   input,  width = 266,          .data
		.sink0_startofpacket (mux_pipeline_002_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_002_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_003_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_003_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_003_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_003_source0_data),                  //   input,  width = 266,          .data
		.sink1_startofpacket (mux_pipeline_003_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_003_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_vf23pey cmd_mux_002 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_002_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_002_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (cmd_mux_002_src_data),                           //  output,  width = 158,          .data
		.src_channel         (cmd_mux_002_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (cmd_mux_002_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_002_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_004_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_004_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_004_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_004_source0_data),                  //   input,  width = 158,          .data
		.sink0_startofpacket (mux_pipeline_004_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_004_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_005_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_005_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_005_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_005_source0_data),                  //   input,  width = 158,          .data
		.sink1_startofpacket (mux_pipeline_005_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_005_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink2_ready         (mux_pipeline_006_source0_ready),                 //  output,    width = 1,     sink2.ready
		.sink2_valid         (mux_pipeline_006_source0_valid),                 //   input,    width = 1,          .valid
		.sink2_channel       (mux_pipeline_006_source0_channel),               //   input,    width = 5,          .channel
		.sink2_data          (mux_pipeline_006_source0_data),                  //   input,  width = 158,          .data
		.sink2_startofpacket (mux_pipeline_006_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (mux_pipeline_006_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_qbxsfpy cmd_mux_003 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (cmd_mux_003_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (cmd_mux_003_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (cmd_mux_003_src_data),                           //  output,  width = 158,          .data
		.src_channel         (cmd_mux_003_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (cmd_mux_003_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (cmd_mux_003_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_007_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_007_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_007_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_007_source0_data),                  //   input,  width = 158,          .data
		.sink0_startofpacket (mux_pipeline_007_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_007_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_008_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_008_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_008_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_008_source0_data),                  //   input,  width = 158,          .data
		.sink1_startofpacket (mux_pipeline_008_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_008_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_se7crli rsp_demux (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_005_src_ready),                           //  output,    width = 1,      sink.ready
		.sink_channel       (router_005_src_channel),                         //   input,    width = 5,          .channel
		.sink_data          (router_005_src_data),                            //   input,  width = 266,          .data
		.sink_startofpacket (router_005_src_startofpacket),                   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_005_src_endofpacket),                     //   input,    width = 1,          .endofpacket
		.sink_valid         (router_005_src_valid),                           //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_src0_ready),                           //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_src0_valid),                           //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_src0_data),                            //  output,  width = 266,          .data
		.src0_channel       (rsp_demux_src0_channel),                         //  output,    width = 5,          .channel
		.src0_startofpacket (rsp_demux_src0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_src0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_src1_ready),                           //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_src1_valid),                           //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_src1_data),                            //  output,  width = 266,          .data
		.src1_channel       (rsp_demux_src1_channel),                         //  output,    width = 5,          .channel
		.src1_startofpacket (rsp_demux_src1_startofpacket),                   //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_src1_endofpacket)                      //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_se7crli rsp_demux_001 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_006_src_ready),                           //  output,    width = 1,      sink.ready
		.sink_channel       (router_006_src_channel),                         //   input,    width = 5,          .channel
		.sink_data          (router_006_src_data),                            //   input,  width = 266,          .data
		.sink_startofpacket (router_006_src_startofpacket),                   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_006_src_endofpacket),                     //   input,    width = 1,          .endofpacket
		.sink_valid         (router_006_src_valid),                           //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_001_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_001_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_001_src0_data),                        //  output,  width = 266,          .data
		.src0_channel       (rsp_demux_001_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (rsp_demux_001_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_001_src0_endofpacket),                 //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_001_src1_ready),                       //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_001_src1_valid),                       //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_001_src1_data),                        //  output,  width = 266,          .data
		.src1_channel       (rsp_demux_001_src1_channel),                     //  output,    width = 5,          .channel
		.src1_startofpacket (rsp_demux_001_src1_startofpacket),               //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_001_src1_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_tsd6raa rsp_demux_002 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_007_src_ready),                           //  output,    width = 1,      sink.ready
		.sink_channel       (router_007_src_channel),                         //   input,    width = 5,          .channel
		.sink_data          (router_007_src_data),                            //   input,  width = 158,          .data
		.sink_startofpacket (router_007_src_startofpacket),                   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_007_src_endofpacket),                     //   input,    width = 1,          .endofpacket
		.sink_valid         (router_007_src_valid),                           //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_002_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_002_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_002_src0_data),                        //  output,  width = 158,          .data
		.src0_channel       (rsp_demux_002_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (rsp_demux_002_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_002_src0_endofpacket),                 //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_002_src1_ready),                       //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_002_src1_valid),                       //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_002_src1_data),                        //  output,  width = 158,          .data
		.src1_channel       (rsp_demux_002_src1_channel),                     //  output,    width = 5,          .channel
		.src1_startofpacket (rsp_demux_002_src1_startofpacket),               //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_002_src1_endofpacket),                 //  output,    width = 1,          .endofpacket
		.src2_ready         (rsp_demux_002_src2_ready),                       //   input,    width = 1,      src2.ready
		.src2_valid         (rsp_demux_002_src2_valid),                       //  output,    width = 1,          .valid
		.src2_data          (rsp_demux_002_src2_data),                        //  output,  width = 158,          .data
		.src2_channel       (rsp_demux_002_src2_channel),                     //  output,    width = 5,          .channel
		.src2_startofpacket (rsp_demux_002_src2_startofpacket),               //  output,    width = 1,          .startofpacket
		.src2_endofpacket   (rsp_demux_002_src2_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_demultiplexer_1921_rkazjqq rsp_demux_003 (
		.clk                (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset              (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.sink_ready         (router_008_src_ready),                           //  output,    width = 1,      sink.ready
		.sink_channel       (router_008_src_channel),                         //   input,    width = 5,          .channel
		.sink_data          (router_008_src_data),                            //   input,  width = 158,          .data
		.sink_startofpacket (router_008_src_startofpacket),                   //   input,    width = 1,          .startofpacket
		.sink_endofpacket   (router_008_src_endofpacket),                     //   input,    width = 1,          .endofpacket
		.sink_valid         (router_008_src_valid),                           //   input,    width = 1,          .valid
		.src0_ready         (rsp_demux_003_src0_ready),                       //   input,    width = 1,      src0.ready
		.src0_valid         (rsp_demux_003_src0_valid),                       //  output,    width = 1,          .valid
		.src0_data          (rsp_demux_003_src0_data),                        //  output,  width = 158,          .data
		.src0_channel       (rsp_demux_003_src0_channel),                     //  output,    width = 5,          .channel
		.src0_startofpacket (rsp_demux_003_src0_startofpacket),               //  output,    width = 1,          .startofpacket
		.src0_endofpacket   (rsp_demux_003_src0_endofpacket),                 //  output,    width = 1,          .endofpacket
		.src1_ready         (rsp_demux_003_src1_ready),                       //   input,    width = 1,      src1.ready
		.src1_valid         (rsp_demux_003_src1_valid),                       //  output,    width = 1,          .valid
		.src1_data          (rsp_demux_003_src1_data),                        //  output,  width = 158,          .data
		.src1_channel       (rsp_demux_003_src1_channel),                     //  output,    width = 5,          .channel
		.src1_startofpacket (rsp_demux_003_src1_startofpacket),               //  output,    width = 1,          .startofpacket
		.src1_endofpacket   (rsp_demux_003_src1_endofpacket)                  //  output,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_qfexr7i rsp_mux (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_src_ready),                              //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_src_valid),                              //  output,    width = 1,          .valid
		.src_data            (rsp_mux_src_data),                               //  output,  width = 158,          .data
		.src_channel         (rsp_mux_src_channel),                            //  output,    width = 5,          .channel
		.src_startofpacket   (rsp_mux_src_startofpacket),                      //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_src_endofpacket),                        //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_009_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_009_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_009_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_009_source0_data),                  //   input,  width = 158,          .data
		.sink0_startofpacket (mux_pipeline_009_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_009_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_010_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_010_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_010_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_010_source0_data),                  //   input,  width = 158,          .data
		.sink1_startofpacket (mux_pipeline_010_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_010_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink2_ready         (mux_pipeline_011_source0_ready),                 //  output,    width = 1,     sink2.ready
		.sink2_valid         (mux_pipeline_011_source0_valid),                 //   input,    width = 1,          .valid
		.sink2_channel       (mux_pipeline_011_source0_channel),               //   input,    width = 5,          .channel
		.sink2_data          (mux_pipeline_011_source0_data),                  //   input,  width = 158,          .data
		.sink2_startofpacket (mux_pipeline_011_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink2_endofpacket   (mux_pipeline_011_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_wqdabaa rsp_mux_001 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_001_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_001_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (rsp_mux_001_src_data),                           //  output,  width = 266,          .data
		.src_channel         (rsp_mux_001_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (rsp_mux_001_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_001_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_012_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_012_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_012_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_012_source0_data),                  //   input,  width = 266,          .data
		.sink0_startofpacket (mux_pipeline_012_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_012_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_wqdabaa rsp_mux_002 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_002_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_002_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (rsp_mux_002_src_data),                           //  output,  width = 266,          .data
		.src_channel         (rsp_mux_002_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (rsp_mux_002_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_002_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_013_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_013_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_013_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_013_source0_data),                  //   input,  width = 266,          .data
		.sink0_startofpacket (mux_pipeline_013_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_013_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_f2szwea rsp_mux_003 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_003_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_003_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (rsp_mux_003_src_data),                           //  output,  width = 158,          .data
		.src_channel         (rsp_mux_003_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (rsp_mux_003_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_003_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_014_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_014_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_014_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_014_source0_data),                  //   input,  width = 158,          .data
		.sink0_startofpacket (mux_pipeline_014_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_014_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_015_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_015_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_015_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_015_source0_data),                  //   input,  width = 158,          .data
		.sink1_startofpacket (mux_pipeline_015_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_015_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_multiplexer_1922_f2szwea rsp_mux_004 (
		.clk                 (clk_100_out_clk_clk),                            //   input,    width = 1,       clk.clk
		.reset               (subsys_debug_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset
		.src_ready           (rsp_mux_004_src_ready),                          //   input,    width = 1,       src.ready
		.src_valid           (rsp_mux_004_src_valid),                          //  output,    width = 1,          .valid
		.src_data            (rsp_mux_004_src_data),                           //  output,  width = 158,          .data
		.src_channel         (rsp_mux_004_src_channel),                        //  output,    width = 5,          .channel
		.src_startofpacket   (rsp_mux_004_src_startofpacket),                  //  output,    width = 1,          .startofpacket
		.src_endofpacket     (rsp_mux_004_src_endofpacket),                    //  output,    width = 1,          .endofpacket
		.sink0_ready         (mux_pipeline_016_source0_ready),                 //  output,    width = 1,     sink0.ready
		.sink0_valid         (mux_pipeline_016_source0_valid),                 //   input,    width = 1,          .valid
		.sink0_channel       (mux_pipeline_016_source0_channel),               //   input,    width = 5,          .channel
		.sink0_data          (mux_pipeline_016_source0_data),                  //   input,  width = 158,          .data
		.sink0_startofpacket (mux_pipeline_016_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink0_endofpacket   (mux_pipeline_016_source0_endofpacket),           //   input,    width = 1,          .endofpacket
		.sink1_ready         (mux_pipeline_017_source0_ready),                 //  output,    width = 1,     sink1.ready
		.sink1_valid         (mux_pipeline_017_source0_valid),                 //   input,    width = 1,          .valid
		.sink1_channel       (mux_pipeline_017_source0_channel),               //   input,    width = 5,          .channel
		.sink1_data          (mux_pipeline_017_source0_data),                  //   input,  width = 158,          .data
		.sink1_startofpacket (mux_pipeline_017_source0_startofpacket),         //   input,    width = 1,          .startofpacket
		.sink1_endofpacket   (mux_pipeline_017_source0_endofpacket)            //   input,    width = 1,          .endofpacket
	);

	qsys_top_altera_merlin_width_adapter_1940_cvucksq #(
		.IN_PKT_ADDR_H                 (73),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (92),
		.IN_PKT_BYTE_CNT_L             (80),
		.IN_PKT_TRANS_COMPRESSED_READ  (74),
		.IN_PKT_TRANS_WRITE            (76),
		.IN_PKT_BURSTWRAP_H            (101),
		.IN_PKT_BURSTWRAP_L            (93),
		.IN_PKT_BURST_SIZE_H           (104),
		.IN_PKT_BURST_SIZE_L           (102),
		.IN_PKT_RESPONSE_STATUS_H      (130),
		.IN_PKT_RESPONSE_STATUS_L      (129),
		.IN_PKT_TRANS_EXCLUSIVE        (79),
		.IN_PKT_BURST_TYPE_H           (106),
		.IN_PKT_BURST_TYPE_L           (105),
		.IN_PKT_ORI_BURST_SIZE_L       (131),
		.IN_PKT_ORI_BURST_SIZE_H       (133),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (158),
		.OUT_PKT_ADDR_H                (181),
		.OUT_PKT_ADDR_L                (144),
		.OUT_PKT_DATA_H                (127),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (143),
		.OUT_PKT_BYTEEN_L              (128),
		.OUT_PKT_BYTE_CNT_H            (200),
		.OUT_PKT_BYTE_CNT_L            (188),
		.OUT_PKT_TRANS_COMPRESSED_READ (182),
		.OUT_PKT_BURST_SIZE_H          (212),
		.OUT_PKT_BURST_SIZE_L          (210),
		.OUT_PKT_RESPONSE_STATUS_H     (238),
		.OUT_PKT_RESPONSE_STATUS_L     (237),
		.OUT_PKT_TRANS_EXCLUSIVE       (187),
		.OUT_PKT_BURST_TYPE_H          (214),
		.OUT_PKT_BURST_TYPE_L          (213),
		.OUT_PKT_ORI_BURST_SIZE_L      (239),
		.OUT_PKT_ORI_BURST_SIZE_H      (241),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (257),
		.OUT_PKT_SOP_OOO               (258),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (266),
		.ST_CHANNEL_W                  (5),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                             //   input,    width = 1,       clk.clk
		.reset                (subsys_debug_reset_reset_bridge_in_reset_reset),                                  //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_demux_src0_valid),                                                            //   input,    width = 1,      sink.valid
		.in_channel           (cmd_demux_src0_channel),                                                          //   input,    width = 5,          .channel
		.in_startofpacket     (cmd_demux_src0_startofpacket),                                                    //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_demux_src0_endofpacket),                                                      //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_demux_src0_ready),                                                            //  output,    width = 1,          .ready
		.in_data              (cmd_demux_src0_data),                                                             //   input,  width = 158,          .data
		.out_endofpacket      (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_data),          //  output,  width = 266,          .data
		.out_channel          (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_channel),       //  output,    width = 5,          .channel
		.out_valid            (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                           // (terminated),                         
	);

	qsys_top_altera_merlin_width_adapter_1940_cvucksq #(
		.IN_PKT_ADDR_H                 (73),
		.IN_PKT_ADDR_L                 (36),
		.IN_PKT_DATA_H                 (31),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (35),
		.IN_PKT_BYTEEN_L               (32),
		.IN_PKT_BYTE_CNT_H             (92),
		.IN_PKT_BYTE_CNT_L             (80),
		.IN_PKT_TRANS_COMPRESSED_READ  (74),
		.IN_PKT_TRANS_WRITE            (76),
		.IN_PKT_BURSTWRAP_H            (101),
		.IN_PKT_BURSTWRAP_L            (93),
		.IN_PKT_BURST_SIZE_H           (104),
		.IN_PKT_BURST_SIZE_L           (102),
		.IN_PKT_RESPONSE_STATUS_H      (130),
		.IN_PKT_RESPONSE_STATUS_L      (129),
		.IN_PKT_TRANS_EXCLUSIVE        (79),
		.IN_PKT_BURST_TYPE_H           (106),
		.IN_PKT_BURST_TYPE_L           (105),
		.IN_PKT_ORI_BURST_SIZE_L       (131),
		.IN_PKT_ORI_BURST_SIZE_H       (133),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (158),
		.OUT_PKT_ADDR_H                (181),
		.OUT_PKT_ADDR_L                (144),
		.OUT_PKT_DATA_H                (127),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (143),
		.OUT_PKT_BYTEEN_L              (128),
		.OUT_PKT_BYTE_CNT_H            (200),
		.OUT_PKT_BYTE_CNT_L            (188),
		.OUT_PKT_TRANS_COMPRESSED_READ (182),
		.OUT_PKT_BURST_SIZE_H          (212),
		.OUT_PKT_BURST_SIZE_L          (210),
		.OUT_PKT_RESPONSE_STATUS_H     (238),
		.OUT_PKT_RESPONSE_STATUS_L     (237),
		.OUT_PKT_TRANS_EXCLUSIVE       (187),
		.OUT_PKT_BURST_TYPE_H          (214),
		.OUT_PKT_BURST_TYPE_L          (213),
		.OUT_PKT_ORI_BURST_SIZE_L      (239),
		.OUT_PKT_ORI_BURST_SIZE_H      (241),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (257),
		.OUT_PKT_SOP_OOO               (258),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (266),
		.ST_CHANNEL_W                  (5),
		.OPTIMIZE_FOR_RSP              (0),
		.RESPONSE_PATH                 (0),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (0),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                             //   input,    width = 1,       clk.clk
		.reset                (subsys_debug_reset_reset_bridge_in_reset_reset),                                  //   input,    width = 1, clk_reset.reset
		.in_valid             (cmd_demux_src1_valid),                                                            //   input,    width = 1,      sink.valid
		.in_channel           (cmd_demux_src1_channel),                                                          //   input,    width = 5,          .channel
		.in_startofpacket     (cmd_demux_src1_startofpacket),                                                    //   input,    width = 1,          .startofpacket
		.in_endofpacket       (cmd_demux_src1_endofpacket),                                                      //   input,    width = 1,          .endofpacket
		.in_ready             (cmd_demux_src1_ready),                                                            //  output,    width = 1,          .ready
		.in_data              (cmd_demux_src1_data),                                                             //   input,  width = 158,          .data
		.out_endofpacket      (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_data),          //  output,  width = 266,          .data
		.out_channel          (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_channel),       //  output,    width = 5,          .channel
		.out_valid            (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                           // (terminated),                         
	);

	qsys_top_altera_merlin_width_adapter_1940_v4soloa #(
		.IN_PKT_ADDR_H                 (181),
		.IN_PKT_ADDR_L                 (144),
		.IN_PKT_DATA_H                 (127),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (143),
		.IN_PKT_BYTEEN_L               (128),
		.IN_PKT_BYTE_CNT_H             (200),
		.IN_PKT_BYTE_CNT_L             (188),
		.IN_PKT_TRANS_COMPRESSED_READ  (182),
		.IN_PKT_TRANS_WRITE            (184),
		.IN_PKT_BURSTWRAP_H            (209),
		.IN_PKT_BURSTWRAP_L            (201),
		.IN_PKT_BURST_SIZE_H           (212),
		.IN_PKT_BURST_SIZE_L           (210),
		.IN_PKT_RESPONSE_STATUS_H      (238),
		.IN_PKT_RESPONSE_STATUS_L      (237),
		.IN_PKT_TRANS_EXCLUSIVE        (187),
		.IN_PKT_BURST_TYPE_H           (214),
		.IN_PKT_BURST_TYPE_L           (213),
		.IN_PKT_ORI_BURST_SIZE_L       (239),
		.IN_PKT_ORI_BURST_SIZE_H       (241),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (266),
		.OUT_PKT_ADDR_H                (73),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (92),
		.OUT_PKT_BYTE_CNT_L            (80),
		.OUT_PKT_TRANS_COMPRESSED_READ (74),
		.OUT_PKT_BURST_SIZE_H          (104),
		.OUT_PKT_BURST_SIZE_L          (102),
		.OUT_PKT_RESPONSE_STATUS_H     (130),
		.OUT_PKT_RESPONSE_STATUS_L     (129),
		.OUT_PKT_TRANS_EXCLUSIVE       (79),
		.OUT_PKT_BURST_TYPE_H          (106),
		.OUT_PKT_BURST_TYPE_L          (105),
		.OUT_PKT_ORI_BURST_SIZE_L      (131),
		.OUT_PKT_ORI_BURST_SIZE_H      (133),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (149),
		.OUT_PKT_SOP_OOO               (150),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (158),
		.ST_CHANNEL_W                  (5),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                             //   input,    width = 1,       clk.clk
		.reset                (subsys_debug_reset_reset_bridge_in_reset_reset),                                  //   input,    width = 1, clk_reset.reset
		.in_valid             (rsp_demux_src0_valid),                                                            //   input,    width = 1,      sink.valid
		.in_channel           (rsp_demux_src0_channel),                                                          //   input,    width = 5,          .channel
		.in_startofpacket     (rsp_demux_src0_startofpacket),                                                    //   input,    width = 1,          .startofpacket
		.in_endofpacket       (rsp_demux_src0_endofpacket),                                                      //   input,    width = 1,          .endofpacket
		.in_ready             (rsp_demux_src0_ready),                                                            //  output,    width = 1,          .ready
		.in_data              (rsp_demux_src0_data),                                                             //   input,  width = 266,          .data
		.out_endofpacket      (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_data),          //  output,  width = 158,          .data
		.out_channel          (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_channel),       //  output,    width = 5,          .channel
		.out_valid            (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                           // (terminated),                         
	);

	qsys_top_altera_merlin_width_adapter_1940_v4soloa #(
		.IN_PKT_ADDR_H                 (181),
		.IN_PKT_ADDR_L                 (144),
		.IN_PKT_DATA_H                 (127),
		.IN_PKT_DATA_L                 (0),
		.IN_PKT_BYTEEN_H               (143),
		.IN_PKT_BYTEEN_L               (128),
		.IN_PKT_BYTE_CNT_H             (200),
		.IN_PKT_BYTE_CNT_L             (188),
		.IN_PKT_TRANS_COMPRESSED_READ  (182),
		.IN_PKT_TRANS_WRITE            (184),
		.IN_PKT_BURSTWRAP_H            (209),
		.IN_PKT_BURSTWRAP_L            (201),
		.IN_PKT_BURST_SIZE_H           (212),
		.IN_PKT_BURST_SIZE_L           (210),
		.IN_PKT_RESPONSE_STATUS_H      (238),
		.IN_PKT_RESPONSE_STATUS_L      (237),
		.IN_PKT_TRANS_EXCLUSIVE        (187),
		.IN_PKT_BURST_TYPE_H           (214),
		.IN_PKT_BURST_TYPE_L           (213),
		.IN_PKT_ORI_BURST_SIZE_L       (239),
		.IN_PKT_ORI_BURST_SIZE_H       (241),
		.IN_PKT_POISON_H               (76),
		.IN_PKT_POISON_L               (76),
		.IN_PKT_DATACHK_H              (80),
		.IN_PKT_DATACHK_L              (77),
		.IN_PKT_ADDRCHK_H              (84),
		.IN_PKT_ADDRCHK_L              (81),
		.IN_PKT_SAI_H                  (88),
		.IN_PKT_SAI_L                  (85),
		.IN_PKT_USER_DATA_H            (89),
		.IN_PKT_USER_DATA_L            (89),
		.IN_ST_DATA_W                  (266),
		.OUT_PKT_ADDR_H                (73),
		.OUT_PKT_ADDR_L                (36),
		.OUT_PKT_DATA_H                (31),
		.OUT_PKT_DATA_L                (0),
		.OUT_PKT_BYTEEN_H              (35),
		.OUT_PKT_BYTEEN_L              (32),
		.OUT_PKT_BYTE_CNT_H            (92),
		.OUT_PKT_BYTE_CNT_L            (80),
		.OUT_PKT_TRANS_COMPRESSED_READ (74),
		.OUT_PKT_BURST_SIZE_H          (104),
		.OUT_PKT_BURST_SIZE_L          (102),
		.OUT_PKT_RESPONSE_STATUS_H     (130),
		.OUT_PKT_RESPONSE_STATUS_L     (129),
		.OUT_PKT_TRANS_EXCLUSIVE       (79),
		.OUT_PKT_BURST_TYPE_H          (106),
		.OUT_PKT_BURST_TYPE_L          (105),
		.OUT_PKT_ORI_BURST_SIZE_L      (131),
		.OUT_PKT_ORI_BURST_SIZE_H      (133),
		.OUT_PKT_POISON_H              (74),
		.OUT_PKT_POISON_L              (74),
		.OUT_PKT_DATACHK_H             (78),
		.OUT_PKT_DATACHK_L             (75),
		.OUT_PKT_ADDRCHK_H             (82),
		.OUT_PKT_ADDRCHK_L             (79),
		.OUT_PKT_SAI_H                 (86),
		.OUT_PKT_SAI_L                 (83),
		.OUT_PKT_EOP_OOO               (149),
		.OUT_PKT_SOP_OOO               (150),
		.OUT_PKT_USER_DATA_H           (89),
		.OUT_PKT_USER_DATA_L           (89),
		.ENABLE_OOO                    (0),
		.OUT_ST_DATA_W                 (158),
		.ST_CHANNEL_W                  (5),
		.OPTIMIZE_FOR_RSP              (1),
		.RESPONSE_PATH                 (1),
		.CONSTANT_BURST_SIZE           (0),
		.PACKING                       (1),
		.ENABLE_ADDRESS_ALIGNMENT      (1),
		.ROLE_BASED_USER               (0),
		.BITSPERBYTE                   (0),
		.SYNC_RESET                    (1)
	) ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter (
		.clk                  (clk_100_out_clk_clk),                                                             //   input,    width = 1,       clk.clk
		.reset                (subsys_debug_reset_reset_bridge_in_reset_reset),                                  //   input,    width = 1, clk_reset.reset
		.in_valid             (rsp_demux_001_src0_valid),                                                        //   input,    width = 1,      sink.valid
		.in_channel           (rsp_demux_001_src0_channel),                                                      //   input,    width = 5,          .channel
		.in_startofpacket     (rsp_demux_001_src0_startofpacket),                                                //   input,    width = 1,          .startofpacket
		.in_endofpacket       (rsp_demux_001_src0_endofpacket),                                                  //   input,    width = 1,          .endofpacket
		.in_ready             (rsp_demux_001_src0_ready),                                                        //  output,    width = 1,          .ready
		.in_data              (rsp_demux_001_src0_data),                                                         //   input,  width = 266,          .data
		.out_endofpacket      (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_endofpacket),   //  output,    width = 1,       src.endofpacket
		.out_data             (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_data),          //  output,  width = 158,          .data
		.out_channel          (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_channel),       //  output,    width = 5,          .channel
		.out_valid            (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_valid),         //  output,    width = 1,          .valid
		.out_ready            (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_ready),         //   input,    width = 1,          .ready
		.out_startofpacket    (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_startofpacket), //  output,    width = 1,          .startofpacket
		.in_command_size_data (3'b000)                                                                           // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline (
		.clk               (clk_100_out_clk_clk),                                      //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                   //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_debug_fpga_m_master_limiter_cmd_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_debug_fpga_m_master_limiter_cmd_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_debug_fpga_m_master_limiter_cmd_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_debug_fpga_m_master_limiter_cmd_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_debug_fpga_m_master_limiter_cmd_src_data),          //   input,  width = 158,          .data
		.in_channel        (subsys_debug_fpga_m_master_limiter_cmd_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (limiter_pipeline_source0_ready),                           //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_source0_valid),                           //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_source0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_source0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_source0_data),                            //  output,  width = 158,          .data
		.out_channel       (limiter_pipeline_source0_channel),                         //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                     // (terminated),                         
		.out_empty         (),                                                         // (terminated),                         
		.out_error         (),                                                         // (terminated),                         
		.in_error          (1'b0)                                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                        //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),     //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_mux_src_ready),                          //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_mux_src_valid),                          //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_mux_src_startofpacket),                  //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_mux_src_endofpacket),                    //   input,    width = 1,          .endofpacket
		.in_data           (rsp_mux_src_data),                           //   input,  width = 158,          .data
		.in_channel        (rsp_mux_src_channel),                        //   input,    width = 5,          .channel
		.out_ready         (limiter_pipeline_001_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_001_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_001_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_001_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_001_source0_data),          //  output,  width = 158,          .data
		.out_channel       (limiter_pipeline_001_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline_002 (
		.clk               (clk_100_out_clk_clk),                                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                 //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_data),          //   input,  width = 158,          .data
		.in_channel        (subsys_hps_lwhps2fpga_wr_limiter_cmd_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (limiter_pipeline_002_source0_ready),                     //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_002_source0_valid),                     //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_002_source0_startofpacket),             //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_002_source0_endofpacket),               //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_002_source0_data),                      //  output,  width = 158,          .data
		.out_channel       (limiter_pipeline_002_source0_channel),                   //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                   // (terminated),                         
		.out_empty         (),                                                       // (terminated),                         
		.out_error         (),                                                       // (terminated),                         
		.in_error          (1'b0)                                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline_003 (
		.clk               (clk_100_out_clk_clk),                        //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),     //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_mux_003_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_mux_003_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_mux_003_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_mux_003_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (rsp_mux_003_src_data),                       //   input,  width = 158,          .data
		.in_channel        (rsp_mux_003_src_channel),                    //   input,    width = 5,          .channel
		.out_ready         (limiter_pipeline_003_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_003_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_003_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_003_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_003_source0_data),          //  output,  width = 158,          .data
		.out_channel       (limiter_pipeline_003_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline_004 (
		.clk               (clk_100_out_clk_clk),                                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                 //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_data),          //   input,  width = 158,          .data
		.in_channel        (subsys_hps_lwhps2fpga_rd_limiter_cmd_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (limiter_pipeline_004_source0_ready),                     //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_004_source0_valid),                     //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_004_source0_startofpacket),             //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_004_source0_endofpacket),               //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_004_source0_data),                      //  output,  width = 158,          .data
		.out_channel       (limiter_pipeline_004_source0_channel),                   //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                   // (terminated),                         
		.out_empty         (),                                                       // (terminated),                         
		.out_error         (),                                                       // (terminated),                         
		.in_error          (1'b0)                                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) limiter_pipeline_005 (
		.clk               (clk_100_out_clk_clk),                        //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),     //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_mux_004_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_mux_004_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_mux_004_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_mux_004_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (rsp_mux_004_src_data),                       //   input,  width = 158,          .data
		.in_channel        (rsp_mux_004_src_channel),                    //   input,    width = 5,          .channel
		.out_ready         (limiter_pipeline_005_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (limiter_pipeline_005_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (limiter_pipeline_005_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (limiter_pipeline_005_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (limiter_pipeline_005_source0_data),          //  output,  width = 158,          .data
		.out_channel       (limiter_pipeline_005_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                       // (terminated),                         
		.out_empty         (),                                           // (terminated),                         
		.out_error         (),                                           // (terminated),                         
		.in_error          (1'b0)                                        // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_src_ready),                      //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_src_valid),                      //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_src_startofpacket),              //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_src_endofpacket),                //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_src_data),                       //   input,  width = 266,          .data
		.in_channel        (cmd_mux_src_channel),                    //   input,    width = 5,          .channel
		.out_ready         (agent_pipeline_source0_ready),           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_source0_valid),           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_source0_startofpacket),   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_source0_endofpacket),     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_source0_data),            //  output,  width = 266,          .data
		.out_channel       (agent_pipeline_source0_channel),         //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                      //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),   //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_mux_001_src_ready),                    //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_mux_001_src_valid),                    //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_mux_001_src_startofpacket),            //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_mux_001_src_endofpacket),              //   input,    width = 1,          .endofpacket
		.in_data           (cmd_mux_001_src_data),                     //   input,  width = 266,          .data
		.in_channel        (cmd_mux_001_src_channel),                  //   input,    width = 5,          .channel
		.out_ready         (agent_pipeline_001_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_001_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_001_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_001_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_001_source0_data),          //  output,  width = 266,          .data
		.out_channel       (agent_pipeline_001_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                     // (terminated),                         
		.out_empty         (),                                         // (terminated),                         
		.out_error         (),                                         // (terminated),                         
		.in_error          (1'b0)                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_002 (
		.clk               (clk_100_out_clk_clk),                      //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),   //   input,    width = 1, cr0_reset.reset
		.in_ready          (ocm_axi_s1_agent_write_rp_ready),          //  output,    width = 1,     sink0.ready
		.in_valid          (ocm_axi_s1_agent_write_rp_valid),          //   input,    width = 1,          .valid
		.in_startofpacket  (ocm_axi_s1_agent_write_rp_startofpacket),  //   input,    width = 1,          .startofpacket
		.in_endofpacket    (ocm_axi_s1_agent_write_rp_endofpacket),    //   input,    width = 1,          .endofpacket
		.in_data           (ocm_axi_s1_agent_write_rp_data),           //   input,  width = 266,          .data
		.out_ready         (agent_pipeline_002_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_002_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_002_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_002_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_002_source0_data),          //  output,  width = 266,          .data
		.in_empty          (1'b0),                                     // (terminated),                         
		.out_empty         (),                                         // (terminated),                         
		.out_error         (),                                         // (terminated),                         
		.in_error          (1'b0),                                     // (terminated),                         
		.out_channel       (),                                         // (terminated),                         
		.in_channel        (1'b0)                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_003 (
		.clk               (clk_100_out_clk_clk),                      //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),   //   input,    width = 1, cr0_reset.reset
		.in_ready          (ocm_axi_s1_agent_read_rp_ready),           //  output,    width = 1,     sink0.ready
		.in_valid          (ocm_axi_s1_agent_read_rp_valid),           //   input,    width = 1,          .valid
		.in_startofpacket  (ocm_axi_s1_agent_read_rp_startofpacket),   //   input,    width = 1,          .startofpacket
		.in_endofpacket    (ocm_axi_s1_agent_read_rp_endofpacket),     //   input,    width = 1,          .endofpacket
		.in_data           (ocm_axi_s1_agent_read_rp_data),            //   input,  width = 266,          .data
		.out_ready         (agent_pipeline_003_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_003_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_003_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_003_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_003_source0_data),          //  output,  width = 266,          .data
		.in_empty          (1'b0),                                     // (terminated),                         
		.out_empty         (),                                         // (terminated),                         
		.out_error         (),                                         // (terminated),                         
		.in_error          (1'b0),                                     // (terminated),                         
		.out_channel       (),                                         // (terminated),                         
		.in_channel        (1'b0)                                      // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_004 (
		.clk               (clk_100_out_clk_clk),                                                     //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                                  //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_data),          //   input,  width = 158,          .data
		.in_channel        (subsys_hps_usb31_phy_reconfig_slave_burst_adapter_source0_channel),       //   input,    width = 5,          .channel
		.out_ready         (agent_pipeline_004_source0_ready),                                        //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_004_source0_valid),                                        //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_004_source0_startofpacket),                                //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_004_source0_endofpacket),                                  //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_004_source0_data),                                         //  output,  width = 158,          .data
		.out_channel       (agent_pipeline_004_source0_channel),                                      //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                                    // (terminated),                         
		.out_empty         (),                                                                        // (terminated),                         
		.out_error         (),                                                                        // (terminated),                         
		.in_error          (1'b0)                                                                     // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_005 (
		.clk               (clk_100_out_clk_clk),                                        //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                     //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_hps_usb31_phy_reconfig_slave_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_hps_usb31_phy_reconfig_slave_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_hps_usb31_phy_reconfig_slave_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_hps_usb31_phy_reconfig_slave_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_hps_usb31_phy_reconfig_slave_agent_rp_data),          //   input,  width = 158,          .data
		.out_ready         (agent_pipeline_005_source0_ready),                           //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_005_source0_valid),                           //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_005_source0_startofpacket),                   //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_005_source0_endofpacket),                     //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_005_source0_data),                            //  output,  width = 158,          .data
		.in_empty          (1'b0),                                                       // (terminated),                         
		.out_empty         (),                                                           // (terminated),                         
		.out_error         (),                                                           // (terminated),                         
		.in_error          (1'b0),                                                       // (terminated),                         
		.out_channel       (),                                                           // (terminated),                         
		.in_channel        (1'b0)                                                        // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_006 (
		.clk               (clk_100_out_clk_clk),                                           //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                        //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_data),          //   input,  width = 158,          .data
		.in_channel        (subsys_periph_pb_cpu_0_s0_burst_adapter_source0_channel),       //   input,    width = 5,          .channel
		.out_ready         (agent_pipeline_006_source0_ready),                              //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_006_source0_valid),                              //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_006_source0_startofpacket),                      //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_006_source0_endofpacket),                        //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_006_source0_data),                               //  output,  width = 158,          .data
		.out_channel       (agent_pipeline_006_source0_channel),                            //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                          // (terminated),                         
		.out_empty         (),                                                              // (terminated),                         
		.out_error         (),                                                              // (terminated),                         
		.in_error          (1'b0)                                                           // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (0),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) agent_pipeline_007 (
		.clk               (clk_100_out_clk_clk),                              //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),           //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_periph_pb_cpu_0_s0_agent_rp_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_periph_pb_cpu_0_s0_agent_rp_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_periph_pb_cpu_0_s0_agent_rp_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_periph_pb_cpu_0_s0_agent_rp_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_periph_pb_cpu_0_s0_agent_rp_data),          //   input,  width = 158,          .data
		.out_ready         (agent_pipeline_007_source0_ready),                 //   input,    width = 1,   source0.ready
		.out_valid         (agent_pipeline_007_source0_valid),                 //  output,    width = 1,          .valid
		.out_startofpacket (agent_pipeline_007_source0_startofpacket),         //  output,    width = 1,          .startofpacket
		.out_endofpacket   (agent_pipeline_007_source0_endofpacket),           //  output,    width = 1,          .endofpacket
		.out_data          (agent_pipeline_007_source0_data),                  //  output,  width = 158,          .data
		.in_empty          (1'b0),                                             // (terminated),                         
		.out_empty         (),                                                 // (terminated),                         
		.out_error         (),                                                 // (terminated),                         
		.in_error          (1'b0),                                             // (terminated),                         
		.out_channel       (),                                                 // (terminated),                         
		.in_channel        (1'b0)                                              // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline (
		.clk               (clk_100_out_clk_clk),                                                             //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                                          //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_data),          //   input,  width = 266,          .data
		.in_channel        (subsys_debug_fpga_m_master_to_ocm_axi_s1_wr_cmd_width_adapter_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_source0_ready),                                                      //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_source0_valid),                                                      //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_source0_startofpacket),                                              //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_source0_endofpacket),                                                //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_source0_data),                                                       //  output,  width = 266,          .data
		.out_channel       (mux_pipeline_source0_channel),                                                    //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                                            // (terminated),                         
		.out_empty         (),                                                                                // (terminated),                         
		.out_error         (),                                                                                // (terminated),                         
		.in_error          (1'b0)                                                                             // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_001 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_001_src0_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_001_src0_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_001_src0_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_001_src0_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_001_src0_data),                //   input,  width = 266,          .data
		.in_channel        (cmd_demux_001_src0_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_001_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_001_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_001_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_001_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_001_source0_data),          //  output,  width = 266,          .data
		.out_channel       (mux_pipeline_001_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_002 (
		.clk               (clk_100_out_clk_clk),                                                             //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                                          //   input,    width = 1, cr0_reset.reset
		.in_ready          (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_data),          //   input,  width = 266,          .data
		.in_channel        (subsys_debug_fpga_m_master_to_ocm_axi_s1_rd_cmd_width_adapter_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_002_source0_ready),                                                  //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_002_source0_valid),                                                  //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_002_source0_startofpacket),                                          //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_002_source0_endofpacket),                                            //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_002_source0_data),                                                   //  output,  width = 266,          .data
		.out_channel       (mux_pipeline_002_source0_channel),                                                //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                                            // (terminated),                         
		.out_empty         (),                                                                                // (terminated),                         
		.out_error         (),                                                                                // (terminated),                         
		.in_error          (1'b0)                                                                             // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_003 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_002_src0_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_002_src0_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_002_src0_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_002_src0_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_002_src0_data),                //   input,  width = 266,          .data
		.in_channel        (cmd_demux_002_src0_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_003_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_003_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_003_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_003_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_003_source0_data),          //  output,  width = 266,          .data
		.out_channel       (mux_pipeline_003_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_004 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_src2_ready),                   //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_src2_valid),                   //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_src2_startofpacket),           //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_src2_endofpacket),             //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_src2_data),                    //   input,  width = 158,          .data
		.in_channel        (cmd_demux_src2_channel),                 //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_004_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_004_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_004_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_004_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_004_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_004_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_005 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_003_src0_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_003_src0_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_003_src0_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_003_src0_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_003_src0_data),                //   input,  width = 158,          .data
		.in_channel        (cmd_demux_003_src0_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_005_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_005_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_005_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_005_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_005_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_005_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_006 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_004_src0_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_004_src0_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_004_src0_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_004_src0_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_004_src0_data),                //   input,  width = 158,          .data
		.in_channel        (cmd_demux_004_src0_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_006_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_006_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_006_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_006_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_006_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_006_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_007 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_003_src1_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_003_src1_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_003_src1_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_003_src1_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_003_src1_data),                //   input,  width = 158,          .data
		.in_channel        (cmd_demux_003_src1_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_007_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_007_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_007_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_007_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_007_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_007_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_008 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (cmd_demux_004_src1_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (cmd_demux_004_src1_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (cmd_demux_004_src1_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (cmd_demux_004_src1_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (cmd_demux_004_src1_data),                //   input,  width = 158,          .data
		.in_channel        (cmd_demux_004_src1_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_008_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_008_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_008_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_008_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_008_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_008_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_009 (
		.clk               (clk_100_out_clk_clk),                                                             //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                                          //   input,    width = 1, cr0_reset.reset
		.in_ready          (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_data),          //   input,  width = 158,          .data
		.in_channel        (ocm_axi_s1_wr_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_009_source0_ready),                                                  //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_009_source0_valid),                                                  //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_009_source0_startofpacket),                                          //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_009_source0_endofpacket),                                            //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_009_source0_data),                                                   //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_009_source0_channel),                                                //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                                            // (terminated),                         
		.out_empty         (),                                                                                // (terminated),                         
		.out_error         (),                                                                                // (terminated),                         
		.in_error          (1'b0)                                                                             // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_010 (
		.clk               (clk_100_out_clk_clk),                                                             //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset),                                          //   input,    width = 1, cr0_reset.reset
		.in_ready          (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_ready),         //  output,    width = 1,     sink0.ready
		.in_valid          (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_valid),         //   input,    width = 1,          .valid
		.in_startofpacket  (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_startofpacket), //   input,    width = 1,          .startofpacket
		.in_endofpacket    (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_endofpacket),   //   input,    width = 1,          .endofpacket
		.in_data           (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_data),          //   input,  width = 158,          .data
		.in_channel        (ocm_axi_s1_rd_to_subsys_debug_fpga_m_master_rsp_width_adapter_src_channel),       //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_010_source0_ready),                                                  //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_010_source0_valid),                                                  //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_010_source0_startofpacket),                                          //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_010_source0_endofpacket),                                            //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_010_source0_data),                                                   //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_010_source0_channel),                                                //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                                                            // (terminated),                         
		.out_empty         (),                                                                                // (terminated),                         
		.out_error         (),                                                                                // (terminated),                         
		.in_error          (1'b0)                                                                             // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_011 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_002_src0_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_002_src0_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_002_src0_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_002_src0_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_002_src0_data),                //   input,  width = 158,          .data
		.in_channel        (rsp_demux_002_src0_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_011_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_011_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_011_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_011_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_011_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_011_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_012 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_src1_ready),                   //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_src1_valid),                   //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_src1_startofpacket),           //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_src1_endofpacket),             //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_src1_data),                    //   input,  width = 266,          .data
		.in_channel        (rsp_demux_src1_channel),                 //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_012_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_012_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_012_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_012_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_012_source0_data),          //  output,  width = 266,          .data
		.out_channel       (mux_pipeline_012_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (266),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_013 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_001_src1_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_001_src1_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_001_src1_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_001_src1_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_001_src1_data),                //   input,  width = 266,          .data
		.in_channel        (rsp_demux_001_src1_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_013_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_013_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_013_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_013_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_013_source0_data),          //  output,  width = 266,          .data
		.out_channel       (mux_pipeline_013_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_014 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_002_src1_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_002_src1_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_002_src1_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_002_src1_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_002_src1_data),                //   input,  width = 158,          .data
		.in_channel        (rsp_demux_002_src1_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_014_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_014_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_014_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_014_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_014_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_014_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_015 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_003_src0_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_003_src0_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_003_src0_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_003_src0_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_003_src0_data),                //   input,  width = 158,          .data
		.in_channel        (rsp_demux_003_src0_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_015_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_015_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_015_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_015_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_015_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_015_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_016 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_002_src2_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_002_src2_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_002_src2_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_002_src2_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_002_src2_data),                //   input,  width = 158,          .data
		.in_channel        (rsp_demux_002_src2_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_016_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_016_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_016_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_016_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_016_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_016_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

	qsys_top_altera_avalon_st_pipeline_stage_1930_bv2ucky #(
		.SYMBOLS_PER_BEAT (1),
		.BITS_PER_SYMBOL  (158),
		.USE_PACKETS      (1),
		.USE_EMPTY        (0),
		.EMPTY_WIDTH      (0),
		.CHANNEL_WIDTH    (5),
		.PACKET_WIDTH     (2),
		.ERROR_WIDTH      (0),
		.PIPELINE_READY   (1),
		.SYNC_RESET       (1)
	) mux_pipeline_017 (
		.clk               (clk_100_out_clk_clk),                    //   input,    width = 1,       cr0.clk
		.reset             (ocm_reset1_reset_bridge_in_reset_reset), //   input,    width = 1, cr0_reset.reset
		.in_ready          (rsp_demux_003_src1_ready),               //  output,    width = 1,     sink0.ready
		.in_valid          (rsp_demux_003_src1_valid),               //   input,    width = 1,          .valid
		.in_startofpacket  (rsp_demux_003_src1_startofpacket),       //   input,    width = 1,          .startofpacket
		.in_endofpacket    (rsp_demux_003_src1_endofpacket),         //   input,    width = 1,          .endofpacket
		.in_data           (rsp_demux_003_src1_data),                //   input,  width = 158,          .data
		.in_channel        (rsp_demux_003_src1_channel),             //   input,    width = 5,          .channel
		.out_ready         (mux_pipeline_017_source0_ready),         //   input,    width = 1,   source0.ready
		.out_valid         (mux_pipeline_017_source0_valid),         //  output,    width = 1,          .valid
		.out_startofpacket (mux_pipeline_017_source0_startofpacket), //  output,    width = 1,          .startofpacket
		.out_endofpacket   (mux_pipeline_017_source0_endofpacket),   //  output,    width = 1,          .endofpacket
		.out_data          (mux_pipeline_017_source0_data),          //  output,  width = 158,          .data
		.out_channel       (mux_pipeline_017_source0_channel),       //  output,    width = 5,          .channel
		.in_empty          (1'b0),                                   // (terminated),                         
		.out_empty         (),                                       // (terminated),                         
		.out_error         (),                                       // (terminated),                         
		.in_error          (1'b0)                                    // (terminated),                         
	);

endmodule
