// hps_subsys_altera_mm_interconnect_1920_wopmpeq.v

// This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
// will probably be lost.
// 
// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module hps_subsys_altera_mm_interconnect_1920_wopmpeq (
		input  wire [6:0]   agilex_hps_io96b0_ch0_axi_awid,                                             //                                            agilex_hps_io96b0_ch0_axi.awid
		input  wire [43:0]  agilex_hps_io96b0_ch0_axi_awaddr,                                           //                                                                     .awaddr
		input  wire [7:0]   agilex_hps_io96b0_ch0_axi_awlen,                                            //                                                                     .awlen
		input  wire [2:0]   agilex_hps_io96b0_ch0_axi_awsize,                                           //                                                                     .awsize
		input  wire [1:0]   agilex_hps_io96b0_ch0_axi_awburst,                                          //                                                                     .awburst
		input  wire [0:0]   agilex_hps_io96b0_ch0_axi_awlock,                                           //                                                                     .awlock
		input  wire [2:0]   agilex_hps_io96b0_ch0_axi_awprot,                                           //                                                                     .awprot
		input  wire [13:0]  agilex_hps_io96b0_ch0_axi_awuser,                                           //                                                                     .awuser
		input  wire [3:0]   agilex_hps_io96b0_ch0_axi_awqos,                                            //                                                                     .awqos
		input  wire         agilex_hps_io96b0_ch0_axi_awvalid,                                          //                                                                     .awvalid
		output wire         agilex_hps_io96b0_ch0_axi_awready,                                          //                                                                     .awready
		input  wire [255:0] agilex_hps_io96b0_ch0_axi_wdata,                                            //                                                                     .wdata
		input  wire [31:0]  agilex_hps_io96b0_ch0_axi_wstrb,                                            //                                                                     .wstrb
		input  wire         agilex_hps_io96b0_ch0_axi_wlast,                                            //                                                                     .wlast
		input  wire         agilex_hps_io96b0_ch0_axi_wvalid,                                           //                                                                     .wvalid
		input  wire [31:0]  agilex_hps_io96b0_ch0_axi_wuser,                                            //                                                                     .wuser
		output wire         agilex_hps_io96b0_ch0_axi_wready,                                           //                                                                     .wready
		output wire [6:0]   agilex_hps_io96b0_ch0_axi_bid,                                              //                                                                     .bid
		output wire [1:0]   agilex_hps_io96b0_ch0_axi_bresp,                                            //                                                                     .bresp
		output wire         agilex_hps_io96b0_ch0_axi_bvalid,                                           //                                                                     .bvalid
		input  wire         agilex_hps_io96b0_ch0_axi_bready,                                           //                                                                     .bready
		input  wire [6:0]   agilex_hps_io96b0_ch0_axi_arid,                                             //                                                                     .arid
		input  wire [43:0]  agilex_hps_io96b0_ch0_axi_araddr,                                           //                                                                     .araddr
		input  wire [7:0]   agilex_hps_io96b0_ch0_axi_arlen,                                            //                                                                     .arlen
		input  wire [2:0]   agilex_hps_io96b0_ch0_axi_arsize,                                           //                                                                     .arsize
		input  wire [1:0]   agilex_hps_io96b0_ch0_axi_arburst,                                          //                                                                     .arburst
		input  wire [0:0]   agilex_hps_io96b0_ch0_axi_arlock,                                           //                                                                     .arlock
		input  wire [2:0]   agilex_hps_io96b0_ch0_axi_arprot,                                           //                                                                     .arprot
		input  wire [13:0]  agilex_hps_io96b0_ch0_axi_aruser,                                           //                                                                     .aruser
		input  wire [3:0]   agilex_hps_io96b0_ch0_axi_arqos,                                            //                                                                     .arqos
		input  wire         agilex_hps_io96b0_ch0_axi_arvalid,                                          //                                                                     .arvalid
		output wire         agilex_hps_io96b0_ch0_axi_arready,                                          //                                                                     .arready
		output wire [6:0]   agilex_hps_io96b0_ch0_axi_rid,                                              //                                                                     .rid
		output wire [255:0] agilex_hps_io96b0_ch0_axi_rdata,                                            //                                                                     .rdata
		output wire [1:0]   agilex_hps_io96b0_ch0_axi_rresp,                                            //                                                                     .rresp
		output wire         agilex_hps_io96b0_ch0_axi_rlast,                                            //                                                                     .rlast
		output wire         agilex_hps_io96b0_ch0_axi_rvalid,                                           //                                                                     .rvalid
		input  wire         agilex_hps_io96b0_ch0_axi_rready,                                           //                                                                     .rready
		output wire [31:0]  agilex_hps_io96b0_ch0_axi_ruser,                                            //                                                                     .ruser
		output wire [6:0]   emif_hps_s0_axi4_awid,                                                      //                                                     emif_hps_s0_axi4.awid
		output wire [39:0]  emif_hps_s0_axi4_awaddr,                                                    //                                                                     .awaddr
		output wire [7:0]   emif_hps_s0_axi4_awlen,                                                     //                                                                     .awlen
		output wire [2:0]   emif_hps_s0_axi4_awsize,                                                    //                                                                     .awsize
		output wire [1:0]   emif_hps_s0_axi4_awburst,                                                   //                                                                     .awburst
		output wire [0:0]   emif_hps_s0_axi4_awlock,                                                    //                                                                     .awlock
		output wire [2:0]   emif_hps_s0_axi4_awprot,                                                    //                                                                     .awprot
		output wire [13:0]  emif_hps_s0_axi4_awuser,                                                    //                                                                     .awuser
		output wire [3:0]   emif_hps_s0_axi4_awqos,                                                     //                                                                     .awqos
		output wire         emif_hps_s0_axi4_awvalid,                                                   //                                                                     .awvalid
		input  wire         emif_hps_s0_axi4_awready,                                                   //                                                                     .awready
		output wire [255:0] emif_hps_s0_axi4_wdata,                                                     //                                                                     .wdata
		output wire [31:0]  emif_hps_s0_axi4_wstrb,                                                     //                                                                     .wstrb
		output wire         emif_hps_s0_axi4_wlast,                                                     //                                                                     .wlast
		output wire         emif_hps_s0_axi4_wvalid,                                                    //                                                                     .wvalid
		output wire [31:0]  emif_hps_s0_axi4_wuser,                                                     //                                                                     .wuser
		input  wire         emif_hps_s0_axi4_wready,                                                    //                                                                     .wready
		input  wire [6:0]   emif_hps_s0_axi4_bid,                                                       //                                                                     .bid
		input  wire [1:0]   emif_hps_s0_axi4_bresp,                                                     //                                                                     .bresp
		input  wire         emif_hps_s0_axi4_bvalid,                                                    //                                                                     .bvalid
		output wire         emif_hps_s0_axi4_bready,                                                    //                                                                     .bready
		output wire [6:0]   emif_hps_s0_axi4_arid,                                                      //                                                                     .arid
		output wire [39:0]  emif_hps_s0_axi4_araddr,                                                    //                                                                     .araddr
		output wire [7:0]   emif_hps_s0_axi4_arlen,                                                     //                                                                     .arlen
		output wire [2:0]   emif_hps_s0_axi4_arsize,                                                    //                                                                     .arsize
		output wire [1:0]   emif_hps_s0_axi4_arburst,                                                   //                                                                     .arburst
		output wire [0:0]   emif_hps_s0_axi4_arlock,                                                    //                                                                     .arlock
		output wire [2:0]   emif_hps_s0_axi4_arprot,                                                    //                                                                     .arprot
		output wire [13:0]  emif_hps_s0_axi4_aruser,                                                    //                                                                     .aruser
		output wire [3:0]   emif_hps_s0_axi4_arqos,                                                     //                                                                     .arqos
		output wire         emif_hps_s0_axi4_arvalid,                                                   //                                                                     .arvalid
		input  wire         emif_hps_s0_axi4_arready,                                                   //                                                                     .arready
		input  wire [6:0]   emif_hps_s0_axi4_rid,                                                       //                                                                     .rid
		input  wire [255:0] emif_hps_s0_axi4_rdata,                                                     //                                                                     .rdata
		input  wire [1:0]   emif_hps_s0_axi4_rresp,                                                     //                                                                     .rresp
		input  wire         emif_hps_s0_axi4_rlast,                                                     //                                                                     .rlast
		input  wire         emif_hps_s0_axi4_rvalid,                                                    //                                                                     .rvalid
		output wire         emif_hps_s0_axi4_rready,                                                    //                                                                     .rready
		input  wire [31:0]  emif_hps_s0_axi4_ruser,                                                     //                                                                     .ruser
		input  wire         agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset_reset, // agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset.reset,  Reset Input
		input  wire         emif_hps_usr_clk_0_clk                                                      //                                                   emif_hps_usr_clk_0.clk,    Clock Input
	);

	wire   [31:0] agilex_hps_io96b0_ch0_axi_translator_m0_ruser;    // emif_hps_s0_axi4_translator:s0_ruser -> agilex_hps_io96b0_ch0_axi_translator:m0_ruser
	wire   [31:0] agilex_hps_io96b0_ch0_axi_translator_m0_wuser;    // agilex_hps_io96b0_ch0_axi_translator:m0_wuser -> emif_hps_s0_axi4_translator:s0_wuser
	wire    [1:0] agilex_hps_io96b0_ch0_axi_translator_m0_awburst;  // agilex_hps_io96b0_ch0_axi_translator:m0_awburst -> emif_hps_s0_axi4_translator:s0_awburst
	wire    [3:0] agilex_hps_io96b0_ch0_axi_translator_m0_arregion; // agilex_hps_io96b0_ch0_axi_translator:m0_arregion -> emif_hps_s0_axi4_translator:s0_arregion
	wire   [13:0] agilex_hps_io96b0_ch0_axi_translator_m0_awuser;   // agilex_hps_io96b0_ch0_axi_translator:m0_awuser -> emif_hps_s0_axi4_translator:s0_awuser
	wire    [7:0] agilex_hps_io96b0_ch0_axi_translator_m0_arlen;    // agilex_hps_io96b0_ch0_axi_translator:m0_arlen -> emif_hps_s0_axi4_translator:s0_arlen
	wire    [3:0] agilex_hps_io96b0_ch0_axi_translator_m0_arqos;    // agilex_hps_io96b0_ch0_axi_translator:m0_arqos -> emif_hps_s0_axi4_translator:s0_arqos
	wire   [31:0] agilex_hps_io96b0_ch0_axi_translator_m0_wstrb;    // agilex_hps_io96b0_ch0_axi_translator:m0_wstrb -> emif_hps_s0_axi4_translator:s0_wstrb
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_wready;   // emif_hps_s0_axi4_translator:s0_wready -> agilex_hps_io96b0_ch0_axi_translator:m0_wready
	wire    [6:0] agilex_hps_io96b0_ch0_axi_translator_m0_rid;      // emif_hps_s0_axi4_translator:s0_rid -> agilex_hps_io96b0_ch0_axi_translator:m0_rid
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_rready;   // agilex_hps_io96b0_ch0_axi_translator:m0_rready -> emif_hps_s0_axi4_translator:s0_rready
	wire    [7:0] agilex_hps_io96b0_ch0_axi_translator_m0_awlen;    // agilex_hps_io96b0_ch0_axi_translator:m0_awlen -> emif_hps_s0_axi4_translator:s0_awlen
	wire    [3:0] agilex_hps_io96b0_ch0_axi_translator_m0_awqos;    // agilex_hps_io96b0_ch0_axi_translator:m0_awqos -> emif_hps_s0_axi4_translator:s0_awqos
	wire    [3:0] agilex_hps_io96b0_ch0_axi_translator_m0_arcache;  // agilex_hps_io96b0_ch0_axi_translator:m0_arcache -> emif_hps_s0_axi4_translator:s0_arcache
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_wvalid;   // agilex_hps_io96b0_ch0_axi_translator:m0_wvalid -> emif_hps_s0_axi4_translator:s0_wvalid
	wire   [43:0] agilex_hps_io96b0_ch0_axi_translator_m0_araddr;   // agilex_hps_io96b0_ch0_axi_translator:m0_araddr -> emif_hps_s0_axi4_translator:s0_araddr
	wire    [2:0] agilex_hps_io96b0_ch0_axi_translator_m0_arprot;   // agilex_hps_io96b0_ch0_axi_translator:m0_arprot -> emif_hps_s0_axi4_translator:s0_arprot
	wire    [2:0] agilex_hps_io96b0_ch0_axi_translator_m0_awprot;   // agilex_hps_io96b0_ch0_axi_translator:m0_awprot -> emif_hps_s0_axi4_translator:s0_awprot
	wire  [255:0] agilex_hps_io96b0_ch0_axi_translator_m0_wdata;    // agilex_hps_io96b0_ch0_axi_translator:m0_wdata -> emif_hps_s0_axi4_translator:s0_wdata
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_arvalid;  // agilex_hps_io96b0_ch0_axi_translator:m0_arvalid -> emif_hps_s0_axi4_translator:s0_arvalid
	wire    [3:0] agilex_hps_io96b0_ch0_axi_translator_m0_awcache;  // agilex_hps_io96b0_ch0_axi_translator:m0_awcache -> emif_hps_s0_axi4_translator:s0_awcache
	wire    [6:0] agilex_hps_io96b0_ch0_axi_translator_m0_arid;     // agilex_hps_io96b0_ch0_axi_translator:m0_arid -> emif_hps_s0_axi4_translator:s0_arid
	wire    [0:0] agilex_hps_io96b0_ch0_axi_translator_m0_arlock;   // agilex_hps_io96b0_ch0_axi_translator:m0_arlock -> emif_hps_s0_axi4_translator:s0_arlock
	wire    [0:0] agilex_hps_io96b0_ch0_axi_translator_m0_awlock;   // agilex_hps_io96b0_ch0_axi_translator:m0_awlock -> emif_hps_s0_axi4_translator:s0_awlock
	wire   [43:0] agilex_hps_io96b0_ch0_axi_translator_m0_awaddr;   // agilex_hps_io96b0_ch0_axi_translator:m0_awaddr -> emif_hps_s0_axi4_translator:s0_awaddr
	wire    [1:0] agilex_hps_io96b0_ch0_axi_translator_m0_bresp;    // emif_hps_s0_axi4_translator:s0_bresp -> agilex_hps_io96b0_ch0_axi_translator:m0_bresp
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_arready;  // emif_hps_s0_axi4_translator:s0_arready -> agilex_hps_io96b0_ch0_axi_translator:m0_arready
	wire  [255:0] agilex_hps_io96b0_ch0_axi_translator_m0_rdata;    // emif_hps_s0_axi4_translator:s0_rdata -> agilex_hps_io96b0_ch0_axi_translator:m0_rdata
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_awready;  // emif_hps_s0_axi4_translator:s0_awready -> agilex_hps_io96b0_ch0_axi_translator:m0_awready
	wire    [1:0] agilex_hps_io96b0_ch0_axi_translator_m0_arburst;  // agilex_hps_io96b0_ch0_axi_translator:m0_arburst -> emif_hps_s0_axi4_translator:s0_arburst
	wire    [2:0] agilex_hps_io96b0_ch0_axi_translator_m0_arsize;   // agilex_hps_io96b0_ch0_axi_translator:m0_arsize -> emif_hps_s0_axi4_translator:s0_arsize
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_bready;   // agilex_hps_io96b0_ch0_axi_translator:m0_bready -> emif_hps_s0_axi4_translator:s0_bready
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_rlast;    // emif_hps_s0_axi4_translator:s0_rlast -> agilex_hps_io96b0_ch0_axi_translator:m0_rlast
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_wlast;    // agilex_hps_io96b0_ch0_axi_translator:m0_wlast -> emif_hps_s0_axi4_translator:s0_wlast
	wire    [3:0] agilex_hps_io96b0_ch0_axi_translator_m0_awregion; // agilex_hps_io96b0_ch0_axi_translator:m0_awregion -> emif_hps_s0_axi4_translator:s0_awregion
	wire   [31:0] agilex_hps_io96b0_ch0_axi_translator_m0_buser;    // emif_hps_s0_axi4_translator:s0_buser -> agilex_hps_io96b0_ch0_axi_translator:m0_buser
	wire    [1:0] agilex_hps_io96b0_ch0_axi_translator_m0_rresp;    // emif_hps_s0_axi4_translator:s0_rresp -> agilex_hps_io96b0_ch0_axi_translator:m0_rresp
	wire    [6:0] agilex_hps_io96b0_ch0_axi_translator_m0_awid;     // agilex_hps_io96b0_ch0_axi_translator:m0_awid -> emif_hps_s0_axi4_translator:s0_awid
	wire    [6:0] agilex_hps_io96b0_ch0_axi_translator_m0_bid;      // emif_hps_s0_axi4_translator:s0_bid -> agilex_hps_io96b0_ch0_axi_translator:m0_bid
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_bvalid;   // emif_hps_s0_axi4_translator:s0_bvalid -> agilex_hps_io96b0_ch0_axi_translator:m0_bvalid
	wire    [2:0] agilex_hps_io96b0_ch0_axi_translator_m0_awsize;   // agilex_hps_io96b0_ch0_axi_translator:m0_awsize -> emif_hps_s0_axi4_translator:s0_awsize
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_awvalid;  // agilex_hps_io96b0_ch0_axi_translator:m0_awvalid -> emif_hps_s0_axi4_translator:s0_awvalid
	wire   [13:0] agilex_hps_io96b0_ch0_axi_translator_m0_aruser;   // agilex_hps_io96b0_ch0_axi_translator:m0_aruser -> emif_hps_s0_axi4_translator:s0_aruser
	wire          agilex_hps_io96b0_ch0_axi_translator_m0_rvalid;   // emif_hps_s0_axi4_translator:s0_rvalid -> agilex_hps_io96b0_ch0_axi_translator:m0_rvalid

	hps_subsys_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (0),
		.USE_M0_AWREGION                   (1),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (0),
		.USE_M0_AWCACHE                    (1),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (1),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (0),
		.USE_M0_ARREGION                   (1),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (1),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (0),
		.USE_S0_ARQOS                      (1),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (7),
		.DATA_WIDTH                        (256),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (7),
		.M0_ADDR_WIDTH                     (44),
		.S0_WRITE_ADDR_USER_WIDTH          (14),
		.S0_READ_ADDR_USER_WIDTH           (14),
		.M0_WRITE_ADDR_USER_WIDTH          (14),
		.M0_READ_ADDR_USER_WIDTH           (14),
		.S0_WRITE_DATA_USER_WIDTH          (32),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.S0_READ_DATA_USER_WIDTH           (32),
		.M0_WRITE_DATA_USER_WIDTH          (32),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (32),
		.M0_READ_DATA_USER_WIDTH           (32),
		.S0_ADDR_WIDTH                     (44),
		.USE_S0_AWUSER                     (1),
		.USE_S0_ARUSER                     (1),
		.USE_S0_WUSER                      (1),
		.USE_S0_RUSER                      (1),
		.USE_S0_BUSER                      (0),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (1),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) agilex_hps_io96b0_ch0_axi_translator (
		.aclk              (emif_hps_usr_clk_0_clk),                                                      //   input,    width = 1,       clk.clk
		.aresetn           (~agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset_n
		.m0_awid           (agilex_hps_io96b0_ch0_axi_translator_m0_awid),                                //  output,    width = 7,        m0.awid
		.m0_awaddr         (agilex_hps_io96b0_ch0_axi_translator_m0_awaddr),                              //  output,   width = 44,          .awaddr
		.m0_awlen          (agilex_hps_io96b0_ch0_axi_translator_m0_awlen),                               //  output,    width = 8,          .awlen
		.m0_awsize         (agilex_hps_io96b0_ch0_axi_translator_m0_awsize),                              //  output,    width = 3,          .awsize
		.m0_awburst        (agilex_hps_io96b0_ch0_axi_translator_m0_awburst),                             //  output,    width = 2,          .awburst
		.m0_awlock         (agilex_hps_io96b0_ch0_axi_translator_m0_awlock),                              //  output,    width = 1,          .awlock
		.m0_awcache        (agilex_hps_io96b0_ch0_axi_translator_m0_awcache),                             //  output,    width = 4,          .awcache
		.m0_awprot         (agilex_hps_io96b0_ch0_axi_translator_m0_awprot),                              //  output,    width = 3,          .awprot
		.m0_awuser         (agilex_hps_io96b0_ch0_axi_translator_m0_awuser),                              //  output,   width = 14,          .awuser
		.m0_awqos          (agilex_hps_io96b0_ch0_axi_translator_m0_awqos),                               //  output,    width = 4,          .awqos
		.m0_awregion       (agilex_hps_io96b0_ch0_axi_translator_m0_awregion),                            //  output,    width = 4,          .awregion
		.m0_awvalid        (agilex_hps_io96b0_ch0_axi_translator_m0_awvalid),                             //  output,    width = 1,          .awvalid
		.m0_awready        (agilex_hps_io96b0_ch0_axi_translator_m0_awready),                             //   input,    width = 1,          .awready
		.m0_wdata          (agilex_hps_io96b0_ch0_axi_translator_m0_wdata),                               //  output,  width = 256,          .wdata
		.m0_wstrb          (agilex_hps_io96b0_ch0_axi_translator_m0_wstrb),                               //  output,   width = 32,          .wstrb
		.m0_wlast          (agilex_hps_io96b0_ch0_axi_translator_m0_wlast),                               //  output,    width = 1,          .wlast
		.m0_wvalid         (agilex_hps_io96b0_ch0_axi_translator_m0_wvalid),                              //  output,    width = 1,          .wvalid
		.m0_wuser          (agilex_hps_io96b0_ch0_axi_translator_m0_wuser),                               //  output,   width = 32,          .wuser
		.m0_wready         (agilex_hps_io96b0_ch0_axi_translator_m0_wready),                              //   input,    width = 1,          .wready
		.m0_bid            (agilex_hps_io96b0_ch0_axi_translator_m0_bid),                                 //   input,    width = 7,          .bid
		.m0_bresp          (agilex_hps_io96b0_ch0_axi_translator_m0_bresp),                               //   input,    width = 2,          .bresp
		.m0_buser          (agilex_hps_io96b0_ch0_axi_translator_m0_buser),                               //   input,   width = 32,          .buser
		.m0_bvalid         (agilex_hps_io96b0_ch0_axi_translator_m0_bvalid),                              //   input,    width = 1,          .bvalid
		.m0_bready         (agilex_hps_io96b0_ch0_axi_translator_m0_bready),                              //  output,    width = 1,          .bready
		.m0_arid           (agilex_hps_io96b0_ch0_axi_translator_m0_arid),                                //  output,    width = 7,          .arid
		.m0_araddr         (agilex_hps_io96b0_ch0_axi_translator_m0_araddr),                              //  output,   width = 44,          .araddr
		.m0_arlen          (agilex_hps_io96b0_ch0_axi_translator_m0_arlen),                               //  output,    width = 8,          .arlen
		.m0_arsize         (agilex_hps_io96b0_ch0_axi_translator_m0_arsize),                              //  output,    width = 3,          .arsize
		.m0_arburst        (agilex_hps_io96b0_ch0_axi_translator_m0_arburst),                             //  output,    width = 2,          .arburst
		.m0_arlock         (agilex_hps_io96b0_ch0_axi_translator_m0_arlock),                              //  output,    width = 1,          .arlock
		.m0_arcache        (agilex_hps_io96b0_ch0_axi_translator_m0_arcache),                             //  output,    width = 4,          .arcache
		.m0_arprot         (agilex_hps_io96b0_ch0_axi_translator_m0_arprot),                              //  output,    width = 3,          .arprot
		.m0_aruser         (agilex_hps_io96b0_ch0_axi_translator_m0_aruser),                              //  output,   width = 14,          .aruser
		.m0_arqos          (agilex_hps_io96b0_ch0_axi_translator_m0_arqos),                               //  output,    width = 4,          .arqos
		.m0_arregion       (agilex_hps_io96b0_ch0_axi_translator_m0_arregion),                            //  output,    width = 4,          .arregion
		.m0_arvalid        (agilex_hps_io96b0_ch0_axi_translator_m0_arvalid),                             //  output,    width = 1,          .arvalid
		.m0_arready        (agilex_hps_io96b0_ch0_axi_translator_m0_arready),                             //   input,    width = 1,          .arready
		.m0_rid            (agilex_hps_io96b0_ch0_axi_translator_m0_rid),                                 //   input,    width = 7,          .rid
		.m0_rdata          (agilex_hps_io96b0_ch0_axi_translator_m0_rdata),                               //   input,  width = 256,          .rdata
		.m0_rresp          (agilex_hps_io96b0_ch0_axi_translator_m0_rresp),                               //   input,    width = 2,          .rresp
		.m0_rlast          (agilex_hps_io96b0_ch0_axi_translator_m0_rlast),                               //   input,    width = 1,          .rlast
		.m0_rvalid         (agilex_hps_io96b0_ch0_axi_translator_m0_rvalid),                              //   input,    width = 1,          .rvalid
		.m0_rready         (agilex_hps_io96b0_ch0_axi_translator_m0_rready),                              //  output,    width = 1,          .rready
		.m0_ruser          (agilex_hps_io96b0_ch0_axi_translator_m0_ruser),                               //   input,   width = 32,          .ruser
		.s0_awid           (agilex_hps_io96b0_ch0_axi_awid),                                              //   input,    width = 7,        s0.awid
		.s0_awaddr         (agilex_hps_io96b0_ch0_axi_awaddr),                                            //   input,   width = 44,          .awaddr
		.s0_awlen          (agilex_hps_io96b0_ch0_axi_awlen),                                             //   input,    width = 8,          .awlen
		.s0_awsize         (agilex_hps_io96b0_ch0_axi_awsize),                                            //   input,    width = 3,          .awsize
		.s0_awburst        (agilex_hps_io96b0_ch0_axi_awburst),                                           //   input,    width = 2,          .awburst
		.s0_awlock         (agilex_hps_io96b0_ch0_axi_awlock),                                            //   input,    width = 1,          .awlock
		.s0_awprot         (agilex_hps_io96b0_ch0_axi_awprot),                                            //   input,    width = 3,          .awprot
		.s0_awuser         (agilex_hps_io96b0_ch0_axi_awuser),                                            //   input,   width = 14,          .awuser
		.s0_awqos          (agilex_hps_io96b0_ch0_axi_awqos),                                             //   input,    width = 4,          .awqos
		.s0_awvalid        (agilex_hps_io96b0_ch0_axi_awvalid),                                           //   input,    width = 1,          .awvalid
		.s0_awready        (agilex_hps_io96b0_ch0_axi_awready),                                           //  output,    width = 1,          .awready
		.s0_wdata          (agilex_hps_io96b0_ch0_axi_wdata),                                             //   input,  width = 256,          .wdata
		.s0_wstrb          (agilex_hps_io96b0_ch0_axi_wstrb),                                             //   input,   width = 32,          .wstrb
		.s0_wlast          (agilex_hps_io96b0_ch0_axi_wlast),                                             //   input,    width = 1,          .wlast
		.s0_wvalid         (agilex_hps_io96b0_ch0_axi_wvalid),                                            //   input,    width = 1,          .wvalid
		.s0_wuser          (agilex_hps_io96b0_ch0_axi_wuser),                                             //   input,   width = 32,          .wuser
		.s0_wready         (agilex_hps_io96b0_ch0_axi_wready),                                            //  output,    width = 1,          .wready
		.s0_bid            (agilex_hps_io96b0_ch0_axi_bid),                                               //  output,    width = 7,          .bid
		.s0_bresp          (agilex_hps_io96b0_ch0_axi_bresp),                                             //  output,    width = 2,          .bresp
		.s0_bvalid         (agilex_hps_io96b0_ch0_axi_bvalid),                                            //  output,    width = 1,          .bvalid
		.s0_bready         (agilex_hps_io96b0_ch0_axi_bready),                                            //   input,    width = 1,          .bready
		.s0_arid           (agilex_hps_io96b0_ch0_axi_arid),                                              //   input,    width = 7,          .arid
		.s0_araddr         (agilex_hps_io96b0_ch0_axi_araddr),                                            //   input,   width = 44,          .araddr
		.s0_arlen          (agilex_hps_io96b0_ch0_axi_arlen),                                             //   input,    width = 8,          .arlen
		.s0_arsize         (agilex_hps_io96b0_ch0_axi_arsize),                                            //   input,    width = 3,          .arsize
		.s0_arburst        (agilex_hps_io96b0_ch0_axi_arburst),                                           //   input,    width = 2,          .arburst
		.s0_arlock         (agilex_hps_io96b0_ch0_axi_arlock),                                            //   input,    width = 1,          .arlock
		.s0_arprot         (agilex_hps_io96b0_ch0_axi_arprot),                                            //   input,    width = 3,          .arprot
		.s0_aruser         (agilex_hps_io96b0_ch0_axi_aruser),                                            //   input,   width = 14,          .aruser
		.s0_arqos          (agilex_hps_io96b0_ch0_axi_arqos),                                             //   input,    width = 4,          .arqos
		.s0_arvalid        (agilex_hps_io96b0_ch0_axi_arvalid),                                           //   input,    width = 1,          .arvalid
		.s0_arready        (agilex_hps_io96b0_ch0_axi_arready),                                           //  output,    width = 1,          .arready
		.s0_rid            (agilex_hps_io96b0_ch0_axi_rid),                                               //  output,    width = 7,          .rid
		.s0_rdata          (agilex_hps_io96b0_ch0_axi_rdata),                                             //  output,  width = 256,          .rdata
		.s0_rresp          (agilex_hps_io96b0_ch0_axi_rresp),                                             //  output,    width = 2,          .rresp
		.s0_rlast          (agilex_hps_io96b0_ch0_axi_rlast),                                             //  output,    width = 1,          .rlast
		.s0_rvalid         (agilex_hps_io96b0_ch0_axi_rvalid),                                            //  output,    width = 1,          .rvalid
		.s0_rready         (agilex_hps_io96b0_ch0_axi_rready),                                            //   input,    width = 1,          .rready
		.s0_ruser          (agilex_hps_io96b0_ch0_axi_ruser),                                             //  output,   width = 32,          .ruser
		.m0_awuser_addrchk (),                                                                            // (terminated),                         
		.m0_awuser_sai     (),                                                                            // (terminated),                         
		.m0_wuser_datachk  (),                                                                            // (terminated),                         
		.m0_wuser_data     (),                                                                            // (terminated),                         
		.m0_wuser_poison   (),                                                                            // (terminated),                         
		.m0_aruser_addrchk (),                                                                            // (terminated),                         
		.m0_aruser_sai     (),                                                                            // (terminated),                         
		.m0_ruser_datachk  (32'b00000000000000000000000000000000),                                        // (terminated),                         
		.m0_ruser_data     (4'b0000),                                                                     // (terminated),                         
		.m0_ruser_poison   (4'b0000),                                                                     // (terminated),                         
		.s0_awcache        (4'b0000),                                                                     // (terminated),                         
		.s0_awuser_addrchk (4'b0000),                                                                     // (terminated),                         
		.s0_awuser_sai     (4'b0000),                                                                     // (terminated),                         
		.s0_awregion       (4'b0000),                                                                     // (terminated),                         
		.s0_wuser_datachk  (32'b00000000000000000000000000000000),                                        // (terminated),                         
		.s0_wuser_data     (4'b0000),                                                                     // (terminated),                         
		.s0_wuser_poison   (4'b0000),                                                                     // (terminated),                         
		.s0_buser          (),                                                                            // (terminated),                         
		.s0_arcache        (4'b0000),                                                                     // (terminated),                         
		.s0_aruser_addrchk (4'b0000),                                                                     // (terminated),                         
		.s0_aruser_sai     (4'b0000),                                                                     // (terminated),                         
		.s0_arregion       (4'b0000),                                                                     // (terminated),                         
		.s0_ruser_datachk  (),                                                                            // (terminated),                         
		.s0_ruser_data     (),                                                                            // (terminated),                         
		.s0_ruser_poison   (),                                                                            // (terminated),                         
		.s0_wid            (7'b0000000),                                                                  // (terminated),                         
		.s0_ardomain       (2'b00),                                                                       // (terminated),                         
		.s0_arsnoop        (4'b0000),                                                                     // (terminated),                         
		.s0_arbar          (2'b00),                                                                       // (terminated),                         
		.s0_awdomain       (2'b00),                                                                       // (terminated),                         
		.s0_awsnoop        (3'b000),                                                                      // (terminated),                         
		.s0_awbar          (2'b00),                                                                       // (terminated),                         
		.s0_awunique       (1'b0),                                                                        // (terminated),                         
		.m0_wid            (),                                                                            // (terminated),                         
		.m0_ardomain       (),                                                                            // (terminated),                         
		.m0_arsnoop        (),                                                                            // (terminated),                         
		.m0_arbar          (),                                                                            // (terminated),                         
		.m0_awdomain       (),                                                                            // (terminated),                         
		.m0_awsnoop        (),                                                                            // (terminated),                         
		.m0_awbar          (),                                                                            // (terminated),                         
		.m0_awunique       ()                                                                             // (terminated),                         
	);

	hps_subsys_altera_merlin_axi_translator_1950_sjnedva #(
		.USE_S0_AWID                       (1),
		.USE_S0_AWREGION                   (1),
		.USE_M0_AWREGION                   (0),
		.USE_S0_AWLEN                      (1),
		.USE_S0_AWSIZE                     (1),
		.USE_S0_AWBURST                    (1),
		.USE_S0_AWLOCK                     (1),
		.USE_M0_AWLOCK                     (1),
		.USE_S0_AWCACHE                    (1),
		.USE_M0_AWCACHE                    (0),
		.USE_M0_AWPROT                     (1),
		.USE_S0_AWQOS                      (1),
		.USE_M0_AWQOS                      (1),
		.USE_S0_WSTRB                      (1),
		.USE_M0_WLAST                      (1),
		.USE_S0_BID                        (1),
		.USE_S0_BRESP                      (1),
		.USE_M0_BRESP                      (1),
		.USE_S0_ARID                       (1),
		.USE_S0_ARREGION                   (1),
		.USE_M0_ARREGION                   (0),
		.USE_S0_ARLEN                      (1),
		.USE_S0_ARSIZE                     (1),
		.USE_S0_ARBURST                    (1),
		.USE_S0_ARLOCK                     (1),
		.USE_M0_ARLOCK                     (1),
		.USE_M0_ARCACHE                    (0),
		.USE_M0_ARQOS                      (1),
		.USE_M0_ARPROT                     (1),
		.USE_S0_ARCACHE                    (1),
		.USE_S0_ARQOS                      (1),
		.USE_S0_RID                        (1),
		.USE_S0_RRESP                      (1),
		.USE_M0_RRESP                      (1),
		.USE_S0_RLAST                      (1),
		.M0_ID_WIDTH                       (7),
		.DATA_WIDTH                        (256),
		.M0_SAI_WIDTH                      (4),
		.S0_SAI_WIDTH                      (4),
		.USER_DATA_WIDTH                   (4),
		.M0_USER_ADDRCHK_WIDTH             (4),
		.S0_USER_ADDRCHK_WIDTH             (4),
		.S0_ID_WIDTH                       (7),
		.M0_ADDR_WIDTH                     (40),
		.S0_WRITE_ADDR_USER_WIDTH          (14),
		.S0_READ_ADDR_USER_WIDTH           (14),
		.M0_WRITE_ADDR_USER_WIDTH          (14),
		.M0_READ_ADDR_USER_WIDTH           (14),
		.S0_WRITE_DATA_USER_WIDTH          (32),
		.S0_WRITE_RESPONSE_DATA_USER_WIDTH (32),
		.S0_READ_DATA_USER_WIDTH           (32),
		.M0_WRITE_DATA_USER_WIDTH          (32),
		.M0_WRITE_RESPONSE_DATA_USER_WIDTH (1),
		.M0_READ_DATA_USER_WIDTH           (32),
		.S0_ADDR_WIDTH                     (44),
		.USE_S0_AWUSER                     (1),
		.USE_S0_ARUSER                     (1),
		.USE_S0_WUSER                      (1),
		.USE_S0_RUSER                      (1),
		.USE_S0_BUSER                      (1),
		.USE_M0_AWUSER                     (1),
		.USE_M0_ARUSER                     (1),
		.USE_M0_WUSER                      (1),
		.USE_M0_RUSER                      (1),
		.USE_M0_BUSER                      (0),
		.M0_AXI_VERSION                    ("AXI4"),
		.M0_BURST_LENGTH_WIDTH             (8),
		.S0_BURST_LENGTH_WIDTH             (8),
		.M0_LOCK_WIDTH                     (1),
		.S0_LOCK_WIDTH                     (1),
		.S0_AXI_VERSION                    ("AXI4"),
		.ACE_LITE_SUPPORT                  (0),
		.USE_M0_AWUSER_ADDRCHK             (0),
		.USE_M0_AWUSER_SAI                 (0),
		.USE_M0_ARUSER_ADDRCHK             (0),
		.USE_M0_ARUSER_SAI                 (0),
		.USE_M0_WUSER_DATACHK              (0),
		.USE_M0_WUSER_POISON               (0),
		.USE_M0_RUSER_DATACHK              (0),
		.USE_M0_RUSER_POISON               (0),
		.USE_M0_WUSER_DATA                 (0),
		.USE_M0_RUSER_DATA                 (0),
		.USE_S0_AWUSER_ADDRCHK             (0),
		.USE_S0_AWUSER_SAI                 (0),
		.USE_S0_ARUSER_ADDRCHK             (0),
		.USE_S0_ARUSER_SAI                 (0),
		.USE_S0_WUSER_DATACHK              (0),
		.USE_S0_WUSER_POISON               (0),
		.USE_S0_RUSER_DATACHK              (0),
		.USE_S0_WUSER_DATA                 (0),
		.USE_S0_RUSER_DATA                 (0),
		.USE_S0_RUSER_POISON               (0),
		.REGENERATE_ADDRCHK                (0),
		.ROLE_BASED_USER                   (0)
	) emif_hps_s0_axi4_translator (
		.aclk              (emif_hps_usr_clk_0_clk),                                                      //   input,    width = 1,       clk.clk
		.aresetn           (~agilex_hps_io96b0_ch0_axi_translator_clk_reset_reset_bridge_in_reset_reset), //   input,    width = 1, clk_reset.reset_n
		.m0_awid           (emif_hps_s0_axi4_awid),                                                       //  output,    width = 7,        m0.awid
		.m0_awaddr         (emif_hps_s0_axi4_awaddr),                                                     //  output,   width = 40,          .awaddr
		.m0_awlen          (emif_hps_s0_axi4_awlen),                                                      //  output,    width = 8,          .awlen
		.m0_awsize         (emif_hps_s0_axi4_awsize),                                                     //  output,    width = 3,          .awsize
		.m0_awburst        (emif_hps_s0_axi4_awburst),                                                    //  output,    width = 2,          .awburst
		.m0_awlock         (emif_hps_s0_axi4_awlock),                                                     //  output,    width = 1,          .awlock
		.m0_awprot         (emif_hps_s0_axi4_awprot),                                                     //  output,    width = 3,          .awprot
		.m0_awuser         (emif_hps_s0_axi4_awuser),                                                     //  output,   width = 14,          .awuser
		.m0_awqos          (emif_hps_s0_axi4_awqos),                                                      //  output,    width = 4,          .awqos
		.m0_awvalid        (emif_hps_s0_axi4_awvalid),                                                    //  output,    width = 1,          .awvalid
		.m0_awready        (emif_hps_s0_axi4_awready),                                                    //   input,    width = 1,          .awready
		.m0_wdata          (emif_hps_s0_axi4_wdata),                                                      //  output,  width = 256,          .wdata
		.m0_wstrb          (emif_hps_s0_axi4_wstrb),                                                      //  output,   width = 32,          .wstrb
		.m0_wlast          (emif_hps_s0_axi4_wlast),                                                      //  output,    width = 1,          .wlast
		.m0_wvalid         (emif_hps_s0_axi4_wvalid),                                                     //  output,    width = 1,          .wvalid
		.m0_wuser          (emif_hps_s0_axi4_wuser),                                                      //  output,   width = 32,          .wuser
		.m0_wready         (emif_hps_s0_axi4_wready),                                                     //   input,    width = 1,          .wready
		.m0_bid            (emif_hps_s0_axi4_bid),                                                        //   input,    width = 7,          .bid
		.m0_bresp          (emif_hps_s0_axi4_bresp),                                                      //   input,    width = 2,          .bresp
		.m0_bvalid         (emif_hps_s0_axi4_bvalid),                                                     //   input,    width = 1,          .bvalid
		.m0_bready         (emif_hps_s0_axi4_bready),                                                     //  output,    width = 1,          .bready
		.m0_arid           (emif_hps_s0_axi4_arid),                                                       //  output,    width = 7,          .arid
		.m0_araddr         (emif_hps_s0_axi4_araddr),                                                     //  output,   width = 40,          .araddr
		.m0_arlen          (emif_hps_s0_axi4_arlen),                                                      //  output,    width = 8,          .arlen
		.m0_arsize         (emif_hps_s0_axi4_arsize),                                                     //  output,    width = 3,          .arsize
		.m0_arburst        (emif_hps_s0_axi4_arburst),                                                    //  output,    width = 2,          .arburst
		.m0_arlock         (emif_hps_s0_axi4_arlock),                                                     //  output,    width = 1,          .arlock
		.m0_arprot         (emif_hps_s0_axi4_arprot),                                                     //  output,    width = 3,          .arprot
		.m0_aruser         (emif_hps_s0_axi4_aruser),                                                     //  output,   width = 14,          .aruser
		.m0_arqos          (emif_hps_s0_axi4_arqos),                                                      //  output,    width = 4,          .arqos
		.m0_arvalid        (emif_hps_s0_axi4_arvalid),                                                    //  output,    width = 1,          .arvalid
		.m0_arready        (emif_hps_s0_axi4_arready),                                                    //   input,    width = 1,          .arready
		.m0_rid            (emif_hps_s0_axi4_rid),                                                        //   input,    width = 7,          .rid
		.m0_rdata          (emif_hps_s0_axi4_rdata),                                                      //   input,  width = 256,          .rdata
		.m0_rresp          (emif_hps_s0_axi4_rresp),                                                      //   input,    width = 2,          .rresp
		.m0_rlast          (emif_hps_s0_axi4_rlast),                                                      //   input,    width = 1,          .rlast
		.m0_rvalid         (emif_hps_s0_axi4_rvalid),                                                     //   input,    width = 1,          .rvalid
		.m0_rready         (emif_hps_s0_axi4_rready),                                                     //  output,    width = 1,          .rready
		.m0_ruser          (emif_hps_s0_axi4_ruser),                                                      //   input,   width = 32,          .ruser
		.s0_awid           (agilex_hps_io96b0_ch0_axi_translator_m0_awid),                                //   input,    width = 7,        s0.awid
		.s0_awaddr         (agilex_hps_io96b0_ch0_axi_translator_m0_awaddr),                              //   input,   width = 44,          .awaddr
		.s0_awlen          (agilex_hps_io96b0_ch0_axi_translator_m0_awlen),                               //   input,    width = 8,          .awlen
		.s0_awsize         (agilex_hps_io96b0_ch0_axi_translator_m0_awsize),                              //   input,    width = 3,          .awsize
		.s0_awburst        (agilex_hps_io96b0_ch0_axi_translator_m0_awburst),                             //   input,    width = 2,          .awburst
		.s0_awlock         (agilex_hps_io96b0_ch0_axi_translator_m0_awlock),                              //   input,    width = 1,          .awlock
		.s0_awcache        (agilex_hps_io96b0_ch0_axi_translator_m0_awcache),                             //   input,    width = 4,          .awcache
		.s0_awprot         (agilex_hps_io96b0_ch0_axi_translator_m0_awprot),                              //   input,    width = 3,          .awprot
		.s0_awuser         (agilex_hps_io96b0_ch0_axi_translator_m0_awuser),                              //   input,   width = 14,          .awuser
		.s0_awqos          (agilex_hps_io96b0_ch0_axi_translator_m0_awqos),                               //   input,    width = 4,          .awqos
		.s0_awregion       (agilex_hps_io96b0_ch0_axi_translator_m0_awregion),                            //   input,    width = 4,          .awregion
		.s0_awvalid        (agilex_hps_io96b0_ch0_axi_translator_m0_awvalid),                             //   input,    width = 1,          .awvalid
		.s0_awready        (agilex_hps_io96b0_ch0_axi_translator_m0_awready),                             //  output,    width = 1,          .awready
		.s0_wdata          (agilex_hps_io96b0_ch0_axi_translator_m0_wdata),                               //   input,  width = 256,          .wdata
		.s0_wstrb          (agilex_hps_io96b0_ch0_axi_translator_m0_wstrb),                               //   input,   width = 32,          .wstrb
		.s0_wlast          (agilex_hps_io96b0_ch0_axi_translator_m0_wlast),                               //   input,    width = 1,          .wlast
		.s0_wvalid         (agilex_hps_io96b0_ch0_axi_translator_m0_wvalid),                              //   input,    width = 1,          .wvalid
		.s0_wuser          (agilex_hps_io96b0_ch0_axi_translator_m0_wuser),                               //   input,   width = 32,          .wuser
		.s0_wready         (agilex_hps_io96b0_ch0_axi_translator_m0_wready),                              //  output,    width = 1,          .wready
		.s0_bid            (agilex_hps_io96b0_ch0_axi_translator_m0_bid),                                 //  output,    width = 7,          .bid
		.s0_bresp          (agilex_hps_io96b0_ch0_axi_translator_m0_bresp),                               //  output,    width = 2,          .bresp
		.s0_buser          (agilex_hps_io96b0_ch0_axi_translator_m0_buser),                               //  output,   width = 32,          .buser
		.s0_bvalid         (agilex_hps_io96b0_ch0_axi_translator_m0_bvalid),                              //  output,    width = 1,          .bvalid
		.s0_bready         (agilex_hps_io96b0_ch0_axi_translator_m0_bready),                              //   input,    width = 1,          .bready
		.s0_arid           (agilex_hps_io96b0_ch0_axi_translator_m0_arid),                                //   input,    width = 7,          .arid
		.s0_araddr         (agilex_hps_io96b0_ch0_axi_translator_m0_araddr),                              //   input,   width = 44,          .araddr
		.s0_arlen          (agilex_hps_io96b0_ch0_axi_translator_m0_arlen),                               //   input,    width = 8,          .arlen
		.s0_arsize         (agilex_hps_io96b0_ch0_axi_translator_m0_arsize),                              //   input,    width = 3,          .arsize
		.s0_arburst        (agilex_hps_io96b0_ch0_axi_translator_m0_arburst),                             //   input,    width = 2,          .arburst
		.s0_arlock         (agilex_hps_io96b0_ch0_axi_translator_m0_arlock),                              //   input,    width = 1,          .arlock
		.s0_arcache        (agilex_hps_io96b0_ch0_axi_translator_m0_arcache),                             //   input,    width = 4,          .arcache
		.s0_arprot         (agilex_hps_io96b0_ch0_axi_translator_m0_arprot),                              //   input,    width = 3,          .arprot
		.s0_aruser         (agilex_hps_io96b0_ch0_axi_translator_m0_aruser),                              //   input,   width = 14,          .aruser
		.s0_arqos          (agilex_hps_io96b0_ch0_axi_translator_m0_arqos),                               //   input,    width = 4,          .arqos
		.s0_arregion       (agilex_hps_io96b0_ch0_axi_translator_m0_arregion),                            //   input,    width = 4,          .arregion
		.s0_arvalid        (agilex_hps_io96b0_ch0_axi_translator_m0_arvalid),                             //   input,    width = 1,          .arvalid
		.s0_arready        (agilex_hps_io96b0_ch0_axi_translator_m0_arready),                             //  output,    width = 1,          .arready
		.s0_rid            (agilex_hps_io96b0_ch0_axi_translator_m0_rid),                                 //  output,    width = 7,          .rid
		.s0_rdata          (agilex_hps_io96b0_ch0_axi_translator_m0_rdata),                               //  output,  width = 256,          .rdata
		.s0_rresp          (agilex_hps_io96b0_ch0_axi_translator_m0_rresp),                               //  output,    width = 2,          .rresp
		.s0_rlast          (agilex_hps_io96b0_ch0_axi_translator_m0_rlast),                               //  output,    width = 1,          .rlast
		.s0_rvalid         (agilex_hps_io96b0_ch0_axi_translator_m0_rvalid),                              //  output,    width = 1,          .rvalid
		.s0_rready         (agilex_hps_io96b0_ch0_axi_translator_m0_rready),                              //   input,    width = 1,          .rready
		.s0_ruser          (agilex_hps_io96b0_ch0_axi_translator_m0_ruser),                               //  output,   width = 32,          .ruser
		.m0_awcache        (),                                                                            // (terminated),                         
		.m0_awuser_addrchk (),                                                                            // (terminated),                         
		.m0_awuser_sai     (),                                                                            // (terminated),                         
		.m0_awregion       (),                                                                            // (terminated),                         
		.m0_wuser_datachk  (),                                                                            // (terminated),                         
		.m0_wuser_data     (),                                                                            // (terminated),                         
		.m0_wuser_poison   (),                                                                            // (terminated),                         
		.m0_buser          (1'b0),                                                                        // (terminated),                         
		.m0_arcache        (),                                                                            // (terminated),                         
		.m0_aruser_addrchk (),                                                                            // (terminated),                         
		.m0_aruser_sai     (),                                                                            // (terminated),                         
		.m0_arregion       (),                                                                            // (terminated),                         
		.m0_ruser_datachk  (32'b00000000000000000000000000000000),                                        // (terminated),                         
		.m0_ruser_data     (4'b0000),                                                                     // (terminated),                         
		.m0_ruser_poison   (4'b0000),                                                                     // (terminated),                         
		.s0_awuser_addrchk (4'b0000),                                                                     // (terminated),                         
		.s0_awuser_sai     (4'b0000),                                                                     // (terminated),                         
		.s0_wuser_datachk  (32'b00000000000000000000000000000000),                                        // (terminated),                         
		.s0_wuser_data     (4'b0000),                                                                     // (terminated),                         
		.s0_wuser_poison   (4'b0000),                                                                     // (terminated),                         
		.s0_aruser_addrchk (4'b0000),                                                                     // (terminated),                         
		.s0_aruser_sai     (4'b0000),                                                                     // (terminated),                         
		.s0_ruser_datachk  (),                                                                            // (terminated),                         
		.s0_ruser_data     (),                                                                            // (terminated),                         
		.s0_ruser_poison   (),                                                                            // (terminated),                         
		.s0_wid            (7'b0000000),                                                                  // (terminated),                         
		.s0_ardomain       (2'b00),                                                                       // (terminated),                         
		.s0_arsnoop        (4'b0000),                                                                     // (terminated),                         
		.s0_arbar          (2'b00),                                                                       // (terminated),                         
		.s0_awdomain       (2'b00),                                                                       // (terminated),                         
		.s0_awsnoop        (3'b000),                                                                      // (terminated),                         
		.s0_awbar          (2'b00),                                                                       // (terminated),                         
		.s0_awunique       (1'b0),                                                                        // (terminated),                         
		.m0_wid            (),                                                                            // (terminated),                         
		.m0_ardomain       (),                                                                            // (terminated),                         
		.m0_arsnoop        (),                                                                            // (terminated),                         
		.m0_arbar          (),                                                                            // (terminated),                         
		.m0_awdomain       (),                                                                            // (terminated),                         
		.m0_awsnoop        (),                                                                            // (terminated),                         
		.m0_awbar          (),                                                                            // (terminated),                         
		.m0_awunique       ()                                                                             // (terminated),                         
	);

endmodule
