// (C) 2001-2024 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.


// (C) 2001-2023 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.


(* icm_name="sm_flux_dpma_clk_mux", module_type="mux", simple_name="UNKNOWN", atom_type__std *)
module tennm_sm_flux_dpma_clk_mux 
    #(
        parameter sel                                                = "SEL_UNUSED"                   /* Settings: SEL_LOCAL_SYSPLL_C2_CLK, SEL_GLOBAL_DOWNWARD_SYSPLL_C2_CLK, SEL_GLOBAL_UPWARD_SYSPLL_C2_CLK, SEL_CNOC_CLK, SEL_UNUSED */
    )
    (
        input i_cnoc_clk,
        input i_global_downward_syspll_c2_clk,
        input i_global_upward_syspll_c2_clk,
        input i_local_syspll_c2_clk,
        output o_ux_dpma_clk
    );

`ifdef DDM_BASED_COREIP_GENERATOR
    sm_flux_dpma_clk_mux 
`ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    #(
        .sel(sel)
    )
`endif // ifdef DEFINE_SF_RTL_MODULE_PARAMETERS
    x_sm_flux_dpma_clk_mux (
        .i_cnoc_clk(i_cnoc_clk),
        .i_global_downward_syspll_c2_clk(i_global_downward_syspll_c2_clk),
        .i_global_upward_syspll_c2_clk(i_global_upward_syspll_c2_clk),
        .i_local_syspll_c2_clk(i_local_syspll_c2_clk),
        .o_ux_dpma_clk(o_ux_dpma_clk)
        );
`else // ifdef DDM_BASED_COREIP_GENERATOR
    generate
        if ( "SEL_LOCAL_SYSPLL_C2_CLK" == sel ) begin : sel_is_LOCAL_SYSPLL_C2_CLK
            assign o_ux_dpma_clk = i_local_syspll_c2_clk;
        end : sel_is_LOCAL_SYSPLL_C2_CLK
        if ( "SEL_GLOBAL_DOWNWARD_SYSPLL_C2_CLK" == sel ) begin : sel_is_GLOBAL_DOWNWARD_SYSPLL_C2_CLK
            assign o_ux_dpma_clk = i_global_downward_syspll_c2_clk;
        end : sel_is_GLOBAL_DOWNWARD_SYSPLL_C2_CLK
        if ( "SEL_GLOBAL_UPWARD_SYSPLL_C2_CLK" == sel ) begin : sel_is_GLOBAL_UPWARD_SYSPLL_C2_CLK
            assign o_ux_dpma_clk = i_global_upward_syspll_c2_clk;
        end : sel_is_GLOBAL_UPWARD_SYSPLL_C2_CLK
        if ( "SEL_CNOC_CLK" == sel ) begin : sel_is_CNOC_CLK
            assign o_ux_dpma_clk = i_cnoc_clk;
        end : sel_is_CNOC_CLK
    endgenerate
`endif // ifdef DDM_BASED_COREIP_GENERATOR

endmodule // tennm_sm_flux_dpma_clk_mux

`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "jdaUczDmknd1j2HuPjy2WibKQVNvjDAujm2msitPRQoSFM04DSnFOv0NrtpdX9wrEXFRSeF81hifny2PNSYSx2xbOYWohtJE59kvSVpRk/5J+3xhF/pnYEmSr+fA5rANOS6fNQCkK4f0YSNgBEN5vciEqUoettmRJ9wpaoO4wE8Lj97m69uhnOhz9+QnQN0/xq50SaYZiq9mlvbuEQSq5FYqTlYbfMHbID9Wx8jVEPNzCI1DDgNtT+v/8fLX9NA479otpw+AATIX2OUItvWxWiPK36DpQJRUt3Cngzo7+NMTnPbCTRziwAxrHBy1toHy/8aNnO7jq8vSAFcd9REpetMQm5YNLq7F/tv7k8RVDjNDp/JeKlndm4YJduxbPAXGUSsA/eECWSEmRsvFvVVYWaSUFU+vprmF9fSo3hZeGs3Y7D+1T3ilnvtnuKvO8anuwv2ljzmUtvc6nA8DAUZgbMjZaMlaEejKwgBvrX1MHkns5x7RMJgUXzwvVNCPwmcNGDBMgTqrmoUxiDuOZ+Dwl07mW2aIlquvIeRItRwmnvx79Rp5JaFQKNLf6OvwuZD4+T3aZ02+h22ncnt1VjJarsRjzVxENgzvy0AWdUIYssIf7GWmalAeDV9ty+utCf/lrcNcvDpal2e87aghlJmcWovFjqJuk7ob+kv7oaikQEO37dnwCiqWe4UmuFcO+b4e4HDAATRv05xN+YmEYmBXsJ+gaMy07yZ7HdB8LkEgGV1k4NDvMd/SQHxu/OBjeLJArSwvkUmBUnEf3R0K4vMTo1nIPjYGp0Bp9JRdCx3mdUrB2GOxToCrkRyB8bcSnwsYZOxFxvTJtI4fflyJz6DZkiZrGNvMHQaYBaIoUNKxhw+pV/qKorybY4X2lmEE6Y2hrR8EuG4u9/Kr/X0Jdn9leWRvDN1+7lyZTN7OFQCieEzbn+oOfOCIcjr5Vzr6cZw+F6//VasrJO25ylKUxnczUUbm3UgsQISD7DW0SuKKiauNxMwSvnt1xTll8UEHmvfJ"
`endif
`ifdef QUESTA_INTEL_OEM
`pragma questa_oem_00 "mr8jg6yVyp+1vCTSmm9okNGk/MFlI0RPgpclK5sJLh1jVstZniZ9YOfmN88MxbRZ2R9n6JUN5qUH1ePxKsetzz1WYna7MjmI3bbnOOrj9bgeBmNZMK5blGJcG/5l8YpGARVzlg+qL5wBUfY239yiLMLlxcFQsSMeUV3CxQOjMGuwK0UNiTu9YQpoIvBUadaVlUJYD0/eo11RyVMEsbtlFdUm+sT9khX6udL1+1bFfkRCaC58aKNntBXVlhG5SgXXEO7J+pQudVq4foS24iRMl6gGtD0Lg0i5spCxYPg2boUYYMkib26X/QovErAfw0QnQUCmOAcu/8sYlMWk3HfMs2V8Q3Zr11onjQEPFFyq5aEM5RQLI9LQDBsO1Pdazc9ilCjXDcgcwyTvqtbesuKHAdT5+7hFp2BoMuStUSGeRogix1fAHoeXJO+iHAFt/C2w/hZizRcoUsg2q97XwjHmuPs4sqMKOVJUFhg4eYsAyhCU+TKO7Ro8ZQnakvLjDcDy+1vAj1nCrd9FgbkZ4iD+oMQvG9I8Qsf1B9JB2+doedt0otQX8P6/uZCc3OFfa1fteFL6i6wgXIQQRGyiIPYvvHwvU6OL7QxprY67Par7c9jBkLRhjvNMn5p6bDeqPNonP6OV+c8/nDiFRN3JuzzLRhECRsjKwxOa6Ny45LZC6bqaIlTTX78S5JWB6B3xAj0ooMWhw0oQc/l2gpLz2q8JS9yNZvrP7vsPy++Szx19UCLLBIK9R+lG2ScyulJp6Z1M+tUxq4eXP4AXcrx7LmpsiJ97Bn4cy9vVCD+bowWqBFGYs63DJkhysefwTvCbhbIaaP3gYNUTZDIzfbfWMIsLgGnG6q2xaUGn/KBZHL/Kq9kgDtcjoMXHlKo3/e8Y4/1+Ve/Jn/3nT7F31QHDhatueaXjpFYIG51zeqLNki34kdd5m3coXp3T+iv/p5Iua4ceM6MK91/qacJzwX/viGTezmP2AEh0x3GnE6h4saTOVrhOI7E+GfxZY/Aaszdyq/Z9"
`endif