// emif_hps.v

// Generated using ACDS version 24.1 115

`timescale 1 ps / 1 ps
module emif_hps (
		output wire         noc_aclk_0,              //      usr_clk_0.clk
		input  wire [39:0]  s0_axi4_araddr,          //        s0_axi4.araddr
		input  wire [1:0]   s0_axi4_arburst,         //               .arburst
		input  wire [6:0]   s0_axi4_arid,            //               .arid
		input  wire [7:0]   s0_axi4_arlen,           //               .arlen
		input  wire         s0_axi4_arlock,          //               .arlock
		input  wire [3:0]   s0_axi4_arqos,           //               .arqos
		input  wire [2:0]   s0_axi4_arsize,          //               .arsize
		input  wire         s0_axi4_arvalid,         //               .arvalid
		input  wire [13:0]  s0_axi4_aruser,          //               .aruser
		input  wire [2:0]   s0_axi4_arprot,          //               .arprot
		input  wire [39:0]  s0_axi4_awaddr,          //               .awaddr
		input  wire [1:0]   s0_axi4_awburst,         //               .awburst
		input  wire [6:0]   s0_axi4_awid,            //               .awid
		input  wire [7:0]   s0_axi4_awlen,           //               .awlen
		input  wire         s0_axi4_awlock,          //               .awlock
		input  wire [3:0]   s0_axi4_awqos,           //               .awqos
		input  wire [2:0]   s0_axi4_awsize,          //               .awsize
		input  wire         s0_axi4_awvalid,         //               .awvalid
		input  wire [13:0]  s0_axi4_awuser,          //               .awuser
		input  wire [2:0]   s0_axi4_awprot,          //               .awprot
		input  wire         s0_axi4_bready,          //               .bready
		input  wire         s0_axi4_rready,          //               .rready
		input  wire [255:0] s0_axi4_wdata,           //               .wdata
		input  wire [31:0]  s0_axi4_wstrb,           //               .wstrb
		input  wire         s0_axi4_wlast,           //               .wlast
		input  wire         s0_axi4_wvalid,          //               .wvalid
		input  wire [31:0]  s0_axi4_wuser,           //               .wuser
		output wire [31:0]  s0_axi4_ruser,           //               .ruser
		output wire         s0_axi4_arready,         //               .arready
		output wire         s0_axi4_awready,         //               .awready
		output wire [6:0]   s0_axi4_bid,             //               .bid
		output wire [1:0]   s0_axi4_bresp,           //               .bresp
		output wire         s0_axi4_bvalid,          //               .bvalid
		output wire [255:0] s0_axi4_rdata,           //               .rdata
		output wire [6:0]   s0_axi4_rid,             //               .rid
		output wire         s0_axi4_rlast,           //               .rlast
		output wire [1:0]   s0_axi4_rresp,           //               .rresp
		output wire         s0_axi4_rvalid,          //               .rvalid
		output wire         s0_axi4_wready,          //               .wready
		output wire         emif_mem_0_mem_ck_t,     //     emif_mem_0.mem_ck_t
		output wire         emif_mem_0_mem_ck_c,     //               .mem_ck_c
		output wire         emif_mem_0_mem_cke,      //               .mem_cke
		output wire         emif_mem_0_mem_odt,      //               .mem_odt
		output wire         emif_mem_0_mem_cs_n,     //               .mem_cs_n
		output wire [16:0]  emif_mem_0_mem_a,        //               .mem_a
		output wire [1:0]   emif_mem_0_mem_ba,       //               .mem_ba
		output wire         emif_mem_0_mem_bg,       //               .mem_bg
		output wire         emif_mem_0_mem_act_n,    //               .mem_act_n
		output wire         emif_mem_0_mem_par,      //               .mem_par
		input  wire         emif_mem_0_mem_alert_n,  //               .mem_alert_n
		output wire         emif_mem_0_mem_reset_n,  //               .mem_reset_n
		inout  wire [31:0]  emif_mem_0_mem_dq,       //               .mem_dq
		inout  wire [3:0]   emif_mem_0_mem_dqs_t,    //               .mem_dqs_t
		inout  wire [3:0]   emif_mem_0_mem_dqs_c,    //               .mem_dqs_c
		inout  wire [3:0]   emif_mem_0_mem_dbi_n,    //               .mem_dbi_n
		input  wire         emif_oct_0_oct_rzqin,    //     emif_oct_0.oct_rzqin
		output wire         s0_noc_axi4lite_clk,     //    s0_axil_clk.clk
		output wire         s0_noc_axi4lite_rst_n,   //  s0_axil_rst_n.reset_n
		input  wire [26:0]  s0_noc_axi4lite_awaddr,  //        s0_axil.awaddr
		input  wire         s0_noc_axi4lite_awvalid, //               .awvalid
		output wire         s0_noc_axi4lite_awready, //               .awready
		input  wire [31:0]  s0_noc_axi4lite_wdata,   //               .wdata
		input  wire [3:0]   s0_noc_axi4lite_wstrb,   //               .wstrb
		input  wire         s0_noc_axi4lite_wvalid,  //               .wvalid
		output wire         s0_noc_axi4lite_wready,  //               .wready
		output wire [1:0]   s0_noc_axi4lite_bresp,   //               .bresp
		output wire         s0_noc_axi4lite_bvalid,  //               .bvalid
		input  wire         s0_noc_axi4lite_bready,  //               .bready
		input  wire [26:0]  s0_noc_axi4lite_araddr,  //               .araddr
		input  wire         s0_noc_axi4lite_arvalid, //               .arvalid
		output wire         s0_noc_axi4lite_arready, //               .arready
		output wire [31:0]  s0_noc_axi4lite_rdata,   //               .rdata
		output wire [1:0]   s0_noc_axi4lite_rresp,   //               .rresp
		output wire         s0_noc_axi4lite_rvalid,  //               .rvalid
		input  wire         s0_noc_axi4lite_rready,  //               .rready
		input  wire [2:0]   s0_noc_axi4lite_awprot,  //               .awprot
		input  wire [2:0]   s0_noc_axi4lite_arprot,  //               .arprot
		output wire         out_reset_0_n,           //    usr_rst_n_0.reset_n
		input  wire         emif_ref_clk_0_clk       // emif_ref_clk_0.clk
	);

	emif_hps_emif_hps_ph2_610_r3atsia emif_hps_ph2_inst (
		.noc_aclk_0              (noc_aclk_0),              //  output,    width = 1,      usr_clk_0.clk
		.s0_axi4_araddr          (s0_axi4_araddr),          //   input,   width = 40,        s0_axi4.araddr
		.s0_axi4_arburst         (s0_axi4_arburst),         //   input,    width = 2,               .arburst
		.s0_axi4_arid            (s0_axi4_arid),            //   input,    width = 7,               .arid
		.s0_axi4_arlen           (s0_axi4_arlen),           //   input,    width = 8,               .arlen
		.s0_axi4_arlock          (s0_axi4_arlock),          //   input,    width = 1,               .arlock
		.s0_axi4_arqos           (s0_axi4_arqos),           //   input,    width = 4,               .arqos
		.s0_axi4_arsize          (s0_axi4_arsize),          //   input,    width = 3,               .arsize
		.s0_axi4_arvalid         (s0_axi4_arvalid),         //   input,    width = 1,               .arvalid
		.s0_axi4_aruser          (s0_axi4_aruser),          //   input,   width = 14,               .aruser
		.s0_axi4_arprot          (s0_axi4_arprot),          //   input,    width = 3,               .arprot
		.s0_axi4_awaddr          (s0_axi4_awaddr),          //   input,   width = 40,               .awaddr
		.s0_axi4_awburst         (s0_axi4_awburst),         //   input,    width = 2,               .awburst
		.s0_axi4_awid            (s0_axi4_awid),            //   input,    width = 7,               .awid
		.s0_axi4_awlen           (s0_axi4_awlen),           //   input,    width = 8,               .awlen
		.s0_axi4_awlock          (s0_axi4_awlock),          //   input,    width = 1,               .awlock
		.s0_axi4_awqos           (s0_axi4_awqos),           //   input,    width = 4,               .awqos
		.s0_axi4_awsize          (s0_axi4_awsize),          //   input,    width = 3,               .awsize
		.s0_axi4_awvalid         (s0_axi4_awvalid),         //   input,    width = 1,               .awvalid
		.s0_axi4_awuser          (s0_axi4_awuser),          //   input,   width = 14,               .awuser
		.s0_axi4_awprot          (s0_axi4_awprot),          //   input,    width = 3,               .awprot
		.s0_axi4_bready          (s0_axi4_bready),          //   input,    width = 1,               .bready
		.s0_axi4_rready          (s0_axi4_rready),          //   input,    width = 1,               .rready
		.s0_axi4_wdata           (s0_axi4_wdata),           //   input,  width = 256,               .wdata
		.s0_axi4_wstrb           (s0_axi4_wstrb),           //   input,   width = 32,               .wstrb
		.s0_axi4_wlast           (s0_axi4_wlast),           //   input,    width = 1,               .wlast
		.s0_axi4_wvalid          (s0_axi4_wvalid),          //   input,    width = 1,               .wvalid
		.s0_axi4_wuser           (s0_axi4_wuser),           //   input,   width = 32,               .wuser
		.s0_axi4_ruser           (s0_axi4_ruser),           //  output,   width = 32,               .ruser
		.s0_axi4_arready         (s0_axi4_arready),         //  output,    width = 1,               .arready
		.s0_axi4_awready         (s0_axi4_awready),         //  output,    width = 1,               .awready
		.s0_axi4_bid             (s0_axi4_bid),             //  output,    width = 7,               .bid
		.s0_axi4_bresp           (s0_axi4_bresp),           //  output,    width = 2,               .bresp
		.s0_axi4_bvalid          (s0_axi4_bvalid),          //  output,    width = 1,               .bvalid
		.s0_axi4_rdata           (s0_axi4_rdata),           //  output,  width = 256,               .rdata
		.s0_axi4_rid             (s0_axi4_rid),             //  output,    width = 7,               .rid
		.s0_axi4_rlast           (s0_axi4_rlast),           //  output,    width = 1,               .rlast
		.s0_axi4_rresp           (s0_axi4_rresp),           //  output,    width = 2,               .rresp
		.s0_axi4_rvalid          (s0_axi4_rvalid),          //  output,    width = 1,               .rvalid
		.s0_axi4_wready          (s0_axi4_wready),          //  output,    width = 1,               .wready
		.emif_mem_0_mem_ck_t     (emif_mem_0_mem_ck_t),     //  output,    width = 1,     emif_mem_0.mem_ck_t
		.emif_mem_0_mem_ck_c     (emif_mem_0_mem_ck_c),     //  output,    width = 1,               .mem_ck_c
		.emif_mem_0_mem_cke      (emif_mem_0_mem_cke),      //  output,    width = 1,               .mem_cke
		.emif_mem_0_mem_odt      (emif_mem_0_mem_odt),      //  output,    width = 1,               .mem_odt
		.emif_mem_0_mem_cs_n     (emif_mem_0_mem_cs_n),     //  output,    width = 1,               .mem_cs_n
		.emif_mem_0_mem_a        (emif_mem_0_mem_a),        //  output,   width = 17,               .mem_a
		.emif_mem_0_mem_ba       (emif_mem_0_mem_ba),       //  output,    width = 2,               .mem_ba
		.emif_mem_0_mem_bg       (emif_mem_0_mem_bg),       //  output,    width = 1,               .mem_bg
		.emif_mem_0_mem_act_n    (emif_mem_0_mem_act_n),    //  output,    width = 1,               .mem_act_n
		.emif_mem_0_mem_par      (emif_mem_0_mem_par),      //  output,    width = 1,               .mem_par
		.emif_mem_0_mem_alert_n  (emif_mem_0_mem_alert_n),  //   input,    width = 1,               .mem_alert_n
		.emif_mem_0_mem_reset_n  (emif_mem_0_mem_reset_n),  //  output,    width = 1,               .mem_reset_n
		.emif_mem_0_mem_dq       (emif_mem_0_mem_dq),       //   inout,   width = 32,               .mem_dq
		.emif_mem_0_mem_dqs_t    (emif_mem_0_mem_dqs_t),    //   inout,    width = 4,               .mem_dqs_t
		.emif_mem_0_mem_dqs_c    (emif_mem_0_mem_dqs_c),    //   inout,    width = 4,               .mem_dqs_c
		.emif_mem_0_mem_dbi_n    (emif_mem_0_mem_dbi_n),    //   inout,    width = 4,               .mem_dbi_n
		.emif_oct_0_oct_rzqin    (emif_oct_0_oct_rzqin),    //   input,    width = 1,     emif_oct_0.oct_rzqin
		.s0_noc_axi4lite_clk     (s0_noc_axi4lite_clk),     //  output,    width = 1,    s0_axil_clk.clk
		.s0_noc_axi4lite_rst_n   (s0_noc_axi4lite_rst_n),   //  output,    width = 1,  s0_axil_rst_n.reset_n
		.s0_noc_axi4lite_awaddr  (s0_noc_axi4lite_awaddr),  //   input,   width = 27,        s0_axil.awaddr
		.s0_noc_axi4lite_awvalid (s0_noc_axi4lite_awvalid), //   input,    width = 1,               .awvalid
		.s0_noc_axi4lite_awready (s0_noc_axi4lite_awready), //  output,    width = 1,               .awready
		.s0_noc_axi4lite_wdata   (s0_noc_axi4lite_wdata),   //   input,   width = 32,               .wdata
		.s0_noc_axi4lite_wstrb   (s0_noc_axi4lite_wstrb),   //   input,    width = 4,               .wstrb
		.s0_noc_axi4lite_wvalid  (s0_noc_axi4lite_wvalid),  //   input,    width = 1,               .wvalid
		.s0_noc_axi4lite_wready  (s0_noc_axi4lite_wready),  //  output,    width = 1,               .wready
		.s0_noc_axi4lite_bresp   (s0_noc_axi4lite_bresp),   //  output,    width = 2,               .bresp
		.s0_noc_axi4lite_bvalid  (s0_noc_axi4lite_bvalid),  //  output,    width = 1,               .bvalid
		.s0_noc_axi4lite_bready  (s0_noc_axi4lite_bready),  //   input,    width = 1,               .bready
		.s0_noc_axi4lite_araddr  (s0_noc_axi4lite_araddr),  //   input,   width = 27,               .araddr
		.s0_noc_axi4lite_arvalid (s0_noc_axi4lite_arvalid), //   input,    width = 1,               .arvalid
		.s0_noc_axi4lite_arready (s0_noc_axi4lite_arready), //  output,    width = 1,               .arready
		.s0_noc_axi4lite_rdata   (s0_noc_axi4lite_rdata),   //  output,   width = 32,               .rdata
		.s0_noc_axi4lite_rresp   (s0_noc_axi4lite_rresp),   //  output,    width = 2,               .rresp
		.s0_noc_axi4lite_rvalid  (s0_noc_axi4lite_rvalid),  //  output,    width = 1,               .rvalid
		.s0_noc_axi4lite_rready  (s0_noc_axi4lite_rready),  //   input,    width = 1,               .rready
		.s0_noc_axi4lite_awprot  (s0_noc_axi4lite_awprot),  //   input,    width = 3,               .awprot
		.s0_noc_axi4lite_arprot  (s0_noc_axi4lite_arprot),  //   input,    width = 3,               .arprot
		.out_reset_0_n           (out_reset_0_n),           //  output,    width = 1,    usr_rst_n_0.reset_n
		.emif_ref_clk_0_clk      (emif_ref_clk_0_clk)       //   input,    width = 1, emif_ref_clk_0.clk
	);

endmodule
