module system_intel_onchip_memory_0 (
		input  wire        clk,        //   clk1.clk
		input  wire [16:0] address,    //     s1.address
		input  wire        read,       //       .read
		output wire [31:0] readdata,   //       .readdata
		input  wire [3:0]  byteenable, //       .byteenable
		input  wire        write,      //       .write
		input  wire [31:0] writedata,  //       .writedata
		input  wire        reset,      // reset1.reset
		input  wire        reset_req   //       .reset_req
	);
endmodule

