golden top Board Configuration

golden top Board Configuration

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Pin Assignments:

CLOCK
Name Location Direction IO Standard
CLOCK1_50 A8 input 3.3-V LVCMOS
CLOCK2_50 AH9 input 3.3-V LVCMOS
CLOCK3_50 R2 input 3.3-V LVCMOS
CLOCK_50 K43 input 1.2-V

KEY
Name Location Direction IO Standard
KEY[0] E2 input 3.3-V LVCMOS
KEY[1] K3 input 3.3-V LVCMOS

FPGA
Name Location Direction IO Standard
FPGA_UART_TX T6 input 3.3-V LVCMOS
FPGA_UART_RX L1 output 3.3-V LVCMOS

SW
Name Location Direction IO Standard
SW[0] A19 input 1.2-V
SW[1] B24 input 1.2-V

LED
Name Location Direction IO Standard
LED[0] AG2 output 3.3-V LVCMOS
LED[1] AM6 output 3.3-V LVCMOS
LED[2] AF1 output 3.3-V LVCMOS
LED[3] AF2 output 3.3-V LVCMOS

SDRAM
Name Location Direction IO Standard
DRAM_CLK BK32 output 1.8-V LVCMOS
DRAM_CKE BK40 output 1.8-V LVCMOS
DRAM_ADDR[0] BN26 output 1.8-V LVCMOS
DRAM_ADDR[1] BH27 output 1.8-V LVCMOS
DRAM_ADDR[2] BM26 output 1.8-V LVCMOS
DRAM_ADDR[3] BH21 output 1.8-V LVCMOS
DRAM_ADDR[4] BH26 output 1.8-V LVCMOS
DRAM_ADDR[5] BH18 output 1.8-V LVCMOS
DRAM_ADDR[6] BK18 output 1.8-V LVCMOS
DRAM_ADDR[7] BH32 output 1.8-V LVCMOS
DRAM_ADDR[8] BM24 output 1.8-V LVCMOS
DRAM_ADDR[9] BH35 output 1.8-V LVCMOS
DRAM_ADDR[10] BN27 output 1.8-V LVCMOS
DRAM_ADDR[11] BN29 output 1.8-V LVCMOS
DRAM_ADDR[12] BK26 output 1.8-V LVCMOS
DRAM_BA[0] BH43 output 1.8-V LVCMOS
DRAM_BA[1] BM29 output 1.8-V LVCMOS
DRAM_DQ[0] BM50 inout 1.8-V LVCMOS
DRAM_DQ[1] BM51 inout 1.8-V LVCMOS
DRAM_DQ[2] BN47 inout 1.8-V LVCMOS
DRAM_DQ[3] BM47 inout 1.8-V LVCMOS
DRAM_DQ[4] BL51 inout 1.8-V LVCMOS
DRAM_DQ[5] BH50 inout 1.8-V LVCMOS
DRAM_DQ[6] BK50 inout 1.8-V LVCMOS
DRAM_DQ[7] BH46 inout 1.8-V LVCMOS
DRAM_DQ[8] BM37 inout 1.8-V LVCMOS
DRAM_DQ[9] BN37 inout 1.8-V LVCMOS
DRAM_DQ[10] BM42 inout 1.8-V LVCMOS
DRAM_DQ[11] BN42 inout 1.8-V LVCMOS
DRAM_DQ[12] BM44 inout 1.8-V LVCMOS
DRAM_DQ[13] BN45 inout 1.8-V LVCMOS
DRAM_DQ[14] BN39 inout 1.8-V LVCMOS
DRAM_DQ[15] BM45 inout 1.8-V LVCMOS
DRAM_DQ[16] BG2 inout 1.8-V LVCMOS
DRAM_DQ[17] BA2 inout 1.8-V LVCMOS
DRAM_DQ[18] BC2 inout 1.8-V LVCMOS
DRAM_DQ[19] BJ1 inout 1.8-V LVCMOS
DRAM_DQ[20] BE4 inout 1.8-V LVCMOS
DRAM_DQ[21] BG1 inout 1.8-V LVCMOS
DRAM_DQ[22] BC1 inout 1.8-V LVCMOS
DRAM_DQ[23] BD1 inout 1.8-V LVCMOS
DRAM_DQ[24] BN5 inout 1.8-V LVCMOS
DRAM_DQ[25] BM9 inout 1.8-V LVCMOS
DRAM_DQ[26] BM8 inout 1.8-V LVCMOS
DRAM_DQ[27] BN11 inout 1.8-V LVCMOS
DRAM_DQ[28] BN8 inout 1.8-V LVCMOS
DRAM_DQ[29] BN14 inout 1.8-V LVCMOS
DRAM_DQ[30] BM11 inout 1.8-V LVCMOS
DRAM_DQ[31] BN16 inout 1.8-V LVCMOS
DRAM_CS_n BN34 output 1.8-V LVCMOS
DRAM_WE_n BM34 output 1.8-V LVCMOS
DRAM_CAS_n BH40 output 1.8-V LVCMOS
DRAM_RAS_n BM31 output 1.8-V LVCMOS
DRAM_DQM[0] BE6 output 1.8-V LVCMOS
DRAM_DQM[1] BM19 output 1.8-V LVCMOS
DRAM_DQM[2] BJ2 output 1.8-V LVCMOS
DRAM_DQM[3] BM14 output 1.8-V LVCMOS

SD
Name Location Direction IO Standard
SD_CLK Y1 output 3.3-V LVCMOS
SD_DATA[0] AC2 inout 3.3-V LVCMOS
SD_DATA[1] AC1 inout 3.3-V LVCMOS
SD_DATA[2] V2 inout 3.3-V LVCMOS
SD_DATA[3] V1 inout 3.3-V LVCMOS
SD_CMD N1 inout 3.3-V LVCMOS

HDMI
Name Location Direction IO Standard
HDMI_I2C_SCL M2 inout 3.3-V LVCMOS
HDMI_I2C_SDA N2 inout 3.3-V LVCMOS
HDMI_TX_HS R52 output 1.2-V
HDMI_TX_VS N52 output 1.2-V
HDMI_TX_D[0] G52 output 1.2-V
HDMI_TX_D[1] J52 output 1.2-V
HDMI_TX_D[2] G51 output 1.2-V
HDMI_TX_D[3] J51 output 1.2-V
HDMI_TX_D[4] M51 output 1.2-V
HDMI_TX_D[5] H43 output 1.2-V
HDMI_TX_D[6] A34 output 1.2-V
HDMI_TX_D[7] A29 output 1.2-V
HDMI_TX_D[8] B29 output 1.2-V
HDMI_TX_D[9] B27 output 1.2-V
HDMI_TX_D[10] A26 output 1.2-V
HDMI_TX_D[11] B26 output 1.2-V
HDMI_TX_D[12] A31 output 1.2-V
HDMI_TX_D[13] H35 output 1.2-V
HDMI_TX_D[14] A37 output 1.2-V
HDMI_TX_D[15] F35 output 1.2-V
HDMI_TX_D[16] F40 output 1.2-V
HDMI_TX_D[17] F32 output 1.2-V
HDMI_TX_D[18] V52 output 1.2-V
HDMI_TX_D[19] K35 output 1.2-V
HDMI_TX_D[20] V51 output 1.2-V
HDMI_TX_D[21] K32 output 1.2-V
HDMI_TX_D[22] K40 output 1.2-V
HDMI_TX_D[23] A24 output 1.2-V
HDMI_TX_DE R51 output 1.2-V
HDMI_TX_CLK_p L51 output DIFFERENTIAL 1.2-V SSTL
HDMI_ISEL J2 output 3.3-V LVCMOS
HDMI_PD_n J1 output 3.3-V LVCMOS
DDC_I2C_SCL AV2 inout 3.3-V LVCMOS
DDC_I2C_SDA AN1 inout 3.3-V LVCMOS

NET
Name Location Direction IO Standard
NET_TX_CLK AY6 output 1.8-V LVCMOS
NET_TX_DATA[0] BH10 output 1.8-V LVCMOS
NET_TX_DATA[1] BK10 output 1.8-V LVCMOS
NET_TX_DATA[2] BM2 output 1.8-V LVCMOS
NET_TX_DATA[3] BM3 output 1.8-V LVCMOS
NET_TX_CTRL AU6 output 1.8-V LVCMOS
NET_RX_CLK AT9 input 1.8-V LVCMOS
NET_RX_DATA[0] BF12 input 1.8-V LVCMOS
NET_RX_DATA[1] BF9 input 1.8-V LVCMOS
NET_RX_DATA[2] BB12 input 1.8-V LVCMOS
NET_RX_DATA[3] BH3 input 1.8-V LVCMOS
NET_RX_CTRL AU4 input 1.8-V LVCMOS
NET_MDC BB9 output 1.8-V LVCMOS
NET_MDIO BH7 inout 1.8-V LVCMOS
NET_RESET_n AW12 output 1.8-V LVCMOS

CAM
Name Location Direction IO Standard
CAM_CLK_p B45 input DPHY
CAM_CLK_n A45 input DPHY
CAM_D_p[0] B47 input DPHY
CAM_D_p[1] B50 input DPHY
CAM_D_p[2] B42 input DPHY
CAM_D_p[3] B39 input DPHY
CAM_D_n[0] A47 input DPHY
CAM_D_n[1] B51 input DPHY
CAM_D_n[2] A44 input DPHY
CAM_D_n[3] A42 input DPHY
CAM_I2C_SCL K27 inout 3.3-V LVCMOS
CAM_I2C_SDA K26 inout 3.3-V LVCMOS
CAM_GPIO AL9 inout 3.3-V LVCMOS
CAM_RZQ1 F43 input 1.2-V

GPIO
Name Location Direction IO Standard
GPIO[0] B3 inout 3.3-V LVCMOS
GPIO[1] A11 inout 3.3-V LVCMOS
GPIO[2] D18 inout 3.3-V LVCMOS
GPIO[3] B11 inout 3.3-V LVCMOS
GPIO[4] H7 inout 3.3-V LVCMOS
GPIO[5] B5 inout 3.3-V LVCMOS
GPIO[6] W9 inout 3.3-V LVCMOS
GPIO[7] F3 inout 3.3-V LVCMOS
GPIO[8] U9 inout 3.3-V LVCMOS
GPIO[9] C2 inout 3.3-V LVCMOS
GPIO[10] U12 inout 3.3-V LVCMOS
GPIO[11] F7 inout 3.3-V LVCMOS
GPIO[12] P9 inout 3.3-V LVCMOS
GPIO[13] K7 inout 3.3-V LVCMOS
GPIO[14] K10 inout 3.3-V LVCMOS
GPIO[15] K13 inout 3.3-V LVCMOS
GPIO[16] D3 inout 3.3-V LVCMOS
GPIO[17] H13 inout 3.3-V LVCMOS
GPIO[18] B8 inout 3.3-V LVCMOS
GPIO[19] F10 inout 3.3-V LVCMOS
GPIO[20] A9 inout 3.3-V LVCMOS
GPIO[21] D10 inout 3.3-V LVCMOS
GPIO[22] F13 inout 3.3-V LVCMOS
GPIO[23] K18 inout 3.3-V LVCMOS
GPIO[24] F18 inout 3.3-V LVCMOS
GPIO[25] H21 inout 3.3-V LVCMOS
GPIO[26] D26 inout 3.3-V LVCMOS
GPIO[27] K21 inout 3.3-V LVCMOS
GPIO[28] H27 inout 3.3-V LVCMOS
GPIO[29] F26 inout 3.3-V LVCMOS
GPIO[30] B14 inout 3.3-V LVCMOS
GPIO[31] F27 inout 3.3-V LVCMOS
GPIO[32] B16 inout 3.3-V LVCMOS
GPIO[33] A14 inout 3.3-V LVCMOS
GPIO[34] F21 inout 3.3-V LVCMOS
GPIO[35] B19 inout 3.3-V LVCMOS

TMD0
Name Location Direction IO Standard
TMD0_D[0] AD6 inout 3.3-V LVCMOS
TMD0_D[1] P6 inout 3.3-V LVCMOS
TMD0_D[2] AB9 inout 3.3-V LVCMOS
TMD0_D[3] AE12 inout 3.3-V LVCMOS
TMD0_D[4] P4 inout 3.3-V LVCMOS
TMD0_D[5] AA4 inout 3.3-V LVCMOS
TMD0_D[6] AH12 inout 3.3-V LVCMOS
TMD0_D[7] AA6 inout 3.3-V LVCMOS

TMD1
Name Location Direction IO Standard
TMD1_D[0] AR2 inout 3.3-V LVCMOS
TMD1_D[1] AJ6 inout 3.3-V LVCMOS
TMD1_D[2] AK1 inout 3.3-V LVCMOS
TMD1_D[3] AR1 inout 3.3-V LVCMOS
TMD1_D[4] AL12 inout 3.3-V LVCMOS
TMD1_D[5] AJ4 inout 3.3-V LVCMOS
TMD1_D[6] AV1 inout 3.3-V LVCMOS
TMD1_D[7] AK2 inout 3.3-V LVCMOS